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1// SPDX-License-Identifier: GPL-2.0-only
2/* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22#include <linux/can/core.h>
23#include <linux/can/dev.h>
24#include <linux/can/led.h>
25#include <linux/clk.h>
26#include <linux/completion.h>
27#include <linux/delay.h>
28#include <linux/device.h>
29#include <linux/freezer.h>
30#include <linux/interrupt.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/netdevice.h>
35#include <linux/property.h>
36#include <linux/platform_device.h>
37#include <linux/slab.h>
38#include <linux/spi/spi.h>
39#include <linux/uaccess.h>
40#include <linux/regulator/consumer.h>
41
42/* SPI interface instruction set */
43#define INSTRUCTION_WRITE 0x02
44#define INSTRUCTION_READ 0x03
45#define INSTRUCTION_BIT_MODIFY 0x05
46#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
47#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
48#define INSTRUCTION_RESET 0xC0
49#define RTS_TXB0 0x01
50#define RTS_TXB1 0x02
51#define RTS_TXB2 0x04
52#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
53
54/* MPC251x registers */
55#define CANSTAT 0x0e
56#define CANCTRL 0x0f
57# define CANCTRL_REQOP_MASK 0xe0
58# define CANCTRL_REQOP_CONF 0x80
59# define CANCTRL_REQOP_LISTEN_ONLY 0x60
60# define CANCTRL_REQOP_LOOPBACK 0x40
61# define CANCTRL_REQOP_SLEEP 0x20
62# define CANCTRL_REQOP_NORMAL 0x00
63# define CANCTRL_OSM 0x08
64# define CANCTRL_ABAT 0x10
65#define TEC 0x1c
66#define REC 0x1d
67#define CNF1 0x2a
68# define CNF1_SJW_SHIFT 6
69#define CNF2 0x29
70# define CNF2_BTLMODE 0x80
71# define CNF2_SAM 0x40
72# define CNF2_PS1_SHIFT 3
73#define CNF3 0x28
74# define CNF3_SOF 0x08
75# define CNF3_WAKFIL 0x04
76# define CNF3_PHSEG2_MASK 0x07
77#define CANINTE 0x2b
78# define CANINTE_MERRE 0x80
79# define CANINTE_WAKIE 0x40
80# define CANINTE_ERRIE 0x20
81# define CANINTE_TX2IE 0x10
82# define CANINTE_TX1IE 0x08
83# define CANINTE_TX0IE 0x04
84# define CANINTE_RX1IE 0x02
85# define CANINTE_RX0IE 0x01
86#define CANINTF 0x2c
87# define CANINTF_MERRF 0x80
88# define CANINTF_WAKIF 0x40
89# define CANINTF_ERRIF 0x20
90# define CANINTF_TX2IF 0x10
91# define CANINTF_TX1IF 0x08
92# define CANINTF_TX0IF 0x04
93# define CANINTF_RX1IF 0x02
94# define CANINTF_RX0IF 0x01
95# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
96# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
97# define CANINTF_ERR (CANINTF_ERRIF)
98#define EFLG 0x2d
99# define EFLG_EWARN 0x01
100# define EFLG_RXWAR 0x02
101# define EFLG_TXWAR 0x04
102# define EFLG_RXEP 0x08
103# define EFLG_TXEP 0x10
104# define EFLG_TXBO 0x20
105# define EFLG_RX0OVR 0x40
106# define EFLG_RX1OVR 0x80
107#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
108# define TXBCTRL_ABTF 0x40
109# define TXBCTRL_MLOA 0x20
110# define TXBCTRL_TXERR 0x10
111# define TXBCTRL_TXREQ 0x08
112#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
113# define SIDH_SHIFT 3
114#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
115# define SIDL_SID_MASK 7
116# define SIDL_SID_SHIFT 5
117# define SIDL_EXIDE_SHIFT 3
118# define SIDL_EID_SHIFT 16
119# define SIDL_EID_MASK 3
120#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
121#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
122#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
123# define DLC_RTR_SHIFT 6
124#define TXBCTRL_OFF 0
125#define TXBSIDH_OFF 1
126#define TXBSIDL_OFF 2
127#define TXBEID8_OFF 3
128#define TXBEID0_OFF 4
129#define TXBDLC_OFF 5
130#define TXBDAT_OFF 6
131#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
132# define RXBCTRL_BUKT 0x04
133# define RXBCTRL_RXM0 0x20
134# define RXBCTRL_RXM1 0x40
135#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
136# define RXBSIDH_SHIFT 3
137#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
138# define RXBSIDL_IDE 0x08
139# define RXBSIDL_SRR 0x10
140# define RXBSIDL_EID 3
141# define RXBSIDL_SHIFT 5
142#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
143#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
144#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
145# define RXBDLC_LEN_MASK 0x0f
146# define RXBDLC_RTR 0x40
147#define RXBCTRL_OFF 0
148#define RXBSIDH_OFF 1
149#define RXBSIDL_OFF 2
150#define RXBEID8_OFF 3
151#define RXBEID0_OFF 4
152#define RXBDLC_OFF 5
153#define RXBDAT_OFF 6
154#define RXFSID(n) ((n < 3) ? 0 : 4)
155#define RXFSIDH(n) ((n) * 4 + RXFSID(n))
156#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
157#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
158#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
159#define RXMSIDH(n) ((n) * 4 + 0x20)
160#define RXMSIDL(n) ((n) * 4 + 0x21)
161#define RXMEID8(n) ((n) * 4 + 0x22)
162#define RXMEID0(n) ((n) * 4 + 0x23)
163
164#define GET_BYTE(val, byte) \
165 (((val) >> ((byte) * 8)) & 0xff)
166#define SET_BYTE(val, byte) \
167 (((val) & 0xff) << ((byte) * 8))
168
169/* Buffer size required for the largest SPI transfer (i.e., reading a
170 * frame)
171 */
172#define CAN_FRAME_MAX_DATA_LEN 8
173#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
174#define CAN_FRAME_MAX_BITS 128
175
176#define TX_ECHO_SKB_MAX 1
177
178#define MCP251X_OST_DELAY_MS (5)
179
180#define DEVICE_NAME "mcp251x"
181
182static const struct can_bittiming_const mcp251x_bittiming_const = {
183 .name = DEVICE_NAME,
184 .tseg1_min = 3,
185 .tseg1_max = 16,
186 .tseg2_min = 2,
187 .tseg2_max = 8,
188 .sjw_max = 4,
189 .brp_min = 1,
190 .brp_max = 64,
191 .brp_inc = 1,
192};
193
194enum mcp251x_model {
195 CAN_MCP251X_MCP2510 = 0x2510,
196 CAN_MCP251X_MCP2515 = 0x2515,
197 CAN_MCP251X_MCP25625 = 0x25625,
198};
199
200struct mcp251x_priv {
201 struct can_priv can;
202 struct net_device *net;
203 struct spi_device *spi;
204 enum mcp251x_model model;
205
206 struct mutex mcp_lock; /* SPI device lock */
207
208 u8 *spi_tx_buf;
209 u8 *spi_rx_buf;
210
211 struct sk_buff *tx_skb;
212 int tx_len;
213
214 struct workqueue_struct *wq;
215 struct work_struct tx_work;
216 struct work_struct restart_work;
217
218 int force_quit;
219 int after_suspend;
220#define AFTER_SUSPEND_UP 1
221#define AFTER_SUSPEND_DOWN 2
222#define AFTER_SUSPEND_POWER 4
223#define AFTER_SUSPEND_RESTART 8
224 int restart_tx;
225 struct regulator *power;
226 struct regulator *transceiver;
227 struct clk *clk;
228};
229
230#define MCP251X_IS(_model) \
231static inline int mcp251x_is_##_model(struct spi_device *spi) \
232{ \
233 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
234 return priv->model == CAN_MCP251X_MCP##_model; \
235}
236
237MCP251X_IS(2510);
238
239static void mcp251x_clean(struct net_device *net)
240{
241 struct mcp251x_priv *priv = netdev_priv(net);
242
243 if (priv->tx_skb || priv->tx_len)
244 net->stats.tx_errors++;
245 dev_kfree_skb(priv->tx_skb);
246 if (priv->tx_len)
247 can_free_echo_skb(priv->net, 0);
248 priv->tx_skb = NULL;
249 priv->tx_len = 0;
250}
251
252/* Note about handling of error return of mcp251x_spi_trans: accessing
253 * registers via SPI is not really different conceptually than using
254 * normal I/O assembler instructions, although it's much more
255 * complicated from a practical POV. So it's not advisable to always
256 * check the return value of this function. Imagine that every
257 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
258 * error();", it would be a great mess (well there are some situation
259 * when exception handling C++ like could be useful after all). So we
260 * just check that transfers are OK at the beginning of our
261 * conversation with the chip and to avoid doing really nasty things
262 * (like injecting bogus packets in the network stack).
263 */
264static int mcp251x_spi_trans(struct spi_device *spi, int len)
265{
266 struct mcp251x_priv *priv = spi_get_drvdata(spi);
267 struct spi_transfer t = {
268 .tx_buf = priv->spi_tx_buf,
269 .rx_buf = priv->spi_rx_buf,
270 .len = len,
271 .cs_change = 0,
272 };
273 struct spi_message m;
274 int ret;
275
276 spi_message_init(&m);
277 spi_message_add_tail(&t, &m);
278
279 ret = spi_sync(spi, &m);
280 if (ret)
281 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
282 return ret;
283}
284
285static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
286{
287 struct mcp251x_priv *priv = spi_get_drvdata(spi);
288 u8 val = 0;
289
290 priv->spi_tx_buf[0] = INSTRUCTION_READ;
291 priv->spi_tx_buf[1] = reg;
292
293 mcp251x_spi_trans(spi, 3);
294 val = priv->spi_rx_buf[2];
295
296 return val;
297}
298
299static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
300{
301 struct mcp251x_priv *priv = spi_get_drvdata(spi);
302
303 priv->spi_tx_buf[0] = INSTRUCTION_READ;
304 priv->spi_tx_buf[1] = reg;
305
306 mcp251x_spi_trans(spi, 4);
307
308 *v1 = priv->spi_rx_buf[2];
309 *v2 = priv->spi_rx_buf[3];
310}
311
312static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
313{
314 struct mcp251x_priv *priv = spi_get_drvdata(spi);
315
316 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
317 priv->spi_tx_buf[1] = reg;
318 priv->spi_tx_buf[2] = val;
319
320 mcp251x_spi_trans(spi, 3);
321}
322
323static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
324{
325 struct mcp251x_priv *priv = spi_get_drvdata(spi);
326
327 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
328 priv->spi_tx_buf[1] = reg;
329 priv->spi_tx_buf[2] = v1;
330 priv->spi_tx_buf[3] = v2;
331
332 mcp251x_spi_trans(spi, 4);
333}
334
335static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
336 u8 mask, u8 val)
337{
338 struct mcp251x_priv *priv = spi_get_drvdata(spi);
339
340 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
341 priv->spi_tx_buf[1] = reg;
342 priv->spi_tx_buf[2] = mask;
343 priv->spi_tx_buf[3] = val;
344
345 mcp251x_spi_trans(spi, 4);
346}
347
348static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
349 int len, int tx_buf_idx)
350{
351 struct mcp251x_priv *priv = spi_get_drvdata(spi);
352
353 if (mcp251x_is_2510(spi)) {
354 int i;
355
356 for (i = 1; i < TXBDAT_OFF + len; i++)
357 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
358 buf[i]);
359 } else {
360 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
361 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
362 }
363}
364
365static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
366 int tx_buf_idx)
367{
368 struct mcp251x_priv *priv = spi_get_drvdata(spi);
369 u32 sid, eid, exide, rtr;
370 u8 buf[SPI_TRANSFER_BUF_LEN];
371
372 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
373 if (exide)
374 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
375 else
376 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
377 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
378 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
379
380 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
381 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
382 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
383 (exide << SIDL_EXIDE_SHIFT) |
384 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
385 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
386 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
387 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
388 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
389 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
390
391 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
392 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
393 mcp251x_spi_trans(priv->spi, 1);
394}
395
396static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
397 int buf_idx)
398{
399 struct mcp251x_priv *priv = spi_get_drvdata(spi);
400
401 if (mcp251x_is_2510(spi)) {
402 int i, len;
403
404 for (i = 1; i < RXBDAT_OFF; i++)
405 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
406
407 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
408 for (; i < (RXBDAT_OFF + len); i++)
409 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
410 } else {
411 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
412 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
413 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
414 }
415}
416
417static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
418{
419 struct mcp251x_priv *priv = spi_get_drvdata(spi);
420 struct sk_buff *skb;
421 struct can_frame *frame;
422 u8 buf[SPI_TRANSFER_BUF_LEN];
423
424 skb = alloc_can_skb(priv->net, &frame);
425 if (!skb) {
426 dev_err(&spi->dev, "cannot allocate RX skb\n");
427 priv->net->stats.rx_dropped++;
428 return;
429 }
430
431 mcp251x_hw_rx_frame(spi, buf, buf_idx);
432 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
433 /* Extended ID format */
434 frame->can_id = CAN_EFF_FLAG;
435 frame->can_id |=
436 /* Extended ID part */
437 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
438 SET_BYTE(buf[RXBEID8_OFF], 1) |
439 SET_BYTE(buf[RXBEID0_OFF], 0) |
440 /* Standard ID part */
441 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
442 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
443 /* Remote transmission request */
444 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
445 frame->can_id |= CAN_RTR_FLAG;
446 } else {
447 /* Standard ID format */
448 frame->can_id =
449 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
450 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
451 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
452 frame->can_id |= CAN_RTR_FLAG;
453 }
454 /* Data length */
455 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
456 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
457
458 priv->net->stats.rx_packets++;
459 priv->net->stats.rx_bytes += frame->can_dlc;
460
461 can_led_event(priv->net, CAN_LED_EVENT_RX);
462
463 netif_rx_ni(skb);
464}
465
466static void mcp251x_hw_sleep(struct spi_device *spi)
467{
468 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
469}
470
471/* May only be called when device is sleeping! */
472static int mcp251x_hw_wake(struct spi_device *spi)
473{
474 unsigned long timeout;
475
476 /* Force wakeup interrupt to wake device, but don't execute IST */
477 disable_irq(spi->irq);
478 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
479
480 /* Wait for oscillator startup timer after wake up */
481 mdelay(MCP251X_OST_DELAY_MS);
482
483 /* Put device into config mode */
484 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
485
486 /* Wait for the device to enter config mode */
487 timeout = jiffies + HZ;
488 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
489 CANCTRL_REQOP_CONF) {
490 schedule();
491 if (time_after(jiffies, timeout)) {
492 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
493 return -EBUSY;
494 }
495 }
496
497 /* Disable and clear pending interrupts */
498 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
499 enable_irq(spi->irq);
500
501 return 0;
502}
503
504static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
505 struct net_device *net)
506{
507 struct mcp251x_priv *priv = netdev_priv(net);
508 struct spi_device *spi = priv->spi;
509
510 if (priv->tx_skb || priv->tx_len) {
511 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
512 return NETDEV_TX_BUSY;
513 }
514
515 if (can_dropped_invalid_skb(net, skb))
516 return NETDEV_TX_OK;
517
518 netif_stop_queue(net);
519 priv->tx_skb = skb;
520 queue_work(priv->wq, &priv->tx_work);
521
522 return NETDEV_TX_OK;
523}
524
525static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
526{
527 struct mcp251x_priv *priv = netdev_priv(net);
528
529 switch (mode) {
530 case CAN_MODE_START:
531 mcp251x_clean(net);
532 /* We have to delay work since SPI I/O may sleep */
533 priv->can.state = CAN_STATE_ERROR_ACTIVE;
534 priv->restart_tx = 1;
535 if (priv->can.restart_ms == 0)
536 priv->after_suspend = AFTER_SUSPEND_RESTART;
537 queue_work(priv->wq, &priv->restart_work);
538 break;
539 default:
540 return -EOPNOTSUPP;
541 }
542
543 return 0;
544}
545
546static int mcp251x_set_normal_mode(struct spi_device *spi)
547{
548 struct mcp251x_priv *priv = spi_get_drvdata(spi);
549 unsigned long timeout;
550
551 /* Enable interrupts */
552 mcp251x_write_reg(spi, CANINTE,
553 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
554 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
555
556 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
557 /* Put device into loopback mode */
558 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
559 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
560 /* Put device into listen-only mode */
561 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
562 } else {
563 /* Put device into normal mode */
564 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
565
566 /* Wait for the device to enter normal mode */
567 timeout = jiffies + HZ;
568 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
569 schedule();
570 if (time_after(jiffies, timeout)) {
571 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
572 return -EBUSY;
573 }
574 }
575 }
576 priv->can.state = CAN_STATE_ERROR_ACTIVE;
577 return 0;
578}
579
580static int mcp251x_do_set_bittiming(struct net_device *net)
581{
582 struct mcp251x_priv *priv = netdev_priv(net);
583 struct can_bittiming *bt = &priv->can.bittiming;
584 struct spi_device *spi = priv->spi;
585
586 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
587 (bt->brp - 1));
588 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
589 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
590 CNF2_SAM : 0) |
591 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
592 (bt->prop_seg - 1));
593 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
594 (bt->phase_seg2 - 1));
595 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
596 mcp251x_read_reg(spi, CNF1),
597 mcp251x_read_reg(spi, CNF2),
598 mcp251x_read_reg(spi, CNF3));
599
600 return 0;
601}
602
603static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
604{
605 mcp251x_do_set_bittiming(net);
606
607 mcp251x_write_reg(spi, RXBCTRL(0),
608 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
609 mcp251x_write_reg(spi, RXBCTRL(1),
610 RXBCTRL_RXM0 | RXBCTRL_RXM1);
611 return 0;
612}
613
614static int mcp251x_hw_reset(struct spi_device *spi)
615{
616 struct mcp251x_priv *priv = spi_get_drvdata(spi);
617 unsigned long timeout;
618 int ret;
619
620 /* Wait for oscillator startup timer after power up */
621 mdelay(MCP251X_OST_DELAY_MS);
622
623 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
624 ret = mcp251x_spi_trans(spi, 1);
625 if (ret)
626 return ret;
627
628 /* Wait for oscillator startup timer after reset */
629 mdelay(MCP251X_OST_DELAY_MS);
630
631 /* Wait for reset to finish */
632 timeout = jiffies + HZ;
633 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
634 CANCTRL_REQOP_CONF) {
635 usleep_range(MCP251X_OST_DELAY_MS * 1000,
636 MCP251X_OST_DELAY_MS * 1000 * 2);
637
638 if (time_after(jiffies, timeout)) {
639 dev_err(&spi->dev,
640 "MCP251x didn't enter in conf mode after reset\n");
641 return -EBUSY;
642 }
643 }
644 return 0;
645}
646
647static int mcp251x_hw_probe(struct spi_device *spi)
648{
649 u8 ctrl;
650 int ret;
651
652 ret = mcp251x_hw_reset(spi);
653 if (ret)
654 return ret;
655
656 ctrl = mcp251x_read_reg(spi, CANCTRL);
657
658 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
659
660 /* Check for power up default value */
661 if ((ctrl & 0x17) != 0x07)
662 return -ENODEV;
663
664 return 0;
665}
666
667static int mcp251x_power_enable(struct regulator *reg, int enable)
668{
669 if (IS_ERR_OR_NULL(reg))
670 return 0;
671
672 if (enable)
673 return regulator_enable(reg);
674 else
675 return regulator_disable(reg);
676}
677
678static int mcp251x_stop(struct net_device *net)
679{
680 struct mcp251x_priv *priv = netdev_priv(net);
681 struct spi_device *spi = priv->spi;
682
683 close_candev(net);
684
685 priv->force_quit = 1;
686 free_irq(spi->irq, priv);
687 destroy_workqueue(priv->wq);
688 priv->wq = NULL;
689
690 mutex_lock(&priv->mcp_lock);
691
692 /* Disable and clear pending interrupts */
693 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
694
695 mcp251x_write_reg(spi, TXBCTRL(0), 0);
696 mcp251x_clean(net);
697
698 mcp251x_hw_sleep(spi);
699
700 mcp251x_power_enable(priv->transceiver, 0);
701
702 priv->can.state = CAN_STATE_STOPPED;
703
704 mutex_unlock(&priv->mcp_lock);
705
706 can_led_event(net, CAN_LED_EVENT_STOP);
707
708 return 0;
709}
710
711static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
712{
713 struct sk_buff *skb;
714 struct can_frame *frame;
715
716 skb = alloc_can_err_skb(net, &frame);
717 if (skb) {
718 frame->can_id |= can_id;
719 frame->data[1] = data1;
720 netif_rx_ni(skb);
721 } else {
722 netdev_err(net, "cannot allocate error skb\n");
723 }
724}
725
726static void mcp251x_tx_work_handler(struct work_struct *ws)
727{
728 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
729 tx_work);
730 struct spi_device *spi = priv->spi;
731 struct net_device *net = priv->net;
732 struct can_frame *frame;
733
734 mutex_lock(&priv->mcp_lock);
735 if (priv->tx_skb) {
736 if (priv->can.state == CAN_STATE_BUS_OFF) {
737 mcp251x_clean(net);
738 } else {
739 frame = (struct can_frame *)priv->tx_skb->data;
740
741 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
742 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
743 mcp251x_hw_tx(spi, frame, 0);
744 priv->tx_len = 1 + frame->can_dlc;
745 can_put_echo_skb(priv->tx_skb, net, 0);
746 priv->tx_skb = NULL;
747 }
748 }
749 mutex_unlock(&priv->mcp_lock);
750}
751
752static void mcp251x_restart_work_handler(struct work_struct *ws)
753{
754 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
755 restart_work);
756 struct spi_device *spi = priv->spi;
757 struct net_device *net = priv->net;
758
759 mutex_lock(&priv->mcp_lock);
760 if (priv->after_suspend) {
761 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
762 mcp251x_hw_reset(spi);
763 mcp251x_setup(net, spi);
764 } else {
765 mcp251x_hw_wake(spi);
766 }
767 priv->force_quit = 0;
768 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
769 mcp251x_set_normal_mode(spi);
770 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
771 netif_device_attach(net);
772 mcp251x_clean(net);
773 mcp251x_set_normal_mode(spi);
774 netif_wake_queue(net);
775 } else {
776 mcp251x_hw_sleep(spi);
777 }
778 priv->after_suspend = 0;
779 }
780
781 if (priv->restart_tx) {
782 priv->restart_tx = 0;
783 mcp251x_write_reg(spi, TXBCTRL(0), 0);
784 mcp251x_clean(net);
785 netif_wake_queue(net);
786 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
787 }
788 mutex_unlock(&priv->mcp_lock);
789}
790
791static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
792{
793 struct mcp251x_priv *priv = dev_id;
794 struct spi_device *spi = priv->spi;
795 struct net_device *net = priv->net;
796
797 mutex_lock(&priv->mcp_lock);
798 while (!priv->force_quit) {
799 enum can_state new_state;
800 u8 intf, eflag;
801 u8 clear_intf = 0;
802 int can_id = 0, data1 = 0;
803
804 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
805
806 /* mask out flags we don't care about */
807 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
808
809 /* receive buffer 0 */
810 if (intf & CANINTF_RX0IF) {
811 mcp251x_hw_rx(spi, 0);
812 /* Free one buffer ASAP
813 * (The MCP2515/25625 does this automatically.)
814 */
815 if (mcp251x_is_2510(spi))
816 mcp251x_write_bits(spi, CANINTF,
817 CANINTF_RX0IF, 0x00);
818 }
819
820 /* receive buffer 1 */
821 if (intf & CANINTF_RX1IF) {
822 mcp251x_hw_rx(spi, 1);
823 /* The MCP2515/25625 does this automatically. */
824 if (mcp251x_is_2510(spi))
825 clear_intf |= CANINTF_RX1IF;
826 }
827
828 /* any error or tx interrupt we need to clear? */
829 if (intf & (CANINTF_ERR | CANINTF_TX))
830 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
831 if (clear_intf)
832 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
833
834 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
835 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
836
837 /* Update can state */
838 if (eflag & EFLG_TXBO) {
839 new_state = CAN_STATE_BUS_OFF;
840 can_id |= CAN_ERR_BUSOFF;
841 } else if (eflag & EFLG_TXEP) {
842 new_state = CAN_STATE_ERROR_PASSIVE;
843 can_id |= CAN_ERR_CRTL;
844 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
845 } else if (eflag & EFLG_RXEP) {
846 new_state = CAN_STATE_ERROR_PASSIVE;
847 can_id |= CAN_ERR_CRTL;
848 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
849 } else if (eflag & EFLG_TXWAR) {
850 new_state = CAN_STATE_ERROR_WARNING;
851 can_id |= CAN_ERR_CRTL;
852 data1 |= CAN_ERR_CRTL_TX_WARNING;
853 } else if (eflag & EFLG_RXWAR) {
854 new_state = CAN_STATE_ERROR_WARNING;
855 can_id |= CAN_ERR_CRTL;
856 data1 |= CAN_ERR_CRTL_RX_WARNING;
857 } else {
858 new_state = CAN_STATE_ERROR_ACTIVE;
859 }
860
861 /* Update can state statistics */
862 switch (priv->can.state) {
863 case CAN_STATE_ERROR_ACTIVE:
864 if (new_state >= CAN_STATE_ERROR_WARNING &&
865 new_state <= CAN_STATE_BUS_OFF)
866 priv->can.can_stats.error_warning++;
867 fallthrough;
868 case CAN_STATE_ERROR_WARNING:
869 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
870 new_state <= CAN_STATE_BUS_OFF)
871 priv->can.can_stats.error_passive++;
872 break;
873 default:
874 break;
875 }
876 priv->can.state = new_state;
877
878 if (intf & CANINTF_ERRIF) {
879 /* Handle overflow counters */
880 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
881 if (eflag & EFLG_RX0OVR) {
882 net->stats.rx_over_errors++;
883 net->stats.rx_errors++;
884 }
885 if (eflag & EFLG_RX1OVR) {
886 net->stats.rx_over_errors++;
887 net->stats.rx_errors++;
888 }
889 can_id |= CAN_ERR_CRTL;
890 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
891 }
892 mcp251x_error_skb(net, can_id, data1);
893 }
894
895 if (priv->can.state == CAN_STATE_BUS_OFF) {
896 if (priv->can.restart_ms == 0) {
897 priv->force_quit = 1;
898 priv->can.can_stats.bus_off++;
899 can_bus_off(net);
900 mcp251x_hw_sleep(spi);
901 break;
902 }
903 }
904
905 if (intf == 0)
906 break;
907
908 if (intf & CANINTF_TX) {
909 net->stats.tx_packets++;
910 net->stats.tx_bytes += priv->tx_len - 1;
911 can_led_event(net, CAN_LED_EVENT_TX);
912 if (priv->tx_len) {
913 can_get_echo_skb(net, 0);
914 priv->tx_len = 0;
915 }
916 netif_wake_queue(net);
917 }
918 }
919 mutex_unlock(&priv->mcp_lock);
920 return IRQ_HANDLED;
921}
922
923static int mcp251x_open(struct net_device *net)
924{
925 struct mcp251x_priv *priv = netdev_priv(net);
926 struct spi_device *spi = priv->spi;
927 unsigned long flags = 0;
928 int ret;
929
930 ret = open_candev(net);
931 if (ret) {
932 dev_err(&spi->dev, "unable to set initial baudrate!\n");
933 return ret;
934 }
935
936 mutex_lock(&priv->mcp_lock);
937 mcp251x_power_enable(priv->transceiver, 1);
938
939 priv->force_quit = 0;
940 priv->tx_skb = NULL;
941 priv->tx_len = 0;
942
943 if (!dev_fwnode(&spi->dev))
944 flags = IRQF_TRIGGER_FALLING;
945
946 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
947 flags | IRQF_ONESHOT, dev_name(&spi->dev),
948 priv);
949 if (ret) {
950 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
951 goto out_close;
952 }
953
954 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
955 0);
956 if (!priv->wq) {
957 ret = -ENOMEM;
958 goto out_clean;
959 }
960 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
961 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
962
963 ret = mcp251x_hw_wake(spi);
964 if (ret)
965 goto out_free_wq;
966 ret = mcp251x_setup(net, spi);
967 if (ret)
968 goto out_free_wq;
969 ret = mcp251x_set_normal_mode(spi);
970 if (ret)
971 goto out_free_wq;
972
973 can_led_event(net, CAN_LED_EVENT_OPEN);
974
975 netif_wake_queue(net);
976 mutex_unlock(&priv->mcp_lock);
977
978 return 0;
979
980out_free_wq:
981 destroy_workqueue(priv->wq);
982out_clean:
983 free_irq(spi->irq, priv);
984 mcp251x_hw_sleep(spi);
985out_close:
986 mcp251x_power_enable(priv->transceiver, 0);
987 close_candev(net);
988 mutex_unlock(&priv->mcp_lock);
989 return ret;
990}
991
992static const struct net_device_ops mcp251x_netdev_ops = {
993 .ndo_open = mcp251x_open,
994 .ndo_stop = mcp251x_stop,
995 .ndo_start_xmit = mcp251x_hard_start_xmit,
996 .ndo_change_mtu = can_change_mtu,
997};
998
999static const struct of_device_id mcp251x_of_match[] = {
1000 {
1001 .compatible = "microchip,mcp2510",
1002 .data = (void *)CAN_MCP251X_MCP2510,
1003 },
1004 {
1005 .compatible = "microchip,mcp2515",
1006 .data = (void *)CAN_MCP251X_MCP2515,
1007 },
1008 {
1009 .compatible = "microchip,mcp25625",
1010 .data = (void *)CAN_MCP251X_MCP25625,
1011 },
1012 { }
1013};
1014MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1015
1016static const struct spi_device_id mcp251x_id_table[] = {
1017 {
1018 .name = "mcp2510",
1019 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1020 },
1021 {
1022 .name = "mcp2515",
1023 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1024 },
1025 {
1026 .name = "mcp25625",
1027 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1028 },
1029 { }
1030};
1031MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1032
1033static int mcp251x_can_probe(struct spi_device *spi)
1034{
1035 const void *match = device_get_match_data(&spi->dev);
1036 struct net_device *net;
1037 struct mcp251x_priv *priv;
1038 struct clk *clk;
1039 u32 freq;
1040 int ret;
1041
1042 clk = devm_clk_get_optional(&spi->dev, NULL);
1043 if (IS_ERR(clk))
1044 return PTR_ERR(clk);
1045
1046 freq = clk_get_rate(clk);
1047 if (freq == 0)
1048 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1049
1050 /* Sanity check */
1051 if (freq < 1000000 || freq > 25000000)
1052 return -ERANGE;
1053
1054 /* Allocate can/net device */
1055 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1056 if (!net)
1057 return -ENOMEM;
1058
1059 ret = clk_prepare_enable(clk);
1060 if (ret)
1061 goto out_free;
1062
1063 net->netdev_ops = &mcp251x_netdev_ops;
1064 net->flags |= IFF_ECHO;
1065
1066 priv = netdev_priv(net);
1067 priv->can.bittiming_const = &mcp251x_bittiming_const;
1068 priv->can.do_set_mode = mcp251x_do_set_mode;
1069 priv->can.clock.freq = freq / 2;
1070 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1071 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1072 if (match)
1073 priv->model = (enum mcp251x_model)match;
1074 else
1075 priv->model = spi_get_device_id(spi)->driver_data;
1076 priv->net = net;
1077 priv->clk = clk;
1078
1079 spi_set_drvdata(spi, priv);
1080
1081 /* Configure the SPI bus */
1082 spi->bits_per_word = 8;
1083 if (mcp251x_is_2510(spi))
1084 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1085 else
1086 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1087 ret = spi_setup(spi);
1088 if (ret)
1089 goto out_clk;
1090
1091 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1092 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1093 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1094 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1095 ret = -EPROBE_DEFER;
1096 goto out_clk;
1097 }
1098
1099 ret = mcp251x_power_enable(priv->power, 1);
1100 if (ret)
1101 goto out_clk;
1102
1103 priv->spi = spi;
1104 mutex_init(&priv->mcp_lock);
1105
1106 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1107 GFP_KERNEL);
1108 if (!priv->spi_tx_buf) {
1109 ret = -ENOMEM;
1110 goto error_probe;
1111 }
1112
1113 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1114 GFP_KERNEL);
1115 if (!priv->spi_rx_buf) {
1116 ret = -ENOMEM;
1117 goto error_probe;
1118 }
1119
1120 SET_NETDEV_DEV(net, &spi->dev);
1121
1122 /* Here is OK to not lock the MCP, no one knows about it yet */
1123 ret = mcp251x_hw_probe(spi);
1124 if (ret) {
1125 if (ret == -ENODEV)
1126 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1127 priv->model);
1128 goto error_probe;
1129 }
1130
1131 mcp251x_hw_sleep(spi);
1132
1133 ret = register_candev(net);
1134 if (ret)
1135 goto error_probe;
1136
1137 devm_can_led_init(net);
1138
1139 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1140 return 0;
1141
1142error_probe:
1143 mcp251x_power_enable(priv->power, 0);
1144
1145out_clk:
1146 clk_disable_unprepare(clk);
1147
1148out_free:
1149 free_candev(net);
1150
1151 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1152 return ret;
1153}
1154
1155static int mcp251x_can_remove(struct spi_device *spi)
1156{
1157 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1158 struct net_device *net = priv->net;
1159
1160 unregister_candev(net);
1161
1162 mcp251x_power_enable(priv->power, 0);
1163
1164 clk_disable_unprepare(priv->clk);
1165
1166 free_candev(net);
1167
1168 return 0;
1169}
1170
1171static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1172{
1173 struct spi_device *spi = to_spi_device(dev);
1174 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1175 struct net_device *net = priv->net;
1176
1177 priv->force_quit = 1;
1178 disable_irq(spi->irq);
1179 /* Note: at this point neither IST nor workqueues are running.
1180 * open/stop cannot be called anyway so locking is not needed
1181 */
1182 if (netif_running(net)) {
1183 netif_device_detach(net);
1184
1185 mcp251x_hw_sleep(spi);
1186 mcp251x_power_enable(priv->transceiver, 0);
1187 priv->after_suspend = AFTER_SUSPEND_UP;
1188 } else {
1189 priv->after_suspend = AFTER_SUSPEND_DOWN;
1190 }
1191
1192 mcp251x_power_enable(priv->power, 0);
1193 priv->after_suspend |= AFTER_SUSPEND_POWER;
1194
1195 return 0;
1196}
1197
1198static int __maybe_unused mcp251x_can_resume(struct device *dev)
1199{
1200 struct spi_device *spi = to_spi_device(dev);
1201 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1202
1203 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1204 mcp251x_power_enable(priv->power, 1);
1205 if (priv->after_suspend & AFTER_SUSPEND_UP)
1206 mcp251x_power_enable(priv->transceiver, 1);
1207
1208 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1209 queue_work(priv->wq, &priv->restart_work);
1210 else
1211 priv->after_suspend = 0;
1212
1213 priv->force_quit = 0;
1214 enable_irq(spi->irq);
1215 return 0;
1216}
1217
1218static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1219 mcp251x_can_resume);
1220
1221static struct spi_driver mcp251x_can_driver = {
1222 .driver = {
1223 .name = DEVICE_NAME,
1224 .of_match_table = mcp251x_of_match,
1225 .pm = &mcp251x_can_pm_ops,
1226 },
1227 .id_table = mcp251x_id_table,
1228 .probe = mcp251x_can_probe,
1229 .remove = mcp251x_can_remove,
1230};
1231module_spi_driver(mcp251x_can_driver);
1232
1233MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1234 "Christian Pellegrin <chripell@evolware.org>");
1235MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1236MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22#include <linux/bitfield.h>
23#include <linux/can/core.h>
24#include <linux/can/dev.h>
25#include <linux/clk.h>
26#include <linux/completion.h>
27#include <linux/delay.h>
28#include <linux/device.h>
29#include <linux/ethtool.h>
30#include <linux/freezer.h>
31#include <linux/gpio/driver.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/iopoll.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
38#include <linux/platform_device.h>
39#include <linux/property.h>
40#include <linux/regulator/consumer.h>
41#include <linux/slab.h>
42#include <linux/spi/spi.h>
43#include <linux/uaccess.h>
44
45/* SPI interface instruction set */
46#define INSTRUCTION_WRITE 0x02
47#define INSTRUCTION_READ 0x03
48#define INSTRUCTION_BIT_MODIFY 0x05
49#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
50#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
51#define INSTRUCTION_RESET 0xC0
52#define RTS_TXB0 0x01
53#define RTS_TXB1 0x02
54#define RTS_TXB2 0x04
55#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
56
57/* MPC251x registers */
58#define BFPCTRL 0x0c
59# define BFPCTRL_B0BFM BIT(0)
60# define BFPCTRL_B1BFM BIT(1)
61# define BFPCTRL_BFM(n) (BFPCTRL_B0BFM << (n))
62# define BFPCTRL_BFM_MASK GENMASK(1, 0)
63# define BFPCTRL_B0BFE BIT(2)
64# define BFPCTRL_B1BFE BIT(3)
65# define BFPCTRL_BFE(n) (BFPCTRL_B0BFE << (n))
66# define BFPCTRL_BFE_MASK GENMASK(3, 2)
67# define BFPCTRL_B0BFS BIT(4)
68# define BFPCTRL_B1BFS BIT(5)
69# define BFPCTRL_BFS(n) (BFPCTRL_B0BFS << (n))
70# define BFPCTRL_BFS_MASK GENMASK(5, 4)
71#define TXRTSCTRL 0x0d
72# define TXRTSCTRL_B0RTSM BIT(0)
73# define TXRTSCTRL_B1RTSM BIT(1)
74# define TXRTSCTRL_B2RTSM BIT(2)
75# define TXRTSCTRL_RTSM(n) (TXRTSCTRL_B0RTSM << (n))
76# define TXRTSCTRL_RTSM_MASK GENMASK(2, 0)
77# define TXRTSCTRL_B0RTS BIT(3)
78# define TXRTSCTRL_B1RTS BIT(4)
79# define TXRTSCTRL_B2RTS BIT(5)
80# define TXRTSCTRL_RTS(n) (TXRTSCTRL_B0RTS << (n))
81# define TXRTSCTRL_RTS_MASK GENMASK(5, 3)
82#define CANSTAT 0x0e
83#define CANCTRL 0x0f
84# define CANCTRL_REQOP_MASK 0xe0
85# define CANCTRL_REQOP_CONF 0x80
86# define CANCTRL_REQOP_LISTEN_ONLY 0x60
87# define CANCTRL_REQOP_LOOPBACK 0x40
88# define CANCTRL_REQOP_SLEEP 0x20
89# define CANCTRL_REQOP_NORMAL 0x00
90# define CANCTRL_OSM 0x08
91# define CANCTRL_ABAT 0x10
92#define TEC 0x1c
93#define REC 0x1d
94#define CNF1 0x2a
95# define CNF1_SJW_SHIFT 6
96#define CNF2 0x29
97# define CNF2_BTLMODE 0x80
98# define CNF2_SAM 0x40
99# define CNF2_PS1_SHIFT 3
100#define CNF3 0x28
101# define CNF3_SOF 0x08
102# define CNF3_WAKFIL 0x04
103# define CNF3_PHSEG2_MASK 0x07
104#define CANINTE 0x2b
105# define CANINTE_MERRE 0x80
106# define CANINTE_WAKIE 0x40
107# define CANINTE_ERRIE 0x20
108# define CANINTE_TX2IE 0x10
109# define CANINTE_TX1IE 0x08
110# define CANINTE_TX0IE 0x04
111# define CANINTE_RX1IE 0x02
112# define CANINTE_RX0IE 0x01
113#define CANINTF 0x2c
114# define CANINTF_MERRF 0x80
115# define CANINTF_WAKIF 0x40
116# define CANINTF_ERRIF 0x20
117# define CANINTF_TX2IF 0x10
118# define CANINTF_TX1IF 0x08
119# define CANINTF_TX0IF 0x04
120# define CANINTF_RX1IF 0x02
121# define CANINTF_RX0IF 0x01
122# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
123# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
124# define CANINTF_ERR (CANINTF_ERRIF)
125#define EFLG 0x2d
126# define EFLG_EWARN 0x01
127# define EFLG_RXWAR 0x02
128# define EFLG_TXWAR 0x04
129# define EFLG_RXEP 0x08
130# define EFLG_TXEP 0x10
131# define EFLG_TXBO 0x20
132# define EFLG_RX0OVR 0x40
133# define EFLG_RX1OVR 0x80
134#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
135# define TXBCTRL_ABTF 0x40
136# define TXBCTRL_MLOA 0x20
137# define TXBCTRL_TXERR 0x10
138# define TXBCTRL_TXREQ 0x08
139#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
140# define SIDH_SHIFT 3
141#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
142# define SIDL_SID_MASK 7
143# define SIDL_SID_SHIFT 5
144# define SIDL_EXIDE_SHIFT 3
145# define SIDL_EID_SHIFT 16
146# define SIDL_EID_MASK 3
147#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
148#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
149#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
150# define DLC_RTR_SHIFT 6
151#define TXBCTRL_OFF 0
152#define TXBSIDH_OFF 1
153#define TXBSIDL_OFF 2
154#define TXBEID8_OFF 3
155#define TXBEID0_OFF 4
156#define TXBDLC_OFF 5
157#define TXBDAT_OFF 6
158#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
159# define RXBCTRL_BUKT 0x04
160# define RXBCTRL_RXM0 0x20
161# define RXBCTRL_RXM1 0x40
162#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
163# define RXBSIDH_SHIFT 3
164#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
165# define RXBSIDL_IDE 0x08
166# define RXBSIDL_SRR 0x10
167# define RXBSIDL_EID 3
168# define RXBSIDL_SHIFT 5
169#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
170#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
171#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
172# define RXBDLC_LEN_MASK 0x0f
173# define RXBDLC_RTR 0x40
174#define RXBCTRL_OFF 0
175#define RXBSIDH_OFF 1
176#define RXBSIDL_OFF 2
177#define RXBEID8_OFF 3
178#define RXBEID0_OFF 4
179#define RXBDLC_OFF 5
180#define RXBDAT_OFF 6
181#define RXFSID(n) ((n < 3) ? 0 : 4)
182#define RXFSIDH(n) ((n) * 4 + RXFSID(n))
183#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
184#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
185#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
186#define RXMSIDH(n) ((n) * 4 + 0x20)
187#define RXMSIDL(n) ((n) * 4 + 0x21)
188#define RXMEID8(n) ((n) * 4 + 0x22)
189#define RXMEID0(n) ((n) * 4 + 0x23)
190
191#define GET_BYTE(val, byte) \
192 (((val) >> ((byte) * 8)) & 0xff)
193#define SET_BYTE(val, byte) \
194 (((val) & 0xff) << ((byte) * 8))
195
196/* Buffer size required for the largest SPI transfer (i.e., reading a
197 * frame)
198 */
199#define CAN_FRAME_MAX_DATA_LEN 8
200#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
201#define CAN_FRAME_MAX_BITS 128
202
203#define TX_ECHO_SKB_MAX 1
204
205#define MCP251X_OST_DELAY_MS (5)
206
207#define DEVICE_NAME "mcp251x"
208
209static const struct can_bittiming_const mcp251x_bittiming_const = {
210 .name = DEVICE_NAME,
211 .tseg1_min = 3,
212 .tseg1_max = 16,
213 .tseg2_min = 2,
214 .tseg2_max = 8,
215 .sjw_max = 4,
216 .brp_min = 1,
217 .brp_max = 64,
218 .brp_inc = 1,
219};
220
221enum mcp251x_model {
222 CAN_MCP251X_MCP2510 = 0x2510,
223 CAN_MCP251X_MCP2515 = 0x2515,
224 CAN_MCP251X_MCP25625 = 0x25625,
225};
226
227struct mcp251x_priv {
228 struct can_priv can;
229 struct net_device *net;
230 struct spi_device *spi;
231 enum mcp251x_model model;
232
233 struct mutex mcp_lock; /* SPI device lock */
234
235 u8 *spi_tx_buf;
236 u8 *spi_rx_buf;
237
238 struct sk_buff *tx_skb;
239
240 struct workqueue_struct *wq;
241 struct work_struct tx_work;
242 struct work_struct restart_work;
243
244 int force_quit;
245 int after_suspend;
246#define AFTER_SUSPEND_UP 1
247#define AFTER_SUSPEND_DOWN 2
248#define AFTER_SUSPEND_POWER 4
249#define AFTER_SUSPEND_RESTART 8
250 int restart_tx;
251 bool tx_busy;
252
253 struct regulator *power;
254 struct regulator *transceiver;
255 struct clk *clk;
256#ifdef CONFIG_GPIOLIB
257 struct gpio_chip gpio;
258 u8 reg_bfpctrl;
259#endif
260};
261
262#define MCP251X_IS(_model) \
263static inline int mcp251x_is_##_model(struct spi_device *spi) \
264{ \
265 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
266 return priv->model == CAN_MCP251X_MCP##_model; \
267}
268
269MCP251X_IS(2510);
270
271static void mcp251x_clean(struct net_device *net)
272{
273 struct mcp251x_priv *priv = netdev_priv(net);
274
275 if (priv->tx_skb || priv->tx_busy)
276 net->stats.tx_errors++;
277 dev_kfree_skb(priv->tx_skb);
278 if (priv->tx_busy)
279 can_free_echo_skb(priv->net, 0, NULL);
280 priv->tx_skb = NULL;
281 priv->tx_busy = false;
282}
283
284/* Note about handling of error return of mcp251x_spi_trans: accessing
285 * registers via SPI is not really different conceptually than using
286 * normal I/O assembler instructions, although it's much more
287 * complicated from a practical POV. So it's not advisable to always
288 * check the return value of this function. Imagine that every
289 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
290 * error();", it would be a great mess (well there are some situation
291 * when exception handling C++ like could be useful after all). So we
292 * just check that transfers are OK at the beginning of our
293 * conversation with the chip and to avoid doing really nasty things
294 * (like injecting bogus packets in the network stack).
295 */
296static int mcp251x_spi_trans(struct spi_device *spi, int len)
297{
298 struct mcp251x_priv *priv = spi_get_drvdata(spi);
299 struct spi_transfer t = {
300 .tx_buf = priv->spi_tx_buf,
301 .rx_buf = priv->spi_rx_buf,
302 .len = len,
303 .cs_change = 0,
304 };
305 struct spi_message m;
306 int ret;
307
308 spi_message_init(&m);
309 spi_message_add_tail(&t, &m);
310
311 ret = spi_sync(spi, &m);
312 if (ret)
313 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
314 return ret;
315}
316
317static int mcp251x_spi_write(struct spi_device *spi, int len)
318{
319 struct mcp251x_priv *priv = spi_get_drvdata(spi);
320 int ret;
321
322 ret = spi_write(spi, priv->spi_tx_buf, len);
323 if (ret)
324 dev_err(&spi->dev, "spi write failed: ret = %d\n", ret);
325
326 return ret;
327}
328
329static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
330{
331 struct mcp251x_priv *priv = spi_get_drvdata(spi);
332 u8 val = 0;
333
334 priv->spi_tx_buf[0] = INSTRUCTION_READ;
335 priv->spi_tx_buf[1] = reg;
336
337 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
338 spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1);
339 } else {
340 mcp251x_spi_trans(spi, 3);
341 val = priv->spi_rx_buf[2];
342 }
343
344 return val;
345}
346
347static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
348{
349 struct mcp251x_priv *priv = spi_get_drvdata(spi);
350
351 priv->spi_tx_buf[0] = INSTRUCTION_READ;
352 priv->spi_tx_buf[1] = reg;
353
354 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
355 u8 val[2] = { 0 };
356
357 spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2);
358 *v1 = val[0];
359 *v2 = val[1];
360 } else {
361 mcp251x_spi_trans(spi, 4);
362
363 *v1 = priv->spi_rx_buf[2];
364 *v2 = priv->spi_rx_buf[3];
365 }
366}
367
368static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
369{
370 struct mcp251x_priv *priv = spi_get_drvdata(spi);
371
372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = val;
375
376 mcp251x_spi_write(spi, 3);
377}
378
379static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
380{
381 struct mcp251x_priv *priv = spi_get_drvdata(spi);
382
383 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
384 priv->spi_tx_buf[1] = reg;
385 priv->spi_tx_buf[2] = v1;
386 priv->spi_tx_buf[3] = v2;
387
388 mcp251x_spi_write(spi, 4);
389}
390
391static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
392 u8 mask, u8 val)
393{
394 struct mcp251x_priv *priv = spi_get_drvdata(spi);
395
396 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
397 priv->spi_tx_buf[1] = reg;
398 priv->spi_tx_buf[2] = mask;
399 priv->spi_tx_buf[3] = val;
400
401 mcp251x_spi_write(spi, 4);
402}
403
404static u8 mcp251x_read_stat(struct spi_device *spi)
405{
406 return mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK;
407}
408
409#define mcp251x_read_stat_poll_timeout(addr, val, cond, delay_us, timeout_us) \
410 readx_poll_timeout(mcp251x_read_stat, addr, val, cond, \
411 delay_us, timeout_us)
412
413#ifdef CONFIG_GPIOLIB
414enum {
415 MCP251X_GPIO_TX0RTS = 0, /* inputs */
416 MCP251X_GPIO_TX1RTS,
417 MCP251X_GPIO_TX2RTS,
418 MCP251X_GPIO_RX0BF, /* outputs */
419 MCP251X_GPIO_RX1BF,
420};
421
422#define MCP251X_GPIO_INPUT_MASK \
423 GENMASK(MCP251X_GPIO_TX2RTS, MCP251X_GPIO_TX0RTS)
424#define MCP251X_GPIO_OUTPUT_MASK \
425 GENMASK(MCP251X_GPIO_RX1BF, MCP251X_GPIO_RX0BF)
426
427static const char * const mcp251x_gpio_names[] = {
428 [MCP251X_GPIO_TX0RTS] = "TX0RTS", /* inputs */
429 [MCP251X_GPIO_TX1RTS] = "TX1RTS",
430 [MCP251X_GPIO_TX2RTS] = "TX2RTS",
431 [MCP251X_GPIO_RX0BF] = "RX0BF", /* outputs */
432 [MCP251X_GPIO_RX1BF] = "RX1BF",
433};
434
435static inline bool mcp251x_gpio_is_input(unsigned int offset)
436{
437 return offset <= MCP251X_GPIO_TX2RTS;
438}
439
440static int mcp251x_gpio_request(struct gpio_chip *chip,
441 unsigned int offset)
442{
443 struct mcp251x_priv *priv = gpiochip_get_data(chip);
444 u8 val;
445
446 /* nothing to be done for inputs */
447 if (mcp251x_gpio_is_input(offset))
448 return 0;
449
450 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
451
452 mutex_lock(&priv->mcp_lock);
453 mcp251x_write_bits(priv->spi, BFPCTRL, val, val);
454 mutex_unlock(&priv->mcp_lock);
455
456 priv->reg_bfpctrl |= val;
457
458 return 0;
459}
460
461static void mcp251x_gpio_free(struct gpio_chip *chip,
462 unsigned int offset)
463{
464 struct mcp251x_priv *priv = gpiochip_get_data(chip);
465 u8 val;
466
467 /* nothing to be done for inputs */
468 if (mcp251x_gpio_is_input(offset))
469 return;
470
471 val = BFPCTRL_BFE(offset - MCP251X_GPIO_RX0BF);
472
473 mutex_lock(&priv->mcp_lock);
474 mcp251x_write_bits(priv->spi, BFPCTRL, val, 0);
475 mutex_unlock(&priv->mcp_lock);
476
477 priv->reg_bfpctrl &= ~val;
478}
479
480static int mcp251x_gpio_get_direction(struct gpio_chip *chip,
481 unsigned int offset)
482{
483 if (mcp251x_gpio_is_input(offset))
484 return GPIO_LINE_DIRECTION_IN;
485
486 return GPIO_LINE_DIRECTION_OUT;
487}
488
489static int mcp251x_gpio_get(struct gpio_chip *chip, unsigned int offset)
490{
491 struct mcp251x_priv *priv = gpiochip_get_data(chip);
492 u8 reg, mask, val;
493
494 if (mcp251x_gpio_is_input(offset)) {
495 reg = TXRTSCTRL;
496 mask = TXRTSCTRL_RTS(offset);
497 } else {
498 reg = BFPCTRL;
499 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
500 }
501
502 mutex_lock(&priv->mcp_lock);
503 val = mcp251x_read_reg(priv->spi, reg);
504 mutex_unlock(&priv->mcp_lock);
505
506 return !!(val & mask);
507}
508
509static int mcp251x_gpio_get_multiple(struct gpio_chip *chip,
510 unsigned long *maskp, unsigned long *bitsp)
511{
512 struct mcp251x_priv *priv = gpiochip_get_data(chip);
513 unsigned long bits = 0;
514 u8 val;
515
516 mutex_lock(&priv->mcp_lock);
517 if (maskp[0] & MCP251X_GPIO_INPUT_MASK) {
518 val = mcp251x_read_reg(priv->spi, TXRTSCTRL);
519 val = FIELD_GET(TXRTSCTRL_RTS_MASK, val);
520 bits |= FIELD_PREP(MCP251X_GPIO_INPUT_MASK, val);
521 }
522 if (maskp[0] & MCP251X_GPIO_OUTPUT_MASK) {
523 val = mcp251x_read_reg(priv->spi, BFPCTRL);
524 val = FIELD_GET(BFPCTRL_BFS_MASK, val);
525 bits |= FIELD_PREP(MCP251X_GPIO_OUTPUT_MASK, val);
526 }
527 mutex_unlock(&priv->mcp_lock);
528
529 bitsp[0] = bits;
530 return 0;
531}
532
533static void mcp251x_gpio_set(struct gpio_chip *chip, unsigned int offset,
534 int value)
535{
536 struct mcp251x_priv *priv = gpiochip_get_data(chip);
537 u8 mask, val;
538
539 mask = BFPCTRL_BFS(offset - MCP251X_GPIO_RX0BF);
540 val = value ? mask : 0;
541
542 mutex_lock(&priv->mcp_lock);
543 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
544 mutex_unlock(&priv->mcp_lock);
545
546 priv->reg_bfpctrl &= ~mask;
547 priv->reg_bfpctrl |= val;
548}
549
550static void
551mcp251x_gpio_set_multiple(struct gpio_chip *chip,
552 unsigned long *maskp, unsigned long *bitsp)
553{
554 struct mcp251x_priv *priv = gpiochip_get_data(chip);
555 u8 mask, val;
556
557 mask = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, maskp[0]);
558 mask = FIELD_PREP(BFPCTRL_BFS_MASK, mask);
559
560 val = FIELD_GET(MCP251X_GPIO_OUTPUT_MASK, bitsp[0]);
561 val = FIELD_PREP(BFPCTRL_BFS_MASK, val);
562
563 if (!mask)
564 return;
565
566 mutex_lock(&priv->mcp_lock);
567 mcp251x_write_bits(priv->spi, BFPCTRL, mask, val);
568 mutex_unlock(&priv->mcp_lock);
569
570 priv->reg_bfpctrl &= ~mask;
571 priv->reg_bfpctrl |= val;
572}
573
574static void mcp251x_gpio_restore(struct spi_device *spi)
575{
576 struct mcp251x_priv *priv = spi_get_drvdata(spi);
577
578 mcp251x_write_reg(spi, BFPCTRL, priv->reg_bfpctrl);
579}
580
581static int mcp251x_gpio_setup(struct mcp251x_priv *priv)
582{
583 struct gpio_chip *gpio = &priv->gpio;
584
585 if (!device_property_present(&priv->spi->dev, "gpio-controller"))
586 return 0;
587
588 /* gpiochip handles TX[0..2]RTS and RX[0..1]BF */
589 gpio->label = priv->spi->modalias;
590 gpio->parent = &priv->spi->dev;
591 gpio->owner = THIS_MODULE;
592 gpio->request = mcp251x_gpio_request;
593 gpio->free = mcp251x_gpio_free;
594 gpio->get_direction = mcp251x_gpio_get_direction;
595 gpio->get = mcp251x_gpio_get;
596 gpio->get_multiple = mcp251x_gpio_get_multiple;
597 gpio->set = mcp251x_gpio_set;
598 gpio->set_multiple = mcp251x_gpio_set_multiple;
599 gpio->base = -1;
600 gpio->ngpio = ARRAY_SIZE(mcp251x_gpio_names);
601 gpio->names = mcp251x_gpio_names;
602 gpio->can_sleep = true;
603
604 return devm_gpiochip_add_data(&priv->spi->dev, gpio, priv);
605}
606#else
607static inline void mcp251x_gpio_restore(struct spi_device *spi)
608{
609}
610
611static inline int mcp251x_gpio_setup(struct mcp251x_priv *priv)
612{
613 return 0;
614}
615#endif
616
617static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
618 int len, int tx_buf_idx)
619{
620 struct mcp251x_priv *priv = spi_get_drvdata(spi);
621
622 if (mcp251x_is_2510(spi)) {
623 int i;
624
625 for (i = 1; i < TXBDAT_OFF + len; i++)
626 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
627 buf[i]);
628 } else {
629 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
630 mcp251x_spi_write(spi, TXBDAT_OFF + len);
631 }
632}
633
634static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
635 int tx_buf_idx)
636{
637 struct mcp251x_priv *priv = spi_get_drvdata(spi);
638 u32 sid, eid, exide, rtr;
639 u8 buf[SPI_TRANSFER_BUF_LEN];
640
641 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
642 if (exide)
643 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
644 else
645 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
646 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
647 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
648
649 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
650 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
651 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
652 (exide << SIDL_EXIDE_SHIFT) |
653 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
654 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
655 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
656 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->len;
657 memcpy(buf + TXBDAT_OFF, frame->data, frame->len);
658 mcp251x_hw_tx_frame(spi, buf, frame->len, tx_buf_idx);
659
660 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
661 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
662 mcp251x_spi_write(priv->spi, 1);
663}
664
665static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
666 int buf_idx)
667{
668 struct mcp251x_priv *priv = spi_get_drvdata(spi);
669
670 if (mcp251x_is_2510(spi)) {
671 int i, len;
672
673 for (i = 1; i < RXBDAT_OFF; i++)
674 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
675
676 len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
677 for (; i < (RXBDAT_OFF + len); i++)
678 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
679 } else {
680 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
681 if (spi->controller->flags & SPI_CONTROLLER_HALF_DUPLEX) {
682 spi_write_then_read(spi, priv->spi_tx_buf, 1,
683 priv->spi_rx_buf,
684 SPI_TRANSFER_BUF_LEN);
685 memcpy(buf + 1, priv->spi_rx_buf,
686 SPI_TRANSFER_BUF_LEN - 1);
687 } else {
688 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
689 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
690 }
691 }
692}
693
694static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
695{
696 struct mcp251x_priv *priv = spi_get_drvdata(spi);
697 struct sk_buff *skb;
698 struct can_frame *frame;
699 u8 buf[SPI_TRANSFER_BUF_LEN];
700
701 skb = alloc_can_skb(priv->net, &frame);
702 if (!skb) {
703 dev_err(&spi->dev, "cannot allocate RX skb\n");
704 priv->net->stats.rx_dropped++;
705 return;
706 }
707
708 mcp251x_hw_rx_frame(spi, buf, buf_idx);
709 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
710 /* Extended ID format */
711 frame->can_id = CAN_EFF_FLAG;
712 frame->can_id |=
713 /* Extended ID part */
714 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
715 SET_BYTE(buf[RXBEID8_OFF], 1) |
716 SET_BYTE(buf[RXBEID0_OFF], 0) |
717 /* Standard ID part */
718 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
719 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
720 /* Remote transmission request */
721 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
722 frame->can_id |= CAN_RTR_FLAG;
723 } else {
724 /* Standard ID format */
725 frame->can_id =
726 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
727 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
728 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
729 frame->can_id |= CAN_RTR_FLAG;
730 }
731 /* Data length */
732 frame->len = can_cc_dlc2len(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
733 if (!(frame->can_id & CAN_RTR_FLAG)) {
734 memcpy(frame->data, buf + RXBDAT_OFF, frame->len);
735
736 priv->net->stats.rx_bytes += frame->len;
737 }
738 priv->net->stats.rx_packets++;
739
740 netif_rx(skb);
741}
742
743static void mcp251x_hw_sleep(struct spi_device *spi)
744{
745 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
746}
747
748/* May only be called when device is sleeping! */
749static int mcp251x_hw_wake(struct spi_device *spi)
750{
751 u8 value;
752 int ret;
753
754 /* Force wakeup interrupt to wake device, but don't execute IST */
755 disable_irq_nosync(spi->irq);
756 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
757
758 /* Wait for oscillator startup timer after wake up */
759 mdelay(MCP251X_OST_DELAY_MS);
760
761 /* Put device into config mode */
762 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
763
764 /* Wait for the device to enter config mode */
765 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
766 MCP251X_OST_DELAY_MS * 1000,
767 USEC_PER_SEC);
768 if (ret) {
769 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
770 return ret;
771 }
772
773 /* Disable and clear pending interrupts */
774 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
775 enable_irq(spi->irq);
776
777 return 0;
778}
779
780static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
781 struct net_device *net)
782{
783 struct mcp251x_priv *priv = netdev_priv(net);
784 struct spi_device *spi = priv->spi;
785
786 if (priv->tx_skb || priv->tx_busy) {
787 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
788 return NETDEV_TX_BUSY;
789 }
790
791 if (can_dev_dropped_skb(net, skb))
792 return NETDEV_TX_OK;
793
794 netif_stop_queue(net);
795 priv->tx_skb = skb;
796 queue_work(priv->wq, &priv->tx_work);
797
798 return NETDEV_TX_OK;
799}
800
801static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
802{
803 struct mcp251x_priv *priv = netdev_priv(net);
804
805 switch (mode) {
806 case CAN_MODE_START:
807 mcp251x_clean(net);
808 /* We have to delay work since SPI I/O may sleep */
809 priv->can.state = CAN_STATE_ERROR_ACTIVE;
810 priv->restart_tx = 1;
811 if (priv->can.restart_ms == 0)
812 priv->after_suspend = AFTER_SUSPEND_RESTART;
813 queue_work(priv->wq, &priv->restart_work);
814 break;
815 default:
816 return -EOPNOTSUPP;
817 }
818
819 return 0;
820}
821
822static int mcp251x_set_normal_mode(struct spi_device *spi)
823{
824 struct mcp251x_priv *priv = spi_get_drvdata(spi);
825 u8 value;
826 int ret;
827
828 /* Enable interrupts */
829 mcp251x_write_reg(spi, CANINTE,
830 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
831 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
832
833 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
834 /* Put device into loopback mode */
835 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
836 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
837 /* Put device into listen-only mode */
838 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
839 } else {
840 /* Put device into normal mode */
841 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
842
843 /* Wait for the device to enter normal mode */
844 ret = mcp251x_read_stat_poll_timeout(spi, value, value == 0,
845 MCP251X_OST_DELAY_MS * 1000,
846 USEC_PER_SEC);
847 if (ret) {
848 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
849 return ret;
850 }
851 }
852 priv->can.state = CAN_STATE_ERROR_ACTIVE;
853 return 0;
854}
855
856static int mcp251x_do_set_bittiming(struct net_device *net)
857{
858 struct mcp251x_priv *priv = netdev_priv(net);
859 struct can_bittiming *bt = &priv->can.bittiming;
860 struct spi_device *spi = priv->spi;
861
862 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
863 (bt->brp - 1));
864 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
865 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
866 CNF2_SAM : 0) |
867 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
868 (bt->prop_seg - 1));
869 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
870 (bt->phase_seg2 - 1));
871 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
872 mcp251x_read_reg(spi, CNF1),
873 mcp251x_read_reg(spi, CNF2),
874 mcp251x_read_reg(spi, CNF3));
875
876 return 0;
877}
878
879static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
880{
881 mcp251x_do_set_bittiming(net);
882
883 mcp251x_write_reg(spi, RXBCTRL(0),
884 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
885 mcp251x_write_reg(spi, RXBCTRL(1),
886 RXBCTRL_RXM0 | RXBCTRL_RXM1);
887 return 0;
888}
889
890static int mcp251x_hw_reset(struct spi_device *spi)
891{
892 struct mcp251x_priv *priv = spi_get_drvdata(spi);
893 u8 value;
894 int ret;
895
896 /* Wait for oscillator startup timer after power up */
897 mdelay(MCP251X_OST_DELAY_MS);
898
899 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
900 ret = mcp251x_spi_write(spi, 1);
901 if (ret)
902 return ret;
903
904 /* Wait for oscillator startup timer after reset */
905 mdelay(MCP251X_OST_DELAY_MS);
906
907 /* Wait for reset to finish */
908 ret = mcp251x_read_stat_poll_timeout(spi, value, value == CANCTRL_REQOP_CONF,
909 MCP251X_OST_DELAY_MS * 1000,
910 USEC_PER_SEC);
911 if (ret)
912 dev_err(&spi->dev, "MCP251x didn't enter in conf mode after reset\n");
913 return ret;
914}
915
916static int mcp251x_hw_probe(struct spi_device *spi)
917{
918 u8 ctrl;
919 int ret;
920
921 ret = mcp251x_hw_reset(spi);
922 if (ret)
923 return ret;
924
925 ctrl = mcp251x_read_reg(spi, CANCTRL);
926
927 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
928
929 /* Check for power up default value */
930 if ((ctrl & 0x17) != 0x07)
931 return -ENODEV;
932
933 return 0;
934}
935
936static int mcp251x_power_enable(struct regulator *reg, int enable)
937{
938 if (IS_ERR_OR_NULL(reg))
939 return 0;
940
941 if (enable)
942 return regulator_enable(reg);
943 else
944 return regulator_disable(reg);
945}
946
947static int mcp251x_stop(struct net_device *net)
948{
949 struct mcp251x_priv *priv = netdev_priv(net);
950 struct spi_device *spi = priv->spi;
951
952 close_candev(net);
953
954 priv->force_quit = 1;
955 free_irq(spi->irq, priv);
956
957 mutex_lock(&priv->mcp_lock);
958
959 /* Disable and clear pending interrupts */
960 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
961
962 mcp251x_write_reg(spi, TXBCTRL(0), 0);
963 mcp251x_clean(net);
964
965 mcp251x_hw_sleep(spi);
966
967 mcp251x_power_enable(priv->transceiver, 0);
968
969 priv->can.state = CAN_STATE_STOPPED;
970
971 mutex_unlock(&priv->mcp_lock);
972
973 return 0;
974}
975
976static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
977{
978 struct sk_buff *skb;
979 struct can_frame *frame;
980
981 skb = alloc_can_err_skb(net, &frame);
982 if (skb) {
983 frame->can_id |= can_id;
984 frame->data[1] = data1;
985 netif_rx(skb);
986 } else {
987 netdev_err(net, "cannot allocate error skb\n");
988 }
989}
990
991static void mcp251x_tx_work_handler(struct work_struct *ws)
992{
993 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
994 tx_work);
995 struct spi_device *spi = priv->spi;
996 struct net_device *net = priv->net;
997 struct can_frame *frame;
998
999 mutex_lock(&priv->mcp_lock);
1000 if (priv->tx_skb) {
1001 if (priv->can.state == CAN_STATE_BUS_OFF) {
1002 mcp251x_clean(net);
1003 } else {
1004 frame = (struct can_frame *)priv->tx_skb->data;
1005
1006 if (frame->len > CAN_FRAME_MAX_DATA_LEN)
1007 frame->len = CAN_FRAME_MAX_DATA_LEN;
1008 mcp251x_hw_tx(spi, frame, 0);
1009 priv->tx_busy = true;
1010 can_put_echo_skb(priv->tx_skb, net, 0, 0);
1011 priv->tx_skb = NULL;
1012 }
1013 }
1014 mutex_unlock(&priv->mcp_lock);
1015}
1016
1017static void mcp251x_restart_work_handler(struct work_struct *ws)
1018{
1019 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
1020 restart_work);
1021 struct spi_device *spi = priv->spi;
1022 struct net_device *net = priv->net;
1023
1024 mutex_lock(&priv->mcp_lock);
1025 if (priv->after_suspend) {
1026 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
1027 mcp251x_hw_reset(spi);
1028 mcp251x_setup(net, spi);
1029 mcp251x_gpio_restore(spi);
1030 } else {
1031 mcp251x_hw_wake(spi);
1032 }
1033 priv->force_quit = 0;
1034 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
1035 mcp251x_set_normal_mode(spi);
1036 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
1037 netif_device_attach(net);
1038 mcp251x_clean(net);
1039 mcp251x_set_normal_mode(spi);
1040 netif_wake_queue(net);
1041 } else {
1042 mcp251x_hw_sleep(spi);
1043 }
1044 priv->after_suspend = 0;
1045 }
1046
1047 if (priv->restart_tx) {
1048 priv->restart_tx = 0;
1049 mcp251x_write_reg(spi, TXBCTRL(0), 0);
1050 mcp251x_clean(net);
1051 netif_wake_queue(net);
1052 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
1053 }
1054 mutex_unlock(&priv->mcp_lock);
1055}
1056
1057static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
1058{
1059 struct mcp251x_priv *priv = dev_id;
1060 struct spi_device *spi = priv->spi;
1061 struct net_device *net = priv->net;
1062
1063 mutex_lock(&priv->mcp_lock);
1064 while (!priv->force_quit) {
1065 enum can_state new_state;
1066 u8 intf, eflag;
1067 u8 clear_intf = 0;
1068 int can_id = 0, data1 = 0;
1069
1070 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
1071
1072 /* receive buffer 0 */
1073 if (intf & CANINTF_RX0IF) {
1074 mcp251x_hw_rx(spi, 0);
1075 /* Free one buffer ASAP
1076 * (The MCP2515/25625 does this automatically.)
1077 */
1078 if (mcp251x_is_2510(spi))
1079 mcp251x_write_bits(spi, CANINTF,
1080 CANINTF_RX0IF, 0x00);
1081
1082 /* check if buffer 1 is already known to be full, no need to re-read */
1083 if (!(intf & CANINTF_RX1IF)) {
1084 u8 intf1, eflag1;
1085
1086 /* intf needs to be read again to avoid a race condition */
1087 mcp251x_read_2regs(spi, CANINTF, &intf1, &eflag1);
1088
1089 /* combine flags from both operations for error handling */
1090 intf |= intf1;
1091 eflag |= eflag1;
1092 }
1093 }
1094
1095 /* receive buffer 1 */
1096 if (intf & CANINTF_RX1IF) {
1097 mcp251x_hw_rx(spi, 1);
1098 /* The MCP2515/25625 does this automatically. */
1099 if (mcp251x_is_2510(spi))
1100 clear_intf |= CANINTF_RX1IF;
1101 }
1102
1103 /* mask out flags we don't care about */
1104 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
1105
1106 /* any error or tx interrupt we need to clear? */
1107 if (intf & (CANINTF_ERR | CANINTF_TX))
1108 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
1109 if (clear_intf)
1110 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
1111
1112 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
1113 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
1114
1115 /* Update can state */
1116 if (eflag & EFLG_TXBO) {
1117 new_state = CAN_STATE_BUS_OFF;
1118 can_id |= CAN_ERR_BUSOFF;
1119 } else if (eflag & EFLG_TXEP) {
1120 new_state = CAN_STATE_ERROR_PASSIVE;
1121 can_id |= CAN_ERR_CRTL;
1122 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
1123 } else if (eflag & EFLG_RXEP) {
1124 new_state = CAN_STATE_ERROR_PASSIVE;
1125 can_id |= CAN_ERR_CRTL;
1126 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
1127 } else if (eflag & EFLG_TXWAR) {
1128 new_state = CAN_STATE_ERROR_WARNING;
1129 can_id |= CAN_ERR_CRTL;
1130 data1 |= CAN_ERR_CRTL_TX_WARNING;
1131 } else if (eflag & EFLG_RXWAR) {
1132 new_state = CAN_STATE_ERROR_WARNING;
1133 can_id |= CAN_ERR_CRTL;
1134 data1 |= CAN_ERR_CRTL_RX_WARNING;
1135 } else {
1136 new_state = CAN_STATE_ERROR_ACTIVE;
1137 }
1138
1139 /* Update can state statistics */
1140 switch (priv->can.state) {
1141 case CAN_STATE_ERROR_ACTIVE:
1142 if (new_state >= CAN_STATE_ERROR_WARNING &&
1143 new_state <= CAN_STATE_BUS_OFF)
1144 priv->can.can_stats.error_warning++;
1145 fallthrough;
1146 case CAN_STATE_ERROR_WARNING:
1147 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
1148 new_state <= CAN_STATE_BUS_OFF)
1149 priv->can.can_stats.error_passive++;
1150 break;
1151 default:
1152 break;
1153 }
1154 priv->can.state = new_state;
1155
1156 if (intf & CANINTF_ERRIF) {
1157 /* Handle overflow counters */
1158 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
1159 if (eflag & EFLG_RX0OVR) {
1160 net->stats.rx_over_errors++;
1161 net->stats.rx_errors++;
1162 }
1163 if (eflag & EFLG_RX1OVR) {
1164 net->stats.rx_over_errors++;
1165 net->stats.rx_errors++;
1166 }
1167 can_id |= CAN_ERR_CRTL;
1168 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
1169 }
1170 mcp251x_error_skb(net, can_id, data1);
1171 }
1172
1173 if (priv->can.state == CAN_STATE_BUS_OFF) {
1174 if (priv->can.restart_ms == 0) {
1175 priv->force_quit = 1;
1176 priv->can.can_stats.bus_off++;
1177 can_bus_off(net);
1178 mcp251x_hw_sleep(spi);
1179 break;
1180 }
1181 }
1182
1183 if (intf == 0)
1184 break;
1185
1186 if (intf & CANINTF_TX) {
1187 if (priv->tx_busy) {
1188 net->stats.tx_packets++;
1189 net->stats.tx_bytes += can_get_echo_skb(net, 0,
1190 NULL);
1191 priv->tx_busy = false;
1192 }
1193 netif_wake_queue(net);
1194 }
1195 }
1196 mutex_unlock(&priv->mcp_lock);
1197 return IRQ_HANDLED;
1198}
1199
1200static int mcp251x_open(struct net_device *net)
1201{
1202 struct mcp251x_priv *priv = netdev_priv(net);
1203 struct spi_device *spi = priv->spi;
1204 unsigned long flags = 0;
1205 int ret;
1206
1207 ret = open_candev(net);
1208 if (ret) {
1209 dev_err(&spi->dev, "unable to set initial baudrate!\n");
1210 return ret;
1211 }
1212
1213 mutex_lock(&priv->mcp_lock);
1214 mcp251x_power_enable(priv->transceiver, 1);
1215
1216 priv->force_quit = 0;
1217 priv->tx_skb = NULL;
1218 priv->tx_busy = false;
1219
1220 if (!dev_fwnode(&spi->dev))
1221 flags = IRQF_TRIGGER_FALLING;
1222
1223 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
1224 flags | IRQF_ONESHOT, dev_name(&spi->dev),
1225 priv);
1226 if (ret) {
1227 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
1228 goto out_close;
1229 }
1230
1231 ret = mcp251x_hw_wake(spi);
1232 if (ret)
1233 goto out_free_irq;
1234 ret = mcp251x_setup(net, spi);
1235 if (ret)
1236 goto out_free_irq;
1237 ret = mcp251x_set_normal_mode(spi);
1238 if (ret)
1239 goto out_free_irq;
1240
1241 netif_wake_queue(net);
1242 mutex_unlock(&priv->mcp_lock);
1243
1244 return 0;
1245
1246out_free_irq:
1247 free_irq(spi->irq, priv);
1248 mcp251x_hw_sleep(spi);
1249out_close:
1250 mcp251x_power_enable(priv->transceiver, 0);
1251 close_candev(net);
1252 mutex_unlock(&priv->mcp_lock);
1253 return ret;
1254}
1255
1256static const struct net_device_ops mcp251x_netdev_ops = {
1257 .ndo_open = mcp251x_open,
1258 .ndo_stop = mcp251x_stop,
1259 .ndo_start_xmit = mcp251x_hard_start_xmit,
1260 .ndo_change_mtu = can_change_mtu,
1261};
1262
1263static const struct ethtool_ops mcp251x_ethtool_ops = {
1264 .get_ts_info = ethtool_op_get_ts_info,
1265};
1266
1267static const struct of_device_id mcp251x_of_match[] = {
1268 {
1269 .compatible = "microchip,mcp2510",
1270 .data = (void *)CAN_MCP251X_MCP2510,
1271 },
1272 {
1273 .compatible = "microchip,mcp2515",
1274 .data = (void *)CAN_MCP251X_MCP2515,
1275 },
1276 {
1277 .compatible = "microchip,mcp25625",
1278 .data = (void *)CAN_MCP251X_MCP25625,
1279 },
1280 { }
1281};
1282MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1283
1284static const struct spi_device_id mcp251x_id_table[] = {
1285 {
1286 .name = "mcp2510",
1287 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1288 },
1289 {
1290 .name = "mcp2515",
1291 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1292 },
1293 {
1294 .name = "mcp25625",
1295 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1296 },
1297 { }
1298};
1299MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1300
1301static int mcp251x_can_probe(struct spi_device *spi)
1302{
1303 struct net_device *net;
1304 struct mcp251x_priv *priv;
1305 struct clk *clk;
1306 u32 freq;
1307 int ret;
1308
1309 clk = devm_clk_get_optional(&spi->dev, NULL);
1310 if (IS_ERR(clk))
1311 return PTR_ERR(clk);
1312
1313 freq = clk_get_rate(clk);
1314 if (freq == 0)
1315 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1316
1317 /* Sanity check */
1318 if (freq < 1000000 || freq > 25000000)
1319 return -ERANGE;
1320
1321 /* Allocate can/net device */
1322 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1323 if (!net)
1324 return -ENOMEM;
1325
1326 ret = clk_prepare_enable(clk);
1327 if (ret)
1328 goto out_free;
1329
1330 net->netdev_ops = &mcp251x_netdev_ops;
1331 net->ethtool_ops = &mcp251x_ethtool_ops;
1332 net->flags |= IFF_ECHO;
1333
1334 priv = netdev_priv(net);
1335 priv->can.bittiming_const = &mcp251x_bittiming_const;
1336 priv->can.do_set_mode = mcp251x_do_set_mode;
1337 priv->can.clock.freq = freq / 2;
1338 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1339 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1340 priv->model = (enum mcp251x_model)(uintptr_t)spi_get_device_match_data(spi);
1341 priv->net = net;
1342 priv->clk = clk;
1343
1344 spi_set_drvdata(spi, priv);
1345
1346 /* Configure the SPI bus */
1347 spi->bits_per_word = 8;
1348 if (mcp251x_is_2510(spi))
1349 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1350 else
1351 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1352 ret = spi_setup(spi);
1353 if (ret)
1354 goto out_clk;
1355
1356 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1357 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1358 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1359 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1360 ret = -EPROBE_DEFER;
1361 goto out_clk;
1362 }
1363
1364 ret = mcp251x_power_enable(priv->power, 1);
1365 if (ret)
1366 goto out_clk;
1367
1368 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
1369 0);
1370 if (!priv->wq) {
1371 ret = -ENOMEM;
1372 goto out_clk;
1373 }
1374 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
1375 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
1376
1377 priv->spi = spi;
1378 mutex_init(&priv->mcp_lock);
1379
1380 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1381 GFP_KERNEL);
1382 if (!priv->spi_tx_buf) {
1383 ret = -ENOMEM;
1384 goto error_probe;
1385 }
1386
1387 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1388 GFP_KERNEL);
1389 if (!priv->spi_rx_buf) {
1390 ret = -ENOMEM;
1391 goto error_probe;
1392 }
1393
1394 SET_NETDEV_DEV(net, &spi->dev);
1395
1396 /* Here is OK to not lock the MCP, no one knows about it yet */
1397 ret = mcp251x_hw_probe(spi);
1398 if (ret) {
1399 if (ret == -ENODEV)
1400 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1401 priv->model);
1402 goto error_probe;
1403 }
1404
1405 mcp251x_hw_sleep(spi);
1406
1407 ret = register_candev(net);
1408 if (ret)
1409 goto error_probe;
1410
1411 ret = mcp251x_gpio_setup(priv);
1412 if (ret)
1413 goto out_unregister_candev;
1414
1415 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1416 return 0;
1417
1418out_unregister_candev:
1419 unregister_candev(net);
1420
1421error_probe:
1422 destroy_workqueue(priv->wq);
1423 priv->wq = NULL;
1424 mcp251x_power_enable(priv->power, 0);
1425
1426out_clk:
1427 clk_disable_unprepare(clk);
1428
1429out_free:
1430 free_candev(net);
1431
1432 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1433 return ret;
1434}
1435
1436static void mcp251x_can_remove(struct spi_device *spi)
1437{
1438 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1439 struct net_device *net = priv->net;
1440
1441 unregister_candev(net);
1442
1443 mcp251x_power_enable(priv->power, 0);
1444
1445 destroy_workqueue(priv->wq);
1446 priv->wq = NULL;
1447
1448 clk_disable_unprepare(priv->clk);
1449
1450 free_candev(net);
1451}
1452
1453static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1454{
1455 struct spi_device *spi = to_spi_device(dev);
1456 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1457 struct net_device *net = priv->net;
1458
1459 priv->force_quit = 1;
1460 disable_irq(spi->irq);
1461 /* Note: at this point neither IST nor workqueues are running.
1462 * open/stop cannot be called anyway so locking is not needed
1463 */
1464 if (netif_running(net)) {
1465 netif_device_detach(net);
1466
1467 mcp251x_hw_sleep(spi);
1468 mcp251x_power_enable(priv->transceiver, 0);
1469 priv->after_suspend = AFTER_SUSPEND_UP;
1470 } else {
1471 priv->after_suspend = AFTER_SUSPEND_DOWN;
1472 }
1473
1474 mcp251x_power_enable(priv->power, 0);
1475 priv->after_suspend |= AFTER_SUSPEND_POWER;
1476
1477 return 0;
1478}
1479
1480static int __maybe_unused mcp251x_can_resume(struct device *dev)
1481{
1482 struct spi_device *spi = to_spi_device(dev);
1483 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1484
1485 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1486 mcp251x_power_enable(priv->power, 1);
1487 if (priv->after_suspend & AFTER_SUSPEND_UP)
1488 mcp251x_power_enable(priv->transceiver, 1);
1489
1490 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1491 queue_work(priv->wq, &priv->restart_work);
1492 else
1493 priv->after_suspend = 0;
1494
1495 priv->force_quit = 0;
1496 enable_irq(spi->irq);
1497 return 0;
1498}
1499
1500static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1501 mcp251x_can_resume);
1502
1503static struct spi_driver mcp251x_can_driver = {
1504 .driver = {
1505 .name = DEVICE_NAME,
1506 .of_match_table = mcp251x_of_match,
1507 .pm = &mcp251x_can_pm_ops,
1508 },
1509 .id_table = mcp251x_id_table,
1510 .probe = mcp251x_can_probe,
1511 .remove = mcp251x_can_remove,
1512};
1513module_spi_driver(mcp251x_can_driver);
1514
1515MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1516 "Christian Pellegrin <chripell@evolware.org>");
1517MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1518MODULE_LICENSE("GPL v2");