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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/bsearch.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include "kfd_priv.h"
27#include "kfd_device_queue_manager.h"
28#include "kfd_pm4_headers_vi.h"
29#include "cwsr_trap_handler.h"
30#include "kfd_iommu.h"
31#include "amdgpu_amdkfd.h"
32
33#define MQD_SIZE_ALIGNED 768
34
35/*
36 * kfd_locked is used to lock the kfd driver during suspend or reset
37 * once locked, kfd driver will stop any further GPU execution.
38 * create process (open) will return -EAGAIN.
39 */
40static atomic_t kfd_locked = ATOMIC_INIT(0);
41
42#ifdef CONFIG_DRM_AMDGPU_CIK
43extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
44#endif
45extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
46extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
47extern const struct kfd2kgd_calls arcturus_kfd2kgd;
48extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
49extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
50
51static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
52#ifdef KFD_SUPPORT_IOMMU_V2
53#ifdef CONFIG_DRM_AMDGPU_CIK
54 [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
55#endif
56 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
57 [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
58#endif
59#ifdef CONFIG_DRM_AMDGPU_CIK
60 [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
61#endif
62 [CHIP_TONGA] = &gfx_v8_kfd2kgd,
63 [CHIP_FIJI] = &gfx_v8_kfd2kgd,
64 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
65 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
66 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
67 [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
68 [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
69 [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
70 [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
71 [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
72 [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
73 [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
74 [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
75 [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
76 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
77 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
78};
79
80#ifdef KFD_SUPPORT_IOMMU_V2
81static const struct kfd_device_info kaveri_device_info = {
82 .asic_family = CHIP_KAVERI,
83 .asic_name = "kaveri",
84 .max_pasid_bits = 16,
85 /* max num of queues for KV.TODO should be a dynamic value */
86 .max_no_of_hqd = 24,
87 .doorbell_size = 4,
88 .ih_ring_entry_size = 4 * sizeof(uint32_t),
89 .event_interrupt_class = &event_interrupt_class_cik,
90 .num_of_watch_points = 4,
91 .mqd_size_aligned = MQD_SIZE_ALIGNED,
92 .supports_cwsr = false,
93 .needs_iommu_device = true,
94 .needs_pci_atomics = false,
95 .num_sdma_engines = 2,
96 .num_xgmi_sdma_engines = 0,
97 .num_sdma_queues_per_engine = 2,
98};
99
100static const struct kfd_device_info carrizo_device_info = {
101 .asic_family = CHIP_CARRIZO,
102 .asic_name = "carrizo",
103 .max_pasid_bits = 16,
104 /* max num of queues for CZ.TODO should be a dynamic value */
105 .max_no_of_hqd = 24,
106 .doorbell_size = 4,
107 .ih_ring_entry_size = 4 * sizeof(uint32_t),
108 .event_interrupt_class = &event_interrupt_class_cik,
109 .num_of_watch_points = 4,
110 .mqd_size_aligned = MQD_SIZE_ALIGNED,
111 .supports_cwsr = true,
112 .needs_iommu_device = true,
113 .needs_pci_atomics = false,
114 .num_sdma_engines = 2,
115 .num_xgmi_sdma_engines = 0,
116 .num_sdma_queues_per_engine = 2,
117};
118
119static const struct kfd_device_info raven_device_info = {
120 .asic_family = CHIP_RAVEN,
121 .asic_name = "raven",
122 .max_pasid_bits = 16,
123 .max_no_of_hqd = 24,
124 .doorbell_size = 8,
125 .ih_ring_entry_size = 8 * sizeof(uint32_t),
126 .event_interrupt_class = &event_interrupt_class_v9,
127 .num_of_watch_points = 4,
128 .mqd_size_aligned = MQD_SIZE_ALIGNED,
129 .supports_cwsr = true,
130 .needs_iommu_device = true,
131 .needs_pci_atomics = true,
132 .num_sdma_engines = 1,
133 .num_xgmi_sdma_engines = 0,
134 .num_sdma_queues_per_engine = 2,
135};
136#endif
137
138static const struct kfd_device_info hawaii_device_info = {
139 .asic_family = CHIP_HAWAII,
140 .asic_name = "hawaii",
141 .max_pasid_bits = 16,
142 /* max num of queues for KV.TODO should be a dynamic value */
143 .max_no_of_hqd = 24,
144 .doorbell_size = 4,
145 .ih_ring_entry_size = 4 * sizeof(uint32_t),
146 .event_interrupt_class = &event_interrupt_class_cik,
147 .num_of_watch_points = 4,
148 .mqd_size_aligned = MQD_SIZE_ALIGNED,
149 .supports_cwsr = false,
150 .needs_iommu_device = false,
151 .needs_pci_atomics = false,
152 .num_sdma_engines = 2,
153 .num_xgmi_sdma_engines = 0,
154 .num_sdma_queues_per_engine = 2,
155};
156
157static const struct kfd_device_info tonga_device_info = {
158 .asic_family = CHIP_TONGA,
159 .asic_name = "tonga",
160 .max_pasid_bits = 16,
161 .max_no_of_hqd = 24,
162 .doorbell_size = 4,
163 .ih_ring_entry_size = 4 * sizeof(uint32_t),
164 .event_interrupt_class = &event_interrupt_class_cik,
165 .num_of_watch_points = 4,
166 .mqd_size_aligned = MQD_SIZE_ALIGNED,
167 .supports_cwsr = false,
168 .needs_iommu_device = false,
169 .needs_pci_atomics = true,
170 .num_sdma_engines = 2,
171 .num_xgmi_sdma_engines = 0,
172 .num_sdma_queues_per_engine = 2,
173};
174
175static const struct kfd_device_info fiji_device_info = {
176 .asic_family = CHIP_FIJI,
177 .asic_name = "fiji",
178 .max_pasid_bits = 16,
179 .max_no_of_hqd = 24,
180 .doorbell_size = 4,
181 .ih_ring_entry_size = 4 * sizeof(uint32_t),
182 .event_interrupt_class = &event_interrupt_class_cik,
183 .num_of_watch_points = 4,
184 .mqd_size_aligned = MQD_SIZE_ALIGNED,
185 .supports_cwsr = true,
186 .needs_iommu_device = false,
187 .needs_pci_atomics = true,
188 .num_sdma_engines = 2,
189 .num_xgmi_sdma_engines = 0,
190 .num_sdma_queues_per_engine = 2,
191};
192
193static const struct kfd_device_info fiji_vf_device_info = {
194 .asic_family = CHIP_FIJI,
195 .asic_name = "fiji",
196 .max_pasid_bits = 16,
197 .max_no_of_hqd = 24,
198 .doorbell_size = 4,
199 .ih_ring_entry_size = 4 * sizeof(uint32_t),
200 .event_interrupt_class = &event_interrupt_class_cik,
201 .num_of_watch_points = 4,
202 .mqd_size_aligned = MQD_SIZE_ALIGNED,
203 .supports_cwsr = true,
204 .needs_iommu_device = false,
205 .needs_pci_atomics = false,
206 .num_sdma_engines = 2,
207 .num_xgmi_sdma_engines = 0,
208 .num_sdma_queues_per_engine = 2,
209};
210
211
212static const struct kfd_device_info polaris10_device_info = {
213 .asic_family = CHIP_POLARIS10,
214 .asic_name = "polaris10",
215 .max_pasid_bits = 16,
216 .max_no_of_hqd = 24,
217 .doorbell_size = 4,
218 .ih_ring_entry_size = 4 * sizeof(uint32_t),
219 .event_interrupt_class = &event_interrupt_class_cik,
220 .num_of_watch_points = 4,
221 .mqd_size_aligned = MQD_SIZE_ALIGNED,
222 .supports_cwsr = true,
223 .needs_iommu_device = false,
224 .needs_pci_atomics = true,
225 .num_sdma_engines = 2,
226 .num_xgmi_sdma_engines = 0,
227 .num_sdma_queues_per_engine = 2,
228};
229
230static const struct kfd_device_info polaris10_vf_device_info = {
231 .asic_family = CHIP_POLARIS10,
232 .asic_name = "polaris10",
233 .max_pasid_bits = 16,
234 .max_no_of_hqd = 24,
235 .doorbell_size = 4,
236 .ih_ring_entry_size = 4 * sizeof(uint32_t),
237 .event_interrupt_class = &event_interrupt_class_cik,
238 .num_of_watch_points = 4,
239 .mqd_size_aligned = MQD_SIZE_ALIGNED,
240 .supports_cwsr = true,
241 .needs_iommu_device = false,
242 .needs_pci_atomics = false,
243 .num_sdma_engines = 2,
244 .num_xgmi_sdma_engines = 0,
245 .num_sdma_queues_per_engine = 2,
246};
247
248static const struct kfd_device_info polaris11_device_info = {
249 .asic_family = CHIP_POLARIS11,
250 .asic_name = "polaris11",
251 .max_pasid_bits = 16,
252 .max_no_of_hqd = 24,
253 .doorbell_size = 4,
254 .ih_ring_entry_size = 4 * sizeof(uint32_t),
255 .event_interrupt_class = &event_interrupt_class_cik,
256 .num_of_watch_points = 4,
257 .mqd_size_aligned = MQD_SIZE_ALIGNED,
258 .supports_cwsr = true,
259 .needs_iommu_device = false,
260 .needs_pci_atomics = true,
261 .num_sdma_engines = 2,
262 .num_xgmi_sdma_engines = 0,
263 .num_sdma_queues_per_engine = 2,
264};
265
266static const struct kfd_device_info polaris12_device_info = {
267 .asic_family = CHIP_POLARIS12,
268 .asic_name = "polaris12",
269 .max_pasid_bits = 16,
270 .max_no_of_hqd = 24,
271 .doorbell_size = 4,
272 .ih_ring_entry_size = 4 * sizeof(uint32_t),
273 .event_interrupt_class = &event_interrupt_class_cik,
274 .num_of_watch_points = 4,
275 .mqd_size_aligned = MQD_SIZE_ALIGNED,
276 .supports_cwsr = true,
277 .needs_iommu_device = false,
278 .needs_pci_atomics = true,
279 .num_sdma_engines = 2,
280 .num_xgmi_sdma_engines = 0,
281 .num_sdma_queues_per_engine = 2,
282};
283
284static const struct kfd_device_info vegam_device_info = {
285 .asic_family = CHIP_VEGAM,
286 .asic_name = "vegam",
287 .max_pasid_bits = 16,
288 .max_no_of_hqd = 24,
289 .doorbell_size = 4,
290 .ih_ring_entry_size = 4 * sizeof(uint32_t),
291 .event_interrupt_class = &event_interrupt_class_cik,
292 .num_of_watch_points = 4,
293 .mqd_size_aligned = MQD_SIZE_ALIGNED,
294 .supports_cwsr = true,
295 .needs_iommu_device = false,
296 .needs_pci_atomics = true,
297 .num_sdma_engines = 2,
298 .num_xgmi_sdma_engines = 0,
299 .num_sdma_queues_per_engine = 2,
300};
301
302static const struct kfd_device_info vega10_device_info = {
303 .asic_family = CHIP_VEGA10,
304 .asic_name = "vega10",
305 .max_pasid_bits = 16,
306 .max_no_of_hqd = 24,
307 .doorbell_size = 8,
308 .ih_ring_entry_size = 8 * sizeof(uint32_t),
309 .event_interrupt_class = &event_interrupt_class_v9,
310 .num_of_watch_points = 4,
311 .mqd_size_aligned = MQD_SIZE_ALIGNED,
312 .supports_cwsr = true,
313 .needs_iommu_device = false,
314 .needs_pci_atomics = false,
315 .num_sdma_engines = 2,
316 .num_xgmi_sdma_engines = 0,
317 .num_sdma_queues_per_engine = 2,
318};
319
320static const struct kfd_device_info vega10_vf_device_info = {
321 .asic_family = CHIP_VEGA10,
322 .asic_name = "vega10",
323 .max_pasid_bits = 16,
324 .max_no_of_hqd = 24,
325 .doorbell_size = 8,
326 .ih_ring_entry_size = 8 * sizeof(uint32_t),
327 .event_interrupt_class = &event_interrupt_class_v9,
328 .num_of_watch_points = 4,
329 .mqd_size_aligned = MQD_SIZE_ALIGNED,
330 .supports_cwsr = true,
331 .needs_iommu_device = false,
332 .needs_pci_atomics = false,
333 .num_sdma_engines = 2,
334 .num_xgmi_sdma_engines = 0,
335 .num_sdma_queues_per_engine = 2,
336};
337
338static const struct kfd_device_info vega12_device_info = {
339 .asic_family = CHIP_VEGA12,
340 .asic_name = "vega12",
341 .max_pasid_bits = 16,
342 .max_no_of_hqd = 24,
343 .doorbell_size = 8,
344 .ih_ring_entry_size = 8 * sizeof(uint32_t),
345 .event_interrupt_class = &event_interrupt_class_v9,
346 .num_of_watch_points = 4,
347 .mqd_size_aligned = MQD_SIZE_ALIGNED,
348 .supports_cwsr = true,
349 .needs_iommu_device = false,
350 .needs_pci_atomics = false,
351 .num_sdma_engines = 2,
352 .num_xgmi_sdma_engines = 0,
353 .num_sdma_queues_per_engine = 2,
354};
355
356static const struct kfd_device_info vega20_device_info = {
357 .asic_family = CHIP_VEGA20,
358 .asic_name = "vega20",
359 .max_pasid_bits = 16,
360 .max_no_of_hqd = 24,
361 .doorbell_size = 8,
362 .ih_ring_entry_size = 8 * sizeof(uint32_t),
363 .event_interrupt_class = &event_interrupt_class_v9,
364 .num_of_watch_points = 4,
365 .mqd_size_aligned = MQD_SIZE_ALIGNED,
366 .supports_cwsr = true,
367 .needs_iommu_device = false,
368 .needs_pci_atomics = false,
369 .num_sdma_engines = 2,
370 .num_xgmi_sdma_engines = 0,
371 .num_sdma_queues_per_engine = 8,
372};
373
374static const struct kfd_device_info arcturus_device_info = {
375 .asic_family = CHIP_ARCTURUS,
376 .asic_name = "arcturus",
377 .max_pasid_bits = 16,
378 .max_no_of_hqd = 24,
379 .doorbell_size = 8,
380 .ih_ring_entry_size = 8 * sizeof(uint32_t),
381 .event_interrupt_class = &event_interrupt_class_v9,
382 .num_of_watch_points = 4,
383 .mqd_size_aligned = MQD_SIZE_ALIGNED,
384 .supports_cwsr = true,
385 .needs_iommu_device = false,
386 .needs_pci_atomics = false,
387 .num_sdma_engines = 2,
388 .num_xgmi_sdma_engines = 6,
389 .num_sdma_queues_per_engine = 8,
390};
391
392static const struct kfd_device_info renoir_device_info = {
393 .asic_family = CHIP_RENOIR,
394 .asic_name = "renoir",
395 .max_pasid_bits = 16,
396 .max_no_of_hqd = 24,
397 .doorbell_size = 8,
398 .ih_ring_entry_size = 8 * sizeof(uint32_t),
399 .event_interrupt_class = &event_interrupt_class_v9,
400 .num_of_watch_points = 4,
401 .mqd_size_aligned = MQD_SIZE_ALIGNED,
402 .supports_cwsr = true,
403 .needs_iommu_device = false,
404 .needs_pci_atomics = false,
405 .num_sdma_engines = 1,
406 .num_xgmi_sdma_engines = 0,
407 .num_sdma_queues_per_engine = 2,
408};
409
410static const struct kfd_device_info navi10_device_info = {
411 .asic_family = CHIP_NAVI10,
412 .asic_name = "navi10",
413 .max_pasid_bits = 16,
414 .max_no_of_hqd = 24,
415 .doorbell_size = 8,
416 .ih_ring_entry_size = 8 * sizeof(uint32_t),
417 .event_interrupt_class = &event_interrupt_class_v9,
418 .num_of_watch_points = 4,
419 .mqd_size_aligned = MQD_SIZE_ALIGNED,
420 .needs_iommu_device = false,
421 .supports_cwsr = true,
422 .needs_pci_atomics = false,
423 .num_sdma_engines = 2,
424 .num_xgmi_sdma_engines = 0,
425 .num_sdma_queues_per_engine = 8,
426};
427
428static const struct kfd_device_info navi12_device_info = {
429 .asic_family = CHIP_NAVI12,
430 .asic_name = "navi12",
431 .max_pasid_bits = 16,
432 .max_no_of_hqd = 24,
433 .doorbell_size = 8,
434 .ih_ring_entry_size = 8 * sizeof(uint32_t),
435 .event_interrupt_class = &event_interrupt_class_v9,
436 .num_of_watch_points = 4,
437 .mqd_size_aligned = MQD_SIZE_ALIGNED,
438 .needs_iommu_device = false,
439 .supports_cwsr = true,
440 .needs_pci_atomics = false,
441 .num_sdma_engines = 2,
442 .num_xgmi_sdma_engines = 0,
443 .num_sdma_queues_per_engine = 8,
444};
445
446static const struct kfd_device_info navi14_device_info = {
447 .asic_family = CHIP_NAVI14,
448 .asic_name = "navi14",
449 .max_pasid_bits = 16,
450 .max_no_of_hqd = 24,
451 .doorbell_size = 8,
452 .ih_ring_entry_size = 8 * sizeof(uint32_t),
453 .event_interrupt_class = &event_interrupt_class_v9,
454 .num_of_watch_points = 4,
455 .mqd_size_aligned = MQD_SIZE_ALIGNED,
456 .needs_iommu_device = false,
457 .supports_cwsr = true,
458 .needs_pci_atomics = false,
459 .num_sdma_engines = 2,
460 .num_xgmi_sdma_engines = 0,
461 .num_sdma_queues_per_engine = 8,
462};
463
464static const struct kfd_device_info sienna_cichlid_device_info = {
465 .asic_family = CHIP_SIENNA_CICHLID,
466 .asic_name = "sienna_cichlid",
467 .max_pasid_bits = 16,
468 .max_no_of_hqd = 24,
469 .doorbell_size = 8,
470 .ih_ring_entry_size = 8 * sizeof(uint32_t),
471 .event_interrupt_class = &event_interrupt_class_v9,
472 .num_of_watch_points = 4,
473 .mqd_size_aligned = MQD_SIZE_ALIGNED,
474 .needs_iommu_device = false,
475 .supports_cwsr = true,
476 .needs_pci_atomics = false,
477 .num_sdma_engines = 4,
478 .num_xgmi_sdma_engines = 0,
479 .num_sdma_queues_per_engine = 8,
480};
481
482static const struct kfd_device_info navy_flounder_device_info = {
483 .asic_family = CHIP_NAVY_FLOUNDER,
484 .asic_name = "navy_flounder",
485 .max_pasid_bits = 16,
486 .max_no_of_hqd = 24,
487 .doorbell_size = 8,
488 .ih_ring_entry_size = 8 * sizeof(uint32_t),
489 .event_interrupt_class = &event_interrupt_class_v9,
490 .num_of_watch_points = 4,
491 .mqd_size_aligned = MQD_SIZE_ALIGNED,
492 .needs_iommu_device = false,
493 .supports_cwsr = true,
494 .needs_pci_atomics = false,
495 .num_sdma_engines = 2,
496 .num_xgmi_sdma_engines = 0,
497 .num_sdma_queues_per_engine = 8,
498};
499
500/* For each entry, [0] is regular and [1] is virtualisation device. */
501static const struct kfd_device_info *kfd_supported_devices[][2] = {
502#ifdef KFD_SUPPORT_IOMMU_V2
503 [CHIP_KAVERI] = {&kaveri_device_info, NULL},
504 [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
505 [CHIP_RAVEN] = {&raven_device_info, NULL},
506#endif
507 [CHIP_HAWAII] = {&hawaii_device_info, NULL},
508 [CHIP_TONGA] = {&tonga_device_info, NULL},
509 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
510 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
511 [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
512 [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
513 [CHIP_VEGAM] = {&vegam_device_info, NULL},
514 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
515 [CHIP_VEGA12] = {&vega12_device_info, NULL},
516 [CHIP_VEGA20] = {&vega20_device_info, NULL},
517 [CHIP_RENOIR] = {&renoir_device_info, NULL},
518 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
519 [CHIP_NAVI10] = {&navi10_device_info, NULL},
520 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
521 [CHIP_NAVI14] = {&navi14_device_info, NULL},
522 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
523 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
524};
525
526static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
527 unsigned int chunk_size);
528static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
529
530static int kfd_resume(struct kfd_dev *kfd);
531
532struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
533 struct pci_dev *pdev, unsigned int asic_type, bool vf)
534{
535 struct kfd_dev *kfd;
536 const struct kfd_device_info *device_info;
537 const struct kfd2kgd_calls *f2g;
538
539 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
540 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
541 dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
542 return NULL; /* asic_type out of range */
543 }
544
545 device_info = kfd_supported_devices[asic_type][vf];
546 f2g = kfd2kgd_funcs[asic_type];
547
548 if (!device_info || !f2g) {
549 dev_err(kfd_device, "%s %s not supported in kfd\n",
550 amdgpu_asic_name[asic_type], vf ? "VF" : "");
551 return NULL;
552 }
553
554 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
555 if (!kfd)
556 return NULL;
557
558 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
559 * 32 and 64-bit requests are possible and must be
560 * supported.
561 */
562 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
563 if (device_info->needs_pci_atomics &&
564 !kfd->pci_atomic_requested) {
565 dev_info(kfd_device,
566 "skipped device %x:%x, PCI rejects atomics\n",
567 pdev->vendor, pdev->device);
568 kfree(kfd);
569 return NULL;
570 }
571
572 kfd->kgd = kgd;
573 kfd->device_info = device_info;
574 kfd->pdev = pdev;
575 kfd->init_complete = false;
576 kfd->kfd2kgd = f2g;
577 atomic_set(&kfd->compute_profile, 0);
578
579 mutex_init(&kfd->doorbell_mutex);
580 memset(&kfd->doorbell_available_index, 0,
581 sizeof(kfd->doorbell_available_index));
582
583 atomic_set(&kfd->sram_ecc_flag, 0);
584
585 return kfd;
586}
587
588static void kfd_cwsr_init(struct kfd_dev *kfd)
589{
590 if (cwsr_enable && kfd->device_info->supports_cwsr) {
591 if (kfd->device_info->asic_family < CHIP_VEGA10) {
592 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
593 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
594 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
595 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
596 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
597 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
598 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
599 } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
600 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
601 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
602 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
603 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
604 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
605 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
606 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
607 } else {
608 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
609 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
610 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
611 }
612
613 kfd->cwsr_enabled = true;
614 }
615}
616
617static int kfd_gws_init(struct kfd_dev *kfd)
618{
619 int ret = 0;
620
621 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
622 return 0;
623
624 if (hws_gws_support
625 || (kfd->device_info->asic_family == CHIP_VEGA10
626 && kfd->mec2_fw_version >= 0x81b3)
627 || (kfd->device_info->asic_family >= CHIP_VEGA12
628 && kfd->device_info->asic_family <= CHIP_RAVEN
629 && kfd->mec2_fw_version >= 0x1b3)
630 || (kfd->device_info->asic_family == CHIP_ARCTURUS
631 && kfd->mec2_fw_version >= 0x30))
632 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd,
633 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws);
634
635 return ret;
636}
637
638static void kfd_smi_init(struct kfd_dev *dev) {
639 INIT_LIST_HEAD(&dev->smi_clients);
640 spin_lock_init(&dev->smi_lock);
641}
642
643bool kgd2kfd_device_init(struct kfd_dev *kfd,
644 struct drm_device *ddev,
645 const struct kgd2kfd_shared_resources *gpu_resources)
646{
647 unsigned int size;
648
649 kfd->ddev = ddev;
650 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
651 KGD_ENGINE_MEC1);
652 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
653 KGD_ENGINE_MEC2);
654 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
655 KGD_ENGINE_SDMA1);
656 kfd->shared_resources = *gpu_resources;
657
658 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
659 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
660 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
661 - kfd->vm_info.first_vmid_kfd + 1;
662
663 /* Verify module parameters regarding mapped process number*/
664 if ((hws_max_conc_proc < 0)
665 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
666 dev_err(kfd_device,
667 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
668 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
669 kfd->vm_info.vmid_num_kfd);
670 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
671 } else
672 kfd->max_proc_per_quantum = hws_max_conc_proc;
673
674 /* calculate max size of mqds needed for queues */
675 size = max_num_of_queues_per_device *
676 kfd->device_info->mqd_size_aligned;
677
678 /*
679 * calculate max size of runlist packet.
680 * There can be only 2 packets at once
681 */
682 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
683 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
684 + sizeof(struct pm4_mes_runlist)) * 2;
685
686 /* Add size of HIQ & DIQ */
687 size += KFD_KERNEL_QUEUE_SIZE * 2;
688
689 /* add another 512KB for all other allocations on gart (HPD, fences) */
690 size += 512 * 1024;
691
692 if (amdgpu_amdkfd_alloc_gtt_mem(
693 kfd->kgd, size, &kfd->gtt_mem,
694 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
695 false)) {
696 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
697 goto alloc_gtt_mem_failure;
698 }
699
700 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
701
702 /* Initialize GTT sa with 512 byte chunk size */
703 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
704 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
705 goto kfd_gtt_sa_init_error;
706 }
707
708 if (kfd_doorbell_init(kfd)) {
709 dev_err(kfd_device,
710 "Error initializing doorbell aperture\n");
711 goto kfd_doorbell_error;
712 }
713
714 if (kfd->kfd2kgd->get_hive_id)
715 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd);
716
717 if (kfd->kfd2kgd->get_unique_id)
718 kfd->unique_id = kfd->kfd2kgd->get_unique_id(kfd->kgd);
719
720 if (kfd_interrupt_init(kfd)) {
721 dev_err(kfd_device, "Error initializing interrupts\n");
722 goto kfd_interrupt_error;
723 }
724
725 kfd->dqm = device_queue_manager_init(kfd);
726 if (!kfd->dqm) {
727 dev_err(kfd_device, "Error initializing queue manager\n");
728 goto device_queue_manager_error;
729 }
730
731 /* If supported on this device, allocate global GWS that is shared
732 * by all KFD processes
733 */
734 if (kfd_gws_init(kfd)) {
735 dev_err(kfd_device, "Could not allocate %d gws\n",
736 amdgpu_amdkfd_get_num_gws(kfd->kgd));
737 goto gws_error;
738 }
739
740 if (kfd_iommu_device_init(kfd)) {
741 dev_err(kfd_device, "Error initializing iommuv2\n");
742 goto device_iommu_error;
743 }
744
745 kfd_cwsr_init(kfd);
746
747 if (kfd_resume(kfd))
748 goto kfd_resume_error;
749
750 kfd->dbgmgr = NULL;
751
752 if (kfd_topology_add_device(kfd)) {
753 dev_err(kfd_device, "Error adding device to topology\n");
754 goto kfd_topology_add_device_error;
755 }
756
757 kfd_smi_init(kfd);
758
759 kfd->init_complete = true;
760 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
761 kfd->pdev->device);
762
763 pr_debug("Starting kfd with the following scheduling policy %d\n",
764 kfd->dqm->sched_policy);
765
766 goto out;
767
768kfd_topology_add_device_error:
769kfd_resume_error:
770device_iommu_error:
771gws_error:
772 device_queue_manager_uninit(kfd->dqm);
773device_queue_manager_error:
774 kfd_interrupt_exit(kfd);
775kfd_interrupt_error:
776 kfd_doorbell_fini(kfd);
777kfd_doorbell_error:
778 kfd_gtt_sa_fini(kfd);
779kfd_gtt_sa_init_error:
780 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
781alloc_gtt_mem_failure:
782 if (kfd->gws)
783 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
784 dev_err(kfd_device,
785 "device %x:%x NOT added due to errors\n",
786 kfd->pdev->vendor, kfd->pdev->device);
787out:
788 return kfd->init_complete;
789}
790
791void kgd2kfd_device_exit(struct kfd_dev *kfd)
792{
793 if (kfd->init_complete) {
794 kgd2kfd_suspend(kfd, false);
795 device_queue_manager_uninit(kfd->dqm);
796 kfd_interrupt_exit(kfd);
797 kfd_topology_remove_device(kfd);
798 kfd_doorbell_fini(kfd);
799 kfd_gtt_sa_fini(kfd);
800 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
801 if (kfd->gws)
802 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
803 }
804
805 kfree(kfd);
806}
807
808int kgd2kfd_pre_reset(struct kfd_dev *kfd)
809{
810 if (!kfd->init_complete)
811 return 0;
812
813 kfd->dqm->ops.pre_reset(kfd->dqm);
814
815 kgd2kfd_suspend(kfd, false);
816
817 kfd_signal_reset_event(kfd);
818 return 0;
819}
820
821/*
822 * Fix me. KFD won't be able to resume existing process for now.
823 * We will keep all existing process in a evicted state and
824 * wait the process to be terminated.
825 */
826
827int kgd2kfd_post_reset(struct kfd_dev *kfd)
828{
829 int ret;
830
831 if (!kfd->init_complete)
832 return 0;
833
834 ret = kfd_resume(kfd);
835 if (ret)
836 return ret;
837 atomic_dec(&kfd_locked);
838
839 atomic_set(&kfd->sram_ecc_flag, 0);
840
841 return 0;
842}
843
844bool kfd_is_locked(void)
845{
846 return (atomic_read(&kfd_locked) > 0);
847}
848
849void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
850{
851 if (!kfd->init_complete)
852 return;
853
854 /* for runtime suspend, skip locking kfd */
855 if (!run_pm) {
856 /* For first KFD device suspend all the KFD processes */
857 if (atomic_inc_return(&kfd_locked) == 1)
858 kfd_suspend_all_processes();
859 }
860
861 kfd->dqm->ops.stop(kfd->dqm);
862 kfd_iommu_suspend(kfd);
863}
864
865int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
866{
867 int ret, count;
868
869 if (!kfd->init_complete)
870 return 0;
871
872 ret = kfd_resume(kfd);
873 if (ret)
874 return ret;
875
876 /* for runtime resume, skip unlocking kfd */
877 if (!run_pm) {
878 count = atomic_dec_return(&kfd_locked);
879 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
880 if (count == 0)
881 ret = kfd_resume_all_processes();
882 }
883
884 return ret;
885}
886
887static int kfd_resume(struct kfd_dev *kfd)
888{
889 int err = 0;
890
891 err = kfd_iommu_resume(kfd);
892 if (err) {
893 dev_err(kfd_device,
894 "Failed to resume IOMMU for device %x:%x\n",
895 kfd->pdev->vendor, kfd->pdev->device);
896 return err;
897 }
898
899 err = kfd->dqm->ops.start(kfd->dqm);
900 if (err) {
901 dev_err(kfd_device,
902 "Error starting queue manager for device %x:%x\n",
903 kfd->pdev->vendor, kfd->pdev->device);
904 goto dqm_start_error;
905 }
906
907 return err;
908
909dqm_start_error:
910 kfd_iommu_suspend(kfd);
911 return err;
912}
913
914static inline void kfd_queue_work(struct workqueue_struct *wq,
915 struct work_struct *work)
916{
917 int cpu, new_cpu;
918
919 cpu = new_cpu = smp_processor_id();
920 do {
921 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
922 if (cpu_to_node(new_cpu) == numa_node_id())
923 break;
924 } while (cpu != new_cpu);
925
926 queue_work_on(new_cpu, wq, work);
927}
928
929/* This is called directly from KGD at ISR. */
930void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
931{
932 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
933 bool is_patched = false;
934 unsigned long flags;
935
936 if (!kfd->init_complete)
937 return;
938
939 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
940 dev_err_once(kfd_device, "Ring entry too small\n");
941 return;
942 }
943
944 spin_lock_irqsave(&kfd->interrupt_lock, flags);
945
946 if (kfd->interrupts_active
947 && interrupt_is_wanted(kfd, ih_ring_entry,
948 patched_ihre, &is_patched)
949 && enqueue_ih_ring_entry(kfd,
950 is_patched ? patched_ihre : ih_ring_entry))
951 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
952
953 spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
954}
955
956int kgd2kfd_quiesce_mm(struct mm_struct *mm)
957{
958 struct kfd_process *p;
959 int r;
960
961 /* Because we are called from arbitrary context (workqueue) as opposed
962 * to process context, kfd_process could attempt to exit while we are
963 * running so the lookup function increments the process ref count.
964 */
965 p = kfd_lookup_process_by_mm(mm);
966 if (!p)
967 return -ESRCH;
968
969 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
970 r = kfd_process_evict_queues(p);
971
972 kfd_unref_process(p);
973 return r;
974}
975
976int kgd2kfd_resume_mm(struct mm_struct *mm)
977{
978 struct kfd_process *p;
979 int r;
980
981 /* Because we are called from arbitrary context (workqueue) as opposed
982 * to process context, kfd_process could attempt to exit while we are
983 * running so the lookup function increments the process ref count.
984 */
985 p = kfd_lookup_process_by_mm(mm);
986 if (!p)
987 return -ESRCH;
988
989 r = kfd_process_restore_queues(p);
990
991 kfd_unref_process(p);
992 return r;
993}
994
995/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
996 * prepare for safe eviction of KFD BOs that belong to the specified
997 * process.
998 *
999 * @mm: mm_struct that identifies the specified KFD process
1000 * @fence: eviction fence attached to KFD process BOs
1001 *
1002 */
1003int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1004 struct dma_fence *fence)
1005{
1006 struct kfd_process *p;
1007 unsigned long active_time;
1008 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1009
1010 if (!fence)
1011 return -EINVAL;
1012
1013 if (dma_fence_is_signaled(fence))
1014 return 0;
1015
1016 p = kfd_lookup_process_by_mm(mm);
1017 if (!p)
1018 return -ENODEV;
1019
1020 if (fence->seqno == p->last_eviction_seqno)
1021 goto out;
1022
1023 p->last_eviction_seqno = fence->seqno;
1024
1025 /* Avoid KFD process starvation. Wait for at least
1026 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1027 */
1028 active_time = get_jiffies_64() - p->last_restore_timestamp;
1029 if (delay_jiffies > active_time)
1030 delay_jiffies -= active_time;
1031 else
1032 delay_jiffies = 0;
1033
1034 /* During process initialization eviction_work.dwork is initialized
1035 * to kfd_evict_bo_worker
1036 */
1037 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1038 p->lead_thread->pid, delay_jiffies);
1039 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1040out:
1041 kfd_unref_process(p);
1042 return 0;
1043}
1044
1045static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1046 unsigned int chunk_size)
1047{
1048 unsigned int num_of_longs;
1049
1050 if (WARN_ON(buf_size < chunk_size))
1051 return -EINVAL;
1052 if (WARN_ON(buf_size == 0))
1053 return -EINVAL;
1054 if (WARN_ON(chunk_size == 0))
1055 return -EINVAL;
1056
1057 kfd->gtt_sa_chunk_size = chunk_size;
1058 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1059
1060 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
1061 BITS_PER_LONG;
1062
1063 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
1064
1065 if (!kfd->gtt_sa_bitmap)
1066 return -ENOMEM;
1067
1068 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1069 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1070
1071 mutex_init(&kfd->gtt_sa_lock);
1072
1073 return 0;
1074
1075}
1076
1077static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1078{
1079 mutex_destroy(&kfd->gtt_sa_lock);
1080 kfree(kfd->gtt_sa_bitmap);
1081}
1082
1083static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1084 unsigned int bit_num,
1085 unsigned int chunk_size)
1086{
1087 return start_addr + bit_num * chunk_size;
1088}
1089
1090static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1091 unsigned int bit_num,
1092 unsigned int chunk_size)
1093{
1094 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1095}
1096
1097int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1098 struct kfd_mem_obj **mem_obj)
1099{
1100 unsigned int found, start_search, cur_size;
1101
1102 if (size == 0)
1103 return -EINVAL;
1104
1105 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1106 return -ENOMEM;
1107
1108 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1109 if (!(*mem_obj))
1110 return -ENOMEM;
1111
1112 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1113
1114 start_search = 0;
1115
1116 mutex_lock(&kfd->gtt_sa_lock);
1117
1118kfd_gtt_restart_search:
1119 /* Find the first chunk that is free */
1120 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1121 kfd->gtt_sa_num_of_chunks,
1122 start_search);
1123
1124 pr_debug("Found = %d\n", found);
1125
1126 /* If there wasn't any free chunk, bail out */
1127 if (found == kfd->gtt_sa_num_of_chunks)
1128 goto kfd_gtt_no_free_chunk;
1129
1130 /* Update fields of mem_obj */
1131 (*mem_obj)->range_start = found;
1132 (*mem_obj)->range_end = found;
1133 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1134 kfd->gtt_start_gpu_addr,
1135 found,
1136 kfd->gtt_sa_chunk_size);
1137 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1138 kfd->gtt_start_cpu_ptr,
1139 found,
1140 kfd->gtt_sa_chunk_size);
1141
1142 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1143 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1144
1145 /* If we need only one chunk, mark it as allocated and get out */
1146 if (size <= kfd->gtt_sa_chunk_size) {
1147 pr_debug("Single bit\n");
1148 set_bit(found, kfd->gtt_sa_bitmap);
1149 goto kfd_gtt_out;
1150 }
1151
1152 /* Otherwise, try to see if we have enough contiguous chunks */
1153 cur_size = size - kfd->gtt_sa_chunk_size;
1154 do {
1155 (*mem_obj)->range_end =
1156 find_next_zero_bit(kfd->gtt_sa_bitmap,
1157 kfd->gtt_sa_num_of_chunks, ++found);
1158 /*
1159 * If next free chunk is not contiguous than we need to
1160 * restart our search from the last free chunk we found (which
1161 * wasn't contiguous to the previous ones
1162 */
1163 if ((*mem_obj)->range_end != found) {
1164 start_search = found;
1165 goto kfd_gtt_restart_search;
1166 }
1167
1168 /*
1169 * If we reached end of buffer, bail out with error
1170 */
1171 if (found == kfd->gtt_sa_num_of_chunks)
1172 goto kfd_gtt_no_free_chunk;
1173
1174 /* Check if we don't need another chunk */
1175 if (cur_size <= kfd->gtt_sa_chunk_size)
1176 cur_size = 0;
1177 else
1178 cur_size -= kfd->gtt_sa_chunk_size;
1179
1180 } while (cur_size > 0);
1181
1182 pr_debug("range_start = %d, range_end = %d\n",
1183 (*mem_obj)->range_start, (*mem_obj)->range_end);
1184
1185 /* Mark the chunks as allocated */
1186 for (found = (*mem_obj)->range_start;
1187 found <= (*mem_obj)->range_end;
1188 found++)
1189 set_bit(found, kfd->gtt_sa_bitmap);
1190
1191kfd_gtt_out:
1192 mutex_unlock(&kfd->gtt_sa_lock);
1193 return 0;
1194
1195kfd_gtt_no_free_chunk:
1196 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1197 mutex_unlock(&kfd->gtt_sa_lock);
1198 kfree(*mem_obj);
1199 return -ENOMEM;
1200}
1201
1202int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1203{
1204 unsigned int bit;
1205
1206 /* Act like kfree when trying to free a NULL object */
1207 if (!mem_obj)
1208 return 0;
1209
1210 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1211 mem_obj, mem_obj->range_start, mem_obj->range_end);
1212
1213 mutex_lock(&kfd->gtt_sa_lock);
1214
1215 /* Mark the chunks as free */
1216 for (bit = mem_obj->range_start;
1217 bit <= mem_obj->range_end;
1218 bit++)
1219 clear_bit(bit, kfd->gtt_sa_bitmap);
1220
1221 mutex_unlock(&kfd->gtt_sa_lock);
1222
1223 kfree(mem_obj);
1224 return 0;
1225}
1226
1227void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1228{
1229 if (kfd)
1230 atomic_inc(&kfd->sram_ecc_flag);
1231}
1232
1233void kfd_inc_compute_active(struct kfd_dev *kfd)
1234{
1235 if (atomic_inc_return(&kfd->compute_profile) == 1)
1236 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false);
1237}
1238
1239void kfd_dec_compute_active(struct kfd_dev *kfd)
1240{
1241 int count = atomic_dec_return(&kfd->compute_profile);
1242
1243 if (count == 0)
1244 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true);
1245 WARN_ONCE(count < 0, "Compute profile ref. count error");
1246}
1247
1248#if defined(CONFIG_DEBUG_FS)
1249
1250/* This function will send a package to HIQ to hang the HWS
1251 * which will trigger a GPU reset and bring the HWS back to normal state
1252 */
1253int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1254{
1255 int r = 0;
1256
1257 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1258 pr_err("HWS is not enabled");
1259 return -EINVAL;
1260 }
1261
1262 r = pm_debugfs_hang_hws(&dev->dqm->packets);
1263 if (!r)
1264 r = dqm_debugfs_execute_queues(dev->dqm);
1265
1266 return r;
1267}
1268
1269#endif
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/amd-iommu.h>
24#include <linux/bsearch.h>
25#include <linux/pci.h>
26#include <linux/slab.h>
27#include "kfd_priv.h"
28#include "kfd_device_queue_manager.h"
29#include "kfd_pm4_headers.h"
30
31#define MQD_SIZE_ALIGNED 768
32
33static const struct kfd_device_info kaveri_device_info = {
34 .asic_family = CHIP_KAVERI,
35 .max_pasid_bits = 16,
36 /* max num of queues for KV.TODO should be a dynamic value */
37 .max_no_of_hqd = 24,
38 .ih_ring_entry_size = 4 * sizeof(uint32_t),
39 .event_interrupt_class = &event_interrupt_class_cik,
40 .num_of_watch_points = 4,
41 .mqd_size_aligned = MQD_SIZE_ALIGNED
42};
43
44static const struct kfd_device_info carrizo_device_info = {
45 .asic_family = CHIP_CARRIZO,
46 .max_pasid_bits = 16,
47 /* max num of queues for CZ.TODO should be a dynamic value */
48 .max_no_of_hqd = 24,
49 .ih_ring_entry_size = 4 * sizeof(uint32_t),
50 .event_interrupt_class = &event_interrupt_class_cik,
51 .num_of_watch_points = 4,
52 .mqd_size_aligned = MQD_SIZE_ALIGNED
53};
54
55struct kfd_deviceid {
56 unsigned short did;
57 const struct kfd_device_info *device_info;
58};
59
60/* Please keep this sorted by increasing device id. */
61static const struct kfd_deviceid supported_devices[] = {
62 { 0x1304, &kaveri_device_info }, /* Kaveri */
63 { 0x1305, &kaveri_device_info }, /* Kaveri */
64 { 0x1306, &kaveri_device_info }, /* Kaveri */
65 { 0x1307, &kaveri_device_info }, /* Kaveri */
66 { 0x1309, &kaveri_device_info }, /* Kaveri */
67 { 0x130A, &kaveri_device_info }, /* Kaveri */
68 { 0x130B, &kaveri_device_info }, /* Kaveri */
69 { 0x130C, &kaveri_device_info }, /* Kaveri */
70 { 0x130D, &kaveri_device_info }, /* Kaveri */
71 { 0x130E, &kaveri_device_info }, /* Kaveri */
72 { 0x130F, &kaveri_device_info }, /* Kaveri */
73 { 0x1310, &kaveri_device_info }, /* Kaveri */
74 { 0x1311, &kaveri_device_info }, /* Kaveri */
75 { 0x1312, &kaveri_device_info }, /* Kaveri */
76 { 0x1313, &kaveri_device_info }, /* Kaveri */
77 { 0x1315, &kaveri_device_info }, /* Kaveri */
78 { 0x1316, &kaveri_device_info }, /* Kaveri */
79 { 0x1317, &kaveri_device_info }, /* Kaveri */
80 { 0x1318, &kaveri_device_info }, /* Kaveri */
81 { 0x131B, &kaveri_device_info }, /* Kaveri */
82 { 0x131C, &kaveri_device_info }, /* Kaveri */
83 { 0x131D, &kaveri_device_info }, /* Kaveri */
84 { 0x9870, &carrizo_device_info }, /* Carrizo */
85 { 0x9874, &carrizo_device_info }, /* Carrizo */
86 { 0x9875, &carrizo_device_info }, /* Carrizo */
87 { 0x9876, &carrizo_device_info }, /* Carrizo */
88 { 0x9877, &carrizo_device_info } /* Carrizo */
89};
90
91static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
92 unsigned int chunk_size);
93static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
94
95static const struct kfd_device_info *lookup_device_info(unsigned short did)
96{
97 size_t i;
98
99 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
100 if (supported_devices[i].did == did) {
101 BUG_ON(supported_devices[i].device_info == NULL);
102 return supported_devices[i].device_info;
103 }
104 }
105
106 return NULL;
107}
108
109struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
110 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
111{
112 struct kfd_dev *kfd;
113
114 const struct kfd_device_info *device_info =
115 lookup_device_info(pdev->device);
116
117 if (!device_info)
118 return NULL;
119
120 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
121 if (!kfd)
122 return NULL;
123
124 kfd->kgd = kgd;
125 kfd->device_info = device_info;
126 kfd->pdev = pdev;
127 kfd->init_complete = false;
128 kfd->kfd2kgd = f2g;
129
130 mutex_init(&kfd->doorbell_mutex);
131 memset(&kfd->doorbell_available_index, 0,
132 sizeof(kfd->doorbell_available_index));
133
134 return kfd;
135}
136
137static bool device_iommu_pasid_init(struct kfd_dev *kfd)
138{
139 const u32 required_iommu_flags = AMD_IOMMU_DEVICE_FLAG_ATS_SUP |
140 AMD_IOMMU_DEVICE_FLAG_PRI_SUP |
141 AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
142
143 struct amd_iommu_device_info iommu_info;
144 unsigned int pasid_limit;
145 int err;
146
147 err = amd_iommu_device_info(kfd->pdev, &iommu_info);
148 if (err < 0) {
149 dev_err(kfd_device,
150 "error getting iommu info. is the iommu enabled?\n");
151 return false;
152 }
153
154 if ((iommu_info.flags & required_iommu_flags) != required_iommu_flags) {
155 dev_err(kfd_device, "error required iommu flags ats(%i), pri(%i), pasid(%i)\n",
156 (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP) != 0,
157 (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) != 0,
158 (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) != 0);
159 return false;
160 }
161
162 pasid_limit = min_t(unsigned int,
163 (unsigned int)1 << kfd->device_info->max_pasid_bits,
164 iommu_info.max_pasids);
165 /*
166 * last pasid is used for kernel queues doorbells
167 * in the future the last pasid might be used for a kernel thread.
168 */
169 pasid_limit = min_t(unsigned int,
170 pasid_limit,
171 kfd->doorbell_process_limit - 1);
172
173 err = amd_iommu_init_device(kfd->pdev, pasid_limit);
174 if (err < 0) {
175 dev_err(kfd_device, "error initializing iommu device\n");
176 return false;
177 }
178
179 if (!kfd_set_pasid_limit(pasid_limit)) {
180 dev_err(kfd_device, "error setting pasid limit\n");
181 amd_iommu_free_device(kfd->pdev);
182 return false;
183 }
184
185 return true;
186}
187
188static void iommu_pasid_shutdown_callback(struct pci_dev *pdev, int pasid)
189{
190 struct kfd_dev *dev = kfd_device_by_pci_dev(pdev);
191
192 if (dev)
193 kfd_unbind_process_from_device(dev, pasid);
194}
195
196/*
197 * This function called by IOMMU driver on PPR failure
198 */
199static int iommu_invalid_ppr_cb(struct pci_dev *pdev, int pasid,
200 unsigned long address, u16 flags)
201{
202 struct kfd_dev *dev;
203
204 dev_warn(kfd_device,
205 "Invalid PPR device %x:%x.%x pasid %d address 0x%lX flags 0x%X",
206 PCI_BUS_NUM(pdev->devfn),
207 PCI_SLOT(pdev->devfn),
208 PCI_FUNC(pdev->devfn),
209 pasid,
210 address,
211 flags);
212
213 dev = kfd_device_by_pci_dev(pdev);
214 BUG_ON(dev == NULL);
215
216 kfd_signal_iommu_event(dev, pasid, address,
217 flags & PPR_FAULT_WRITE, flags & PPR_FAULT_EXEC);
218
219 return AMD_IOMMU_INV_PRI_RSP_INVALID;
220}
221
222bool kgd2kfd_device_init(struct kfd_dev *kfd,
223 const struct kgd2kfd_shared_resources *gpu_resources)
224{
225 unsigned int size;
226
227 kfd->shared_resources = *gpu_resources;
228
229 /* calculate max size of mqds needed for queues */
230 size = max_num_of_queues_per_device *
231 kfd->device_info->mqd_size_aligned;
232
233 /*
234 * calculate max size of runlist packet.
235 * There can be only 2 packets at once
236 */
237 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_map_process) +
238 max_num_of_queues_per_device *
239 sizeof(struct pm4_map_queues) + sizeof(struct pm4_runlist)) * 2;
240
241 /* Add size of HIQ & DIQ */
242 size += KFD_KERNEL_QUEUE_SIZE * 2;
243
244 /* add another 512KB for all other allocations on gart (HPD, fences) */
245 size += 512 * 1024;
246
247 if (kfd->kfd2kgd->init_gtt_mem_allocation(
248 kfd->kgd, size, &kfd->gtt_mem,
249 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr)){
250 dev_err(kfd_device,
251 "Could not allocate %d bytes for device (%x:%x)\n",
252 size, kfd->pdev->vendor, kfd->pdev->device);
253 goto out;
254 }
255
256 dev_info(kfd_device,
257 "Allocated %d bytes on gart for device(%x:%x)\n",
258 size, kfd->pdev->vendor, kfd->pdev->device);
259
260 /* Initialize GTT sa with 512 byte chunk size */
261 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
262 dev_err(kfd_device,
263 "Error initializing gtt sub-allocator\n");
264 goto kfd_gtt_sa_init_error;
265 }
266
267 kfd_doorbell_init(kfd);
268
269 if (kfd_topology_add_device(kfd) != 0) {
270 dev_err(kfd_device,
271 "Error adding device (%x:%x) to topology\n",
272 kfd->pdev->vendor, kfd->pdev->device);
273 goto kfd_topology_add_device_error;
274 }
275
276 if (kfd_interrupt_init(kfd)) {
277 dev_err(kfd_device,
278 "Error initializing interrupts for device (%x:%x)\n",
279 kfd->pdev->vendor, kfd->pdev->device);
280 goto kfd_interrupt_error;
281 }
282
283 if (!device_iommu_pasid_init(kfd)) {
284 dev_err(kfd_device,
285 "Error initializing iommuv2 for device (%x:%x)\n",
286 kfd->pdev->vendor, kfd->pdev->device);
287 goto device_iommu_pasid_error;
288 }
289 amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
290 iommu_pasid_shutdown_callback);
291 amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
292
293 kfd->dqm = device_queue_manager_init(kfd);
294 if (!kfd->dqm) {
295 dev_err(kfd_device,
296 "Error initializing queue manager for device (%x:%x)\n",
297 kfd->pdev->vendor, kfd->pdev->device);
298 goto device_queue_manager_error;
299 }
300
301 if (kfd->dqm->ops.start(kfd->dqm) != 0) {
302 dev_err(kfd_device,
303 "Error starting queuen manager for device (%x:%x)\n",
304 kfd->pdev->vendor, kfd->pdev->device);
305 goto dqm_start_error;
306 }
307
308 kfd->dbgmgr = NULL;
309
310 kfd->init_complete = true;
311 dev_info(kfd_device, "added device (%x:%x)\n", kfd->pdev->vendor,
312 kfd->pdev->device);
313
314 pr_debug("kfd: Starting kfd with the following scheduling policy %d\n",
315 sched_policy);
316
317 goto out;
318
319dqm_start_error:
320 device_queue_manager_uninit(kfd->dqm);
321device_queue_manager_error:
322 amd_iommu_free_device(kfd->pdev);
323device_iommu_pasid_error:
324 kfd_interrupt_exit(kfd);
325kfd_interrupt_error:
326 kfd_topology_remove_device(kfd);
327kfd_topology_add_device_error:
328 kfd_gtt_sa_fini(kfd);
329kfd_gtt_sa_init_error:
330 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem);
331 dev_err(kfd_device,
332 "device (%x:%x) NOT added due to errors\n",
333 kfd->pdev->vendor, kfd->pdev->device);
334out:
335 return kfd->init_complete;
336}
337
338void kgd2kfd_device_exit(struct kfd_dev *kfd)
339{
340 if (kfd->init_complete) {
341 device_queue_manager_uninit(kfd->dqm);
342 amd_iommu_free_device(kfd->pdev);
343 kfd_interrupt_exit(kfd);
344 kfd_topology_remove_device(kfd);
345 kfd_gtt_sa_fini(kfd);
346 kfd->kfd2kgd->free_gtt_mem(kfd->kgd, kfd->gtt_mem);
347 }
348
349 kfree(kfd);
350}
351
352void kgd2kfd_suspend(struct kfd_dev *kfd)
353{
354 BUG_ON(kfd == NULL);
355
356 if (kfd->init_complete) {
357 kfd->dqm->ops.stop(kfd->dqm);
358 amd_iommu_set_invalidate_ctx_cb(kfd->pdev, NULL);
359 amd_iommu_set_invalid_ppr_cb(kfd->pdev, NULL);
360 amd_iommu_free_device(kfd->pdev);
361 }
362}
363
364int kgd2kfd_resume(struct kfd_dev *kfd)
365{
366 unsigned int pasid_limit;
367 int err;
368
369 BUG_ON(kfd == NULL);
370
371 pasid_limit = kfd_get_pasid_limit();
372
373 if (kfd->init_complete) {
374 err = amd_iommu_init_device(kfd->pdev, pasid_limit);
375 if (err < 0)
376 return -ENXIO;
377 amd_iommu_set_invalidate_ctx_cb(kfd->pdev,
378 iommu_pasid_shutdown_callback);
379 amd_iommu_set_invalid_ppr_cb(kfd->pdev, iommu_invalid_ppr_cb);
380 kfd->dqm->ops.start(kfd->dqm);
381 }
382
383 return 0;
384}
385
386/* This is called directly from KGD at ISR. */
387void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
388{
389 if (!kfd->init_complete)
390 return;
391
392 spin_lock(&kfd->interrupt_lock);
393
394 if (kfd->interrupts_active
395 && interrupt_is_wanted(kfd, ih_ring_entry)
396 && enqueue_ih_ring_entry(kfd, ih_ring_entry))
397 schedule_work(&kfd->interrupt_work);
398
399 spin_unlock(&kfd->interrupt_lock);
400}
401
402static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
403 unsigned int chunk_size)
404{
405 unsigned int num_of_bits;
406
407 BUG_ON(!kfd);
408 BUG_ON(!kfd->gtt_mem);
409 BUG_ON(buf_size < chunk_size);
410 BUG_ON(buf_size == 0);
411 BUG_ON(chunk_size == 0);
412
413 kfd->gtt_sa_chunk_size = chunk_size;
414 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
415
416 num_of_bits = kfd->gtt_sa_num_of_chunks / BITS_PER_BYTE;
417 BUG_ON(num_of_bits == 0);
418
419 kfd->gtt_sa_bitmap = kzalloc(num_of_bits, GFP_KERNEL);
420
421 if (!kfd->gtt_sa_bitmap)
422 return -ENOMEM;
423
424 pr_debug("kfd: gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
425 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
426
427 mutex_init(&kfd->gtt_sa_lock);
428
429 return 0;
430
431}
432
433static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
434{
435 mutex_destroy(&kfd->gtt_sa_lock);
436 kfree(kfd->gtt_sa_bitmap);
437}
438
439static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
440 unsigned int bit_num,
441 unsigned int chunk_size)
442{
443 return start_addr + bit_num * chunk_size;
444}
445
446static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
447 unsigned int bit_num,
448 unsigned int chunk_size)
449{
450 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
451}
452
453int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
454 struct kfd_mem_obj **mem_obj)
455{
456 unsigned int found, start_search, cur_size;
457
458 BUG_ON(!kfd);
459
460 if (size == 0)
461 return -EINVAL;
462
463 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
464 return -ENOMEM;
465
466 *mem_obj = kmalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
467 if ((*mem_obj) == NULL)
468 return -ENOMEM;
469
470 pr_debug("kfd: allocated mem_obj = %p for size = %d\n", *mem_obj, size);
471
472 start_search = 0;
473
474 mutex_lock(&kfd->gtt_sa_lock);
475
476kfd_gtt_restart_search:
477 /* Find the first chunk that is free */
478 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
479 kfd->gtt_sa_num_of_chunks,
480 start_search);
481
482 pr_debug("kfd: found = %d\n", found);
483
484 /* If there wasn't any free chunk, bail out */
485 if (found == kfd->gtt_sa_num_of_chunks)
486 goto kfd_gtt_no_free_chunk;
487
488 /* Update fields of mem_obj */
489 (*mem_obj)->range_start = found;
490 (*mem_obj)->range_end = found;
491 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
492 kfd->gtt_start_gpu_addr,
493 found,
494 kfd->gtt_sa_chunk_size);
495 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
496 kfd->gtt_start_cpu_ptr,
497 found,
498 kfd->gtt_sa_chunk_size);
499
500 pr_debug("kfd: gpu_addr = %p, cpu_addr = %p\n",
501 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
502
503 /* If we need only one chunk, mark it as allocated and get out */
504 if (size <= kfd->gtt_sa_chunk_size) {
505 pr_debug("kfd: single bit\n");
506 set_bit(found, kfd->gtt_sa_bitmap);
507 goto kfd_gtt_out;
508 }
509
510 /* Otherwise, try to see if we have enough contiguous chunks */
511 cur_size = size - kfd->gtt_sa_chunk_size;
512 do {
513 (*mem_obj)->range_end =
514 find_next_zero_bit(kfd->gtt_sa_bitmap,
515 kfd->gtt_sa_num_of_chunks, ++found);
516 /*
517 * If next free chunk is not contiguous than we need to
518 * restart our search from the last free chunk we found (which
519 * wasn't contiguous to the previous ones
520 */
521 if ((*mem_obj)->range_end != found) {
522 start_search = found;
523 goto kfd_gtt_restart_search;
524 }
525
526 /*
527 * If we reached end of buffer, bail out with error
528 */
529 if (found == kfd->gtt_sa_num_of_chunks)
530 goto kfd_gtt_no_free_chunk;
531
532 /* Check if we don't need another chunk */
533 if (cur_size <= kfd->gtt_sa_chunk_size)
534 cur_size = 0;
535 else
536 cur_size -= kfd->gtt_sa_chunk_size;
537
538 } while (cur_size > 0);
539
540 pr_debug("kfd: range_start = %d, range_end = %d\n",
541 (*mem_obj)->range_start, (*mem_obj)->range_end);
542
543 /* Mark the chunks as allocated */
544 for (found = (*mem_obj)->range_start;
545 found <= (*mem_obj)->range_end;
546 found++)
547 set_bit(found, kfd->gtt_sa_bitmap);
548
549kfd_gtt_out:
550 mutex_unlock(&kfd->gtt_sa_lock);
551 return 0;
552
553kfd_gtt_no_free_chunk:
554 pr_debug("kfd: allocation failed with mem_obj = %p\n", mem_obj);
555 mutex_unlock(&kfd->gtt_sa_lock);
556 kfree(mem_obj);
557 return -ENOMEM;
558}
559
560int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
561{
562 unsigned int bit;
563
564 BUG_ON(!kfd);
565
566 /* Act like kfree when trying to free a NULL object */
567 if (!mem_obj)
568 return 0;
569
570 pr_debug("kfd: free mem_obj = %p, range_start = %d, range_end = %d\n",
571 mem_obj, mem_obj->range_start, mem_obj->range_end);
572
573 mutex_lock(&kfd->gtt_sa_lock);
574
575 /* Mark the chunks as free */
576 for (bit = mem_obj->range_start;
577 bit <= mem_obj->range_end;
578 bit++)
579 clear_bit(bit, kfd->gtt_sa_bitmap);
580
581 mutex_unlock(&kfd->gtt_sa_lock);
582
583 kfree(mem_obj);
584 return 0;
585}