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1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */
3
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/pci.h>
7#include <linux/ptp_classify.h>
8
9#include "igb.h"
10
11#define INCVALUE_MASK 0x7fffffff
12#define ISGN 0x80000000
13
14/* The 82580 timesync updates the system timer every 8ns by 8ns,
15 * and this update value cannot be reprogrammed.
16 *
17 * Neither the 82576 nor the 82580 offer registers wide enough to hold
18 * nanoseconds time values for very long. For the 82580, SYSTIM always
19 * counts nanoseconds, but the upper 24 bits are not available. The
20 * frequency is adjusted by changing the 32 bit fractional nanoseconds
21 * register, TIMINCA.
22 *
23 * For the 82576, the SYSTIM register time unit is affect by the
24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
25 * field are needed to provide the nominal 16 nanosecond period,
26 * leaving 19 bits for fractional nanoseconds.
27 *
28 * We scale the NIC clock cycle by a large factor so that relatively
29 * small clock corrections can be added or subtracted at each clock
30 * tick. The drawbacks of a large factor are a) that the clock
31 * register overflows more quickly (not such a big deal) and b) that
32 * the increment per tick has to fit into 24 bits. As a result we
33 * need to use a shift of 19 so we can fit a value of 16 into the
34 * TIMINCA register.
35 *
36 *
37 * SYSTIMH SYSTIML
38 * +--------------+ +---+---+------+
39 * 82576 | 32 | | 8 | 5 | 19 |
40 * +--------------+ +---+---+------+
41 * \________ 45 bits _______/ fract
42 *
43 * +----------+---+ +--------------+
44 * 82580 | 24 | 8 | | 32 |
45 * +----------+---+ +--------------+
46 * reserved \______ 40 bits _____/
47 *
48 *
49 * The 45 bit 82576 SYSTIM overflows every
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
51 *
52 * The 40 bit 82580 SYSTIM overflows every
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
54 *
55 * SYSTIM is converted to real time using a timecounter. As
56 * timecounter_cyc2time() allows old timestamps, the timecounter needs
57 * to be updated at least once per half of the SYSTIM interval.
58 * Scheduling of delayed work is not very accurate, and also the NIC
59 * clock can be adjusted to run up to 6% faster and the system clock
60 * up to 10% slower, so we aim for 6 minutes to be sure the actual
61 * interval in the NIC time is shorter than 9.16 minutes.
62 */
63
64#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6)
65#define IGB_PTP_TX_TIMEOUT (HZ * 15)
66#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
67#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
68#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
69#define IGB_NBITS_82580 40
70
71static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
72
73/* SYSTIM read access for the 82576 */
74static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
75{
76 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
77 struct e1000_hw *hw = &igb->hw;
78 u64 val;
79 u32 lo, hi;
80
81 lo = rd32(E1000_SYSTIML);
82 hi = rd32(E1000_SYSTIMH);
83
84 val = ((u64) hi) << 32;
85 val |= lo;
86
87 return val;
88}
89
90/* SYSTIM read access for the 82580 */
91static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
92{
93 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
94 struct e1000_hw *hw = &igb->hw;
95 u32 lo, hi;
96 u64 val;
97
98 /* The timestamp latches on lowest register read. For the 82580
99 * the lowest register is SYSTIMR instead of SYSTIML. However we only
100 * need to provide nanosecond resolution, so we just ignore it.
101 */
102 rd32(E1000_SYSTIMR);
103 lo = rd32(E1000_SYSTIML);
104 hi = rd32(E1000_SYSTIMH);
105
106 val = ((u64) hi) << 32;
107 val |= lo;
108
109 return val;
110}
111
112/* SYSTIM read access for I210/I211 */
113static void igb_ptp_read_i210(struct igb_adapter *adapter,
114 struct timespec64 *ts)
115{
116 struct e1000_hw *hw = &adapter->hw;
117 u32 sec, nsec;
118
119 /* The timestamp latches on lowest register read. For I210/I211, the
120 * lowest register is SYSTIMR. Since we only need to provide nanosecond
121 * resolution, we can ignore it.
122 */
123 rd32(E1000_SYSTIMR);
124 nsec = rd32(E1000_SYSTIML);
125 sec = rd32(E1000_SYSTIMH);
126
127 ts->tv_sec = sec;
128 ts->tv_nsec = nsec;
129}
130
131static void igb_ptp_write_i210(struct igb_adapter *adapter,
132 const struct timespec64 *ts)
133{
134 struct e1000_hw *hw = &adapter->hw;
135
136 /* Writing the SYSTIMR register is not necessary as it only provides
137 * sub-nanosecond resolution.
138 */
139 wr32(E1000_SYSTIML, ts->tv_nsec);
140 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
141}
142
143/**
144 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
145 * @adapter: board private structure
146 * @hwtstamps: timestamp structure to update
147 * @systim: unsigned 64bit system time value.
148 *
149 * We need to convert the system time value stored in the RX/TXSTMP registers
150 * into a hwtstamp which can be used by the upper level timestamping functions.
151 *
152 * The 'tmreg_lock' spinlock is used to protect the consistency of the
153 * system time value. This is needed because reading the 64 bit time
154 * value involves reading two (or three) 32 bit registers. The first
155 * read latches the value. Ditto for writing.
156 *
157 * In addition, here have extended the system time with an overflow
158 * counter in software.
159 **/
160static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
161 struct skb_shared_hwtstamps *hwtstamps,
162 u64 systim)
163{
164 unsigned long flags;
165 u64 ns;
166
167 switch (adapter->hw.mac.type) {
168 case e1000_82576:
169 case e1000_82580:
170 case e1000_i354:
171 case e1000_i350:
172 spin_lock_irqsave(&adapter->tmreg_lock, flags);
173
174 ns = timecounter_cyc2time(&adapter->tc, systim);
175
176 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
177
178 memset(hwtstamps, 0, sizeof(*hwtstamps));
179 hwtstamps->hwtstamp = ns_to_ktime(ns);
180 break;
181 case e1000_i210:
182 case e1000_i211:
183 memset(hwtstamps, 0, sizeof(*hwtstamps));
184 /* Upper 32 bits contain s, lower 32 bits contain ns. */
185 hwtstamps->hwtstamp = ktime_set(systim >> 32,
186 systim & 0xFFFFFFFF);
187 break;
188 default:
189 break;
190 }
191}
192
193/* PTP clock operations */
194static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
195{
196 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
197 ptp_caps);
198 struct e1000_hw *hw = &igb->hw;
199 int neg_adj = 0;
200 u64 rate;
201 u32 incvalue;
202
203 if (ppb < 0) {
204 neg_adj = 1;
205 ppb = -ppb;
206 }
207 rate = ppb;
208 rate <<= 14;
209 rate = div_u64(rate, 1953125);
210
211 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
212
213 if (neg_adj)
214 incvalue -= rate;
215 else
216 incvalue += rate;
217
218 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
219
220 return 0;
221}
222
223static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
224{
225 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
226 ptp_caps);
227 struct e1000_hw *hw = &igb->hw;
228 int neg_adj = 0;
229 u64 rate;
230 u32 inca;
231
232 if (scaled_ppm < 0) {
233 neg_adj = 1;
234 scaled_ppm = -scaled_ppm;
235 }
236 rate = scaled_ppm;
237 rate <<= 13;
238 rate = div_u64(rate, 15625);
239
240 inca = rate & INCVALUE_MASK;
241 if (neg_adj)
242 inca |= ISGN;
243
244 wr32(E1000_TIMINCA, inca);
245
246 return 0;
247}
248
249static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
250{
251 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
252 ptp_caps);
253 unsigned long flags;
254
255 spin_lock_irqsave(&igb->tmreg_lock, flags);
256 timecounter_adjtime(&igb->tc, delta);
257 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
258
259 return 0;
260}
261
262static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
263{
264 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
265 ptp_caps);
266 unsigned long flags;
267 struct timespec64 now, then = ns_to_timespec64(delta);
268
269 spin_lock_irqsave(&igb->tmreg_lock, flags);
270
271 igb_ptp_read_i210(igb, &now);
272 now = timespec64_add(now, then);
273 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
274
275 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
276
277 return 0;
278}
279
280static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp,
281 struct timespec64 *ts,
282 struct ptp_system_timestamp *sts)
283{
284 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
285 ptp_caps);
286 struct e1000_hw *hw = &igb->hw;
287 unsigned long flags;
288 u32 lo, hi;
289 u64 ns;
290
291 spin_lock_irqsave(&igb->tmreg_lock, flags);
292
293 ptp_read_system_prets(sts);
294 lo = rd32(E1000_SYSTIML);
295 ptp_read_system_postts(sts);
296 hi = rd32(E1000_SYSTIMH);
297
298 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
299
300 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
301
302 *ts = ns_to_timespec64(ns);
303
304 return 0;
305}
306
307static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp,
308 struct timespec64 *ts,
309 struct ptp_system_timestamp *sts)
310{
311 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
312 ptp_caps);
313 struct e1000_hw *hw = &igb->hw;
314 unsigned long flags;
315 u32 lo, hi;
316 u64 ns;
317
318 spin_lock_irqsave(&igb->tmreg_lock, flags);
319
320 ptp_read_system_prets(sts);
321 rd32(E1000_SYSTIMR);
322 ptp_read_system_postts(sts);
323 lo = rd32(E1000_SYSTIML);
324 hi = rd32(E1000_SYSTIMH);
325
326 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
327
328 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
329
330 *ts = ns_to_timespec64(ns);
331
332 return 0;
333}
334
335static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp,
336 struct timespec64 *ts,
337 struct ptp_system_timestamp *sts)
338{
339 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
340 ptp_caps);
341 struct e1000_hw *hw = &igb->hw;
342 unsigned long flags;
343
344 spin_lock_irqsave(&igb->tmreg_lock, flags);
345
346 ptp_read_system_prets(sts);
347 rd32(E1000_SYSTIMR);
348 ptp_read_system_postts(sts);
349 ts->tv_nsec = rd32(E1000_SYSTIML);
350 ts->tv_sec = rd32(E1000_SYSTIMH);
351
352 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
353
354 return 0;
355}
356
357static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
358 const struct timespec64 *ts)
359{
360 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
361 ptp_caps);
362 unsigned long flags;
363 u64 ns;
364
365 ns = timespec64_to_ns(ts);
366
367 spin_lock_irqsave(&igb->tmreg_lock, flags);
368
369 timecounter_init(&igb->tc, &igb->cc, ns);
370
371 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
372
373 return 0;
374}
375
376static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
377 const struct timespec64 *ts)
378{
379 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
380 ptp_caps);
381 unsigned long flags;
382
383 spin_lock_irqsave(&igb->tmreg_lock, flags);
384
385 igb_ptp_write_i210(igb, ts);
386
387 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
388
389 return 0;
390}
391
392static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
393{
394 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
395 static const u32 mask[IGB_N_SDP] = {
396 E1000_CTRL_SDP0_DIR,
397 E1000_CTRL_SDP1_DIR,
398 E1000_CTRL_EXT_SDP2_DIR,
399 E1000_CTRL_EXT_SDP3_DIR,
400 };
401
402 if (input)
403 *ptr &= ~mask[pin];
404 else
405 *ptr |= mask[pin];
406}
407
408static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
409{
410 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
412 };
413 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
415 };
416 static const u32 ts_sdp_en[IGB_N_SDP] = {
417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
418 };
419 struct e1000_hw *hw = &igb->hw;
420 u32 ctrl, ctrl_ext, tssdp = 0;
421
422 ctrl = rd32(E1000_CTRL);
423 ctrl_ext = rd32(E1000_CTRL_EXT);
424 tssdp = rd32(E1000_TSSDP);
425
426 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
427
428 /* Make sure this pin is not enabled as an output. */
429 tssdp &= ~ts_sdp_en[pin];
430
431 if (chan == 1) {
432 tssdp &= ~AUX1_SEL_SDP3;
433 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
434 } else {
435 tssdp &= ~AUX0_SEL_SDP3;
436 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
437 }
438
439 wr32(E1000_TSSDP, tssdp);
440 wr32(E1000_CTRL, ctrl);
441 wr32(E1000_CTRL_EXT, ctrl_ext);
442}
443
444static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
445{
446 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
447 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
448 };
449 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
450 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
451 };
452 static const u32 ts_sdp_en[IGB_N_SDP] = {
453 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
454 };
455 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
456 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
457 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
458 };
459 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
460 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
461 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
462 };
463 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
464 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
465 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
466 };
467 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
468 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
469 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
470 };
471 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
472 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
473 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
474 };
475 struct e1000_hw *hw = &igb->hw;
476 u32 ctrl, ctrl_ext, tssdp = 0;
477
478 ctrl = rd32(E1000_CTRL);
479 ctrl_ext = rd32(E1000_CTRL_EXT);
480 tssdp = rd32(E1000_TSSDP);
481
482 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
483
484 /* Make sure this pin is not enabled as an input. */
485 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
486 tssdp &= ~AUX0_TS_SDP_EN;
487
488 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
489 tssdp &= ~AUX1_TS_SDP_EN;
490
491 tssdp &= ~ts_sdp_sel_clr[pin];
492 if (freq) {
493 if (chan == 1)
494 tssdp |= ts_sdp_sel_fc1[pin];
495 else
496 tssdp |= ts_sdp_sel_fc0[pin];
497 } else {
498 if (chan == 1)
499 tssdp |= ts_sdp_sel_tt1[pin];
500 else
501 tssdp |= ts_sdp_sel_tt0[pin];
502 }
503 tssdp |= ts_sdp_en[pin];
504
505 wr32(E1000_TSSDP, tssdp);
506 wr32(E1000_CTRL, ctrl);
507 wr32(E1000_CTRL_EXT, ctrl_ext);
508}
509
510static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
511 struct ptp_clock_request *rq, int on)
512{
513 struct igb_adapter *igb =
514 container_of(ptp, struct igb_adapter, ptp_caps);
515 struct e1000_hw *hw = &igb->hw;
516 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
517 unsigned long flags;
518 struct timespec64 ts;
519 int use_freq = 0, pin = -1;
520 s64 ns;
521
522 switch (rq->type) {
523 case PTP_CLK_REQ_EXTTS:
524 /* Reject requests with unsupported flags */
525 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
526 PTP_RISING_EDGE |
527 PTP_FALLING_EDGE |
528 PTP_STRICT_FLAGS))
529 return -EOPNOTSUPP;
530
531 /* Reject requests failing to enable both edges. */
532 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
533 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
534 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
535 return -EOPNOTSUPP;
536
537 if (on) {
538 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
539 rq->extts.index);
540 if (pin < 0)
541 return -EBUSY;
542 }
543 if (rq->extts.index == 1) {
544 tsauxc_mask = TSAUXC_EN_TS1;
545 tsim_mask = TSINTR_AUTT1;
546 } else {
547 tsauxc_mask = TSAUXC_EN_TS0;
548 tsim_mask = TSINTR_AUTT0;
549 }
550 spin_lock_irqsave(&igb->tmreg_lock, flags);
551 tsauxc = rd32(E1000_TSAUXC);
552 tsim = rd32(E1000_TSIM);
553 if (on) {
554 igb_pin_extts(igb, rq->extts.index, pin);
555 tsauxc |= tsauxc_mask;
556 tsim |= tsim_mask;
557 } else {
558 tsauxc &= ~tsauxc_mask;
559 tsim &= ~tsim_mask;
560 }
561 wr32(E1000_TSAUXC, tsauxc);
562 wr32(E1000_TSIM, tsim);
563 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
564 return 0;
565
566 case PTP_CLK_REQ_PEROUT:
567 /* Reject requests with unsupported flags */
568 if (rq->perout.flags)
569 return -EOPNOTSUPP;
570
571 if (on) {
572 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
573 rq->perout.index);
574 if (pin < 0)
575 return -EBUSY;
576 }
577 ts.tv_sec = rq->perout.period.sec;
578 ts.tv_nsec = rq->perout.period.nsec;
579 ns = timespec64_to_ns(&ts);
580 ns = ns >> 1;
581 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
582 (ns == 250000000LL) || (ns == 500000000LL))) {
583 if (ns < 8LL)
584 return -EINVAL;
585 use_freq = 1;
586 }
587 ts = ns_to_timespec64(ns);
588 if (rq->perout.index == 1) {
589 if (use_freq) {
590 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
591 tsim_mask = 0;
592 } else {
593 tsauxc_mask = TSAUXC_EN_TT1;
594 tsim_mask = TSINTR_TT1;
595 }
596 trgttiml = E1000_TRGTTIML1;
597 trgttimh = E1000_TRGTTIMH1;
598 freqout = E1000_FREQOUT1;
599 } else {
600 if (use_freq) {
601 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
602 tsim_mask = 0;
603 } else {
604 tsauxc_mask = TSAUXC_EN_TT0;
605 tsim_mask = TSINTR_TT0;
606 }
607 trgttiml = E1000_TRGTTIML0;
608 trgttimh = E1000_TRGTTIMH0;
609 freqout = E1000_FREQOUT0;
610 }
611 spin_lock_irqsave(&igb->tmreg_lock, flags);
612 tsauxc = rd32(E1000_TSAUXC);
613 tsim = rd32(E1000_TSIM);
614 if (rq->perout.index == 1) {
615 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
616 tsim &= ~TSINTR_TT1;
617 } else {
618 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
619 tsim &= ~TSINTR_TT0;
620 }
621 if (on) {
622 int i = rq->perout.index;
623 igb_pin_perout(igb, i, pin, use_freq);
624 igb->perout[i].start.tv_sec = rq->perout.start.sec;
625 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
626 igb->perout[i].period.tv_sec = ts.tv_sec;
627 igb->perout[i].period.tv_nsec = ts.tv_nsec;
628 wr32(trgttimh, rq->perout.start.sec);
629 wr32(trgttiml, rq->perout.start.nsec);
630 if (use_freq)
631 wr32(freqout, ns);
632 tsauxc |= tsauxc_mask;
633 tsim |= tsim_mask;
634 }
635 wr32(E1000_TSAUXC, tsauxc);
636 wr32(E1000_TSIM, tsim);
637 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
638 return 0;
639
640 case PTP_CLK_REQ_PPS:
641 spin_lock_irqsave(&igb->tmreg_lock, flags);
642 tsim = rd32(E1000_TSIM);
643 if (on)
644 tsim |= TSINTR_SYS_WRAP;
645 else
646 tsim &= ~TSINTR_SYS_WRAP;
647 igb->pps_sys_wrap_on = !!on;
648 wr32(E1000_TSIM, tsim);
649 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
650 return 0;
651 }
652
653 return -EOPNOTSUPP;
654}
655
656static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
657 struct ptp_clock_request *rq, int on)
658{
659 return -EOPNOTSUPP;
660}
661
662static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
663 enum ptp_pin_function func, unsigned int chan)
664{
665 switch (func) {
666 case PTP_PF_NONE:
667 case PTP_PF_EXTTS:
668 case PTP_PF_PEROUT:
669 break;
670 case PTP_PF_PHYSYNC:
671 return -1;
672 }
673 return 0;
674}
675
676/**
677 * igb_ptp_tx_work
678 * @work: pointer to work struct
679 *
680 * This work function polls the TSYNCTXCTL valid bit to determine when a
681 * timestamp has been taken for the current stored skb.
682 **/
683static void igb_ptp_tx_work(struct work_struct *work)
684{
685 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
686 ptp_tx_work);
687 struct e1000_hw *hw = &adapter->hw;
688 u32 tsynctxctl;
689
690 if (!adapter->ptp_tx_skb)
691 return;
692
693 if (time_is_before_jiffies(adapter->ptp_tx_start +
694 IGB_PTP_TX_TIMEOUT)) {
695 dev_kfree_skb_any(adapter->ptp_tx_skb);
696 adapter->ptp_tx_skb = NULL;
697 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
698 adapter->tx_hwtstamp_timeouts++;
699 /* Clear the tx valid bit in TSYNCTXCTL register to enable
700 * interrupt
701 */
702 rd32(E1000_TXSTMPH);
703 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
704 return;
705 }
706
707 tsynctxctl = rd32(E1000_TSYNCTXCTL);
708 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
709 igb_ptp_tx_hwtstamp(adapter);
710 else
711 /* reschedule to check later */
712 schedule_work(&adapter->ptp_tx_work);
713}
714
715static void igb_ptp_overflow_check(struct work_struct *work)
716{
717 struct igb_adapter *igb =
718 container_of(work, struct igb_adapter, ptp_overflow_work.work);
719 struct timespec64 ts;
720 u64 ns;
721
722 /* Update the timecounter */
723 ns = timecounter_read(&igb->tc);
724
725 ts = ns_to_timespec64(ns);
726 pr_debug("igb overflow check at %lld.%09lu\n",
727 (long long) ts.tv_sec, ts.tv_nsec);
728
729 schedule_delayed_work(&igb->ptp_overflow_work,
730 IGB_SYSTIM_OVERFLOW_PERIOD);
731}
732
733/**
734 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
735 * @adapter: private network adapter structure
736 *
737 * This watchdog task is scheduled to detect error case where hardware has
738 * dropped an Rx packet that was timestamped when the ring is full. The
739 * particular error is rare but leaves the device in a state unable to timestamp
740 * any future packets.
741 **/
742void igb_ptp_rx_hang(struct igb_adapter *adapter)
743{
744 struct e1000_hw *hw = &adapter->hw;
745 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
746 unsigned long rx_event;
747
748 /* Other hardware uses per-packet timestamps */
749 if (hw->mac.type != e1000_82576)
750 return;
751
752 /* If we don't have a valid timestamp in the registers, just update the
753 * timeout counter and exit
754 */
755 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
756 adapter->last_rx_ptp_check = jiffies;
757 return;
758 }
759
760 /* Determine the most recent watchdog or rx_timestamp event */
761 rx_event = adapter->last_rx_ptp_check;
762 if (time_after(adapter->last_rx_timestamp, rx_event))
763 rx_event = adapter->last_rx_timestamp;
764
765 /* Only need to read the high RXSTMP register to clear the lock */
766 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
767 rd32(E1000_RXSTMPH);
768 adapter->last_rx_ptp_check = jiffies;
769 adapter->rx_hwtstamp_cleared++;
770 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
771 }
772}
773
774/**
775 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
776 * @adapter: private network adapter structure
777 */
778void igb_ptp_tx_hang(struct igb_adapter *adapter)
779{
780 struct e1000_hw *hw = &adapter->hw;
781 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
782 IGB_PTP_TX_TIMEOUT);
783
784 if (!adapter->ptp_tx_skb)
785 return;
786
787 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
788 return;
789
790 /* If we haven't received a timestamp within the timeout, it is
791 * reasonable to assume that it will never occur, so we can unlock the
792 * timestamp bit when this occurs.
793 */
794 if (timeout) {
795 cancel_work_sync(&adapter->ptp_tx_work);
796 dev_kfree_skb_any(adapter->ptp_tx_skb);
797 adapter->ptp_tx_skb = NULL;
798 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
799 adapter->tx_hwtstamp_timeouts++;
800 /* Clear the tx valid bit in TSYNCTXCTL register to enable
801 * interrupt
802 */
803 rd32(E1000_TXSTMPH);
804 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
805 }
806}
807
808/**
809 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
810 * @adapter: Board private structure.
811 *
812 * If we were asked to do hardware stamping and such a time stamp is
813 * available, then it must have been for this skb here because we only
814 * allow only one such packet into the queue.
815 **/
816static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
817{
818 struct sk_buff *skb = adapter->ptp_tx_skb;
819 struct e1000_hw *hw = &adapter->hw;
820 struct skb_shared_hwtstamps shhwtstamps;
821 u64 regval;
822 int adjust = 0;
823
824 regval = rd32(E1000_TXSTMPL);
825 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
826
827 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
828 /* adjust timestamp for the TX latency based on link speed */
829 if (adapter->hw.mac.type == e1000_i210) {
830 switch (adapter->link_speed) {
831 case SPEED_10:
832 adjust = IGB_I210_TX_LATENCY_10;
833 break;
834 case SPEED_100:
835 adjust = IGB_I210_TX_LATENCY_100;
836 break;
837 case SPEED_1000:
838 adjust = IGB_I210_TX_LATENCY_1000;
839 break;
840 }
841 }
842
843 shhwtstamps.hwtstamp =
844 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
845
846 /* Clear the lock early before calling skb_tstamp_tx so that
847 * applications are not woken up before the lock bit is clear. We use
848 * a copy of the skb pointer to ensure other threads can't change it
849 * while we're notifying the stack.
850 */
851 adapter->ptp_tx_skb = NULL;
852 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
853
854 /* Notify the stack and free the skb after we've unlocked */
855 skb_tstamp_tx(skb, &shhwtstamps);
856 dev_kfree_skb_any(skb);
857}
858
859/**
860 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
861 * @q_vector: Pointer to interrupt specific structure
862 * @va: Pointer to address containing Rx buffer
863 * @skb: Buffer containing timestamp and packet
864 *
865 * This function is meant to retrieve a timestamp from the first buffer of an
866 * incoming frame. The value is stored in little endian format starting on
867 * byte 8.
868 **/
869void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
870 struct sk_buff *skb)
871{
872 __le64 *regval = (__le64 *)va;
873 struct igb_adapter *adapter = q_vector->adapter;
874 int adjust = 0;
875
876 /* The timestamp is recorded in little endian format.
877 * DWORD: 0 1 2 3
878 * Field: Reserved Reserved SYSTIML SYSTIMH
879 */
880 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
881 le64_to_cpu(regval[1]));
882
883 /* adjust timestamp for the RX latency based on link speed */
884 if (adapter->hw.mac.type == e1000_i210) {
885 switch (adapter->link_speed) {
886 case SPEED_10:
887 adjust = IGB_I210_RX_LATENCY_10;
888 break;
889 case SPEED_100:
890 adjust = IGB_I210_RX_LATENCY_100;
891 break;
892 case SPEED_1000:
893 adjust = IGB_I210_RX_LATENCY_1000;
894 break;
895 }
896 }
897 skb_hwtstamps(skb)->hwtstamp =
898 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
899}
900
901/**
902 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
903 * @q_vector: Pointer to interrupt specific structure
904 * @skb: Buffer containing timestamp and packet
905 *
906 * This function is meant to retrieve a timestamp from the internal registers
907 * of the adapter and store it in the skb.
908 **/
909void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
910 struct sk_buff *skb)
911{
912 struct igb_adapter *adapter = q_vector->adapter;
913 struct e1000_hw *hw = &adapter->hw;
914 u64 regval;
915 int adjust = 0;
916
917 /* If this bit is set, then the RX registers contain the time stamp. No
918 * other packet will be time stamped until we read these registers, so
919 * read the registers to make them available again. Because only one
920 * packet can be time stamped at a time, we know that the register
921 * values must belong to this one here and therefore we don't need to
922 * compare any of the additional attributes stored for it.
923 *
924 * If nothing went wrong, then it should have a shared tx_flags that we
925 * can turn into a skb_shared_hwtstamps.
926 */
927 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
928 return;
929
930 regval = rd32(E1000_RXSTMPL);
931 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
932
933 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
934
935 /* adjust timestamp for the RX latency based on link speed */
936 if (adapter->hw.mac.type == e1000_i210) {
937 switch (adapter->link_speed) {
938 case SPEED_10:
939 adjust = IGB_I210_RX_LATENCY_10;
940 break;
941 case SPEED_100:
942 adjust = IGB_I210_RX_LATENCY_100;
943 break;
944 case SPEED_1000:
945 adjust = IGB_I210_RX_LATENCY_1000;
946 break;
947 }
948 }
949 skb_hwtstamps(skb)->hwtstamp =
950 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
951
952 /* Update the last_rx_timestamp timer in order to enable watchdog check
953 * for error case of latched timestamp on a dropped packet.
954 */
955 adapter->last_rx_timestamp = jiffies;
956}
957
958/**
959 * igb_ptp_get_ts_config - get hardware time stamping config
960 * @netdev:
961 * @ifreq:
962 *
963 * Get the hwtstamp_config settings to return to the user. Rather than attempt
964 * to deconstruct the settings from the registers, just return a shadow copy
965 * of the last known settings.
966 **/
967int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
968{
969 struct igb_adapter *adapter = netdev_priv(netdev);
970 struct hwtstamp_config *config = &adapter->tstamp_config;
971
972 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
973 -EFAULT : 0;
974}
975
976/**
977 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
978 * @adapter: networking device structure
979 * @config: hwtstamp configuration
980 *
981 * Outgoing time stamping can be enabled and disabled. Play nice and
982 * disable it when requested, although it shouldn't case any overhead
983 * when no packet needs it. At most one packet in the queue may be
984 * marked for time stamping, otherwise it would be impossible to tell
985 * for sure to which packet the hardware time stamp belongs.
986 *
987 * Incoming time stamping has to be configured via the hardware
988 * filters. Not all combinations are supported, in particular event
989 * type has to be specified. Matching the kind of event packet is
990 * not supported, with the exception of "all V2 events regardless of
991 * level 2 or 4".
992 */
993static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
994 struct hwtstamp_config *config)
995{
996 struct e1000_hw *hw = &adapter->hw;
997 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
998 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
999 u32 tsync_rx_cfg = 0;
1000 bool is_l4 = false;
1001 bool is_l2 = false;
1002 u32 regval;
1003
1004 /* reserved for future extensions */
1005 if (config->flags)
1006 return -EINVAL;
1007
1008 switch (config->tx_type) {
1009 case HWTSTAMP_TX_OFF:
1010 tsync_tx_ctl = 0;
1011 case HWTSTAMP_TX_ON:
1012 break;
1013 default:
1014 return -ERANGE;
1015 }
1016
1017 switch (config->rx_filter) {
1018 case HWTSTAMP_FILTER_NONE:
1019 tsync_rx_ctl = 0;
1020 break;
1021 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1022 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1023 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
1024 is_l4 = true;
1025 break;
1026 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1027 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1028 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
1029 is_l4 = true;
1030 break;
1031 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1032 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1033 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1034 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1035 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1036 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1037 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1038 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1039 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1040 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
1041 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1042 is_l2 = true;
1043 is_l4 = true;
1044 break;
1045 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1046 case HWTSTAMP_FILTER_NTP_ALL:
1047 case HWTSTAMP_FILTER_ALL:
1048 /* 82576 cannot timestamp all packets, which it needs to do to
1049 * support both V1 Sync and Delay_Req messages
1050 */
1051 if (hw->mac.type != e1000_82576) {
1052 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1053 config->rx_filter = HWTSTAMP_FILTER_ALL;
1054 break;
1055 }
1056 fallthrough;
1057 default:
1058 config->rx_filter = HWTSTAMP_FILTER_NONE;
1059 return -ERANGE;
1060 }
1061
1062 if (hw->mac.type == e1000_82575) {
1063 if (tsync_rx_ctl | tsync_tx_ctl)
1064 return -EINVAL;
1065 return 0;
1066 }
1067
1068 /* Per-packet timestamping only works if all packets are
1069 * timestamped, so enable timestamping in all packets as
1070 * long as one Rx filter was configured.
1071 */
1072 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1073 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1074 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1075 config->rx_filter = HWTSTAMP_FILTER_ALL;
1076 is_l2 = true;
1077 is_l4 = true;
1078
1079 if ((hw->mac.type == e1000_i210) ||
1080 (hw->mac.type == e1000_i211)) {
1081 regval = rd32(E1000_RXPBS);
1082 regval |= E1000_RXPBS_CFG_TS_EN;
1083 wr32(E1000_RXPBS, regval);
1084 }
1085 }
1086
1087 /* enable/disable TX */
1088 regval = rd32(E1000_TSYNCTXCTL);
1089 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1090 regval |= tsync_tx_ctl;
1091 wr32(E1000_TSYNCTXCTL, regval);
1092
1093 /* enable/disable RX */
1094 regval = rd32(E1000_TSYNCRXCTL);
1095 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1096 regval |= tsync_rx_ctl;
1097 wr32(E1000_TSYNCRXCTL, regval);
1098
1099 /* define which PTP packets are time stamped */
1100 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1101
1102 /* define ethertype filter for timestamped packets */
1103 if (is_l2)
1104 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1105 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1106 E1000_ETQF_1588 | /* enable timestamping */
1107 ETH_P_1588)); /* 1588 eth protocol type */
1108 else
1109 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1110
1111 /* L4 Queue Filter[3]: filter by destination port and protocol */
1112 if (is_l4) {
1113 u32 ftqf = (IPPROTO_UDP /* UDP */
1114 | E1000_FTQF_VF_BP /* VF not compared */
1115 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1116 | E1000_FTQF_MASK); /* mask all inputs */
1117 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1118
1119 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1120 wr32(E1000_IMIREXT(3),
1121 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1122 if (hw->mac.type == e1000_82576) {
1123 /* enable source port check */
1124 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1125 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1126 }
1127 wr32(E1000_FTQF(3), ftqf);
1128 } else {
1129 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1130 }
1131 wrfl();
1132
1133 /* clear TX/RX time stamp registers, just to be sure */
1134 regval = rd32(E1000_TXSTMPL);
1135 regval = rd32(E1000_TXSTMPH);
1136 regval = rd32(E1000_RXSTMPL);
1137 regval = rd32(E1000_RXSTMPH);
1138
1139 return 0;
1140}
1141
1142/**
1143 * igb_ptp_set_ts_config - set hardware time stamping config
1144 * @netdev:
1145 * @ifreq:
1146 *
1147 **/
1148int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1149{
1150 struct igb_adapter *adapter = netdev_priv(netdev);
1151 struct hwtstamp_config config;
1152 int err;
1153
1154 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1155 return -EFAULT;
1156
1157 err = igb_ptp_set_timestamp_mode(adapter, &config);
1158 if (err)
1159 return err;
1160
1161 /* save these settings for future reference */
1162 memcpy(&adapter->tstamp_config, &config,
1163 sizeof(adapter->tstamp_config));
1164
1165 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1166 -EFAULT : 0;
1167}
1168
1169/**
1170 * igb_ptp_init - Initialize PTP functionality
1171 * @adapter: Board private structure
1172 *
1173 * This function is called at device probe to initialize the PTP
1174 * functionality.
1175 */
1176void igb_ptp_init(struct igb_adapter *adapter)
1177{
1178 struct e1000_hw *hw = &adapter->hw;
1179 struct net_device *netdev = adapter->netdev;
1180 int i;
1181
1182 switch (hw->mac.type) {
1183 case e1000_82576:
1184 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1185 adapter->ptp_caps.owner = THIS_MODULE;
1186 adapter->ptp_caps.max_adj = 999999881;
1187 adapter->ptp_caps.n_ext_ts = 0;
1188 adapter->ptp_caps.pps = 0;
1189 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1190 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1191 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576;
1192 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1193 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1194 adapter->cc.read = igb_ptp_read_82576;
1195 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1196 adapter->cc.mult = 1;
1197 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1198 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1199 break;
1200 case e1000_82580:
1201 case e1000_i354:
1202 case e1000_i350:
1203 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1204 adapter->ptp_caps.owner = THIS_MODULE;
1205 adapter->ptp_caps.max_adj = 62499999;
1206 adapter->ptp_caps.n_ext_ts = 0;
1207 adapter->ptp_caps.pps = 0;
1208 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1209 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1210 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580;
1211 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1212 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1213 adapter->cc.read = igb_ptp_read_82580;
1214 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1215 adapter->cc.mult = 1;
1216 adapter->cc.shift = 0;
1217 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1218 break;
1219 case e1000_i210:
1220 case e1000_i211:
1221 for (i = 0; i < IGB_N_SDP; i++) {
1222 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1223
1224 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1225 ppd->index = i;
1226 ppd->func = PTP_PF_NONE;
1227 }
1228 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1229 adapter->ptp_caps.owner = THIS_MODULE;
1230 adapter->ptp_caps.max_adj = 62499999;
1231 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1232 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1233 adapter->ptp_caps.n_pins = IGB_N_SDP;
1234 adapter->ptp_caps.pps = 1;
1235 adapter->ptp_caps.pin_config = adapter->sdp_config;
1236 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1237 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1238 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210;
1239 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1240 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1241 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1242 break;
1243 default:
1244 adapter->ptp_clock = NULL;
1245 return;
1246 }
1247
1248 spin_lock_init(&adapter->tmreg_lock);
1249 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1250
1251 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1252 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1253 igb_ptp_overflow_check);
1254
1255 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1256 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1257
1258 igb_ptp_reset(adapter);
1259
1260 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1261 &adapter->pdev->dev);
1262 if (IS_ERR(adapter->ptp_clock)) {
1263 adapter->ptp_clock = NULL;
1264 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1265 } else if (adapter->ptp_clock) {
1266 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1267 adapter->netdev->name);
1268 adapter->ptp_flags |= IGB_PTP_ENABLED;
1269 }
1270}
1271
1272/**
1273 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1274 * @adapter: Board private structure
1275 *
1276 * This function stops the overflow check work and PTP Tx timestamp work, and
1277 * will prepare the device for OS suspend.
1278 */
1279void igb_ptp_suspend(struct igb_adapter *adapter)
1280{
1281 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1282 return;
1283
1284 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1285 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1286
1287 cancel_work_sync(&adapter->ptp_tx_work);
1288 if (adapter->ptp_tx_skb) {
1289 dev_kfree_skb_any(adapter->ptp_tx_skb);
1290 adapter->ptp_tx_skb = NULL;
1291 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1292 }
1293}
1294
1295/**
1296 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1297 * @adapter: Board private structure.
1298 *
1299 * This function stops the PTP support and cancels the delayed work.
1300 **/
1301void igb_ptp_stop(struct igb_adapter *adapter)
1302{
1303 igb_ptp_suspend(adapter);
1304
1305 if (adapter->ptp_clock) {
1306 ptp_clock_unregister(adapter->ptp_clock);
1307 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1308 adapter->netdev->name);
1309 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1310 }
1311}
1312
1313/**
1314 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1315 * @adapter: Board private structure.
1316 *
1317 * This function handles the reset work required to re-enable the PTP device.
1318 **/
1319void igb_ptp_reset(struct igb_adapter *adapter)
1320{
1321 struct e1000_hw *hw = &adapter->hw;
1322 unsigned long flags;
1323
1324 /* reset the tstamp_config */
1325 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1326
1327 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1328
1329 switch (adapter->hw.mac.type) {
1330 case e1000_82576:
1331 /* Dial the nominal frequency. */
1332 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1333 break;
1334 case e1000_82580:
1335 case e1000_i354:
1336 case e1000_i350:
1337 case e1000_i210:
1338 case e1000_i211:
1339 wr32(E1000_TSAUXC, 0x0);
1340 wr32(E1000_TSSDP, 0x0);
1341 wr32(E1000_TSIM,
1342 TSYNC_INTERRUPTS |
1343 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1344 wr32(E1000_IMS, E1000_IMS_TS);
1345 break;
1346 default:
1347 /* No work to do. */
1348 goto out;
1349 }
1350
1351 /* Re-initialize the timer. */
1352 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1353 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1354
1355 igb_ptp_write_i210(adapter, &ts);
1356 } else {
1357 timecounter_init(&adapter->tc, &adapter->cc,
1358 ktime_to_ns(ktime_get_real()));
1359 }
1360out:
1361 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1362
1363 wrfl();
1364
1365 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1366 schedule_delayed_work(&adapter->ptp_overflow_work,
1367 IGB_SYSTIM_OVERFLOW_PERIOD);
1368}
1/* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
2 *
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/pci.h>
21#include <linux/ptp_classify.h>
22
23#include "igb.h"
24
25#define INCVALUE_MASK 0x7fffffff
26#define ISGN 0x80000000
27
28/* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
30 *
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
35 * register, TIMINCA.
36 *
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
41 *
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
48 * TIMINCA register.
49 *
50 *
51 * SYSTIMH SYSTIML
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
56 *
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
61 *
62 *
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
65 *
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
68 */
69
70#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71#define IGB_PTP_TX_TIMEOUT (HZ * 15)
72#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
73#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
75#define IGB_NBITS_82580 40
76
77static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
78
79/* SYSTIM read access for the 82576 */
80static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
81{
82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
83 struct e1000_hw *hw = &igb->hw;
84 u64 val;
85 u32 lo, hi;
86
87 lo = rd32(E1000_SYSTIML);
88 hi = rd32(E1000_SYSTIMH);
89
90 val = ((u64) hi) << 32;
91 val |= lo;
92
93 return val;
94}
95
96/* SYSTIM read access for the 82580 */
97static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
98{
99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
100 struct e1000_hw *hw = &igb->hw;
101 u32 lo, hi;
102 u64 val;
103
104 /* The timestamp latches on lowest register read. For the 82580
105 * the lowest register is SYSTIMR instead of SYSTIML. However we only
106 * need to provide nanosecond resolution, so we just ignore it.
107 */
108 rd32(E1000_SYSTIMR);
109 lo = rd32(E1000_SYSTIML);
110 hi = rd32(E1000_SYSTIMH);
111
112 val = ((u64) hi) << 32;
113 val |= lo;
114
115 return val;
116}
117
118/* SYSTIM read access for I210/I211 */
119static void igb_ptp_read_i210(struct igb_adapter *adapter,
120 struct timespec64 *ts)
121{
122 struct e1000_hw *hw = &adapter->hw;
123 u32 sec, nsec;
124
125 /* The timestamp latches on lowest register read. For I210/I211, the
126 * lowest register is SYSTIMR. Since we only need to provide nanosecond
127 * resolution, we can ignore it.
128 */
129 rd32(E1000_SYSTIMR);
130 nsec = rd32(E1000_SYSTIML);
131 sec = rd32(E1000_SYSTIMH);
132
133 ts->tv_sec = sec;
134 ts->tv_nsec = nsec;
135}
136
137static void igb_ptp_write_i210(struct igb_adapter *adapter,
138 const struct timespec64 *ts)
139{
140 struct e1000_hw *hw = &adapter->hw;
141
142 /* Writing the SYSTIMR register is not necessary as it only provides
143 * sub-nanosecond resolution.
144 */
145 wr32(E1000_SYSTIML, ts->tv_nsec);
146 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
147}
148
149/**
150 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
151 * @adapter: board private structure
152 * @hwtstamps: timestamp structure to update
153 * @systim: unsigned 64bit system time value.
154 *
155 * We need to convert the system time value stored in the RX/TXSTMP registers
156 * into a hwtstamp which can be used by the upper level timestamping functions.
157 *
158 * The 'tmreg_lock' spinlock is used to protect the consistency of the
159 * system time value. This is needed because reading the 64 bit time
160 * value involves reading two (or three) 32 bit registers. The first
161 * read latches the value. Ditto for writing.
162 *
163 * In addition, here have extended the system time with an overflow
164 * counter in software.
165 **/
166static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
167 struct skb_shared_hwtstamps *hwtstamps,
168 u64 systim)
169{
170 unsigned long flags;
171 u64 ns;
172
173 switch (adapter->hw.mac.type) {
174 case e1000_82576:
175 case e1000_82580:
176 case e1000_i354:
177 case e1000_i350:
178 spin_lock_irqsave(&adapter->tmreg_lock, flags);
179
180 ns = timecounter_cyc2time(&adapter->tc, systim);
181
182 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
183
184 memset(hwtstamps, 0, sizeof(*hwtstamps));
185 hwtstamps->hwtstamp = ns_to_ktime(ns);
186 break;
187 case e1000_i210:
188 case e1000_i211:
189 memset(hwtstamps, 0, sizeof(*hwtstamps));
190 /* Upper 32 bits contain s, lower 32 bits contain ns. */
191 hwtstamps->hwtstamp = ktime_set(systim >> 32,
192 systim & 0xFFFFFFFF);
193 break;
194 default:
195 break;
196 }
197}
198
199/* PTP clock operations */
200static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
201{
202 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
203 ptp_caps);
204 struct e1000_hw *hw = &igb->hw;
205 int neg_adj = 0;
206 u64 rate;
207 u32 incvalue;
208
209 if (ppb < 0) {
210 neg_adj = 1;
211 ppb = -ppb;
212 }
213 rate = ppb;
214 rate <<= 14;
215 rate = div_u64(rate, 1953125);
216
217 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
218
219 if (neg_adj)
220 incvalue -= rate;
221 else
222 incvalue += rate;
223
224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
225
226 return 0;
227}
228
229static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
230{
231 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
232 ptp_caps);
233 struct e1000_hw *hw = &igb->hw;
234 int neg_adj = 0;
235 u64 rate;
236 u32 inca;
237
238 if (ppb < 0) {
239 neg_adj = 1;
240 ppb = -ppb;
241 }
242 rate = ppb;
243 rate <<= 26;
244 rate = div_u64(rate, 1953125);
245
246 inca = rate & INCVALUE_MASK;
247 if (neg_adj)
248 inca |= ISGN;
249
250 wr32(E1000_TIMINCA, inca);
251
252 return 0;
253}
254
255static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
256{
257 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
258 ptp_caps);
259 unsigned long flags;
260
261 spin_lock_irqsave(&igb->tmreg_lock, flags);
262 timecounter_adjtime(&igb->tc, delta);
263 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
264
265 return 0;
266}
267
268static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
269{
270 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
271 ptp_caps);
272 unsigned long flags;
273 struct timespec64 now, then = ns_to_timespec64(delta);
274
275 spin_lock_irqsave(&igb->tmreg_lock, flags);
276
277 igb_ptp_read_i210(igb, &now);
278 now = timespec64_add(now, then);
279 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
280
281 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
282
283 return 0;
284}
285
286static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
287 struct timespec64 *ts)
288{
289 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
290 ptp_caps);
291 unsigned long flags;
292 u64 ns;
293
294 spin_lock_irqsave(&igb->tmreg_lock, flags);
295
296 ns = timecounter_read(&igb->tc);
297
298 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
299
300 *ts = ns_to_timespec64(ns);
301
302 return 0;
303}
304
305static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
306 struct timespec64 *ts)
307{
308 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
309 ptp_caps);
310 unsigned long flags;
311
312 spin_lock_irqsave(&igb->tmreg_lock, flags);
313
314 igb_ptp_read_i210(igb, ts);
315
316 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
317
318 return 0;
319}
320
321static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
322 const struct timespec64 *ts)
323{
324 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
325 ptp_caps);
326 unsigned long flags;
327 u64 ns;
328
329 ns = timespec64_to_ns(ts);
330
331 spin_lock_irqsave(&igb->tmreg_lock, flags);
332
333 timecounter_init(&igb->tc, &igb->cc, ns);
334
335 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
336
337 return 0;
338}
339
340static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
341 const struct timespec64 *ts)
342{
343 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
344 ptp_caps);
345 unsigned long flags;
346
347 spin_lock_irqsave(&igb->tmreg_lock, flags);
348
349 igb_ptp_write_i210(igb, ts);
350
351 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
352
353 return 0;
354}
355
356static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
357{
358 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
359 static const u32 mask[IGB_N_SDP] = {
360 E1000_CTRL_SDP0_DIR,
361 E1000_CTRL_SDP1_DIR,
362 E1000_CTRL_EXT_SDP2_DIR,
363 E1000_CTRL_EXT_SDP3_DIR,
364 };
365
366 if (input)
367 *ptr &= ~mask[pin];
368 else
369 *ptr |= mask[pin];
370}
371
372static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
373{
374 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
375 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
376 };
377 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
378 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
379 };
380 static const u32 ts_sdp_en[IGB_N_SDP] = {
381 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
382 };
383 struct e1000_hw *hw = &igb->hw;
384 u32 ctrl, ctrl_ext, tssdp = 0;
385
386 ctrl = rd32(E1000_CTRL);
387 ctrl_ext = rd32(E1000_CTRL_EXT);
388 tssdp = rd32(E1000_TSSDP);
389
390 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
391
392 /* Make sure this pin is not enabled as an output. */
393 tssdp &= ~ts_sdp_en[pin];
394
395 if (chan == 1) {
396 tssdp &= ~AUX1_SEL_SDP3;
397 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
398 } else {
399 tssdp &= ~AUX0_SEL_SDP3;
400 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
401 }
402
403 wr32(E1000_TSSDP, tssdp);
404 wr32(E1000_CTRL, ctrl);
405 wr32(E1000_CTRL_EXT, ctrl_ext);
406}
407
408static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
409{
410 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
412 };
413 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
415 };
416 static const u32 ts_sdp_en[IGB_N_SDP] = {
417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
418 };
419 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
420 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
421 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
422 };
423 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
424 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
425 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
426 };
427 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
428 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
429 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
430 };
431 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
432 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
433 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
434 };
435 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
436 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
437 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
438 };
439 struct e1000_hw *hw = &igb->hw;
440 u32 ctrl, ctrl_ext, tssdp = 0;
441
442 ctrl = rd32(E1000_CTRL);
443 ctrl_ext = rd32(E1000_CTRL_EXT);
444 tssdp = rd32(E1000_TSSDP);
445
446 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
447
448 /* Make sure this pin is not enabled as an input. */
449 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
450 tssdp &= ~AUX0_TS_SDP_EN;
451
452 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
453 tssdp &= ~AUX1_TS_SDP_EN;
454
455 tssdp &= ~ts_sdp_sel_clr[pin];
456 if (freq) {
457 if (chan == 1)
458 tssdp |= ts_sdp_sel_fc1[pin];
459 else
460 tssdp |= ts_sdp_sel_fc0[pin];
461 } else {
462 if (chan == 1)
463 tssdp |= ts_sdp_sel_tt1[pin];
464 else
465 tssdp |= ts_sdp_sel_tt0[pin];
466 }
467 tssdp |= ts_sdp_en[pin];
468
469 wr32(E1000_TSSDP, tssdp);
470 wr32(E1000_CTRL, ctrl);
471 wr32(E1000_CTRL_EXT, ctrl_ext);
472}
473
474static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
475 struct ptp_clock_request *rq, int on)
476{
477 struct igb_adapter *igb =
478 container_of(ptp, struct igb_adapter, ptp_caps);
479 struct e1000_hw *hw = &igb->hw;
480 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
481 unsigned long flags;
482 struct timespec64 ts;
483 int use_freq = 0, pin = -1;
484 s64 ns;
485
486 switch (rq->type) {
487 case PTP_CLK_REQ_EXTTS:
488 if (on) {
489 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
490 rq->extts.index);
491 if (pin < 0)
492 return -EBUSY;
493 }
494 if (rq->extts.index == 1) {
495 tsauxc_mask = TSAUXC_EN_TS1;
496 tsim_mask = TSINTR_AUTT1;
497 } else {
498 tsauxc_mask = TSAUXC_EN_TS0;
499 tsim_mask = TSINTR_AUTT0;
500 }
501 spin_lock_irqsave(&igb->tmreg_lock, flags);
502 tsauxc = rd32(E1000_TSAUXC);
503 tsim = rd32(E1000_TSIM);
504 if (on) {
505 igb_pin_extts(igb, rq->extts.index, pin);
506 tsauxc |= tsauxc_mask;
507 tsim |= tsim_mask;
508 } else {
509 tsauxc &= ~tsauxc_mask;
510 tsim &= ~tsim_mask;
511 }
512 wr32(E1000_TSAUXC, tsauxc);
513 wr32(E1000_TSIM, tsim);
514 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
515 return 0;
516
517 case PTP_CLK_REQ_PEROUT:
518 if (on) {
519 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
520 rq->perout.index);
521 if (pin < 0)
522 return -EBUSY;
523 }
524 ts.tv_sec = rq->perout.period.sec;
525 ts.tv_nsec = rq->perout.period.nsec;
526 ns = timespec64_to_ns(&ts);
527 ns = ns >> 1;
528 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
529 (ns == 250000000LL) || (ns == 500000000LL))) {
530 if (ns < 8LL)
531 return -EINVAL;
532 use_freq = 1;
533 }
534 ts = ns_to_timespec64(ns);
535 if (rq->perout.index == 1) {
536 if (use_freq) {
537 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
538 tsim_mask = 0;
539 } else {
540 tsauxc_mask = TSAUXC_EN_TT1;
541 tsim_mask = TSINTR_TT1;
542 }
543 trgttiml = E1000_TRGTTIML1;
544 trgttimh = E1000_TRGTTIMH1;
545 freqout = E1000_FREQOUT1;
546 } else {
547 if (use_freq) {
548 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
549 tsim_mask = 0;
550 } else {
551 tsauxc_mask = TSAUXC_EN_TT0;
552 tsim_mask = TSINTR_TT0;
553 }
554 trgttiml = E1000_TRGTTIML0;
555 trgttimh = E1000_TRGTTIMH0;
556 freqout = E1000_FREQOUT0;
557 }
558 spin_lock_irqsave(&igb->tmreg_lock, flags);
559 tsauxc = rd32(E1000_TSAUXC);
560 tsim = rd32(E1000_TSIM);
561 if (rq->perout.index == 1) {
562 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
563 tsim &= ~TSINTR_TT1;
564 } else {
565 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
566 tsim &= ~TSINTR_TT0;
567 }
568 if (on) {
569 int i = rq->perout.index;
570 igb_pin_perout(igb, i, pin, use_freq);
571 igb->perout[i].start.tv_sec = rq->perout.start.sec;
572 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
573 igb->perout[i].period.tv_sec = ts.tv_sec;
574 igb->perout[i].period.tv_nsec = ts.tv_nsec;
575 wr32(trgttimh, rq->perout.start.sec);
576 wr32(trgttiml, rq->perout.start.nsec);
577 if (use_freq)
578 wr32(freqout, ns);
579 tsauxc |= tsauxc_mask;
580 tsim |= tsim_mask;
581 }
582 wr32(E1000_TSAUXC, tsauxc);
583 wr32(E1000_TSIM, tsim);
584 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
585 return 0;
586
587 case PTP_CLK_REQ_PPS:
588 spin_lock_irqsave(&igb->tmreg_lock, flags);
589 tsim = rd32(E1000_TSIM);
590 if (on)
591 tsim |= TSINTR_SYS_WRAP;
592 else
593 tsim &= ~TSINTR_SYS_WRAP;
594 wr32(E1000_TSIM, tsim);
595 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
596 return 0;
597 }
598
599 return -EOPNOTSUPP;
600}
601
602static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
603 struct ptp_clock_request *rq, int on)
604{
605 return -EOPNOTSUPP;
606}
607
608static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
609 enum ptp_pin_function func, unsigned int chan)
610{
611 switch (func) {
612 case PTP_PF_NONE:
613 case PTP_PF_EXTTS:
614 case PTP_PF_PEROUT:
615 break;
616 case PTP_PF_PHYSYNC:
617 return -1;
618 }
619 return 0;
620}
621
622/**
623 * igb_ptp_tx_work
624 * @work: pointer to work struct
625 *
626 * This work function polls the TSYNCTXCTL valid bit to determine when a
627 * timestamp has been taken for the current stored skb.
628 **/
629static void igb_ptp_tx_work(struct work_struct *work)
630{
631 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
632 ptp_tx_work);
633 struct e1000_hw *hw = &adapter->hw;
634 u32 tsynctxctl;
635
636 if (!adapter->ptp_tx_skb)
637 return;
638
639 if (time_is_before_jiffies(adapter->ptp_tx_start +
640 IGB_PTP_TX_TIMEOUT)) {
641 dev_kfree_skb_any(adapter->ptp_tx_skb);
642 adapter->ptp_tx_skb = NULL;
643 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
644 adapter->tx_hwtstamp_timeouts++;
645 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
646 return;
647 }
648
649 tsynctxctl = rd32(E1000_TSYNCTXCTL);
650 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
651 igb_ptp_tx_hwtstamp(adapter);
652 else
653 /* reschedule to check later */
654 schedule_work(&adapter->ptp_tx_work);
655}
656
657static void igb_ptp_overflow_check(struct work_struct *work)
658{
659 struct igb_adapter *igb =
660 container_of(work, struct igb_adapter, ptp_overflow_work.work);
661 struct timespec64 ts;
662
663 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
664
665 pr_debug("igb overflow check at %lld.%09lu\n",
666 (long long) ts.tv_sec, ts.tv_nsec);
667
668 schedule_delayed_work(&igb->ptp_overflow_work,
669 IGB_SYSTIM_OVERFLOW_PERIOD);
670}
671
672/**
673 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
674 * @adapter: private network adapter structure
675 *
676 * This watchdog task is scheduled to detect error case where hardware has
677 * dropped an Rx packet that was timestamped when the ring is full. The
678 * particular error is rare but leaves the device in a state unable to timestamp
679 * any future packets.
680 **/
681void igb_ptp_rx_hang(struct igb_adapter *adapter)
682{
683 struct e1000_hw *hw = &adapter->hw;
684 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
685 unsigned long rx_event;
686
687 if (hw->mac.type != e1000_82576)
688 return;
689
690 /* If we don't have a valid timestamp in the registers, just update the
691 * timeout counter and exit
692 */
693 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
694 adapter->last_rx_ptp_check = jiffies;
695 return;
696 }
697
698 /* Determine the most recent watchdog or rx_timestamp event */
699 rx_event = adapter->last_rx_ptp_check;
700 if (time_after(adapter->last_rx_timestamp, rx_event))
701 rx_event = adapter->last_rx_timestamp;
702
703 /* Only need to read the high RXSTMP register to clear the lock */
704 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
705 rd32(E1000_RXSTMPH);
706 adapter->last_rx_ptp_check = jiffies;
707 adapter->rx_hwtstamp_cleared++;
708 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
709 }
710}
711
712/**
713 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
714 * @adapter: Board private structure.
715 *
716 * If we were asked to do hardware stamping and such a time stamp is
717 * available, then it must have been for this skb here because we only
718 * allow only one such packet into the queue.
719 **/
720static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
721{
722 struct e1000_hw *hw = &adapter->hw;
723 struct skb_shared_hwtstamps shhwtstamps;
724 u64 regval;
725
726 regval = rd32(E1000_TXSTMPL);
727 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
728
729 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
730 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
731 dev_kfree_skb_any(adapter->ptp_tx_skb);
732 adapter->ptp_tx_skb = NULL;
733 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
734}
735
736/**
737 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
738 * @q_vector: Pointer to interrupt specific structure
739 * @va: Pointer to address containing Rx buffer
740 * @skb: Buffer containing timestamp and packet
741 *
742 * This function is meant to retrieve a timestamp from the first buffer of an
743 * incoming frame. The value is stored in little endian format starting on
744 * byte 8.
745 **/
746void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
747 unsigned char *va,
748 struct sk_buff *skb)
749{
750 __le64 *regval = (__le64 *)va;
751
752 /* The timestamp is recorded in little endian format.
753 * DWORD: 0 1 2 3
754 * Field: Reserved Reserved SYSTIML SYSTIMH
755 */
756 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
757 le64_to_cpu(regval[1]));
758}
759
760/**
761 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
762 * @q_vector: Pointer to interrupt specific structure
763 * @skb: Buffer containing timestamp and packet
764 *
765 * This function is meant to retrieve a timestamp from the internal registers
766 * of the adapter and store it in the skb.
767 **/
768void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
769 struct sk_buff *skb)
770{
771 struct igb_adapter *adapter = q_vector->adapter;
772 struct e1000_hw *hw = &adapter->hw;
773 u64 regval;
774
775 /* If this bit is set, then the RX registers contain the time stamp. No
776 * other packet will be time stamped until we read these registers, so
777 * read the registers to make them available again. Because only one
778 * packet can be time stamped at a time, we know that the register
779 * values must belong to this one here and therefore we don't need to
780 * compare any of the additional attributes stored for it.
781 *
782 * If nothing went wrong, then it should have a shared tx_flags that we
783 * can turn into a skb_shared_hwtstamps.
784 */
785 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
786 return;
787
788 regval = rd32(E1000_RXSTMPL);
789 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
790
791 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
792
793 /* Update the last_rx_timestamp timer in order to enable watchdog check
794 * for error case of latched timestamp on a dropped packet.
795 */
796 adapter->last_rx_timestamp = jiffies;
797}
798
799/**
800 * igb_ptp_get_ts_config - get hardware time stamping config
801 * @netdev:
802 * @ifreq:
803 *
804 * Get the hwtstamp_config settings to return to the user. Rather than attempt
805 * to deconstruct the settings from the registers, just return a shadow copy
806 * of the last known settings.
807 **/
808int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
809{
810 struct igb_adapter *adapter = netdev_priv(netdev);
811 struct hwtstamp_config *config = &adapter->tstamp_config;
812
813 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
814 -EFAULT : 0;
815}
816
817/**
818 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
819 * @adapter: networking device structure
820 * @config: hwtstamp configuration
821 *
822 * Outgoing time stamping can be enabled and disabled. Play nice and
823 * disable it when requested, although it shouldn't case any overhead
824 * when no packet needs it. At most one packet in the queue may be
825 * marked for time stamping, otherwise it would be impossible to tell
826 * for sure to which packet the hardware time stamp belongs.
827 *
828 * Incoming time stamping has to be configured via the hardware
829 * filters. Not all combinations are supported, in particular event
830 * type has to be specified. Matching the kind of event packet is
831 * not supported, with the exception of "all V2 events regardless of
832 * level 2 or 4".
833 */
834static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
835 struct hwtstamp_config *config)
836{
837 struct e1000_hw *hw = &adapter->hw;
838 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
839 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
840 u32 tsync_rx_cfg = 0;
841 bool is_l4 = false;
842 bool is_l2 = false;
843 u32 regval;
844
845 /* reserved for future extensions */
846 if (config->flags)
847 return -EINVAL;
848
849 switch (config->tx_type) {
850 case HWTSTAMP_TX_OFF:
851 tsync_tx_ctl = 0;
852 case HWTSTAMP_TX_ON:
853 break;
854 default:
855 return -ERANGE;
856 }
857
858 switch (config->rx_filter) {
859 case HWTSTAMP_FILTER_NONE:
860 tsync_rx_ctl = 0;
861 break;
862 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
863 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
864 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
865 is_l4 = true;
866 break;
867 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
868 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
869 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
870 is_l4 = true;
871 break;
872 case HWTSTAMP_FILTER_PTP_V2_EVENT:
873 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
874 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
875 case HWTSTAMP_FILTER_PTP_V2_SYNC:
876 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
877 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
878 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
879 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
880 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
881 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
882 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
883 is_l2 = true;
884 is_l4 = true;
885 break;
886 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
887 case HWTSTAMP_FILTER_ALL:
888 /* 82576 cannot timestamp all packets, which it needs to do to
889 * support both V1 Sync and Delay_Req messages
890 */
891 if (hw->mac.type != e1000_82576) {
892 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
893 config->rx_filter = HWTSTAMP_FILTER_ALL;
894 break;
895 }
896 /* fall through */
897 default:
898 config->rx_filter = HWTSTAMP_FILTER_NONE;
899 return -ERANGE;
900 }
901
902 if (hw->mac.type == e1000_82575) {
903 if (tsync_rx_ctl | tsync_tx_ctl)
904 return -EINVAL;
905 return 0;
906 }
907
908 /* Per-packet timestamping only works if all packets are
909 * timestamped, so enable timestamping in all packets as
910 * long as one Rx filter was configured.
911 */
912 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
913 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
914 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
915 config->rx_filter = HWTSTAMP_FILTER_ALL;
916 is_l2 = true;
917 is_l4 = true;
918
919 if ((hw->mac.type == e1000_i210) ||
920 (hw->mac.type == e1000_i211)) {
921 regval = rd32(E1000_RXPBS);
922 regval |= E1000_RXPBS_CFG_TS_EN;
923 wr32(E1000_RXPBS, regval);
924 }
925 }
926
927 /* enable/disable TX */
928 regval = rd32(E1000_TSYNCTXCTL);
929 regval &= ~E1000_TSYNCTXCTL_ENABLED;
930 regval |= tsync_tx_ctl;
931 wr32(E1000_TSYNCTXCTL, regval);
932
933 /* enable/disable RX */
934 regval = rd32(E1000_TSYNCRXCTL);
935 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
936 regval |= tsync_rx_ctl;
937 wr32(E1000_TSYNCRXCTL, regval);
938
939 /* define which PTP packets are time stamped */
940 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
941
942 /* define ethertype filter for timestamped packets */
943 if (is_l2)
944 wr32(E1000_ETQF(3),
945 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
946 E1000_ETQF_1588 | /* enable timestamping */
947 ETH_P_1588)); /* 1588 eth protocol type */
948 else
949 wr32(E1000_ETQF(3), 0);
950
951 /* L4 Queue Filter[3]: filter by destination port and protocol */
952 if (is_l4) {
953 u32 ftqf = (IPPROTO_UDP /* UDP */
954 | E1000_FTQF_VF_BP /* VF not compared */
955 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
956 | E1000_FTQF_MASK); /* mask all inputs */
957 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
958
959 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
960 wr32(E1000_IMIREXT(3),
961 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
962 if (hw->mac.type == e1000_82576) {
963 /* enable source port check */
964 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
965 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
966 }
967 wr32(E1000_FTQF(3), ftqf);
968 } else {
969 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
970 }
971 wrfl();
972
973 /* clear TX/RX time stamp registers, just to be sure */
974 regval = rd32(E1000_TXSTMPL);
975 regval = rd32(E1000_TXSTMPH);
976 regval = rd32(E1000_RXSTMPL);
977 regval = rd32(E1000_RXSTMPH);
978
979 return 0;
980}
981
982/**
983 * igb_ptp_set_ts_config - set hardware time stamping config
984 * @netdev:
985 * @ifreq:
986 *
987 **/
988int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
989{
990 struct igb_adapter *adapter = netdev_priv(netdev);
991 struct hwtstamp_config config;
992 int err;
993
994 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
995 return -EFAULT;
996
997 err = igb_ptp_set_timestamp_mode(adapter, &config);
998 if (err)
999 return err;
1000
1001 /* save these settings for future reference */
1002 memcpy(&adapter->tstamp_config, &config,
1003 sizeof(adapter->tstamp_config));
1004
1005 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1006 -EFAULT : 0;
1007}
1008
1009void igb_ptp_init(struct igb_adapter *adapter)
1010{
1011 struct e1000_hw *hw = &adapter->hw;
1012 struct net_device *netdev = adapter->netdev;
1013 int i;
1014
1015 switch (hw->mac.type) {
1016 case e1000_82576:
1017 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1018 adapter->ptp_caps.owner = THIS_MODULE;
1019 adapter->ptp_caps.max_adj = 999999881;
1020 adapter->ptp_caps.n_ext_ts = 0;
1021 adapter->ptp_caps.pps = 0;
1022 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1023 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1024 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1025 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1026 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1027 adapter->cc.read = igb_ptp_read_82576;
1028 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1029 adapter->cc.mult = 1;
1030 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1031 /* Dial the nominal frequency. */
1032 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1033 break;
1034 case e1000_82580:
1035 case e1000_i354:
1036 case e1000_i350:
1037 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1038 adapter->ptp_caps.owner = THIS_MODULE;
1039 adapter->ptp_caps.max_adj = 62499999;
1040 adapter->ptp_caps.n_ext_ts = 0;
1041 adapter->ptp_caps.pps = 0;
1042 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1043 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1044 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1045 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1046 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1047 adapter->cc.read = igb_ptp_read_82580;
1048 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1049 adapter->cc.mult = 1;
1050 adapter->cc.shift = 0;
1051 /* Enable the timer functions by clearing bit 31. */
1052 wr32(E1000_TSAUXC, 0x0);
1053 break;
1054 case e1000_i210:
1055 case e1000_i211:
1056 for (i = 0; i < IGB_N_SDP; i++) {
1057 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1058
1059 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1060 ppd->index = i;
1061 ppd->func = PTP_PF_NONE;
1062 }
1063 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1064 adapter->ptp_caps.owner = THIS_MODULE;
1065 adapter->ptp_caps.max_adj = 62499999;
1066 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1067 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1068 adapter->ptp_caps.n_pins = IGB_N_SDP;
1069 adapter->ptp_caps.pps = 1;
1070 adapter->ptp_caps.pin_config = adapter->sdp_config;
1071 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1072 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1073 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1074 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1075 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1076 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1077 /* Enable the timer functions by clearing bit 31. */
1078 wr32(E1000_TSAUXC, 0x0);
1079 break;
1080 default:
1081 adapter->ptp_clock = NULL;
1082 return;
1083 }
1084
1085 wrfl();
1086
1087 spin_lock_init(&adapter->tmreg_lock);
1088 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1089
1090 /* Initialize the clock and overflow work for devices that need it. */
1091 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1092 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1093
1094 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
1095 } else {
1096 timecounter_init(&adapter->tc, &adapter->cc,
1097 ktime_to_ns(ktime_get_real()));
1098
1099 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1100 igb_ptp_overflow_check);
1101
1102 schedule_delayed_work(&adapter->ptp_overflow_work,
1103 IGB_SYSTIM_OVERFLOW_PERIOD);
1104 }
1105
1106 /* Initialize the time sync interrupts for devices that support it. */
1107 if (hw->mac.type >= e1000_82580) {
1108 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1109 wr32(E1000_IMS, E1000_IMS_TS);
1110 }
1111
1112 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1113 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1114
1115 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1116 &adapter->pdev->dev);
1117 if (IS_ERR(adapter->ptp_clock)) {
1118 adapter->ptp_clock = NULL;
1119 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1120 } else {
1121 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1122 adapter->netdev->name);
1123 adapter->flags |= IGB_FLAG_PTP;
1124 }
1125}
1126
1127/**
1128 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1129 * @adapter: Board private structure.
1130 *
1131 * This function stops the PTP support and cancels the delayed work.
1132 **/
1133void igb_ptp_stop(struct igb_adapter *adapter)
1134{
1135 switch (adapter->hw.mac.type) {
1136 case e1000_82576:
1137 case e1000_82580:
1138 case e1000_i354:
1139 case e1000_i350:
1140 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1141 break;
1142 case e1000_i210:
1143 case e1000_i211:
1144 /* No delayed work to cancel. */
1145 break;
1146 default:
1147 return;
1148 }
1149
1150 cancel_work_sync(&adapter->ptp_tx_work);
1151 if (adapter->ptp_tx_skb) {
1152 dev_kfree_skb_any(adapter->ptp_tx_skb);
1153 adapter->ptp_tx_skb = NULL;
1154 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1155 }
1156
1157 if (adapter->ptp_clock) {
1158 ptp_clock_unregister(adapter->ptp_clock);
1159 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1160 adapter->netdev->name);
1161 adapter->flags &= ~IGB_FLAG_PTP;
1162 }
1163}
1164
1165/**
1166 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1167 * @adapter: Board private structure.
1168 *
1169 * This function handles the reset work required to re-enable the PTP device.
1170 **/
1171void igb_ptp_reset(struct igb_adapter *adapter)
1172{
1173 struct e1000_hw *hw = &adapter->hw;
1174 unsigned long flags;
1175
1176 if (!(adapter->flags & IGB_FLAG_PTP))
1177 return;
1178
1179 /* reset the tstamp_config */
1180 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1181
1182 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1183
1184 switch (adapter->hw.mac.type) {
1185 case e1000_82576:
1186 /* Dial the nominal frequency. */
1187 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1188 break;
1189 case e1000_82580:
1190 case e1000_i354:
1191 case e1000_i350:
1192 case e1000_i210:
1193 case e1000_i211:
1194 wr32(E1000_TSAUXC, 0x0);
1195 wr32(E1000_TSSDP, 0x0);
1196 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1197 wr32(E1000_IMS, E1000_IMS_TS);
1198 break;
1199 default:
1200 /* No work to do. */
1201 goto out;
1202 }
1203
1204 /* Re-initialize the timer. */
1205 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1206 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1207
1208 igb_ptp_write_i210(adapter, &ts);
1209 } else {
1210 timecounter_init(&adapter->tc, &adapter->cc,
1211 ktime_to_ns(ktime_get_real()));
1212 }
1213out:
1214 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1215}