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1/*
2 * Copyright © 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * Authors: David Woodhouse <dwmw2@infradead.org>
14 */
15
16#include <linux/intel-iommu.h>
17#include <linux/mmu_notifier.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/intel-svm.h>
21#include <linux/rculist.h>
22#include <linux/pci.h>
23#include <linux/pci-ats.h>
24#include <linux/dmar.h>
25#include <linux/interrupt.h>
26
27static irqreturn_t prq_event_thread(int irq, void *d);
28
29struct pasid_entry {
30 u64 val;
31};
32
33struct pasid_state_entry {
34 u64 val;
35};
36
37int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
38{
39 struct page *pages;
40 int order;
41
42 order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT;
43 if (order < 0)
44 order = 0;
45
46 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
47 if (!pages) {
48 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
49 iommu->name);
50 return -ENOMEM;
51 }
52 iommu->pasid_table = page_address(pages);
53 pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
54
55 if (ecap_dis(iommu->ecap)) {
56 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
57 if (pages)
58 iommu->pasid_state_table = page_address(pages);
59 else
60 pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
61 iommu->name);
62 }
63
64 idr_init(&iommu->pasid_idr);
65
66 return 0;
67}
68
69int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
70{
71 int order;
72
73 order = ecap_pss(iommu->ecap) + 7 - PAGE_SHIFT;
74 if (order < 0)
75 order = 0;
76
77 if (iommu->pasid_table) {
78 free_pages((unsigned long)iommu->pasid_table, order);
79 iommu->pasid_table = NULL;
80 }
81 if (iommu->pasid_state_table) {
82 free_pages((unsigned long)iommu->pasid_state_table, order);
83 iommu->pasid_state_table = NULL;
84 }
85 idr_destroy(&iommu->pasid_idr);
86 return 0;
87}
88
89#define PRQ_ORDER 0
90
91int intel_svm_enable_prq(struct intel_iommu *iommu)
92{
93 struct page *pages;
94 int irq, ret;
95
96 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
97 if (!pages) {
98 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
99 iommu->name);
100 return -ENOMEM;
101 }
102 iommu->prq = page_address(pages);
103
104 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
105 if (irq <= 0) {
106 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
107 iommu->name);
108 ret = -EINVAL;
109 err:
110 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
111 iommu->prq = NULL;
112 return ret;
113 }
114 iommu->pr_irq = irq;
115
116 snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
117
118 ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
119 iommu->prq_name, iommu);
120 if (ret) {
121 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
122 iommu->name);
123 dmar_free_hwirq(irq);
124 goto err;
125 }
126 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
127 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
128 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
129
130 return 0;
131}
132
133int intel_svm_finish_prq(struct intel_iommu *iommu)
134{
135 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
136 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
137 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
138
139 free_irq(iommu->pr_irq, iommu);
140 dmar_free_hwirq(iommu->pr_irq);
141 iommu->pr_irq = 0;
142
143 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
144 iommu->prq = NULL;
145
146 return 0;
147}
148
149static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
150 unsigned long address, unsigned long pages, int ih, int gl)
151{
152 struct qi_desc desc;
153
154 if (pages == -1) {
155 /* For global kernel pages we have to flush them in *all* PASIDs
156 * because that's the only option the hardware gives us. Despite
157 * the fact that they are actually only accessible through one. */
158 if (gl)
159 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
160 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
161 else
162 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
163 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
164 desc.high = 0;
165 } else {
166 int mask = ilog2(__roundup_pow_of_two(pages));
167
168 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
169 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
170 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
171 QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
172 }
173 qi_submit_sync(&desc, svm->iommu);
174
175 if (sdev->dev_iotlb) {
176 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
177 QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
178 if (pages == -1) {
179 desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
180 } else if (pages > 1) {
181 /* The least significant zero bit indicates the size. So,
182 * for example, an "address" value of 0x12345f000 will
183 * flush from 0x123440000 to 0x12347ffff (256KiB). */
184 unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
185 unsigned long mask = __rounddown_pow_of_two(address ^ last);;
186
187 desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
188 } else {
189 desc.high = QI_DEV_EIOTLB_ADDR(address);
190 }
191 qi_submit_sync(&desc, svm->iommu);
192 }
193}
194
195static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
196 unsigned long pages, int ih, int gl)
197{
198 struct intel_svm_dev *sdev;
199
200 /* Try deferred invalidate if available */
201 if (svm->iommu->pasid_state_table &&
202 !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
203 return;
204
205 rcu_read_lock();
206 list_for_each_entry_rcu(sdev, &svm->devs, list)
207 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
208 rcu_read_unlock();
209}
210
211static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
212 unsigned long address, pte_t pte)
213{
214 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
215
216 intel_flush_svm_range(svm, address, 1, 1, 0);
217}
218
219static void intel_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm,
220 unsigned long address)
221{
222 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
223
224 intel_flush_svm_range(svm, address, 1, 1, 0);
225}
226
227/* Pages have been freed at this point */
228static void intel_invalidate_range(struct mmu_notifier *mn,
229 struct mm_struct *mm,
230 unsigned long start, unsigned long end)
231{
232 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
233
234 intel_flush_svm_range(svm, start,
235 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
236}
237
238
239static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
240{
241 struct qi_desc desc;
242
243 desc.high = 0;
244 desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
245
246 qi_submit_sync(&desc, svm->iommu);
247}
248
249static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
250{
251 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
252 struct intel_svm_dev *sdev;
253
254 /* This might end up being called from exit_mmap(), *before* the page
255 * tables are cleared. And __mmu_notifier_release() will delete us from
256 * the list of notifiers so that our invalidate_range() callback doesn't
257 * get called when the page tables are cleared. So we need to protect
258 * against hardware accessing those page tables.
259 *
260 * We do it by clearing the entry in the PASID table and then flushing
261 * the IOTLB and the PASID table caches. This might upset hardware;
262 * perhaps we'll want to point the PASID to a dummy PGD (like the zero
263 * page) so that we end up taking a fault that the hardware really
264 * *has* to handle gracefully without affecting other processes.
265 */
266 svm->iommu->pasid_table[svm->pasid].val = 0;
267 wmb();
268
269 rcu_read_lock();
270 list_for_each_entry_rcu(sdev, &svm->devs, list) {
271 intel_flush_pasid_dev(svm, sdev, svm->pasid);
272 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
273 }
274 rcu_read_unlock();
275
276}
277
278static const struct mmu_notifier_ops intel_mmuops = {
279 .release = intel_mm_release,
280 .change_pte = intel_change_pte,
281 .invalidate_page = intel_invalidate_page,
282 .invalidate_range = intel_invalidate_range,
283};
284
285static DEFINE_MUTEX(pasid_mutex);
286
287int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
288{
289 struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
290 struct intel_svm_dev *sdev;
291 struct intel_svm *svm = NULL;
292 struct mm_struct *mm = NULL;
293 int pasid_max;
294 int ret;
295
296 if (WARN_ON(!iommu))
297 return -EINVAL;
298
299 if (dev_is_pci(dev)) {
300 pasid_max = pci_max_pasids(to_pci_dev(dev));
301 if (pasid_max < 0)
302 return -EINVAL;
303 } else
304 pasid_max = 1 << 20;
305
306 if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
307 if (!ecap_srs(iommu->ecap))
308 return -EINVAL;
309 } else if (pasid) {
310 mm = get_task_mm(current);
311 BUG_ON(!mm);
312 }
313
314 mutex_lock(&pasid_mutex);
315 if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
316 int i;
317
318 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
319 if (svm->mm != mm ||
320 (svm->flags & SVM_FLAG_PRIVATE_PASID))
321 continue;
322
323 if (svm->pasid >= pasid_max) {
324 dev_warn(dev,
325 "Limited PASID width. Cannot use existing PASID %d\n",
326 svm->pasid);
327 ret = -ENOSPC;
328 goto out;
329 }
330
331 list_for_each_entry(sdev, &svm->devs, list) {
332 if (dev == sdev->dev) {
333 if (sdev->ops != ops) {
334 ret = -EBUSY;
335 goto out;
336 }
337 sdev->users++;
338 goto success;
339 }
340 }
341
342 break;
343 }
344 }
345
346 sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
347 if (!sdev) {
348 ret = -ENOMEM;
349 goto out;
350 }
351 sdev->dev = dev;
352
353 ret = intel_iommu_enable_pasid(iommu, sdev);
354 if (ret || !pasid) {
355 /* If they don't actually want to assign a PASID, this is
356 * just an enabling check/preparation. */
357 kfree(sdev);
358 goto out;
359 }
360 /* Finish the setup now we know we're keeping it */
361 sdev->users = 1;
362 sdev->ops = ops;
363 init_rcu_head(&sdev->rcu);
364
365 if (!svm) {
366 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
367 if (!svm) {
368 ret = -ENOMEM;
369 kfree(sdev);
370 goto out;
371 }
372 svm->iommu = iommu;
373
374 if (pasid_max > 2 << ecap_pss(iommu->ecap))
375 pasid_max = 2 << ecap_pss(iommu->ecap);
376
377 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
378 ret = idr_alloc(&iommu->pasid_idr, svm,
379 !!cap_caching_mode(iommu->cap),
380 pasid_max - 1, GFP_KERNEL);
381 if (ret < 0) {
382 kfree(svm);
383 goto out;
384 }
385 svm->pasid = ret;
386 svm->notifier.ops = &intel_mmuops;
387 svm->mm = mm;
388 svm->flags = flags;
389 INIT_LIST_HEAD_RCU(&svm->devs);
390 ret = -ENOMEM;
391 if (mm) {
392 ret = mmu_notifier_register(&svm->notifier, mm);
393 if (ret) {
394 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
395 kfree(svm);
396 kfree(sdev);
397 goto out;
398 }
399 iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
400 } else
401 iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
402 wmb();
403 /* In caching mode, we still have to flush with PASID 0 when
404 * a PASID table entry becomes present. Not entirely clear
405 * *why* that would be the case — surely we could just issue
406 * a flush with the PASID value that we've changed? The PASID
407 * is the index into the table, after all. It's not like domain
408 * IDs in the case of the equivalent context-entry change in
409 * caching mode. And for that matter it's not entirely clear why
410 * a VMM would be in the business of caching the PASID table
411 * anyway. Surely that can be left entirely to the guest? */
412 if (cap_caching_mode(iommu->cap))
413 intel_flush_pasid_dev(svm, sdev, 0);
414 }
415 list_add_rcu(&sdev->list, &svm->devs);
416
417 success:
418 *pasid = svm->pasid;
419 ret = 0;
420 out:
421 mutex_unlock(&pasid_mutex);
422 if (mm)
423 mmput(mm);
424 return ret;
425}
426EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
427
428int intel_svm_unbind_mm(struct device *dev, int pasid)
429{
430 struct intel_svm_dev *sdev;
431 struct intel_iommu *iommu;
432 struct intel_svm *svm;
433 int ret = -EINVAL;
434
435 mutex_lock(&pasid_mutex);
436 iommu = intel_svm_device_to_iommu(dev);
437 if (!iommu || !iommu->pasid_table)
438 goto out;
439
440 svm = idr_find(&iommu->pasid_idr, pasid);
441 if (!svm)
442 goto out;
443
444 list_for_each_entry(sdev, &svm->devs, list) {
445 if (dev == sdev->dev) {
446 ret = 0;
447 sdev->users--;
448 if (!sdev->users) {
449 list_del_rcu(&sdev->list);
450 /* Flush the PASID cache and IOTLB for this device.
451 * Note that we do depend on the hardware *not* using
452 * the PASID any more. Just as we depend on other
453 * devices never using PASIDs that they have no right
454 * to use. We have a *shared* PASID table, because it's
455 * large and has to be physically contiguous. So it's
456 * hard to be as defensive as we might like. */
457 intel_flush_pasid_dev(svm, sdev, svm->pasid);
458 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
459 kfree_rcu(sdev, rcu);
460
461 if (list_empty(&svm->devs)) {
462
463 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
464 if (svm->mm)
465 mmu_notifier_unregister(&svm->notifier, svm->mm);
466
467 /* We mandate that no page faults may be outstanding
468 * for the PASID when intel_svm_unbind_mm() is called.
469 * If that is not obeyed, subtle errors will happen.
470 * Let's make them less subtle... */
471 memset(svm, 0x6b, sizeof(*svm));
472 kfree(svm);
473 }
474 }
475 break;
476 }
477 }
478 out:
479 mutex_unlock(&pasid_mutex);
480
481 return ret;
482}
483EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
484
485/* Page request queue descriptor */
486struct page_req_dsc {
487 u64 srr:1;
488 u64 bof:1;
489 u64 pasid_present:1;
490 u64 lpig:1;
491 u64 pasid:20;
492 u64 bus:8;
493 u64 private:23;
494 u64 prg_index:9;
495 u64 rd_req:1;
496 u64 wr_req:1;
497 u64 exe_req:1;
498 u64 priv_req:1;
499 u64 devfn:8;
500 u64 addr:52;
501};
502
503#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
504
505static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
506{
507 unsigned long requested = 0;
508
509 if (req->exe_req)
510 requested |= VM_EXEC;
511
512 if (req->rd_req)
513 requested |= VM_READ;
514
515 if (req->wr_req)
516 requested |= VM_WRITE;
517
518 return (requested & ~vma->vm_flags) != 0;
519}
520
521static irqreturn_t prq_event_thread(int irq, void *d)
522{
523 struct intel_iommu *iommu = d;
524 struct intel_svm *svm = NULL;
525 int head, tail, handled = 0;
526
527 /* Clear PPR bit before reading head/tail registers, to
528 * ensure that we get a new interrupt if needed. */
529 writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
530
531 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
532 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
533 while (head != tail) {
534 struct intel_svm_dev *sdev;
535 struct vm_area_struct *vma;
536 struct page_req_dsc *req;
537 struct qi_desc resp;
538 int ret, result;
539 u64 address;
540
541 handled = 1;
542
543 req = &iommu->prq[head / sizeof(*req)];
544
545 result = QI_RESP_FAILURE;
546 address = (u64)req->addr << VTD_PAGE_SHIFT;
547 if (!req->pasid_present) {
548 pr_err("%s: Page request without PASID: %08llx %08llx\n",
549 iommu->name, ((unsigned long long *)req)[0],
550 ((unsigned long long *)req)[1]);
551 goto bad_req;
552 }
553
554 if (!svm || svm->pasid != req->pasid) {
555 rcu_read_lock();
556 svm = idr_find(&iommu->pasid_idr, req->pasid);
557 /* It *can't* go away, because the driver is not permitted
558 * to unbind the mm while any page faults are outstanding.
559 * So we only need RCU to protect the internal idr code. */
560 rcu_read_unlock();
561
562 if (!svm) {
563 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
564 iommu->name, req->pasid, ((unsigned long long *)req)[0],
565 ((unsigned long long *)req)[1]);
566 goto no_pasid;
567 }
568 }
569
570 result = QI_RESP_INVALID;
571 /* Since we're using init_mm.pgd directly, we should never take
572 * any faults on kernel addresses. */
573 if (!svm->mm)
574 goto bad_req;
575 /* If the mm is already defunct, don't handle faults. */
576 if (!atomic_inc_not_zero(&svm->mm->mm_users))
577 goto bad_req;
578 down_read(&svm->mm->mmap_sem);
579 vma = find_extend_vma(svm->mm, address);
580 if (!vma || address < vma->vm_start)
581 goto invalid;
582
583 if (access_error(vma, req))
584 goto invalid;
585
586 ret = handle_mm_fault(svm->mm, vma, address,
587 req->wr_req ? FAULT_FLAG_WRITE : 0);
588 if (ret & VM_FAULT_ERROR)
589 goto invalid;
590
591 result = QI_RESP_SUCCESS;
592 invalid:
593 up_read(&svm->mm->mmap_sem);
594 mmput(svm->mm);
595 bad_req:
596 /* Accounting for major/minor faults? */
597 rcu_read_lock();
598 list_for_each_entry_rcu(sdev, &svm->devs, list) {
599 if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
600 break;
601 }
602 /* Other devices can go away, but the drivers are not permitted
603 * to unbind while any page faults might be in flight. So it's
604 * OK to drop the 'lock' here now we have it. */
605 rcu_read_unlock();
606
607 if (WARN_ON(&sdev->list == &svm->devs))
608 sdev = NULL;
609
610 if (sdev && sdev->ops && sdev->ops->fault_cb) {
611 int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
612 (req->exe_req << 1) | (req->priv_req);
613 sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
614 }
615 /* We get here in the error case where the PASID lookup failed,
616 and these can be NULL. Do not use them below this point! */
617 sdev = NULL;
618 svm = NULL;
619 no_pasid:
620 if (req->lpig) {
621 /* Page Group Response */
622 resp.low = QI_PGRP_PASID(req->pasid) |
623 QI_PGRP_DID((req->bus << 8) | req->devfn) |
624 QI_PGRP_PASID_P(req->pasid_present) |
625 QI_PGRP_RESP_TYPE;
626 resp.high = QI_PGRP_IDX(req->prg_index) |
627 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
628
629 qi_submit_sync(&resp, iommu);
630 } else if (req->srr) {
631 /* Page Stream Response */
632 resp.low = QI_PSTRM_IDX(req->prg_index) |
633 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
634 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
635 resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
636 QI_PSTRM_RESP_CODE(result);
637
638 qi_submit_sync(&resp, iommu);
639 }
640
641 head = (head + sizeof(*req)) & PRQ_RING_MASK;
642 }
643
644 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
645
646 return IRQ_RETVAL(handled);
647}