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1/*
2 * Copyright © 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * Authors: David Woodhouse <dwmw2@infradead.org>
14 */
15
16#include <linux/intel-iommu.h>
17#include <linux/mmu_notifier.h>
18#include <linux/sched.h>
19#include <linux/sched/mm.h>
20#include <linux/slab.h>
21#include <linux/intel-svm.h>
22#include <linux/rculist.h>
23#include <linux/pci.h>
24#include <linux/pci-ats.h>
25#include <linux/dmar.h>
26#include <linux/interrupt.h>
27#include <asm/page.h>
28
29#define PASID_ENTRY_P BIT_ULL(0)
30#define PASID_ENTRY_FLPM_5LP BIT_ULL(9)
31#define PASID_ENTRY_SRE BIT_ULL(11)
32
33static irqreturn_t prq_event_thread(int irq, void *d);
34
35struct pasid_entry {
36 u64 val;
37};
38
39struct pasid_state_entry {
40 u64 val;
41};
42
43int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
44{
45 struct page *pages;
46 int order;
47
48 if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
49 !cap_fl1gp_support(iommu->cap))
50 return -EINVAL;
51
52 if (cpu_feature_enabled(X86_FEATURE_LA57) &&
53 !cap_5lp_support(iommu->cap))
54 return -EINVAL;
55
56 /* Start at 2 because it's defined as 2^(1+PSS) */
57 iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
58
59 /* Eventually I'm promised we will get a multi-level PASID table
60 * and it won't have to be physically contiguous. Until then,
61 * limit the size because 8MiB contiguous allocations can be hard
62 * to come by. The limit of 0x20000, which is 1MiB for each of
63 * the PASID and PASID-state tables, is somewhat arbitrary. */
64 if (iommu->pasid_max > 0x20000)
65 iommu->pasid_max = 0x20000;
66
67 order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
68 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
69 if (!pages) {
70 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
71 iommu->name);
72 return -ENOMEM;
73 }
74 iommu->pasid_table = page_address(pages);
75 pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
76
77 if (ecap_dis(iommu->ecap)) {
78 /* Just making it explicit... */
79 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
80 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
81 if (pages)
82 iommu->pasid_state_table = page_address(pages);
83 else
84 pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
85 iommu->name);
86 }
87
88 idr_init(&iommu->pasid_idr);
89
90 return 0;
91}
92
93int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
94{
95 int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
96
97 if (iommu->pasid_table) {
98 free_pages((unsigned long)iommu->pasid_table, order);
99 iommu->pasid_table = NULL;
100 }
101 if (iommu->pasid_state_table) {
102 free_pages((unsigned long)iommu->pasid_state_table, order);
103 iommu->pasid_state_table = NULL;
104 }
105 idr_destroy(&iommu->pasid_idr);
106 return 0;
107}
108
109#define PRQ_ORDER 0
110
111int intel_svm_enable_prq(struct intel_iommu *iommu)
112{
113 struct page *pages;
114 int irq, ret;
115
116 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
117 if (!pages) {
118 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
119 iommu->name);
120 return -ENOMEM;
121 }
122 iommu->prq = page_address(pages);
123
124 irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
125 if (irq <= 0) {
126 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
127 iommu->name);
128 ret = -EINVAL;
129 err:
130 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
131 iommu->prq = NULL;
132 return ret;
133 }
134 iommu->pr_irq = irq;
135
136 snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
137
138 ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
139 iommu->prq_name, iommu);
140 if (ret) {
141 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
142 iommu->name);
143 dmar_free_hwirq(irq);
144 iommu->pr_irq = 0;
145 goto err;
146 }
147 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
148 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
149 dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
150
151 return 0;
152}
153
154int intel_svm_finish_prq(struct intel_iommu *iommu)
155{
156 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
157 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
158 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
159
160 if (iommu->pr_irq) {
161 free_irq(iommu->pr_irq, iommu);
162 dmar_free_hwirq(iommu->pr_irq);
163 iommu->pr_irq = 0;
164 }
165
166 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
167 iommu->prq = NULL;
168
169 return 0;
170}
171
172static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
173 unsigned long address, unsigned long pages, int ih, int gl)
174{
175 struct qi_desc desc;
176
177 if (pages == -1) {
178 /* For global kernel pages we have to flush them in *all* PASIDs
179 * because that's the only option the hardware gives us. Despite
180 * the fact that they are actually only accessible through one. */
181 if (gl)
182 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
183 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
184 else
185 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
186 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
187 desc.high = 0;
188 } else {
189 int mask = ilog2(__roundup_pow_of_two(pages));
190
191 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
192 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
193 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
194 QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
195 }
196 qi_submit_sync(&desc, svm->iommu);
197
198 if (sdev->dev_iotlb) {
199 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
200 QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
201 if (pages == -1) {
202 desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
203 } else if (pages > 1) {
204 /* The least significant zero bit indicates the size. So,
205 * for example, an "address" value of 0x12345f000 will
206 * flush from 0x123440000 to 0x12347ffff (256KiB). */
207 unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
208 unsigned long mask = __rounddown_pow_of_two(address ^ last);
209
210 desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
211 } else {
212 desc.high = QI_DEV_EIOTLB_ADDR(address);
213 }
214 qi_submit_sync(&desc, svm->iommu);
215 }
216}
217
218static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
219 unsigned long pages, int ih, int gl)
220{
221 struct intel_svm_dev *sdev;
222
223 /* Try deferred invalidate if available */
224 if (svm->iommu->pasid_state_table &&
225 !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
226 return;
227
228 rcu_read_lock();
229 list_for_each_entry_rcu(sdev, &svm->devs, list)
230 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
231 rcu_read_unlock();
232}
233
234static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
235 unsigned long address, pte_t pte)
236{
237 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
238
239 intel_flush_svm_range(svm, address, 1, 1, 0);
240}
241
242/* Pages have been freed at this point */
243static void intel_invalidate_range(struct mmu_notifier *mn,
244 struct mm_struct *mm,
245 unsigned long start, unsigned long end)
246{
247 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
248
249 intel_flush_svm_range(svm, start,
250 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
251}
252
253
254static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
255{
256 struct qi_desc desc;
257
258 desc.high = 0;
259 desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
260
261 qi_submit_sync(&desc, svm->iommu);
262}
263
264static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
265{
266 struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
267 struct intel_svm_dev *sdev;
268
269 /* This might end up being called from exit_mmap(), *before* the page
270 * tables are cleared. And __mmu_notifier_release() will delete us from
271 * the list of notifiers so that our invalidate_range() callback doesn't
272 * get called when the page tables are cleared. So we need to protect
273 * against hardware accessing those page tables.
274 *
275 * We do it by clearing the entry in the PASID table and then flushing
276 * the IOTLB and the PASID table caches. This might upset hardware;
277 * perhaps we'll want to point the PASID to a dummy PGD (like the zero
278 * page) so that we end up taking a fault that the hardware really
279 * *has* to handle gracefully without affecting other processes.
280 */
281 svm->iommu->pasid_table[svm->pasid].val = 0;
282 wmb();
283
284 rcu_read_lock();
285 list_for_each_entry_rcu(sdev, &svm->devs, list) {
286 intel_flush_pasid_dev(svm, sdev, svm->pasid);
287 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
288 }
289 rcu_read_unlock();
290
291}
292
293static const struct mmu_notifier_ops intel_mmuops = {
294 .flags = MMU_INVALIDATE_DOES_NOT_BLOCK,
295 .release = intel_mm_release,
296 .change_pte = intel_change_pte,
297 .invalidate_range = intel_invalidate_range,
298};
299
300static DEFINE_MUTEX(pasid_mutex);
301
302int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
303{
304 struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
305 struct intel_svm_dev *sdev;
306 struct intel_svm *svm = NULL;
307 struct mm_struct *mm = NULL;
308 u64 pasid_entry_val;
309 int pasid_max;
310 int ret;
311
312 if (WARN_ON(!iommu || !iommu->pasid_table))
313 return -EINVAL;
314
315 if (dev_is_pci(dev)) {
316 pasid_max = pci_max_pasids(to_pci_dev(dev));
317 if (pasid_max < 0)
318 return -EINVAL;
319 } else
320 pasid_max = 1 << 20;
321
322 if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
323 if (!ecap_srs(iommu->ecap))
324 return -EINVAL;
325 } else if (pasid) {
326 mm = get_task_mm(current);
327 BUG_ON(!mm);
328 }
329
330 mutex_lock(&pasid_mutex);
331 if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
332 int i;
333
334 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
335 if (svm->mm != mm ||
336 (svm->flags & SVM_FLAG_PRIVATE_PASID))
337 continue;
338
339 if (svm->pasid >= pasid_max) {
340 dev_warn(dev,
341 "Limited PASID width. Cannot use existing PASID %d\n",
342 svm->pasid);
343 ret = -ENOSPC;
344 goto out;
345 }
346
347 list_for_each_entry(sdev, &svm->devs, list) {
348 if (dev == sdev->dev) {
349 if (sdev->ops != ops) {
350 ret = -EBUSY;
351 goto out;
352 }
353 sdev->users++;
354 goto success;
355 }
356 }
357
358 break;
359 }
360 }
361
362 sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
363 if (!sdev) {
364 ret = -ENOMEM;
365 goto out;
366 }
367 sdev->dev = dev;
368
369 ret = intel_iommu_enable_pasid(iommu, sdev);
370 if (ret || !pasid) {
371 /* If they don't actually want to assign a PASID, this is
372 * just an enabling check/preparation. */
373 kfree(sdev);
374 goto out;
375 }
376 /* Finish the setup now we know we're keeping it */
377 sdev->users = 1;
378 sdev->ops = ops;
379 init_rcu_head(&sdev->rcu);
380
381 if (!svm) {
382 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
383 if (!svm) {
384 ret = -ENOMEM;
385 kfree(sdev);
386 goto out;
387 }
388 svm->iommu = iommu;
389
390 if (pasid_max > iommu->pasid_max)
391 pasid_max = iommu->pasid_max;
392
393 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
394 ret = idr_alloc(&iommu->pasid_idr, svm,
395 !!cap_caching_mode(iommu->cap),
396 pasid_max - 1, GFP_KERNEL);
397 if (ret < 0) {
398 kfree(svm);
399 kfree(sdev);
400 goto out;
401 }
402 svm->pasid = ret;
403 svm->notifier.ops = &intel_mmuops;
404 svm->mm = mm;
405 svm->flags = flags;
406 INIT_LIST_HEAD_RCU(&svm->devs);
407 ret = -ENOMEM;
408 if (mm) {
409 ret = mmu_notifier_register(&svm->notifier, mm);
410 if (ret) {
411 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
412 kfree(svm);
413 kfree(sdev);
414 goto out;
415 }
416 pasid_entry_val = (u64)__pa(mm->pgd) | PASID_ENTRY_P;
417 } else
418 pasid_entry_val = (u64)__pa(init_mm.pgd) |
419 PASID_ENTRY_P | PASID_ENTRY_SRE;
420 if (cpu_feature_enabled(X86_FEATURE_LA57))
421 pasid_entry_val |= PASID_ENTRY_FLPM_5LP;
422
423 iommu->pasid_table[svm->pasid].val = pasid_entry_val;
424
425 wmb();
426
427 /*
428 * Flush PASID cache when a PASID table entry becomes
429 * present.
430 */
431 if (cap_caching_mode(iommu->cap))
432 intel_flush_pasid_dev(svm, sdev, svm->pasid);
433 }
434 list_add_rcu(&sdev->list, &svm->devs);
435
436 success:
437 *pasid = svm->pasid;
438 ret = 0;
439 out:
440 mutex_unlock(&pasid_mutex);
441 if (mm)
442 mmput(mm);
443 return ret;
444}
445EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
446
447int intel_svm_unbind_mm(struct device *dev, int pasid)
448{
449 struct intel_svm_dev *sdev;
450 struct intel_iommu *iommu;
451 struct intel_svm *svm;
452 int ret = -EINVAL;
453
454 mutex_lock(&pasid_mutex);
455 iommu = intel_svm_device_to_iommu(dev);
456 if (!iommu || !iommu->pasid_table)
457 goto out;
458
459 svm = idr_find(&iommu->pasid_idr, pasid);
460 if (!svm)
461 goto out;
462
463 list_for_each_entry(sdev, &svm->devs, list) {
464 if (dev == sdev->dev) {
465 ret = 0;
466 sdev->users--;
467 if (!sdev->users) {
468 list_del_rcu(&sdev->list);
469 /* Flush the PASID cache and IOTLB for this device.
470 * Note that we do depend on the hardware *not* using
471 * the PASID any more. Just as we depend on other
472 * devices never using PASIDs that they have no right
473 * to use. We have a *shared* PASID table, because it's
474 * large and has to be physically contiguous. So it's
475 * hard to be as defensive as we might like. */
476 intel_flush_pasid_dev(svm, sdev, svm->pasid);
477 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
478 kfree_rcu(sdev, rcu);
479
480 if (list_empty(&svm->devs)) {
481 svm->iommu->pasid_table[svm->pasid].val = 0;
482 wmb();
483
484 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
485 if (svm->mm)
486 mmu_notifier_unregister(&svm->notifier, svm->mm);
487
488 /* We mandate that no page faults may be outstanding
489 * for the PASID when intel_svm_unbind_mm() is called.
490 * If that is not obeyed, subtle errors will happen.
491 * Let's make them less subtle... */
492 memset(svm, 0x6b, sizeof(*svm));
493 kfree(svm);
494 }
495 }
496 break;
497 }
498 }
499 out:
500 mutex_unlock(&pasid_mutex);
501
502 return ret;
503}
504EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
505
506int intel_svm_is_pasid_valid(struct device *dev, int pasid)
507{
508 struct intel_iommu *iommu;
509 struct intel_svm *svm;
510 int ret = -EINVAL;
511
512 mutex_lock(&pasid_mutex);
513 iommu = intel_svm_device_to_iommu(dev);
514 if (!iommu || !iommu->pasid_table)
515 goto out;
516
517 svm = idr_find(&iommu->pasid_idr, pasid);
518 if (!svm)
519 goto out;
520
521 /* init_mm is used in this case */
522 if (!svm->mm)
523 ret = 1;
524 else if (atomic_read(&svm->mm->mm_users) > 0)
525 ret = 1;
526 else
527 ret = 0;
528
529 out:
530 mutex_unlock(&pasid_mutex);
531
532 return ret;
533}
534EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
535
536/* Page request queue descriptor */
537struct page_req_dsc {
538 u64 srr:1;
539 u64 bof:1;
540 u64 pasid_present:1;
541 u64 lpig:1;
542 u64 pasid:20;
543 u64 bus:8;
544 u64 private:23;
545 u64 prg_index:9;
546 u64 rd_req:1;
547 u64 wr_req:1;
548 u64 exe_req:1;
549 u64 priv_req:1;
550 u64 devfn:8;
551 u64 addr:52;
552};
553
554#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
555
556static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
557{
558 unsigned long requested = 0;
559
560 if (req->exe_req)
561 requested |= VM_EXEC;
562
563 if (req->rd_req)
564 requested |= VM_READ;
565
566 if (req->wr_req)
567 requested |= VM_WRITE;
568
569 return (requested & ~vma->vm_flags) != 0;
570}
571
572static bool is_canonical_address(u64 addr)
573{
574 int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
575 long saddr = (long) addr;
576
577 return (((saddr << shift) >> shift) == saddr);
578}
579
580static irqreturn_t prq_event_thread(int irq, void *d)
581{
582 struct intel_iommu *iommu = d;
583 struct intel_svm *svm = NULL;
584 int head, tail, handled = 0;
585
586 /* Clear PPR bit before reading head/tail registers, to
587 * ensure that we get a new interrupt if needed. */
588 writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
589
590 tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
591 head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
592 while (head != tail) {
593 struct intel_svm_dev *sdev;
594 struct vm_area_struct *vma;
595 struct page_req_dsc *req;
596 struct qi_desc resp;
597 int ret, result;
598 u64 address;
599
600 handled = 1;
601
602 req = &iommu->prq[head / sizeof(*req)];
603
604 result = QI_RESP_FAILURE;
605 address = (u64)req->addr << VTD_PAGE_SHIFT;
606 if (!req->pasid_present) {
607 pr_err("%s: Page request without PASID: %08llx %08llx\n",
608 iommu->name, ((unsigned long long *)req)[0],
609 ((unsigned long long *)req)[1]);
610 goto bad_req;
611 }
612
613 if (!svm || svm->pasid != req->pasid) {
614 rcu_read_lock();
615 svm = idr_find(&iommu->pasid_idr, req->pasid);
616 /* It *can't* go away, because the driver is not permitted
617 * to unbind the mm while any page faults are outstanding.
618 * So we only need RCU to protect the internal idr code. */
619 rcu_read_unlock();
620
621 if (!svm) {
622 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
623 iommu->name, req->pasid, ((unsigned long long *)req)[0],
624 ((unsigned long long *)req)[1]);
625 goto no_pasid;
626 }
627 }
628
629 result = QI_RESP_INVALID;
630 /* Since we're using init_mm.pgd directly, we should never take
631 * any faults on kernel addresses. */
632 if (!svm->mm)
633 goto bad_req;
634 /* If the mm is already defunct, don't handle faults. */
635 if (!mmget_not_zero(svm->mm))
636 goto bad_req;
637
638 /* If address is not canonical, return invalid response */
639 if (!is_canonical_address(address))
640 goto bad_req;
641
642 down_read(&svm->mm->mmap_sem);
643 vma = find_extend_vma(svm->mm, address);
644 if (!vma || address < vma->vm_start)
645 goto invalid;
646
647 if (access_error(vma, req))
648 goto invalid;
649
650 ret = handle_mm_fault(vma, address,
651 req->wr_req ? FAULT_FLAG_WRITE : 0);
652 if (ret & VM_FAULT_ERROR)
653 goto invalid;
654
655 result = QI_RESP_SUCCESS;
656 invalid:
657 up_read(&svm->mm->mmap_sem);
658 mmput(svm->mm);
659 bad_req:
660 /* Accounting for major/minor faults? */
661 rcu_read_lock();
662 list_for_each_entry_rcu(sdev, &svm->devs, list) {
663 if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
664 break;
665 }
666 /* Other devices can go away, but the drivers are not permitted
667 * to unbind while any page faults might be in flight. So it's
668 * OK to drop the 'lock' here now we have it. */
669 rcu_read_unlock();
670
671 if (WARN_ON(&sdev->list == &svm->devs))
672 sdev = NULL;
673
674 if (sdev && sdev->ops && sdev->ops->fault_cb) {
675 int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
676 (req->exe_req << 1) | (req->priv_req);
677 sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
678 }
679 /* We get here in the error case where the PASID lookup failed,
680 and these can be NULL. Do not use them below this point! */
681 sdev = NULL;
682 svm = NULL;
683 no_pasid:
684 if (req->lpig) {
685 /* Page Group Response */
686 resp.low = QI_PGRP_PASID(req->pasid) |
687 QI_PGRP_DID((req->bus << 8) | req->devfn) |
688 QI_PGRP_PASID_P(req->pasid_present) |
689 QI_PGRP_RESP_TYPE;
690 resp.high = QI_PGRP_IDX(req->prg_index) |
691 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
692
693 qi_submit_sync(&resp, iommu);
694 } else if (req->srr) {
695 /* Page Stream Response */
696 resp.low = QI_PSTRM_IDX(req->prg_index) |
697 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
698 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
699 resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
700 QI_PSTRM_RESP_CODE(result);
701
702 qi_submit_sync(&resp, iommu);
703 }
704
705 head = (head + sizeof(*req)) & PRQ_RING_MASK;
706 }
707
708 dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
709
710 return IRQ_RETVAL(handled);
711}