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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35#include "hda_controller.h"
36
37static bool static_hdmi_pcm;
38module_param(static_hdmi_pcm, bool, 0644);
39MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41static bool enable_acomp = true;
42module_param(enable_acomp, bool, 0444);
43MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45static bool enable_silent_stream =
46IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47module_param(enable_silent_stream, bool, 0644);
48MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50struct hdmi_spec_per_cvt {
51 hda_nid_t cvt_nid;
52 int assigned;
53 unsigned int channels_min;
54 unsigned int channels_max;
55 u32 rates;
56 u64 formats;
57 unsigned int maxbps;
58};
59
60/* max. connections to a widget */
61#define HDA_MAX_CONNECTIONS 32
62
63struct hdmi_spec_per_pin {
64 hda_nid_t pin_nid;
65 int dev_id;
66 /* pin idx, different device entries on the same pin use the same idx */
67 int pin_nid_idx;
68 int num_mux_nids;
69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
70 int mux_idx;
71 hda_nid_t cvt_nid;
72
73 struct hda_codec *codec;
74 struct hdmi_eld sink_eld;
75 struct mutex lock;
76 struct delayed_work work;
77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
79 int repoll_count;
80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
82 bool non_pcm;
83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
85#ifdef CONFIG_SND_PROC_FS
86 struct snd_info_entry *proc_entry;
87#endif
88};
89
90/* operations used by generic code that can be overridden by patches */
91struct hdmi_ops {
92 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
93 int dev_id, unsigned char *buf, int *eld_size);
94
95 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int dev_id,
97 int ca, int active_channels, int conn_type);
98
99 /* enable/disable HBR (HD passthrough) */
100 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int dev_id, bool hbr);
102
103 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
104 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
105 int format);
106
107 void (*pin_cvt_fixup)(struct hda_codec *codec,
108 struct hdmi_spec_per_pin *per_pin,
109 hda_nid_t cvt_nid);
110};
111
112struct hdmi_pcm {
113 struct hda_pcm *pcm;
114 struct snd_jack *jack;
115 struct snd_kcontrol *eld_ctl;
116};
117
118struct hdmi_spec {
119 struct hda_codec *codec;
120 int num_cvts;
121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
122 hda_nid_t cvt_nids[4]; /* only for haswell fix */
123
124 /*
125 * num_pins is the number of virtual pins
126 * for example, there are 3 pins, and each pin
127 * has 4 device entries, then the num_pins is 12
128 */
129 int num_pins;
130 /*
131 * num_nids is the number of real pins
132 * In the above example, num_nids is 3
133 */
134 int num_nids;
135 /*
136 * dev_num is the number of device entries
137 * on each pin.
138 * In the above example, dev_num is 4
139 */
140 int dev_num;
141 struct snd_array pins; /* struct hdmi_spec_per_pin */
142 struct hdmi_pcm pcm_rec[16];
143 struct mutex pcm_lock;
144 struct mutex bind_lock; /* for audio component binding */
145 /* pcm_bitmap means which pcms have been assigned to pins*/
146 unsigned long pcm_bitmap;
147 int pcm_used; /* counter of pcm_rec[] */
148 /* bitmap shows whether the pcm is opened in user space
149 * bit 0 means the first playback PCM (PCM3);
150 * bit 1 means the second playback PCM, and so on.
151 */
152 unsigned long pcm_in_use;
153
154 struct hdmi_eld temp_eld;
155 struct hdmi_ops ops;
156
157 bool dyn_pin_out;
158 bool dyn_pcm_assign;
159 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
160 /*
161 * Non-generic VIA/NVIDIA specific
162 */
163 struct hda_multi_out multiout;
164 struct hda_pcm_stream pcm_playback;
165
166 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
167 bool acomp_registered; /* audio component registered in this driver */
168 bool force_connect; /* force connectivity */
169 struct drm_audio_component_audio_ops drm_audio_ops;
170 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
171
172 struct hdac_chmap chmap;
173 hda_nid_t vendor_nid;
174 const int *port_map;
175 int port_num;
176 bool send_silent_stream; /* Flag to enable silent stream feature */
177};
178
179#ifdef CONFIG_SND_HDA_COMPONENT
180static inline bool codec_has_acomp(struct hda_codec *codec)
181{
182 struct hdmi_spec *spec = codec->spec;
183 return spec->use_acomp_notifier;
184}
185#else
186#define codec_has_acomp(codec) false
187#endif
188
189struct hdmi_audio_infoframe {
190 u8 type; /* 0x84 */
191 u8 ver; /* 0x01 */
192 u8 len; /* 0x0a */
193
194 u8 checksum;
195
196 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
197 u8 SS01_SF24;
198 u8 CXT04;
199 u8 CA;
200 u8 LFEPBL01_LSV36_DM_INH7;
201};
202
203struct dp_audio_infoframe {
204 u8 type; /* 0x84 */
205 u8 len; /* 0x1b */
206 u8 ver; /* 0x11 << 2 */
207
208 u8 CC02_CT47; /* match with HDMI infoframe from this on */
209 u8 SS01_SF24;
210 u8 CXT04;
211 u8 CA;
212 u8 LFEPBL01_LSV36_DM_INH7;
213};
214
215union audio_infoframe {
216 struct hdmi_audio_infoframe hdmi;
217 struct dp_audio_infoframe dp;
218 u8 bytes[0];
219};
220
221/*
222 * HDMI routines
223 */
224
225#define get_pin(spec, idx) \
226 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
227#define get_cvt(spec, idx) \
228 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
229/* obtain hdmi_pcm object assigned to idx */
230#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
231/* obtain hda_pcm object assigned to idx */
232#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
233
234static int pin_id_to_pin_index(struct hda_codec *codec,
235 hda_nid_t pin_nid, int dev_id)
236{
237 struct hdmi_spec *spec = codec->spec;
238 int pin_idx;
239 struct hdmi_spec_per_pin *per_pin;
240
241 /*
242 * (dev_id == -1) means it is NON-MST pin
243 * return the first virtual pin on this port
244 */
245 if (dev_id == -1)
246 dev_id = 0;
247
248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
249 per_pin = get_pin(spec, pin_idx);
250 if ((per_pin->pin_nid == pin_nid) &&
251 (per_pin->dev_id == dev_id))
252 return pin_idx;
253 }
254
255 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
256 return -EINVAL;
257}
258
259static int hinfo_to_pcm_index(struct hda_codec *codec,
260 struct hda_pcm_stream *hinfo)
261{
262 struct hdmi_spec *spec = codec->spec;
263 int pcm_idx;
264
265 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
266 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
267 return pcm_idx;
268
269 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
270 return -EINVAL;
271}
272
273static int hinfo_to_pin_index(struct hda_codec *codec,
274 struct hda_pcm_stream *hinfo)
275{
276 struct hdmi_spec *spec = codec->spec;
277 struct hdmi_spec_per_pin *per_pin;
278 int pin_idx;
279
280 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
281 per_pin = get_pin(spec, pin_idx);
282 if (per_pin->pcm &&
283 per_pin->pcm->pcm->stream == hinfo)
284 return pin_idx;
285 }
286
287 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
288 hinfo_to_pcm_index(codec, hinfo));
289 return -EINVAL;
290}
291
292static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
293 int pcm_idx)
294{
295 int i;
296 struct hdmi_spec_per_pin *per_pin;
297
298 for (i = 0; i < spec->num_pins; i++) {
299 per_pin = get_pin(spec, i);
300 if (per_pin->pcm_idx == pcm_idx)
301 return per_pin;
302 }
303 return NULL;
304}
305
306static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
307{
308 struct hdmi_spec *spec = codec->spec;
309 int cvt_idx;
310
311 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
312 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
313 return cvt_idx;
314
315 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
316 return -EINVAL;
317}
318
319static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
320 struct snd_ctl_elem_info *uinfo)
321{
322 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
323 struct hdmi_spec *spec = codec->spec;
324 struct hdmi_spec_per_pin *per_pin;
325 struct hdmi_eld *eld;
326 int pcm_idx;
327
328 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
329
330 pcm_idx = kcontrol->private_value;
331 mutex_lock(&spec->pcm_lock);
332 per_pin = pcm_idx_to_pin(spec, pcm_idx);
333 if (!per_pin) {
334 /* no pin is bound to the pcm */
335 uinfo->count = 0;
336 goto unlock;
337 }
338 eld = &per_pin->sink_eld;
339 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
340
341 unlock:
342 mutex_unlock(&spec->pcm_lock);
343 return 0;
344}
345
346static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
350 struct hdmi_spec *spec = codec->spec;
351 struct hdmi_spec_per_pin *per_pin;
352 struct hdmi_eld *eld;
353 int pcm_idx;
354 int err = 0;
355
356 pcm_idx = kcontrol->private_value;
357 mutex_lock(&spec->pcm_lock);
358 per_pin = pcm_idx_to_pin(spec, pcm_idx);
359 if (!per_pin) {
360 /* no pin is bound to the pcm */
361 memset(ucontrol->value.bytes.data, 0,
362 ARRAY_SIZE(ucontrol->value.bytes.data));
363 goto unlock;
364 }
365
366 eld = &per_pin->sink_eld;
367 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
368 eld->eld_size > ELD_MAX_SIZE) {
369 snd_BUG();
370 err = -EINVAL;
371 goto unlock;
372 }
373
374 memset(ucontrol->value.bytes.data, 0,
375 ARRAY_SIZE(ucontrol->value.bytes.data));
376 if (eld->eld_valid)
377 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
378 eld->eld_size);
379
380 unlock:
381 mutex_unlock(&spec->pcm_lock);
382 return err;
383}
384
385static const struct snd_kcontrol_new eld_bytes_ctl = {
386 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
387 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
388 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
389 .name = "ELD",
390 .info = hdmi_eld_ctl_info,
391 .get = hdmi_eld_ctl_get,
392};
393
394static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
395 int device)
396{
397 struct snd_kcontrol *kctl;
398 struct hdmi_spec *spec = codec->spec;
399 int err;
400
401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
402 if (!kctl)
403 return -ENOMEM;
404 kctl->private_value = pcm_idx;
405 kctl->id.device = device;
406
407 /* no pin nid is associated with the kctl now
408 * tbd: associate pin nid to eld ctl later
409 */
410 err = snd_hda_ctl_add(codec, 0, kctl);
411 if (err < 0)
412 return err;
413
414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
415 return 0;
416}
417
418#ifdef BE_PARANOID
419static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
420 int *packet_index, int *byte_index)
421{
422 int val;
423
424 val = snd_hda_codec_read(codec, pin_nid, 0,
425 AC_VERB_GET_HDMI_DIP_INDEX, 0);
426
427 *packet_index = val >> 5;
428 *byte_index = val & 0x1f;
429}
430#endif
431
432static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
433 int packet_index, int byte_index)
434{
435 int val;
436
437 val = (packet_index << 5) | (byte_index & 0x1f);
438
439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
440}
441
442static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
443 unsigned char val)
444{
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
446}
447
448static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
449{
450 struct hdmi_spec *spec = codec->spec;
451 int pin_out;
452
453 /* Unmute */
454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
455 snd_hda_codec_write(codec, pin_nid, 0,
456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
457
458 if (spec->dyn_pin_out)
459 /* Disable pin out until stream is active */
460 pin_out = 0;
461 else
462 /* Enable pin out: some machines with GM965 gets broken output
463 * when the pin is disabled or changed while using with HDMI
464 */
465 pin_out = PIN_OUT;
466
467 snd_hda_codec_write(codec, pin_nid, 0,
468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
469}
470
471/*
472 * ELD proc files
473 */
474
475#ifdef CONFIG_SND_PROC_FS
476static void print_eld_info(struct snd_info_entry *entry,
477 struct snd_info_buffer *buffer)
478{
479 struct hdmi_spec_per_pin *per_pin = entry->private_data;
480
481 mutex_lock(&per_pin->lock);
482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
483 mutex_unlock(&per_pin->lock);
484}
485
486static void write_eld_info(struct snd_info_entry *entry,
487 struct snd_info_buffer *buffer)
488{
489 struct hdmi_spec_per_pin *per_pin = entry->private_data;
490
491 mutex_lock(&per_pin->lock);
492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
493 mutex_unlock(&per_pin->lock);
494}
495
496static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
497{
498 char name[32];
499 struct hda_codec *codec = per_pin->codec;
500 struct snd_info_entry *entry;
501 int err;
502
503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
504 err = snd_card_proc_new(codec->card, name, &entry);
505 if (err < 0)
506 return err;
507
508 snd_info_set_text_ops(entry, per_pin, print_eld_info);
509 entry->c.text.write = write_eld_info;
510 entry->mode |= 0200;
511 per_pin->proc_entry = entry;
512
513 return 0;
514}
515
516static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
517{
518 if (!per_pin->codec->bus->shutdown) {
519 snd_info_free_entry(per_pin->proc_entry);
520 per_pin->proc_entry = NULL;
521 }
522}
523#else
524static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
525 int index)
526{
527 return 0;
528}
529static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
530{
531}
532#endif
533
534/*
535 * Audio InfoFrame routines
536 */
537
538/*
539 * Enable Audio InfoFrame Transmission
540 */
541static void hdmi_start_infoframe_trans(struct hda_codec *codec,
542 hda_nid_t pin_nid)
543{
544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
546 AC_DIPXMIT_BEST);
547}
548
549/*
550 * Disable Audio InfoFrame Transmission
551 */
552static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
553 hda_nid_t pin_nid)
554{
555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
557 AC_DIPXMIT_DISABLE);
558}
559
560static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
561{
562#ifdef CONFIG_SND_DEBUG_VERBOSE
563 int i;
564 int size;
565
566 size = snd_hdmi_get_eld_size(codec, pin_nid);
567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
568
569 for (i = 0; i < 8; i++) {
570 size = snd_hda_codec_read(codec, pin_nid, 0,
571 AC_VERB_GET_HDMI_DIP_SIZE, i);
572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
573 }
574#endif
575}
576
577static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
578{
579#ifdef BE_PARANOID
580 int i, j;
581 int size;
582 int pi, bi;
583 for (i = 0; i < 8; i++) {
584 size = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_DIP_SIZE, i);
586 if (size == 0)
587 continue;
588
589 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
590 for (j = 1; j < 1000; j++) {
591 hdmi_write_dip_byte(codec, pin_nid, 0x0);
592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
593 if (pi != i)
594 codec_dbg(codec, "dip index %d: %d != %d\n",
595 bi, pi, i);
596 if (bi == 0) /* byte index wrapped around */
597 break;
598 }
599 codec_dbg(codec,
600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
601 i, size, j);
602 }
603#endif
604}
605
606static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
607{
608 u8 *bytes = (u8 *)hdmi_ai;
609 u8 sum = 0;
610 int i;
611
612 hdmi_ai->checksum = 0;
613
614 for (i = 0; i < sizeof(*hdmi_ai); i++)
615 sum += bytes[i];
616
617 hdmi_ai->checksum = -sum;
618}
619
620static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
621 hda_nid_t pin_nid,
622 u8 *dip, int size)
623{
624 int i;
625
626 hdmi_debug_dip_size(codec, pin_nid);
627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
628
629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
630 for (i = 0; i < size; i++)
631 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
632}
633
634static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
635 u8 *dip, int size)
636{
637 u8 val;
638 int i;
639
640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
641 != AC_DIPXMIT_BEST)
642 return false;
643
644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
645 for (i = 0; i < size; i++) {
646 val = snd_hda_codec_read(codec, pin_nid, 0,
647 AC_VERB_GET_HDMI_DIP_DATA, 0);
648 if (val != dip[i])
649 return false;
650 }
651
652 return true;
653}
654
655static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
656 int dev_id, unsigned char *buf, int *eld_size)
657{
658 snd_hda_set_dev_select(codec, nid, dev_id);
659
660 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
661}
662
663static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
664 hda_nid_t pin_nid, int dev_id,
665 int ca, int active_channels,
666 int conn_type)
667{
668 union audio_infoframe ai;
669
670 memset(&ai, 0, sizeof(ai));
671 if (conn_type == 0) { /* HDMI */
672 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
673
674 hdmi_ai->type = 0x84;
675 hdmi_ai->ver = 0x01;
676 hdmi_ai->len = 0x0a;
677 hdmi_ai->CC02_CT47 = active_channels - 1;
678 hdmi_ai->CA = ca;
679 hdmi_checksum_audio_infoframe(hdmi_ai);
680 } else if (conn_type == 1) { /* DisplayPort */
681 struct dp_audio_infoframe *dp_ai = &ai.dp;
682
683 dp_ai->type = 0x84;
684 dp_ai->len = 0x1b;
685 dp_ai->ver = 0x11 << 2;
686 dp_ai->CC02_CT47 = active_channels - 1;
687 dp_ai->CA = ca;
688 } else {
689 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
690 pin_nid);
691 return;
692 }
693
694 snd_hda_set_dev_select(codec, pin_nid, dev_id);
695
696 /*
697 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
698 * sizeof(*dp_ai) to avoid partial match/update problems when
699 * the user switches between HDMI/DP monitors.
700 */
701 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
702 sizeof(ai))) {
703 codec_dbg(codec,
704 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
705 pin_nid,
706 active_channels, ca);
707 hdmi_stop_infoframe_trans(codec, pin_nid);
708 hdmi_fill_audio_infoframe(codec, pin_nid,
709 ai.bytes, sizeof(ai));
710 hdmi_start_infoframe_trans(codec, pin_nid);
711 }
712}
713
714static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
715 struct hdmi_spec_per_pin *per_pin,
716 bool non_pcm)
717{
718 struct hdmi_spec *spec = codec->spec;
719 struct hdac_chmap *chmap = &spec->chmap;
720 hda_nid_t pin_nid = per_pin->pin_nid;
721 int dev_id = per_pin->dev_id;
722 int channels = per_pin->channels;
723 int active_channels;
724 struct hdmi_eld *eld;
725 int ca;
726
727 if (!channels)
728 return;
729
730 snd_hda_set_dev_select(codec, pin_nid, dev_id);
731
732 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
733 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
734 snd_hda_codec_write(codec, pin_nid, 0,
735 AC_VERB_SET_AMP_GAIN_MUTE,
736 AMP_OUT_UNMUTE);
737
738 eld = &per_pin->sink_eld;
739
740 ca = snd_hdac_channel_allocation(&codec->core,
741 eld->info.spk_alloc, channels,
742 per_pin->chmap_set, non_pcm, per_pin->chmap);
743
744 active_channels = snd_hdac_get_active_channels(ca);
745
746 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
747 active_channels);
748
749 /*
750 * always configure channel mapping, it may have been changed by the
751 * user in the meantime
752 */
753 snd_hdac_setup_channel_mapping(&spec->chmap,
754 pin_nid, non_pcm, ca, channels,
755 per_pin->chmap, per_pin->chmap_set);
756
757 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
758 ca, active_channels, eld->info.conn_type);
759
760 per_pin->non_pcm = non_pcm;
761}
762
763/*
764 * Unsolicited events
765 */
766
767static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
768
769static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
770 int dev_id)
771{
772 struct hdmi_spec *spec = codec->spec;
773 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
774
775 if (pin_idx < 0)
776 return;
777 mutex_lock(&spec->pcm_lock);
778 hdmi_present_sense(get_pin(spec, pin_idx), 1);
779 mutex_unlock(&spec->pcm_lock);
780}
781
782static void jack_callback(struct hda_codec *codec,
783 struct hda_jack_callback *jack)
784{
785 /* stop polling when notification is enabled */
786 if (codec_has_acomp(codec))
787 return;
788
789 check_presence_and_report(codec, jack->nid, jack->dev_id);
790}
791
792static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
793 struct hda_jack_tbl *jack)
794{
795 jack->jack_dirty = 1;
796
797 codec_dbg(codec,
798 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
799 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
800 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
801
802 check_presence_and_report(codec, jack->nid, jack->dev_id);
803}
804
805static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
806{
807 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
808 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
809 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
810 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
811
812 codec_info(codec,
813 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
814 codec->addr,
815 tag,
816 subtag,
817 cp_state,
818 cp_ready);
819
820 /* TODO */
821 if (cp_state) {
822 ;
823 }
824 if (cp_ready) {
825 ;
826 }
827}
828
829
830static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
831{
832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
834 struct hda_jack_tbl *jack;
835
836 if (codec_has_acomp(codec))
837 return;
838
839 if (codec->dp_mst) {
840 int dev_entry =
841 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
842
843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
844 } else {
845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
846 }
847
848 if (!jack) {
849 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
850 return;
851 }
852
853 if (subtag == 0)
854 hdmi_intrinsic_event(codec, res, jack);
855 else
856 hdmi_non_intrinsic_event(codec, res);
857}
858
859static void haswell_verify_D0(struct hda_codec *codec,
860 hda_nid_t cvt_nid, hda_nid_t nid)
861{
862 int pwr;
863
864 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
865 * thus pins could only choose converter 0 for use. Make sure the
866 * converters are in correct power state */
867 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
868 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
869
870 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
871 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
872 AC_PWRST_D0);
873 msleep(40);
874 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
875 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
876 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
877 }
878}
879
880/*
881 * Callbacks
882 */
883
884/* HBR should be Non-PCM, 8 channels */
885#define is_hbr_format(format) \
886 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
887
888static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
889 int dev_id, bool hbr)
890{
891 int pinctl, new_pinctl;
892
893 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
894 snd_hda_set_dev_select(codec, pin_nid, dev_id);
895 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
897
898 if (pinctl < 0)
899 return hbr ? -EINVAL : 0;
900
901 new_pinctl = pinctl & ~AC_PINCTL_EPT;
902 if (hbr)
903 new_pinctl |= AC_PINCTL_EPT_HBR;
904 else
905 new_pinctl |= AC_PINCTL_EPT_NATIVE;
906
907 codec_dbg(codec,
908 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
909 pin_nid,
910 pinctl == new_pinctl ? "" : "new-",
911 new_pinctl);
912
913 if (pinctl != new_pinctl)
914 snd_hda_codec_write(codec, pin_nid, 0,
915 AC_VERB_SET_PIN_WIDGET_CONTROL,
916 new_pinctl);
917 } else if (hbr)
918 return -EINVAL;
919
920 return 0;
921}
922
923static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
924 hda_nid_t pin_nid, int dev_id,
925 u32 stream_tag, int format)
926{
927 struct hdmi_spec *spec = codec->spec;
928 unsigned int param;
929 int err;
930
931 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
932 is_hbr_format(format));
933
934 if (err) {
935 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
936 return err;
937 }
938
939 if (spec->intel_hsw_fixup) {
940
941 /*
942 * on recent platforms IEC Coding Type is required for HBR
943 * support, read current Digital Converter settings and set
944 * ICT bitfield if needed.
945 */
946 param = snd_hda_codec_read(codec, cvt_nid, 0,
947 AC_VERB_GET_DIGI_CONVERT_1, 0);
948
949 param = (param >> 16) & ~(AC_DIG3_ICT);
950
951 /* on recent platforms ICT mode is required for HBR support */
952 if (is_hbr_format(format))
953 param |= 0x1;
954
955 snd_hda_codec_write(codec, cvt_nid, 0,
956 AC_VERB_SET_DIGI_CONVERT_3, param);
957 }
958
959 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
960 return 0;
961}
962
963/* Try to find an available converter
964 * If pin_idx is less then zero, just try to find an available converter.
965 * Otherwise, try to find an available converter and get the cvt mux index
966 * of the pin.
967 */
968static int hdmi_choose_cvt(struct hda_codec *codec,
969 int pin_idx, int *cvt_id)
970{
971 struct hdmi_spec *spec = codec->spec;
972 struct hdmi_spec_per_pin *per_pin;
973 struct hdmi_spec_per_cvt *per_cvt = NULL;
974 int cvt_idx, mux_idx = 0;
975
976 /* pin_idx < 0 means no pin will be bound to the converter */
977 if (pin_idx < 0)
978 per_pin = NULL;
979 else
980 per_pin = get_pin(spec, pin_idx);
981
982 /* Dynamically assign converter to stream */
983 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
984 per_cvt = get_cvt(spec, cvt_idx);
985
986 /* Must not already be assigned */
987 if (per_cvt->assigned)
988 continue;
989 if (per_pin == NULL)
990 break;
991 /* Must be in pin's mux's list of converters */
992 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
993 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
994 break;
995 /* Not in mux list */
996 if (mux_idx == per_pin->num_mux_nids)
997 continue;
998 break;
999 }
1000
1001 /* No free converters */
1002 if (cvt_idx == spec->num_cvts)
1003 return -EBUSY;
1004
1005 if (per_pin != NULL)
1006 per_pin->mux_idx = mux_idx;
1007
1008 if (cvt_id)
1009 *cvt_id = cvt_idx;
1010
1011 return 0;
1012}
1013
1014/* Assure the pin select the right convetor */
1015static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1016 struct hdmi_spec_per_pin *per_pin)
1017{
1018 hda_nid_t pin_nid = per_pin->pin_nid;
1019 int mux_idx, curr;
1020
1021 mux_idx = per_pin->mux_idx;
1022 curr = snd_hda_codec_read(codec, pin_nid, 0,
1023 AC_VERB_GET_CONNECT_SEL, 0);
1024 if (curr != mux_idx)
1025 snd_hda_codec_write_cache(codec, pin_nid, 0,
1026 AC_VERB_SET_CONNECT_SEL,
1027 mux_idx);
1028}
1029
1030/* get the mux index for the converter of the pins
1031 * converter's mux index is the same for all pins on Intel platform
1032 */
1033static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1034 hda_nid_t cvt_nid)
1035{
1036 int i;
1037
1038 for (i = 0; i < spec->num_cvts; i++)
1039 if (spec->cvt_nids[i] == cvt_nid)
1040 return i;
1041 return -EINVAL;
1042}
1043
1044/* Intel HDMI workaround to fix audio routing issue:
1045 * For some Intel display codecs, pins share the same connection list.
1046 * So a conveter can be selected by multiple pins and playback on any of these
1047 * pins will generate sound on the external display, because audio flows from
1048 * the same converter to the display pipeline. Also muting one pin may make
1049 * other pins have no sound output.
1050 * So this function assures that an assigned converter for a pin is not selected
1051 * by any other pins.
1052 */
1053static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1054 hda_nid_t pin_nid,
1055 int dev_id, int mux_idx)
1056{
1057 struct hdmi_spec *spec = codec->spec;
1058 hda_nid_t nid;
1059 int cvt_idx, curr;
1060 struct hdmi_spec_per_cvt *per_cvt;
1061 struct hdmi_spec_per_pin *per_pin;
1062 int pin_idx;
1063
1064 /* configure the pins connections */
1065 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1066 int dev_id_saved;
1067 int dev_num;
1068
1069 per_pin = get_pin(spec, pin_idx);
1070 /*
1071 * pin not connected to monitor
1072 * no need to operate on it
1073 */
1074 if (!per_pin->pcm)
1075 continue;
1076
1077 if ((per_pin->pin_nid == pin_nid) &&
1078 (per_pin->dev_id == dev_id))
1079 continue;
1080
1081 /*
1082 * if per_pin->dev_id >= dev_num,
1083 * snd_hda_get_dev_select() will fail,
1084 * and the following operation is unpredictable.
1085 * So skip this situation.
1086 */
1087 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1088 if (per_pin->dev_id >= dev_num)
1089 continue;
1090
1091 nid = per_pin->pin_nid;
1092
1093 /*
1094 * Calling this function should not impact
1095 * on the device entry selection
1096 * So let's save the dev id for each pin,
1097 * and restore it when return
1098 */
1099 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1100 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1101 curr = snd_hda_codec_read(codec, nid, 0,
1102 AC_VERB_GET_CONNECT_SEL, 0);
1103 if (curr != mux_idx) {
1104 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1105 continue;
1106 }
1107
1108
1109 /* choose an unassigned converter. The conveters in the
1110 * connection list are in the same order as in the codec.
1111 */
1112 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1113 per_cvt = get_cvt(spec, cvt_idx);
1114 if (!per_cvt->assigned) {
1115 codec_dbg(codec,
1116 "choose cvt %d for pin nid %d\n",
1117 cvt_idx, nid);
1118 snd_hda_codec_write_cache(codec, nid, 0,
1119 AC_VERB_SET_CONNECT_SEL,
1120 cvt_idx);
1121 break;
1122 }
1123 }
1124 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1125 }
1126}
1127
1128/* A wrapper of intel_not_share_asigned_cvt() */
1129static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1130 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1131{
1132 int mux_idx;
1133 struct hdmi_spec *spec = codec->spec;
1134
1135 /* On Intel platform, the mapping of converter nid to
1136 * mux index of the pins are always the same.
1137 * The pin nid may be 0, this means all pins will not
1138 * share the converter.
1139 */
1140 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1141 if (mux_idx >= 0)
1142 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1143}
1144
1145/* skeleton caller of pin_cvt_fixup ops */
1146static void pin_cvt_fixup(struct hda_codec *codec,
1147 struct hdmi_spec_per_pin *per_pin,
1148 hda_nid_t cvt_nid)
1149{
1150 struct hdmi_spec *spec = codec->spec;
1151
1152 if (spec->ops.pin_cvt_fixup)
1153 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1154}
1155
1156/* called in hdmi_pcm_open when no pin is assigned to the PCM
1157 * in dyn_pcm_assign mode.
1158 */
1159static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1160 struct hda_codec *codec,
1161 struct snd_pcm_substream *substream)
1162{
1163 struct hdmi_spec *spec = codec->spec;
1164 struct snd_pcm_runtime *runtime = substream->runtime;
1165 int cvt_idx, pcm_idx;
1166 struct hdmi_spec_per_cvt *per_cvt = NULL;
1167 int err;
1168
1169 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1170 if (pcm_idx < 0)
1171 return -EINVAL;
1172
1173 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1174 if (err)
1175 return err;
1176
1177 per_cvt = get_cvt(spec, cvt_idx);
1178 per_cvt->assigned = 1;
1179 hinfo->nid = per_cvt->cvt_nid;
1180
1181 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1182
1183 set_bit(pcm_idx, &spec->pcm_in_use);
1184 /* todo: setup spdif ctls assign */
1185
1186 /* Initially set the converter's capabilities */
1187 hinfo->channels_min = per_cvt->channels_min;
1188 hinfo->channels_max = per_cvt->channels_max;
1189 hinfo->rates = per_cvt->rates;
1190 hinfo->formats = per_cvt->formats;
1191 hinfo->maxbps = per_cvt->maxbps;
1192
1193 /* Store the updated parameters */
1194 runtime->hw.channels_min = hinfo->channels_min;
1195 runtime->hw.channels_max = hinfo->channels_max;
1196 runtime->hw.formats = hinfo->formats;
1197 runtime->hw.rates = hinfo->rates;
1198
1199 snd_pcm_hw_constraint_step(substream->runtime, 0,
1200 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1201 return 0;
1202}
1203
1204/*
1205 * HDA PCM callbacks
1206 */
1207static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1208 struct hda_codec *codec,
1209 struct snd_pcm_substream *substream)
1210{
1211 struct hdmi_spec *spec = codec->spec;
1212 struct snd_pcm_runtime *runtime = substream->runtime;
1213 int pin_idx, cvt_idx, pcm_idx;
1214 struct hdmi_spec_per_pin *per_pin;
1215 struct hdmi_eld *eld;
1216 struct hdmi_spec_per_cvt *per_cvt = NULL;
1217 int err;
1218
1219 /* Validate hinfo */
1220 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1221 if (pcm_idx < 0)
1222 return -EINVAL;
1223
1224 mutex_lock(&spec->pcm_lock);
1225 pin_idx = hinfo_to_pin_index(codec, hinfo);
1226 if (!spec->dyn_pcm_assign) {
1227 if (snd_BUG_ON(pin_idx < 0)) {
1228 err = -EINVAL;
1229 goto unlock;
1230 }
1231 } else {
1232 /* no pin is assigned to the PCM
1233 * PA need pcm open successfully when probe
1234 */
1235 if (pin_idx < 0) {
1236 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1237 goto unlock;
1238 }
1239 }
1240
1241 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1242 if (err < 0)
1243 goto unlock;
1244
1245 per_cvt = get_cvt(spec, cvt_idx);
1246 /* Claim converter */
1247 per_cvt->assigned = 1;
1248
1249 set_bit(pcm_idx, &spec->pcm_in_use);
1250 per_pin = get_pin(spec, pin_idx);
1251 per_pin->cvt_nid = per_cvt->cvt_nid;
1252 hinfo->nid = per_cvt->cvt_nid;
1253
1254 /* flip stripe flag for the assigned stream if supported */
1255 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1256 azx_stream(get_azx_dev(substream))->stripe = 1;
1257
1258 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1259 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1260 AC_VERB_SET_CONNECT_SEL,
1261 per_pin->mux_idx);
1262
1263 /* configure unused pins to choose other converters */
1264 pin_cvt_fixup(codec, per_pin, 0);
1265
1266 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1267
1268 /* Initially set the converter's capabilities */
1269 hinfo->channels_min = per_cvt->channels_min;
1270 hinfo->channels_max = per_cvt->channels_max;
1271 hinfo->rates = per_cvt->rates;
1272 hinfo->formats = per_cvt->formats;
1273 hinfo->maxbps = per_cvt->maxbps;
1274
1275 eld = &per_pin->sink_eld;
1276 /* Restrict capabilities by ELD if this isn't disabled */
1277 if (!static_hdmi_pcm && eld->eld_valid) {
1278 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1279 if (hinfo->channels_min > hinfo->channels_max ||
1280 !hinfo->rates || !hinfo->formats) {
1281 per_cvt->assigned = 0;
1282 hinfo->nid = 0;
1283 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1284 err = -ENODEV;
1285 goto unlock;
1286 }
1287 }
1288
1289 /* Store the updated parameters */
1290 runtime->hw.channels_min = hinfo->channels_min;
1291 runtime->hw.channels_max = hinfo->channels_max;
1292 runtime->hw.formats = hinfo->formats;
1293 runtime->hw.rates = hinfo->rates;
1294
1295 snd_pcm_hw_constraint_step(substream->runtime, 0,
1296 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1297 unlock:
1298 mutex_unlock(&spec->pcm_lock);
1299 return err;
1300}
1301
1302/*
1303 * HDA/HDMI auto parsing
1304 */
1305static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1306{
1307 struct hdmi_spec *spec = codec->spec;
1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1309 hda_nid_t pin_nid = per_pin->pin_nid;
1310 int dev_id = per_pin->dev_id;
1311 int conns;
1312
1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1314 codec_warn(codec,
1315 "HDMI: pin %d wcaps %#x does not support connection list\n",
1316 pin_nid, get_wcaps(codec, pin_nid));
1317 return -EINVAL;
1318 }
1319
1320 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1321
1322 if (spec->intel_hsw_fixup) {
1323 conns = spec->num_cvts;
1324 memcpy(per_pin->mux_nids, spec->cvt_nids,
1325 sizeof(hda_nid_t) * conns);
1326 } else {
1327 conns = snd_hda_get_raw_connections(codec, pin_nid,
1328 per_pin->mux_nids,
1329 HDA_MAX_CONNECTIONS);
1330 }
1331
1332 /* all the device entries on the same pin have the same conn list */
1333 per_pin->num_mux_nids = conns;
1334
1335 return 0;
1336}
1337
1338static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1339 struct hdmi_spec_per_pin *per_pin)
1340{
1341 int i;
1342
1343 /*
1344 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1345 * platforms (with maximum of 'num_nids + dev_num - 1')
1346 *
1347 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1348 * if m==0. This guarantees that dynamic pcm assignments are compatible
1349 * with the legacy static per_pin-pcm assignment that existed in the
1350 * days before DP-MST.
1351 *
1352 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1353 *
1354 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1355 */
1356
1357 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1358 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1359 return per_pin->pin_nid_idx;
1360 } else {
1361 i = spec->num_nids + (per_pin->dev_id - 1);
1362 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1363 return i;
1364 }
1365
1366 /* have a second try; check the area over num_nids */
1367 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1368 if (!test_bit(i, &spec->pcm_bitmap))
1369 return i;
1370 }
1371
1372 /* the last try; check the empty slots in pins */
1373 for (i = 0; i < spec->num_nids; i++) {
1374 if (!test_bit(i, &spec->pcm_bitmap))
1375 return i;
1376 }
1377 return -EBUSY;
1378}
1379
1380static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1381 struct hdmi_spec_per_pin *per_pin)
1382{
1383 int idx;
1384
1385 /* pcm already be attached to the pin */
1386 if (per_pin->pcm)
1387 return;
1388 idx = hdmi_find_pcm_slot(spec, per_pin);
1389 if (idx == -EBUSY)
1390 return;
1391 per_pin->pcm_idx = idx;
1392 per_pin->pcm = get_hdmi_pcm(spec, idx);
1393 set_bit(idx, &spec->pcm_bitmap);
1394}
1395
1396static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1397 struct hdmi_spec_per_pin *per_pin)
1398{
1399 int idx;
1400
1401 /* pcm already be detached from the pin */
1402 if (!per_pin->pcm)
1403 return;
1404 idx = per_pin->pcm_idx;
1405 per_pin->pcm_idx = -1;
1406 per_pin->pcm = NULL;
1407 if (idx >= 0 && idx < spec->pcm_used)
1408 clear_bit(idx, &spec->pcm_bitmap);
1409}
1410
1411static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1412 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1413{
1414 int mux_idx;
1415
1416 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1417 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1418 break;
1419 return mux_idx;
1420}
1421
1422static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1423
1424static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1425 struct hdmi_spec_per_pin *per_pin)
1426{
1427 struct hda_codec *codec = per_pin->codec;
1428 struct hda_pcm *pcm;
1429 struct hda_pcm_stream *hinfo;
1430 struct snd_pcm_substream *substream;
1431 int mux_idx;
1432 bool non_pcm;
1433
1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1435 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1436 else
1437 return;
1438 if (!pcm->pcm)
1439 return;
1440 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1441 return;
1442
1443 /* hdmi audio only uses playback and one substream */
1444 hinfo = pcm->stream;
1445 substream = pcm->pcm->streams[0].substream;
1446
1447 per_pin->cvt_nid = hinfo->nid;
1448
1449 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1450 if (mux_idx < per_pin->num_mux_nids) {
1451 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1452 per_pin->dev_id);
1453 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1454 AC_VERB_SET_CONNECT_SEL,
1455 mux_idx);
1456 }
1457 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1458
1459 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1460 if (substream->runtime)
1461 per_pin->channels = substream->runtime->channels;
1462 per_pin->setup = true;
1463 per_pin->mux_idx = mux_idx;
1464
1465 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1466}
1467
1468static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1469 struct hdmi_spec_per_pin *per_pin)
1470{
1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1472 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1473
1474 per_pin->chmap_set = false;
1475 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1476
1477 per_pin->setup = false;
1478 per_pin->channels = 0;
1479}
1480
1481static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1482 struct hdmi_spec_per_pin *per_pin)
1483{
1484 struct hdmi_spec *spec = codec->spec;
1485
1486 if (per_pin->pcm_idx >= 0)
1487 return spec->pcm_rec[per_pin->pcm_idx].jack;
1488 else
1489 return NULL;
1490}
1491
1492/* update per_pin ELD from the given new ELD;
1493 * setup info frame and notification accordingly
1494 * also notify ELD kctl and report jack status changes
1495 */
1496static void update_eld(struct hda_codec *codec,
1497 struct hdmi_spec_per_pin *per_pin,
1498 struct hdmi_eld *eld,
1499 int repoll)
1500{
1501 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1502 struct hdmi_spec *spec = codec->spec;
1503 struct snd_jack *pcm_jack;
1504 bool old_eld_valid = pin_eld->eld_valid;
1505 bool eld_changed;
1506 int pcm_idx;
1507
1508 if (eld->eld_valid) {
1509 if (eld->eld_size <= 0 ||
1510 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1511 eld->eld_size) < 0) {
1512 eld->eld_valid = false;
1513 if (repoll) {
1514 schedule_delayed_work(&per_pin->work,
1515 msecs_to_jiffies(300));
1516 return;
1517 }
1518 }
1519 }
1520
1521 if (!eld->eld_valid || eld->eld_size <= 0) {
1522 eld->eld_valid = false;
1523 eld->eld_size = 0;
1524 }
1525
1526 /* for monitor disconnection, save pcm_idx firstly */
1527 pcm_idx = per_pin->pcm_idx;
1528
1529 /*
1530 * pcm_idx >=0 before update_eld() means it is in monitor
1531 * disconnected event. Jack must be fetched before update_eld().
1532 */
1533 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1534
1535 if (spec->dyn_pcm_assign) {
1536 if (eld->eld_valid) {
1537 hdmi_attach_hda_pcm(spec, per_pin);
1538 hdmi_pcm_setup_pin(spec, per_pin);
1539 } else {
1540 hdmi_pcm_reset_pin(spec, per_pin);
1541 hdmi_detach_hda_pcm(spec, per_pin);
1542 }
1543 }
1544 /* if pcm_idx == -1, it means this is in monitor connection event
1545 * we can get the correct pcm_idx now.
1546 */
1547 if (pcm_idx == -1)
1548 pcm_idx = per_pin->pcm_idx;
1549 if (!pcm_jack)
1550 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1551
1552 if (eld->eld_valid)
1553 snd_hdmi_show_eld(codec, &eld->info);
1554
1555 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1556 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1557 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1558 if (pin_eld->eld_size != eld->eld_size ||
1559 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1560 eld->eld_size) != 0)
1561 eld_changed = true;
1562
1563 if (eld_changed) {
1564 pin_eld->monitor_present = eld->monitor_present;
1565 pin_eld->eld_valid = eld->eld_valid;
1566 pin_eld->eld_size = eld->eld_size;
1567 if (eld->eld_valid)
1568 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1569 eld->eld_size);
1570 pin_eld->info = eld->info;
1571 }
1572
1573 /*
1574 * Re-setup pin and infoframe. This is needed e.g. when
1575 * - sink is first plugged-in
1576 * - transcoder can change during stream playback on Haswell
1577 * and this can make HW reset converter selection on a pin.
1578 */
1579 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1580 pin_cvt_fixup(codec, per_pin, 0);
1581 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1582 }
1583
1584 if (eld_changed && pcm_idx >= 0)
1585 snd_ctl_notify(codec->card,
1586 SNDRV_CTL_EVENT_MASK_VALUE |
1587 SNDRV_CTL_EVENT_MASK_INFO,
1588 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1589
1590 if (eld_changed && pcm_jack)
1591 snd_jack_report(pcm_jack,
1592 (eld->monitor_present && eld->eld_valid) ?
1593 SND_JACK_AVOUT : 0);
1594}
1595
1596/* update ELD and jack state via HD-audio verbs */
1597static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1598 int repoll)
1599{
1600 struct hda_codec *codec = per_pin->codec;
1601 struct hdmi_spec *spec = codec->spec;
1602 struct hdmi_eld *eld = &spec->temp_eld;
1603 hda_nid_t pin_nid = per_pin->pin_nid;
1604 int dev_id = per_pin->dev_id;
1605 /*
1606 * Always execute a GetPinSense verb here, even when called from
1607 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1608 * response's PD bit is not the real PD value, but indicates that
1609 * the real PD value changed. An older version of the HD-audio
1610 * specification worked this way. Hence, we just ignore the data in
1611 * the unsolicited response to avoid custom WARs.
1612 */
1613 int present;
1614 int ret;
1615
1616 ret = snd_hda_power_up_pm(codec);
1617 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec)))
1618 goto out;
1619
1620 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1621
1622 mutex_lock(&per_pin->lock);
1623 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1624 if (eld->monitor_present)
1625 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1626 else
1627 eld->eld_valid = false;
1628
1629 codec_dbg(codec,
1630 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1631 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1632
1633 if (eld->eld_valid) {
1634 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1635 eld->eld_buffer, &eld->eld_size) < 0)
1636 eld->eld_valid = false;
1637 }
1638
1639 update_eld(codec, per_pin, eld, repoll);
1640 mutex_unlock(&per_pin->lock);
1641 out:
1642 snd_hda_power_down_pm(codec);
1643}
1644
1645static void silent_stream_enable(struct hda_codec *codec,
1646 struct hdmi_spec_per_pin *per_pin)
1647{
1648 unsigned int newval, oldval;
1649
1650 codec_dbg(codec, "hdmi: enabling silent stream for NID %d\n",
1651 per_pin->pin_nid);
1652
1653 mutex_lock(&per_pin->lock);
1654
1655 if (!per_pin->channels)
1656 per_pin->channels = 2;
1657
1658 oldval = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1659 AC_VERB_GET_CONV, 0);
1660 newval = (oldval & 0xF0) | 0xF;
1661 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1662 AC_VERB_SET_CHANNEL_STREAMID, newval);
1663
1664 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1665
1666 mutex_unlock(&per_pin->lock);
1667}
1668
1669/* update ELD and jack state via audio component */
1670static void sync_eld_via_acomp(struct hda_codec *codec,
1671 struct hdmi_spec_per_pin *per_pin)
1672{
1673 struct hdmi_spec *spec = codec->spec;
1674 struct hdmi_eld *eld = &spec->temp_eld;
1675 bool monitor_prev, monitor_next;
1676
1677 mutex_lock(&per_pin->lock);
1678 eld->monitor_present = false;
1679 monitor_prev = per_pin->sink_eld.monitor_present;
1680 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1681 per_pin->dev_id, &eld->monitor_present,
1682 eld->eld_buffer, ELD_MAX_SIZE);
1683 eld->eld_valid = (eld->eld_size > 0);
1684 update_eld(codec, per_pin, eld, 0);
1685 monitor_next = per_pin->sink_eld.monitor_present;
1686 mutex_unlock(&per_pin->lock);
1687
1688 /*
1689 * Power-up will call hdmi_present_sense, so the PM calls
1690 * have to be done without mutex held.
1691 */
1692
1693 if (spec->send_silent_stream) {
1694 int pm_ret;
1695
1696 if (!monitor_prev && monitor_next) {
1697 pm_ret = snd_hda_power_up_pm(codec);
1698 if (pm_ret < 0)
1699 codec_err(codec,
1700 "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
1701 pm_ret);
1702 silent_stream_enable(codec, per_pin);
1703 } else if (monitor_prev && !monitor_next) {
1704 pm_ret = snd_hda_power_down_pm(codec);
1705 if (pm_ret < 0)
1706 codec_err(codec,
1707 "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
1708 pm_ret);
1709 }
1710 }
1711}
1712
1713static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1714{
1715 struct hda_codec *codec = per_pin->codec;
1716
1717 if (!codec_has_acomp(codec))
1718 hdmi_present_sense_via_verbs(per_pin, repoll);
1719 else
1720 sync_eld_via_acomp(codec, per_pin);
1721}
1722
1723static void hdmi_repoll_eld(struct work_struct *work)
1724{
1725 struct hdmi_spec_per_pin *per_pin =
1726 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1727 struct hda_codec *codec = per_pin->codec;
1728 struct hdmi_spec *spec = codec->spec;
1729 struct hda_jack_tbl *jack;
1730
1731 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1732 per_pin->dev_id);
1733 if (jack)
1734 jack->jack_dirty = 1;
1735
1736 if (per_pin->repoll_count++ > 6)
1737 per_pin->repoll_count = 0;
1738
1739 mutex_lock(&spec->pcm_lock);
1740 hdmi_present_sense(per_pin, per_pin->repoll_count);
1741 mutex_unlock(&spec->pcm_lock);
1742}
1743
1744static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1745{
1746 struct hdmi_spec *spec = codec->spec;
1747 unsigned int caps, config;
1748 int pin_idx;
1749 struct hdmi_spec_per_pin *per_pin;
1750 int err;
1751 int dev_num, i;
1752
1753 caps = snd_hda_query_pin_caps(codec, pin_nid);
1754 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1755 return 0;
1756
1757 /*
1758 * For DP MST audio, Configuration Default is the same for
1759 * all device entries on the same pin
1760 */
1761 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1762 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1763 !spec->force_connect)
1764 return 0;
1765
1766 /*
1767 * To simplify the implementation, malloc all
1768 * the virtual pins in the initialization statically
1769 */
1770 if (spec->intel_hsw_fixup) {
1771 /*
1772 * On Intel platforms, device entries number is
1773 * changed dynamically. If there is a DP MST
1774 * hub connected, the device entries number is 3.
1775 * Otherwise, it is 1.
1776 * Here we manually set dev_num to 3, so that
1777 * we can initialize all the device entries when
1778 * bootup statically.
1779 */
1780 dev_num = 3;
1781 spec->dev_num = 3;
1782 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1783 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1784 /*
1785 * spec->dev_num is the maxinum number of device entries
1786 * among all the pins
1787 */
1788 spec->dev_num = (spec->dev_num > dev_num) ?
1789 spec->dev_num : dev_num;
1790 } else {
1791 /*
1792 * If the platform doesn't support DP MST,
1793 * manually set dev_num to 1. This means
1794 * the pin has only one device entry.
1795 */
1796 dev_num = 1;
1797 spec->dev_num = 1;
1798 }
1799
1800 for (i = 0; i < dev_num; i++) {
1801 pin_idx = spec->num_pins;
1802 per_pin = snd_array_new(&spec->pins);
1803
1804 if (!per_pin)
1805 return -ENOMEM;
1806
1807 if (spec->dyn_pcm_assign) {
1808 per_pin->pcm = NULL;
1809 per_pin->pcm_idx = -1;
1810 } else {
1811 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1812 per_pin->pcm_idx = pin_idx;
1813 }
1814 per_pin->pin_nid = pin_nid;
1815 per_pin->pin_nid_idx = spec->num_nids;
1816 per_pin->dev_id = i;
1817 per_pin->non_pcm = false;
1818 snd_hda_set_dev_select(codec, pin_nid, i);
1819 err = hdmi_read_pin_conn(codec, pin_idx);
1820 if (err < 0)
1821 return err;
1822 spec->num_pins++;
1823 }
1824 spec->num_nids++;
1825
1826 return 0;
1827}
1828
1829static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1830{
1831 struct hdmi_spec *spec = codec->spec;
1832 struct hdmi_spec_per_cvt *per_cvt;
1833 unsigned int chans;
1834 int err;
1835
1836 chans = get_wcaps(codec, cvt_nid);
1837 chans = get_wcaps_channels(chans);
1838
1839 per_cvt = snd_array_new(&spec->cvts);
1840 if (!per_cvt)
1841 return -ENOMEM;
1842
1843 per_cvt->cvt_nid = cvt_nid;
1844 per_cvt->channels_min = 2;
1845 if (chans <= 16) {
1846 per_cvt->channels_max = chans;
1847 if (chans > spec->chmap.channels_max)
1848 spec->chmap.channels_max = chans;
1849 }
1850
1851 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1852 &per_cvt->rates,
1853 &per_cvt->formats,
1854 &per_cvt->maxbps);
1855 if (err < 0)
1856 return err;
1857
1858 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1859 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1860 spec->num_cvts++;
1861
1862 return 0;
1863}
1864
1865static const struct snd_pci_quirk force_connect_list[] = {
1866 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1867 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1868 {}
1869};
1870
1871static int hdmi_parse_codec(struct hda_codec *codec)
1872{
1873 struct hdmi_spec *spec = codec->spec;
1874 hda_nid_t start_nid;
1875 unsigned int caps;
1876 int i, nodes;
1877 const struct snd_pci_quirk *q;
1878
1879 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1880 if (!start_nid || nodes < 0) {
1881 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1882 return -EINVAL;
1883 }
1884
1885 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
1886
1887 if (q && q->value)
1888 spec->force_connect = true;
1889
1890 /*
1891 * hdmi_add_pin() assumes total amount of converters to
1892 * be known, so first discover all converters
1893 */
1894 for (i = 0; i < nodes; i++) {
1895 hda_nid_t nid = start_nid + i;
1896
1897 caps = get_wcaps(codec, nid);
1898
1899 if (!(caps & AC_WCAP_DIGITAL))
1900 continue;
1901
1902 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
1903 hdmi_add_cvt(codec, nid);
1904 }
1905
1906 /* discover audio pins */
1907 for (i = 0; i < nodes; i++) {
1908 hda_nid_t nid = start_nid + i;
1909
1910 caps = get_wcaps(codec, nid);
1911
1912 if (!(caps & AC_WCAP_DIGITAL))
1913 continue;
1914
1915 if (get_wcaps_type(caps) == AC_WID_PIN)
1916 hdmi_add_pin(codec, nid);
1917 }
1918
1919 return 0;
1920}
1921
1922/*
1923 */
1924static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1925{
1926 struct hda_spdif_out *spdif;
1927 bool non_pcm;
1928
1929 mutex_lock(&codec->spdif_mutex);
1930 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1931 /* Add sanity check to pass klockwork check.
1932 * This should never happen.
1933 */
1934 if (WARN_ON(spdif == NULL)) {
1935 mutex_unlock(&codec->spdif_mutex);
1936 return true;
1937 }
1938 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1939 mutex_unlock(&codec->spdif_mutex);
1940 return non_pcm;
1941}
1942
1943/*
1944 * HDMI callbacks
1945 */
1946
1947static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1948 struct hda_codec *codec,
1949 unsigned int stream_tag,
1950 unsigned int format,
1951 struct snd_pcm_substream *substream)
1952{
1953 hda_nid_t cvt_nid = hinfo->nid;
1954 struct hdmi_spec *spec = codec->spec;
1955 int pin_idx;
1956 struct hdmi_spec_per_pin *per_pin;
1957 struct snd_pcm_runtime *runtime = substream->runtime;
1958 bool non_pcm;
1959 int pinctl, stripe;
1960 int err = 0;
1961
1962 mutex_lock(&spec->pcm_lock);
1963 pin_idx = hinfo_to_pin_index(codec, hinfo);
1964 if (spec->dyn_pcm_assign && pin_idx < 0) {
1965 /* when dyn_pcm_assign and pcm is not bound to a pin
1966 * skip pin setup and return 0 to make audio playback
1967 * be ongoing
1968 */
1969 pin_cvt_fixup(codec, NULL, cvt_nid);
1970 snd_hda_codec_setup_stream(codec, cvt_nid,
1971 stream_tag, 0, format);
1972 goto unlock;
1973 }
1974
1975 if (snd_BUG_ON(pin_idx < 0)) {
1976 err = -EINVAL;
1977 goto unlock;
1978 }
1979 per_pin = get_pin(spec, pin_idx);
1980
1981 /* Verify pin:cvt selections to avoid silent audio after S3.
1982 * After S3, the audio driver restores pin:cvt selections
1983 * but this can happen before gfx is ready and such selection
1984 * is overlooked by HW. Thus multiple pins can share a same
1985 * default convertor and mute control will affect each other,
1986 * which can cause a resumed audio playback become silent
1987 * after S3.
1988 */
1989 pin_cvt_fixup(codec, per_pin, 0);
1990
1991 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1992 /* Todo: add DP1.2 MST audio support later */
1993 if (codec_has_acomp(codec))
1994 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1995 per_pin->dev_id, runtime->rate);
1996
1997 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1998 mutex_lock(&per_pin->lock);
1999 per_pin->channels = substream->runtime->channels;
2000 per_pin->setup = true;
2001
2002 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2003 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2004 substream);
2005 snd_hda_codec_write(codec, cvt_nid, 0,
2006 AC_VERB_SET_STRIPE_CONTROL,
2007 stripe);
2008 }
2009
2010 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2011 mutex_unlock(&per_pin->lock);
2012 if (spec->dyn_pin_out) {
2013 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2014 per_pin->dev_id);
2015 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2016 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2017 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2018 AC_VERB_SET_PIN_WIDGET_CONTROL,
2019 pinctl | PIN_OUT);
2020 }
2021
2022 /* snd_hda_set_dev_select() has been called before */
2023 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2024 per_pin->dev_id, stream_tag, format);
2025 unlock:
2026 mutex_unlock(&spec->pcm_lock);
2027 return err;
2028}
2029
2030static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2031 struct hda_codec *codec,
2032 struct snd_pcm_substream *substream)
2033{
2034 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2035 return 0;
2036}
2037
2038static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2039 struct hda_codec *codec,
2040 struct snd_pcm_substream *substream)
2041{
2042 struct hdmi_spec *spec = codec->spec;
2043 int cvt_idx, pin_idx, pcm_idx;
2044 struct hdmi_spec_per_cvt *per_cvt;
2045 struct hdmi_spec_per_pin *per_pin;
2046 int pinctl;
2047 int err = 0;
2048
2049 if (hinfo->nid) {
2050 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2051 if (snd_BUG_ON(pcm_idx < 0))
2052 return -EINVAL;
2053 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2054 if (snd_BUG_ON(cvt_idx < 0))
2055 return -EINVAL;
2056 per_cvt = get_cvt(spec, cvt_idx);
2057
2058 snd_BUG_ON(!per_cvt->assigned);
2059 per_cvt->assigned = 0;
2060 hinfo->nid = 0;
2061
2062 azx_stream(get_azx_dev(substream))->stripe = 0;
2063
2064 mutex_lock(&spec->pcm_lock);
2065 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2066 clear_bit(pcm_idx, &spec->pcm_in_use);
2067 pin_idx = hinfo_to_pin_index(codec, hinfo);
2068 if (spec->dyn_pcm_assign && pin_idx < 0)
2069 goto unlock;
2070
2071 if (snd_BUG_ON(pin_idx < 0)) {
2072 err = -EINVAL;
2073 goto unlock;
2074 }
2075 per_pin = get_pin(spec, pin_idx);
2076
2077 if (spec->dyn_pin_out) {
2078 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2079 per_pin->dev_id);
2080 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2081 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2082 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2083 AC_VERB_SET_PIN_WIDGET_CONTROL,
2084 pinctl & ~PIN_OUT);
2085 }
2086
2087 mutex_lock(&per_pin->lock);
2088 per_pin->chmap_set = false;
2089 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2090
2091 per_pin->setup = false;
2092 per_pin->channels = 0;
2093 mutex_unlock(&per_pin->lock);
2094 unlock:
2095 mutex_unlock(&spec->pcm_lock);
2096 }
2097
2098 return err;
2099}
2100
2101static const struct hda_pcm_ops generic_ops = {
2102 .open = hdmi_pcm_open,
2103 .close = hdmi_pcm_close,
2104 .prepare = generic_hdmi_playback_pcm_prepare,
2105 .cleanup = generic_hdmi_playback_pcm_cleanup,
2106};
2107
2108static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2109{
2110 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2111 struct hdmi_spec *spec = codec->spec;
2112 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2113
2114 if (!per_pin)
2115 return 0;
2116
2117 return per_pin->sink_eld.info.spk_alloc;
2118}
2119
2120static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2121 unsigned char *chmap)
2122{
2123 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2124 struct hdmi_spec *spec = codec->spec;
2125 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2126
2127 /* chmap is already set to 0 in caller */
2128 if (!per_pin)
2129 return;
2130
2131 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2132}
2133
2134static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2135 unsigned char *chmap, int prepared)
2136{
2137 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2138 struct hdmi_spec *spec = codec->spec;
2139 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2140
2141 if (!per_pin)
2142 return;
2143 mutex_lock(&per_pin->lock);
2144 per_pin->chmap_set = true;
2145 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2146 if (prepared)
2147 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2148 mutex_unlock(&per_pin->lock);
2149}
2150
2151static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2152{
2153 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2154 struct hdmi_spec *spec = codec->spec;
2155 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2156
2157 return per_pin ? true:false;
2158}
2159
2160static int generic_hdmi_build_pcms(struct hda_codec *codec)
2161{
2162 struct hdmi_spec *spec = codec->spec;
2163 int idx, pcm_num;
2164
2165 /*
2166 * for non-mst mode, pcm number is the same as before
2167 * for DP MST mode without extra PCM, pcm number is same
2168 * for DP MST mode with extra PCMs, pcm number is
2169 * (nid number + dev_num - 1)
2170 * dev_num is the device entry number in a pin
2171 */
2172
2173 if (codec->mst_no_extra_pcms)
2174 pcm_num = spec->num_nids;
2175 else
2176 pcm_num = spec->num_nids + spec->dev_num - 1;
2177
2178 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2179
2180 for (idx = 0; idx < pcm_num; idx++) {
2181 struct hda_pcm *info;
2182 struct hda_pcm_stream *pstr;
2183
2184 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2185 if (!info)
2186 return -ENOMEM;
2187
2188 spec->pcm_rec[idx].pcm = info;
2189 spec->pcm_used++;
2190 info->pcm_type = HDA_PCM_TYPE_HDMI;
2191 info->own_chmap = true;
2192
2193 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2194 pstr->substreams = 1;
2195 pstr->ops = generic_ops;
2196 /* pcm number is less than 16 */
2197 if (spec->pcm_used >= 16)
2198 break;
2199 /* other pstr fields are set in open */
2200 }
2201
2202 return 0;
2203}
2204
2205static void free_hdmi_jack_priv(struct snd_jack *jack)
2206{
2207 struct hdmi_pcm *pcm = jack->private_data;
2208
2209 pcm->jack = NULL;
2210}
2211
2212static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2213{
2214 char hdmi_str[32] = "HDMI/DP";
2215 struct hdmi_spec *spec = codec->spec;
2216 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2217 struct snd_jack *jack;
2218 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2219 int err;
2220
2221 if (pcmdev > 0)
2222 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2223 if (!spec->dyn_pcm_assign &&
2224 !is_jack_detectable(codec, per_pin->pin_nid))
2225 strncat(hdmi_str, " Phantom",
2226 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2227
2228 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2229 true, false);
2230 if (err < 0)
2231 return err;
2232
2233 spec->pcm_rec[pcm_idx].jack = jack;
2234 jack->private_data = &spec->pcm_rec[pcm_idx];
2235 jack->private_free = free_hdmi_jack_priv;
2236 return 0;
2237}
2238
2239static int generic_hdmi_build_controls(struct hda_codec *codec)
2240{
2241 struct hdmi_spec *spec = codec->spec;
2242 int dev, err;
2243 int pin_idx, pcm_idx;
2244
2245 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2246 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2247 /* no PCM: mark this for skipping permanently */
2248 set_bit(pcm_idx, &spec->pcm_bitmap);
2249 continue;
2250 }
2251
2252 err = generic_hdmi_build_jack(codec, pcm_idx);
2253 if (err < 0)
2254 return err;
2255
2256 /* create the spdif for each pcm
2257 * pin will be bound when monitor is connected
2258 */
2259 if (spec->dyn_pcm_assign)
2260 err = snd_hda_create_dig_out_ctls(codec,
2261 0, spec->cvt_nids[0],
2262 HDA_PCM_TYPE_HDMI);
2263 else {
2264 struct hdmi_spec_per_pin *per_pin =
2265 get_pin(spec, pcm_idx);
2266 err = snd_hda_create_dig_out_ctls(codec,
2267 per_pin->pin_nid,
2268 per_pin->mux_nids[0],
2269 HDA_PCM_TYPE_HDMI);
2270 }
2271 if (err < 0)
2272 return err;
2273 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2274
2275 dev = get_pcm_rec(spec, pcm_idx)->device;
2276 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2277 /* add control for ELD Bytes */
2278 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2279 if (err < 0)
2280 return err;
2281 }
2282 }
2283
2284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2285 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2286 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2287
2288 pin_eld->eld_valid = false;
2289 hdmi_present_sense(per_pin, 0);
2290 }
2291
2292 /* add channel maps */
2293 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2294 struct hda_pcm *pcm;
2295
2296 pcm = get_pcm_rec(spec, pcm_idx);
2297 if (!pcm || !pcm->pcm)
2298 break;
2299 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2300 if (err < 0)
2301 return err;
2302 }
2303
2304 return 0;
2305}
2306
2307static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec = codec->spec;
2310 int pin_idx;
2311
2312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2313 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2314
2315 per_pin->codec = codec;
2316 mutex_init(&per_pin->lock);
2317 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2318 eld_proc_new(per_pin, pin_idx);
2319 }
2320 return 0;
2321}
2322
2323static int generic_hdmi_init(struct hda_codec *codec)
2324{
2325 struct hdmi_spec *spec = codec->spec;
2326 int pin_idx;
2327
2328 mutex_lock(&spec->bind_lock);
2329 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2330 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2331 hda_nid_t pin_nid = per_pin->pin_nid;
2332 int dev_id = per_pin->dev_id;
2333
2334 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2335 hdmi_init_pin(codec, pin_nid);
2336 if (codec_has_acomp(codec))
2337 continue;
2338 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2339 jack_callback);
2340 }
2341 mutex_unlock(&spec->bind_lock);
2342 return 0;
2343}
2344
2345static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2346{
2347 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2348 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2349}
2350
2351static void hdmi_array_free(struct hdmi_spec *spec)
2352{
2353 snd_array_free(&spec->pins);
2354 snd_array_free(&spec->cvts);
2355}
2356
2357static void generic_spec_free(struct hda_codec *codec)
2358{
2359 struct hdmi_spec *spec = codec->spec;
2360
2361 if (spec) {
2362 hdmi_array_free(spec);
2363 kfree(spec);
2364 codec->spec = NULL;
2365 }
2366 codec->dp_mst = false;
2367}
2368
2369static void generic_hdmi_free(struct hda_codec *codec)
2370{
2371 struct hdmi_spec *spec = codec->spec;
2372 int pin_idx, pcm_idx;
2373
2374 if (spec->acomp_registered) {
2375 snd_hdac_acomp_exit(&codec->bus->core);
2376 } else if (codec_has_acomp(codec)) {
2377 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2378 }
2379 codec->relaxed_resume = 0;
2380
2381 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2382 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2383 cancel_delayed_work_sync(&per_pin->work);
2384 eld_proc_free(per_pin);
2385 }
2386
2387 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2388 if (spec->pcm_rec[pcm_idx].jack == NULL)
2389 continue;
2390 if (spec->dyn_pcm_assign)
2391 snd_device_free(codec->card,
2392 spec->pcm_rec[pcm_idx].jack);
2393 else
2394 spec->pcm_rec[pcm_idx].jack = NULL;
2395 }
2396
2397 generic_spec_free(codec);
2398}
2399
2400#ifdef CONFIG_PM
2401static int generic_hdmi_resume(struct hda_codec *codec)
2402{
2403 struct hdmi_spec *spec = codec->spec;
2404 int pin_idx;
2405
2406 codec->patch_ops.init(codec);
2407 snd_hda_regmap_sync(codec);
2408
2409 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2410 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2411 hdmi_present_sense(per_pin, 1);
2412 }
2413 return 0;
2414}
2415#endif
2416
2417static const struct hda_codec_ops generic_hdmi_patch_ops = {
2418 .init = generic_hdmi_init,
2419 .free = generic_hdmi_free,
2420 .build_pcms = generic_hdmi_build_pcms,
2421 .build_controls = generic_hdmi_build_controls,
2422 .unsol_event = hdmi_unsol_event,
2423#ifdef CONFIG_PM
2424 .resume = generic_hdmi_resume,
2425#endif
2426};
2427
2428static const struct hdmi_ops generic_standard_hdmi_ops = {
2429 .pin_get_eld = hdmi_pin_get_eld,
2430 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2431 .pin_hbr_setup = hdmi_pin_hbr_setup,
2432 .setup_stream = hdmi_setup_stream,
2433};
2434
2435/* allocate codec->spec and assign/initialize generic parser ops */
2436static int alloc_generic_hdmi(struct hda_codec *codec)
2437{
2438 struct hdmi_spec *spec;
2439
2440 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2441 if (!spec)
2442 return -ENOMEM;
2443
2444 spec->codec = codec;
2445 spec->ops = generic_standard_hdmi_ops;
2446 spec->dev_num = 1; /* initialize to 1 */
2447 mutex_init(&spec->pcm_lock);
2448 mutex_init(&spec->bind_lock);
2449 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2450
2451 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2452 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2453 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2454 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2455
2456 codec->spec = spec;
2457 hdmi_array_init(spec, 4);
2458
2459 codec->patch_ops = generic_hdmi_patch_ops;
2460
2461 return 0;
2462}
2463
2464/* generic HDMI parser */
2465static int patch_generic_hdmi(struct hda_codec *codec)
2466{
2467 int err;
2468
2469 err = alloc_generic_hdmi(codec);
2470 if (err < 0)
2471 return err;
2472
2473 err = hdmi_parse_codec(codec);
2474 if (err < 0) {
2475 generic_spec_free(codec);
2476 return err;
2477 }
2478
2479 generic_hdmi_init_per_pins(codec);
2480 return 0;
2481}
2482
2483/*
2484 * generic audio component binding
2485 */
2486
2487/* turn on / off the unsol event jack detection dynamically */
2488static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2489 int dev_id, bool use_acomp)
2490{
2491 struct hda_jack_tbl *tbl;
2492
2493 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2494 if (tbl) {
2495 /* clear unsol even if component notifier is used, or re-enable
2496 * if notifier is cleared
2497 */
2498 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2499 snd_hda_codec_write_cache(codec, nid, 0,
2500 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2501 }
2502}
2503
2504/* set up / clear component notifier dynamically */
2505static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2506 bool use_acomp)
2507{
2508 struct hdmi_spec *spec;
2509 int i;
2510
2511 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2512 mutex_lock(&spec->bind_lock);
2513 spec->use_acomp_notifier = use_acomp;
2514 spec->codec->relaxed_resume = use_acomp;
2515 spec->codec->bus->keep_power = 0;
2516 /* reprogram each jack detection logic depending on the notifier */
2517 for (i = 0; i < spec->num_pins; i++)
2518 reprogram_jack_detect(spec->codec,
2519 get_pin(spec, i)->pin_nid,
2520 get_pin(spec, i)->dev_id,
2521 use_acomp);
2522 mutex_unlock(&spec->bind_lock);
2523}
2524
2525/* enable / disable the notifier via master bind / unbind */
2526static int generic_acomp_master_bind(struct device *dev,
2527 struct drm_audio_component *acomp)
2528{
2529 generic_acomp_notifier_set(acomp, true);
2530 return 0;
2531}
2532
2533static void generic_acomp_master_unbind(struct device *dev,
2534 struct drm_audio_component *acomp)
2535{
2536 generic_acomp_notifier_set(acomp, false);
2537}
2538
2539/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2540static int match_bound_vga(struct device *dev, int subtype, void *data)
2541{
2542 struct hdac_bus *bus = data;
2543 struct pci_dev *pci, *master;
2544
2545 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2546 return 0;
2547 master = to_pci_dev(bus->dev);
2548 pci = to_pci_dev(dev);
2549 return master->bus == pci->bus;
2550}
2551
2552/* audio component notifier for AMD/Nvidia HDMI codecs */
2553static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2554{
2555 struct hda_codec *codec = audio_ptr;
2556 struct hdmi_spec *spec = codec->spec;
2557 hda_nid_t pin_nid = spec->port2pin(codec, port);
2558
2559 if (!pin_nid)
2560 return;
2561 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2562 return;
2563 /* skip notification during system suspend (but not in runtime PM);
2564 * the state will be updated at resume
2565 */
2566 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2567 return;
2568 /* ditto during suspend/resume process itself */
2569 if (snd_hdac_is_in_pm(&codec->core))
2570 return;
2571
2572 check_presence_and_report(codec, pin_nid, dev_id);
2573}
2574
2575/* set up the private drm_audio_ops from the template */
2576static void setup_drm_audio_ops(struct hda_codec *codec,
2577 const struct drm_audio_component_audio_ops *ops)
2578{
2579 struct hdmi_spec *spec = codec->spec;
2580
2581 spec->drm_audio_ops.audio_ptr = codec;
2582 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2583 * will call pin_eld_notify with using audio_ptr pointer
2584 * We need make sure audio_ptr is really setup
2585 */
2586 wmb();
2587 spec->drm_audio_ops.pin2port = ops->pin2port;
2588 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2589 spec->drm_audio_ops.master_bind = ops->master_bind;
2590 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2591}
2592
2593/* initialize the generic HDMI audio component */
2594static void generic_acomp_init(struct hda_codec *codec,
2595 const struct drm_audio_component_audio_ops *ops,
2596 int (*port2pin)(struct hda_codec *, int))
2597{
2598 struct hdmi_spec *spec = codec->spec;
2599
2600 if (!enable_acomp) {
2601 codec_info(codec, "audio component disabled by module option\n");
2602 return;
2603 }
2604
2605 spec->port2pin = port2pin;
2606 setup_drm_audio_ops(codec, ops);
2607 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2608 match_bound_vga, 0)) {
2609 spec->acomp_registered = true;
2610 }
2611}
2612
2613/*
2614 * Intel codec parsers and helpers
2615 */
2616
2617#define INTEL_GET_VENDOR_VERB 0xf81
2618#define INTEL_SET_VENDOR_VERB 0x781
2619#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2620#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2621
2622static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2623 bool update_tree)
2624{
2625 unsigned int vendor_param;
2626 struct hdmi_spec *spec = codec->spec;
2627
2628 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2629 INTEL_GET_VENDOR_VERB, 0);
2630 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2631 return;
2632
2633 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2634 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2635 INTEL_SET_VENDOR_VERB, vendor_param);
2636 if (vendor_param == -1)
2637 return;
2638
2639 if (update_tree)
2640 snd_hda_codec_update_widgets(codec);
2641}
2642
2643static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2644{
2645 unsigned int vendor_param;
2646 struct hdmi_spec *spec = codec->spec;
2647
2648 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2649 INTEL_GET_VENDOR_VERB, 0);
2650 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2651 return;
2652
2653 /* enable DP1.2 mode */
2654 vendor_param |= INTEL_EN_DP12;
2655 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2656 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2657 INTEL_SET_VENDOR_VERB, vendor_param);
2658}
2659
2660/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2661 * Otherwise you may get severe h/w communication errors.
2662 */
2663static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2664 unsigned int power_state)
2665{
2666 if (power_state == AC_PWRST_D0) {
2667 intel_haswell_enable_all_pins(codec, false);
2668 intel_haswell_fixup_enable_dp12(codec);
2669 }
2670
2671 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2672 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2673}
2674
2675/* There is a fixed mapping between audio pin node and display port.
2676 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2677 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2678 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2679 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2680 *
2681 * on VLV, ILK:
2682 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2683 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2684 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2685 */
2686static int intel_base_nid(struct hda_codec *codec)
2687{
2688 switch (codec->core.vendor_id) {
2689 case 0x80860054: /* ILK */
2690 case 0x80862804: /* ILK */
2691 case 0x80862882: /* VLV */
2692 return 4;
2693 default:
2694 return 5;
2695 }
2696}
2697
2698static int intel_pin2port(void *audio_ptr, int pin_nid)
2699{
2700 struct hda_codec *codec = audio_ptr;
2701 struct hdmi_spec *spec = codec->spec;
2702 int base_nid, i;
2703
2704 if (!spec->port_num) {
2705 base_nid = intel_base_nid(codec);
2706 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2707 return -1;
2708 return pin_nid - base_nid + 1;
2709 }
2710
2711 /*
2712 * looking for the pin number in the mapping table and return
2713 * the index which indicate the port number
2714 */
2715 for (i = 0; i < spec->port_num; i++) {
2716 if (pin_nid == spec->port_map[i])
2717 return i;
2718 }
2719
2720 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2721 return -1;
2722}
2723
2724static int intel_port2pin(struct hda_codec *codec, int port)
2725{
2726 struct hdmi_spec *spec = codec->spec;
2727
2728 if (!spec->port_num) {
2729 /* we assume only from port-B to port-D */
2730 if (port < 1 || port > 3)
2731 return 0;
2732 return port + intel_base_nid(codec) - 1;
2733 }
2734
2735 if (port < 0 || port >= spec->port_num)
2736 return 0;
2737 return spec->port_map[port];
2738}
2739
2740static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2741{
2742 struct hda_codec *codec = audio_ptr;
2743 int pin_nid;
2744 int dev_id = pipe;
2745
2746 pin_nid = intel_port2pin(codec, port);
2747 if (!pin_nid)
2748 return;
2749 /* skip notification during system suspend (but not in runtime PM);
2750 * the state will be updated at resume
2751 */
2752 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2753 return;
2754 /* ditto during suspend/resume process itself */
2755 if (snd_hdac_is_in_pm(&codec->core))
2756 return;
2757
2758 snd_hdac_i915_set_bclk(&codec->bus->core);
2759 check_presence_and_report(codec, pin_nid, dev_id);
2760}
2761
2762static const struct drm_audio_component_audio_ops intel_audio_ops = {
2763 .pin2port = intel_pin2port,
2764 .pin_eld_notify = intel_pin_eld_notify,
2765};
2766
2767/* register i915 component pin_eld_notify callback */
2768static void register_i915_notifier(struct hda_codec *codec)
2769{
2770 struct hdmi_spec *spec = codec->spec;
2771
2772 spec->use_acomp_notifier = true;
2773 spec->port2pin = intel_port2pin;
2774 setup_drm_audio_ops(codec, &intel_audio_ops);
2775 snd_hdac_acomp_register_notifier(&codec->bus->core,
2776 &spec->drm_audio_ops);
2777 /* no need for forcible resume for jack check thanks to notifier */
2778 codec->relaxed_resume = 1;
2779}
2780
2781/* setup_stream ops override for HSW+ */
2782static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2783 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2784 int format)
2785{
2786 haswell_verify_D0(codec, cvt_nid, pin_nid);
2787 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2788 stream_tag, format);
2789}
2790
2791/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2792static void i915_pin_cvt_fixup(struct hda_codec *codec,
2793 struct hdmi_spec_per_pin *per_pin,
2794 hda_nid_t cvt_nid)
2795{
2796 if (per_pin) {
2797 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2798 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2799 per_pin->dev_id);
2800 intel_verify_pin_cvt_connect(codec, per_pin);
2801 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2802 per_pin->dev_id, per_pin->mux_idx);
2803 } else {
2804 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2805 }
2806}
2807
2808/* precondition and allocation for Intel codecs */
2809static int alloc_intel_hdmi(struct hda_codec *codec)
2810{
2811 int err;
2812
2813 /* requires i915 binding */
2814 if (!codec->bus->core.audio_component) {
2815 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2816 /* set probe_id here to prevent generic fallback binding */
2817 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2818 return -ENODEV;
2819 }
2820
2821 err = alloc_generic_hdmi(codec);
2822 if (err < 0)
2823 return err;
2824 /* no need to handle unsol events */
2825 codec->patch_ops.unsol_event = NULL;
2826 return 0;
2827}
2828
2829/* parse and post-process for Intel codecs */
2830static int parse_intel_hdmi(struct hda_codec *codec)
2831{
2832 int err, retries = 3;
2833
2834 do {
2835 err = hdmi_parse_codec(codec);
2836 } while (err < 0 && retries--);
2837
2838 if (err < 0) {
2839 generic_spec_free(codec);
2840 return err;
2841 }
2842
2843 generic_hdmi_init_per_pins(codec);
2844 register_i915_notifier(codec);
2845 return 0;
2846}
2847
2848/* Intel Haswell and onwards; audio component with eld notifier */
2849static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2850 const int *port_map, int port_num)
2851{
2852 struct hdmi_spec *spec;
2853 int err;
2854
2855 err = alloc_intel_hdmi(codec);
2856 if (err < 0)
2857 return err;
2858 spec = codec->spec;
2859 codec->dp_mst = true;
2860 spec->dyn_pcm_assign = true;
2861 spec->vendor_nid = vendor_nid;
2862 spec->port_map = port_map;
2863 spec->port_num = port_num;
2864 spec->intel_hsw_fixup = true;
2865
2866 intel_haswell_enable_all_pins(codec, true);
2867 intel_haswell_fixup_enable_dp12(codec);
2868
2869 codec->display_power_control = 1;
2870
2871 codec->patch_ops.set_power_state = haswell_set_power_state;
2872 codec->depop_delay = 0;
2873 codec->auto_runtime_pm = 1;
2874
2875 spec->ops.setup_stream = i915_hsw_setup_stream;
2876 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2877
2878 /*
2879 * Enable silent stream feature, if it is enabled via
2880 * module param or Kconfig option
2881 */
2882 if (enable_silent_stream)
2883 spec->send_silent_stream = true;
2884
2885 return parse_intel_hdmi(codec);
2886}
2887
2888static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2889{
2890 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2891}
2892
2893static int patch_i915_glk_hdmi(struct hda_codec *codec)
2894{
2895 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2896}
2897
2898static int patch_i915_icl_hdmi(struct hda_codec *codec)
2899{
2900 /*
2901 * pin to port mapping table where the value indicate the pin number and
2902 * the index indicate the port number.
2903 */
2904 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
2905
2906 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2907}
2908
2909static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2910{
2911 /*
2912 * pin to port mapping table where the value indicate the pin number and
2913 * the index indicate the port number.
2914 */
2915 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2916
2917 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2918}
2919
2920/* Intel Baytrail and Braswell; with eld notifier */
2921static int patch_i915_byt_hdmi(struct hda_codec *codec)
2922{
2923 struct hdmi_spec *spec;
2924 int err;
2925
2926 err = alloc_intel_hdmi(codec);
2927 if (err < 0)
2928 return err;
2929 spec = codec->spec;
2930
2931 /* For Valleyview/Cherryview, only the display codec is in the display
2932 * power well and can use link_power ops to request/release the power.
2933 */
2934 codec->display_power_control = 1;
2935
2936 codec->depop_delay = 0;
2937 codec->auto_runtime_pm = 1;
2938
2939 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2940
2941 return parse_intel_hdmi(codec);
2942}
2943
2944/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2945static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2946{
2947 int err;
2948
2949 err = alloc_intel_hdmi(codec);
2950 if (err < 0)
2951 return err;
2952 return parse_intel_hdmi(codec);
2953}
2954
2955/*
2956 * Shared non-generic implementations
2957 */
2958
2959static int simple_playback_build_pcms(struct hda_codec *codec)
2960{
2961 struct hdmi_spec *spec = codec->spec;
2962 struct hda_pcm *info;
2963 unsigned int chans;
2964 struct hda_pcm_stream *pstr;
2965 struct hdmi_spec_per_cvt *per_cvt;
2966
2967 per_cvt = get_cvt(spec, 0);
2968 chans = get_wcaps(codec, per_cvt->cvt_nid);
2969 chans = get_wcaps_channels(chans);
2970
2971 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2972 if (!info)
2973 return -ENOMEM;
2974 spec->pcm_rec[0].pcm = info;
2975 info->pcm_type = HDA_PCM_TYPE_HDMI;
2976 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2977 *pstr = spec->pcm_playback;
2978 pstr->nid = per_cvt->cvt_nid;
2979 if (pstr->channels_max <= 2 && chans && chans <= 16)
2980 pstr->channels_max = chans;
2981
2982 return 0;
2983}
2984
2985/* unsolicited event for jack sensing */
2986static void simple_hdmi_unsol_event(struct hda_codec *codec,
2987 unsigned int res)
2988{
2989 snd_hda_jack_set_dirty_all(codec);
2990 snd_hda_jack_report_sync(codec);
2991}
2992
2993/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2994 * as long as spec->pins[] is set correctly
2995 */
2996#define simple_hdmi_build_jack generic_hdmi_build_jack
2997
2998static int simple_playback_build_controls(struct hda_codec *codec)
2999{
3000 struct hdmi_spec *spec = codec->spec;
3001 struct hdmi_spec_per_cvt *per_cvt;
3002 int err;
3003
3004 per_cvt = get_cvt(spec, 0);
3005 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3006 per_cvt->cvt_nid,
3007 HDA_PCM_TYPE_HDMI);
3008 if (err < 0)
3009 return err;
3010 return simple_hdmi_build_jack(codec, 0);
3011}
3012
3013static int simple_playback_init(struct hda_codec *codec)
3014{
3015 struct hdmi_spec *spec = codec->spec;
3016 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3017 hda_nid_t pin = per_pin->pin_nid;
3018
3019 snd_hda_codec_write(codec, pin, 0,
3020 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3021 /* some codecs require to unmute the pin */
3022 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3023 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3024 AMP_OUT_UNMUTE);
3025 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3026 return 0;
3027}
3028
3029static void simple_playback_free(struct hda_codec *codec)
3030{
3031 struct hdmi_spec *spec = codec->spec;
3032
3033 hdmi_array_free(spec);
3034 kfree(spec);
3035}
3036
3037/*
3038 * Nvidia specific implementations
3039 */
3040
3041#define Nv_VERB_SET_Channel_Allocation 0xF79
3042#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3043#define Nv_VERB_SET_Audio_Protection_On 0xF98
3044#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3045
3046#define nvhdmi_master_con_nid_7x 0x04
3047#define nvhdmi_master_pin_nid_7x 0x05
3048
3049static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3050 /*front, rear, clfe, rear_surr */
3051 0x6, 0x8, 0xa, 0xc,
3052};
3053
3054static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3055 /* set audio protect on */
3056 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3057 /* enable digital output on pin widget */
3058 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3059 {} /* terminator */
3060};
3061
3062static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3063 /* set audio protect on */
3064 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3065 /* enable digital output on pin widget */
3066 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3067 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3068 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3069 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3070 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3071 {} /* terminator */
3072};
3073
3074#ifdef LIMITED_RATE_FMT_SUPPORT
3075/* support only the safe format and rate */
3076#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3077#define SUPPORTED_MAXBPS 16
3078#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3079#else
3080/* support all rates and formats */
3081#define SUPPORTED_RATES \
3082 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3083 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3084 SNDRV_PCM_RATE_192000)
3085#define SUPPORTED_MAXBPS 24
3086#define SUPPORTED_FORMATS \
3087 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3088#endif
3089
3090static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3091{
3092 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3093 return 0;
3094}
3095
3096static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3097{
3098 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3099 return 0;
3100}
3101
3102static const unsigned int channels_2_6_8[] = {
3103 2, 6, 8
3104};
3105
3106static const unsigned int channels_2_8[] = {
3107 2, 8
3108};
3109
3110static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3111 .count = ARRAY_SIZE(channels_2_6_8),
3112 .list = channels_2_6_8,
3113 .mask = 0,
3114};
3115
3116static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3117 .count = ARRAY_SIZE(channels_2_8),
3118 .list = channels_2_8,
3119 .mask = 0,
3120};
3121
3122static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3123 struct hda_codec *codec,
3124 struct snd_pcm_substream *substream)
3125{
3126 struct hdmi_spec *spec = codec->spec;
3127 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3128
3129 switch (codec->preset->vendor_id) {
3130 case 0x10de0002:
3131 case 0x10de0003:
3132 case 0x10de0005:
3133 case 0x10de0006:
3134 hw_constraints_channels = &hw_constraints_2_8_channels;
3135 break;
3136 case 0x10de0007:
3137 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3138 break;
3139 default:
3140 break;
3141 }
3142
3143 if (hw_constraints_channels != NULL) {
3144 snd_pcm_hw_constraint_list(substream->runtime, 0,
3145 SNDRV_PCM_HW_PARAM_CHANNELS,
3146 hw_constraints_channels);
3147 } else {
3148 snd_pcm_hw_constraint_step(substream->runtime, 0,
3149 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3150 }
3151
3152 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3153}
3154
3155static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3156 struct hda_codec *codec,
3157 struct snd_pcm_substream *substream)
3158{
3159 struct hdmi_spec *spec = codec->spec;
3160 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3161}
3162
3163static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3164 struct hda_codec *codec,
3165 unsigned int stream_tag,
3166 unsigned int format,
3167 struct snd_pcm_substream *substream)
3168{
3169 struct hdmi_spec *spec = codec->spec;
3170 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3171 stream_tag, format, substream);
3172}
3173
3174static const struct hda_pcm_stream simple_pcm_playback = {
3175 .substreams = 1,
3176 .channels_min = 2,
3177 .channels_max = 2,
3178 .ops = {
3179 .open = simple_playback_pcm_open,
3180 .close = simple_playback_pcm_close,
3181 .prepare = simple_playback_pcm_prepare
3182 },
3183};
3184
3185static const struct hda_codec_ops simple_hdmi_patch_ops = {
3186 .build_controls = simple_playback_build_controls,
3187 .build_pcms = simple_playback_build_pcms,
3188 .init = simple_playback_init,
3189 .free = simple_playback_free,
3190 .unsol_event = simple_hdmi_unsol_event,
3191};
3192
3193static int patch_simple_hdmi(struct hda_codec *codec,
3194 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3195{
3196 struct hdmi_spec *spec;
3197 struct hdmi_spec_per_cvt *per_cvt;
3198 struct hdmi_spec_per_pin *per_pin;
3199
3200 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3201 if (!spec)
3202 return -ENOMEM;
3203
3204 spec->codec = codec;
3205 codec->spec = spec;
3206 hdmi_array_init(spec, 1);
3207
3208 spec->multiout.num_dacs = 0; /* no analog */
3209 spec->multiout.max_channels = 2;
3210 spec->multiout.dig_out_nid = cvt_nid;
3211 spec->num_cvts = 1;
3212 spec->num_pins = 1;
3213 per_pin = snd_array_new(&spec->pins);
3214 per_cvt = snd_array_new(&spec->cvts);
3215 if (!per_pin || !per_cvt) {
3216 simple_playback_free(codec);
3217 return -ENOMEM;
3218 }
3219 per_cvt->cvt_nid = cvt_nid;
3220 per_pin->pin_nid = pin_nid;
3221 spec->pcm_playback = simple_pcm_playback;
3222
3223 codec->patch_ops = simple_hdmi_patch_ops;
3224
3225 return 0;
3226}
3227
3228static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3229 int channels)
3230{
3231 unsigned int chanmask;
3232 int chan = channels ? (channels - 1) : 1;
3233
3234 switch (channels) {
3235 default:
3236 case 0:
3237 case 2:
3238 chanmask = 0x00;
3239 break;
3240 case 4:
3241 chanmask = 0x08;
3242 break;
3243 case 6:
3244 chanmask = 0x0b;
3245 break;
3246 case 8:
3247 chanmask = 0x13;
3248 break;
3249 }
3250
3251 /* Set the audio infoframe channel allocation and checksum fields. The
3252 * channel count is computed implicitly by the hardware. */
3253 snd_hda_codec_write(codec, 0x1, 0,
3254 Nv_VERB_SET_Channel_Allocation, chanmask);
3255
3256 snd_hda_codec_write(codec, 0x1, 0,
3257 Nv_VERB_SET_Info_Frame_Checksum,
3258 (0x71 - chan - chanmask));
3259}
3260
3261static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3262 struct hda_codec *codec,
3263 struct snd_pcm_substream *substream)
3264{
3265 struct hdmi_spec *spec = codec->spec;
3266 int i;
3267
3268 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3269 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3270 for (i = 0; i < 4; i++) {
3271 /* set the stream id */
3272 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3273 AC_VERB_SET_CHANNEL_STREAMID, 0);
3274 /* set the stream format */
3275 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3276 AC_VERB_SET_STREAM_FORMAT, 0);
3277 }
3278
3279 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3280 * streams are disabled. */
3281 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3282
3283 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3284}
3285
3286static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3287 struct hda_codec *codec,
3288 unsigned int stream_tag,
3289 unsigned int format,
3290 struct snd_pcm_substream *substream)
3291{
3292 int chs;
3293 unsigned int dataDCC2, channel_id;
3294 int i;
3295 struct hdmi_spec *spec = codec->spec;
3296 struct hda_spdif_out *spdif;
3297 struct hdmi_spec_per_cvt *per_cvt;
3298
3299 mutex_lock(&codec->spdif_mutex);
3300 per_cvt = get_cvt(spec, 0);
3301 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3302
3303 chs = substream->runtime->channels;
3304
3305 dataDCC2 = 0x2;
3306
3307 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3308 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3309 snd_hda_codec_write(codec,
3310 nvhdmi_master_con_nid_7x,
3311 0,
3312 AC_VERB_SET_DIGI_CONVERT_1,
3313 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3314
3315 /* set the stream id */
3316 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3317 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3318
3319 /* set the stream format */
3320 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3321 AC_VERB_SET_STREAM_FORMAT, format);
3322
3323 /* turn on again (if needed) */
3324 /* enable and set the channel status audio/data flag */
3325 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3326 snd_hda_codec_write(codec,
3327 nvhdmi_master_con_nid_7x,
3328 0,
3329 AC_VERB_SET_DIGI_CONVERT_1,
3330 spdif->ctls & 0xff);
3331 snd_hda_codec_write(codec,
3332 nvhdmi_master_con_nid_7x,
3333 0,
3334 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3335 }
3336
3337 for (i = 0; i < 4; i++) {
3338 if (chs == 2)
3339 channel_id = 0;
3340 else
3341 channel_id = i * 2;
3342
3343 /* turn off SPDIF once;
3344 *otherwise the IEC958 bits won't be updated
3345 */
3346 if (codec->spdif_status_reset &&
3347 (spdif->ctls & AC_DIG1_ENABLE))
3348 snd_hda_codec_write(codec,
3349 nvhdmi_con_nids_7x[i],
3350 0,
3351 AC_VERB_SET_DIGI_CONVERT_1,
3352 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3353 /* set the stream id */
3354 snd_hda_codec_write(codec,
3355 nvhdmi_con_nids_7x[i],
3356 0,
3357 AC_VERB_SET_CHANNEL_STREAMID,
3358 (stream_tag << 4) | channel_id);
3359 /* set the stream format */
3360 snd_hda_codec_write(codec,
3361 nvhdmi_con_nids_7x[i],
3362 0,
3363 AC_VERB_SET_STREAM_FORMAT,
3364 format);
3365 /* turn on again (if needed) */
3366 /* enable and set the channel status audio/data flag */
3367 if (codec->spdif_status_reset &&
3368 (spdif->ctls & AC_DIG1_ENABLE)) {
3369 snd_hda_codec_write(codec,
3370 nvhdmi_con_nids_7x[i],
3371 0,
3372 AC_VERB_SET_DIGI_CONVERT_1,
3373 spdif->ctls & 0xff);
3374 snd_hda_codec_write(codec,
3375 nvhdmi_con_nids_7x[i],
3376 0,
3377 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3378 }
3379 }
3380
3381 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3382
3383 mutex_unlock(&codec->spdif_mutex);
3384 return 0;
3385}
3386
3387static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3388 .substreams = 1,
3389 .channels_min = 2,
3390 .channels_max = 8,
3391 .nid = nvhdmi_master_con_nid_7x,
3392 .rates = SUPPORTED_RATES,
3393 .maxbps = SUPPORTED_MAXBPS,
3394 .formats = SUPPORTED_FORMATS,
3395 .ops = {
3396 .open = simple_playback_pcm_open,
3397 .close = nvhdmi_8ch_7x_pcm_close,
3398 .prepare = nvhdmi_8ch_7x_pcm_prepare
3399 },
3400};
3401
3402static int patch_nvhdmi_2ch(struct hda_codec *codec)
3403{
3404 struct hdmi_spec *spec;
3405 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3406 nvhdmi_master_pin_nid_7x);
3407 if (err < 0)
3408 return err;
3409
3410 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3411 /* override the PCM rates, etc, as the codec doesn't give full list */
3412 spec = codec->spec;
3413 spec->pcm_playback.rates = SUPPORTED_RATES;
3414 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3415 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3416 return 0;
3417}
3418
3419static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3420{
3421 struct hdmi_spec *spec = codec->spec;
3422 int err = simple_playback_build_pcms(codec);
3423 if (!err) {
3424 struct hda_pcm *info = get_pcm_rec(spec, 0);
3425 info->own_chmap = true;
3426 }
3427 return err;
3428}
3429
3430static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3431{
3432 struct hdmi_spec *spec = codec->spec;
3433 struct hda_pcm *info;
3434 struct snd_pcm_chmap *chmap;
3435 int err;
3436
3437 err = simple_playback_build_controls(codec);
3438 if (err < 0)
3439 return err;
3440
3441 /* add channel maps */
3442 info = get_pcm_rec(spec, 0);
3443 err = snd_pcm_add_chmap_ctls(info->pcm,
3444 SNDRV_PCM_STREAM_PLAYBACK,
3445 snd_pcm_alt_chmaps, 8, 0, &chmap);
3446 if (err < 0)
3447 return err;
3448 switch (codec->preset->vendor_id) {
3449 case 0x10de0002:
3450 case 0x10de0003:
3451 case 0x10de0005:
3452 case 0x10de0006:
3453 chmap->channel_mask = (1U << 2) | (1U << 8);
3454 break;
3455 case 0x10de0007:
3456 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3457 }
3458 return 0;
3459}
3460
3461static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3462{
3463 struct hdmi_spec *spec;
3464 int err = patch_nvhdmi_2ch(codec);
3465 if (err < 0)
3466 return err;
3467 spec = codec->spec;
3468 spec->multiout.max_channels = 8;
3469 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3470 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3471 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3472 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3473
3474 /* Initialize the audio infoframe channel mask and checksum to something
3475 * valid */
3476 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3477
3478 return 0;
3479}
3480
3481/*
3482 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3483 * - 0x10de0015
3484 * - 0x10de0040
3485 */
3486static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3487 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3488{
3489 if (cap->ca_index == 0x00 && channels == 2)
3490 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3491
3492 /* If the speaker allocation matches the channel count, it is OK. */
3493 if (cap->channels != channels)
3494 return -1;
3495
3496 /* all channels are remappable freely */
3497 return SNDRV_CTL_TLVT_CHMAP_VAR;
3498}
3499
3500static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3501 int ca, int chs, unsigned char *map)
3502{
3503 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3504 return -EINVAL;
3505
3506 return 0;
3507}
3508
3509/* map from pin NID to port; port is 0-based */
3510/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3511static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3512{
3513 return pin_nid - 4;
3514}
3515
3516/* reverse-map from port to pin NID: see above */
3517static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3518{
3519 return port + 4;
3520}
3521
3522static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3523 .pin2port = nvhdmi_pin2port,
3524 .pin_eld_notify = generic_acomp_pin_eld_notify,
3525 .master_bind = generic_acomp_master_bind,
3526 .master_unbind = generic_acomp_master_unbind,
3527};
3528
3529static int patch_nvhdmi(struct hda_codec *codec)
3530{
3531 struct hdmi_spec *spec;
3532 int err;
3533
3534 err = alloc_generic_hdmi(codec);
3535 if (err < 0)
3536 return err;
3537 codec->dp_mst = true;
3538
3539 spec = codec->spec;
3540 spec->dyn_pcm_assign = true;
3541
3542 err = hdmi_parse_codec(codec);
3543 if (err < 0) {
3544 generic_spec_free(codec);
3545 return err;
3546 }
3547
3548 generic_hdmi_init_per_pins(codec);
3549
3550 spec->dyn_pin_out = true;
3551
3552 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3553 nvhdmi_chmap_cea_alloc_validate_get_type;
3554 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3555
3556 codec->link_down_at_suspend = 1;
3557
3558 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3559
3560 return 0;
3561}
3562
3563static int patch_nvhdmi_legacy(struct hda_codec *codec)
3564{
3565 struct hdmi_spec *spec;
3566 int err;
3567
3568 err = patch_generic_hdmi(codec);
3569 if (err)
3570 return err;
3571
3572 spec = codec->spec;
3573 spec->dyn_pin_out = true;
3574
3575 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3576 nvhdmi_chmap_cea_alloc_validate_get_type;
3577 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3578
3579 codec->link_down_at_suspend = 1;
3580
3581 return 0;
3582}
3583
3584/*
3585 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3586 * accessed using vendor-defined verbs. These registers can be used for
3587 * interoperability between the HDA and HDMI drivers.
3588 */
3589
3590/* Audio Function Group node */
3591#define NVIDIA_AFG_NID 0x01
3592
3593/*
3594 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3595 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3596 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3597 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3598 * additional bit (at position 30) to signal the validity of the format.
3599 *
3600 * | 31 | 30 | 29 16 | 15 0 |
3601 * +---------+-------+--------+--------+
3602 * | TRIGGER | VALID | UNUSED | FORMAT |
3603 * +-----------------------------------|
3604 *
3605 * Note that for the trigger bit to take effect it needs to change value
3606 * (i.e. it needs to be toggled).
3607 */
3608#define NVIDIA_GET_SCRATCH0 0xfa6
3609#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3610#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3611#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3612#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3613#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3614#define NVIDIA_SCRATCH_VALID (1 << 6)
3615
3616#define NVIDIA_GET_SCRATCH1 0xfab
3617#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3618#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3619#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3620#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3621
3622/*
3623 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3624 * the format is invalidated so that the HDMI codec can be disabled.
3625 */
3626static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3627{
3628 unsigned int value;
3629
3630 /* bits [31:30] contain the trigger and valid bits */
3631 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3632 NVIDIA_GET_SCRATCH0, 0);
3633 value = (value >> 24) & 0xff;
3634
3635 /* bits [15:0] are used to store the HDA format */
3636 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3637 NVIDIA_SET_SCRATCH0_BYTE0,
3638 (format >> 0) & 0xff);
3639 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3640 NVIDIA_SET_SCRATCH0_BYTE1,
3641 (format >> 8) & 0xff);
3642
3643 /* bits [16:24] are unused */
3644 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3645 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3646
3647 /*
3648 * Bit 30 signals that the data is valid and hence that HDMI audio can
3649 * be enabled.
3650 */
3651 if (format == 0)
3652 value &= ~NVIDIA_SCRATCH_VALID;
3653 else
3654 value |= NVIDIA_SCRATCH_VALID;
3655
3656 /*
3657 * Whenever the trigger bit is toggled, an interrupt is raised in the
3658 * HDMI codec. The HDMI driver will use that as trigger to update its
3659 * configuration.
3660 */
3661 value ^= NVIDIA_SCRATCH_TRIGGER;
3662
3663 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3664 NVIDIA_SET_SCRATCH0_BYTE3, value);
3665}
3666
3667static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3668 struct hda_codec *codec,
3669 unsigned int stream_tag,
3670 unsigned int format,
3671 struct snd_pcm_substream *substream)
3672{
3673 int err;
3674
3675 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3676 format, substream);
3677 if (err < 0)
3678 return err;
3679
3680 /* notify the HDMI codec of the format change */
3681 tegra_hdmi_set_format(codec, format);
3682
3683 return 0;
3684}
3685
3686static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3687 struct hda_codec *codec,
3688 struct snd_pcm_substream *substream)
3689{
3690 /* invalidate the format in the HDMI codec */
3691 tegra_hdmi_set_format(codec, 0);
3692
3693 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3694}
3695
3696static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3697{
3698 struct hdmi_spec *spec = codec->spec;
3699 unsigned int i;
3700
3701 for (i = 0; i < spec->num_pins; i++) {
3702 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3703
3704 if (pcm->pcm_type == type)
3705 return pcm;
3706 }
3707
3708 return NULL;
3709}
3710
3711static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3712{
3713 struct hda_pcm_stream *stream;
3714 struct hda_pcm *pcm;
3715 int err;
3716
3717 err = generic_hdmi_build_pcms(codec);
3718 if (err < 0)
3719 return err;
3720
3721 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3722 if (!pcm)
3723 return -ENODEV;
3724
3725 /*
3726 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3727 * codec about format changes.
3728 */
3729 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3730 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3731 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3732
3733 return 0;
3734}
3735
3736static int patch_tegra_hdmi(struct hda_codec *codec)
3737{
3738 struct hdmi_spec *spec;
3739 int err;
3740
3741 err = patch_generic_hdmi(codec);
3742 if (err)
3743 return err;
3744
3745 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3746 spec = codec->spec;
3747 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3748 nvhdmi_chmap_cea_alloc_validate_get_type;
3749 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3750
3751 return 0;
3752}
3753
3754/*
3755 * ATI/AMD-specific implementations
3756 */
3757
3758#define is_amdhdmi_rev3_or_later(codec) \
3759 ((codec)->core.vendor_id == 0x1002aa01 && \
3760 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3761#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3762
3763/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3764#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3765#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3766#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3767#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3768#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3769#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3770#define ATI_VERB_SET_HBR_CONTROL 0x77c
3771#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3772#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3773#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3774#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3775#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3776#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3777#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3778#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3779#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3780#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3781#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3782#define ATI_VERB_GET_HBR_CONTROL 0xf7c
3783#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3784#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3785#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3786#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3787#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3788
3789/* AMD specific HDA cvt verbs */
3790#define ATI_VERB_SET_RAMP_RATE 0x770
3791#define ATI_VERB_GET_RAMP_RATE 0xf70
3792
3793#define ATI_OUT_ENABLE 0x1
3794
3795#define ATI_MULTICHANNEL_MODE_PAIRED 0
3796#define ATI_MULTICHANNEL_MODE_SINGLE 1
3797
3798#define ATI_HBR_CAPABLE 0x01
3799#define ATI_HBR_ENABLE 0x10
3800
3801static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3802 int dev_id, unsigned char *buf, int *eld_size)
3803{
3804 WARN_ON(dev_id != 0);
3805 /* call hda_eld.c ATI/AMD-specific function */
3806 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3807 is_amdhdmi_rev3_or_later(codec));
3808}
3809
3810static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3811 hda_nid_t pin_nid, int dev_id, int ca,
3812 int active_channels, int conn_type)
3813{
3814 WARN_ON(dev_id != 0);
3815 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3816}
3817
3818static int atihdmi_paired_swap_fc_lfe(int pos)
3819{
3820 /*
3821 * ATI/AMD have automatic FC/LFE swap built-in
3822 * when in pairwise mapping mode.
3823 */
3824
3825 switch (pos) {
3826 /* see channel_allocations[].speakers[] */
3827 case 2: return 3;
3828 case 3: return 2;
3829 default: break;
3830 }
3831
3832 return pos;
3833}
3834
3835static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3836 int ca, int chs, unsigned char *map)
3837{
3838 struct hdac_cea_channel_speaker_allocation *cap;
3839 int i, j;
3840
3841 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3842
3843 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3844 for (i = 0; i < chs; ++i) {
3845 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3846 bool ok = false;
3847 bool companion_ok = false;
3848
3849 if (!mask)
3850 continue;
3851
3852 for (j = 0 + i % 2; j < 8; j += 2) {
3853 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3854 if (cap->speakers[chan_idx] == mask) {
3855 /* channel is in a supported position */
3856 ok = true;
3857
3858 if (i % 2 == 0 && i + 1 < chs) {
3859 /* even channel, check the odd companion */
3860 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3861 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3862 int comp_mask_act = cap->speakers[comp_chan_idx];
3863
3864 if (comp_mask_req == comp_mask_act)
3865 companion_ok = true;
3866 else
3867 return -EINVAL;
3868 }
3869 break;
3870 }
3871 }
3872
3873 if (!ok)
3874 return -EINVAL;
3875
3876 if (companion_ok)
3877 i++; /* companion channel already checked */
3878 }
3879
3880 return 0;
3881}
3882
3883static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3884 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3885{
3886 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3887 int verb;
3888 int ati_channel_setup = 0;
3889
3890 if (hdmi_slot > 7)
3891 return -EINVAL;
3892
3893 if (!has_amd_full_remap_support(codec)) {
3894 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3895
3896 /* In case this is an odd slot but without stream channel, do not
3897 * disable the slot since the corresponding even slot could have a
3898 * channel. In case neither have a channel, the slot pair will be
3899 * disabled when this function is called for the even slot. */
3900 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3901 return 0;
3902
3903 hdmi_slot -= hdmi_slot % 2;
3904
3905 if (stream_channel != 0xf)
3906 stream_channel -= stream_channel % 2;
3907 }
3908
3909 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3910
3911 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3912
3913 if (stream_channel != 0xf)
3914 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3915
3916 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3917}
3918
3919static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3920 hda_nid_t pin_nid, int asp_slot)
3921{
3922 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3923 bool was_odd = false;
3924 int ati_asp_slot = asp_slot;
3925 int verb;
3926 int ati_channel_setup;
3927
3928 if (asp_slot > 7)
3929 return -EINVAL;
3930
3931 if (!has_amd_full_remap_support(codec)) {
3932 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3933 if (ati_asp_slot % 2 != 0) {
3934 ati_asp_slot -= 1;
3935 was_odd = true;
3936 }
3937 }
3938
3939 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3940
3941 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3942
3943 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3944 return 0xf;
3945
3946 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3947}
3948
3949static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3950 struct hdac_chmap *chmap,
3951 struct hdac_cea_channel_speaker_allocation *cap,
3952 int channels)
3953{
3954 int c;
3955
3956 /*
3957 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3958 * we need to take that into account (a single channel may take 2
3959 * channel slots if we need to carry a silent channel next to it).
3960 * On Rev3+ AMD codecs this function is not used.
3961 */
3962 int chanpairs = 0;
3963
3964 /* We only produce even-numbered channel count TLVs */
3965 if ((channels % 2) != 0)
3966 return -1;
3967
3968 for (c = 0; c < 7; c += 2) {
3969 if (cap->speakers[c] || cap->speakers[c+1])
3970 chanpairs++;
3971 }
3972
3973 if (chanpairs * 2 != channels)
3974 return -1;
3975
3976 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3977}
3978
3979static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3980 struct hdac_cea_channel_speaker_allocation *cap,
3981 unsigned int *chmap, int channels)
3982{
3983 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3984 int count = 0;
3985 int c;
3986
3987 for (c = 7; c >= 0; c--) {
3988 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3989 int spk = cap->speakers[chan];
3990 if (!spk) {
3991 /* add N/A channel if the companion channel is occupied */
3992 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3993 chmap[count++] = SNDRV_CHMAP_NA;
3994
3995 continue;
3996 }
3997
3998 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3999 }
4000
4001 WARN_ON(count != channels);
4002}
4003
4004static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4005 int dev_id, bool hbr)
4006{
4007 int hbr_ctl, hbr_ctl_new;
4008
4009 WARN_ON(dev_id != 0);
4010
4011 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4012 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4013 if (hbr)
4014 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4015 else
4016 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4017
4018 codec_dbg(codec,
4019 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4020 pin_nid,
4021 hbr_ctl == hbr_ctl_new ? "" : "new-",
4022 hbr_ctl_new);
4023
4024 if (hbr_ctl != hbr_ctl_new)
4025 snd_hda_codec_write(codec, pin_nid, 0,
4026 ATI_VERB_SET_HBR_CONTROL,
4027 hbr_ctl_new);
4028
4029 } else if (hbr)
4030 return -EINVAL;
4031
4032 return 0;
4033}
4034
4035static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4036 hda_nid_t pin_nid, int dev_id,
4037 u32 stream_tag, int format)
4038{
4039 if (is_amdhdmi_rev3_or_later(codec)) {
4040 int ramp_rate = 180; /* default as per AMD spec */
4041 /* disable ramp-up/down for non-pcm as per AMD spec */
4042 if (format & AC_FMT_TYPE_NON_PCM)
4043 ramp_rate = 0;
4044
4045 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4046 }
4047
4048 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4049 stream_tag, format);
4050}
4051
4052
4053static int atihdmi_init(struct hda_codec *codec)
4054{
4055 struct hdmi_spec *spec = codec->spec;
4056 int pin_idx, err;
4057
4058 err = generic_hdmi_init(codec);
4059
4060 if (err)
4061 return err;
4062
4063 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4064 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4065
4066 /* make sure downmix information in infoframe is zero */
4067 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4068
4069 /* enable channel-wise remap mode if supported */
4070 if (has_amd_full_remap_support(codec))
4071 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4072 ATI_VERB_SET_MULTICHANNEL_MODE,
4073 ATI_MULTICHANNEL_MODE_SINGLE);
4074 }
4075 codec->auto_runtime_pm = 1;
4076
4077 return 0;
4078}
4079
4080/* map from pin NID to port; port is 0-based */
4081/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4082static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4083{
4084 return pin_nid / 2 - 1;
4085}
4086
4087/* reverse-map from port to pin NID: see above */
4088static int atihdmi_port2pin(struct hda_codec *codec, int port)
4089{
4090 return port * 2 + 3;
4091}
4092
4093static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4094 .pin2port = atihdmi_pin2port,
4095 .pin_eld_notify = generic_acomp_pin_eld_notify,
4096 .master_bind = generic_acomp_master_bind,
4097 .master_unbind = generic_acomp_master_unbind,
4098};
4099
4100static int patch_atihdmi(struct hda_codec *codec)
4101{
4102 struct hdmi_spec *spec;
4103 struct hdmi_spec_per_cvt *per_cvt;
4104 int err, cvt_idx;
4105
4106 err = patch_generic_hdmi(codec);
4107
4108 if (err)
4109 return err;
4110
4111 codec->patch_ops.init = atihdmi_init;
4112
4113 spec = codec->spec;
4114
4115 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4116 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4117 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4118 spec->ops.setup_stream = atihdmi_setup_stream;
4119
4120 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4121 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4122
4123 if (!has_amd_full_remap_support(codec)) {
4124 /* override to ATI/AMD-specific versions with pairwise mapping */
4125 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4126 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4127 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4128 atihdmi_paired_cea_alloc_to_tlv_chmap;
4129 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4130 }
4131
4132 /* ATI/AMD converters do not advertise all of their capabilities */
4133 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4134 per_cvt = get_cvt(spec, cvt_idx);
4135 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4136 per_cvt->rates |= SUPPORTED_RATES;
4137 per_cvt->formats |= SUPPORTED_FORMATS;
4138 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4139 }
4140
4141 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4142
4143 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4144 * the link-down as is. Tell the core to allow it.
4145 */
4146 codec->link_down_at_suspend = 1;
4147
4148 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4149
4150 return 0;
4151}
4152
4153/* VIA HDMI Implementation */
4154#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4155#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4156
4157static int patch_via_hdmi(struct hda_codec *codec)
4158{
4159 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4160}
4161
4162/*
4163 * patch entries
4164 */
4165static const struct hda_device_id snd_hda_id_hdmi[] = {
4166HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4167HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4168HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4169HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4170HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4171HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4172HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4173HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4174HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4175HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4176HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4177HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4178HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4179HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4180HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4181HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4182HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4183HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4184HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4185HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4186HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4187HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4188HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4189HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4190HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4191HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4192HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4193/* 17 is known to be absent */
4194HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4195HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4196HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4197HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4198HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4199HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4200HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4201HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4202HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4203HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4204HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4205HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4206HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4207HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4208HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4209HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4210HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4211HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4212HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4213HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4214HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4215HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4216HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4217HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4218HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4219HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4220HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4221HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4222HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4223HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4224HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4225HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4226HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4227HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4228HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4229HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4230HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4231HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4232HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4233HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4234HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4235HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4236HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4237HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4238HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4239HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4240HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4241HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4242HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4243HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4244HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4245HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4246HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4247HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4248HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4249HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4250HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4251HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4252HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4253HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4254HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4255HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4256HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4257HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4258HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4259HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4260HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4261HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4262HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4263HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4264HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4265HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4266HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4267HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4268HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4269HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4270HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4271HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4272HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4273HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4274HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4275HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4276HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4277HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4278HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4279/* special ID for generic HDMI */
4280HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4281{} /* terminator */
4282};
4283MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4284
4285MODULE_LICENSE("GPL");
4286MODULE_DESCRIPTION("HDMI HD-audio codec");
4287MODULE_ALIAS("snd-hda-codec-intelhdmi");
4288MODULE_ALIAS("snd-hda-codec-nvhdmi");
4289MODULE_ALIAS("snd-hda-codec-atihdmi");
4290
4291static struct hda_codec_driver hdmi_driver = {
4292 .id = snd_hda_id_hdmi,
4293};
4294
4295module_hda_codec_driver(hdmi_driver);
1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
35#include <linux/module.h>
36#include <sound/core.h>
37#include <sound/jack.h>
38#include <sound/asoundef.h>
39#include <sound/tlv.h>
40#include <sound/hdaudio.h>
41#include <sound/hda_i915.h>
42#include <sound/hda_chmap.h>
43#include "hda_codec.h"
44#include "hda_local.h"
45#include "hda_jack.h"
46
47static bool static_hdmi_pcm;
48module_param(static_hdmi_pcm, bool, 0644);
49MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50
51#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56#define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
57 ((codec)->core.vendor_id == 0x80862800))
58#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
59#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
60 || is_skylake(codec) || is_broxton(codec) \
61 || is_kabylake(codec)) || is_geminilake(codec) \
62 || is_cannonlake(codec)
63#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
64#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
65#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
66
67struct hdmi_spec_per_cvt {
68 hda_nid_t cvt_nid;
69 int assigned;
70 unsigned int channels_min;
71 unsigned int channels_max;
72 u32 rates;
73 u64 formats;
74 unsigned int maxbps;
75};
76
77/* max. connections to a widget */
78#define HDA_MAX_CONNECTIONS 32
79
80struct hdmi_spec_per_pin {
81 hda_nid_t pin_nid;
82 int dev_id;
83 /* pin idx, different device entries on the same pin use the same idx */
84 int pin_nid_idx;
85 int num_mux_nids;
86 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
87 int mux_idx;
88 hda_nid_t cvt_nid;
89
90 struct hda_codec *codec;
91 struct hdmi_eld sink_eld;
92 struct mutex lock;
93 struct delayed_work work;
94 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
95 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
96 int repoll_count;
97 bool setup; /* the stream has been set up by prepare callback */
98 int channels; /* current number of channels */
99 bool non_pcm;
100 bool chmap_set; /* channel-map override by ALSA API? */
101 unsigned char chmap[8]; /* ALSA API channel-map */
102#ifdef CONFIG_SND_PROC_FS
103 struct snd_info_entry *proc_entry;
104#endif
105};
106
107/* operations used by generic code that can be overridden by patches */
108struct hdmi_ops {
109 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
110 unsigned char *buf, int *eld_size);
111
112 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
113 int ca, int active_channels, int conn_type);
114
115 /* enable/disable HBR (HD passthrough) */
116 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
117
118 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
119 hda_nid_t pin_nid, u32 stream_tag, int format);
120
121 void (*pin_cvt_fixup)(struct hda_codec *codec,
122 struct hdmi_spec_per_pin *per_pin,
123 hda_nid_t cvt_nid);
124};
125
126struct hdmi_pcm {
127 struct hda_pcm *pcm;
128 struct snd_jack *jack;
129 struct snd_kcontrol *eld_ctl;
130};
131
132struct hdmi_spec {
133 int num_cvts;
134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
135 hda_nid_t cvt_nids[4]; /* only for haswell fix */
136
137 /*
138 * num_pins is the number of virtual pins
139 * for example, there are 3 pins, and each pin
140 * has 4 device entries, then the num_pins is 12
141 */
142 int num_pins;
143 /*
144 * num_nids is the number of real pins
145 * In the above example, num_nids is 3
146 */
147 int num_nids;
148 /*
149 * dev_num is the number of device entries
150 * on each pin.
151 * In the above example, dev_num is 4
152 */
153 int dev_num;
154 struct snd_array pins; /* struct hdmi_spec_per_pin */
155 struct hdmi_pcm pcm_rec[16];
156 struct mutex pcm_lock;
157 /* pcm_bitmap means which pcms have been assigned to pins*/
158 unsigned long pcm_bitmap;
159 int pcm_used; /* counter of pcm_rec[] */
160 /* bitmap shows whether the pcm is opened in user space
161 * bit 0 means the first playback PCM (PCM3);
162 * bit 1 means the second playback PCM, and so on.
163 */
164 unsigned long pcm_in_use;
165
166 struct hdmi_eld temp_eld;
167 struct hdmi_ops ops;
168
169 bool dyn_pin_out;
170 bool dyn_pcm_assign;
171 /*
172 * Non-generic VIA/NVIDIA specific
173 */
174 struct hda_multi_out multiout;
175 struct hda_pcm_stream pcm_playback;
176
177 /* i915/powerwell (Haswell+/Valleyview+) specific */
178 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
179 struct i915_audio_component_audio_ops i915_audio_ops;
180
181 struct hdac_chmap chmap;
182 hda_nid_t vendor_nid;
183};
184
185#ifdef CONFIG_SND_HDA_I915
186static inline bool codec_has_acomp(struct hda_codec *codec)
187{
188 struct hdmi_spec *spec = codec->spec;
189 return spec->use_acomp_notifier;
190}
191#else
192#define codec_has_acomp(codec) false
193#endif
194
195struct hdmi_audio_infoframe {
196 u8 type; /* 0x84 */
197 u8 ver; /* 0x01 */
198 u8 len; /* 0x0a */
199
200 u8 checksum;
201
202 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
203 u8 SS01_SF24;
204 u8 CXT04;
205 u8 CA;
206 u8 LFEPBL01_LSV36_DM_INH7;
207};
208
209struct dp_audio_infoframe {
210 u8 type; /* 0x84 */
211 u8 len; /* 0x1b */
212 u8 ver; /* 0x11 << 2 */
213
214 u8 CC02_CT47; /* match with HDMI infoframe from this on */
215 u8 SS01_SF24;
216 u8 CXT04;
217 u8 CA;
218 u8 LFEPBL01_LSV36_DM_INH7;
219};
220
221union audio_infoframe {
222 struct hdmi_audio_infoframe hdmi;
223 struct dp_audio_infoframe dp;
224 u8 bytes[0];
225};
226
227/*
228 * HDMI routines
229 */
230
231#define get_pin(spec, idx) \
232 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
233#define get_cvt(spec, idx) \
234 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
235/* obtain hdmi_pcm object assigned to idx */
236#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
237/* obtain hda_pcm object assigned to idx */
238#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
239
240static int pin_id_to_pin_index(struct hda_codec *codec,
241 hda_nid_t pin_nid, int dev_id)
242{
243 struct hdmi_spec *spec = codec->spec;
244 int pin_idx;
245 struct hdmi_spec_per_pin *per_pin;
246
247 /*
248 * (dev_id == -1) means it is NON-MST pin
249 * return the first virtual pin on this port
250 */
251 if (dev_id == -1)
252 dev_id = 0;
253
254 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
255 per_pin = get_pin(spec, pin_idx);
256 if ((per_pin->pin_nid == pin_nid) &&
257 (per_pin->dev_id == dev_id))
258 return pin_idx;
259 }
260
261 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
262 return -EINVAL;
263}
264
265static int hinfo_to_pcm_index(struct hda_codec *codec,
266 struct hda_pcm_stream *hinfo)
267{
268 struct hdmi_spec *spec = codec->spec;
269 int pcm_idx;
270
271 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
272 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
273 return pcm_idx;
274
275 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
276 return -EINVAL;
277}
278
279static int hinfo_to_pin_index(struct hda_codec *codec,
280 struct hda_pcm_stream *hinfo)
281{
282 struct hdmi_spec *spec = codec->spec;
283 struct hdmi_spec_per_pin *per_pin;
284 int pin_idx;
285
286 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
287 per_pin = get_pin(spec, pin_idx);
288 if (per_pin->pcm &&
289 per_pin->pcm->pcm->stream == hinfo)
290 return pin_idx;
291 }
292
293 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
294 return -EINVAL;
295}
296
297static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
298 int pcm_idx)
299{
300 int i;
301 struct hdmi_spec_per_pin *per_pin;
302
303 for (i = 0; i < spec->num_pins; i++) {
304 per_pin = get_pin(spec, i);
305 if (per_pin->pcm_idx == pcm_idx)
306 return per_pin;
307 }
308 return NULL;
309}
310
311static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
312{
313 struct hdmi_spec *spec = codec->spec;
314 int cvt_idx;
315
316 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
317 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
318 return cvt_idx;
319
320 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
321 return -EINVAL;
322}
323
324static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
325 struct snd_ctl_elem_info *uinfo)
326{
327 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
328 struct hdmi_spec *spec = codec->spec;
329 struct hdmi_spec_per_pin *per_pin;
330 struct hdmi_eld *eld;
331 int pcm_idx;
332
333 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
334
335 pcm_idx = kcontrol->private_value;
336 mutex_lock(&spec->pcm_lock);
337 per_pin = pcm_idx_to_pin(spec, pcm_idx);
338 if (!per_pin) {
339 /* no pin is bound to the pcm */
340 uinfo->count = 0;
341 mutex_unlock(&spec->pcm_lock);
342 return 0;
343 }
344 eld = &per_pin->sink_eld;
345 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
346 mutex_unlock(&spec->pcm_lock);
347
348 return 0;
349}
350
351static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
352 struct snd_ctl_elem_value *ucontrol)
353{
354 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
355 struct hdmi_spec *spec = codec->spec;
356 struct hdmi_spec_per_pin *per_pin;
357 struct hdmi_eld *eld;
358 int pcm_idx;
359
360 pcm_idx = kcontrol->private_value;
361 mutex_lock(&spec->pcm_lock);
362 per_pin = pcm_idx_to_pin(spec, pcm_idx);
363 if (!per_pin) {
364 /* no pin is bound to the pcm */
365 memset(ucontrol->value.bytes.data, 0,
366 ARRAY_SIZE(ucontrol->value.bytes.data));
367 mutex_unlock(&spec->pcm_lock);
368 return 0;
369 }
370 eld = &per_pin->sink_eld;
371
372 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
373 eld->eld_size > ELD_MAX_SIZE) {
374 mutex_unlock(&spec->pcm_lock);
375 snd_BUG();
376 return -EINVAL;
377 }
378
379 memset(ucontrol->value.bytes.data, 0,
380 ARRAY_SIZE(ucontrol->value.bytes.data));
381 if (eld->eld_valid)
382 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
383 eld->eld_size);
384 mutex_unlock(&spec->pcm_lock);
385
386 return 0;
387}
388
389static const struct snd_kcontrol_new eld_bytes_ctl = {
390 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
391 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
392 .name = "ELD",
393 .info = hdmi_eld_ctl_info,
394 .get = hdmi_eld_ctl_get,
395};
396
397static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
398 int device)
399{
400 struct snd_kcontrol *kctl;
401 struct hdmi_spec *spec = codec->spec;
402 int err;
403
404 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
405 if (!kctl)
406 return -ENOMEM;
407 kctl->private_value = pcm_idx;
408 kctl->id.device = device;
409
410 /* no pin nid is associated with the kctl now
411 * tbd: associate pin nid to eld ctl later
412 */
413 err = snd_hda_ctl_add(codec, 0, kctl);
414 if (err < 0)
415 return err;
416
417 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
418 return 0;
419}
420
421#ifdef BE_PARANOID
422static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
423 int *packet_index, int *byte_index)
424{
425 int val;
426
427 val = snd_hda_codec_read(codec, pin_nid, 0,
428 AC_VERB_GET_HDMI_DIP_INDEX, 0);
429
430 *packet_index = val >> 5;
431 *byte_index = val & 0x1f;
432}
433#endif
434
435static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
436 int packet_index, int byte_index)
437{
438 int val;
439
440 val = (packet_index << 5) | (byte_index & 0x1f);
441
442 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
443}
444
445static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
446 unsigned char val)
447{
448 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
449}
450
451static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
452{
453 struct hdmi_spec *spec = codec->spec;
454 int pin_out;
455
456 /* Unmute */
457 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
458 snd_hda_codec_write(codec, pin_nid, 0,
459 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
460
461 if (spec->dyn_pin_out)
462 /* Disable pin out until stream is active */
463 pin_out = 0;
464 else
465 /* Enable pin out: some machines with GM965 gets broken output
466 * when the pin is disabled or changed while using with HDMI
467 */
468 pin_out = PIN_OUT;
469
470 snd_hda_codec_write(codec, pin_nid, 0,
471 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
472}
473
474/*
475 * ELD proc files
476 */
477
478#ifdef CONFIG_SND_PROC_FS
479static void print_eld_info(struct snd_info_entry *entry,
480 struct snd_info_buffer *buffer)
481{
482 struct hdmi_spec_per_pin *per_pin = entry->private_data;
483
484 mutex_lock(&per_pin->lock);
485 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
486 mutex_unlock(&per_pin->lock);
487}
488
489static void write_eld_info(struct snd_info_entry *entry,
490 struct snd_info_buffer *buffer)
491{
492 struct hdmi_spec_per_pin *per_pin = entry->private_data;
493
494 mutex_lock(&per_pin->lock);
495 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
496 mutex_unlock(&per_pin->lock);
497}
498
499static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
500{
501 char name[32];
502 struct hda_codec *codec = per_pin->codec;
503 struct snd_info_entry *entry;
504 int err;
505
506 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
507 err = snd_card_proc_new(codec->card, name, &entry);
508 if (err < 0)
509 return err;
510
511 snd_info_set_text_ops(entry, per_pin, print_eld_info);
512 entry->c.text.write = write_eld_info;
513 entry->mode |= S_IWUSR;
514 per_pin->proc_entry = entry;
515
516 return 0;
517}
518
519static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
520{
521 if (!per_pin->codec->bus->shutdown) {
522 snd_info_free_entry(per_pin->proc_entry);
523 per_pin->proc_entry = NULL;
524 }
525}
526#else
527static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
528 int index)
529{
530 return 0;
531}
532static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
533{
534}
535#endif
536
537/*
538 * Audio InfoFrame routines
539 */
540
541/*
542 * Enable Audio InfoFrame Transmission
543 */
544static void hdmi_start_infoframe_trans(struct hda_codec *codec,
545 hda_nid_t pin_nid)
546{
547 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
548 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
549 AC_DIPXMIT_BEST);
550}
551
552/*
553 * Disable Audio InfoFrame Transmission
554 */
555static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
556 hda_nid_t pin_nid)
557{
558 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
559 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
560 AC_DIPXMIT_DISABLE);
561}
562
563static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
564{
565#ifdef CONFIG_SND_DEBUG_VERBOSE
566 int i;
567 int size;
568
569 size = snd_hdmi_get_eld_size(codec, pin_nid);
570 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
571
572 for (i = 0; i < 8; i++) {
573 size = snd_hda_codec_read(codec, pin_nid, 0,
574 AC_VERB_GET_HDMI_DIP_SIZE, i);
575 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
576 }
577#endif
578}
579
580static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
581{
582#ifdef BE_PARANOID
583 int i, j;
584 int size;
585 int pi, bi;
586 for (i = 0; i < 8; i++) {
587 size = snd_hda_codec_read(codec, pin_nid, 0,
588 AC_VERB_GET_HDMI_DIP_SIZE, i);
589 if (size == 0)
590 continue;
591
592 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
593 for (j = 1; j < 1000; j++) {
594 hdmi_write_dip_byte(codec, pin_nid, 0x0);
595 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
596 if (pi != i)
597 codec_dbg(codec, "dip index %d: %d != %d\n",
598 bi, pi, i);
599 if (bi == 0) /* byte index wrapped around */
600 break;
601 }
602 codec_dbg(codec,
603 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
604 i, size, j);
605 }
606#endif
607}
608
609static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
610{
611 u8 *bytes = (u8 *)hdmi_ai;
612 u8 sum = 0;
613 int i;
614
615 hdmi_ai->checksum = 0;
616
617 for (i = 0; i < sizeof(*hdmi_ai); i++)
618 sum += bytes[i];
619
620 hdmi_ai->checksum = -sum;
621}
622
623static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
624 hda_nid_t pin_nid,
625 u8 *dip, int size)
626{
627 int i;
628
629 hdmi_debug_dip_size(codec, pin_nid);
630 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
631
632 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
633 for (i = 0; i < size; i++)
634 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
635}
636
637static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
638 u8 *dip, int size)
639{
640 u8 val;
641 int i;
642
643 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
644 != AC_DIPXMIT_BEST)
645 return false;
646
647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
648 for (i = 0; i < size; i++) {
649 val = snd_hda_codec_read(codec, pin_nid, 0,
650 AC_VERB_GET_HDMI_DIP_DATA, 0);
651 if (val != dip[i])
652 return false;
653 }
654
655 return true;
656}
657
658static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
659 hda_nid_t pin_nid,
660 int ca, int active_channels,
661 int conn_type)
662{
663 union audio_infoframe ai;
664
665 memset(&ai, 0, sizeof(ai));
666 if (conn_type == 0) { /* HDMI */
667 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
668
669 hdmi_ai->type = 0x84;
670 hdmi_ai->ver = 0x01;
671 hdmi_ai->len = 0x0a;
672 hdmi_ai->CC02_CT47 = active_channels - 1;
673 hdmi_ai->CA = ca;
674 hdmi_checksum_audio_infoframe(hdmi_ai);
675 } else if (conn_type == 1) { /* DisplayPort */
676 struct dp_audio_infoframe *dp_ai = &ai.dp;
677
678 dp_ai->type = 0x84;
679 dp_ai->len = 0x1b;
680 dp_ai->ver = 0x11 << 2;
681 dp_ai->CC02_CT47 = active_channels - 1;
682 dp_ai->CA = ca;
683 } else {
684 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
685 pin_nid);
686 return;
687 }
688
689 /*
690 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
691 * sizeof(*dp_ai) to avoid partial match/update problems when
692 * the user switches between HDMI/DP monitors.
693 */
694 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
695 sizeof(ai))) {
696 codec_dbg(codec,
697 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
698 pin_nid,
699 active_channels, ca);
700 hdmi_stop_infoframe_trans(codec, pin_nid);
701 hdmi_fill_audio_infoframe(codec, pin_nid,
702 ai.bytes, sizeof(ai));
703 hdmi_start_infoframe_trans(codec, pin_nid);
704 }
705}
706
707static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
708 struct hdmi_spec_per_pin *per_pin,
709 bool non_pcm)
710{
711 struct hdmi_spec *spec = codec->spec;
712 struct hdac_chmap *chmap = &spec->chmap;
713 hda_nid_t pin_nid = per_pin->pin_nid;
714 int channels = per_pin->channels;
715 int active_channels;
716 struct hdmi_eld *eld;
717 int ca;
718
719 if (!channels)
720 return;
721
722 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
723 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
724 snd_hda_codec_write(codec, pin_nid, 0,
725 AC_VERB_SET_AMP_GAIN_MUTE,
726 AMP_OUT_UNMUTE);
727
728 eld = &per_pin->sink_eld;
729
730 ca = snd_hdac_channel_allocation(&codec->core,
731 eld->info.spk_alloc, channels,
732 per_pin->chmap_set, non_pcm, per_pin->chmap);
733
734 active_channels = snd_hdac_get_active_channels(ca);
735
736 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
737 active_channels);
738
739 /*
740 * always configure channel mapping, it may have been changed by the
741 * user in the meantime
742 */
743 snd_hdac_setup_channel_mapping(&spec->chmap,
744 pin_nid, non_pcm, ca, channels,
745 per_pin->chmap, per_pin->chmap_set);
746
747 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
748 eld->info.conn_type);
749
750 per_pin->non_pcm = non_pcm;
751}
752
753/*
754 * Unsolicited events
755 */
756
757static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
758
759static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
760 int dev_id)
761{
762 struct hdmi_spec *spec = codec->spec;
763 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
764
765 if (pin_idx < 0)
766 return;
767 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
768 snd_hda_jack_report_sync(codec);
769}
770
771static void jack_callback(struct hda_codec *codec,
772 struct hda_jack_callback *jack)
773{
774 /* hda_jack don't support DP MST */
775 check_presence_and_report(codec, jack->nid, 0);
776}
777
778static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
779{
780 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
781 struct hda_jack_tbl *jack;
782 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
783
784 /*
785 * assume DP MST uses dyn_pcm_assign and acomp and
786 * never comes here
787 * if DP MST supports unsol event, below code need
788 * consider dev_entry
789 */
790 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
791 if (!jack)
792 return;
793 jack->jack_dirty = 1;
794
795 codec_dbg(codec,
796 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
797 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
798 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
799
800 /* hda_jack don't support DP MST */
801 check_presence_and_report(codec, jack->nid, 0);
802}
803
804static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
805{
806 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
807 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
808 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
809 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
810
811 codec_info(codec,
812 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
813 codec->addr,
814 tag,
815 subtag,
816 cp_state,
817 cp_ready);
818
819 /* TODO */
820 if (cp_state)
821 ;
822 if (cp_ready)
823 ;
824}
825
826
827static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
828{
829 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
830 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
831
832 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
833 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
834 return;
835 }
836
837 if (subtag == 0)
838 hdmi_intrinsic_event(codec, res);
839 else
840 hdmi_non_intrinsic_event(codec, res);
841}
842
843static void haswell_verify_D0(struct hda_codec *codec,
844 hda_nid_t cvt_nid, hda_nid_t nid)
845{
846 int pwr;
847
848 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
849 * thus pins could only choose converter 0 for use. Make sure the
850 * converters are in correct power state */
851 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
852 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
853
854 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
855 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
856 AC_PWRST_D0);
857 msleep(40);
858 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
859 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
860 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
861 }
862}
863
864/*
865 * Callbacks
866 */
867
868/* HBR should be Non-PCM, 8 channels */
869#define is_hbr_format(format) \
870 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
871
872static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
873 bool hbr)
874{
875 int pinctl, new_pinctl;
876
877 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
878 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
879 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
880
881 if (pinctl < 0)
882 return hbr ? -EINVAL : 0;
883
884 new_pinctl = pinctl & ~AC_PINCTL_EPT;
885 if (hbr)
886 new_pinctl |= AC_PINCTL_EPT_HBR;
887 else
888 new_pinctl |= AC_PINCTL_EPT_NATIVE;
889
890 codec_dbg(codec,
891 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
892 pin_nid,
893 pinctl == new_pinctl ? "" : "new-",
894 new_pinctl);
895
896 if (pinctl != new_pinctl)
897 snd_hda_codec_write(codec, pin_nid, 0,
898 AC_VERB_SET_PIN_WIDGET_CONTROL,
899 new_pinctl);
900 } else if (hbr)
901 return -EINVAL;
902
903 return 0;
904}
905
906static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
907 hda_nid_t pin_nid, u32 stream_tag, int format)
908{
909 struct hdmi_spec *spec = codec->spec;
910 unsigned int param;
911 int err;
912
913 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
914
915 if (err) {
916 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
917 return err;
918 }
919
920 if (is_haswell_plus(codec)) {
921
922 /*
923 * on recent platforms IEC Coding Type is required for HBR
924 * support, read current Digital Converter settings and set
925 * ICT bitfield if needed.
926 */
927 param = snd_hda_codec_read(codec, cvt_nid, 0,
928 AC_VERB_GET_DIGI_CONVERT_1, 0);
929
930 param = (param >> 16) & ~(AC_DIG3_ICT);
931
932 /* on recent platforms ICT mode is required for HBR support */
933 if (is_hbr_format(format))
934 param |= 0x1;
935
936 snd_hda_codec_write(codec, cvt_nid, 0,
937 AC_VERB_SET_DIGI_CONVERT_3, param);
938 }
939
940 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
941 return 0;
942}
943
944/* Try to find an available converter
945 * If pin_idx is less then zero, just try to find an available converter.
946 * Otherwise, try to find an available converter and get the cvt mux index
947 * of the pin.
948 */
949static int hdmi_choose_cvt(struct hda_codec *codec,
950 int pin_idx, int *cvt_id)
951{
952 struct hdmi_spec *spec = codec->spec;
953 struct hdmi_spec_per_pin *per_pin;
954 struct hdmi_spec_per_cvt *per_cvt = NULL;
955 int cvt_idx, mux_idx = 0;
956
957 /* pin_idx < 0 means no pin will be bound to the converter */
958 if (pin_idx < 0)
959 per_pin = NULL;
960 else
961 per_pin = get_pin(spec, pin_idx);
962
963 /* Dynamically assign converter to stream */
964 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
965 per_cvt = get_cvt(spec, cvt_idx);
966
967 /* Must not already be assigned */
968 if (per_cvt->assigned)
969 continue;
970 if (per_pin == NULL)
971 break;
972 /* Must be in pin's mux's list of converters */
973 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
974 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
975 break;
976 /* Not in mux list */
977 if (mux_idx == per_pin->num_mux_nids)
978 continue;
979 break;
980 }
981
982 /* No free converters */
983 if (cvt_idx == spec->num_cvts)
984 return -EBUSY;
985
986 if (per_pin != NULL)
987 per_pin->mux_idx = mux_idx;
988
989 if (cvt_id)
990 *cvt_id = cvt_idx;
991
992 return 0;
993}
994
995/* Assure the pin select the right convetor */
996static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
997 struct hdmi_spec_per_pin *per_pin)
998{
999 hda_nid_t pin_nid = per_pin->pin_nid;
1000 int mux_idx, curr;
1001
1002 mux_idx = per_pin->mux_idx;
1003 curr = snd_hda_codec_read(codec, pin_nid, 0,
1004 AC_VERB_GET_CONNECT_SEL, 0);
1005 if (curr != mux_idx)
1006 snd_hda_codec_write_cache(codec, pin_nid, 0,
1007 AC_VERB_SET_CONNECT_SEL,
1008 mux_idx);
1009}
1010
1011/* get the mux index for the converter of the pins
1012 * converter's mux index is the same for all pins on Intel platform
1013 */
1014static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1015 hda_nid_t cvt_nid)
1016{
1017 int i;
1018
1019 for (i = 0; i < spec->num_cvts; i++)
1020 if (spec->cvt_nids[i] == cvt_nid)
1021 return i;
1022 return -EINVAL;
1023}
1024
1025/* Intel HDMI workaround to fix audio routing issue:
1026 * For some Intel display codecs, pins share the same connection list.
1027 * So a conveter can be selected by multiple pins and playback on any of these
1028 * pins will generate sound on the external display, because audio flows from
1029 * the same converter to the display pipeline. Also muting one pin may make
1030 * other pins have no sound output.
1031 * So this function assures that an assigned converter for a pin is not selected
1032 * by any other pins.
1033 */
1034static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1035 hda_nid_t pin_nid,
1036 int dev_id, int mux_idx)
1037{
1038 struct hdmi_spec *spec = codec->spec;
1039 hda_nid_t nid;
1040 int cvt_idx, curr;
1041 struct hdmi_spec_per_cvt *per_cvt;
1042 struct hdmi_spec_per_pin *per_pin;
1043 int pin_idx;
1044
1045 /* configure the pins connections */
1046 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1047 int dev_id_saved;
1048 int dev_num;
1049
1050 per_pin = get_pin(spec, pin_idx);
1051 /*
1052 * pin not connected to monitor
1053 * no need to operate on it
1054 */
1055 if (!per_pin->pcm)
1056 continue;
1057
1058 if ((per_pin->pin_nid == pin_nid) &&
1059 (per_pin->dev_id == dev_id))
1060 continue;
1061
1062 /*
1063 * if per_pin->dev_id >= dev_num,
1064 * snd_hda_get_dev_select() will fail,
1065 * and the following operation is unpredictable.
1066 * So skip this situation.
1067 */
1068 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1069 if (per_pin->dev_id >= dev_num)
1070 continue;
1071
1072 nid = per_pin->pin_nid;
1073
1074 /*
1075 * Calling this function should not impact
1076 * on the device entry selection
1077 * So let's save the dev id for each pin,
1078 * and restore it when return
1079 */
1080 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1081 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1082 curr = snd_hda_codec_read(codec, nid, 0,
1083 AC_VERB_GET_CONNECT_SEL, 0);
1084 if (curr != mux_idx) {
1085 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1086 continue;
1087 }
1088
1089
1090 /* choose an unassigned converter. The conveters in the
1091 * connection list are in the same order as in the codec.
1092 */
1093 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1094 per_cvt = get_cvt(spec, cvt_idx);
1095 if (!per_cvt->assigned) {
1096 codec_dbg(codec,
1097 "choose cvt %d for pin nid %d\n",
1098 cvt_idx, nid);
1099 snd_hda_codec_write_cache(codec, nid, 0,
1100 AC_VERB_SET_CONNECT_SEL,
1101 cvt_idx);
1102 break;
1103 }
1104 }
1105 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1106 }
1107}
1108
1109/* A wrapper of intel_not_share_asigned_cvt() */
1110static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1111 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1112{
1113 int mux_idx;
1114 struct hdmi_spec *spec = codec->spec;
1115
1116 /* On Intel platform, the mapping of converter nid to
1117 * mux index of the pins are always the same.
1118 * The pin nid may be 0, this means all pins will not
1119 * share the converter.
1120 */
1121 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1122 if (mux_idx >= 0)
1123 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1124}
1125
1126/* skeleton caller of pin_cvt_fixup ops */
1127static void pin_cvt_fixup(struct hda_codec *codec,
1128 struct hdmi_spec_per_pin *per_pin,
1129 hda_nid_t cvt_nid)
1130{
1131 struct hdmi_spec *spec = codec->spec;
1132
1133 if (spec->ops.pin_cvt_fixup)
1134 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1135}
1136
1137/* called in hdmi_pcm_open when no pin is assigned to the PCM
1138 * in dyn_pcm_assign mode.
1139 */
1140static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1141 struct hda_codec *codec,
1142 struct snd_pcm_substream *substream)
1143{
1144 struct hdmi_spec *spec = codec->spec;
1145 struct snd_pcm_runtime *runtime = substream->runtime;
1146 int cvt_idx, pcm_idx;
1147 struct hdmi_spec_per_cvt *per_cvt = NULL;
1148 int err;
1149
1150 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1151 if (pcm_idx < 0)
1152 return -EINVAL;
1153
1154 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1155 if (err)
1156 return err;
1157
1158 per_cvt = get_cvt(spec, cvt_idx);
1159 per_cvt->assigned = 1;
1160 hinfo->nid = per_cvt->cvt_nid;
1161
1162 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1163
1164 set_bit(pcm_idx, &spec->pcm_in_use);
1165 /* todo: setup spdif ctls assign */
1166
1167 /* Initially set the converter's capabilities */
1168 hinfo->channels_min = per_cvt->channels_min;
1169 hinfo->channels_max = per_cvt->channels_max;
1170 hinfo->rates = per_cvt->rates;
1171 hinfo->formats = per_cvt->formats;
1172 hinfo->maxbps = per_cvt->maxbps;
1173
1174 /* Store the updated parameters */
1175 runtime->hw.channels_min = hinfo->channels_min;
1176 runtime->hw.channels_max = hinfo->channels_max;
1177 runtime->hw.formats = hinfo->formats;
1178 runtime->hw.rates = hinfo->rates;
1179
1180 snd_pcm_hw_constraint_step(substream->runtime, 0,
1181 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1182 return 0;
1183}
1184
1185/*
1186 * HDA PCM callbacks
1187 */
1188static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1189 struct hda_codec *codec,
1190 struct snd_pcm_substream *substream)
1191{
1192 struct hdmi_spec *spec = codec->spec;
1193 struct snd_pcm_runtime *runtime = substream->runtime;
1194 int pin_idx, cvt_idx, pcm_idx;
1195 struct hdmi_spec_per_pin *per_pin;
1196 struct hdmi_eld *eld;
1197 struct hdmi_spec_per_cvt *per_cvt = NULL;
1198 int err;
1199
1200 /* Validate hinfo */
1201 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1202 if (pcm_idx < 0)
1203 return -EINVAL;
1204
1205 mutex_lock(&spec->pcm_lock);
1206 pin_idx = hinfo_to_pin_index(codec, hinfo);
1207 if (!spec->dyn_pcm_assign) {
1208 if (snd_BUG_ON(pin_idx < 0)) {
1209 mutex_unlock(&spec->pcm_lock);
1210 return -EINVAL;
1211 }
1212 } else {
1213 /* no pin is assigned to the PCM
1214 * PA need pcm open successfully when probe
1215 */
1216 if (pin_idx < 0) {
1217 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1218 mutex_unlock(&spec->pcm_lock);
1219 return err;
1220 }
1221 }
1222
1223 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1224 if (err < 0) {
1225 mutex_unlock(&spec->pcm_lock);
1226 return err;
1227 }
1228
1229 per_cvt = get_cvt(spec, cvt_idx);
1230 /* Claim converter */
1231 per_cvt->assigned = 1;
1232
1233 set_bit(pcm_idx, &spec->pcm_in_use);
1234 per_pin = get_pin(spec, pin_idx);
1235 per_pin->cvt_nid = per_cvt->cvt_nid;
1236 hinfo->nid = per_cvt->cvt_nid;
1237
1238 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1239 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1240 AC_VERB_SET_CONNECT_SEL,
1241 per_pin->mux_idx);
1242
1243 /* configure unused pins to choose other converters */
1244 pin_cvt_fixup(codec, per_pin, 0);
1245
1246 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1247
1248 /* Initially set the converter's capabilities */
1249 hinfo->channels_min = per_cvt->channels_min;
1250 hinfo->channels_max = per_cvt->channels_max;
1251 hinfo->rates = per_cvt->rates;
1252 hinfo->formats = per_cvt->formats;
1253 hinfo->maxbps = per_cvt->maxbps;
1254
1255 eld = &per_pin->sink_eld;
1256 /* Restrict capabilities by ELD if this isn't disabled */
1257 if (!static_hdmi_pcm && eld->eld_valid) {
1258 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1259 if (hinfo->channels_min > hinfo->channels_max ||
1260 !hinfo->rates || !hinfo->formats) {
1261 per_cvt->assigned = 0;
1262 hinfo->nid = 0;
1263 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1264 mutex_unlock(&spec->pcm_lock);
1265 return -ENODEV;
1266 }
1267 }
1268
1269 mutex_unlock(&spec->pcm_lock);
1270 /* Store the updated parameters */
1271 runtime->hw.channels_min = hinfo->channels_min;
1272 runtime->hw.channels_max = hinfo->channels_max;
1273 runtime->hw.formats = hinfo->formats;
1274 runtime->hw.rates = hinfo->rates;
1275
1276 snd_pcm_hw_constraint_step(substream->runtime, 0,
1277 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1278 return 0;
1279}
1280
1281/*
1282 * HDA/HDMI auto parsing
1283 */
1284static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1285{
1286 struct hdmi_spec *spec = codec->spec;
1287 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1288 hda_nid_t pin_nid = per_pin->pin_nid;
1289
1290 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1291 codec_warn(codec,
1292 "HDMI: pin %d wcaps %#x does not support connection list\n",
1293 pin_nid, get_wcaps(codec, pin_nid));
1294 return -EINVAL;
1295 }
1296
1297 /* all the device entries on the same pin have the same conn list */
1298 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1299 per_pin->mux_nids,
1300 HDA_MAX_CONNECTIONS);
1301
1302 return 0;
1303}
1304
1305static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1306 struct hdmi_spec_per_pin *per_pin)
1307{
1308 int i;
1309
1310 /* try the prefer PCM */
1311 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1312 return per_pin->pin_nid_idx;
1313
1314 /* have a second try; check the "reserved area" over num_pins */
1315 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1316 if (!test_bit(i, &spec->pcm_bitmap))
1317 return i;
1318 }
1319
1320 /* the last try; check the empty slots in pins */
1321 for (i = 0; i < spec->num_nids; i++) {
1322 if (!test_bit(i, &spec->pcm_bitmap))
1323 return i;
1324 }
1325 return -EBUSY;
1326}
1327
1328static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1329 struct hdmi_spec_per_pin *per_pin)
1330{
1331 int idx;
1332
1333 /* pcm already be attached to the pin */
1334 if (per_pin->pcm)
1335 return;
1336 idx = hdmi_find_pcm_slot(spec, per_pin);
1337 if (idx == -EBUSY)
1338 return;
1339 per_pin->pcm_idx = idx;
1340 per_pin->pcm = get_hdmi_pcm(spec, idx);
1341 set_bit(idx, &spec->pcm_bitmap);
1342}
1343
1344static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1345 struct hdmi_spec_per_pin *per_pin)
1346{
1347 int idx;
1348
1349 /* pcm already be detached from the pin */
1350 if (!per_pin->pcm)
1351 return;
1352 idx = per_pin->pcm_idx;
1353 per_pin->pcm_idx = -1;
1354 per_pin->pcm = NULL;
1355 if (idx >= 0 && idx < spec->pcm_used)
1356 clear_bit(idx, &spec->pcm_bitmap);
1357}
1358
1359static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1360 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1361{
1362 int mux_idx;
1363
1364 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1365 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1366 break;
1367 return mux_idx;
1368}
1369
1370static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1371
1372static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1373 struct hdmi_spec_per_pin *per_pin)
1374{
1375 struct hda_codec *codec = per_pin->codec;
1376 struct hda_pcm *pcm;
1377 struct hda_pcm_stream *hinfo;
1378 struct snd_pcm_substream *substream;
1379 int mux_idx;
1380 bool non_pcm;
1381
1382 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1383 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1384 else
1385 return;
1386 if (!pcm->pcm)
1387 return;
1388 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1389 return;
1390
1391 /* hdmi audio only uses playback and one substream */
1392 hinfo = pcm->stream;
1393 substream = pcm->pcm->streams[0].substream;
1394
1395 per_pin->cvt_nid = hinfo->nid;
1396
1397 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1398 if (mux_idx < per_pin->num_mux_nids) {
1399 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1400 per_pin->dev_id);
1401 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1402 AC_VERB_SET_CONNECT_SEL,
1403 mux_idx);
1404 }
1405 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1406
1407 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1408 if (substream->runtime)
1409 per_pin->channels = substream->runtime->channels;
1410 per_pin->setup = true;
1411 per_pin->mux_idx = mux_idx;
1412
1413 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1414}
1415
1416static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1417 struct hdmi_spec_per_pin *per_pin)
1418{
1419 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1420 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1421
1422 per_pin->chmap_set = false;
1423 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1424
1425 per_pin->setup = false;
1426 per_pin->channels = 0;
1427}
1428
1429/* update per_pin ELD from the given new ELD;
1430 * setup info frame and notification accordingly
1431 */
1432static void update_eld(struct hda_codec *codec,
1433 struct hdmi_spec_per_pin *per_pin,
1434 struct hdmi_eld *eld)
1435{
1436 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1437 struct hdmi_spec *spec = codec->spec;
1438 bool old_eld_valid = pin_eld->eld_valid;
1439 bool eld_changed;
1440 int pcm_idx = -1;
1441
1442 /* for monitor disconnection, save pcm_idx firstly */
1443 pcm_idx = per_pin->pcm_idx;
1444 if (spec->dyn_pcm_assign) {
1445 if (eld->eld_valid) {
1446 hdmi_attach_hda_pcm(spec, per_pin);
1447 hdmi_pcm_setup_pin(spec, per_pin);
1448 } else {
1449 hdmi_pcm_reset_pin(spec, per_pin);
1450 hdmi_detach_hda_pcm(spec, per_pin);
1451 }
1452 }
1453 /* if pcm_idx == -1, it means this is in monitor connection event
1454 * we can get the correct pcm_idx now.
1455 */
1456 if (pcm_idx == -1)
1457 pcm_idx = per_pin->pcm_idx;
1458
1459 if (eld->eld_valid)
1460 snd_hdmi_show_eld(codec, &eld->info);
1461
1462 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1463 if (eld->eld_valid && pin_eld->eld_valid)
1464 if (pin_eld->eld_size != eld->eld_size ||
1465 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1466 eld->eld_size) != 0)
1467 eld_changed = true;
1468
1469 pin_eld->monitor_present = eld->monitor_present;
1470 pin_eld->eld_valid = eld->eld_valid;
1471 pin_eld->eld_size = eld->eld_size;
1472 if (eld->eld_valid)
1473 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1474 pin_eld->info = eld->info;
1475
1476 /*
1477 * Re-setup pin and infoframe. This is needed e.g. when
1478 * - sink is first plugged-in
1479 * - transcoder can change during stream playback on Haswell
1480 * and this can make HW reset converter selection on a pin.
1481 */
1482 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1483 pin_cvt_fixup(codec, per_pin, 0);
1484 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1485 }
1486
1487 if (eld_changed && pcm_idx >= 0)
1488 snd_ctl_notify(codec->card,
1489 SNDRV_CTL_EVENT_MASK_VALUE |
1490 SNDRV_CTL_EVENT_MASK_INFO,
1491 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1492}
1493
1494/* update ELD and jack state via HD-audio verbs */
1495static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1496 int repoll)
1497{
1498 struct hda_jack_tbl *jack;
1499 struct hda_codec *codec = per_pin->codec;
1500 struct hdmi_spec *spec = codec->spec;
1501 struct hdmi_eld *eld = &spec->temp_eld;
1502 hda_nid_t pin_nid = per_pin->pin_nid;
1503 /*
1504 * Always execute a GetPinSense verb here, even when called from
1505 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1506 * response's PD bit is not the real PD value, but indicates that
1507 * the real PD value changed. An older version of the HD-audio
1508 * specification worked this way. Hence, we just ignore the data in
1509 * the unsolicited response to avoid custom WARs.
1510 */
1511 int present;
1512 bool ret;
1513 bool do_repoll = false;
1514
1515 present = snd_hda_pin_sense(codec, pin_nid);
1516
1517 mutex_lock(&per_pin->lock);
1518 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1519 if (eld->monitor_present)
1520 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1521 else
1522 eld->eld_valid = false;
1523
1524 codec_dbg(codec,
1525 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1526 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1527
1528 if (eld->eld_valid) {
1529 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1530 &eld->eld_size) < 0)
1531 eld->eld_valid = false;
1532 else {
1533 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1534 eld->eld_size) < 0)
1535 eld->eld_valid = false;
1536 }
1537 if (!eld->eld_valid && repoll)
1538 do_repoll = true;
1539 }
1540
1541 if (do_repoll)
1542 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1543 else
1544 update_eld(codec, per_pin, eld);
1545
1546 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1547
1548 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1549 if (jack)
1550 jack->block_report = !ret;
1551
1552 mutex_unlock(&per_pin->lock);
1553 return ret;
1554}
1555
1556static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1557 struct hdmi_spec_per_pin *per_pin)
1558{
1559 struct hdmi_spec *spec = codec->spec;
1560 struct snd_jack *jack = NULL;
1561 struct hda_jack_tbl *jack_tbl;
1562
1563 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1564 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1565 * NULL even after snd_hda_jack_tbl_clear() is called to
1566 * free snd_jack. This may cause access invalid memory
1567 * when calling snd_jack_report
1568 */
1569 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1570 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1571 else if (!spec->dyn_pcm_assign) {
1572 /*
1573 * jack tbl doesn't support DP MST
1574 * DP MST will use dyn_pcm_assign,
1575 * so DP MST will never come here
1576 */
1577 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1578 if (jack_tbl)
1579 jack = jack_tbl->jack;
1580 }
1581 return jack;
1582}
1583
1584/* update ELD and jack state via audio component */
1585static void sync_eld_via_acomp(struct hda_codec *codec,
1586 struct hdmi_spec_per_pin *per_pin)
1587{
1588 struct hdmi_spec *spec = codec->spec;
1589 struct hdmi_eld *eld = &spec->temp_eld;
1590 struct snd_jack *jack = NULL;
1591 int size;
1592
1593 mutex_lock(&per_pin->lock);
1594 eld->monitor_present = false;
1595 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1596 per_pin->dev_id, &eld->monitor_present,
1597 eld->eld_buffer, ELD_MAX_SIZE);
1598 if (size > 0) {
1599 size = min(size, ELD_MAX_SIZE);
1600 if (snd_hdmi_parse_eld(codec, &eld->info,
1601 eld->eld_buffer, size) < 0)
1602 size = -EINVAL;
1603 }
1604
1605 if (size > 0) {
1606 eld->eld_valid = true;
1607 eld->eld_size = size;
1608 } else {
1609 eld->eld_valid = false;
1610 eld->eld_size = 0;
1611 }
1612
1613 /* pcm_idx >=0 before update_eld() means it is in monitor
1614 * disconnected event. Jack must be fetched before update_eld()
1615 */
1616 jack = pin_idx_to_jack(codec, per_pin);
1617 update_eld(codec, per_pin, eld);
1618 if (jack == NULL)
1619 jack = pin_idx_to_jack(codec, per_pin);
1620 if (jack == NULL)
1621 goto unlock;
1622 snd_jack_report(jack,
1623 eld->monitor_present ? SND_JACK_AVOUT : 0);
1624 unlock:
1625 mutex_unlock(&per_pin->lock);
1626}
1627
1628static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1629{
1630 struct hda_codec *codec = per_pin->codec;
1631 struct hdmi_spec *spec = codec->spec;
1632 int ret;
1633
1634 /* no temporary power up/down needed for component notifier */
1635 if (!codec_has_acomp(codec))
1636 snd_hda_power_up_pm(codec);
1637
1638 mutex_lock(&spec->pcm_lock);
1639 if (codec_has_acomp(codec)) {
1640 sync_eld_via_acomp(codec, per_pin);
1641 ret = false; /* don't call snd_hda_jack_report_sync() */
1642 } else {
1643 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1644 }
1645 mutex_unlock(&spec->pcm_lock);
1646
1647 if (!codec_has_acomp(codec))
1648 snd_hda_power_down_pm(codec);
1649
1650 return ret;
1651}
1652
1653static void hdmi_repoll_eld(struct work_struct *work)
1654{
1655 struct hdmi_spec_per_pin *per_pin =
1656 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1657
1658 if (per_pin->repoll_count++ > 6)
1659 per_pin->repoll_count = 0;
1660
1661 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1662 snd_hda_jack_report_sync(per_pin->codec);
1663}
1664
1665static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1666 hda_nid_t nid);
1667
1668static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1669{
1670 struct hdmi_spec *spec = codec->spec;
1671 unsigned int caps, config;
1672 int pin_idx;
1673 struct hdmi_spec_per_pin *per_pin;
1674 int err;
1675 int dev_num, i;
1676
1677 caps = snd_hda_query_pin_caps(codec, pin_nid);
1678 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1679 return 0;
1680
1681 /*
1682 * For DP MST audio, Configuration Default is the same for
1683 * all device entries on the same pin
1684 */
1685 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1686 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1687 return 0;
1688
1689 /*
1690 * To simplify the implementation, malloc all
1691 * the virtual pins in the initialization statically
1692 */
1693 if (is_haswell_plus(codec)) {
1694 /*
1695 * On Intel platforms, device entries number is
1696 * changed dynamically. If there is a DP MST
1697 * hub connected, the device entries number is 3.
1698 * Otherwise, it is 1.
1699 * Here we manually set dev_num to 3, so that
1700 * we can initialize all the device entries when
1701 * bootup statically.
1702 */
1703 dev_num = 3;
1704 spec->dev_num = 3;
1705 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1706 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1707 /*
1708 * spec->dev_num is the maxinum number of device entries
1709 * among all the pins
1710 */
1711 spec->dev_num = (spec->dev_num > dev_num) ?
1712 spec->dev_num : dev_num;
1713 } else {
1714 /*
1715 * If the platform doesn't support DP MST,
1716 * manually set dev_num to 1. This means
1717 * the pin has only one device entry.
1718 */
1719 dev_num = 1;
1720 spec->dev_num = 1;
1721 }
1722
1723 for (i = 0; i < dev_num; i++) {
1724 pin_idx = spec->num_pins;
1725 per_pin = snd_array_new(&spec->pins);
1726
1727 if (!per_pin)
1728 return -ENOMEM;
1729
1730 if (spec->dyn_pcm_assign) {
1731 per_pin->pcm = NULL;
1732 per_pin->pcm_idx = -1;
1733 } else {
1734 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1735 per_pin->pcm_idx = pin_idx;
1736 }
1737 per_pin->pin_nid = pin_nid;
1738 per_pin->pin_nid_idx = spec->num_nids;
1739 per_pin->dev_id = i;
1740 per_pin->non_pcm = false;
1741 snd_hda_set_dev_select(codec, pin_nid, i);
1742 if (is_haswell_plus(codec))
1743 intel_haswell_fixup_connect_list(codec, pin_nid);
1744 err = hdmi_read_pin_conn(codec, pin_idx);
1745 if (err < 0)
1746 return err;
1747 spec->num_pins++;
1748 }
1749 spec->num_nids++;
1750
1751 return 0;
1752}
1753
1754static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1755{
1756 struct hdmi_spec *spec = codec->spec;
1757 struct hdmi_spec_per_cvt *per_cvt;
1758 unsigned int chans;
1759 int err;
1760
1761 chans = get_wcaps(codec, cvt_nid);
1762 chans = get_wcaps_channels(chans);
1763
1764 per_cvt = snd_array_new(&spec->cvts);
1765 if (!per_cvt)
1766 return -ENOMEM;
1767
1768 per_cvt->cvt_nid = cvt_nid;
1769 per_cvt->channels_min = 2;
1770 if (chans <= 16) {
1771 per_cvt->channels_max = chans;
1772 if (chans > spec->chmap.channels_max)
1773 spec->chmap.channels_max = chans;
1774 }
1775
1776 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1777 &per_cvt->rates,
1778 &per_cvt->formats,
1779 &per_cvt->maxbps);
1780 if (err < 0)
1781 return err;
1782
1783 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1784 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1785 spec->num_cvts++;
1786
1787 return 0;
1788}
1789
1790static int hdmi_parse_codec(struct hda_codec *codec)
1791{
1792 hda_nid_t nid;
1793 int i, nodes;
1794
1795 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1796 if (!nid || nodes < 0) {
1797 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1798 return -EINVAL;
1799 }
1800
1801 for (i = 0; i < nodes; i++, nid++) {
1802 unsigned int caps;
1803 unsigned int type;
1804
1805 caps = get_wcaps(codec, nid);
1806 type = get_wcaps_type(caps);
1807
1808 if (!(caps & AC_WCAP_DIGITAL))
1809 continue;
1810
1811 switch (type) {
1812 case AC_WID_AUD_OUT:
1813 hdmi_add_cvt(codec, nid);
1814 break;
1815 case AC_WID_PIN:
1816 hdmi_add_pin(codec, nid);
1817 break;
1818 }
1819 }
1820
1821 return 0;
1822}
1823
1824/*
1825 */
1826static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1827{
1828 struct hda_spdif_out *spdif;
1829 bool non_pcm;
1830
1831 mutex_lock(&codec->spdif_mutex);
1832 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1833 /* Add sanity check to pass klockwork check.
1834 * This should never happen.
1835 */
1836 if (WARN_ON(spdif == NULL))
1837 return true;
1838 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1839 mutex_unlock(&codec->spdif_mutex);
1840 return non_pcm;
1841}
1842
1843/*
1844 * HDMI callbacks
1845 */
1846
1847static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1848 struct hda_codec *codec,
1849 unsigned int stream_tag,
1850 unsigned int format,
1851 struct snd_pcm_substream *substream)
1852{
1853 hda_nid_t cvt_nid = hinfo->nid;
1854 struct hdmi_spec *spec = codec->spec;
1855 int pin_idx;
1856 struct hdmi_spec_per_pin *per_pin;
1857 hda_nid_t pin_nid;
1858 struct snd_pcm_runtime *runtime = substream->runtime;
1859 bool non_pcm;
1860 int pinctl;
1861 int err;
1862
1863 mutex_lock(&spec->pcm_lock);
1864 pin_idx = hinfo_to_pin_index(codec, hinfo);
1865 if (spec->dyn_pcm_assign && pin_idx < 0) {
1866 /* when dyn_pcm_assign and pcm is not bound to a pin
1867 * skip pin setup and return 0 to make audio playback
1868 * be ongoing
1869 */
1870 pin_cvt_fixup(codec, NULL, cvt_nid);
1871 snd_hda_codec_setup_stream(codec, cvt_nid,
1872 stream_tag, 0, format);
1873 mutex_unlock(&spec->pcm_lock);
1874 return 0;
1875 }
1876
1877 if (snd_BUG_ON(pin_idx < 0)) {
1878 mutex_unlock(&spec->pcm_lock);
1879 return -EINVAL;
1880 }
1881 per_pin = get_pin(spec, pin_idx);
1882 pin_nid = per_pin->pin_nid;
1883
1884 /* Verify pin:cvt selections to avoid silent audio after S3.
1885 * After S3, the audio driver restores pin:cvt selections
1886 * but this can happen before gfx is ready and such selection
1887 * is overlooked by HW. Thus multiple pins can share a same
1888 * default convertor and mute control will affect each other,
1889 * which can cause a resumed audio playback become silent
1890 * after S3.
1891 */
1892 pin_cvt_fixup(codec, per_pin, 0);
1893
1894 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1895 /* Todo: add DP1.2 MST audio support later */
1896 if (codec_has_acomp(codec))
1897 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1898 runtime->rate);
1899
1900 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1901 mutex_lock(&per_pin->lock);
1902 per_pin->channels = substream->runtime->channels;
1903 per_pin->setup = true;
1904
1905 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1906 mutex_unlock(&per_pin->lock);
1907 if (spec->dyn_pin_out) {
1908 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1909 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1910 snd_hda_codec_write(codec, pin_nid, 0,
1911 AC_VERB_SET_PIN_WIDGET_CONTROL,
1912 pinctl | PIN_OUT);
1913 }
1914
1915 /* snd_hda_set_dev_select() has been called before */
1916 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1917 stream_tag, format);
1918 mutex_unlock(&spec->pcm_lock);
1919 return err;
1920}
1921
1922static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1923 struct hda_codec *codec,
1924 struct snd_pcm_substream *substream)
1925{
1926 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1927 return 0;
1928}
1929
1930static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1931 struct hda_codec *codec,
1932 struct snd_pcm_substream *substream)
1933{
1934 struct hdmi_spec *spec = codec->spec;
1935 int cvt_idx, pin_idx, pcm_idx;
1936 struct hdmi_spec_per_cvt *per_cvt;
1937 struct hdmi_spec_per_pin *per_pin;
1938 int pinctl;
1939
1940 if (hinfo->nid) {
1941 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1942 if (snd_BUG_ON(pcm_idx < 0))
1943 return -EINVAL;
1944 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1945 if (snd_BUG_ON(cvt_idx < 0))
1946 return -EINVAL;
1947 per_cvt = get_cvt(spec, cvt_idx);
1948
1949 snd_BUG_ON(!per_cvt->assigned);
1950 per_cvt->assigned = 0;
1951 hinfo->nid = 0;
1952
1953 mutex_lock(&spec->pcm_lock);
1954 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1955 clear_bit(pcm_idx, &spec->pcm_in_use);
1956 pin_idx = hinfo_to_pin_index(codec, hinfo);
1957 if (spec->dyn_pcm_assign && pin_idx < 0) {
1958 mutex_unlock(&spec->pcm_lock);
1959 return 0;
1960 }
1961
1962 if (snd_BUG_ON(pin_idx < 0)) {
1963 mutex_unlock(&spec->pcm_lock);
1964 return -EINVAL;
1965 }
1966 per_pin = get_pin(spec, pin_idx);
1967
1968 if (spec->dyn_pin_out) {
1969 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1970 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1971 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1972 AC_VERB_SET_PIN_WIDGET_CONTROL,
1973 pinctl & ~PIN_OUT);
1974 }
1975
1976 mutex_lock(&per_pin->lock);
1977 per_pin->chmap_set = false;
1978 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1979
1980 per_pin->setup = false;
1981 per_pin->channels = 0;
1982 mutex_unlock(&per_pin->lock);
1983 mutex_unlock(&spec->pcm_lock);
1984 }
1985
1986 return 0;
1987}
1988
1989static const struct hda_pcm_ops generic_ops = {
1990 .open = hdmi_pcm_open,
1991 .close = hdmi_pcm_close,
1992 .prepare = generic_hdmi_playback_pcm_prepare,
1993 .cleanup = generic_hdmi_playback_pcm_cleanup,
1994};
1995
1996static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
1997{
1998 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1999 struct hdmi_spec *spec = codec->spec;
2000 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2001
2002 if (!per_pin)
2003 return 0;
2004
2005 return per_pin->sink_eld.info.spk_alloc;
2006}
2007
2008static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2009 unsigned char *chmap)
2010{
2011 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2012 struct hdmi_spec *spec = codec->spec;
2013 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2014
2015 /* chmap is already set to 0 in caller */
2016 if (!per_pin)
2017 return;
2018
2019 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2020}
2021
2022static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2023 unsigned char *chmap, int prepared)
2024{
2025 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2026 struct hdmi_spec *spec = codec->spec;
2027 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2028
2029 if (!per_pin)
2030 return;
2031 mutex_lock(&per_pin->lock);
2032 per_pin->chmap_set = true;
2033 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2034 if (prepared)
2035 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2036 mutex_unlock(&per_pin->lock);
2037}
2038
2039static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2040{
2041 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2042 struct hdmi_spec *spec = codec->spec;
2043 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2044
2045 return per_pin ? true:false;
2046}
2047
2048static int generic_hdmi_build_pcms(struct hda_codec *codec)
2049{
2050 struct hdmi_spec *spec = codec->spec;
2051 int idx;
2052
2053 /*
2054 * for non-mst mode, pcm number is the same as before
2055 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2056 * dev_num is the device entry number in a pin
2057 *
2058 */
2059 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2060 struct hda_pcm *info;
2061 struct hda_pcm_stream *pstr;
2062
2063 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2064 if (!info)
2065 return -ENOMEM;
2066
2067 spec->pcm_rec[idx].pcm = info;
2068 spec->pcm_used++;
2069 info->pcm_type = HDA_PCM_TYPE_HDMI;
2070 info->own_chmap = true;
2071
2072 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2073 pstr->substreams = 1;
2074 pstr->ops = generic_ops;
2075 /* pcm number is less than 16 */
2076 if (spec->pcm_used >= 16)
2077 break;
2078 /* other pstr fields are set in open */
2079 }
2080
2081 return 0;
2082}
2083
2084static void free_hdmi_jack_priv(struct snd_jack *jack)
2085{
2086 struct hdmi_pcm *pcm = jack->private_data;
2087
2088 pcm->jack = NULL;
2089}
2090
2091static int add_hdmi_jack_kctl(struct hda_codec *codec,
2092 struct hdmi_spec *spec,
2093 int pcm_idx,
2094 const char *name)
2095{
2096 struct snd_jack *jack;
2097 int err;
2098
2099 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2100 true, false);
2101 if (err < 0)
2102 return err;
2103
2104 spec->pcm_rec[pcm_idx].jack = jack;
2105 jack->private_data = &spec->pcm_rec[pcm_idx];
2106 jack->private_free = free_hdmi_jack_priv;
2107 return 0;
2108}
2109
2110static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2111{
2112 char hdmi_str[32] = "HDMI/DP";
2113 struct hdmi_spec *spec = codec->spec;
2114 struct hdmi_spec_per_pin *per_pin;
2115 struct hda_jack_tbl *jack;
2116 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2117 bool phantom_jack;
2118 int ret;
2119
2120 if (pcmdev > 0)
2121 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2122
2123 if (spec->dyn_pcm_assign)
2124 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2125
2126 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2127 /* if !dyn_pcm_assign, it must be non-MST mode.
2128 * This means pcms and pins are statically mapped.
2129 * And pcm_idx is pin_idx.
2130 */
2131 per_pin = get_pin(spec, pcm_idx);
2132 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2133 if (phantom_jack)
2134 strncat(hdmi_str, " Phantom",
2135 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2136 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2137 phantom_jack);
2138 if (ret < 0)
2139 return ret;
2140 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2141 if (jack == NULL)
2142 return 0;
2143 /* assign jack->jack to pcm_rec[].jack to
2144 * align with dyn_pcm_assign mode
2145 */
2146 spec->pcm_rec[pcm_idx].jack = jack->jack;
2147 return 0;
2148}
2149
2150static int generic_hdmi_build_controls(struct hda_codec *codec)
2151{
2152 struct hdmi_spec *spec = codec->spec;
2153 int dev, err;
2154 int pin_idx, pcm_idx;
2155
2156 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2157 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2158 /* no PCM: mark this for skipping permanently */
2159 set_bit(pcm_idx, &spec->pcm_bitmap);
2160 continue;
2161 }
2162
2163 err = generic_hdmi_build_jack(codec, pcm_idx);
2164 if (err < 0)
2165 return err;
2166
2167 /* create the spdif for each pcm
2168 * pin will be bound when monitor is connected
2169 */
2170 if (spec->dyn_pcm_assign)
2171 err = snd_hda_create_dig_out_ctls(codec,
2172 0, spec->cvt_nids[0],
2173 HDA_PCM_TYPE_HDMI);
2174 else {
2175 struct hdmi_spec_per_pin *per_pin =
2176 get_pin(spec, pcm_idx);
2177 err = snd_hda_create_dig_out_ctls(codec,
2178 per_pin->pin_nid,
2179 per_pin->mux_nids[0],
2180 HDA_PCM_TYPE_HDMI);
2181 }
2182 if (err < 0)
2183 return err;
2184 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2185
2186 dev = get_pcm_rec(spec, pcm_idx)->device;
2187 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2188 /* add control for ELD Bytes */
2189 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2190 if (err < 0)
2191 return err;
2192 }
2193 }
2194
2195 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2196 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2197
2198 hdmi_present_sense(per_pin, 0);
2199 }
2200
2201 /* add channel maps */
2202 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2203 struct hda_pcm *pcm;
2204
2205 pcm = get_pcm_rec(spec, pcm_idx);
2206 if (!pcm || !pcm->pcm)
2207 break;
2208 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2209 if (err < 0)
2210 return err;
2211 }
2212
2213 return 0;
2214}
2215
2216static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2217{
2218 struct hdmi_spec *spec = codec->spec;
2219 int pin_idx;
2220
2221 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2222 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2223
2224 per_pin->codec = codec;
2225 mutex_init(&per_pin->lock);
2226 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2227 eld_proc_new(per_pin, pin_idx);
2228 }
2229 return 0;
2230}
2231
2232static int generic_hdmi_init(struct hda_codec *codec)
2233{
2234 struct hdmi_spec *spec = codec->spec;
2235 int pin_idx;
2236
2237 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2238 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2239 hda_nid_t pin_nid = per_pin->pin_nid;
2240 int dev_id = per_pin->dev_id;
2241
2242 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2243 hdmi_init_pin(codec, pin_nid);
2244 if (!codec_has_acomp(codec))
2245 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2246 codec->jackpoll_interval > 0 ?
2247 jack_callback : NULL);
2248 }
2249 return 0;
2250}
2251
2252static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2253{
2254 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2255 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2256}
2257
2258static void hdmi_array_free(struct hdmi_spec *spec)
2259{
2260 snd_array_free(&spec->pins);
2261 snd_array_free(&spec->cvts);
2262}
2263
2264static void generic_spec_free(struct hda_codec *codec)
2265{
2266 struct hdmi_spec *spec = codec->spec;
2267
2268 if (spec) {
2269 hdmi_array_free(spec);
2270 kfree(spec);
2271 codec->spec = NULL;
2272 }
2273 codec->dp_mst = false;
2274}
2275
2276static void generic_hdmi_free(struct hda_codec *codec)
2277{
2278 struct hdmi_spec *spec = codec->spec;
2279 int pin_idx, pcm_idx;
2280
2281 if (codec_has_acomp(codec))
2282 snd_hdac_i915_register_notifier(NULL);
2283
2284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2285 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2286 cancel_delayed_work_sync(&per_pin->work);
2287 eld_proc_free(per_pin);
2288 }
2289
2290 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2291 if (spec->pcm_rec[pcm_idx].jack == NULL)
2292 continue;
2293 if (spec->dyn_pcm_assign)
2294 snd_device_free(codec->card,
2295 spec->pcm_rec[pcm_idx].jack);
2296 else
2297 spec->pcm_rec[pcm_idx].jack = NULL;
2298 }
2299
2300 generic_spec_free(codec);
2301}
2302
2303#ifdef CONFIG_PM
2304static int generic_hdmi_resume(struct hda_codec *codec)
2305{
2306 struct hdmi_spec *spec = codec->spec;
2307 int pin_idx;
2308
2309 codec->patch_ops.init(codec);
2310 regcache_sync(codec->core.regmap);
2311
2312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2313 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2314 hdmi_present_sense(per_pin, 1);
2315 }
2316 return 0;
2317}
2318#endif
2319
2320static const struct hda_codec_ops generic_hdmi_patch_ops = {
2321 .init = generic_hdmi_init,
2322 .free = generic_hdmi_free,
2323 .build_pcms = generic_hdmi_build_pcms,
2324 .build_controls = generic_hdmi_build_controls,
2325 .unsol_event = hdmi_unsol_event,
2326#ifdef CONFIG_PM
2327 .resume = generic_hdmi_resume,
2328#endif
2329};
2330
2331static const struct hdmi_ops generic_standard_hdmi_ops = {
2332 .pin_get_eld = snd_hdmi_get_eld,
2333 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2334 .pin_hbr_setup = hdmi_pin_hbr_setup,
2335 .setup_stream = hdmi_setup_stream,
2336};
2337
2338/* allocate codec->spec and assign/initialize generic parser ops */
2339static int alloc_generic_hdmi(struct hda_codec *codec)
2340{
2341 struct hdmi_spec *spec;
2342
2343 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2344 if (!spec)
2345 return -ENOMEM;
2346
2347 spec->ops = generic_standard_hdmi_ops;
2348 spec->dev_num = 1; /* initialize to 1 */
2349 mutex_init(&spec->pcm_lock);
2350 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2351
2352 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2353 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2354 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2355 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2356
2357 codec->spec = spec;
2358 hdmi_array_init(spec, 4);
2359
2360 codec->patch_ops = generic_hdmi_patch_ops;
2361
2362 return 0;
2363}
2364
2365/* generic HDMI parser */
2366static int patch_generic_hdmi(struct hda_codec *codec)
2367{
2368 int err;
2369
2370 err = alloc_generic_hdmi(codec);
2371 if (err < 0)
2372 return err;
2373
2374 err = hdmi_parse_codec(codec);
2375 if (err < 0) {
2376 generic_spec_free(codec);
2377 return err;
2378 }
2379
2380 generic_hdmi_init_per_pins(codec);
2381 return 0;
2382}
2383
2384/*
2385 * Intel codec parsers and helpers
2386 */
2387
2388static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2389 hda_nid_t nid)
2390{
2391 struct hdmi_spec *spec = codec->spec;
2392 hda_nid_t conns[4];
2393 int nconns;
2394
2395 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2396 if (nconns == spec->num_cvts &&
2397 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2398 return;
2399
2400 /* override pins connection list */
2401 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2402 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2403}
2404
2405#define INTEL_VENDOR_NID 0x08
2406#define INTEL_GLK_VENDOR_NID 0x0B
2407#define INTEL_GET_VENDOR_VERB 0xf81
2408#define INTEL_SET_VENDOR_VERB 0x781
2409#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2410#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2411
2412static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2413 bool update_tree)
2414{
2415 unsigned int vendor_param;
2416 struct hdmi_spec *spec = codec->spec;
2417
2418 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2419 INTEL_GET_VENDOR_VERB, 0);
2420 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2421 return;
2422
2423 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2424 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2425 INTEL_SET_VENDOR_VERB, vendor_param);
2426 if (vendor_param == -1)
2427 return;
2428
2429 if (update_tree)
2430 snd_hda_codec_update_widgets(codec);
2431}
2432
2433static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2434{
2435 unsigned int vendor_param;
2436 struct hdmi_spec *spec = codec->spec;
2437
2438 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2439 INTEL_GET_VENDOR_VERB, 0);
2440 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2441 return;
2442
2443 /* enable DP1.2 mode */
2444 vendor_param |= INTEL_EN_DP12;
2445 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2446 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2447 INTEL_SET_VENDOR_VERB, vendor_param);
2448}
2449
2450/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2451 * Otherwise you may get severe h/w communication errors.
2452 */
2453static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2454 unsigned int power_state)
2455{
2456 if (power_state == AC_PWRST_D0) {
2457 intel_haswell_enable_all_pins(codec, false);
2458 intel_haswell_fixup_enable_dp12(codec);
2459 }
2460
2461 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2462 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2463}
2464
2465static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2466{
2467 struct hda_codec *codec = audio_ptr;
2468 int pin_nid;
2469 int dev_id = pipe;
2470
2471 /* we assume only from port-B to port-D */
2472 if (port < 1 || port > 3)
2473 return;
2474
2475 switch (codec->core.vendor_id) {
2476 case 0x80860054: /* ILK */
2477 case 0x80862804: /* ILK */
2478 case 0x80862882: /* VLV */
2479 pin_nid = port + 0x03;
2480 break;
2481 default:
2482 pin_nid = port + 0x04;
2483 break;
2484 }
2485
2486 /* skip notification during system suspend (but not in runtime PM);
2487 * the state will be updated at resume
2488 */
2489 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2490 return;
2491 /* ditto during suspend/resume process itself */
2492 if (atomic_read(&(codec)->core.in_pm))
2493 return;
2494
2495 snd_hdac_i915_set_bclk(&codec->bus->core);
2496 check_presence_and_report(codec, pin_nid, dev_id);
2497}
2498
2499/* register i915 component pin_eld_notify callback */
2500static void register_i915_notifier(struct hda_codec *codec)
2501{
2502 struct hdmi_spec *spec = codec->spec;
2503
2504 spec->use_acomp_notifier = true;
2505 spec->i915_audio_ops.audio_ptr = codec;
2506 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2507 * will call pin_eld_notify with using audio_ptr pointer
2508 * We need make sure audio_ptr is really setup
2509 */
2510 wmb();
2511 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2512 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2513}
2514
2515/* setup_stream ops override for HSW+ */
2516static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2517 hda_nid_t pin_nid, u32 stream_tag, int format)
2518{
2519 haswell_verify_D0(codec, cvt_nid, pin_nid);
2520 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2521}
2522
2523/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2524static void i915_pin_cvt_fixup(struct hda_codec *codec,
2525 struct hdmi_spec_per_pin *per_pin,
2526 hda_nid_t cvt_nid)
2527{
2528 if (per_pin) {
2529 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2530 per_pin->dev_id);
2531 intel_verify_pin_cvt_connect(codec, per_pin);
2532 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2533 per_pin->dev_id, per_pin->mux_idx);
2534 } else {
2535 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2536 }
2537}
2538
2539/* precondition and allocation for Intel codecs */
2540static int alloc_intel_hdmi(struct hda_codec *codec)
2541{
2542 /* requires i915 binding */
2543 if (!codec->bus->core.audio_component) {
2544 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2545 return -ENODEV;
2546 }
2547
2548 return alloc_generic_hdmi(codec);
2549}
2550
2551/* parse and post-process for Intel codecs */
2552static int parse_intel_hdmi(struct hda_codec *codec)
2553{
2554 int err;
2555
2556 err = hdmi_parse_codec(codec);
2557 if (err < 0) {
2558 generic_spec_free(codec);
2559 return err;
2560 }
2561
2562 generic_hdmi_init_per_pins(codec);
2563 register_i915_notifier(codec);
2564 return 0;
2565}
2566
2567/* Intel Haswell and onwards; audio component with eld notifier */
2568static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2569{
2570 struct hdmi_spec *spec;
2571 int err;
2572
2573 err = alloc_intel_hdmi(codec);
2574 if (err < 0)
2575 return err;
2576 spec = codec->spec;
2577 codec->dp_mst = true;
2578 spec->dyn_pcm_assign = true;
2579 spec->vendor_nid = vendor_nid;
2580
2581 intel_haswell_enable_all_pins(codec, true);
2582 intel_haswell_fixup_enable_dp12(codec);
2583
2584 /* For Haswell/Broadwell, the controller is also in the power well and
2585 * can cover the codec power request, and so need not set this flag.
2586 */
2587 if (!is_haswell(codec) && !is_broadwell(codec))
2588 codec->core.link_power_control = 1;
2589
2590 codec->patch_ops.set_power_state = haswell_set_power_state;
2591 codec->depop_delay = 0;
2592 codec->auto_runtime_pm = 1;
2593
2594 spec->ops.setup_stream = i915_hsw_setup_stream;
2595 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2596
2597 return parse_intel_hdmi(codec);
2598}
2599
2600static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2601{
2602 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2603}
2604
2605static int patch_i915_glk_hdmi(struct hda_codec *codec)
2606{
2607 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2608}
2609
2610/* Intel Baytrail and Braswell; with eld notifier */
2611static int patch_i915_byt_hdmi(struct hda_codec *codec)
2612{
2613 struct hdmi_spec *spec;
2614 int err;
2615
2616 err = alloc_intel_hdmi(codec);
2617 if (err < 0)
2618 return err;
2619 spec = codec->spec;
2620
2621 /* For Valleyview/Cherryview, only the display codec is in the display
2622 * power well and can use link_power ops to request/release the power.
2623 */
2624 codec->core.link_power_control = 1;
2625
2626 codec->depop_delay = 0;
2627 codec->auto_runtime_pm = 1;
2628
2629 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2630
2631 return parse_intel_hdmi(codec);
2632}
2633
2634/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2635static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2636{
2637 int err;
2638
2639 err = alloc_intel_hdmi(codec);
2640 if (err < 0)
2641 return err;
2642 return parse_intel_hdmi(codec);
2643}
2644
2645/*
2646 * Shared non-generic implementations
2647 */
2648
2649static int simple_playback_build_pcms(struct hda_codec *codec)
2650{
2651 struct hdmi_spec *spec = codec->spec;
2652 struct hda_pcm *info;
2653 unsigned int chans;
2654 struct hda_pcm_stream *pstr;
2655 struct hdmi_spec_per_cvt *per_cvt;
2656
2657 per_cvt = get_cvt(spec, 0);
2658 chans = get_wcaps(codec, per_cvt->cvt_nid);
2659 chans = get_wcaps_channels(chans);
2660
2661 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2662 if (!info)
2663 return -ENOMEM;
2664 spec->pcm_rec[0].pcm = info;
2665 info->pcm_type = HDA_PCM_TYPE_HDMI;
2666 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2667 *pstr = spec->pcm_playback;
2668 pstr->nid = per_cvt->cvt_nid;
2669 if (pstr->channels_max <= 2 && chans && chans <= 16)
2670 pstr->channels_max = chans;
2671
2672 return 0;
2673}
2674
2675/* unsolicited event for jack sensing */
2676static void simple_hdmi_unsol_event(struct hda_codec *codec,
2677 unsigned int res)
2678{
2679 snd_hda_jack_set_dirty_all(codec);
2680 snd_hda_jack_report_sync(codec);
2681}
2682
2683/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2684 * as long as spec->pins[] is set correctly
2685 */
2686#define simple_hdmi_build_jack generic_hdmi_build_jack
2687
2688static int simple_playback_build_controls(struct hda_codec *codec)
2689{
2690 struct hdmi_spec *spec = codec->spec;
2691 struct hdmi_spec_per_cvt *per_cvt;
2692 int err;
2693
2694 per_cvt = get_cvt(spec, 0);
2695 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2696 per_cvt->cvt_nid,
2697 HDA_PCM_TYPE_HDMI);
2698 if (err < 0)
2699 return err;
2700 return simple_hdmi_build_jack(codec, 0);
2701}
2702
2703static int simple_playback_init(struct hda_codec *codec)
2704{
2705 struct hdmi_spec *spec = codec->spec;
2706 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2707 hda_nid_t pin = per_pin->pin_nid;
2708
2709 snd_hda_codec_write(codec, pin, 0,
2710 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2711 /* some codecs require to unmute the pin */
2712 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2713 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2714 AMP_OUT_UNMUTE);
2715 snd_hda_jack_detect_enable(codec, pin);
2716 return 0;
2717}
2718
2719static void simple_playback_free(struct hda_codec *codec)
2720{
2721 struct hdmi_spec *spec = codec->spec;
2722
2723 hdmi_array_free(spec);
2724 kfree(spec);
2725}
2726
2727/*
2728 * Nvidia specific implementations
2729 */
2730
2731#define Nv_VERB_SET_Channel_Allocation 0xF79
2732#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2733#define Nv_VERB_SET_Audio_Protection_On 0xF98
2734#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2735
2736#define nvhdmi_master_con_nid_7x 0x04
2737#define nvhdmi_master_pin_nid_7x 0x05
2738
2739static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2740 /*front, rear, clfe, rear_surr */
2741 0x6, 0x8, 0xa, 0xc,
2742};
2743
2744static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2745 /* set audio protect on */
2746 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2747 /* enable digital output on pin widget */
2748 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2749 {} /* terminator */
2750};
2751
2752static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2753 /* set audio protect on */
2754 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2755 /* enable digital output on pin widget */
2756 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2757 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2758 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2759 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2760 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2761 {} /* terminator */
2762};
2763
2764#ifdef LIMITED_RATE_FMT_SUPPORT
2765/* support only the safe format and rate */
2766#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2767#define SUPPORTED_MAXBPS 16
2768#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2769#else
2770/* support all rates and formats */
2771#define SUPPORTED_RATES \
2772 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2773 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2774 SNDRV_PCM_RATE_192000)
2775#define SUPPORTED_MAXBPS 24
2776#define SUPPORTED_FORMATS \
2777 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2778#endif
2779
2780static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2781{
2782 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2783 return 0;
2784}
2785
2786static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2787{
2788 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2789 return 0;
2790}
2791
2792static const unsigned int channels_2_6_8[] = {
2793 2, 6, 8
2794};
2795
2796static const unsigned int channels_2_8[] = {
2797 2, 8
2798};
2799
2800static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2801 .count = ARRAY_SIZE(channels_2_6_8),
2802 .list = channels_2_6_8,
2803 .mask = 0,
2804};
2805
2806static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2807 .count = ARRAY_SIZE(channels_2_8),
2808 .list = channels_2_8,
2809 .mask = 0,
2810};
2811
2812static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2813 struct hda_codec *codec,
2814 struct snd_pcm_substream *substream)
2815{
2816 struct hdmi_spec *spec = codec->spec;
2817 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2818
2819 switch (codec->preset->vendor_id) {
2820 case 0x10de0002:
2821 case 0x10de0003:
2822 case 0x10de0005:
2823 case 0x10de0006:
2824 hw_constraints_channels = &hw_constraints_2_8_channels;
2825 break;
2826 case 0x10de0007:
2827 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2828 break;
2829 default:
2830 break;
2831 }
2832
2833 if (hw_constraints_channels != NULL) {
2834 snd_pcm_hw_constraint_list(substream->runtime, 0,
2835 SNDRV_PCM_HW_PARAM_CHANNELS,
2836 hw_constraints_channels);
2837 } else {
2838 snd_pcm_hw_constraint_step(substream->runtime, 0,
2839 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2840 }
2841
2842 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2843}
2844
2845static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2846 struct hda_codec *codec,
2847 struct snd_pcm_substream *substream)
2848{
2849 struct hdmi_spec *spec = codec->spec;
2850 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2851}
2852
2853static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2854 struct hda_codec *codec,
2855 unsigned int stream_tag,
2856 unsigned int format,
2857 struct snd_pcm_substream *substream)
2858{
2859 struct hdmi_spec *spec = codec->spec;
2860 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2861 stream_tag, format, substream);
2862}
2863
2864static const struct hda_pcm_stream simple_pcm_playback = {
2865 .substreams = 1,
2866 .channels_min = 2,
2867 .channels_max = 2,
2868 .ops = {
2869 .open = simple_playback_pcm_open,
2870 .close = simple_playback_pcm_close,
2871 .prepare = simple_playback_pcm_prepare
2872 },
2873};
2874
2875static const struct hda_codec_ops simple_hdmi_patch_ops = {
2876 .build_controls = simple_playback_build_controls,
2877 .build_pcms = simple_playback_build_pcms,
2878 .init = simple_playback_init,
2879 .free = simple_playback_free,
2880 .unsol_event = simple_hdmi_unsol_event,
2881};
2882
2883static int patch_simple_hdmi(struct hda_codec *codec,
2884 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2885{
2886 struct hdmi_spec *spec;
2887 struct hdmi_spec_per_cvt *per_cvt;
2888 struct hdmi_spec_per_pin *per_pin;
2889
2890 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2891 if (!spec)
2892 return -ENOMEM;
2893
2894 codec->spec = spec;
2895 hdmi_array_init(spec, 1);
2896
2897 spec->multiout.num_dacs = 0; /* no analog */
2898 spec->multiout.max_channels = 2;
2899 spec->multiout.dig_out_nid = cvt_nid;
2900 spec->num_cvts = 1;
2901 spec->num_pins = 1;
2902 per_pin = snd_array_new(&spec->pins);
2903 per_cvt = snd_array_new(&spec->cvts);
2904 if (!per_pin || !per_cvt) {
2905 simple_playback_free(codec);
2906 return -ENOMEM;
2907 }
2908 per_cvt->cvt_nid = cvt_nid;
2909 per_pin->pin_nid = pin_nid;
2910 spec->pcm_playback = simple_pcm_playback;
2911
2912 codec->patch_ops = simple_hdmi_patch_ops;
2913
2914 return 0;
2915}
2916
2917static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2918 int channels)
2919{
2920 unsigned int chanmask;
2921 int chan = channels ? (channels - 1) : 1;
2922
2923 switch (channels) {
2924 default:
2925 case 0:
2926 case 2:
2927 chanmask = 0x00;
2928 break;
2929 case 4:
2930 chanmask = 0x08;
2931 break;
2932 case 6:
2933 chanmask = 0x0b;
2934 break;
2935 case 8:
2936 chanmask = 0x13;
2937 break;
2938 }
2939
2940 /* Set the audio infoframe channel allocation and checksum fields. The
2941 * channel count is computed implicitly by the hardware. */
2942 snd_hda_codec_write(codec, 0x1, 0,
2943 Nv_VERB_SET_Channel_Allocation, chanmask);
2944
2945 snd_hda_codec_write(codec, 0x1, 0,
2946 Nv_VERB_SET_Info_Frame_Checksum,
2947 (0x71 - chan - chanmask));
2948}
2949
2950static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2951 struct hda_codec *codec,
2952 struct snd_pcm_substream *substream)
2953{
2954 struct hdmi_spec *spec = codec->spec;
2955 int i;
2956
2957 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2958 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2959 for (i = 0; i < 4; i++) {
2960 /* set the stream id */
2961 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2962 AC_VERB_SET_CHANNEL_STREAMID, 0);
2963 /* set the stream format */
2964 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2965 AC_VERB_SET_STREAM_FORMAT, 0);
2966 }
2967
2968 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2969 * streams are disabled. */
2970 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2971
2972 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2973}
2974
2975static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2976 struct hda_codec *codec,
2977 unsigned int stream_tag,
2978 unsigned int format,
2979 struct snd_pcm_substream *substream)
2980{
2981 int chs;
2982 unsigned int dataDCC2, channel_id;
2983 int i;
2984 struct hdmi_spec *spec = codec->spec;
2985 struct hda_spdif_out *spdif;
2986 struct hdmi_spec_per_cvt *per_cvt;
2987
2988 mutex_lock(&codec->spdif_mutex);
2989 per_cvt = get_cvt(spec, 0);
2990 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2991
2992 chs = substream->runtime->channels;
2993
2994 dataDCC2 = 0x2;
2995
2996 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2997 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2998 snd_hda_codec_write(codec,
2999 nvhdmi_master_con_nid_7x,
3000 0,
3001 AC_VERB_SET_DIGI_CONVERT_1,
3002 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3003
3004 /* set the stream id */
3005 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3006 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3007
3008 /* set the stream format */
3009 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3010 AC_VERB_SET_STREAM_FORMAT, format);
3011
3012 /* turn on again (if needed) */
3013 /* enable and set the channel status audio/data flag */
3014 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3015 snd_hda_codec_write(codec,
3016 nvhdmi_master_con_nid_7x,
3017 0,
3018 AC_VERB_SET_DIGI_CONVERT_1,
3019 spdif->ctls & 0xff);
3020 snd_hda_codec_write(codec,
3021 nvhdmi_master_con_nid_7x,
3022 0,
3023 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3024 }
3025
3026 for (i = 0; i < 4; i++) {
3027 if (chs == 2)
3028 channel_id = 0;
3029 else
3030 channel_id = i * 2;
3031
3032 /* turn off SPDIF once;
3033 *otherwise the IEC958 bits won't be updated
3034 */
3035 if (codec->spdif_status_reset &&
3036 (spdif->ctls & AC_DIG1_ENABLE))
3037 snd_hda_codec_write(codec,
3038 nvhdmi_con_nids_7x[i],
3039 0,
3040 AC_VERB_SET_DIGI_CONVERT_1,
3041 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3042 /* set the stream id */
3043 snd_hda_codec_write(codec,
3044 nvhdmi_con_nids_7x[i],
3045 0,
3046 AC_VERB_SET_CHANNEL_STREAMID,
3047 (stream_tag << 4) | channel_id);
3048 /* set the stream format */
3049 snd_hda_codec_write(codec,
3050 nvhdmi_con_nids_7x[i],
3051 0,
3052 AC_VERB_SET_STREAM_FORMAT,
3053 format);
3054 /* turn on again (if needed) */
3055 /* enable and set the channel status audio/data flag */
3056 if (codec->spdif_status_reset &&
3057 (spdif->ctls & AC_DIG1_ENABLE)) {
3058 snd_hda_codec_write(codec,
3059 nvhdmi_con_nids_7x[i],
3060 0,
3061 AC_VERB_SET_DIGI_CONVERT_1,
3062 spdif->ctls & 0xff);
3063 snd_hda_codec_write(codec,
3064 nvhdmi_con_nids_7x[i],
3065 0,
3066 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3067 }
3068 }
3069
3070 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3071
3072 mutex_unlock(&codec->spdif_mutex);
3073 return 0;
3074}
3075
3076static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3077 .substreams = 1,
3078 .channels_min = 2,
3079 .channels_max = 8,
3080 .nid = nvhdmi_master_con_nid_7x,
3081 .rates = SUPPORTED_RATES,
3082 .maxbps = SUPPORTED_MAXBPS,
3083 .formats = SUPPORTED_FORMATS,
3084 .ops = {
3085 .open = simple_playback_pcm_open,
3086 .close = nvhdmi_8ch_7x_pcm_close,
3087 .prepare = nvhdmi_8ch_7x_pcm_prepare
3088 },
3089};
3090
3091static int patch_nvhdmi_2ch(struct hda_codec *codec)
3092{
3093 struct hdmi_spec *spec;
3094 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3095 nvhdmi_master_pin_nid_7x);
3096 if (err < 0)
3097 return err;
3098
3099 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3100 /* override the PCM rates, etc, as the codec doesn't give full list */
3101 spec = codec->spec;
3102 spec->pcm_playback.rates = SUPPORTED_RATES;
3103 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3104 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3105 return 0;
3106}
3107
3108static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3109{
3110 struct hdmi_spec *spec = codec->spec;
3111 int err = simple_playback_build_pcms(codec);
3112 if (!err) {
3113 struct hda_pcm *info = get_pcm_rec(spec, 0);
3114 info->own_chmap = true;
3115 }
3116 return err;
3117}
3118
3119static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3120{
3121 struct hdmi_spec *spec = codec->spec;
3122 struct hda_pcm *info;
3123 struct snd_pcm_chmap *chmap;
3124 int err;
3125
3126 err = simple_playback_build_controls(codec);
3127 if (err < 0)
3128 return err;
3129
3130 /* add channel maps */
3131 info = get_pcm_rec(spec, 0);
3132 err = snd_pcm_add_chmap_ctls(info->pcm,
3133 SNDRV_PCM_STREAM_PLAYBACK,
3134 snd_pcm_alt_chmaps, 8, 0, &chmap);
3135 if (err < 0)
3136 return err;
3137 switch (codec->preset->vendor_id) {
3138 case 0x10de0002:
3139 case 0x10de0003:
3140 case 0x10de0005:
3141 case 0x10de0006:
3142 chmap->channel_mask = (1U << 2) | (1U << 8);
3143 break;
3144 case 0x10de0007:
3145 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3146 }
3147 return 0;
3148}
3149
3150static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3151{
3152 struct hdmi_spec *spec;
3153 int err = patch_nvhdmi_2ch(codec);
3154 if (err < 0)
3155 return err;
3156 spec = codec->spec;
3157 spec->multiout.max_channels = 8;
3158 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3159 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3160 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3161 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3162
3163 /* Initialize the audio infoframe channel mask and checksum to something
3164 * valid */
3165 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3166
3167 return 0;
3168}
3169
3170/*
3171 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3172 * - 0x10de0015
3173 * - 0x10de0040
3174 */
3175static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3176 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3177{
3178 if (cap->ca_index == 0x00 && channels == 2)
3179 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3180
3181 /* If the speaker allocation matches the channel count, it is OK. */
3182 if (cap->channels != channels)
3183 return -1;
3184
3185 /* all channels are remappable freely */
3186 return SNDRV_CTL_TLVT_CHMAP_VAR;
3187}
3188
3189static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3190 int ca, int chs, unsigned char *map)
3191{
3192 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3193 return -EINVAL;
3194
3195 return 0;
3196}
3197
3198static int patch_nvhdmi(struct hda_codec *codec)
3199{
3200 struct hdmi_spec *spec;
3201 int err;
3202
3203 err = patch_generic_hdmi(codec);
3204 if (err)
3205 return err;
3206
3207 spec = codec->spec;
3208 spec->dyn_pin_out = true;
3209
3210 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3211 nvhdmi_chmap_cea_alloc_validate_get_type;
3212 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3213
3214 return 0;
3215}
3216
3217/*
3218 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3219 * accessed using vendor-defined verbs. These registers can be used for
3220 * interoperability between the HDA and HDMI drivers.
3221 */
3222
3223/* Audio Function Group node */
3224#define NVIDIA_AFG_NID 0x01
3225
3226/*
3227 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3228 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3229 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3230 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3231 * additional bit (at position 30) to signal the validity of the format.
3232 *
3233 * | 31 | 30 | 29 16 | 15 0 |
3234 * +---------+-------+--------+--------+
3235 * | TRIGGER | VALID | UNUSED | FORMAT |
3236 * +-----------------------------------|
3237 *
3238 * Note that for the trigger bit to take effect it needs to change value
3239 * (i.e. it needs to be toggled).
3240 */
3241#define NVIDIA_GET_SCRATCH0 0xfa6
3242#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3243#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3244#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3245#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3246#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3247#define NVIDIA_SCRATCH_VALID (1 << 6)
3248
3249#define NVIDIA_GET_SCRATCH1 0xfab
3250#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3251#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3252#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3253#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3254
3255/*
3256 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3257 * the format is invalidated so that the HDMI codec can be disabled.
3258 */
3259static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3260{
3261 unsigned int value;
3262
3263 /* bits [31:30] contain the trigger and valid bits */
3264 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3265 NVIDIA_GET_SCRATCH0, 0);
3266 value = (value >> 24) & 0xff;
3267
3268 /* bits [15:0] are used to store the HDA format */
3269 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3270 NVIDIA_SET_SCRATCH0_BYTE0,
3271 (format >> 0) & 0xff);
3272 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3273 NVIDIA_SET_SCRATCH0_BYTE1,
3274 (format >> 8) & 0xff);
3275
3276 /* bits [16:24] are unused */
3277 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3278 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3279
3280 /*
3281 * Bit 30 signals that the data is valid and hence that HDMI audio can
3282 * be enabled.
3283 */
3284 if (format == 0)
3285 value &= ~NVIDIA_SCRATCH_VALID;
3286 else
3287 value |= NVIDIA_SCRATCH_VALID;
3288
3289 /*
3290 * Whenever the trigger bit is toggled, an interrupt is raised in the
3291 * HDMI codec. The HDMI driver will use that as trigger to update its
3292 * configuration.
3293 */
3294 value ^= NVIDIA_SCRATCH_TRIGGER;
3295
3296 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3297 NVIDIA_SET_SCRATCH0_BYTE3, value);
3298}
3299
3300static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3301 struct hda_codec *codec,
3302 unsigned int stream_tag,
3303 unsigned int format,
3304 struct snd_pcm_substream *substream)
3305{
3306 int err;
3307
3308 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3309 format, substream);
3310 if (err < 0)
3311 return err;
3312
3313 /* notify the HDMI codec of the format change */
3314 tegra_hdmi_set_format(codec, format);
3315
3316 return 0;
3317}
3318
3319static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3320 struct hda_codec *codec,
3321 struct snd_pcm_substream *substream)
3322{
3323 /* invalidate the format in the HDMI codec */
3324 tegra_hdmi_set_format(codec, 0);
3325
3326 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3327}
3328
3329static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3330{
3331 struct hdmi_spec *spec = codec->spec;
3332 unsigned int i;
3333
3334 for (i = 0; i < spec->num_pins; i++) {
3335 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3336
3337 if (pcm->pcm_type == type)
3338 return pcm;
3339 }
3340
3341 return NULL;
3342}
3343
3344static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3345{
3346 struct hda_pcm_stream *stream;
3347 struct hda_pcm *pcm;
3348 int err;
3349
3350 err = generic_hdmi_build_pcms(codec);
3351 if (err < 0)
3352 return err;
3353
3354 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3355 if (!pcm)
3356 return -ENODEV;
3357
3358 /*
3359 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3360 * codec about format changes.
3361 */
3362 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3363 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3364 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3365
3366 return 0;
3367}
3368
3369static int patch_tegra_hdmi(struct hda_codec *codec)
3370{
3371 int err;
3372
3373 err = patch_generic_hdmi(codec);
3374 if (err)
3375 return err;
3376
3377 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3378
3379 return 0;
3380}
3381
3382/*
3383 * ATI/AMD-specific implementations
3384 */
3385
3386#define is_amdhdmi_rev3_or_later(codec) \
3387 ((codec)->core.vendor_id == 0x1002aa01 && \
3388 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3389#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3390
3391/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3392#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3393#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3394#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3395#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3396#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3397#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3398#define ATI_VERB_SET_HBR_CONTROL 0x77c
3399#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3400#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3401#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3402#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3403#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3404#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3405#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3406#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3407#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3408#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3409#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3410#define ATI_VERB_GET_HBR_CONTROL 0xf7c
3411#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3412#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3413#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3414#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3415#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3416
3417/* AMD specific HDA cvt verbs */
3418#define ATI_VERB_SET_RAMP_RATE 0x770
3419#define ATI_VERB_GET_RAMP_RATE 0xf70
3420
3421#define ATI_OUT_ENABLE 0x1
3422
3423#define ATI_MULTICHANNEL_MODE_PAIRED 0
3424#define ATI_MULTICHANNEL_MODE_SINGLE 1
3425
3426#define ATI_HBR_CAPABLE 0x01
3427#define ATI_HBR_ENABLE 0x10
3428
3429static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3430 unsigned char *buf, int *eld_size)
3431{
3432 /* call hda_eld.c ATI/AMD-specific function */
3433 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3434 is_amdhdmi_rev3_or_later(codec));
3435}
3436
3437static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3438 int active_channels, int conn_type)
3439{
3440 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3441}
3442
3443static int atihdmi_paired_swap_fc_lfe(int pos)
3444{
3445 /*
3446 * ATI/AMD have automatic FC/LFE swap built-in
3447 * when in pairwise mapping mode.
3448 */
3449
3450 switch (pos) {
3451 /* see channel_allocations[].speakers[] */
3452 case 2: return 3;
3453 case 3: return 2;
3454 default: break;
3455 }
3456
3457 return pos;
3458}
3459
3460static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3461 int ca, int chs, unsigned char *map)
3462{
3463 struct hdac_cea_channel_speaker_allocation *cap;
3464 int i, j;
3465
3466 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3467
3468 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3469 for (i = 0; i < chs; ++i) {
3470 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3471 bool ok = false;
3472 bool companion_ok = false;
3473
3474 if (!mask)
3475 continue;
3476
3477 for (j = 0 + i % 2; j < 8; j += 2) {
3478 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3479 if (cap->speakers[chan_idx] == mask) {
3480 /* channel is in a supported position */
3481 ok = true;
3482
3483 if (i % 2 == 0 && i + 1 < chs) {
3484 /* even channel, check the odd companion */
3485 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3486 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3487 int comp_mask_act = cap->speakers[comp_chan_idx];
3488
3489 if (comp_mask_req == comp_mask_act)
3490 companion_ok = true;
3491 else
3492 return -EINVAL;
3493 }
3494 break;
3495 }
3496 }
3497
3498 if (!ok)
3499 return -EINVAL;
3500
3501 if (companion_ok)
3502 i++; /* companion channel already checked */
3503 }
3504
3505 return 0;
3506}
3507
3508static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3509 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3510{
3511 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3512 int verb;
3513 int ati_channel_setup = 0;
3514
3515 if (hdmi_slot > 7)
3516 return -EINVAL;
3517
3518 if (!has_amd_full_remap_support(codec)) {
3519 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3520
3521 /* In case this is an odd slot but without stream channel, do not
3522 * disable the slot since the corresponding even slot could have a
3523 * channel. In case neither have a channel, the slot pair will be
3524 * disabled when this function is called for the even slot. */
3525 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3526 return 0;
3527
3528 hdmi_slot -= hdmi_slot % 2;
3529
3530 if (stream_channel != 0xf)
3531 stream_channel -= stream_channel % 2;
3532 }
3533
3534 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3535
3536 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3537
3538 if (stream_channel != 0xf)
3539 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3540
3541 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3542}
3543
3544static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3545 hda_nid_t pin_nid, int asp_slot)
3546{
3547 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3548 bool was_odd = false;
3549 int ati_asp_slot = asp_slot;
3550 int verb;
3551 int ati_channel_setup;
3552
3553 if (asp_slot > 7)
3554 return -EINVAL;
3555
3556 if (!has_amd_full_remap_support(codec)) {
3557 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3558 if (ati_asp_slot % 2 != 0) {
3559 ati_asp_slot -= 1;
3560 was_odd = true;
3561 }
3562 }
3563
3564 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3565
3566 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3567
3568 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3569 return 0xf;
3570
3571 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3572}
3573
3574static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3575 struct hdac_chmap *chmap,
3576 struct hdac_cea_channel_speaker_allocation *cap,
3577 int channels)
3578{
3579 int c;
3580
3581 /*
3582 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3583 * we need to take that into account (a single channel may take 2
3584 * channel slots if we need to carry a silent channel next to it).
3585 * On Rev3+ AMD codecs this function is not used.
3586 */
3587 int chanpairs = 0;
3588
3589 /* We only produce even-numbered channel count TLVs */
3590 if ((channels % 2) != 0)
3591 return -1;
3592
3593 for (c = 0; c < 7; c += 2) {
3594 if (cap->speakers[c] || cap->speakers[c+1])
3595 chanpairs++;
3596 }
3597
3598 if (chanpairs * 2 != channels)
3599 return -1;
3600
3601 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3602}
3603
3604static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3605 struct hdac_cea_channel_speaker_allocation *cap,
3606 unsigned int *chmap, int channels)
3607{
3608 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3609 int count = 0;
3610 int c;
3611
3612 for (c = 7; c >= 0; c--) {
3613 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3614 int spk = cap->speakers[chan];
3615 if (!spk) {
3616 /* add N/A channel if the companion channel is occupied */
3617 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3618 chmap[count++] = SNDRV_CHMAP_NA;
3619
3620 continue;
3621 }
3622
3623 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3624 }
3625
3626 WARN_ON(count != channels);
3627}
3628
3629static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3630 bool hbr)
3631{
3632 int hbr_ctl, hbr_ctl_new;
3633
3634 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3635 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3636 if (hbr)
3637 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3638 else
3639 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3640
3641 codec_dbg(codec,
3642 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3643 pin_nid,
3644 hbr_ctl == hbr_ctl_new ? "" : "new-",
3645 hbr_ctl_new);
3646
3647 if (hbr_ctl != hbr_ctl_new)
3648 snd_hda_codec_write(codec, pin_nid, 0,
3649 ATI_VERB_SET_HBR_CONTROL,
3650 hbr_ctl_new);
3651
3652 } else if (hbr)
3653 return -EINVAL;
3654
3655 return 0;
3656}
3657
3658static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3659 hda_nid_t pin_nid, u32 stream_tag, int format)
3660{
3661
3662 if (is_amdhdmi_rev3_or_later(codec)) {
3663 int ramp_rate = 180; /* default as per AMD spec */
3664 /* disable ramp-up/down for non-pcm as per AMD spec */
3665 if (format & AC_FMT_TYPE_NON_PCM)
3666 ramp_rate = 0;
3667
3668 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3669 }
3670
3671 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3672}
3673
3674
3675static int atihdmi_init(struct hda_codec *codec)
3676{
3677 struct hdmi_spec *spec = codec->spec;
3678 int pin_idx, err;
3679
3680 err = generic_hdmi_init(codec);
3681
3682 if (err)
3683 return err;
3684
3685 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3686 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3687
3688 /* make sure downmix information in infoframe is zero */
3689 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3690
3691 /* enable channel-wise remap mode if supported */
3692 if (has_amd_full_remap_support(codec))
3693 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3694 ATI_VERB_SET_MULTICHANNEL_MODE,
3695 ATI_MULTICHANNEL_MODE_SINGLE);
3696 }
3697
3698 return 0;
3699}
3700
3701static int patch_atihdmi(struct hda_codec *codec)
3702{
3703 struct hdmi_spec *spec;
3704 struct hdmi_spec_per_cvt *per_cvt;
3705 int err, cvt_idx;
3706
3707 err = patch_generic_hdmi(codec);
3708
3709 if (err)
3710 return err;
3711
3712 codec->patch_ops.init = atihdmi_init;
3713
3714 spec = codec->spec;
3715
3716 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3717 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3718 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3719 spec->ops.setup_stream = atihdmi_setup_stream;
3720
3721 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3722 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3723
3724 if (!has_amd_full_remap_support(codec)) {
3725 /* override to ATI/AMD-specific versions with pairwise mapping */
3726 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3727 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3728 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3729 atihdmi_paired_cea_alloc_to_tlv_chmap;
3730 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3731 }
3732
3733 /* ATI/AMD converters do not advertise all of their capabilities */
3734 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3735 per_cvt = get_cvt(spec, cvt_idx);
3736 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3737 per_cvt->rates |= SUPPORTED_RATES;
3738 per_cvt->formats |= SUPPORTED_FORMATS;
3739 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3740 }
3741
3742 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3743
3744 return 0;
3745}
3746
3747/* VIA HDMI Implementation */
3748#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3749#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3750
3751static int patch_via_hdmi(struct hda_codec *codec)
3752{
3753 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3754}
3755
3756/*
3757 * patch entries
3758 */
3759static const struct hda_device_id snd_hda_id_hdmi[] = {
3760HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3761HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3762HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3763HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3764HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3765HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3766HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3767HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3768HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3769HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3770HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3771HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3772HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3773HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3774HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3775HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3776HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3777HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3778HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3779HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3780HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3781HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3782HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3783HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3784HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3785HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3786HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3787/* 17 is known to be absent */
3788HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3789HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3790HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3791HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3792HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3793HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3794HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3795HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3796HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3797HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3798HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3799HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3800HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3801HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3802HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3803HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3804HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3805HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3806HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3807HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3808HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3809HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3810HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3811HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3812HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3813HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3814HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3815HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3816HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3817HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3818HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3819HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3820HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3821HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3822HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3823HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3824HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3825HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3826HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3827HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3828HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3829HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3830HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3831HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3832HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3833HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3834HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3835HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3836HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3837HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3838HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3839HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3840HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3841HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3842HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3843HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3844HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3845HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3846HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3847HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3848HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3849HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3850HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3851HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3852HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3853HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3854HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3855HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3856HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3857HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3858HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3859/* special ID for generic HDMI */
3860HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3861{} /* terminator */
3862};
3863MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3864
3865MODULE_LICENSE("GPL");
3866MODULE_DESCRIPTION("HDMI HD-audio codec");
3867MODULE_ALIAS("snd-hda-codec-intelhdmi");
3868MODULE_ALIAS("snd-hda-codec-nvhdmi");
3869MODULE_ALIAS("snd-hda-codec-atihdmi");
3870
3871static struct hda_codec_driver hdmi_driver = {
3872 .id = snd_hda_id_hdmi,
3873};
3874
3875module_hda_codec_driver(hdmi_driver);