1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Copyright (c)  2018 Intel Corporation */
 3
 4#ifndef _IGC_BASE_H_
 5#define _IGC_BASE_H_
 6
 7/* forward declaration */
 8void igc_rx_fifo_flush_base(struct igc_hw *hw);
 9void igc_power_down_phy_copper_base(struct igc_hw *hw);
10
11/* Transmit Descriptor - Advanced */
12union igc_adv_tx_desc {
13	struct {
14		__le64 buffer_addr;    /* Address of descriptor's data buf */
15		__le32 cmd_type_len;
16		__le32 olinfo_status;
17	} read;
18	struct {
19		__le64 rsvd;       /* Reserved */
20		__le32 nxtseq_seed;
21		__le32 status;
22	} wb;
23};
24
25/* Context descriptors */
26struct igc_adv_tx_context_desc {
27	__le32 vlan_macip_lens;
28	__le32 launch_time;
29	__le32 type_tucmd_mlhl;
30	__le32 mss_l4len_idx;
31};
32
33/* Adv Transmit Descriptor Config Masks */
34#define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp packet */
35#define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
36#define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
37#define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
38#define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
39#define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
40#define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
41#define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
42#define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
43#define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
44
45#define IGC_RAR_ENTRIES		16
46
47/* Receive Descriptor - Advanced */
48union igc_adv_rx_desc {
49	struct {
50		__le64 pkt_addr; /* Packet buffer address */
51		__le64 hdr_addr; /* Header buffer address */
52	} read;
53	struct {
54		struct {
55			union {
56				__le32 data;
57				struct {
58					__le16 pkt_info; /*RSS type, Pkt type*/
59					/* Split Header, header buffer len */
60					__le16 hdr_info;
61				} hs_rss;
62			} lo_dword;
63			union {
64				__le32 rss; /* RSS Hash */
65				struct {
66					__le16 ip_id; /* IP id */
67					__le16 csum; /* Packet Checksum */
68				} csum_ip;
69			} hi_dword;
70		} lower;
71		struct {
72			__le32 status_error; /* ext status/error */
73			__le16 length; /* Packet length */
74			__le16 vlan; /* VLAN tag */
75		} upper;
76	} wb;  /* writeback */
77};
78
79/* Additional Transmit Descriptor Control definitions */
80#define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
81
82/* Additional Receive Descriptor Control definitions */
83#define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
84
85/* SRRCTL bit definitions */
86#define IGC_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
87#define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
88#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
89
90#endif /* _IGC_BASE_H */