1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c)  2018 Intel Corporation */
  3
  4#ifndef _IGC_BASE_H_
  5#define _IGC_BASE_H_
  6
  7/* forward declaration */
  8void igc_rx_fifo_flush_base(struct igc_hw *hw);
  9void igc_power_down_phy_copper_base(struct igc_hw *hw);
 10bool igc_is_device_id_i225(struct igc_hw *hw);
 11bool igc_is_device_id_i226(struct igc_hw *hw);
 12
 13/* Transmit Descriptor - Advanced */
 14union igc_adv_tx_desc {
 15	struct {
 16		__le64 buffer_addr;    /* Address of descriptor's data buf */
 17		__le32 cmd_type_len;
 18		__le32 olinfo_status;
 19	} read;
 20	struct {
 21		__le64 rsvd;       /* Reserved */
 22		__le32 nxtseq_seed;
 23		__le32 status;
 24	} wb;
 25};
 26
 27/* Context descriptors */
 28struct igc_adv_tx_context_desc {
 29	__le32 vlan_macip_lens;
 30	__le32 launch_time;
 31	__le32 type_tucmd_mlhl;
 32	__le32 mss_l4len_idx;
 33};
 34
 35/* Adv Transmit Descriptor Config Masks */
 36#define IGC_ADVTXD_MAC_TSTAMP	0x00080000 /* IEEE1588 Timestamp packet */
 37#define IGC_ADVTXD_TSTAMP_REG_1	0x00010000 /* Select register 1 for timestamp */
 38#define IGC_ADVTXD_TSTAMP_REG_2	0x00020000 /* Select register 2 for timestamp */
 39#define IGC_ADVTXD_TSTAMP_REG_3	0x00030000 /* Select register 3 for timestamp */
 40#define IGC_ADVTXD_TSTAMP_TIMER_1	0x00010000 /* Select timer 1 for timestamp */
 41#define IGC_ADVTXD_TSTAMP_TIMER_2	0x00020000 /* Select timer 2 for timestamp */
 42#define IGC_ADVTXD_TSTAMP_TIMER_3	0x00030000 /* Select timer 3 for timestamp */
 43
 44#define IGC_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
 45#define IGC_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
 46#define IGC_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
 47#define IGC_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
 48#define IGC_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
 49#define IGC_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
 50#define IGC_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
 51#define IGC_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
 52#define IGC_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
 53
 54#define IGC_RAR_ENTRIES		16
 55
 56/* Receive Descriptor - Advanced */
 57union igc_adv_rx_desc {
 58	struct {
 59		__le64 pkt_addr; /* Packet buffer address */
 60		__le64 hdr_addr; /* Header buffer address */
 61	} read;
 62	struct {
 63		struct {
 64			union {
 65				__le32 data;
 66				struct {
 67					__le16 pkt_info; /*RSS type, Pkt type*/
 68					/* Split Header, header buffer len */
 69					__le16 hdr_info;
 70				} hs_rss;
 71			} lo_dword;
 72			union {
 73				__le32 rss; /* RSS Hash */
 74				struct {
 75					__le16 ip_id; /* IP id */
 76					__le16 csum; /* Packet Checksum */
 77				} csum_ip;
 78			} hi_dword;
 79		} lower;
 80		struct {
 81			__le32 status_error; /* ext status/error */
 82			__le16 length; /* Packet length */
 83			__le16 vlan; /* VLAN tag */
 84		} upper;
 85	} wb;  /* writeback */
 86};
 87
 88/* Additional Transmit Descriptor Control definitions */
 89#define IGC_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
 90#define IGC_TXDCTL_SWFLUSH	0x04000000 /* Transmit Software Flush */
 91
 92/* Additional Receive Descriptor Control definitions */
 93#define IGC_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
 94#define IGC_RXDCTL_SWFLUSH		0x04000000 /* Receive Software Flush */
 95
 96/* SRRCTL bit definitions */
 97#define IGC_SRRCTL_BSIZEPKT_MASK	GENMASK(6, 0)
 98#define IGC_SRRCTL_BSIZEPKT(x)		FIELD_PREP(IGC_SRRCTL_BSIZEPKT_MASK, \
 99					(x) / 1024) /* in 1 KB resolution */
100#define IGC_SRRCTL_BSIZEHDR_MASK	GENMASK(13, 8)
101#define IGC_SRRCTL_BSIZEHDR(x)		FIELD_PREP(IGC_SRRCTL_BSIZEHDR_MASK, \
102					(x) / 64) /* in 64 bytes resolution */
103#define IGC_SRRCTL_DESCTYPE_MASK	GENMASK(27, 25)
104#define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF	FIELD_PREP(IGC_SRRCTL_DESCTYPE_MASK, 1)
105
106#endif /* _IGC_BASE_H */