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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/uaccess.h>
11#include <uapi/linux/sched/types.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_irq.h>
17#include <drm/drm_prime.h>
18#include <drm/drm_of.h>
19#include <drm/drm_vblank.h>
20
21#include "msm_drv.h"
22#include "msm_debugfs.h"
23#include "msm_fence.h"
24#include "msm_gem.h"
25#include "msm_gpu.h"
26#include "msm_kms.h"
27#include "adreno/adreno_gpu.h"
28
29/*
30 * MSM driver version:
31 * - 1.0.0 - initial interface
32 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
33 * - 1.2.0 - adds explicit fence support for submit ioctl
34 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
35 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
36 * MSM_GEM_INFO ioctl.
37 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
38 * GEM object's debug name
39 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
40 * - 1.6.0 - Syncobj support
41 */
42#define MSM_VERSION_MAJOR 1
43#define MSM_VERSION_MINOR 6
44#define MSM_VERSION_PATCHLEVEL 0
45
46static const struct drm_mode_config_funcs mode_config_funcs = {
47 .fb_create = msm_framebuffer_create,
48 .output_poll_changed = drm_fb_helper_output_poll_changed,
49 .atomic_check = drm_atomic_helper_check,
50 .atomic_commit = drm_atomic_helper_commit,
51};
52
53static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
54 .atomic_commit_tail = msm_atomic_commit_tail,
55};
56
57#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
58static bool reglog = false;
59MODULE_PARM_DESC(reglog, "Enable register read/write logging");
60module_param(reglog, bool, 0600);
61#else
62#define reglog 0
63#endif
64
65#ifdef CONFIG_DRM_FBDEV_EMULATION
66static bool fbdev = true;
67MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
68module_param(fbdev, bool, 0600);
69#endif
70
71static char *vram = "16m";
72MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
73module_param(vram, charp, 0);
74
75bool dumpstate = false;
76MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
77module_param(dumpstate, bool, 0600);
78
79static bool modeset = true;
80MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
81module_param(modeset, bool, 0600);
82
83/*
84 * Util/helpers:
85 */
86
87struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
88 const char *name)
89{
90 int i;
91 char n[32];
92
93 snprintf(n, sizeof(n), "%s_clk", name);
94
95 for (i = 0; bulk && i < count; i++) {
96 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
97 return bulk[i].clk;
98 }
99
100
101 return NULL;
102}
103
104struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
105{
106 struct clk *clk;
107 char name2[32];
108
109 clk = devm_clk_get(&pdev->dev, name);
110 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
111 return clk;
112
113 snprintf(name2, sizeof(name2), "%s_clk", name);
114
115 clk = devm_clk_get(&pdev->dev, name2);
116 if (!IS_ERR(clk))
117 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
118 "\"%s\" instead of \"%s\"\n", name, name2);
119
120 return clk;
121}
122
123void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
124 const char *dbgname, bool quiet)
125{
126 struct resource *res;
127 unsigned long size;
128 void __iomem *ptr;
129
130 if (name)
131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
132 else
133 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
134
135 if (!res) {
136 if (!quiet)
137 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
138 return ERR_PTR(-EINVAL);
139 }
140
141 size = resource_size(res);
142
143 ptr = devm_ioremap(&pdev->dev, res->start, size);
144 if (!ptr) {
145 if (!quiet)
146 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
147 return ERR_PTR(-ENOMEM);
148 }
149
150 if (reglog)
151 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
152
153 return ptr;
154}
155
156void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
157 const char *dbgname)
158{
159 return _msm_ioremap(pdev, name, dbgname, false);
160}
161
162void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
163 const char *dbgname)
164{
165 return _msm_ioremap(pdev, name, dbgname, true);
166}
167
168void msm_writel(u32 data, void __iomem *addr)
169{
170 if (reglog)
171 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
172 writel(data, addr);
173}
174
175u32 msm_readl(const void __iomem *addr)
176{
177 u32 val = readl(addr);
178 if (reglog)
179 pr_err("IO:R %p %08x\n", addr, val);
180 return val;
181}
182
183struct msm_vblank_work {
184 struct work_struct work;
185 int crtc_id;
186 bool enable;
187 struct msm_drm_private *priv;
188};
189
190static void vblank_ctrl_worker(struct work_struct *work)
191{
192 struct msm_vblank_work *vbl_work = container_of(work,
193 struct msm_vblank_work, work);
194 struct msm_drm_private *priv = vbl_work->priv;
195 struct msm_kms *kms = priv->kms;
196
197 if (vbl_work->enable)
198 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
199 else
200 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
201
202 kfree(vbl_work);
203}
204
205static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
206 int crtc_id, bool enable)
207{
208 struct msm_vblank_work *vbl_work;
209
210 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
211 if (!vbl_work)
212 return -ENOMEM;
213
214 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
215
216 vbl_work->crtc_id = crtc_id;
217 vbl_work->enable = enable;
218 vbl_work->priv = priv;
219
220 queue_work(priv->wq, &vbl_work->work);
221
222 return 0;
223}
224
225static int msm_drm_uninit(struct device *dev)
226{
227 struct platform_device *pdev = to_platform_device(dev);
228 struct drm_device *ddev = platform_get_drvdata(pdev);
229 struct msm_drm_private *priv = ddev->dev_private;
230 struct msm_kms *kms = priv->kms;
231 struct msm_mdss *mdss = priv->mdss;
232 int i;
233
234 /*
235 * Shutdown the hw if we're far enough along where things might be on.
236 * If we run this too early, we'll end up panicking in any variety of
237 * places. Since we don't register the drm device until late in
238 * msm_drm_init, drm_dev->registered is used as an indicator that the
239 * shutdown will be successful.
240 */
241 if (ddev->registered) {
242 drm_dev_unregister(ddev);
243 drm_atomic_helper_shutdown(ddev);
244 }
245
246 /* We must cancel and cleanup any pending vblank enable/disable
247 * work before drm_irq_uninstall() to avoid work re-enabling an
248 * irq after uninstall has disabled it.
249 */
250
251 flush_workqueue(priv->wq);
252
253 /* clean up event worker threads */
254 for (i = 0; i < priv->num_crtcs; i++) {
255 if (priv->event_thread[i].worker)
256 kthread_destroy_worker(priv->event_thread[i].worker);
257 }
258
259 msm_gem_shrinker_cleanup(ddev);
260
261 drm_kms_helper_poll_fini(ddev);
262
263 msm_perf_debugfs_cleanup(priv);
264 msm_rd_debugfs_cleanup(priv);
265
266#ifdef CONFIG_DRM_FBDEV_EMULATION
267 if (fbdev && priv->fbdev)
268 msm_fbdev_free(ddev);
269#endif
270
271 drm_mode_config_cleanup(ddev);
272
273 pm_runtime_get_sync(dev);
274 drm_irq_uninstall(ddev);
275 pm_runtime_put_sync(dev);
276
277 if (kms && kms->funcs)
278 kms->funcs->destroy(kms);
279
280 if (priv->vram.paddr) {
281 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
282 drm_mm_takedown(&priv->vram.mm);
283 dma_free_attrs(dev, priv->vram.size, NULL,
284 priv->vram.paddr, attrs);
285 }
286
287 component_unbind_all(dev, ddev);
288
289 if (mdss && mdss->funcs)
290 mdss->funcs->destroy(ddev);
291
292 ddev->dev_private = NULL;
293 drm_dev_put(ddev);
294
295 destroy_workqueue(priv->wq);
296 kfree(priv);
297
298 return 0;
299}
300
301#define KMS_MDP4 4
302#define KMS_MDP5 5
303#define KMS_DPU 3
304
305static int get_mdp_ver(struct platform_device *pdev)
306{
307 struct device *dev = &pdev->dev;
308
309 return (int) (unsigned long) of_device_get_match_data(dev);
310}
311
312#include <linux/of_address.h>
313
314bool msm_use_mmu(struct drm_device *dev)
315{
316 struct msm_drm_private *priv = dev->dev_private;
317
318 /* a2xx comes with its own MMU */
319 return priv->is_a2xx || iommu_present(&platform_bus_type);
320}
321
322static int msm_init_vram(struct drm_device *dev)
323{
324 struct msm_drm_private *priv = dev->dev_private;
325 struct device_node *node;
326 unsigned long size = 0;
327 int ret = 0;
328
329 /* In the device-tree world, we could have a 'memory-region'
330 * phandle, which gives us a link to our "vram". Allocating
331 * is all nicely abstracted behind the dma api, but we need
332 * to know the entire size to allocate it all in one go. There
333 * are two cases:
334 * 1) device with no IOMMU, in which case we need exclusive
335 * access to a VRAM carveout big enough for all gpu
336 * buffers
337 * 2) device with IOMMU, but where the bootloader puts up
338 * a splash screen. In this case, the VRAM carveout
339 * need only be large enough for fbdev fb. But we need
340 * exclusive access to the buffer to avoid the kernel
341 * using those pages for other purposes (which appears
342 * as corruption on screen before we have a chance to
343 * load and do initial modeset)
344 */
345
346 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
347 if (node) {
348 struct resource r;
349 ret = of_address_to_resource(node, 0, &r);
350 of_node_put(node);
351 if (ret)
352 return ret;
353 size = r.end - r.start;
354 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
355
356 /* if we have no IOMMU, then we need to use carveout allocator.
357 * Grab the entire CMA chunk carved out in early startup in
358 * mach-msm:
359 */
360 } else if (!msm_use_mmu(dev)) {
361 DRM_INFO("using %s VRAM carveout\n", vram);
362 size = memparse(vram, NULL);
363 }
364
365 if (size) {
366 unsigned long attrs = 0;
367 void *p;
368
369 priv->vram.size = size;
370
371 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
372 spin_lock_init(&priv->vram.lock);
373
374 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
375 attrs |= DMA_ATTR_WRITE_COMBINE;
376
377 /* note that for no-kernel-mapping, the vaddr returned
378 * is bogus, but non-null if allocation succeeded:
379 */
380 p = dma_alloc_attrs(dev->dev, size,
381 &priv->vram.paddr, GFP_KERNEL, attrs);
382 if (!p) {
383 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
384 priv->vram.paddr = 0;
385 return -ENOMEM;
386 }
387
388 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
389 (uint32_t)priv->vram.paddr,
390 (uint32_t)(priv->vram.paddr + size));
391 }
392
393 return ret;
394}
395
396static int msm_drm_init(struct device *dev, struct drm_driver *drv)
397{
398 struct platform_device *pdev = to_platform_device(dev);
399 struct drm_device *ddev;
400 struct msm_drm_private *priv;
401 struct msm_kms *kms;
402 struct msm_mdss *mdss;
403 int ret, i;
404
405 ddev = drm_dev_alloc(drv, dev);
406 if (IS_ERR(ddev)) {
407 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
408 return PTR_ERR(ddev);
409 }
410
411 platform_set_drvdata(pdev, ddev);
412
413 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
414 if (!priv) {
415 ret = -ENOMEM;
416 goto err_put_drm_dev;
417 }
418
419 ddev->dev_private = priv;
420 priv->dev = ddev;
421
422 switch (get_mdp_ver(pdev)) {
423 case KMS_MDP5:
424 ret = mdp5_mdss_init(ddev);
425 break;
426 case KMS_DPU:
427 ret = dpu_mdss_init(ddev);
428 break;
429 default:
430 ret = 0;
431 break;
432 }
433 if (ret)
434 goto err_free_priv;
435
436 mdss = priv->mdss;
437
438 priv->wq = alloc_ordered_workqueue("msm", 0);
439
440 INIT_WORK(&priv->free_work, msm_gem_free_work);
441 init_llist_head(&priv->free_list);
442
443 INIT_LIST_HEAD(&priv->inactive_list);
444
445 drm_mode_config_init(ddev);
446
447 /* Bind all our sub-components: */
448 ret = component_bind_all(dev, ddev);
449 if (ret)
450 goto err_destroy_mdss;
451
452 ret = msm_init_vram(ddev);
453 if (ret)
454 goto err_msm_uninit;
455
456 if (!dev->dma_parms) {
457 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
458 GFP_KERNEL);
459 if (!dev->dma_parms) {
460 ret = -ENOMEM;
461 goto err_msm_uninit;
462 }
463 }
464 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
465
466 msm_gem_shrinker_init(ddev);
467
468 switch (get_mdp_ver(pdev)) {
469 case KMS_MDP4:
470 kms = mdp4_kms_init(ddev);
471 priv->kms = kms;
472 break;
473 case KMS_MDP5:
474 kms = mdp5_kms_init(ddev);
475 break;
476 case KMS_DPU:
477 kms = dpu_kms_init(ddev);
478 priv->kms = kms;
479 break;
480 default:
481 /* valid only for the dummy headless case, where of_node=NULL */
482 WARN_ON(dev->of_node);
483 kms = NULL;
484 break;
485 }
486
487 if (IS_ERR(kms)) {
488 DRM_DEV_ERROR(dev, "failed to load kms\n");
489 ret = PTR_ERR(kms);
490 priv->kms = NULL;
491 goto err_msm_uninit;
492 }
493
494 /* Enable normalization of plane zpos */
495 ddev->mode_config.normalize_zpos = true;
496
497 if (kms) {
498 kms->dev = ddev;
499 ret = kms->funcs->hw_init(kms);
500 if (ret) {
501 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
502 goto err_msm_uninit;
503 }
504 }
505
506 ddev->mode_config.funcs = &mode_config_funcs;
507 ddev->mode_config.helper_private = &mode_config_helper_funcs;
508
509 for (i = 0; i < priv->num_crtcs; i++) {
510 /* initialize event thread */
511 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
512 priv->event_thread[i].dev = ddev;
513 priv->event_thread[i].worker = kthread_create_worker(0,
514 "crtc_event:%d", priv->event_thread[i].crtc_id);
515 if (IS_ERR(priv->event_thread[i].worker)) {
516 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
517 goto err_msm_uninit;
518 }
519
520 sched_set_fifo(priv->event_thread[i].worker->task);
521 }
522
523 ret = drm_vblank_init(ddev, priv->num_crtcs);
524 if (ret < 0) {
525 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
526 goto err_msm_uninit;
527 }
528
529 if (kms) {
530 pm_runtime_get_sync(dev);
531 ret = drm_irq_install(ddev, kms->irq);
532 pm_runtime_put_sync(dev);
533 if (ret < 0) {
534 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
535 goto err_msm_uninit;
536 }
537 }
538
539 ret = drm_dev_register(ddev, 0);
540 if (ret)
541 goto err_msm_uninit;
542
543 drm_mode_config_reset(ddev);
544
545#ifdef CONFIG_DRM_FBDEV_EMULATION
546 if (kms && fbdev)
547 priv->fbdev = msm_fbdev_init(ddev);
548#endif
549
550 ret = msm_debugfs_late_init(ddev);
551 if (ret)
552 goto err_msm_uninit;
553
554 drm_kms_helper_poll_init(ddev);
555
556 return 0;
557
558err_msm_uninit:
559 msm_drm_uninit(dev);
560 return ret;
561err_destroy_mdss:
562 if (mdss && mdss->funcs)
563 mdss->funcs->destroy(ddev);
564err_free_priv:
565 kfree(priv);
566err_put_drm_dev:
567 drm_dev_put(ddev);
568 return ret;
569}
570
571/*
572 * DRM operations:
573 */
574
575static void load_gpu(struct drm_device *dev)
576{
577 static DEFINE_MUTEX(init_lock);
578 struct msm_drm_private *priv = dev->dev_private;
579
580 mutex_lock(&init_lock);
581
582 if (!priv->gpu)
583 priv->gpu = adreno_load_gpu(dev);
584
585 mutex_unlock(&init_lock);
586}
587
588static int context_init(struct drm_device *dev, struct drm_file *file)
589{
590 struct msm_drm_private *priv = dev->dev_private;
591 struct msm_file_private *ctx;
592
593 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
594 if (!ctx)
595 return -ENOMEM;
596
597 msm_submitqueue_init(dev, ctx);
598
599 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
600 file->driver_priv = ctx;
601
602 return 0;
603}
604
605static int msm_open(struct drm_device *dev, struct drm_file *file)
606{
607 /* For now, load gpu on open.. to avoid the requirement of having
608 * firmware in the initrd.
609 */
610 load_gpu(dev);
611
612 return context_init(dev, file);
613}
614
615static void context_close(struct msm_file_private *ctx)
616{
617 msm_submitqueue_close(ctx);
618 kfree(ctx);
619}
620
621static void msm_postclose(struct drm_device *dev, struct drm_file *file)
622{
623 struct msm_drm_private *priv = dev->dev_private;
624 struct msm_file_private *ctx = file->driver_priv;
625
626 mutex_lock(&dev->struct_mutex);
627 if (ctx == priv->lastctx)
628 priv->lastctx = NULL;
629 mutex_unlock(&dev->struct_mutex);
630
631 context_close(ctx);
632}
633
634static irqreturn_t msm_irq(int irq, void *arg)
635{
636 struct drm_device *dev = arg;
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
639 BUG_ON(!kms);
640 return kms->funcs->irq(kms);
641}
642
643static void msm_irq_preinstall(struct drm_device *dev)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_kms *kms = priv->kms;
647 BUG_ON(!kms);
648 kms->funcs->irq_preinstall(kms);
649}
650
651static int msm_irq_postinstall(struct drm_device *dev)
652{
653 struct msm_drm_private *priv = dev->dev_private;
654 struct msm_kms *kms = priv->kms;
655 BUG_ON(!kms);
656
657 if (kms->funcs->irq_postinstall)
658 return kms->funcs->irq_postinstall(kms);
659
660 return 0;
661}
662
663static void msm_irq_uninstall(struct drm_device *dev)
664{
665 struct msm_drm_private *priv = dev->dev_private;
666 struct msm_kms *kms = priv->kms;
667 BUG_ON(!kms);
668 kms->funcs->irq_uninstall(kms);
669}
670
671int msm_crtc_enable_vblank(struct drm_crtc *crtc)
672{
673 struct drm_device *dev = crtc->dev;
674 unsigned int pipe = crtc->index;
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
677 if (!kms)
678 return -ENXIO;
679 DBG("dev=%p, crtc=%u", dev, pipe);
680 return vblank_ctrl_queue_work(priv, pipe, true);
681}
682
683void msm_crtc_disable_vblank(struct drm_crtc *crtc)
684{
685 struct drm_device *dev = crtc->dev;
686 unsigned int pipe = crtc->index;
687 struct msm_drm_private *priv = dev->dev_private;
688 struct msm_kms *kms = priv->kms;
689 if (!kms)
690 return;
691 DBG("dev=%p, crtc=%u", dev, pipe);
692 vblank_ctrl_queue_work(priv, pipe, false);
693}
694
695/*
696 * DRM ioctls:
697 */
698
699static int msm_ioctl_get_param(struct drm_device *dev, void *data,
700 struct drm_file *file)
701{
702 struct msm_drm_private *priv = dev->dev_private;
703 struct drm_msm_param *args = data;
704 struct msm_gpu *gpu;
705
706 /* for now, we just have 3d pipe.. eventually this would need to
707 * be more clever to dispatch to appropriate gpu module:
708 */
709 if (args->pipe != MSM_PIPE_3D0)
710 return -EINVAL;
711
712 gpu = priv->gpu;
713
714 if (!gpu)
715 return -ENXIO;
716
717 return gpu->funcs->get_param(gpu, args->param, &args->value);
718}
719
720static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
721 struct drm_file *file)
722{
723 struct drm_msm_gem_new *args = data;
724
725 if (args->flags & ~MSM_BO_FLAGS) {
726 DRM_ERROR("invalid flags: %08x\n", args->flags);
727 return -EINVAL;
728 }
729
730 return msm_gem_new_handle(dev, file, args->size,
731 args->flags, &args->handle, NULL);
732}
733
734static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
735{
736 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
737}
738
739static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
740 struct drm_file *file)
741{
742 struct drm_msm_gem_cpu_prep *args = data;
743 struct drm_gem_object *obj;
744 ktime_t timeout = to_ktime(args->timeout);
745 int ret;
746
747 if (args->op & ~MSM_PREP_FLAGS) {
748 DRM_ERROR("invalid op: %08x\n", args->op);
749 return -EINVAL;
750 }
751
752 obj = drm_gem_object_lookup(file, args->handle);
753 if (!obj)
754 return -ENOENT;
755
756 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
757
758 drm_gem_object_put(obj);
759
760 return ret;
761}
762
763static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
764 struct drm_file *file)
765{
766 struct drm_msm_gem_cpu_fini *args = data;
767 struct drm_gem_object *obj;
768 int ret;
769
770 obj = drm_gem_object_lookup(file, args->handle);
771 if (!obj)
772 return -ENOENT;
773
774 ret = msm_gem_cpu_fini(obj);
775
776 drm_gem_object_put(obj);
777
778 return ret;
779}
780
781static int msm_ioctl_gem_info_iova(struct drm_device *dev,
782 struct drm_gem_object *obj, uint64_t *iova)
783{
784 struct msm_drm_private *priv = dev->dev_private;
785
786 if (!priv->gpu)
787 return -EINVAL;
788
789 /*
790 * Don't pin the memory here - just get an address so that userspace can
791 * be productive
792 */
793 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
794}
795
796static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
797 struct drm_file *file)
798{
799 struct drm_msm_gem_info *args = data;
800 struct drm_gem_object *obj;
801 struct msm_gem_object *msm_obj;
802 int i, ret = 0;
803
804 if (args->pad)
805 return -EINVAL;
806
807 switch (args->info) {
808 case MSM_INFO_GET_OFFSET:
809 case MSM_INFO_GET_IOVA:
810 /* value returned as immediate, not pointer, so len==0: */
811 if (args->len)
812 return -EINVAL;
813 break;
814 case MSM_INFO_SET_NAME:
815 case MSM_INFO_GET_NAME:
816 break;
817 default:
818 return -EINVAL;
819 }
820
821 obj = drm_gem_object_lookup(file, args->handle);
822 if (!obj)
823 return -ENOENT;
824
825 msm_obj = to_msm_bo(obj);
826
827 switch (args->info) {
828 case MSM_INFO_GET_OFFSET:
829 args->value = msm_gem_mmap_offset(obj);
830 break;
831 case MSM_INFO_GET_IOVA:
832 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
833 break;
834 case MSM_INFO_SET_NAME:
835 /* length check should leave room for terminating null: */
836 if (args->len >= sizeof(msm_obj->name)) {
837 ret = -EINVAL;
838 break;
839 }
840 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
841 args->len)) {
842 msm_obj->name[0] = '\0';
843 ret = -EFAULT;
844 break;
845 }
846 msm_obj->name[args->len] = '\0';
847 for (i = 0; i < args->len; i++) {
848 if (!isprint(msm_obj->name[i])) {
849 msm_obj->name[i] = '\0';
850 break;
851 }
852 }
853 break;
854 case MSM_INFO_GET_NAME:
855 if (args->value && (args->len < strlen(msm_obj->name))) {
856 ret = -EINVAL;
857 break;
858 }
859 args->len = strlen(msm_obj->name);
860 if (args->value) {
861 if (copy_to_user(u64_to_user_ptr(args->value),
862 msm_obj->name, args->len))
863 ret = -EFAULT;
864 }
865 break;
866 }
867
868 drm_gem_object_put(obj);
869
870 return ret;
871}
872
873static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
874 struct drm_file *file)
875{
876 struct msm_drm_private *priv = dev->dev_private;
877 struct drm_msm_wait_fence *args = data;
878 ktime_t timeout = to_ktime(args->timeout);
879 struct msm_gpu_submitqueue *queue;
880 struct msm_gpu *gpu = priv->gpu;
881 int ret;
882
883 if (args->pad) {
884 DRM_ERROR("invalid pad: %08x\n", args->pad);
885 return -EINVAL;
886 }
887
888 if (!gpu)
889 return 0;
890
891 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
892 if (!queue)
893 return -ENOENT;
894
895 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
896 true);
897
898 msm_submitqueue_put(queue);
899 return ret;
900}
901
902static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
903 struct drm_file *file)
904{
905 struct drm_msm_gem_madvise *args = data;
906 struct drm_gem_object *obj;
907 int ret;
908
909 switch (args->madv) {
910 case MSM_MADV_DONTNEED:
911 case MSM_MADV_WILLNEED:
912 break;
913 default:
914 return -EINVAL;
915 }
916
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
918 if (ret)
919 return ret;
920
921 obj = drm_gem_object_lookup(file, args->handle);
922 if (!obj) {
923 ret = -ENOENT;
924 goto unlock;
925 }
926
927 ret = msm_gem_madvise(obj, args->madv);
928 if (ret >= 0) {
929 args->retained = ret;
930 ret = 0;
931 }
932
933 drm_gem_object_put_locked(obj);
934
935unlock:
936 mutex_unlock(&dev->struct_mutex);
937 return ret;
938}
939
940
941static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
942 struct drm_file *file)
943{
944 struct drm_msm_submitqueue *args = data;
945
946 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
947 return -EINVAL;
948
949 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
950 args->flags, &args->id);
951}
952
953static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
954 struct drm_file *file)
955{
956 return msm_submitqueue_query(dev, file->driver_priv, data);
957}
958
959static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
960 struct drm_file *file)
961{
962 u32 id = *(u32 *) data;
963
964 return msm_submitqueue_remove(file->driver_priv, id);
965}
966
967static const struct drm_ioctl_desc msm_ioctls[] = {
968 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
969 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
971 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
973 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
974 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
975 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
977 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
979};
980
981static const struct vm_operations_struct vm_ops = {
982 .fault = msm_gem_fault,
983 .open = drm_gem_vm_open,
984 .close = drm_gem_vm_close,
985};
986
987static const struct file_operations fops = {
988 .owner = THIS_MODULE,
989 .open = drm_open,
990 .release = drm_release,
991 .unlocked_ioctl = drm_ioctl,
992 .compat_ioctl = drm_compat_ioctl,
993 .poll = drm_poll,
994 .read = drm_read,
995 .llseek = no_llseek,
996 .mmap = msm_gem_mmap,
997};
998
999static struct drm_driver msm_driver = {
1000 .driver_features = DRIVER_GEM |
1001 DRIVER_RENDER |
1002 DRIVER_ATOMIC |
1003 DRIVER_MODESET |
1004 DRIVER_SYNCOBJ,
1005 .open = msm_open,
1006 .postclose = msm_postclose,
1007 .lastclose = drm_fb_helper_lastclose,
1008 .irq_handler = msm_irq,
1009 .irq_preinstall = msm_irq_preinstall,
1010 .irq_postinstall = msm_irq_postinstall,
1011 .irq_uninstall = msm_irq_uninstall,
1012 .gem_free_object_unlocked = msm_gem_free_object,
1013 .gem_vm_ops = &vm_ops,
1014 .dumb_create = msm_gem_dumb_create,
1015 .dumb_map_offset = msm_gem_dumb_map_offset,
1016 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1017 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1018 .gem_prime_pin = msm_gem_prime_pin,
1019 .gem_prime_unpin = msm_gem_prime_unpin,
1020 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1021 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1022 .gem_prime_vmap = msm_gem_prime_vmap,
1023 .gem_prime_vunmap = msm_gem_prime_vunmap,
1024 .gem_prime_mmap = msm_gem_prime_mmap,
1025#ifdef CONFIG_DEBUG_FS
1026 .debugfs_init = msm_debugfs_init,
1027#endif
1028 .ioctls = msm_ioctls,
1029 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1030 .fops = &fops,
1031 .name = "msm",
1032 .desc = "MSM Snapdragon DRM",
1033 .date = "20130625",
1034 .major = MSM_VERSION_MAJOR,
1035 .minor = MSM_VERSION_MINOR,
1036 .patchlevel = MSM_VERSION_PATCHLEVEL,
1037};
1038
1039static int __maybe_unused msm_runtime_suspend(struct device *dev)
1040{
1041 struct drm_device *ddev = dev_get_drvdata(dev);
1042 struct msm_drm_private *priv = ddev->dev_private;
1043 struct msm_mdss *mdss = priv->mdss;
1044
1045 DBG("");
1046
1047 if (mdss && mdss->funcs)
1048 return mdss->funcs->disable(mdss);
1049
1050 return 0;
1051}
1052
1053static int __maybe_unused msm_runtime_resume(struct device *dev)
1054{
1055 struct drm_device *ddev = dev_get_drvdata(dev);
1056 struct msm_drm_private *priv = ddev->dev_private;
1057 struct msm_mdss *mdss = priv->mdss;
1058
1059 DBG("");
1060
1061 if (mdss && mdss->funcs)
1062 return mdss->funcs->enable(mdss);
1063
1064 return 0;
1065}
1066
1067static int __maybe_unused msm_pm_suspend(struct device *dev)
1068{
1069
1070 if (pm_runtime_suspended(dev))
1071 return 0;
1072
1073 return msm_runtime_suspend(dev);
1074}
1075
1076static int __maybe_unused msm_pm_resume(struct device *dev)
1077{
1078 if (pm_runtime_suspended(dev))
1079 return 0;
1080
1081 return msm_runtime_resume(dev);
1082}
1083
1084static int __maybe_unused msm_pm_prepare(struct device *dev)
1085{
1086 struct drm_device *ddev = dev_get_drvdata(dev);
1087
1088 return drm_mode_config_helper_suspend(ddev);
1089}
1090
1091static void __maybe_unused msm_pm_complete(struct device *dev)
1092{
1093 struct drm_device *ddev = dev_get_drvdata(dev);
1094
1095 drm_mode_config_helper_resume(ddev);
1096}
1097
1098static const struct dev_pm_ops msm_pm_ops = {
1099 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1100 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1101 .prepare = msm_pm_prepare,
1102 .complete = msm_pm_complete,
1103};
1104
1105/*
1106 * Componentized driver support:
1107 */
1108
1109/*
1110 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1111 * so probably some room for some helpers
1112 */
1113static int compare_of(struct device *dev, void *data)
1114{
1115 return dev->of_node == data;
1116}
1117
1118/*
1119 * Identify what components need to be added by parsing what remote-endpoints
1120 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1121 * is no external component that we need to add since LVDS is within MDP4
1122 * itself.
1123 */
1124static int add_components_mdp(struct device *mdp_dev,
1125 struct component_match **matchptr)
1126{
1127 struct device_node *np = mdp_dev->of_node;
1128 struct device_node *ep_node;
1129 struct device *master_dev;
1130
1131 /*
1132 * on MDP4 based platforms, the MDP platform device is the component
1133 * master that adds other display interface components to itself.
1134 *
1135 * on MDP5 based platforms, the MDSS platform device is the component
1136 * master that adds MDP5 and other display interface components to
1137 * itself.
1138 */
1139 if (of_device_is_compatible(np, "qcom,mdp4"))
1140 master_dev = mdp_dev;
1141 else
1142 master_dev = mdp_dev->parent;
1143
1144 for_each_endpoint_of_node(np, ep_node) {
1145 struct device_node *intf;
1146 struct of_endpoint ep;
1147 int ret;
1148
1149 ret = of_graph_parse_endpoint(ep_node, &ep);
1150 if (ret) {
1151 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1152 of_node_put(ep_node);
1153 return ret;
1154 }
1155
1156 /*
1157 * The LCDC/LVDS port on MDP4 is a speacial case where the
1158 * remote-endpoint isn't a component that we need to add
1159 */
1160 if (of_device_is_compatible(np, "qcom,mdp4") &&
1161 ep.port == 0)
1162 continue;
1163
1164 /*
1165 * It's okay if some of the ports don't have a remote endpoint
1166 * specified. It just means that the port isn't connected to
1167 * any external interface.
1168 */
1169 intf = of_graph_get_remote_port_parent(ep_node);
1170 if (!intf)
1171 continue;
1172
1173 if (of_device_is_available(intf))
1174 drm_of_component_match_add(master_dev, matchptr,
1175 compare_of, intf);
1176
1177 of_node_put(intf);
1178 }
1179
1180 return 0;
1181}
1182
1183static int compare_name_mdp(struct device *dev, void *data)
1184{
1185 return (strstr(dev_name(dev), "mdp") != NULL);
1186}
1187
1188static int add_display_components(struct device *dev,
1189 struct component_match **matchptr)
1190{
1191 struct device *mdp_dev;
1192 int ret;
1193
1194 /*
1195 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1196 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1197 * Populate the children devices, find the MDP5/DPU node, and then add
1198 * the interfaces to our components list.
1199 */
1200 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1201 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
1202 of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
1203 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1204 if (ret) {
1205 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1206 return ret;
1207 }
1208
1209 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1210 if (!mdp_dev) {
1211 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1212 of_platform_depopulate(dev);
1213 return -ENODEV;
1214 }
1215
1216 put_device(mdp_dev);
1217
1218 /* add the MDP component itself */
1219 drm_of_component_match_add(dev, matchptr, compare_of,
1220 mdp_dev->of_node);
1221 } else {
1222 /* MDP4 */
1223 mdp_dev = dev;
1224 }
1225
1226 ret = add_components_mdp(mdp_dev, matchptr);
1227 if (ret)
1228 of_platform_depopulate(dev);
1229
1230 return ret;
1231}
1232
1233/*
1234 * We don't know what's the best binding to link the gpu with the drm device.
1235 * Fow now, we just hunt for all the possible gpus that we support, and add them
1236 * as components.
1237 */
1238static const struct of_device_id msm_gpu_match[] = {
1239 { .compatible = "qcom,adreno" },
1240 { .compatible = "qcom,adreno-3xx" },
1241 { .compatible = "amd,imageon" },
1242 { .compatible = "qcom,kgsl-3d0" },
1243 { },
1244};
1245
1246static int add_gpu_components(struct device *dev,
1247 struct component_match **matchptr)
1248{
1249 struct device_node *np;
1250
1251 np = of_find_matching_node(NULL, msm_gpu_match);
1252 if (!np)
1253 return 0;
1254
1255 if (of_device_is_available(np))
1256 drm_of_component_match_add(dev, matchptr, compare_of, np);
1257
1258 of_node_put(np);
1259
1260 return 0;
1261}
1262
1263static int msm_drm_bind(struct device *dev)
1264{
1265 return msm_drm_init(dev, &msm_driver);
1266}
1267
1268static void msm_drm_unbind(struct device *dev)
1269{
1270 msm_drm_uninit(dev);
1271}
1272
1273static const struct component_master_ops msm_drm_ops = {
1274 .bind = msm_drm_bind,
1275 .unbind = msm_drm_unbind,
1276};
1277
1278/*
1279 * Platform driver:
1280 */
1281
1282static int msm_pdev_probe(struct platform_device *pdev)
1283{
1284 struct component_match *match = NULL;
1285 int ret;
1286
1287 if (get_mdp_ver(pdev)) {
1288 ret = add_display_components(&pdev->dev, &match);
1289 if (ret)
1290 return ret;
1291 }
1292
1293 ret = add_gpu_components(&pdev->dev, &match);
1294 if (ret)
1295 goto fail;
1296
1297 /* on all devices that I am aware of, iommu's which can map
1298 * any address the cpu can see are used:
1299 */
1300 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1301 if (ret)
1302 goto fail;
1303
1304 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1305 if (ret)
1306 goto fail;
1307
1308 return 0;
1309
1310fail:
1311 of_platform_depopulate(&pdev->dev);
1312 return ret;
1313}
1314
1315static int msm_pdev_remove(struct platform_device *pdev)
1316{
1317 component_master_del(&pdev->dev, &msm_drm_ops);
1318 of_platform_depopulate(&pdev->dev);
1319
1320 return 0;
1321}
1322
1323static void msm_pdev_shutdown(struct platform_device *pdev)
1324{
1325 struct drm_device *drm = platform_get_drvdata(pdev);
1326
1327 drm_atomic_helper_shutdown(drm);
1328}
1329
1330static const struct of_device_id dt_match[] = {
1331 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1332 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1333 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1334 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1335 {}
1336};
1337MODULE_DEVICE_TABLE(of, dt_match);
1338
1339static struct platform_driver msm_platform_driver = {
1340 .probe = msm_pdev_probe,
1341 .remove = msm_pdev_remove,
1342 .shutdown = msm_pdev_shutdown,
1343 .driver = {
1344 .name = "msm",
1345 .of_match_table = dt_match,
1346 .pm = &msm_pm_ops,
1347 },
1348};
1349
1350static int __init msm_drm_register(void)
1351{
1352 if (!modeset)
1353 return -EINVAL;
1354
1355 DBG("init");
1356 msm_mdp_register();
1357 msm_dpu_register();
1358 msm_dsi_register();
1359 msm_edp_register();
1360 msm_hdmi_register();
1361 adreno_register();
1362 return platform_driver_register(&msm_platform_driver);
1363}
1364
1365static void __exit msm_drm_unregister(void)
1366{
1367 DBG("fini");
1368 platform_driver_unregister(&msm_platform_driver);
1369 msm_hdmi_unregister();
1370 adreno_unregister();
1371 msm_edp_unregister();
1372 msm_dsi_unregister();
1373 msm_mdp_unregister();
1374 msm_dpu_unregister();
1375}
1376
1377module_init(msm_drm_register);
1378module_exit(msm_drm_unregister);
1379
1380MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1381MODULE_DESCRIPTION("MSM DRM Driver");
1382MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <drm/drm_of.h>
19
20#include "msm_drv.h"
21#include "msm_debugfs.h"
22#include "msm_fence.h"
23#include "msm_gpu.h"
24#include "msm_kms.h"
25
26
27/*
28 * MSM driver version:
29 * - 1.0.0 - initial interface
30 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
31 * - 1.2.0 - adds explicit fence support for submit ioctl
32 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
33 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
34 * MSM_GEM_INFO ioctl.
35 */
36#define MSM_VERSION_MAJOR 1
37#define MSM_VERSION_MINOR 3
38#define MSM_VERSION_PATCHLEVEL 0
39
40static const struct drm_mode_config_funcs mode_config_funcs = {
41 .fb_create = msm_framebuffer_create,
42 .output_poll_changed = drm_fb_helper_output_poll_changed,
43 .atomic_check = drm_atomic_helper_check,
44 .atomic_commit = msm_atomic_commit,
45 .atomic_state_alloc = msm_atomic_state_alloc,
46 .atomic_state_clear = msm_atomic_state_clear,
47 .atomic_state_free = msm_atomic_state_free,
48};
49
50#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
51static bool reglog = false;
52MODULE_PARM_DESC(reglog, "Enable register read/write logging");
53module_param(reglog, bool, 0600);
54#else
55#define reglog 0
56#endif
57
58#ifdef CONFIG_DRM_FBDEV_EMULATION
59static bool fbdev = true;
60MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
61module_param(fbdev, bool, 0600);
62#endif
63
64static char *vram = "16m";
65MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
66module_param(vram, charp, 0);
67
68bool dumpstate = false;
69MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
70module_param(dumpstate, bool, 0600);
71
72static bool modeset = true;
73MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
74module_param(modeset, bool, 0600);
75
76/*
77 * Util/helpers:
78 */
79
80struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
81{
82 struct clk *clk;
83 char name2[32];
84
85 clk = devm_clk_get(&pdev->dev, name);
86 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
87 return clk;
88
89 snprintf(name2, sizeof(name2), "%s_clk", name);
90
91 clk = devm_clk_get(&pdev->dev, name2);
92 if (!IS_ERR(clk))
93 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
94 "\"%s\" instead of \"%s\"\n", name, name2);
95
96 return clk;
97}
98
99void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
100 const char *dbgname)
101{
102 struct resource *res;
103 unsigned long size;
104 void __iomem *ptr;
105
106 if (name)
107 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
108 else
109 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110
111 if (!res) {
112 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
113 return ERR_PTR(-EINVAL);
114 }
115
116 size = resource_size(res);
117
118 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
119 if (!ptr) {
120 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
121 return ERR_PTR(-ENOMEM);
122 }
123
124 if (reglog)
125 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
126
127 return ptr;
128}
129
130void msm_writel(u32 data, void __iomem *addr)
131{
132 if (reglog)
133 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
134 writel(data, addr);
135}
136
137u32 msm_readl(const void __iomem *addr)
138{
139 u32 val = readl(addr);
140 if (reglog)
141 pr_err("IO:R %p %08x\n", addr, val);
142 return val;
143}
144
145struct vblank_event {
146 struct list_head node;
147 int crtc_id;
148 bool enable;
149};
150
151static void vblank_ctrl_worker(struct work_struct *work)
152{
153 struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
154 struct msm_vblank_ctrl, work);
155 struct msm_drm_private *priv = container_of(vbl_ctrl,
156 struct msm_drm_private, vblank_ctrl);
157 struct msm_kms *kms = priv->kms;
158 struct vblank_event *vbl_ev, *tmp;
159 unsigned long flags;
160
161 spin_lock_irqsave(&vbl_ctrl->lock, flags);
162 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
163 list_del(&vbl_ev->node);
164 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
165
166 if (vbl_ev->enable)
167 kms->funcs->enable_vblank(kms,
168 priv->crtcs[vbl_ev->crtc_id]);
169 else
170 kms->funcs->disable_vblank(kms,
171 priv->crtcs[vbl_ev->crtc_id]);
172
173 kfree(vbl_ev);
174
175 spin_lock_irqsave(&vbl_ctrl->lock, flags);
176 }
177
178 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
179}
180
181static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
182 int crtc_id, bool enable)
183{
184 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
185 struct vblank_event *vbl_ev;
186 unsigned long flags;
187
188 vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
189 if (!vbl_ev)
190 return -ENOMEM;
191
192 vbl_ev->crtc_id = crtc_id;
193 vbl_ev->enable = enable;
194
195 spin_lock_irqsave(&vbl_ctrl->lock, flags);
196 list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
197 spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
198
199 queue_work(priv->wq, &vbl_ctrl->work);
200
201 return 0;
202}
203
204static int msm_drm_uninit(struct device *dev)
205{
206 struct platform_device *pdev = to_platform_device(dev);
207 struct drm_device *ddev = platform_get_drvdata(pdev);
208 struct msm_drm_private *priv = ddev->dev_private;
209 struct msm_kms *kms = priv->kms;
210 struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
211 struct vblank_event *vbl_ev, *tmp;
212
213 /* We must cancel and cleanup any pending vblank enable/disable
214 * work before drm_irq_uninstall() to avoid work re-enabling an
215 * irq after uninstall has disabled it.
216 */
217 cancel_work_sync(&vbl_ctrl->work);
218 list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
219 list_del(&vbl_ev->node);
220 kfree(vbl_ev);
221 }
222
223 msm_gem_shrinker_cleanup(ddev);
224
225 drm_kms_helper_poll_fini(ddev);
226
227 drm_dev_unregister(ddev);
228
229 msm_perf_debugfs_cleanup(priv);
230 msm_rd_debugfs_cleanup(priv);
231
232#ifdef CONFIG_DRM_FBDEV_EMULATION
233 if (fbdev && priv->fbdev)
234 msm_fbdev_free(ddev);
235#endif
236 drm_mode_config_cleanup(ddev);
237
238 pm_runtime_get_sync(dev);
239 drm_irq_uninstall(ddev);
240 pm_runtime_put_sync(dev);
241
242 flush_workqueue(priv->wq);
243 destroy_workqueue(priv->wq);
244
245 flush_workqueue(priv->atomic_wq);
246 destroy_workqueue(priv->atomic_wq);
247
248 if (kms && kms->funcs)
249 kms->funcs->destroy(kms);
250
251 if (priv->vram.paddr) {
252 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
253 drm_mm_takedown(&priv->vram.mm);
254 dma_free_attrs(dev, priv->vram.size, NULL,
255 priv->vram.paddr, attrs);
256 }
257
258 component_unbind_all(dev, ddev);
259
260 msm_mdss_destroy(ddev);
261
262 ddev->dev_private = NULL;
263 drm_dev_unref(ddev);
264
265 kfree(priv);
266
267 return 0;
268}
269
270static int get_mdp_ver(struct platform_device *pdev)
271{
272 struct device *dev = &pdev->dev;
273
274 return (int) (unsigned long) of_device_get_match_data(dev);
275}
276
277#include <linux/of_address.h>
278
279static int msm_init_vram(struct drm_device *dev)
280{
281 struct msm_drm_private *priv = dev->dev_private;
282 struct device_node *node;
283 unsigned long size = 0;
284 int ret = 0;
285
286 /* In the device-tree world, we could have a 'memory-region'
287 * phandle, which gives us a link to our "vram". Allocating
288 * is all nicely abstracted behind the dma api, but we need
289 * to know the entire size to allocate it all in one go. There
290 * are two cases:
291 * 1) device with no IOMMU, in which case we need exclusive
292 * access to a VRAM carveout big enough for all gpu
293 * buffers
294 * 2) device with IOMMU, but where the bootloader puts up
295 * a splash screen. In this case, the VRAM carveout
296 * need only be large enough for fbdev fb. But we need
297 * exclusive access to the buffer to avoid the kernel
298 * using those pages for other purposes (which appears
299 * as corruption on screen before we have a chance to
300 * load and do initial modeset)
301 */
302
303 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
304 if (node) {
305 struct resource r;
306 ret = of_address_to_resource(node, 0, &r);
307 of_node_put(node);
308 if (ret)
309 return ret;
310 size = r.end - r.start;
311 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
312
313 /* if we have no IOMMU, then we need to use carveout allocator.
314 * Grab the entire CMA chunk carved out in early startup in
315 * mach-msm:
316 */
317 } else if (!iommu_present(&platform_bus_type)) {
318 DRM_INFO("using %s VRAM carveout\n", vram);
319 size = memparse(vram, NULL);
320 }
321
322 if (size) {
323 unsigned long attrs = 0;
324 void *p;
325
326 priv->vram.size = size;
327
328 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
329 spin_lock_init(&priv->vram.lock);
330
331 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
332 attrs |= DMA_ATTR_WRITE_COMBINE;
333
334 /* note that for no-kernel-mapping, the vaddr returned
335 * is bogus, but non-null if allocation succeeded:
336 */
337 p = dma_alloc_attrs(dev->dev, size,
338 &priv->vram.paddr, GFP_KERNEL, attrs);
339 if (!p) {
340 dev_err(dev->dev, "failed to allocate VRAM\n");
341 priv->vram.paddr = 0;
342 return -ENOMEM;
343 }
344
345 dev_info(dev->dev, "VRAM: %08x->%08x\n",
346 (uint32_t)priv->vram.paddr,
347 (uint32_t)(priv->vram.paddr + size));
348 }
349
350 return ret;
351}
352
353static int msm_drm_init(struct device *dev, struct drm_driver *drv)
354{
355 struct platform_device *pdev = to_platform_device(dev);
356 struct drm_device *ddev;
357 struct msm_drm_private *priv;
358 struct msm_kms *kms;
359 int ret;
360
361 ddev = drm_dev_alloc(drv, dev);
362 if (IS_ERR(ddev)) {
363 dev_err(dev, "failed to allocate drm_device\n");
364 return PTR_ERR(ddev);
365 }
366
367 platform_set_drvdata(pdev, ddev);
368
369 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
370 if (!priv) {
371 drm_dev_unref(ddev);
372 return -ENOMEM;
373 }
374
375 ddev->dev_private = priv;
376 priv->dev = ddev;
377
378 ret = msm_mdss_init(ddev);
379 if (ret) {
380 kfree(priv);
381 drm_dev_unref(ddev);
382 return ret;
383 }
384
385 priv->wq = alloc_ordered_workqueue("msm", 0);
386 priv->atomic_wq = alloc_ordered_workqueue("msm:atomic", 0);
387 init_waitqueue_head(&priv->pending_crtcs_event);
388
389 INIT_LIST_HEAD(&priv->inactive_list);
390 INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
391 INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
392 spin_lock_init(&priv->vblank_ctrl.lock);
393
394 drm_mode_config_init(ddev);
395
396 /* Bind all our sub-components: */
397 ret = component_bind_all(dev, ddev);
398 if (ret) {
399 msm_mdss_destroy(ddev);
400 kfree(priv);
401 drm_dev_unref(ddev);
402 return ret;
403 }
404
405 ret = msm_init_vram(ddev);
406 if (ret)
407 goto fail;
408
409 msm_gem_shrinker_init(ddev);
410
411 switch (get_mdp_ver(pdev)) {
412 case 4:
413 kms = mdp4_kms_init(ddev);
414 priv->kms = kms;
415 break;
416 case 5:
417 kms = mdp5_kms_init(ddev);
418 break;
419 default:
420 kms = ERR_PTR(-ENODEV);
421 break;
422 }
423
424 if (IS_ERR(kms)) {
425 /*
426 * NOTE: once we have GPU support, having no kms should not
427 * be considered fatal.. ideally we would still support gpu
428 * and (for example) use dmabuf/prime to share buffers with
429 * imx drm driver on iMX5
430 */
431 dev_err(dev, "failed to load kms\n");
432 ret = PTR_ERR(kms);
433 goto fail;
434 }
435
436 if (kms) {
437 ret = kms->funcs->hw_init(kms);
438 if (ret) {
439 dev_err(dev, "kms hw init failed: %d\n", ret);
440 goto fail;
441 }
442 }
443
444 ddev->mode_config.funcs = &mode_config_funcs;
445
446 ret = drm_vblank_init(ddev, priv->num_crtcs);
447 if (ret < 0) {
448 dev_err(dev, "failed to initialize vblank\n");
449 goto fail;
450 }
451
452 if (kms) {
453 pm_runtime_get_sync(dev);
454 ret = drm_irq_install(ddev, kms->irq);
455 pm_runtime_put_sync(dev);
456 if (ret < 0) {
457 dev_err(dev, "failed to install IRQ handler\n");
458 goto fail;
459 }
460 }
461
462 ret = drm_dev_register(ddev, 0);
463 if (ret)
464 goto fail;
465
466 drm_mode_config_reset(ddev);
467
468#ifdef CONFIG_DRM_FBDEV_EMULATION
469 if (fbdev)
470 priv->fbdev = msm_fbdev_init(ddev);
471#endif
472
473 ret = msm_debugfs_late_init(ddev);
474 if (ret)
475 goto fail;
476
477 drm_kms_helper_poll_init(ddev);
478
479 return 0;
480
481fail:
482 msm_drm_uninit(dev);
483 return ret;
484}
485
486/*
487 * DRM operations:
488 */
489
490static void load_gpu(struct drm_device *dev)
491{
492 static DEFINE_MUTEX(init_lock);
493 struct msm_drm_private *priv = dev->dev_private;
494
495 mutex_lock(&init_lock);
496
497 if (!priv->gpu)
498 priv->gpu = adreno_load_gpu(dev);
499
500 mutex_unlock(&init_lock);
501}
502
503static int context_init(struct drm_device *dev, struct drm_file *file)
504{
505 struct msm_file_private *ctx;
506
507 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
508 if (!ctx)
509 return -ENOMEM;
510
511 msm_submitqueue_init(dev, ctx);
512
513 file->driver_priv = ctx;
514
515 return 0;
516}
517
518static int msm_open(struct drm_device *dev, struct drm_file *file)
519{
520 /* For now, load gpu on open.. to avoid the requirement of having
521 * firmware in the initrd.
522 */
523 load_gpu(dev);
524
525 return context_init(dev, file);
526}
527
528static void context_close(struct msm_file_private *ctx)
529{
530 msm_submitqueue_close(ctx);
531 kfree(ctx);
532}
533
534static void msm_postclose(struct drm_device *dev, struct drm_file *file)
535{
536 struct msm_drm_private *priv = dev->dev_private;
537 struct msm_file_private *ctx = file->driver_priv;
538
539 mutex_lock(&dev->struct_mutex);
540 if (ctx == priv->lastctx)
541 priv->lastctx = NULL;
542 mutex_unlock(&dev->struct_mutex);
543
544 context_close(ctx);
545}
546
547static irqreturn_t msm_irq(int irq, void *arg)
548{
549 struct drm_device *dev = arg;
550 struct msm_drm_private *priv = dev->dev_private;
551 struct msm_kms *kms = priv->kms;
552 BUG_ON(!kms);
553 return kms->funcs->irq(kms);
554}
555
556static void msm_irq_preinstall(struct drm_device *dev)
557{
558 struct msm_drm_private *priv = dev->dev_private;
559 struct msm_kms *kms = priv->kms;
560 BUG_ON(!kms);
561 kms->funcs->irq_preinstall(kms);
562}
563
564static int msm_irq_postinstall(struct drm_device *dev)
565{
566 struct msm_drm_private *priv = dev->dev_private;
567 struct msm_kms *kms = priv->kms;
568 BUG_ON(!kms);
569 return kms->funcs->irq_postinstall(kms);
570}
571
572static void msm_irq_uninstall(struct drm_device *dev)
573{
574 struct msm_drm_private *priv = dev->dev_private;
575 struct msm_kms *kms = priv->kms;
576 BUG_ON(!kms);
577 kms->funcs->irq_uninstall(kms);
578}
579
580static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
581{
582 struct msm_drm_private *priv = dev->dev_private;
583 struct msm_kms *kms = priv->kms;
584 if (!kms)
585 return -ENXIO;
586 DBG("dev=%p, crtc=%u", dev, pipe);
587 return vblank_ctrl_queue_work(priv, pipe, true);
588}
589
590static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
591{
592 struct msm_drm_private *priv = dev->dev_private;
593 struct msm_kms *kms = priv->kms;
594 if (!kms)
595 return;
596 DBG("dev=%p, crtc=%u", dev, pipe);
597 vblank_ctrl_queue_work(priv, pipe, false);
598}
599
600/*
601 * DRM ioctls:
602 */
603
604static int msm_ioctl_get_param(struct drm_device *dev, void *data,
605 struct drm_file *file)
606{
607 struct msm_drm_private *priv = dev->dev_private;
608 struct drm_msm_param *args = data;
609 struct msm_gpu *gpu;
610
611 /* for now, we just have 3d pipe.. eventually this would need to
612 * be more clever to dispatch to appropriate gpu module:
613 */
614 if (args->pipe != MSM_PIPE_3D0)
615 return -EINVAL;
616
617 gpu = priv->gpu;
618
619 if (!gpu)
620 return -ENXIO;
621
622 return gpu->funcs->get_param(gpu, args->param, &args->value);
623}
624
625static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
626 struct drm_file *file)
627{
628 struct drm_msm_gem_new *args = data;
629
630 if (args->flags & ~MSM_BO_FLAGS) {
631 DRM_ERROR("invalid flags: %08x\n", args->flags);
632 return -EINVAL;
633 }
634
635 return msm_gem_new_handle(dev, file, args->size,
636 args->flags, &args->handle);
637}
638
639static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
640{
641 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
642}
643
644static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
645 struct drm_file *file)
646{
647 struct drm_msm_gem_cpu_prep *args = data;
648 struct drm_gem_object *obj;
649 ktime_t timeout = to_ktime(args->timeout);
650 int ret;
651
652 if (args->op & ~MSM_PREP_FLAGS) {
653 DRM_ERROR("invalid op: %08x\n", args->op);
654 return -EINVAL;
655 }
656
657 obj = drm_gem_object_lookup(file, args->handle);
658 if (!obj)
659 return -ENOENT;
660
661 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
662
663 drm_gem_object_put_unlocked(obj);
664
665 return ret;
666}
667
668static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
669 struct drm_file *file)
670{
671 struct drm_msm_gem_cpu_fini *args = data;
672 struct drm_gem_object *obj;
673 int ret;
674
675 obj = drm_gem_object_lookup(file, args->handle);
676 if (!obj)
677 return -ENOENT;
678
679 ret = msm_gem_cpu_fini(obj);
680
681 drm_gem_object_put_unlocked(obj);
682
683 return ret;
684}
685
686static int msm_ioctl_gem_info_iova(struct drm_device *dev,
687 struct drm_gem_object *obj, uint64_t *iova)
688{
689 struct msm_drm_private *priv = dev->dev_private;
690
691 if (!priv->gpu)
692 return -EINVAL;
693
694 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
695}
696
697static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
698 struct drm_file *file)
699{
700 struct drm_msm_gem_info *args = data;
701 struct drm_gem_object *obj;
702 int ret = 0;
703
704 if (args->flags & ~MSM_INFO_FLAGS)
705 return -EINVAL;
706
707 obj = drm_gem_object_lookup(file, args->handle);
708 if (!obj)
709 return -ENOENT;
710
711 if (args->flags & MSM_INFO_IOVA) {
712 uint64_t iova;
713
714 ret = msm_ioctl_gem_info_iova(dev, obj, &iova);
715 if (!ret)
716 args->offset = iova;
717 } else {
718 args->offset = msm_gem_mmap_offset(obj);
719 }
720
721 drm_gem_object_put_unlocked(obj);
722
723 return ret;
724}
725
726static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
727 struct drm_file *file)
728{
729 struct msm_drm_private *priv = dev->dev_private;
730 struct drm_msm_wait_fence *args = data;
731 ktime_t timeout = to_ktime(args->timeout);
732 struct msm_gpu_submitqueue *queue;
733 struct msm_gpu *gpu = priv->gpu;
734 int ret;
735
736 if (args->pad) {
737 DRM_ERROR("invalid pad: %08x\n", args->pad);
738 return -EINVAL;
739 }
740
741 if (!gpu)
742 return 0;
743
744 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
745 if (!queue)
746 return -ENOENT;
747
748 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
749 true);
750
751 msm_submitqueue_put(queue);
752 return ret;
753}
754
755static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
756 struct drm_file *file)
757{
758 struct drm_msm_gem_madvise *args = data;
759 struct drm_gem_object *obj;
760 int ret;
761
762 switch (args->madv) {
763 case MSM_MADV_DONTNEED:
764 case MSM_MADV_WILLNEED:
765 break;
766 default:
767 return -EINVAL;
768 }
769
770 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 if (ret)
772 return ret;
773
774 obj = drm_gem_object_lookup(file, args->handle);
775 if (!obj) {
776 ret = -ENOENT;
777 goto unlock;
778 }
779
780 ret = msm_gem_madvise(obj, args->madv);
781 if (ret >= 0) {
782 args->retained = ret;
783 ret = 0;
784 }
785
786 drm_gem_object_put(obj);
787
788unlock:
789 mutex_unlock(&dev->struct_mutex);
790 return ret;
791}
792
793
794static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
795 struct drm_file *file)
796{
797 struct drm_msm_submitqueue *args = data;
798
799 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
800 return -EINVAL;
801
802 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
803 args->flags, &args->id);
804}
805
806
807static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
808 struct drm_file *file)
809{
810 u32 id = *(u32 *) data;
811
812 return msm_submitqueue_remove(file->driver_priv, id);
813}
814
815static const struct drm_ioctl_desc msm_ioctls[] = {
816 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
817 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
818 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
819 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
820 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
821 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
822 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
823 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_AUTH|DRM_RENDER_ALLOW),
824 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_AUTH|DRM_RENDER_ALLOW),
825 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_AUTH|DRM_RENDER_ALLOW),
826};
827
828static const struct vm_operations_struct vm_ops = {
829 .fault = msm_gem_fault,
830 .open = drm_gem_vm_open,
831 .close = drm_gem_vm_close,
832};
833
834static const struct file_operations fops = {
835 .owner = THIS_MODULE,
836 .open = drm_open,
837 .release = drm_release,
838 .unlocked_ioctl = drm_ioctl,
839 .compat_ioctl = drm_compat_ioctl,
840 .poll = drm_poll,
841 .read = drm_read,
842 .llseek = no_llseek,
843 .mmap = msm_gem_mmap,
844};
845
846static struct drm_driver msm_driver = {
847 .driver_features = DRIVER_HAVE_IRQ |
848 DRIVER_GEM |
849 DRIVER_PRIME |
850 DRIVER_RENDER |
851 DRIVER_ATOMIC |
852 DRIVER_MODESET,
853 .open = msm_open,
854 .postclose = msm_postclose,
855 .lastclose = drm_fb_helper_lastclose,
856 .irq_handler = msm_irq,
857 .irq_preinstall = msm_irq_preinstall,
858 .irq_postinstall = msm_irq_postinstall,
859 .irq_uninstall = msm_irq_uninstall,
860 .enable_vblank = msm_enable_vblank,
861 .disable_vblank = msm_disable_vblank,
862 .gem_free_object = msm_gem_free_object,
863 .gem_vm_ops = &vm_ops,
864 .dumb_create = msm_gem_dumb_create,
865 .dumb_map_offset = msm_gem_dumb_map_offset,
866 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
867 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
868 .gem_prime_export = drm_gem_prime_export,
869 .gem_prime_import = drm_gem_prime_import,
870 .gem_prime_res_obj = msm_gem_prime_res_obj,
871 .gem_prime_pin = msm_gem_prime_pin,
872 .gem_prime_unpin = msm_gem_prime_unpin,
873 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
874 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
875 .gem_prime_vmap = msm_gem_prime_vmap,
876 .gem_prime_vunmap = msm_gem_prime_vunmap,
877 .gem_prime_mmap = msm_gem_prime_mmap,
878#ifdef CONFIG_DEBUG_FS
879 .debugfs_init = msm_debugfs_init,
880#endif
881 .ioctls = msm_ioctls,
882 .num_ioctls = ARRAY_SIZE(msm_ioctls),
883 .fops = &fops,
884 .name = "msm",
885 .desc = "MSM Snapdragon DRM",
886 .date = "20130625",
887 .major = MSM_VERSION_MAJOR,
888 .minor = MSM_VERSION_MINOR,
889 .patchlevel = MSM_VERSION_PATCHLEVEL,
890};
891
892#ifdef CONFIG_PM_SLEEP
893static int msm_pm_suspend(struct device *dev)
894{
895 struct drm_device *ddev = dev_get_drvdata(dev);
896
897 drm_kms_helper_poll_disable(ddev);
898
899 return 0;
900}
901
902static int msm_pm_resume(struct device *dev)
903{
904 struct drm_device *ddev = dev_get_drvdata(dev);
905
906 drm_kms_helper_poll_enable(ddev);
907
908 return 0;
909}
910#endif
911
912#ifdef CONFIG_PM
913static int msm_runtime_suspend(struct device *dev)
914{
915 struct drm_device *ddev = dev_get_drvdata(dev);
916 struct msm_drm_private *priv = ddev->dev_private;
917
918 DBG("");
919
920 if (priv->mdss)
921 return msm_mdss_disable(priv->mdss);
922
923 return 0;
924}
925
926static int msm_runtime_resume(struct device *dev)
927{
928 struct drm_device *ddev = dev_get_drvdata(dev);
929 struct msm_drm_private *priv = ddev->dev_private;
930
931 DBG("");
932
933 if (priv->mdss)
934 return msm_mdss_enable(priv->mdss);
935
936 return 0;
937}
938#endif
939
940static const struct dev_pm_ops msm_pm_ops = {
941 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
942 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
943};
944
945/*
946 * Componentized driver support:
947 */
948
949/*
950 * NOTE: duplication of the same code as exynos or imx (or probably any other).
951 * so probably some room for some helpers
952 */
953static int compare_of(struct device *dev, void *data)
954{
955 return dev->of_node == data;
956}
957
958/*
959 * Identify what components need to be added by parsing what remote-endpoints
960 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
961 * is no external component that we need to add since LVDS is within MDP4
962 * itself.
963 */
964static int add_components_mdp(struct device *mdp_dev,
965 struct component_match **matchptr)
966{
967 struct device_node *np = mdp_dev->of_node;
968 struct device_node *ep_node;
969 struct device *master_dev;
970
971 /*
972 * on MDP4 based platforms, the MDP platform device is the component
973 * master that adds other display interface components to itself.
974 *
975 * on MDP5 based platforms, the MDSS platform device is the component
976 * master that adds MDP5 and other display interface components to
977 * itself.
978 */
979 if (of_device_is_compatible(np, "qcom,mdp4"))
980 master_dev = mdp_dev;
981 else
982 master_dev = mdp_dev->parent;
983
984 for_each_endpoint_of_node(np, ep_node) {
985 struct device_node *intf;
986 struct of_endpoint ep;
987 int ret;
988
989 ret = of_graph_parse_endpoint(ep_node, &ep);
990 if (ret) {
991 dev_err(mdp_dev, "unable to parse port endpoint\n");
992 of_node_put(ep_node);
993 return ret;
994 }
995
996 /*
997 * The LCDC/LVDS port on MDP4 is a speacial case where the
998 * remote-endpoint isn't a component that we need to add
999 */
1000 if (of_device_is_compatible(np, "qcom,mdp4") &&
1001 ep.port == 0)
1002 continue;
1003
1004 /*
1005 * It's okay if some of the ports don't have a remote endpoint
1006 * specified. It just means that the port isn't connected to
1007 * any external interface.
1008 */
1009 intf = of_graph_get_remote_port_parent(ep_node);
1010 if (!intf)
1011 continue;
1012
1013 drm_of_component_match_add(master_dev, matchptr, compare_of,
1014 intf);
1015 of_node_put(intf);
1016 }
1017
1018 return 0;
1019}
1020
1021static int compare_name_mdp(struct device *dev, void *data)
1022{
1023 return (strstr(dev_name(dev), "mdp") != NULL);
1024}
1025
1026static int add_display_components(struct device *dev,
1027 struct component_match **matchptr)
1028{
1029 struct device *mdp_dev;
1030 int ret;
1031
1032 /*
1033 * MDP5 based devices don't have a flat hierarchy. There is a top level
1034 * parent: MDSS, and children: MDP5, DSI, HDMI, eDP etc. Populate the
1035 * children devices, find the MDP5 node, and then add the interfaces
1036 * to our components list.
1037 */
1038 if (of_device_is_compatible(dev->of_node, "qcom,mdss")) {
1039 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1040 if (ret) {
1041 dev_err(dev, "failed to populate children devices\n");
1042 return ret;
1043 }
1044
1045 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1046 if (!mdp_dev) {
1047 dev_err(dev, "failed to find MDSS MDP node\n");
1048 of_platform_depopulate(dev);
1049 return -ENODEV;
1050 }
1051
1052 put_device(mdp_dev);
1053
1054 /* add the MDP component itself */
1055 drm_of_component_match_add(dev, matchptr, compare_of,
1056 mdp_dev->of_node);
1057 } else {
1058 /* MDP4 */
1059 mdp_dev = dev;
1060 }
1061
1062 ret = add_components_mdp(mdp_dev, matchptr);
1063 if (ret)
1064 of_platform_depopulate(dev);
1065
1066 return ret;
1067}
1068
1069/*
1070 * We don't know what's the best binding to link the gpu with the drm device.
1071 * Fow now, we just hunt for all the possible gpus that we support, and add them
1072 * as components.
1073 */
1074static const struct of_device_id msm_gpu_match[] = {
1075 { .compatible = "qcom,adreno" },
1076 { .compatible = "qcom,adreno-3xx" },
1077 { .compatible = "qcom,kgsl-3d0" },
1078 { },
1079};
1080
1081static int add_gpu_components(struct device *dev,
1082 struct component_match **matchptr)
1083{
1084 struct device_node *np;
1085
1086 np = of_find_matching_node(NULL, msm_gpu_match);
1087 if (!np)
1088 return 0;
1089
1090 drm_of_component_match_add(dev, matchptr, compare_of, np);
1091
1092 of_node_put(np);
1093
1094 return 0;
1095}
1096
1097static int msm_drm_bind(struct device *dev)
1098{
1099 return msm_drm_init(dev, &msm_driver);
1100}
1101
1102static void msm_drm_unbind(struct device *dev)
1103{
1104 msm_drm_uninit(dev);
1105}
1106
1107static const struct component_master_ops msm_drm_ops = {
1108 .bind = msm_drm_bind,
1109 .unbind = msm_drm_unbind,
1110};
1111
1112/*
1113 * Platform driver:
1114 */
1115
1116static int msm_pdev_probe(struct platform_device *pdev)
1117{
1118 struct component_match *match = NULL;
1119 int ret;
1120
1121 ret = add_display_components(&pdev->dev, &match);
1122 if (ret)
1123 return ret;
1124
1125 ret = add_gpu_components(&pdev->dev, &match);
1126 if (ret)
1127 return ret;
1128
1129 /* on all devices that I am aware of, iommu's which can map
1130 * any address the cpu can see are used:
1131 */
1132 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1133 if (ret)
1134 return ret;
1135
1136 return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1137}
1138
1139static int msm_pdev_remove(struct platform_device *pdev)
1140{
1141 component_master_del(&pdev->dev, &msm_drm_ops);
1142 of_platform_depopulate(&pdev->dev);
1143
1144 return 0;
1145}
1146
1147static const struct of_device_id dt_match[] = {
1148 { .compatible = "qcom,mdp4", .data = (void *)4 }, /* MDP4 */
1149 { .compatible = "qcom,mdss", .data = (void *)5 }, /* MDP5 MDSS */
1150 {}
1151};
1152MODULE_DEVICE_TABLE(of, dt_match);
1153
1154static struct platform_driver msm_platform_driver = {
1155 .probe = msm_pdev_probe,
1156 .remove = msm_pdev_remove,
1157 .driver = {
1158 .name = "msm",
1159 .of_match_table = dt_match,
1160 .pm = &msm_pm_ops,
1161 },
1162};
1163
1164static int __init msm_drm_register(void)
1165{
1166 if (!modeset)
1167 return -EINVAL;
1168
1169 DBG("init");
1170 msm_mdp_register();
1171 msm_dsi_register();
1172 msm_edp_register();
1173 msm_hdmi_register();
1174 adreno_register();
1175 return platform_driver_register(&msm_platform_driver);
1176}
1177
1178static void __exit msm_drm_unregister(void)
1179{
1180 DBG("fini");
1181 platform_driver_unregister(&msm_platform_driver);
1182 msm_hdmi_unregister();
1183 adreno_unregister();
1184 msm_edp_unregister();
1185 msm_dsi_unregister();
1186 msm_mdp_unregister();
1187}
1188
1189module_init(msm_drm_register);
1190module_exit(msm_drm_unregister);
1191
1192MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1193MODULE_DESCRIPTION("MSM DRM Driver");
1194MODULE_LICENSE("GPL");