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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/uaccess.h>
11#include <uapi/linux/sched/types.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_irq.h>
17#include <drm/drm_prime.h>
18#include <drm/drm_of.h>
19#include <drm/drm_vblank.h>
20
21#include "msm_drv.h"
22#include "msm_debugfs.h"
23#include "msm_fence.h"
24#include "msm_gem.h"
25#include "msm_gpu.h"
26#include "msm_kms.h"
27#include "adreno/adreno_gpu.h"
28
29/*
30 * MSM driver version:
31 * - 1.0.0 - initial interface
32 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
33 * - 1.2.0 - adds explicit fence support for submit ioctl
34 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
35 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
36 * MSM_GEM_INFO ioctl.
37 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
38 * GEM object's debug name
39 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
40 * - 1.6.0 - Syncobj support
41 */
42#define MSM_VERSION_MAJOR 1
43#define MSM_VERSION_MINOR 6
44#define MSM_VERSION_PATCHLEVEL 0
45
46static const struct drm_mode_config_funcs mode_config_funcs = {
47 .fb_create = msm_framebuffer_create,
48 .output_poll_changed = drm_fb_helper_output_poll_changed,
49 .atomic_check = drm_atomic_helper_check,
50 .atomic_commit = drm_atomic_helper_commit,
51};
52
53static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
54 .atomic_commit_tail = msm_atomic_commit_tail,
55};
56
57#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
58static bool reglog = false;
59MODULE_PARM_DESC(reglog, "Enable register read/write logging");
60module_param(reglog, bool, 0600);
61#else
62#define reglog 0
63#endif
64
65#ifdef CONFIG_DRM_FBDEV_EMULATION
66static bool fbdev = true;
67MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
68module_param(fbdev, bool, 0600);
69#endif
70
71static char *vram = "16m";
72MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
73module_param(vram, charp, 0);
74
75bool dumpstate = false;
76MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
77module_param(dumpstate, bool, 0600);
78
79static bool modeset = true;
80MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
81module_param(modeset, bool, 0600);
82
83/*
84 * Util/helpers:
85 */
86
87struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
88 const char *name)
89{
90 int i;
91 char n[32];
92
93 snprintf(n, sizeof(n), "%s_clk", name);
94
95 for (i = 0; bulk && i < count; i++) {
96 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
97 return bulk[i].clk;
98 }
99
100
101 return NULL;
102}
103
104struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
105{
106 struct clk *clk;
107 char name2[32];
108
109 clk = devm_clk_get(&pdev->dev, name);
110 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
111 return clk;
112
113 snprintf(name2, sizeof(name2), "%s_clk", name);
114
115 clk = devm_clk_get(&pdev->dev, name2);
116 if (!IS_ERR(clk))
117 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
118 "\"%s\" instead of \"%s\"\n", name, name2);
119
120 return clk;
121}
122
123void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
124 const char *dbgname, bool quiet)
125{
126 struct resource *res;
127 unsigned long size;
128 void __iomem *ptr;
129
130 if (name)
131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
132 else
133 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
134
135 if (!res) {
136 if (!quiet)
137 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
138 return ERR_PTR(-EINVAL);
139 }
140
141 size = resource_size(res);
142
143 ptr = devm_ioremap(&pdev->dev, res->start, size);
144 if (!ptr) {
145 if (!quiet)
146 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
147 return ERR_PTR(-ENOMEM);
148 }
149
150 if (reglog)
151 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
152
153 return ptr;
154}
155
156void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
157 const char *dbgname)
158{
159 return _msm_ioremap(pdev, name, dbgname, false);
160}
161
162void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
163 const char *dbgname)
164{
165 return _msm_ioremap(pdev, name, dbgname, true);
166}
167
168void msm_writel(u32 data, void __iomem *addr)
169{
170 if (reglog)
171 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
172 writel(data, addr);
173}
174
175u32 msm_readl(const void __iomem *addr)
176{
177 u32 val = readl(addr);
178 if (reglog)
179 pr_err("IO:R %p %08x\n", addr, val);
180 return val;
181}
182
183struct msm_vblank_work {
184 struct work_struct work;
185 int crtc_id;
186 bool enable;
187 struct msm_drm_private *priv;
188};
189
190static void vblank_ctrl_worker(struct work_struct *work)
191{
192 struct msm_vblank_work *vbl_work = container_of(work,
193 struct msm_vblank_work, work);
194 struct msm_drm_private *priv = vbl_work->priv;
195 struct msm_kms *kms = priv->kms;
196
197 if (vbl_work->enable)
198 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
199 else
200 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
201
202 kfree(vbl_work);
203}
204
205static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
206 int crtc_id, bool enable)
207{
208 struct msm_vblank_work *vbl_work;
209
210 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
211 if (!vbl_work)
212 return -ENOMEM;
213
214 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
215
216 vbl_work->crtc_id = crtc_id;
217 vbl_work->enable = enable;
218 vbl_work->priv = priv;
219
220 queue_work(priv->wq, &vbl_work->work);
221
222 return 0;
223}
224
225static int msm_drm_uninit(struct device *dev)
226{
227 struct platform_device *pdev = to_platform_device(dev);
228 struct drm_device *ddev = platform_get_drvdata(pdev);
229 struct msm_drm_private *priv = ddev->dev_private;
230 struct msm_kms *kms = priv->kms;
231 struct msm_mdss *mdss = priv->mdss;
232 int i;
233
234 /*
235 * Shutdown the hw if we're far enough along where things might be on.
236 * If we run this too early, we'll end up panicking in any variety of
237 * places. Since we don't register the drm device until late in
238 * msm_drm_init, drm_dev->registered is used as an indicator that the
239 * shutdown will be successful.
240 */
241 if (ddev->registered) {
242 drm_dev_unregister(ddev);
243 drm_atomic_helper_shutdown(ddev);
244 }
245
246 /* We must cancel and cleanup any pending vblank enable/disable
247 * work before drm_irq_uninstall() to avoid work re-enabling an
248 * irq after uninstall has disabled it.
249 */
250
251 flush_workqueue(priv->wq);
252
253 /* clean up event worker threads */
254 for (i = 0; i < priv->num_crtcs; i++) {
255 if (priv->event_thread[i].worker)
256 kthread_destroy_worker(priv->event_thread[i].worker);
257 }
258
259 msm_gem_shrinker_cleanup(ddev);
260
261 drm_kms_helper_poll_fini(ddev);
262
263 msm_perf_debugfs_cleanup(priv);
264 msm_rd_debugfs_cleanup(priv);
265
266#ifdef CONFIG_DRM_FBDEV_EMULATION
267 if (fbdev && priv->fbdev)
268 msm_fbdev_free(ddev);
269#endif
270
271 drm_mode_config_cleanup(ddev);
272
273 pm_runtime_get_sync(dev);
274 drm_irq_uninstall(ddev);
275 pm_runtime_put_sync(dev);
276
277 if (kms && kms->funcs)
278 kms->funcs->destroy(kms);
279
280 if (priv->vram.paddr) {
281 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
282 drm_mm_takedown(&priv->vram.mm);
283 dma_free_attrs(dev, priv->vram.size, NULL,
284 priv->vram.paddr, attrs);
285 }
286
287 component_unbind_all(dev, ddev);
288
289 if (mdss && mdss->funcs)
290 mdss->funcs->destroy(ddev);
291
292 ddev->dev_private = NULL;
293 drm_dev_put(ddev);
294
295 destroy_workqueue(priv->wq);
296 kfree(priv);
297
298 return 0;
299}
300
301#define KMS_MDP4 4
302#define KMS_MDP5 5
303#define KMS_DPU 3
304
305static int get_mdp_ver(struct platform_device *pdev)
306{
307 struct device *dev = &pdev->dev;
308
309 return (int) (unsigned long) of_device_get_match_data(dev);
310}
311
312#include <linux/of_address.h>
313
314bool msm_use_mmu(struct drm_device *dev)
315{
316 struct msm_drm_private *priv = dev->dev_private;
317
318 /* a2xx comes with its own MMU */
319 return priv->is_a2xx || iommu_present(&platform_bus_type);
320}
321
322static int msm_init_vram(struct drm_device *dev)
323{
324 struct msm_drm_private *priv = dev->dev_private;
325 struct device_node *node;
326 unsigned long size = 0;
327 int ret = 0;
328
329 /* In the device-tree world, we could have a 'memory-region'
330 * phandle, which gives us a link to our "vram". Allocating
331 * is all nicely abstracted behind the dma api, but we need
332 * to know the entire size to allocate it all in one go. There
333 * are two cases:
334 * 1) device with no IOMMU, in which case we need exclusive
335 * access to a VRAM carveout big enough for all gpu
336 * buffers
337 * 2) device with IOMMU, but where the bootloader puts up
338 * a splash screen. In this case, the VRAM carveout
339 * need only be large enough for fbdev fb. But we need
340 * exclusive access to the buffer to avoid the kernel
341 * using those pages for other purposes (which appears
342 * as corruption on screen before we have a chance to
343 * load and do initial modeset)
344 */
345
346 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
347 if (node) {
348 struct resource r;
349 ret = of_address_to_resource(node, 0, &r);
350 of_node_put(node);
351 if (ret)
352 return ret;
353 size = r.end - r.start;
354 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
355
356 /* if we have no IOMMU, then we need to use carveout allocator.
357 * Grab the entire CMA chunk carved out in early startup in
358 * mach-msm:
359 */
360 } else if (!msm_use_mmu(dev)) {
361 DRM_INFO("using %s VRAM carveout\n", vram);
362 size = memparse(vram, NULL);
363 }
364
365 if (size) {
366 unsigned long attrs = 0;
367 void *p;
368
369 priv->vram.size = size;
370
371 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
372 spin_lock_init(&priv->vram.lock);
373
374 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
375 attrs |= DMA_ATTR_WRITE_COMBINE;
376
377 /* note that for no-kernel-mapping, the vaddr returned
378 * is bogus, but non-null if allocation succeeded:
379 */
380 p = dma_alloc_attrs(dev->dev, size,
381 &priv->vram.paddr, GFP_KERNEL, attrs);
382 if (!p) {
383 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
384 priv->vram.paddr = 0;
385 return -ENOMEM;
386 }
387
388 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
389 (uint32_t)priv->vram.paddr,
390 (uint32_t)(priv->vram.paddr + size));
391 }
392
393 return ret;
394}
395
396static int msm_drm_init(struct device *dev, struct drm_driver *drv)
397{
398 struct platform_device *pdev = to_platform_device(dev);
399 struct drm_device *ddev;
400 struct msm_drm_private *priv;
401 struct msm_kms *kms;
402 struct msm_mdss *mdss;
403 int ret, i;
404
405 ddev = drm_dev_alloc(drv, dev);
406 if (IS_ERR(ddev)) {
407 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
408 return PTR_ERR(ddev);
409 }
410
411 platform_set_drvdata(pdev, ddev);
412
413 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
414 if (!priv) {
415 ret = -ENOMEM;
416 goto err_put_drm_dev;
417 }
418
419 ddev->dev_private = priv;
420 priv->dev = ddev;
421
422 switch (get_mdp_ver(pdev)) {
423 case KMS_MDP5:
424 ret = mdp5_mdss_init(ddev);
425 break;
426 case KMS_DPU:
427 ret = dpu_mdss_init(ddev);
428 break;
429 default:
430 ret = 0;
431 break;
432 }
433 if (ret)
434 goto err_free_priv;
435
436 mdss = priv->mdss;
437
438 priv->wq = alloc_ordered_workqueue("msm", 0);
439
440 INIT_WORK(&priv->free_work, msm_gem_free_work);
441 init_llist_head(&priv->free_list);
442
443 INIT_LIST_HEAD(&priv->inactive_list);
444
445 drm_mode_config_init(ddev);
446
447 /* Bind all our sub-components: */
448 ret = component_bind_all(dev, ddev);
449 if (ret)
450 goto err_destroy_mdss;
451
452 ret = msm_init_vram(ddev);
453 if (ret)
454 goto err_msm_uninit;
455
456 if (!dev->dma_parms) {
457 dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
458 GFP_KERNEL);
459 if (!dev->dma_parms) {
460 ret = -ENOMEM;
461 goto err_msm_uninit;
462 }
463 }
464 dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
465
466 msm_gem_shrinker_init(ddev);
467
468 switch (get_mdp_ver(pdev)) {
469 case KMS_MDP4:
470 kms = mdp4_kms_init(ddev);
471 priv->kms = kms;
472 break;
473 case KMS_MDP5:
474 kms = mdp5_kms_init(ddev);
475 break;
476 case KMS_DPU:
477 kms = dpu_kms_init(ddev);
478 priv->kms = kms;
479 break;
480 default:
481 /* valid only for the dummy headless case, where of_node=NULL */
482 WARN_ON(dev->of_node);
483 kms = NULL;
484 break;
485 }
486
487 if (IS_ERR(kms)) {
488 DRM_DEV_ERROR(dev, "failed to load kms\n");
489 ret = PTR_ERR(kms);
490 priv->kms = NULL;
491 goto err_msm_uninit;
492 }
493
494 /* Enable normalization of plane zpos */
495 ddev->mode_config.normalize_zpos = true;
496
497 if (kms) {
498 kms->dev = ddev;
499 ret = kms->funcs->hw_init(kms);
500 if (ret) {
501 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
502 goto err_msm_uninit;
503 }
504 }
505
506 ddev->mode_config.funcs = &mode_config_funcs;
507 ddev->mode_config.helper_private = &mode_config_helper_funcs;
508
509 for (i = 0; i < priv->num_crtcs; i++) {
510 /* initialize event thread */
511 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
512 priv->event_thread[i].dev = ddev;
513 priv->event_thread[i].worker = kthread_create_worker(0,
514 "crtc_event:%d", priv->event_thread[i].crtc_id);
515 if (IS_ERR(priv->event_thread[i].worker)) {
516 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
517 goto err_msm_uninit;
518 }
519
520 sched_set_fifo(priv->event_thread[i].worker->task);
521 }
522
523 ret = drm_vblank_init(ddev, priv->num_crtcs);
524 if (ret < 0) {
525 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
526 goto err_msm_uninit;
527 }
528
529 if (kms) {
530 pm_runtime_get_sync(dev);
531 ret = drm_irq_install(ddev, kms->irq);
532 pm_runtime_put_sync(dev);
533 if (ret < 0) {
534 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
535 goto err_msm_uninit;
536 }
537 }
538
539 ret = drm_dev_register(ddev, 0);
540 if (ret)
541 goto err_msm_uninit;
542
543 drm_mode_config_reset(ddev);
544
545#ifdef CONFIG_DRM_FBDEV_EMULATION
546 if (kms && fbdev)
547 priv->fbdev = msm_fbdev_init(ddev);
548#endif
549
550 ret = msm_debugfs_late_init(ddev);
551 if (ret)
552 goto err_msm_uninit;
553
554 drm_kms_helper_poll_init(ddev);
555
556 return 0;
557
558err_msm_uninit:
559 msm_drm_uninit(dev);
560 return ret;
561err_destroy_mdss:
562 if (mdss && mdss->funcs)
563 mdss->funcs->destroy(ddev);
564err_free_priv:
565 kfree(priv);
566err_put_drm_dev:
567 drm_dev_put(ddev);
568 return ret;
569}
570
571/*
572 * DRM operations:
573 */
574
575static void load_gpu(struct drm_device *dev)
576{
577 static DEFINE_MUTEX(init_lock);
578 struct msm_drm_private *priv = dev->dev_private;
579
580 mutex_lock(&init_lock);
581
582 if (!priv->gpu)
583 priv->gpu = adreno_load_gpu(dev);
584
585 mutex_unlock(&init_lock);
586}
587
588static int context_init(struct drm_device *dev, struct drm_file *file)
589{
590 struct msm_drm_private *priv = dev->dev_private;
591 struct msm_file_private *ctx;
592
593 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
594 if (!ctx)
595 return -ENOMEM;
596
597 msm_submitqueue_init(dev, ctx);
598
599 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
600 file->driver_priv = ctx;
601
602 return 0;
603}
604
605static int msm_open(struct drm_device *dev, struct drm_file *file)
606{
607 /* For now, load gpu on open.. to avoid the requirement of having
608 * firmware in the initrd.
609 */
610 load_gpu(dev);
611
612 return context_init(dev, file);
613}
614
615static void context_close(struct msm_file_private *ctx)
616{
617 msm_submitqueue_close(ctx);
618 kfree(ctx);
619}
620
621static void msm_postclose(struct drm_device *dev, struct drm_file *file)
622{
623 struct msm_drm_private *priv = dev->dev_private;
624 struct msm_file_private *ctx = file->driver_priv;
625
626 mutex_lock(&dev->struct_mutex);
627 if (ctx == priv->lastctx)
628 priv->lastctx = NULL;
629 mutex_unlock(&dev->struct_mutex);
630
631 context_close(ctx);
632}
633
634static irqreturn_t msm_irq(int irq, void *arg)
635{
636 struct drm_device *dev = arg;
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
639 BUG_ON(!kms);
640 return kms->funcs->irq(kms);
641}
642
643static void msm_irq_preinstall(struct drm_device *dev)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_kms *kms = priv->kms;
647 BUG_ON(!kms);
648 kms->funcs->irq_preinstall(kms);
649}
650
651static int msm_irq_postinstall(struct drm_device *dev)
652{
653 struct msm_drm_private *priv = dev->dev_private;
654 struct msm_kms *kms = priv->kms;
655 BUG_ON(!kms);
656
657 if (kms->funcs->irq_postinstall)
658 return kms->funcs->irq_postinstall(kms);
659
660 return 0;
661}
662
663static void msm_irq_uninstall(struct drm_device *dev)
664{
665 struct msm_drm_private *priv = dev->dev_private;
666 struct msm_kms *kms = priv->kms;
667 BUG_ON(!kms);
668 kms->funcs->irq_uninstall(kms);
669}
670
671int msm_crtc_enable_vblank(struct drm_crtc *crtc)
672{
673 struct drm_device *dev = crtc->dev;
674 unsigned int pipe = crtc->index;
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
677 if (!kms)
678 return -ENXIO;
679 DBG("dev=%p, crtc=%u", dev, pipe);
680 return vblank_ctrl_queue_work(priv, pipe, true);
681}
682
683void msm_crtc_disable_vblank(struct drm_crtc *crtc)
684{
685 struct drm_device *dev = crtc->dev;
686 unsigned int pipe = crtc->index;
687 struct msm_drm_private *priv = dev->dev_private;
688 struct msm_kms *kms = priv->kms;
689 if (!kms)
690 return;
691 DBG("dev=%p, crtc=%u", dev, pipe);
692 vblank_ctrl_queue_work(priv, pipe, false);
693}
694
695/*
696 * DRM ioctls:
697 */
698
699static int msm_ioctl_get_param(struct drm_device *dev, void *data,
700 struct drm_file *file)
701{
702 struct msm_drm_private *priv = dev->dev_private;
703 struct drm_msm_param *args = data;
704 struct msm_gpu *gpu;
705
706 /* for now, we just have 3d pipe.. eventually this would need to
707 * be more clever to dispatch to appropriate gpu module:
708 */
709 if (args->pipe != MSM_PIPE_3D0)
710 return -EINVAL;
711
712 gpu = priv->gpu;
713
714 if (!gpu)
715 return -ENXIO;
716
717 return gpu->funcs->get_param(gpu, args->param, &args->value);
718}
719
720static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
721 struct drm_file *file)
722{
723 struct drm_msm_gem_new *args = data;
724
725 if (args->flags & ~MSM_BO_FLAGS) {
726 DRM_ERROR("invalid flags: %08x\n", args->flags);
727 return -EINVAL;
728 }
729
730 return msm_gem_new_handle(dev, file, args->size,
731 args->flags, &args->handle, NULL);
732}
733
734static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
735{
736 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
737}
738
739static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
740 struct drm_file *file)
741{
742 struct drm_msm_gem_cpu_prep *args = data;
743 struct drm_gem_object *obj;
744 ktime_t timeout = to_ktime(args->timeout);
745 int ret;
746
747 if (args->op & ~MSM_PREP_FLAGS) {
748 DRM_ERROR("invalid op: %08x\n", args->op);
749 return -EINVAL;
750 }
751
752 obj = drm_gem_object_lookup(file, args->handle);
753 if (!obj)
754 return -ENOENT;
755
756 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
757
758 drm_gem_object_put(obj);
759
760 return ret;
761}
762
763static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
764 struct drm_file *file)
765{
766 struct drm_msm_gem_cpu_fini *args = data;
767 struct drm_gem_object *obj;
768 int ret;
769
770 obj = drm_gem_object_lookup(file, args->handle);
771 if (!obj)
772 return -ENOENT;
773
774 ret = msm_gem_cpu_fini(obj);
775
776 drm_gem_object_put(obj);
777
778 return ret;
779}
780
781static int msm_ioctl_gem_info_iova(struct drm_device *dev,
782 struct drm_gem_object *obj, uint64_t *iova)
783{
784 struct msm_drm_private *priv = dev->dev_private;
785
786 if (!priv->gpu)
787 return -EINVAL;
788
789 /*
790 * Don't pin the memory here - just get an address so that userspace can
791 * be productive
792 */
793 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
794}
795
796static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
797 struct drm_file *file)
798{
799 struct drm_msm_gem_info *args = data;
800 struct drm_gem_object *obj;
801 struct msm_gem_object *msm_obj;
802 int i, ret = 0;
803
804 if (args->pad)
805 return -EINVAL;
806
807 switch (args->info) {
808 case MSM_INFO_GET_OFFSET:
809 case MSM_INFO_GET_IOVA:
810 /* value returned as immediate, not pointer, so len==0: */
811 if (args->len)
812 return -EINVAL;
813 break;
814 case MSM_INFO_SET_NAME:
815 case MSM_INFO_GET_NAME:
816 break;
817 default:
818 return -EINVAL;
819 }
820
821 obj = drm_gem_object_lookup(file, args->handle);
822 if (!obj)
823 return -ENOENT;
824
825 msm_obj = to_msm_bo(obj);
826
827 switch (args->info) {
828 case MSM_INFO_GET_OFFSET:
829 args->value = msm_gem_mmap_offset(obj);
830 break;
831 case MSM_INFO_GET_IOVA:
832 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
833 break;
834 case MSM_INFO_SET_NAME:
835 /* length check should leave room for terminating null: */
836 if (args->len >= sizeof(msm_obj->name)) {
837 ret = -EINVAL;
838 break;
839 }
840 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
841 args->len)) {
842 msm_obj->name[0] = '\0';
843 ret = -EFAULT;
844 break;
845 }
846 msm_obj->name[args->len] = '\0';
847 for (i = 0; i < args->len; i++) {
848 if (!isprint(msm_obj->name[i])) {
849 msm_obj->name[i] = '\0';
850 break;
851 }
852 }
853 break;
854 case MSM_INFO_GET_NAME:
855 if (args->value && (args->len < strlen(msm_obj->name))) {
856 ret = -EINVAL;
857 break;
858 }
859 args->len = strlen(msm_obj->name);
860 if (args->value) {
861 if (copy_to_user(u64_to_user_ptr(args->value),
862 msm_obj->name, args->len))
863 ret = -EFAULT;
864 }
865 break;
866 }
867
868 drm_gem_object_put(obj);
869
870 return ret;
871}
872
873static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
874 struct drm_file *file)
875{
876 struct msm_drm_private *priv = dev->dev_private;
877 struct drm_msm_wait_fence *args = data;
878 ktime_t timeout = to_ktime(args->timeout);
879 struct msm_gpu_submitqueue *queue;
880 struct msm_gpu *gpu = priv->gpu;
881 int ret;
882
883 if (args->pad) {
884 DRM_ERROR("invalid pad: %08x\n", args->pad);
885 return -EINVAL;
886 }
887
888 if (!gpu)
889 return 0;
890
891 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
892 if (!queue)
893 return -ENOENT;
894
895 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
896 true);
897
898 msm_submitqueue_put(queue);
899 return ret;
900}
901
902static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
903 struct drm_file *file)
904{
905 struct drm_msm_gem_madvise *args = data;
906 struct drm_gem_object *obj;
907 int ret;
908
909 switch (args->madv) {
910 case MSM_MADV_DONTNEED:
911 case MSM_MADV_WILLNEED:
912 break;
913 default:
914 return -EINVAL;
915 }
916
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
918 if (ret)
919 return ret;
920
921 obj = drm_gem_object_lookup(file, args->handle);
922 if (!obj) {
923 ret = -ENOENT;
924 goto unlock;
925 }
926
927 ret = msm_gem_madvise(obj, args->madv);
928 if (ret >= 0) {
929 args->retained = ret;
930 ret = 0;
931 }
932
933 drm_gem_object_put_locked(obj);
934
935unlock:
936 mutex_unlock(&dev->struct_mutex);
937 return ret;
938}
939
940
941static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
942 struct drm_file *file)
943{
944 struct drm_msm_submitqueue *args = data;
945
946 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
947 return -EINVAL;
948
949 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
950 args->flags, &args->id);
951}
952
953static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
954 struct drm_file *file)
955{
956 return msm_submitqueue_query(dev, file->driver_priv, data);
957}
958
959static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
960 struct drm_file *file)
961{
962 u32 id = *(u32 *) data;
963
964 return msm_submitqueue_remove(file->driver_priv, id);
965}
966
967static const struct drm_ioctl_desc msm_ioctls[] = {
968 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
969 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
970 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
971 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
972 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
973 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
974 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
975 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
976 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
977 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
978 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
979};
980
981static const struct vm_operations_struct vm_ops = {
982 .fault = msm_gem_fault,
983 .open = drm_gem_vm_open,
984 .close = drm_gem_vm_close,
985};
986
987static const struct file_operations fops = {
988 .owner = THIS_MODULE,
989 .open = drm_open,
990 .release = drm_release,
991 .unlocked_ioctl = drm_ioctl,
992 .compat_ioctl = drm_compat_ioctl,
993 .poll = drm_poll,
994 .read = drm_read,
995 .llseek = no_llseek,
996 .mmap = msm_gem_mmap,
997};
998
999static struct drm_driver msm_driver = {
1000 .driver_features = DRIVER_GEM |
1001 DRIVER_RENDER |
1002 DRIVER_ATOMIC |
1003 DRIVER_MODESET |
1004 DRIVER_SYNCOBJ,
1005 .open = msm_open,
1006 .postclose = msm_postclose,
1007 .lastclose = drm_fb_helper_lastclose,
1008 .irq_handler = msm_irq,
1009 .irq_preinstall = msm_irq_preinstall,
1010 .irq_postinstall = msm_irq_postinstall,
1011 .irq_uninstall = msm_irq_uninstall,
1012 .gem_free_object_unlocked = msm_gem_free_object,
1013 .gem_vm_ops = &vm_ops,
1014 .dumb_create = msm_gem_dumb_create,
1015 .dumb_map_offset = msm_gem_dumb_map_offset,
1016 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1017 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1018 .gem_prime_pin = msm_gem_prime_pin,
1019 .gem_prime_unpin = msm_gem_prime_unpin,
1020 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1021 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1022 .gem_prime_vmap = msm_gem_prime_vmap,
1023 .gem_prime_vunmap = msm_gem_prime_vunmap,
1024 .gem_prime_mmap = msm_gem_prime_mmap,
1025#ifdef CONFIG_DEBUG_FS
1026 .debugfs_init = msm_debugfs_init,
1027#endif
1028 .ioctls = msm_ioctls,
1029 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1030 .fops = &fops,
1031 .name = "msm",
1032 .desc = "MSM Snapdragon DRM",
1033 .date = "20130625",
1034 .major = MSM_VERSION_MAJOR,
1035 .minor = MSM_VERSION_MINOR,
1036 .patchlevel = MSM_VERSION_PATCHLEVEL,
1037};
1038
1039static int __maybe_unused msm_runtime_suspend(struct device *dev)
1040{
1041 struct drm_device *ddev = dev_get_drvdata(dev);
1042 struct msm_drm_private *priv = ddev->dev_private;
1043 struct msm_mdss *mdss = priv->mdss;
1044
1045 DBG("");
1046
1047 if (mdss && mdss->funcs)
1048 return mdss->funcs->disable(mdss);
1049
1050 return 0;
1051}
1052
1053static int __maybe_unused msm_runtime_resume(struct device *dev)
1054{
1055 struct drm_device *ddev = dev_get_drvdata(dev);
1056 struct msm_drm_private *priv = ddev->dev_private;
1057 struct msm_mdss *mdss = priv->mdss;
1058
1059 DBG("");
1060
1061 if (mdss && mdss->funcs)
1062 return mdss->funcs->enable(mdss);
1063
1064 return 0;
1065}
1066
1067static int __maybe_unused msm_pm_suspend(struct device *dev)
1068{
1069
1070 if (pm_runtime_suspended(dev))
1071 return 0;
1072
1073 return msm_runtime_suspend(dev);
1074}
1075
1076static int __maybe_unused msm_pm_resume(struct device *dev)
1077{
1078 if (pm_runtime_suspended(dev))
1079 return 0;
1080
1081 return msm_runtime_resume(dev);
1082}
1083
1084static int __maybe_unused msm_pm_prepare(struct device *dev)
1085{
1086 struct drm_device *ddev = dev_get_drvdata(dev);
1087
1088 return drm_mode_config_helper_suspend(ddev);
1089}
1090
1091static void __maybe_unused msm_pm_complete(struct device *dev)
1092{
1093 struct drm_device *ddev = dev_get_drvdata(dev);
1094
1095 drm_mode_config_helper_resume(ddev);
1096}
1097
1098static const struct dev_pm_ops msm_pm_ops = {
1099 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1100 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1101 .prepare = msm_pm_prepare,
1102 .complete = msm_pm_complete,
1103};
1104
1105/*
1106 * Componentized driver support:
1107 */
1108
1109/*
1110 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1111 * so probably some room for some helpers
1112 */
1113static int compare_of(struct device *dev, void *data)
1114{
1115 return dev->of_node == data;
1116}
1117
1118/*
1119 * Identify what components need to be added by parsing what remote-endpoints
1120 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1121 * is no external component that we need to add since LVDS is within MDP4
1122 * itself.
1123 */
1124static int add_components_mdp(struct device *mdp_dev,
1125 struct component_match **matchptr)
1126{
1127 struct device_node *np = mdp_dev->of_node;
1128 struct device_node *ep_node;
1129 struct device *master_dev;
1130
1131 /*
1132 * on MDP4 based platforms, the MDP platform device is the component
1133 * master that adds other display interface components to itself.
1134 *
1135 * on MDP5 based platforms, the MDSS platform device is the component
1136 * master that adds MDP5 and other display interface components to
1137 * itself.
1138 */
1139 if (of_device_is_compatible(np, "qcom,mdp4"))
1140 master_dev = mdp_dev;
1141 else
1142 master_dev = mdp_dev->parent;
1143
1144 for_each_endpoint_of_node(np, ep_node) {
1145 struct device_node *intf;
1146 struct of_endpoint ep;
1147 int ret;
1148
1149 ret = of_graph_parse_endpoint(ep_node, &ep);
1150 if (ret) {
1151 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1152 of_node_put(ep_node);
1153 return ret;
1154 }
1155
1156 /*
1157 * The LCDC/LVDS port on MDP4 is a speacial case where the
1158 * remote-endpoint isn't a component that we need to add
1159 */
1160 if (of_device_is_compatible(np, "qcom,mdp4") &&
1161 ep.port == 0)
1162 continue;
1163
1164 /*
1165 * It's okay if some of the ports don't have a remote endpoint
1166 * specified. It just means that the port isn't connected to
1167 * any external interface.
1168 */
1169 intf = of_graph_get_remote_port_parent(ep_node);
1170 if (!intf)
1171 continue;
1172
1173 if (of_device_is_available(intf))
1174 drm_of_component_match_add(master_dev, matchptr,
1175 compare_of, intf);
1176
1177 of_node_put(intf);
1178 }
1179
1180 return 0;
1181}
1182
1183static int compare_name_mdp(struct device *dev, void *data)
1184{
1185 return (strstr(dev_name(dev), "mdp") != NULL);
1186}
1187
1188static int add_display_components(struct device *dev,
1189 struct component_match **matchptr)
1190{
1191 struct device *mdp_dev;
1192 int ret;
1193
1194 /*
1195 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1196 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1197 * Populate the children devices, find the MDP5/DPU node, and then add
1198 * the interfaces to our components list.
1199 */
1200 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1201 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
1202 of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
1203 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1204 if (ret) {
1205 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1206 return ret;
1207 }
1208
1209 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1210 if (!mdp_dev) {
1211 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1212 of_platform_depopulate(dev);
1213 return -ENODEV;
1214 }
1215
1216 put_device(mdp_dev);
1217
1218 /* add the MDP component itself */
1219 drm_of_component_match_add(dev, matchptr, compare_of,
1220 mdp_dev->of_node);
1221 } else {
1222 /* MDP4 */
1223 mdp_dev = dev;
1224 }
1225
1226 ret = add_components_mdp(mdp_dev, matchptr);
1227 if (ret)
1228 of_platform_depopulate(dev);
1229
1230 return ret;
1231}
1232
1233/*
1234 * We don't know what's the best binding to link the gpu with the drm device.
1235 * Fow now, we just hunt for all the possible gpus that we support, and add them
1236 * as components.
1237 */
1238static const struct of_device_id msm_gpu_match[] = {
1239 { .compatible = "qcom,adreno" },
1240 { .compatible = "qcom,adreno-3xx" },
1241 { .compatible = "amd,imageon" },
1242 { .compatible = "qcom,kgsl-3d0" },
1243 { },
1244};
1245
1246static int add_gpu_components(struct device *dev,
1247 struct component_match **matchptr)
1248{
1249 struct device_node *np;
1250
1251 np = of_find_matching_node(NULL, msm_gpu_match);
1252 if (!np)
1253 return 0;
1254
1255 if (of_device_is_available(np))
1256 drm_of_component_match_add(dev, matchptr, compare_of, np);
1257
1258 of_node_put(np);
1259
1260 return 0;
1261}
1262
1263static int msm_drm_bind(struct device *dev)
1264{
1265 return msm_drm_init(dev, &msm_driver);
1266}
1267
1268static void msm_drm_unbind(struct device *dev)
1269{
1270 msm_drm_uninit(dev);
1271}
1272
1273static const struct component_master_ops msm_drm_ops = {
1274 .bind = msm_drm_bind,
1275 .unbind = msm_drm_unbind,
1276};
1277
1278/*
1279 * Platform driver:
1280 */
1281
1282static int msm_pdev_probe(struct platform_device *pdev)
1283{
1284 struct component_match *match = NULL;
1285 int ret;
1286
1287 if (get_mdp_ver(pdev)) {
1288 ret = add_display_components(&pdev->dev, &match);
1289 if (ret)
1290 return ret;
1291 }
1292
1293 ret = add_gpu_components(&pdev->dev, &match);
1294 if (ret)
1295 goto fail;
1296
1297 /* on all devices that I am aware of, iommu's which can map
1298 * any address the cpu can see are used:
1299 */
1300 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1301 if (ret)
1302 goto fail;
1303
1304 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1305 if (ret)
1306 goto fail;
1307
1308 return 0;
1309
1310fail:
1311 of_platform_depopulate(&pdev->dev);
1312 return ret;
1313}
1314
1315static int msm_pdev_remove(struct platform_device *pdev)
1316{
1317 component_master_del(&pdev->dev, &msm_drm_ops);
1318 of_platform_depopulate(&pdev->dev);
1319
1320 return 0;
1321}
1322
1323static void msm_pdev_shutdown(struct platform_device *pdev)
1324{
1325 struct drm_device *drm = platform_get_drvdata(pdev);
1326
1327 drm_atomic_helper_shutdown(drm);
1328}
1329
1330static const struct of_device_id dt_match[] = {
1331 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1332 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1333 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1334 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1335 {}
1336};
1337MODULE_DEVICE_TABLE(of, dt_match);
1338
1339static struct platform_driver msm_platform_driver = {
1340 .probe = msm_pdev_probe,
1341 .remove = msm_pdev_remove,
1342 .shutdown = msm_pdev_shutdown,
1343 .driver = {
1344 .name = "msm",
1345 .of_match_table = dt_match,
1346 .pm = &msm_pm_ops,
1347 },
1348};
1349
1350static int __init msm_drm_register(void)
1351{
1352 if (!modeset)
1353 return -EINVAL;
1354
1355 DBG("init");
1356 msm_mdp_register();
1357 msm_dpu_register();
1358 msm_dsi_register();
1359 msm_edp_register();
1360 msm_hdmi_register();
1361 adreno_register();
1362 return platform_driver_register(&msm_platform_driver);
1363}
1364
1365static void __exit msm_drm_unregister(void)
1366{
1367 DBG("fini");
1368 platform_driver_unregister(&msm_platform_driver);
1369 msm_hdmi_unregister();
1370 adreno_unregister();
1371 msm_edp_unregister();
1372 msm_dsi_unregister();
1373 msm_mdp_unregister();
1374 msm_dpu_unregister();
1375}
1376
1377module_init(msm_drm_register);
1378module_exit(msm_drm_unregister);
1379
1380MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1381MODULE_DESCRIPTION("MSM DRM Driver");
1382MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_drv.h"
19#include "msm_gpu.h"
20#include "msm_kms.h"
21
22static void msm_fb_output_poll_changed(struct drm_device *dev)
23{
24 struct msm_drm_private *priv = dev->dev_private;
25 if (priv->fbdev)
26 drm_fb_helper_hotplug_event(priv->fbdev);
27}
28
29static const struct drm_mode_config_funcs mode_config_funcs = {
30 .fb_create = msm_framebuffer_create,
31 .output_poll_changed = msm_fb_output_poll_changed,
32};
33
34int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
35{
36 struct msm_drm_private *priv = dev->dev_private;
37 int idx = priv->num_mmus++;
38
39 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
40 return -EINVAL;
41
42 priv->mmus[idx] = mmu;
43
44 return idx;
45}
46
47#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
48static bool reglog = false;
49MODULE_PARM_DESC(reglog, "Enable register read/write logging");
50module_param(reglog, bool, 0600);
51#else
52#define reglog 0
53#endif
54
55static char *vram;
56MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
57module_param(vram, charp, 0);
58
59/*
60 * Util/helpers:
61 */
62
63void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
64 const char *dbgname)
65{
66 struct resource *res;
67 unsigned long size;
68 void __iomem *ptr;
69
70 if (name)
71 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
72 else
73 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
74
75 if (!res) {
76 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
77 return ERR_PTR(-EINVAL);
78 }
79
80 size = resource_size(res);
81
82 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
83 if (!ptr) {
84 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
85 return ERR_PTR(-ENOMEM);
86 }
87
88 if (reglog)
89 printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
90
91 return ptr;
92}
93
94void msm_writel(u32 data, void __iomem *addr)
95{
96 if (reglog)
97 printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
98 writel(data, addr);
99}
100
101u32 msm_readl(const void __iomem *addr)
102{
103 u32 val = readl(addr);
104 if (reglog)
105 printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
106 return val;
107}
108
109/*
110 * DRM operations:
111 */
112
113static int msm_unload(struct drm_device *dev)
114{
115 struct msm_drm_private *priv = dev->dev_private;
116 struct msm_kms *kms = priv->kms;
117 struct msm_gpu *gpu = priv->gpu;
118
119 drm_kms_helper_poll_fini(dev);
120 drm_mode_config_cleanup(dev);
121 drm_vblank_cleanup(dev);
122
123 pm_runtime_get_sync(dev->dev);
124 drm_irq_uninstall(dev);
125 pm_runtime_put_sync(dev->dev);
126
127 flush_workqueue(priv->wq);
128 destroy_workqueue(priv->wq);
129
130 if (kms) {
131 pm_runtime_disable(dev->dev);
132 kms->funcs->destroy(kms);
133 }
134
135 if (gpu) {
136 mutex_lock(&dev->struct_mutex);
137 gpu->funcs->pm_suspend(gpu);
138 gpu->funcs->destroy(gpu);
139 mutex_unlock(&dev->struct_mutex);
140 }
141
142 if (priv->vram.paddr) {
143 DEFINE_DMA_ATTRS(attrs);
144 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
145 drm_mm_takedown(&priv->vram.mm);
146 dma_free_attrs(dev->dev, priv->vram.size, NULL,
147 priv->vram.paddr, &attrs);
148 }
149
150 component_unbind_all(dev->dev, dev);
151
152 dev->dev_private = NULL;
153
154 kfree(priv);
155
156 return 0;
157}
158
159static int get_mdp_ver(struct platform_device *pdev)
160{
161#ifdef CONFIG_OF
162 const static struct of_device_id match_types[] = { {
163 .compatible = "qcom,mdss_mdp",
164 .data = (void *)5,
165 }, {
166 /* end node */
167 } };
168 struct device *dev = &pdev->dev;
169 const struct of_device_id *match;
170 match = of_match_node(match_types, dev->of_node);
171 if (match)
172 return (int)match->data;
173#endif
174 return 4;
175}
176
177static int msm_load(struct drm_device *dev, unsigned long flags)
178{
179 struct platform_device *pdev = dev->platformdev;
180 struct msm_drm_private *priv;
181 struct msm_kms *kms;
182 int ret;
183
184
185 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
186 if (!priv) {
187 dev_err(dev->dev, "failed to allocate private data\n");
188 return -ENOMEM;
189 }
190
191 dev->dev_private = priv;
192
193 priv->wq = alloc_ordered_workqueue("msm", 0);
194 init_waitqueue_head(&priv->fence_event);
195
196 INIT_LIST_HEAD(&priv->inactive_list);
197 INIT_LIST_HEAD(&priv->fence_cbs);
198
199 drm_mode_config_init(dev);
200
201 /* if we have no IOMMU, then we need to use carveout allocator.
202 * Grab the entire CMA chunk carved out in early startup in
203 * mach-msm:
204 */
205 if (!iommu_present(&platform_bus_type)) {
206 DEFINE_DMA_ATTRS(attrs);
207 unsigned long size;
208 void *p;
209
210 DBG("using %s VRAM carveout", vram);
211 size = memparse(vram, NULL);
212 priv->vram.size = size;
213
214 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
215
216 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
217 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
218
219 /* note that for no-kernel-mapping, the vaddr returned
220 * is bogus, but non-null if allocation succeeded:
221 */
222 p = dma_alloc_attrs(dev->dev, size,
223 &priv->vram.paddr, 0, &attrs);
224 if (!p) {
225 dev_err(dev->dev, "failed to allocate VRAM\n");
226 priv->vram.paddr = 0;
227 ret = -ENOMEM;
228 goto fail;
229 }
230
231 dev_info(dev->dev, "VRAM: %08x->%08x\n",
232 (uint32_t)priv->vram.paddr,
233 (uint32_t)(priv->vram.paddr + size));
234 }
235
236 platform_set_drvdata(pdev, dev);
237
238 /* Bind all our sub-components: */
239 ret = component_bind_all(dev->dev, dev);
240 if (ret)
241 return ret;
242
243 switch (get_mdp_ver(pdev)) {
244 case 4:
245 kms = mdp4_kms_init(dev);
246 break;
247 case 5:
248 kms = mdp5_kms_init(dev);
249 break;
250 default:
251 kms = ERR_PTR(-ENODEV);
252 break;
253 }
254
255 if (IS_ERR(kms)) {
256 /*
257 * NOTE: once we have GPU support, having no kms should not
258 * be considered fatal.. ideally we would still support gpu
259 * and (for example) use dmabuf/prime to share buffers with
260 * imx drm driver on iMX5
261 */
262 dev_err(dev->dev, "failed to load kms\n");
263 ret = PTR_ERR(kms);
264 goto fail;
265 }
266
267 priv->kms = kms;
268
269 if (kms) {
270 pm_runtime_enable(dev->dev);
271 ret = kms->funcs->hw_init(kms);
272 if (ret) {
273 dev_err(dev->dev, "kms hw init failed: %d\n", ret);
274 goto fail;
275 }
276 }
277
278 dev->mode_config.min_width = 0;
279 dev->mode_config.min_height = 0;
280 dev->mode_config.max_width = 2048;
281 dev->mode_config.max_height = 2048;
282 dev->mode_config.funcs = &mode_config_funcs;
283
284 ret = drm_vblank_init(dev, 1);
285 if (ret < 0) {
286 dev_err(dev->dev, "failed to initialize vblank\n");
287 goto fail;
288 }
289
290 pm_runtime_get_sync(dev->dev);
291 ret = drm_irq_install(dev);
292 pm_runtime_put_sync(dev->dev);
293 if (ret < 0) {
294 dev_err(dev->dev, "failed to install IRQ handler\n");
295 goto fail;
296 }
297
298#ifdef CONFIG_DRM_MSM_FBDEV
299 priv->fbdev = msm_fbdev_init(dev);
300#endif
301
302 drm_kms_helper_poll_init(dev);
303
304 return 0;
305
306fail:
307 msm_unload(dev);
308 return ret;
309}
310
311static void load_gpu(struct drm_device *dev)
312{
313 struct msm_drm_private *priv = dev->dev_private;
314 struct msm_gpu *gpu;
315
316 if (priv->gpu)
317 return;
318
319 mutex_lock(&dev->struct_mutex);
320 gpu = a3xx_gpu_init(dev);
321 if (IS_ERR(gpu)) {
322 dev_warn(dev->dev, "failed to load a3xx gpu\n");
323 gpu = NULL;
324 /* not fatal */
325 }
326
327 if (gpu) {
328 int ret;
329 gpu->funcs->pm_resume(gpu);
330 ret = gpu->funcs->hw_init(gpu);
331 if (ret) {
332 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
333 gpu->funcs->destroy(gpu);
334 gpu = NULL;
335 } else {
336 /* give inactive pm a chance to kick in: */
337 msm_gpu_retire(gpu);
338 }
339
340 }
341
342 priv->gpu = gpu;
343
344 mutex_unlock(&dev->struct_mutex);
345}
346
347static int msm_open(struct drm_device *dev, struct drm_file *file)
348{
349 struct msm_file_private *ctx;
350
351 /* For now, load gpu on open.. to avoid the requirement of having
352 * firmware in the initrd.
353 */
354 load_gpu(dev);
355
356 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
357 if (!ctx)
358 return -ENOMEM;
359
360 file->driver_priv = ctx;
361
362 return 0;
363}
364
365static void msm_preclose(struct drm_device *dev, struct drm_file *file)
366{
367 struct msm_drm_private *priv = dev->dev_private;
368 struct msm_file_private *ctx = file->driver_priv;
369 struct msm_kms *kms = priv->kms;
370
371 if (kms)
372 kms->funcs->preclose(kms, file);
373
374 mutex_lock(&dev->struct_mutex);
375 if (ctx == priv->lastctx)
376 priv->lastctx = NULL;
377 mutex_unlock(&dev->struct_mutex);
378
379 kfree(ctx);
380}
381
382static void msm_lastclose(struct drm_device *dev)
383{
384 struct msm_drm_private *priv = dev->dev_private;
385 if (priv->fbdev) {
386 drm_modeset_lock_all(dev);
387 drm_fb_helper_restore_fbdev_mode(priv->fbdev);
388 drm_modeset_unlock_all(dev);
389 }
390}
391
392static irqreturn_t msm_irq(int irq, void *arg)
393{
394 struct drm_device *dev = arg;
395 struct msm_drm_private *priv = dev->dev_private;
396 struct msm_kms *kms = priv->kms;
397 BUG_ON(!kms);
398 return kms->funcs->irq(kms);
399}
400
401static void msm_irq_preinstall(struct drm_device *dev)
402{
403 struct msm_drm_private *priv = dev->dev_private;
404 struct msm_kms *kms = priv->kms;
405 BUG_ON(!kms);
406 kms->funcs->irq_preinstall(kms);
407}
408
409static int msm_irq_postinstall(struct drm_device *dev)
410{
411 struct msm_drm_private *priv = dev->dev_private;
412 struct msm_kms *kms = priv->kms;
413 BUG_ON(!kms);
414 return kms->funcs->irq_postinstall(kms);
415}
416
417static void msm_irq_uninstall(struct drm_device *dev)
418{
419 struct msm_drm_private *priv = dev->dev_private;
420 struct msm_kms *kms = priv->kms;
421 BUG_ON(!kms);
422 kms->funcs->irq_uninstall(kms);
423}
424
425static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
426{
427 struct msm_drm_private *priv = dev->dev_private;
428 struct msm_kms *kms = priv->kms;
429 if (!kms)
430 return -ENXIO;
431 DBG("dev=%p, crtc=%d", dev, crtc_id);
432 return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
433}
434
435static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
436{
437 struct msm_drm_private *priv = dev->dev_private;
438 struct msm_kms *kms = priv->kms;
439 if (!kms)
440 return;
441 DBG("dev=%p, crtc=%d", dev, crtc_id);
442 kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
443}
444
445/*
446 * DRM debugfs:
447 */
448
449#ifdef CONFIG_DEBUG_FS
450static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
451{
452 struct msm_drm_private *priv = dev->dev_private;
453 struct msm_gpu *gpu = priv->gpu;
454
455 if (gpu) {
456 seq_printf(m, "%s Status:\n", gpu->name);
457 gpu->funcs->show(gpu, m);
458 }
459
460 return 0;
461}
462
463static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
464{
465 struct msm_drm_private *priv = dev->dev_private;
466 struct msm_gpu *gpu = priv->gpu;
467
468 if (gpu) {
469 seq_printf(m, "Active Objects (%s):\n", gpu->name);
470 msm_gem_describe_objects(&gpu->active_list, m);
471 }
472
473 seq_printf(m, "Inactive Objects:\n");
474 msm_gem_describe_objects(&priv->inactive_list, m);
475
476 return 0;
477}
478
479static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
480{
481 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
482}
483
484static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
485{
486 struct msm_drm_private *priv = dev->dev_private;
487 struct drm_framebuffer *fb, *fbdev_fb = NULL;
488
489 if (priv->fbdev) {
490 seq_printf(m, "fbcon ");
491 fbdev_fb = priv->fbdev->fb;
492 msm_framebuffer_describe(fbdev_fb, m);
493 }
494
495 mutex_lock(&dev->mode_config.fb_lock);
496 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
497 if (fb == fbdev_fb)
498 continue;
499
500 seq_printf(m, "user ");
501 msm_framebuffer_describe(fb, m);
502 }
503 mutex_unlock(&dev->mode_config.fb_lock);
504
505 return 0;
506}
507
508static int show_locked(struct seq_file *m, void *arg)
509{
510 struct drm_info_node *node = (struct drm_info_node *) m->private;
511 struct drm_device *dev = node->minor->dev;
512 int (*show)(struct drm_device *dev, struct seq_file *m) =
513 node->info_ent->data;
514 int ret;
515
516 ret = mutex_lock_interruptible(&dev->struct_mutex);
517 if (ret)
518 return ret;
519
520 ret = show(dev, m);
521
522 mutex_unlock(&dev->struct_mutex);
523
524 return ret;
525}
526
527static struct drm_info_list msm_debugfs_list[] = {
528 {"gpu", show_locked, 0, msm_gpu_show},
529 {"gem", show_locked, 0, msm_gem_show},
530 { "mm", show_locked, 0, msm_mm_show },
531 { "fb", show_locked, 0, msm_fb_show },
532};
533
534static int msm_debugfs_init(struct drm_minor *minor)
535{
536 struct drm_device *dev = minor->dev;
537 int ret;
538
539 ret = drm_debugfs_create_files(msm_debugfs_list,
540 ARRAY_SIZE(msm_debugfs_list),
541 minor->debugfs_root, minor);
542
543 if (ret) {
544 dev_err(dev->dev, "could not install msm_debugfs_list\n");
545 return ret;
546 }
547
548 return ret;
549}
550
551static void msm_debugfs_cleanup(struct drm_minor *minor)
552{
553 drm_debugfs_remove_files(msm_debugfs_list,
554 ARRAY_SIZE(msm_debugfs_list), minor);
555}
556#endif
557
558/*
559 * Fences:
560 */
561
562int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
563 struct timespec *timeout)
564{
565 struct msm_drm_private *priv = dev->dev_private;
566 int ret;
567
568 if (!priv->gpu)
569 return 0;
570
571 if (fence > priv->gpu->submitted_fence) {
572 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
573 fence, priv->gpu->submitted_fence);
574 return -EINVAL;
575 }
576
577 if (!timeout) {
578 /* no-wait: */
579 ret = fence_completed(dev, fence) ? 0 : -EBUSY;
580 } else {
581 unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
582 unsigned long start_jiffies = jiffies;
583 unsigned long remaining_jiffies;
584
585 if (time_after(start_jiffies, timeout_jiffies))
586 remaining_jiffies = 0;
587 else
588 remaining_jiffies = timeout_jiffies - start_jiffies;
589
590 ret = wait_event_interruptible_timeout(priv->fence_event,
591 fence_completed(dev, fence),
592 remaining_jiffies);
593
594 if (ret == 0) {
595 DBG("timeout waiting for fence: %u (completed: %u)",
596 fence, priv->completed_fence);
597 ret = -ETIMEDOUT;
598 } else if (ret != -ERESTARTSYS) {
599 ret = 0;
600 }
601 }
602
603 return ret;
604}
605
606/* called from workqueue */
607void msm_update_fence(struct drm_device *dev, uint32_t fence)
608{
609 struct msm_drm_private *priv = dev->dev_private;
610
611 mutex_lock(&dev->struct_mutex);
612 priv->completed_fence = max(fence, priv->completed_fence);
613
614 while (!list_empty(&priv->fence_cbs)) {
615 struct msm_fence_cb *cb;
616
617 cb = list_first_entry(&priv->fence_cbs,
618 struct msm_fence_cb, work.entry);
619
620 if (cb->fence > priv->completed_fence)
621 break;
622
623 list_del_init(&cb->work.entry);
624 queue_work(priv->wq, &cb->work);
625 }
626
627 mutex_unlock(&dev->struct_mutex);
628
629 wake_up_all(&priv->fence_event);
630}
631
632void __msm_fence_worker(struct work_struct *work)
633{
634 struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
635 cb->func(cb);
636}
637
638/*
639 * DRM ioctls:
640 */
641
642static int msm_ioctl_get_param(struct drm_device *dev, void *data,
643 struct drm_file *file)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct drm_msm_param *args = data;
647 struct msm_gpu *gpu;
648
649 /* for now, we just have 3d pipe.. eventually this would need to
650 * be more clever to dispatch to appropriate gpu module:
651 */
652 if (args->pipe != MSM_PIPE_3D0)
653 return -EINVAL;
654
655 gpu = priv->gpu;
656
657 if (!gpu)
658 return -ENXIO;
659
660 return gpu->funcs->get_param(gpu, args->param, &args->value);
661}
662
663static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
664 struct drm_file *file)
665{
666 struct drm_msm_gem_new *args = data;
667
668 if (args->flags & ~MSM_BO_FLAGS) {
669 DRM_ERROR("invalid flags: %08x\n", args->flags);
670 return -EINVAL;
671 }
672
673 return msm_gem_new_handle(dev, file, args->size,
674 args->flags, &args->handle);
675}
676
677#define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
678
679static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
680 struct drm_file *file)
681{
682 struct drm_msm_gem_cpu_prep *args = data;
683 struct drm_gem_object *obj;
684 int ret;
685
686 if (args->op & ~MSM_PREP_FLAGS) {
687 DRM_ERROR("invalid op: %08x\n", args->op);
688 return -EINVAL;
689 }
690
691 obj = drm_gem_object_lookup(dev, file, args->handle);
692 if (!obj)
693 return -ENOENT;
694
695 ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
696
697 drm_gem_object_unreference_unlocked(obj);
698
699 return ret;
700}
701
702static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
703 struct drm_file *file)
704{
705 struct drm_msm_gem_cpu_fini *args = data;
706 struct drm_gem_object *obj;
707 int ret;
708
709 obj = drm_gem_object_lookup(dev, file, args->handle);
710 if (!obj)
711 return -ENOENT;
712
713 ret = msm_gem_cpu_fini(obj);
714
715 drm_gem_object_unreference_unlocked(obj);
716
717 return ret;
718}
719
720static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
721 struct drm_file *file)
722{
723 struct drm_msm_gem_info *args = data;
724 struct drm_gem_object *obj;
725 int ret = 0;
726
727 if (args->pad)
728 return -EINVAL;
729
730 obj = drm_gem_object_lookup(dev, file, args->handle);
731 if (!obj)
732 return -ENOENT;
733
734 args->offset = msm_gem_mmap_offset(obj);
735
736 drm_gem_object_unreference_unlocked(obj);
737
738 return ret;
739}
740
741static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
742 struct drm_file *file)
743{
744 struct drm_msm_wait_fence *args = data;
745
746 if (args->pad) {
747 DRM_ERROR("invalid pad: %08x\n", args->pad);
748 return -EINVAL;
749 }
750
751 return msm_wait_fence_interruptable(dev, args->fence,
752 &TS(args->timeout));
753}
754
755static const struct drm_ioctl_desc msm_ioctls[] = {
756 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
757 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
758 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
759 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
760 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
761 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
762 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
763};
764
765static const struct vm_operations_struct vm_ops = {
766 .fault = msm_gem_fault,
767 .open = drm_gem_vm_open,
768 .close = drm_gem_vm_close,
769};
770
771static const struct file_operations fops = {
772 .owner = THIS_MODULE,
773 .open = drm_open,
774 .release = drm_release,
775 .unlocked_ioctl = drm_ioctl,
776#ifdef CONFIG_COMPAT
777 .compat_ioctl = drm_compat_ioctl,
778#endif
779 .poll = drm_poll,
780 .read = drm_read,
781 .llseek = no_llseek,
782 .mmap = msm_gem_mmap,
783};
784
785static struct drm_driver msm_driver = {
786 .driver_features = DRIVER_HAVE_IRQ |
787 DRIVER_GEM |
788 DRIVER_PRIME |
789 DRIVER_RENDER |
790 DRIVER_MODESET,
791 .load = msm_load,
792 .unload = msm_unload,
793 .open = msm_open,
794 .preclose = msm_preclose,
795 .lastclose = msm_lastclose,
796 .irq_handler = msm_irq,
797 .irq_preinstall = msm_irq_preinstall,
798 .irq_postinstall = msm_irq_postinstall,
799 .irq_uninstall = msm_irq_uninstall,
800 .get_vblank_counter = drm_vblank_count,
801 .enable_vblank = msm_enable_vblank,
802 .disable_vblank = msm_disable_vblank,
803 .gem_free_object = msm_gem_free_object,
804 .gem_vm_ops = &vm_ops,
805 .dumb_create = msm_gem_dumb_create,
806 .dumb_map_offset = msm_gem_dumb_map_offset,
807 .dumb_destroy = drm_gem_dumb_destroy,
808 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
809 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
810 .gem_prime_export = drm_gem_prime_export,
811 .gem_prime_import = drm_gem_prime_import,
812 .gem_prime_pin = msm_gem_prime_pin,
813 .gem_prime_unpin = msm_gem_prime_unpin,
814 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
815 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
816 .gem_prime_vmap = msm_gem_prime_vmap,
817 .gem_prime_vunmap = msm_gem_prime_vunmap,
818#ifdef CONFIG_DEBUG_FS
819 .debugfs_init = msm_debugfs_init,
820 .debugfs_cleanup = msm_debugfs_cleanup,
821#endif
822 .ioctls = msm_ioctls,
823 .num_ioctls = DRM_MSM_NUM_IOCTLS,
824 .fops = &fops,
825 .name = "msm",
826 .desc = "MSM Snapdragon DRM",
827 .date = "20130625",
828 .major = 1,
829 .minor = 0,
830};
831
832#ifdef CONFIG_PM_SLEEP
833static int msm_pm_suspend(struct device *dev)
834{
835 struct drm_device *ddev = dev_get_drvdata(dev);
836
837 drm_kms_helper_poll_disable(ddev);
838
839 return 0;
840}
841
842static int msm_pm_resume(struct device *dev)
843{
844 struct drm_device *ddev = dev_get_drvdata(dev);
845
846 drm_kms_helper_poll_enable(ddev);
847
848 return 0;
849}
850#endif
851
852static const struct dev_pm_ops msm_pm_ops = {
853 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
854};
855
856/*
857 * Componentized driver support:
858 */
859
860#ifdef CONFIG_OF
861/* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx
862 * (or probably any other).. so probably some room for some helpers
863 */
864static int compare_of(struct device *dev, void *data)
865{
866 return dev->of_node == data;
867}
868
869static int msm_drm_add_components(struct device *master, struct master *m)
870{
871 struct device_node *np = master->of_node;
872 unsigned i;
873 int ret;
874
875 for (i = 0; ; i++) {
876 struct device_node *node;
877
878 node = of_parse_phandle(np, "connectors", i);
879 if (!node)
880 break;
881
882 ret = component_master_add_child(m, compare_of, node);
883 of_node_put(node);
884
885 if (ret)
886 return ret;
887 }
888 return 0;
889}
890#else
891static int compare_dev(struct device *dev, void *data)
892{
893 return dev == data;
894}
895
896static int msm_drm_add_components(struct device *master, struct master *m)
897{
898 /* For non-DT case, it kinda sucks. We don't actually have a way
899 * to know whether or not we are waiting for certain devices (or if
900 * they are simply not present). But for non-DT we only need to
901 * care about apq8064/apq8060/etc (all mdp4/a3xx):
902 */
903 static const char *devnames[] = {
904 "hdmi_msm.0", "kgsl-3d0.0",
905 };
906 int i;
907
908 DBG("Adding components..");
909
910 for (i = 0; i < ARRAY_SIZE(devnames); i++) {
911 struct device *dev;
912 int ret;
913
914 dev = bus_find_device_by_name(&platform_bus_type,
915 NULL, devnames[i]);
916 if (!dev) {
917 dev_info(master, "still waiting for %s\n", devnames[i]);
918 return -EPROBE_DEFER;
919 }
920
921 ret = component_master_add_child(m, compare_dev, dev);
922 if (ret) {
923 DBG("could not add child: %d", ret);
924 return ret;
925 }
926 }
927
928 return 0;
929}
930#endif
931
932static int msm_drm_bind(struct device *dev)
933{
934 return drm_platform_init(&msm_driver, to_platform_device(dev));
935}
936
937static void msm_drm_unbind(struct device *dev)
938{
939 drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
940}
941
942static const struct component_master_ops msm_drm_ops = {
943 .add_components = msm_drm_add_components,
944 .bind = msm_drm_bind,
945 .unbind = msm_drm_unbind,
946};
947
948/*
949 * Platform driver:
950 */
951
952static int msm_pdev_probe(struct platform_device *pdev)
953{
954 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
955 return component_master_add(&pdev->dev, &msm_drm_ops);
956}
957
958static int msm_pdev_remove(struct platform_device *pdev)
959{
960 component_master_del(&pdev->dev, &msm_drm_ops);
961
962 return 0;
963}
964
965static const struct platform_device_id msm_id[] = {
966 { "mdp", 0 },
967 { }
968};
969
970static const struct of_device_id dt_match[] = {
971 { .compatible = "qcom,mdss_mdp" },
972 {}
973};
974MODULE_DEVICE_TABLE(of, dt_match);
975
976static struct platform_driver msm_platform_driver = {
977 .probe = msm_pdev_probe,
978 .remove = msm_pdev_remove,
979 .driver = {
980 .owner = THIS_MODULE,
981 .name = "msm",
982 .of_match_table = dt_match,
983 .pm = &msm_pm_ops,
984 },
985 .id_table = msm_id,
986};
987
988static int __init msm_drm_register(void)
989{
990 DBG("init");
991 hdmi_register();
992 a3xx_register();
993 return platform_driver_register(&msm_platform_driver);
994}
995
996static void __exit msm_drm_unregister(void)
997{
998 DBG("fini");
999 platform_driver_unregister(&msm_platform_driver);
1000 hdmi_unregister();
1001 a3xx_unregister();
1002}
1003
1004module_init(msm_drm_register);
1005module_exit(msm_drm_unregister);
1006
1007MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1008MODULE_DESCRIPTION("MSM DRM Driver");
1009MODULE_LICENSE("GPL");