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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/pci.h>
30
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_gem.h>
34#include <drm/drm_gem_vram_helper.h>
35
36#include "ast_drv.h"
37
38void ast_set_index_reg_mask(struct ast_private *ast,
39 uint32_t base, uint8_t index,
40 uint8_t mask, uint8_t val)
41{
42 u8 tmp;
43 ast_io_write8(ast, base, index);
44 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
45 ast_set_index_reg(ast, base, index, tmp);
46}
47
48uint8_t ast_get_index_reg(struct ast_private *ast,
49 uint32_t base, uint8_t index)
50{
51 uint8_t ret;
52 ast_io_write8(ast, base, index);
53 ret = ast_io_read8(ast, base + 1);
54 return ret;
55}
56
57uint8_t ast_get_index_reg_mask(struct ast_private *ast,
58 uint32_t base, uint8_t index, uint8_t mask)
59{
60 uint8_t ret;
61 ast_io_write8(ast, base, index);
62 ret = ast_io_read8(ast, base + 1) & mask;
63 return ret;
64}
65
66static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
67{
68 struct device_node *np = dev->pdev->dev.of_node;
69 struct ast_private *ast = to_ast_private(dev);
70 uint32_t data, jregd0, jregd1;
71
72 /* Defaults */
73 ast->config_mode = ast_use_defaults;
74 *scu_rev = 0xffffffff;
75
76 /* Check if we have device-tree properties */
77 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
78 scu_rev)) {
79 /* We do, disable P2A access */
80 ast->config_mode = ast_use_dt;
81 drm_info(dev, "Using device-tree for configuration\n");
82 return;
83 }
84
85 /* Not all families have a P2A bridge */
86 if (dev->pdev->device != PCI_CHIP_AST2000)
87 return;
88
89 /*
90 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
91 * is disabled. We force using P2A if VGA only mode bit
92 * is set D[7]
93 */
94 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
95 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
96 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
97 /* Double check it's actually working */
98 data = ast_read32(ast, 0xf004);
99 if (data != 0xFFFFFFFF) {
100 /* P2A works, grab silicon revision */
101 ast->config_mode = ast_use_p2a;
102
103 drm_info(dev, "Using P2A bridge for configuration\n");
104
105 /* Read SCU7c (silicon revision register) */
106 ast_write32(ast, 0xf004, 0x1e6e0000);
107 ast_write32(ast, 0xf000, 0x1);
108 *scu_rev = ast_read32(ast, 0x1207c);
109 return;
110 }
111 }
112
113 /* We have a P2A bridge but it's disabled */
114 drm_info(dev, "P2A bridge disabled, using default configuration\n");
115}
116
117static int ast_detect_chip(struct drm_device *dev, bool *need_post)
118{
119 struct ast_private *ast = to_ast_private(dev);
120 uint32_t jreg, scu_rev;
121
122 /*
123 * If VGA isn't enabled, we need to enable now or subsequent
124 * access to the scratch registers will fail. We also inform
125 * our caller that it needs to POST the chip
126 * (Assumption: VGA not enabled -> need to POST)
127 */
128 if (!ast_is_vga_enabled(dev)) {
129 ast_enable_vga(dev);
130 drm_info(dev, "VGA not enabled on entry, requesting chip POST\n");
131 *need_post = true;
132 } else
133 *need_post = false;
134
135
136 /* Enable extended register access */
137 ast_open_key(ast);
138 ast_enable_mmio(dev);
139
140 /* Find out whether P2A works or whether to use device-tree */
141 ast_detect_config_mode(dev, &scu_rev);
142
143 /* Identify chipset */
144 if (dev->pdev->revision >= 0x40) {
145 ast->chip = AST2500;
146 drm_info(dev, "AST 2500 detected\n");
147 } else if (dev->pdev->revision >= 0x30) {
148 ast->chip = AST2400;
149 drm_info(dev, "AST 2400 detected\n");
150 } else if (dev->pdev->revision >= 0x20) {
151 ast->chip = AST2300;
152 drm_info(dev, "AST 2300 detected\n");
153 } else if (dev->pdev->revision >= 0x10) {
154 switch (scu_rev & 0x0300) {
155 case 0x0200:
156 ast->chip = AST1100;
157 drm_info(dev, "AST 1100 detected\n");
158 break;
159 case 0x0100:
160 ast->chip = AST2200;
161 drm_info(dev, "AST 2200 detected\n");
162 break;
163 case 0x0000:
164 ast->chip = AST2150;
165 drm_info(dev, "AST 2150 detected\n");
166 break;
167 default:
168 ast->chip = AST2100;
169 drm_info(dev, "AST 2100 detected\n");
170 break;
171 }
172 ast->vga2_clone = false;
173 } else {
174 ast->chip = AST2000;
175 drm_info(dev, "AST 2000 detected\n");
176 }
177
178 /* Check if we support wide screen */
179 switch (ast->chip) {
180 case AST2000:
181 ast->support_wide_screen = false;
182 break;
183 default:
184 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
185 if (!(jreg & 0x80))
186 ast->support_wide_screen = true;
187 else if (jreg & 0x01)
188 ast->support_wide_screen = true;
189 else {
190 ast->support_wide_screen = false;
191 if (ast->chip == AST2300 &&
192 (scu_rev & 0x300) == 0x0) /* ast1300 */
193 ast->support_wide_screen = true;
194 if (ast->chip == AST2400 &&
195 (scu_rev & 0x300) == 0x100) /* ast1400 */
196 ast->support_wide_screen = true;
197 if (ast->chip == AST2500 &&
198 scu_rev == 0x100) /* ast2510 */
199 ast->support_wide_screen = true;
200 }
201 break;
202 }
203
204 /* Check 3rd Tx option (digital output afaik) */
205 ast->tx_chip_type = AST_TX_NONE;
206
207 /*
208 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
209 * enabled, in that case, assume we have a SIL164 TMDS transmitter
210 *
211 * Don't make that assumption if we the chip wasn't enabled and
212 * is at power-on reset, otherwise we'll incorrectly "detect" a
213 * SIL164 when there is none.
214 */
215 if (!*need_post) {
216 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
217 if (jreg & 0x80)
218 ast->tx_chip_type = AST_TX_SIL164;
219 }
220
221 if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
222 /*
223 * On AST2300 and 2400, look the configuration set by the SoC in
224 * the SOC scratch register #1 bits 11:8 (interestingly marked
225 * as "reserved" in the spec)
226 */
227 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
228 switch (jreg) {
229 case 0x04:
230 ast->tx_chip_type = AST_TX_SIL164;
231 break;
232 case 0x08:
233 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
234 if (ast->dp501_fw_addr) {
235 /* backup firmware */
236 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
237 kfree(ast->dp501_fw_addr);
238 ast->dp501_fw_addr = NULL;
239 }
240 }
241 fallthrough;
242 case 0x0c:
243 ast->tx_chip_type = AST_TX_DP501;
244 }
245 }
246
247 /* Print stuff for diagnostic purposes */
248 switch(ast->tx_chip_type) {
249 case AST_TX_SIL164:
250 drm_info(dev, "Using Sil164 TMDS transmitter\n");
251 break;
252 case AST_TX_DP501:
253 drm_info(dev, "Using DP501 DisplayPort transmitter\n");
254 break;
255 default:
256 drm_info(dev, "Analog VGA only\n");
257 }
258 return 0;
259}
260
261static int ast_get_dram_info(struct drm_device *dev)
262{
263 struct device_node *np = dev->pdev->dev.of_node;
264 struct ast_private *ast = to_ast_private(dev);
265 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
266 uint32_t denum, num, div, ref_pll, dsel;
267
268 switch (ast->config_mode) {
269 case ast_use_dt:
270 /*
271 * If some properties are missing, use reasonable
272 * defaults for AST2400
273 */
274 if (of_property_read_u32(np, "aspeed,mcr-configuration",
275 &mcr_cfg))
276 mcr_cfg = 0x00000577;
277 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
278 &mcr_scu_mpll))
279 mcr_scu_mpll = 0x000050C0;
280 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
281 &mcr_scu_strap))
282 mcr_scu_strap = 0;
283 break;
284 case ast_use_p2a:
285 ast_write32(ast, 0xf004, 0x1e6e0000);
286 ast_write32(ast, 0xf000, 0x1);
287 mcr_cfg = ast_read32(ast, 0x10004);
288 mcr_scu_mpll = ast_read32(ast, 0x10120);
289 mcr_scu_strap = ast_read32(ast, 0x10170);
290 break;
291 case ast_use_defaults:
292 default:
293 ast->dram_bus_width = 16;
294 ast->dram_type = AST_DRAM_1Gx16;
295 if (ast->chip == AST2500)
296 ast->mclk = 800;
297 else
298 ast->mclk = 396;
299 return 0;
300 }
301
302 if (mcr_cfg & 0x40)
303 ast->dram_bus_width = 16;
304 else
305 ast->dram_bus_width = 32;
306
307 if (ast->chip == AST2500) {
308 switch (mcr_cfg & 0x03) {
309 case 0:
310 ast->dram_type = AST_DRAM_1Gx16;
311 break;
312 default:
313 case 1:
314 ast->dram_type = AST_DRAM_2Gx16;
315 break;
316 case 2:
317 ast->dram_type = AST_DRAM_4Gx16;
318 break;
319 case 3:
320 ast->dram_type = AST_DRAM_8Gx16;
321 break;
322 }
323 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
324 switch (mcr_cfg & 0x03) {
325 case 0:
326 ast->dram_type = AST_DRAM_512Mx16;
327 break;
328 default:
329 case 1:
330 ast->dram_type = AST_DRAM_1Gx16;
331 break;
332 case 2:
333 ast->dram_type = AST_DRAM_2Gx16;
334 break;
335 case 3:
336 ast->dram_type = AST_DRAM_4Gx16;
337 break;
338 }
339 } else {
340 switch (mcr_cfg & 0x0c) {
341 case 0:
342 case 4:
343 ast->dram_type = AST_DRAM_512Mx16;
344 break;
345 case 8:
346 if (mcr_cfg & 0x40)
347 ast->dram_type = AST_DRAM_1Gx16;
348 else
349 ast->dram_type = AST_DRAM_512Mx32;
350 break;
351 case 0xc:
352 ast->dram_type = AST_DRAM_1Gx32;
353 break;
354 }
355 }
356
357 if (mcr_scu_strap & 0x2000)
358 ref_pll = 14318;
359 else
360 ref_pll = 12000;
361
362 denum = mcr_scu_mpll & 0x1f;
363 num = (mcr_scu_mpll & 0x3fe0) >> 5;
364 dsel = (mcr_scu_mpll & 0xc000) >> 14;
365 switch (dsel) {
366 case 3:
367 div = 0x4;
368 break;
369 case 2:
370 case 1:
371 div = 0x2;
372 break;
373 default:
374 div = 0x1;
375 break;
376 }
377 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
378 return 0;
379}
380
381int ast_driver_load(struct drm_device *dev, unsigned long flags)
382{
383 struct ast_private *ast;
384 bool need_post;
385 int ret = 0;
386
387 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
388 if (!ast)
389 return -ENOMEM;
390
391 dev->dev_private = ast;
392 ast->dev = dev;
393
394 ast->regs = pci_iomap(dev->pdev, 1, 0);
395 if (!ast->regs) {
396 ret = -EIO;
397 goto out_free;
398 }
399
400 /*
401 * If we don't have IO space at all, use MMIO now and
402 * assume the chip has MMIO enabled by default (rev 0x20
403 * and higher).
404 */
405 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
406 drm_info(dev, "platform has no IO space, trying MMIO\n");
407 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
408 }
409
410 /* "map" IO regs if the above hasn't done so already */
411 if (!ast->ioregs) {
412 ast->ioregs = pci_iomap(dev->pdev, 2, 0);
413 if (!ast->ioregs) {
414 ret = -EIO;
415 goto out_free;
416 }
417 }
418
419 ast_detect_chip(dev, &need_post);
420
421 ret = ast_get_dram_info(dev);
422 if (ret)
423 goto out_free;
424 drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
425 ast->mclk, ast->dram_type, ast->dram_bus_width);
426
427 if (need_post)
428 ast_post_gpu(dev);
429
430 ret = ast_mm_init(ast);
431 if (ret)
432 goto out_free;
433
434 ret = ast_mode_config_init(ast);
435 if (ret)
436 goto out_free;
437
438 return 0;
439out_free:
440 kfree(ast);
441 dev->dev_private = NULL;
442 return ret;
443}
444
445void ast_driver_unload(struct drm_device *dev)
446{
447 struct ast_private *ast = to_ast_private(dev);
448
449 /* enable standard VGA decode */
450 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04);
451
452 ast_release_firmware(dev);
453 kfree(ast->dp501_fw_addr);
454
455 kfree(ast);
456}
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28#include <drm/drmP.h>
29#include "ast_drv.h"
30
31
32#include <drm/drm_fb_helper.h>
33#include <drm/drm_crtc_helper.h>
34
35void ast_set_index_reg_mask(struct ast_private *ast,
36 uint32_t base, uint8_t index,
37 uint8_t mask, uint8_t val)
38{
39 u8 tmp;
40 ast_io_write8(ast, base, index);
41 tmp = (ast_io_read8(ast, base + 1) & mask) | val;
42 ast_set_index_reg(ast, base, index, tmp);
43}
44
45uint8_t ast_get_index_reg(struct ast_private *ast,
46 uint32_t base, uint8_t index)
47{
48 uint8_t ret;
49 ast_io_write8(ast, base, index);
50 ret = ast_io_read8(ast, base + 1);
51 return ret;
52}
53
54uint8_t ast_get_index_reg_mask(struct ast_private *ast,
55 uint32_t base, uint8_t index, uint8_t mask)
56{
57 uint8_t ret;
58 ast_io_write8(ast, base, index);
59 ret = ast_io_read8(ast, base + 1) & mask;
60 return ret;
61}
62
63static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
64{
65 struct device_node *np = dev->pdev->dev.of_node;
66 struct ast_private *ast = dev->dev_private;
67 uint32_t data, jregd0, jregd1;
68
69 /* Defaults */
70 ast->config_mode = ast_use_defaults;
71 *scu_rev = 0xffffffff;
72
73 /* Check if we have device-tree properties */
74 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id",
75 scu_rev)) {
76 /* We do, disable P2A access */
77 ast->config_mode = ast_use_dt;
78 DRM_INFO("Using device-tree for configuration\n");
79 return;
80 }
81
82 /* Not all families have a P2A bridge */
83 if (dev->pdev->device != PCI_CHIP_AST2000)
84 return;
85
86 /*
87 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
88 * is disabled. We force using P2A if VGA only mode bit
89 * is set D[7]
90 */
91 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
92 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
93 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
94 /* Double check it's actually working */
95 data = ast_read32(ast, 0xf004);
96 if (data != 0xFFFFFFFF) {
97 /* P2A works, grab silicon revision */
98 ast->config_mode = ast_use_p2a;
99
100 DRM_INFO("Using P2A bridge for configuration\n");
101
102 /* Read SCU7c (silicon revision register) */
103 ast_write32(ast, 0xf004, 0x1e6e0000);
104 ast_write32(ast, 0xf000, 0x1);
105 *scu_rev = ast_read32(ast, 0x1207c);
106 return;
107 }
108 }
109
110 /* We have a P2A bridge but it's disabled */
111 DRM_INFO("P2A bridge disabled, using default configuration\n");
112}
113
114static int ast_detect_chip(struct drm_device *dev, bool *need_post)
115{
116 struct ast_private *ast = dev->dev_private;
117 uint32_t jreg, scu_rev;
118
119 /*
120 * If VGA isn't enabled, we need to enable now or subsequent
121 * access to the scratch registers will fail. We also inform
122 * our caller that it needs to POST the chip
123 * (Assumption: VGA not enabled -> need to POST)
124 */
125 if (!ast_is_vga_enabled(dev)) {
126 ast_enable_vga(dev);
127 DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
128 *need_post = true;
129 } else
130 *need_post = false;
131
132
133 /* Enable extended register access */
134 ast_enable_mmio(dev);
135 ast_open_key(ast);
136
137 /* Find out whether P2A works or whether to use device-tree */
138 ast_detect_config_mode(dev, &scu_rev);
139
140 /* Identify chipset */
141 if (dev->pdev->device == PCI_CHIP_AST1180) {
142 ast->chip = AST1100;
143 DRM_INFO("AST 1180 detected\n");
144 } else {
145 if (dev->pdev->revision >= 0x40) {
146 ast->chip = AST2500;
147 DRM_INFO("AST 2500 detected\n");
148 } else if (dev->pdev->revision >= 0x30) {
149 ast->chip = AST2400;
150 DRM_INFO("AST 2400 detected\n");
151 } else if (dev->pdev->revision >= 0x20) {
152 ast->chip = AST2300;
153 DRM_INFO("AST 2300 detected\n");
154 } else if (dev->pdev->revision >= 0x10) {
155 switch (scu_rev & 0x0300) {
156 case 0x0200:
157 ast->chip = AST1100;
158 DRM_INFO("AST 1100 detected\n");
159 break;
160 case 0x0100:
161 ast->chip = AST2200;
162 DRM_INFO("AST 2200 detected\n");
163 break;
164 case 0x0000:
165 ast->chip = AST2150;
166 DRM_INFO("AST 2150 detected\n");
167 break;
168 default:
169 ast->chip = AST2100;
170 DRM_INFO("AST 2100 detected\n");
171 break;
172 }
173 ast->vga2_clone = false;
174 } else {
175 ast->chip = AST2000;
176 DRM_INFO("AST 2000 detected\n");
177 }
178 }
179
180 /* Check if we support wide screen */
181 switch (ast->chip) {
182 case AST1180:
183 ast->support_wide_screen = true;
184 break;
185 case AST2000:
186 ast->support_wide_screen = false;
187 break;
188 default:
189 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
190 if (!(jreg & 0x80))
191 ast->support_wide_screen = true;
192 else if (jreg & 0x01)
193 ast->support_wide_screen = true;
194 else {
195 ast->support_wide_screen = false;
196 if (ast->chip == AST2300 &&
197 (scu_rev & 0x300) == 0x0) /* ast1300 */
198 ast->support_wide_screen = true;
199 if (ast->chip == AST2400 &&
200 (scu_rev & 0x300) == 0x100) /* ast1400 */
201 ast->support_wide_screen = true;
202 if (ast->chip == AST2500 &&
203 scu_rev == 0x100) /* ast2510 */
204 ast->support_wide_screen = true;
205 }
206 break;
207 }
208
209 /* Check 3rd Tx option (digital output afaik) */
210 ast->tx_chip_type = AST_TX_NONE;
211
212 /*
213 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
214 * enabled, in that case, assume we have a SIL164 TMDS transmitter
215 *
216 * Don't make that assumption if we the chip wasn't enabled and
217 * is at power-on reset, otherwise we'll incorrectly "detect" a
218 * SIL164 when there is none.
219 */
220 if (!*need_post) {
221 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
222 if (jreg & 0x80)
223 ast->tx_chip_type = AST_TX_SIL164;
224 }
225
226 if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
227 /*
228 * On AST2300 and 2400, look the configuration set by the SoC in
229 * the SOC scratch register #1 bits 11:8 (interestingly marked
230 * as "reserved" in the spec)
231 */
232 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
233 switch (jreg) {
234 case 0x04:
235 ast->tx_chip_type = AST_TX_SIL164;
236 break;
237 case 0x08:
238 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
239 if (ast->dp501_fw_addr) {
240 /* backup firmware */
241 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
242 kfree(ast->dp501_fw_addr);
243 ast->dp501_fw_addr = NULL;
244 }
245 }
246 /* fallthrough */
247 case 0x0c:
248 ast->tx_chip_type = AST_TX_DP501;
249 }
250 }
251
252 /* Print stuff for diagnostic purposes */
253 switch(ast->tx_chip_type) {
254 case AST_TX_SIL164:
255 DRM_INFO("Using Sil164 TMDS transmitter\n");
256 break;
257 case AST_TX_DP501:
258 DRM_INFO("Using DP501 DisplayPort transmitter\n");
259 break;
260 default:
261 DRM_INFO("Analog VGA only\n");
262 }
263 return 0;
264}
265
266static int ast_get_dram_info(struct drm_device *dev)
267{
268 struct device_node *np = dev->pdev->dev.of_node;
269 struct ast_private *ast = dev->dev_private;
270 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
271 uint32_t denum, num, div, ref_pll, dsel;
272
273 switch (ast->config_mode) {
274 case ast_use_dt:
275 /*
276 * If some properties are missing, use reasonable
277 * defaults for AST2400
278 */
279 if (of_property_read_u32(np, "aspeed,mcr-configuration",
280 &mcr_cfg))
281 mcr_cfg = 0x00000577;
282 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll",
283 &mcr_scu_mpll))
284 mcr_scu_mpll = 0x000050C0;
285 if (of_property_read_u32(np, "aspeed,mcr-scu-strap",
286 &mcr_scu_strap))
287 mcr_scu_strap = 0;
288 break;
289 case ast_use_p2a:
290 ast_write32(ast, 0xf004, 0x1e6e0000);
291 ast_write32(ast, 0xf000, 0x1);
292 mcr_cfg = ast_read32(ast, 0x10004);
293 mcr_scu_mpll = ast_read32(ast, 0x10120);
294 mcr_scu_strap = ast_read32(ast, 0x10170);
295 break;
296 case ast_use_defaults:
297 default:
298 ast->dram_bus_width = 16;
299 ast->dram_type = AST_DRAM_1Gx16;
300 if (ast->chip == AST2500)
301 ast->mclk = 800;
302 else
303 ast->mclk = 396;
304 return 0;
305 }
306
307 if (mcr_cfg & 0x40)
308 ast->dram_bus_width = 16;
309 else
310 ast->dram_bus_width = 32;
311
312 if (ast->chip == AST2500) {
313 switch (mcr_cfg & 0x03) {
314 case 0:
315 ast->dram_type = AST_DRAM_1Gx16;
316 break;
317 default:
318 case 1:
319 ast->dram_type = AST_DRAM_2Gx16;
320 break;
321 case 2:
322 ast->dram_type = AST_DRAM_4Gx16;
323 break;
324 case 3:
325 ast->dram_type = AST_DRAM_8Gx16;
326 break;
327 }
328 } else if (ast->chip == AST2300 || ast->chip == AST2400) {
329 switch (mcr_cfg & 0x03) {
330 case 0:
331 ast->dram_type = AST_DRAM_512Mx16;
332 break;
333 default:
334 case 1:
335 ast->dram_type = AST_DRAM_1Gx16;
336 break;
337 case 2:
338 ast->dram_type = AST_DRAM_2Gx16;
339 break;
340 case 3:
341 ast->dram_type = AST_DRAM_4Gx16;
342 break;
343 }
344 } else {
345 switch (mcr_cfg & 0x0c) {
346 case 0:
347 case 4:
348 ast->dram_type = AST_DRAM_512Mx16;
349 break;
350 case 8:
351 if (mcr_cfg & 0x40)
352 ast->dram_type = AST_DRAM_1Gx16;
353 else
354 ast->dram_type = AST_DRAM_512Mx32;
355 break;
356 case 0xc:
357 ast->dram_type = AST_DRAM_1Gx32;
358 break;
359 }
360 }
361
362 if (mcr_scu_strap & 0x2000)
363 ref_pll = 14318;
364 else
365 ref_pll = 12000;
366
367 denum = mcr_scu_mpll & 0x1f;
368 num = (mcr_scu_mpll & 0x3fe0) >> 5;
369 dsel = (mcr_scu_mpll & 0xc000) >> 14;
370 switch (dsel) {
371 case 3:
372 div = 0x4;
373 break;
374 case 2:
375 case 1:
376 div = 0x2;
377 break;
378 default:
379 div = 0x1;
380 break;
381 }
382 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000));
383 return 0;
384}
385
386static void ast_user_framebuffer_destroy(struct drm_framebuffer *fb)
387{
388 struct ast_framebuffer *ast_fb = to_ast_framebuffer(fb);
389
390 drm_gem_object_put_unlocked(ast_fb->obj);
391 drm_framebuffer_cleanup(fb);
392 kfree(ast_fb);
393}
394
395static const struct drm_framebuffer_funcs ast_fb_funcs = {
396 .destroy = ast_user_framebuffer_destroy,
397};
398
399
400int ast_framebuffer_init(struct drm_device *dev,
401 struct ast_framebuffer *ast_fb,
402 const struct drm_mode_fb_cmd2 *mode_cmd,
403 struct drm_gem_object *obj)
404{
405 int ret;
406
407 drm_helper_mode_fill_fb_struct(dev, &ast_fb->base, mode_cmd);
408 ast_fb->obj = obj;
409 ret = drm_framebuffer_init(dev, &ast_fb->base, &ast_fb_funcs);
410 if (ret) {
411 DRM_ERROR("framebuffer init failed %d\n", ret);
412 return ret;
413 }
414 return 0;
415}
416
417static struct drm_framebuffer *
418ast_user_framebuffer_create(struct drm_device *dev,
419 struct drm_file *filp,
420 const struct drm_mode_fb_cmd2 *mode_cmd)
421{
422 struct drm_gem_object *obj;
423 struct ast_framebuffer *ast_fb;
424 int ret;
425
426 obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]);
427 if (obj == NULL)
428 return ERR_PTR(-ENOENT);
429
430 ast_fb = kzalloc(sizeof(*ast_fb), GFP_KERNEL);
431 if (!ast_fb) {
432 drm_gem_object_put_unlocked(obj);
433 return ERR_PTR(-ENOMEM);
434 }
435
436 ret = ast_framebuffer_init(dev, ast_fb, mode_cmd, obj);
437 if (ret) {
438 drm_gem_object_put_unlocked(obj);
439 kfree(ast_fb);
440 return ERR_PTR(ret);
441 }
442 return &ast_fb->base;
443}
444
445static const struct drm_mode_config_funcs ast_mode_funcs = {
446 .fb_create = ast_user_framebuffer_create,
447};
448
449static u32 ast_get_vram_info(struct drm_device *dev)
450{
451 struct ast_private *ast = dev->dev_private;
452 u8 jreg;
453 u32 vram_size;
454 ast_open_key(ast);
455
456 vram_size = AST_VIDMEM_DEFAULT_SIZE;
457 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
458 switch (jreg & 3) {
459 case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
460 case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
461 case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
462 case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
463 }
464
465 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
466 switch (jreg & 0x03) {
467 case 1:
468 vram_size -= 0x100000;
469 break;
470 case 2:
471 vram_size -= 0x200000;
472 break;
473 case 3:
474 vram_size -= 0x400000;
475 break;
476 }
477
478 return vram_size;
479}
480
481int ast_driver_load(struct drm_device *dev, unsigned long flags)
482{
483 struct ast_private *ast;
484 bool need_post;
485 int ret = 0;
486
487 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL);
488 if (!ast)
489 return -ENOMEM;
490
491 dev->dev_private = ast;
492 ast->dev = dev;
493
494 ast->regs = pci_iomap(dev->pdev, 1, 0);
495 if (!ast->regs) {
496 ret = -EIO;
497 goto out_free;
498 }
499
500 /*
501 * If we don't have IO space at all, use MMIO now and
502 * assume the chip has MMIO enabled by default (rev 0x20
503 * and higher).
504 */
505 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
506 DRM_INFO("platform has no IO space, trying MMIO\n");
507 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
508 }
509
510 /* "map" IO regs if the above hasn't done so already */
511 if (!ast->ioregs) {
512 ast->ioregs = pci_iomap(dev->pdev, 2, 0);
513 if (!ast->ioregs) {
514 ret = -EIO;
515 goto out_free;
516 }
517 }
518
519 ast_detect_chip(dev, &need_post);
520
521 if (need_post)
522 ast_post_gpu(dev);
523
524 if (ast->chip != AST1180) {
525 ret = ast_get_dram_info(dev);
526 if (ret)
527 goto out_free;
528 ast->vram_size = ast_get_vram_info(dev);
529 DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
530 ast->mclk, ast->dram_type,
531 ast->dram_bus_width, ast->vram_size);
532 }
533
534 ret = ast_mm_init(ast);
535 if (ret)
536 goto out_free;
537
538 drm_mode_config_init(dev);
539
540 dev->mode_config.funcs = (void *)&ast_mode_funcs;
541 dev->mode_config.min_width = 0;
542 dev->mode_config.min_height = 0;
543 dev->mode_config.preferred_depth = 24;
544 dev->mode_config.prefer_shadow = 1;
545 dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0);
546
547 if (ast->chip == AST2100 ||
548 ast->chip == AST2200 ||
549 ast->chip == AST2300 ||
550 ast->chip == AST2400 ||
551 ast->chip == AST2500 ||
552 ast->chip == AST1180) {
553 dev->mode_config.max_width = 1920;
554 dev->mode_config.max_height = 2048;
555 } else {
556 dev->mode_config.max_width = 1600;
557 dev->mode_config.max_height = 1200;
558 }
559
560 ret = ast_mode_init(dev);
561 if (ret)
562 goto out_free;
563
564 ret = ast_fbdev_init(dev);
565 if (ret)
566 goto out_free;
567
568 return 0;
569out_free:
570 kfree(ast);
571 dev->dev_private = NULL;
572 return ret;
573}
574
575void ast_driver_unload(struct drm_device *dev)
576{
577 struct ast_private *ast = dev->dev_private;
578
579 ast_release_firmware(dev);
580 kfree(ast->dp501_fw_addr);
581 ast_mode_fini(dev);
582 ast_fbdev_fini(dev);
583 drm_mode_config_cleanup(dev);
584
585 ast_mm_fini(ast);
586 pci_iounmap(dev->pdev, ast->ioregs);
587 pci_iounmap(dev->pdev, ast->regs);
588 kfree(ast);
589}
590
591int ast_gem_create(struct drm_device *dev,
592 u32 size, bool iskernel,
593 struct drm_gem_object **obj)
594{
595 struct ast_bo *astbo;
596 int ret;
597
598 *obj = NULL;
599
600 size = roundup(size, PAGE_SIZE);
601 if (size == 0)
602 return -EINVAL;
603
604 ret = ast_bo_create(dev, size, 0, 0, &astbo);
605 if (ret) {
606 if (ret != -ERESTARTSYS)
607 DRM_ERROR("failed to allocate GEM object\n");
608 return ret;
609 }
610 *obj = &astbo->gem;
611 return 0;
612}
613
614int ast_dumb_create(struct drm_file *file,
615 struct drm_device *dev,
616 struct drm_mode_create_dumb *args)
617{
618 int ret;
619 struct drm_gem_object *gobj;
620 u32 handle;
621
622 args->pitch = args->width * ((args->bpp + 7) / 8);
623 args->size = args->pitch * args->height;
624
625 ret = ast_gem_create(dev, args->size, false,
626 &gobj);
627 if (ret)
628 return ret;
629
630 ret = drm_gem_handle_create(file, gobj, &handle);
631 drm_gem_object_put_unlocked(gobj);
632 if (ret)
633 return ret;
634
635 args->handle = handle;
636 return 0;
637}
638
639static void ast_bo_unref(struct ast_bo **bo)
640{
641 struct ttm_buffer_object *tbo;
642
643 if ((*bo) == NULL)
644 return;
645
646 tbo = &((*bo)->bo);
647 ttm_bo_unref(&tbo);
648 *bo = NULL;
649}
650
651void ast_gem_free_object(struct drm_gem_object *obj)
652{
653 struct ast_bo *ast_bo = gem_to_ast_bo(obj);
654
655 ast_bo_unref(&ast_bo);
656}
657
658
659static inline u64 ast_bo_mmap_offset(struct ast_bo *bo)
660{
661 return drm_vma_node_offset_addr(&bo->bo.vma_node);
662}
663int
664ast_dumb_mmap_offset(struct drm_file *file,
665 struct drm_device *dev,
666 uint32_t handle,
667 uint64_t *offset)
668{
669 struct drm_gem_object *obj;
670 struct ast_bo *bo;
671
672 obj = drm_gem_object_lookup(file, handle);
673 if (obj == NULL)
674 return -ENOENT;
675
676 bo = gem_to_ast_bo(obj);
677 *offset = ast_bo_mmap_offset(bo);
678
679 drm_gem_object_put_unlocked(obj);
680
681 return 0;
682
683}
684