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1/*
2 * Copyright 2015-2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/pci.h>
24#include <linux/acpi.h>
25#include "kfd_crat.h"
26#include "kfd_priv.h"
27#include "kfd_topology.h"
28#include "kfd_iommu.h"
29#include "amdgpu_amdkfd.h"
30
31/* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
32 * GPU processor ID are expressed with Bit[31]=1.
33 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
34 * used in the CRAT.
35 */
36static uint32_t gpu_processor_id_low = 0x80001000;
37
38/* Return the next available gpu_processor_id and increment it for next GPU
39 * @total_cu_count - Total CUs present in the GPU including ones
40 * masked off
41 */
42static inline unsigned int get_and_inc_gpu_processor_id(
43 unsigned int total_cu_count)
44{
45 int current_id = gpu_processor_id_low;
46
47 gpu_processor_id_low += total_cu_count;
48 return current_id;
49}
50
51/* Static table to describe GPU Cache information */
52struct kfd_gpu_cache_info {
53 uint32_t cache_size;
54 uint32_t cache_level;
55 uint32_t flags;
56 /* Indicates how many Compute Units share this cache
57 * Value = 1 indicates the cache is not shared
58 */
59 uint32_t num_cu_shared;
60};
61
62static struct kfd_gpu_cache_info kaveri_cache_info[] = {
63 {
64 /* TCP L1 Cache per CU */
65 .cache_size = 16,
66 .cache_level = 1,
67 .flags = (CRAT_CACHE_FLAGS_ENABLED |
68 CRAT_CACHE_FLAGS_DATA_CACHE |
69 CRAT_CACHE_FLAGS_SIMD_CACHE),
70 .num_cu_shared = 1,
71
72 },
73 {
74 /* Scalar L1 Instruction Cache (in SQC module) per bank */
75 .cache_size = 16,
76 .cache_level = 1,
77 .flags = (CRAT_CACHE_FLAGS_ENABLED |
78 CRAT_CACHE_FLAGS_INST_CACHE |
79 CRAT_CACHE_FLAGS_SIMD_CACHE),
80 .num_cu_shared = 2,
81 },
82 {
83 /* Scalar L1 Data Cache (in SQC module) per bank */
84 .cache_size = 8,
85 .cache_level = 1,
86 .flags = (CRAT_CACHE_FLAGS_ENABLED |
87 CRAT_CACHE_FLAGS_DATA_CACHE |
88 CRAT_CACHE_FLAGS_SIMD_CACHE),
89 .num_cu_shared = 2,
90 },
91
92 /* TODO: Add L2 Cache information */
93};
94
95
96static struct kfd_gpu_cache_info carrizo_cache_info[] = {
97 {
98 /* TCP L1 Cache per CU */
99 .cache_size = 16,
100 .cache_level = 1,
101 .flags = (CRAT_CACHE_FLAGS_ENABLED |
102 CRAT_CACHE_FLAGS_DATA_CACHE |
103 CRAT_CACHE_FLAGS_SIMD_CACHE),
104 .num_cu_shared = 1,
105 },
106 {
107 /* Scalar L1 Instruction Cache (in SQC module) per bank */
108 .cache_size = 8,
109 .cache_level = 1,
110 .flags = (CRAT_CACHE_FLAGS_ENABLED |
111 CRAT_CACHE_FLAGS_INST_CACHE |
112 CRAT_CACHE_FLAGS_SIMD_CACHE),
113 .num_cu_shared = 4,
114 },
115 {
116 /* Scalar L1 Data Cache (in SQC module) per bank. */
117 .cache_size = 4,
118 .cache_level = 1,
119 .flags = (CRAT_CACHE_FLAGS_ENABLED |
120 CRAT_CACHE_FLAGS_DATA_CACHE |
121 CRAT_CACHE_FLAGS_SIMD_CACHE),
122 .num_cu_shared = 4,
123 },
124
125 /* TODO: Add L2 Cache information */
126};
127
128/* NOTE: In future if more information is added to struct kfd_gpu_cache_info
129 * the following ASICs may need a separate table.
130 */
131#define hawaii_cache_info kaveri_cache_info
132#define tonga_cache_info carrizo_cache_info
133#define fiji_cache_info carrizo_cache_info
134#define polaris10_cache_info carrizo_cache_info
135#define polaris11_cache_info carrizo_cache_info
136#define polaris12_cache_info carrizo_cache_info
137#define vegam_cache_info carrizo_cache_info
138/* TODO - check & update Vega10 cache details */
139#define vega10_cache_info carrizo_cache_info
140#define raven_cache_info carrizo_cache_info
141#define renoir_cache_info carrizo_cache_info
142/* TODO - check & update Navi10 cache details */
143#define navi10_cache_info carrizo_cache_info
144
145static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
146 struct crat_subtype_computeunit *cu)
147{
148 dev->node_props.cpu_cores_count = cu->num_cpu_cores;
149 dev->node_props.cpu_core_id_base = cu->processor_id_low;
150 if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
151 dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
152
153 pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
154 cu->processor_id_low);
155}
156
157static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
158 struct crat_subtype_computeunit *cu)
159{
160 dev->node_props.simd_id_base = cu->processor_id_low;
161 dev->node_props.simd_count = cu->num_simd_cores;
162 dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
163 dev->node_props.max_waves_per_simd = cu->max_waves_simd;
164 dev->node_props.wave_front_size = cu->wave_front_size;
165 dev->node_props.array_count = cu->array_count;
166 dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
167 dev->node_props.simd_per_cu = cu->num_simd_per_cu;
168 dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
169 if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
170 dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
171 pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low);
172}
173
174/* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct
175 * topology device present in the device_list
176 */
177static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu,
178 struct list_head *device_list)
179{
180 struct kfd_topology_device *dev;
181
182 pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
183 cu->proximity_domain, cu->hsa_capability);
184 list_for_each_entry(dev, device_list, list) {
185 if (cu->proximity_domain == dev->proximity_domain) {
186 if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
187 kfd_populated_cu_info_cpu(dev, cu);
188
189 if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
190 kfd_populated_cu_info_gpu(dev, cu);
191 break;
192 }
193 }
194
195 return 0;
196}
197
198static struct kfd_mem_properties *
199find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width,
200 struct kfd_topology_device *dev)
201{
202 struct kfd_mem_properties *props;
203
204 list_for_each_entry(props, &dev->mem_props, list) {
205 if (props->heap_type == heap_type
206 && props->flags == flags
207 && props->width == width)
208 return props;
209 }
210
211 return NULL;
212}
213/* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
214 * topology device present in the device_list
215 */
216static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem,
217 struct list_head *device_list)
218{
219 struct kfd_mem_properties *props;
220 struct kfd_topology_device *dev;
221 uint32_t heap_type;
222 uint64_t size_in_bytes;
223 uint32_t flags = 0;
224 uint32_t width;
225
226 pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
227 mem->proximity_domain);
228 list_for_each_entry(dev, device_list, list) {
229 if (mem->proximity_domain == dev->proximity_domain) {
230 /* We're on GPU node */
231 if (dev->node_props.cpu_cores_count == 0) {
232 /* APU */
233 if (mem->visibility_type == 0)
234 heap_type =
235 HSA_MEM_HEAP_TYPE_FB_PRIVATE;
236 /* dGPU */
237 else
238 heap_type = mem->visibility_type;
239 } else
240 heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
241
242 if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
243 flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
244 if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
245 flags |= HSA_MEM_FLAGS_NON_VOLATILE;
246
247 size_in_bytes =
248 ((uint64_t)mem->length_high << 32) +
249 mem->length_low;
250 width = mem->width;
251
252 /* Multiple banks of the same type are aggregated into
253 * one. User mode doesn't care about multiple physical
254 * memory segments. It's managed as a single virtual
255 * heap for user mode.
256 */
257 props = find_subtype_mem(heap_type, flags, width, dev);
258 if (props) {
259 props->size_in_bytes += size_in_bytes;
260 break;
261 }
262
263 props = kfd_alloc_struct(props);
264 if (!props)
265 return -ENOMEM;
266
267 props->heap_type = heap_type;
268 props->flags = flags;
269 props->size_in_bytes = size_in_bytes;
270 props->width = width;
271
272 dev->node_props.mem_banks_count++;
273 list_add_tail(&props->list, &dev->mem_props);
274
275 break;
276 }
277 }
278
279 return 0;
280}
281
282/* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct
283 * topology device present in the device_list
284 */
285static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache,
286 struct list_head *device_list)
287{
288 struct kfd_cache_properties *props;
289 struct kfd_topology_device *dev;
290 uint32_t id;
291 uint32_t total_num_of_cu;
292
293 id = cache->processor_id_low;
294
295 pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
296 list_for_each_entry(dev, device_list, list) {
297 total_num_of_cu = (dev->node_props.array_count *
298 dev->node_props.cu_per_simd_array);
299
300 /* Cache infomration in CRAT doesn't have proximity_domain
301 * information as it is associated with a CPU core or GPU
302 * Compute Unit. So map the cache using CPU core Id or SIMD
303 * (GPU) ID.
304 * TODO: This works because currently we can safely assume that
305 * Compute Units are parsed before caches are parsed. In
306 * future, remove this dependency
307 */
308 if ((id >= dev->node_props.cpu_core_id_base &&
309 id <= dev->node_props.cpu_core_id_base +
310 dev->node_props.cpu_cores_count) ||
311 (id >= dev->node_props.simd_id_base &&
312 id < dev->node_props.simd_id_base +
313 total_num_of_cu)) {
314 props = kfd_alloc_struct(props);
315 if (!props)
316 return -ENOMEM;
317
318 props->processor_id_low = id;
319 props->cache_level = cache->cache_level;
320 props->cache_size = cache->cache_size;
321 props->cacheline_size = cache->cache_line_size;
322 props->cachelines_per_tag = cache->lines_per_tag;
323 props->cache_assoc = cache->associativity;
324 props->cache_latency = cache->cache_latency;
325 memcpy(props->sibling_map, cache->sibling_map,
326 sizeof(props->sibling_map));
327
328 if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
329 props->cache_type |= HSA_CACHE_TYPE_DATA;
330 if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
331 props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
332 if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
333 props->cache_type |= HSA_CACHE_TYPE_CPU;
334 if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
335 props->cache_type |= HSA_CACHE_TYPE_HSACU;
336
337 dev->cache_count++;
338 dev->node_props.caches_count++;
339 list_add_tail(&props->list, &dev->cache_props);
340
341 break;
342 }
343 }
344
345 return 0;
346}
347
348/* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct
349 * topology device present in the device_list
350 */
351static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
352 struct list_head *device_list)
353{
354 struct kfd_iolink_properties *props = NULL, *props2;
355 struct kfd_topology_device *dev, *to_dev;
356 uint32_t id_from;
357 uint32_t id_to;
358
359 id_from = iolink->proximity_domain_from;
360 id_to = iolink->proximity_domain_to;
361
362 pr_debug("Found IO link entry in CRAT table with id_from=%d, id_to %d\n",
363 id_from, id_to);
364 list_for_each_entry(dev, device_list, list) {
365 if (id_from == dev->proximity_domain) {
366 props = kfd_alloc_struct(props);
367 if (!props)
368 return -ENOMEM;
369
370 props->node_from = id_from;
371 props->node_to = id_to;
372 props->ver_maj = iolink->version_major;
373 props->ver_min = iolink->version_minor;
374 props->iolink_type = iolink->io_interface_type;
375
376 if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
377 props->weight = 20;
378 else if (props->iolink_type == CRAT_IOLINK_TYPE_XGMI)
379 props->weight = 15 * iolink->num_hops_xgmi;
380 else
381 props->weight = node_distance(id_from, id_to);
382
383 props->min_latency = iolink->minimum_latency;
384 props->max_latency = iolink->maximum_latency;
385 props->min_bandwidth = iolink->minimum_bandwidth_mbs;
386 props->max_bandwidth = iolink->maximum_bandwidth_mbs;
387 props->rec_transfer_size =
388 iolink->recommended_transfer_size;
389
390 dev->io_link_count++;
391 dev->node_props.io_links_count++;
392 list_add_tail(&props->list, &dev->io_link_props);
393 break;
394 }
395 }
396
397 /* CPU topology is created before GPUs are detected, so CPU->GPU
398 * links are not built at that time. If a PCIe type is discovered, it
399 * means a GPU is detected and we are adding GPU->CPU to the topology.
400 * At this time, also add the corresponded CPU->GPU link if GPU
401 * is large bar.
402 * For xGMI, we only added the link with one direction in the crat
403 * table, add corresponded reversed direction link now.
404 */
405 if (props && (iolink->flags & CRAT_IOLINK_FLAGS_BI_DIRECTIONAL)) {
406 to_dev = kfd_topology_device_by_proximity_domain(id_to);
407 if (!to_dev)
408 return -ENODEV;
409 /* same everything but the other direction */
410 props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL);
411 props2->node_from = id_to;
412 props2->node_to = id_from;
413 props2->kobj = NULL;
414 to_dev->io_link_count++;
415 to_dev->node_props.io_links_count++;
416 list_add_tail(&props2->list, &to_dev->io_link_props);
417 }
418
419 return 0;
420}
421
422/* kfd_parse_subtype - parse subtypes and attach it to correct topology device
423 * present in the device_list
424 * @sub_type_hdr - subtype section of crat_image
425 * @device_list - list of topology devices present in this crat_image
426 */
427static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr,
428 struct list_head *device_list)
429{
430 struct crat_subtype_computeunit *cu;
431 struct crat_subtype_memory *mem;
432 struct crat_subtype_cache *cache;
433 struct crat_subtype_iolink *iolink;
434 int ret = 0;
435
436 switch (sub_type_hdr->type) {
437 case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
438 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
439 ret = kfd_parse_subtype_cu(cu, device_list);
440 break;
441 case CRAT_SUBTYPE_MEMORY_AFFINITY:
442 mem = (struct crat_subtype_memory *)sub_type_hdr;
443 ret = kfd_parse_subtype_mem(mem, device_list);
444 break;
445 case CRAT_SUBTYPE_CACHE_AFFINITY:
446 cache = (struct crat_subtype_cache *)sub_type_hdr;
447 ret = kfd_parse_subtype_cache(cache, device_list);
448 break;
449 case CRAT_SUBTYPE_TLB_AFFINITY:
450 /*
451 * For now, nothing to do here
452 */
453 pr_debug("Found TLB entry in CRAT table (not processing)\n");
454 break;
455 case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
456 /*
457 * For now, nothing to do here
458 */
459 pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n");
460 break;
461 case CRAT_SUBTYPE_IOLINK_AFFINITY:
462 iolink = (struct crat_subtype_iolink *)sub_type_hdr;
463 ret = kfd_parse_subtype_iolink(iolink, device_list);
464 break;
465 default:
466 pr_warn("Unknown subtype %d in CRAT\n",
467 sub_type_hdr->type);
468 }
469
470 return ret;
471}
472
473/* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT
474 * create a kfd_topology_device and add in to device_list. Also parse
475 * CRAT subtypes and attach it to appropriate kfd_topology_device
476 * @crat_image - input image containing CRAT
477 * @device_list - [OUT] list of kfd_topology_device generated after
478 * parsing crat_image
479 * @proximity_domain - Proximity domain of the first device in the table
480 *
481 * Return - 0 if successful else -ve value
482 */
483int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
484 uint32_t proximity_domain)
485{
486 struct kfd_topology_device *top_dev = NULL;
487 struct crat_subtype_generic *sub_type_hdr;
488 uint16_t node_id;
489 int ret = 0;
490 struct crat_header *crat_table = (struct crat_header *)crat_image;
491 uint16_t num_nodes;
492 uint32_t image_len;
493
494 if (!crat_image)
495 return -EINVAL;
496
497 if (!list_empty(device_list)) {
498 pr_warn("Error device list should be empty\n");
499 return -EINVAL;
500 }
501
502 num_nodes = crat_table->num_domains;
503 image_len = crat_table->length;
504
505 pr_debug("Parsing CRAT table with %d nodes\n", num_nodes);
506
507 for (node_id = 0; node_id < num_nodes; node_id++) {
508 top_dev = kfd_create_topology_device(device_list);
509 if (!top_dev)
510 break;
511 top_dev->proximity_domain = proximity_domain++;
512 }
513
514 if (!top_dev) {
515 ret = -ENOMEM;
516 goto err;
517 }
518
519 memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH);
520 memcpy(top_dev->oem_table_id, crat_table->oem_table_id,
521 CRAT_OEMTABLEID_LENGTH);
522 top_dev->oem_revision = crat_table->oem_revision;
523
524 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
525 while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
526 ((char *)crat_image) + image_len) {
527 if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
528 ret = kfd_parse_subtype(sub_type_hdr, device_list);
529 if (ret)
530 break;
531 }
532
533 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
534 sub_type_hdr->length);
535 }
536
537err:
538 if (ret)
539 kfd_release_topology_device_list(device_list);
540
541 return ret;
542}
543
544/* Helper function. See kfd_fill_gpu_cache_info for parameter description */
545static int fill_in_pcache(struct crat_subtype_cache *pcache,
546 struct kfd_gpu_cache_info *pcache_info,
547 struct kfd_cu_info *cu_info,
548 int mem_available,
549 int cu_bitmask,
550 int cache_type, unsigned int cu_processor_id,
551 int cu_block)
552{
553 unsigned int cu_sibling_map_mask;
554 int first_active_cu;
555
556 /* First check if enough memory is available */
557 if (sizeof(struct crat_subtype_cache) > mem_available)
558 return -ENOMEM;
559
560 cu_sibling_map_mask = cu_bitmask;
561 cu_sibling_map_mask >>= cu_block;
562 cu_sibling_map_mask &=
563 ((1 << pcache_info[cache_type].num_cu_shared) - 1);
564 first_active_cu = ffs(cu_sibling_map_mask);
565
566 /* CU could be inactive. In case of shared cache find the first active
567 * CU. and incase of non-shared cache check if the CU is inactive. If
568 * inactive active skip it
569 */
570 if (first_active_cu) {
571 memset(pcache, 0, sizeof(struct crat_subtype_cache));
572 pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY;
573 pcache->length = sizeof(struct crat_subtype_cache);
574 pcache->flags = pcache_info[cache_type].flags;
575 pcache->processor_id_low = cu_processor_id
576 + (first_active_cu - 1);
577 pcache->cache_level = pcache_info[cache_type].cache_level;
578 pcache->cache_size = pcache_info[cache_type].cache_size;
579
580 /* Sibling map is w.r.t processor_id_low, so shift out
581 * inactive CU
582 */
583 cu_sibling_map_mask =
584 cu_sibling_map_mask >> (first_active_cu - 1);
585
586 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
587 pcache->sibling_map[1] =
588 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
589 pcache->sibling_map[2] =
590 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
591 pcache->sibling_map[3] =
592 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
593 return 0;
594 }
595 return 1;
596}
597
598/* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info
599 * tables
600 *
601 * @kdev - [IN] GPU device
602 * @gpu_processor_id - [IN] GPU processor ID to which these caches
603 * associate
604 * @available_size - [IN] Amount of memory available in pcache
605 * @cu_info - [IN] Compute Unit info obtained from KGD
606 * @pcache - [OUT] memory into which cache data is to be filled in.
607 * @size_filled - [OUT] amount of data used up in pcache.
608 * @num_of_entries - [OUT] number of caches added
609 */
610static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
611 int gpu_processor_id,
612 int available_size,
613 struct kfd_cu_info *cu_info,
614 struct crat_subtype_cache *pcache,
615 int *size_filled,
616 int *num_of_entries)
617{
618 struct kfd_gpu_cache_info *pcache_info;
619 int num_of_cache_types = 0;
620 int i, j, k;
621 int ct = 0;
622 int mem_available = available_size;
623 unsigned int cu_processor_id;
624 int ret;
625
626 switch (kdev->device_info->asic_family) {
627 case CHIP_KAVERI:
628 pcache_info = kaveri_cache_info;
629 num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
630 break;
631 case CHIP_HAWAII:
632 pcache_info = hawaii_cache_info;
633 num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
634 break;
635 case CHIP_CARRIZO:
636 pcache_info = carrizo_cache_info;
637 num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);
638 break;
639 case CHIP_TONGA:
640 pcache_info = tonga_cache_info;
641 num_of_cache_types = ARRAY_SIZE(tonga_cache_info);
642 break;
643 case CHIP_FIJI:
644 pcache_info = fiji_cache_info;
645 num_of_cache_types = ARRAY_SIZE(fiji_cache_info);
646 break;
647 case CHIP_POLARIS10:
648 pcache_info = polaris10_cache_info;
649 num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);
650 break;
651 case CHIP_POLARIS11:
652 pcache_info = polaris11_cache_info;
653 num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
654 break;
655 case CHIP_POLARIS12:
656 pcache_info = polaris12_cache_info;
657 num_of_cache_types = ARRAY_SIZE(polaris12_cache_info);
658 break;
659 case CHIP_VEGAM:
660 pcache_info = vegam_cache_info;
661 num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
662 break;
663 case CHIP_VEGA10:
664 case CHIP_VEGA12:
665 case CHIP_VEGA20:
666 case CHIP_ARCTURUS:
667 pcache_info = vega10_cache_info;
668 num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
669 break;
670 case CHIP_RAVEN:
671 pcache_info = raven_cache_info;
672 num_of_cache_types = ARRAY_SIZE(raven_cache_info);
673 break;
674 case CHIP_RENOIR:
675 pcache_info = renoir_cache_info;
676 num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
677 break;
678 case CHIP_NAVI10:
679 case CHIP_NAVI12:
680 case CHIP_NAVI14:
681 case CHIP_SIENNA_CICHLID:
682 case CHIP_NAVY_FLOUNDER:
683 pcache_info = navi10_cache_info;
684 num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
685 break;
686 default:
687 return -EINVAL;
688 }
689
690 *size_filled = 0;
691 *num_of_entries = 0;
692
693 /* For each type of cache listed in the kfd_gpu_cache_info table,
694 * go through all available Compute Units.
695 * The [i,j,k] loop will
696 * if kfd_gpu_cache_info.num_cu_shared = 1
697 * will parse through all available CU
698 * If (kfd_gpu_cache_info.num_cu_shared != 1)
699 * then it will consider only one CU from
700 * the shared unit
701 */
702
703 for (ct = 0; ct < num_of_cache_types; ct++) {
704 cu_processor_id = gpu_processor_id;
705 for (i = 0; i < cu_info->num_shader_engines; i++) {
706 for (j = 0; j < cu_info->num_shader_arrays_per_engine;
707 j++) {
708 for (k = 0; k < cu_info->num_cu_per_sh;
709 k += pcache_info[ct].num_cu_shared) {
710
711 ret = fill_in_pcache(pcache,
712 pcache_info,
713 cu_info,
714 mem_available,
715 cu_info->cu_bitmap[i % 4][j + i / 4],
716 ct,
717 cu_processor_id,
718 k);
719
720 if (ret < 0)
721 break;
722
723 if (!ret) {
724 pcache++;
725 (*num_of_entries)++;
726 mem_available -=
727 sizeof(*pcache);
728 (*size_filled) +=
729 sizeof(*pcache);
730 }
731
732 /* Move to next CU block */
733 cu_processor_id +=
734 pcache_info[ct].num_cu_shared;
735 }
736 }
737 }
738 }
739
740 pr_debug("Added [%d] GPU cache entries\n", *num_of_entries);
741
742 return 0;
743}
744
745/*
746 * kfd_create_crat_image_acpi - Allocates memory for CRAT image and
747 * copies CRAT from ACPI (if available).
748 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
749 *
750 * @crat_image: CRAT read from ACPI. If no CRAT in ACPI then
751 * crat_image will be NULL
752 * @size: [OUT] size of crat_image
753 *
754 * Return 0 if successful else return error code
755 */
756int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
757{
758 struct acpi_table_header *crat_table;
759 acpi_status status;
760 void *pcrat_image;
761
762 if (!crat_image)
763 return -EINVAL;
764
765 *crat_image = NULL;
766
767 /* Fetch the CRAT table from ACPI */
768 status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
769 if (status == AE_NOT_FOUND) {
770 pr_warn("CRAT table not found\n");
771 return -ENODATA;
772 } else if (ACPI_FAILURE(status)) {
773 const char *err = acpi_format_exception(status);
774
775 pr_err("CRAT table error: %s\n", err);
776 return -EINVAL;
777 }
778
779 if (ignore_crat) {
780 pr_info("CRAT table disabled by module option\n");
781 return -ENODATA;
782 }
783
784 pcrat_image = kmemdup(crat_table, crat_table->length, GFP_KERNEL);
785 if (!pcrat_image)
786 return -ENOMEM;
787
788 *crat_image = pcrat_image;
789 *size = crat_table->length;
790
791 return 0;
792}
793
794/* Memory required to create Virtual CRAT.
795 * Since there is no easy way to predict the amount of memory required, the
796 * following amount are allocated for CPU and GPU Virtual CRAT. This is
797 * expected to cover all known conditions. But to be safe additional check
798 * is put in the code to ensure we don't overwrite.
799 */
800#define VCRAT_SIZE_FOR_CPU (2 * PAGE_SIZE)
801#define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE)
802
803/* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
804 *
805 * @numa_node_id: CPU NUMA node id
806 * @avail_size: Available size in the memory
807 * @sub_type_hdr: Memory into which compute info will be filled in
808 *
809 * Return 0 if successful else return -ve value
810 */
811static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size,
812 int proximity_domain,
813 struct crat_subtype_computeunit *sub_type_hdr)
814{
815 const struct cpumask *cpumask;
816
817 *avail_size -= sizeof(struct crat_subtype_computeunit);
818 if (*avail_size < 0)
819 return -ENOMEM;
820
821 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
822
823 /* Fill in subtype header data */
824 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
825 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
826 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
827
828 cpumask = cpumask_of_node(numa_node_id);
829
830 /* Fill in CU data */
831 sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
832 sub_type_hdr->proximity_domain = proximity_domain;
833 sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id);
834 if (sub_type_hdr->processor_id_low == -1)
835 return -EINVAL;
836
837 sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask);
838
839 return 0;
840}
841
842/* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node
843 *
844 * @numa_node_id: CPU NUMA node id
845 * @avail_size: Available size in the memory
846 * @sub_type_hdr: Memory into which compute info will be filled in
847 *
848 * Return 0 if successful else return -ve value
849 */
850static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
851 int proximity_domain,
852 struct crat_subtype_memory *sub_type_hdr)
853{
854 uint64_t mem_in_bytes = 0;
855 pg_data_t *pgdat;
856 int zone_type;
857
858 *avail_size -= sizeof(struct crat_subtype_memory);
859 if (*avail_size < 0)
860 return -ENOMEM;
861
862 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
863
864 /* Fill in subtype header data */
865 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
866 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
867 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
868
869 /* Fill in Memory Subunit data */
870
871 /* Unlike si_meminfo, si_meminfo_node is not exported. So
872 * the following lines are duplicated from si_meminfo_node
873 * function
874 */
875 pgdat = NODE_DATA(numa_node_id);
876 for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
877 mem_in_bytes += zone_managed_pages(&pgdat->node_zones[zone_type]);
878 mem_in_bytes <<= PAGE_SHIFT;
879
880 sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
881 sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
882 sub_type_hdr->proximity_domain = proximity_domain;
883
884 return 0;
885}
886
887#ifdef CONFIG_X86_64
888static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
889 uint32_t *num_entries,
890 struct crat_subtype_iolink *sub_type_hdr)
891{
892 int nid;
893 struct cpuinfo_x86 *c = &cpu_data(0);
894 uint8_t link_type;
895
896 if (c->x86_vendor == X86_VENDOR_AMD)
897 link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT;
898 else
899 link_type = CRAT_IOLINK_TYPE_QPI_1_1;
900
901 *num_entries = 0;
902
903 /* Create IO links from this node to other CPU nodes */
904 for_each_online_node(nid) {
905 if (nid == numa_node_id) /* node itself */
906 continue;
907
908 *avail_size -= sizeof(struct crat_subtype_iolink);
909 if (*avail_size < 0)
910 return -ENOMEM;
911
912 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
913
914 /* Fill in subtype header data */
915 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
916 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
917 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
918
919 /* Fill in IO link data */
920 sub_type_hdr->proximity_domain_from = numa_node_id;
921 sub_type_hdr->proximity_domain_to = nid;
922 sub_type_hdr->io_interface_type = link_type;
923
924 (*num_entries)++;
925 sub_type_hdr++;
926 }
927
928 return 0;
929}
930#endif
931
932/* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
933 *
934 * @pcrat_image: Fill in VCRAT for CPU
935 * @size: [IN] allocated size of crat_image.
936 * [OUT] actual size of data filled in crat_image
937 */
938static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
939{
940 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
941 struct acpi_table_header *acpi_table;
942 acpi_status status;
943 struct crat_subtype_generic *sub_type_hdr;
944 int avail_size = *size;
945 int numa_node_id;
946#ifdef CONFIG_X86_64
947 uint32_t entries = 0;
948#endif
949 int ret = 0;
950
951 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_CPU)
952 return -EINVAL;
953
954 /* Fill in CRAT Header.
955 * Modify length and total_entries as subunits are added.
956 */
957 avail_size -= sizeof(struct crat_header);
958 if (avail_size < 0)
959 return -ENOMEM;
960
961 memset(crat_table, 0, sizeof(struct crat_header));
962 memcpy(&crat_table->signature, CRAT_SIGNATURE,
963 sizeof(crat_table->signature));
964 crat_table->length = sizeof(struct crat_header);
965
966 status = acpi_get_table("DSDT", 0, &acpi_table);
967 if (status != AE_OK)
968 pr_warn("DSDT table not found for OEM information\n");
969 else {
970 crat_table->oem_revision = acpi_table->revision;
971 memcpy(crat_table->oem_id, acpi_table->oem_id,
972 CRAT_OEMID_LENGTH);
973 memcpy(crat_table->oem_table_id, acpi_table->oem_table_id,
974 CRAT_OEMTABLEID_LENGTH);
975 }
976 crat_table->total_entries = 0;
977 crat_table->num_domains = 0;
978
979 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
980
981 for_each_online_node(numa_node_id) {
982 if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
983 continue;
984
985 /* Fill in Subtype: Compute Unit */
986 ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
987 crat_table->num_domains,
988 (struct crat_subtype_computeunit *)sub_type_hdr);
989 if (ret < 0)
990 return ret;
991 crat_table->length += sub_type_hdr->length;
992 crat_table->total_entries++;
993
994 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
995 sub_type_hdr->length);
996
997 /* Fill in Subtype: Memory */
998 ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size,
999 crat_table->num_domains,
1000 (struct crat_subtype_memory *)sub_type_hdr);
1001 if (ret < 0)
1002 return ret;
1003 crat_table->length += sub_type_hdr->length;
1004 crat_table->total_entries++;
1005
1006 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1007 sub_type_hdr->length);
1008
1009 /* Fill in Subtype: IO Link */
1010#ifdef CONFIG_X86_64
1011 ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
1012 &entries,
1013 (struct crat_subtype_iolink *)sub_type_hdr);
1014 if (ret < 0)
1015 return ret;
1016 crat_table->length += (sub_type_hdr->length * entries);
1017 crat_table->total_entries += entries;
1018
1019 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1020 sub_type_hdr->length * entries);
1021#else
1022 pr_info("IO link not available for non x86 platforms\n");
1023#endif
1024
1025 crat_table->num_domains++;
1026 }
1027
1028 /* TODO: Add cache Subtype for CPU.
1029 * Currently, CPU cache information is available in function
1030 * detect_cache_attributes(cpu) defined in the file
1031 * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not
1032 * exported and to get the same information the code needs to be
1033 * duplicated.
1034 */
1035
1036 *size = crat_table->length;
1037 pr_info("Virtual CRAT table created for CPU\n");
1038
1039 return 0;
1040}
1041
1042static int kfd_fill_gpu_memory_affinity(int *avail_size,
1043 struct kfd_dev *kdev, uint8_t type, uint64_t size,
1044 struct crat_subtype_memory *sub_type_hdr,
1045 uint32_t proximity_domain,
1046 const struct kfd_local_mem_info *local_mem_info)
1047{
1048 *avail_size -= sizeof(struct crat_subtype_memory);
1049 if (*avail_size < 0)
1050 return -ENOMEM;
1051
1052 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
1053 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
1054 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
1055 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1056
1057 sub_type_hdr->proximity_domain = proximity_domain;
1058
1059 pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n",
1060 type, size);
1061
1062 sub_type_hdr->length_low = lower_32_bits(size);
1063 sub_type_hdr->length_high = upper_32_bits(size);
1064
1065 sub_type_hdr->width = local_mem_info->vram_width;
1066 sub_type_hdr->visibility_type = type;
1067
1068 return 0;
1069}
1070
1071/* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
1072 * to its NUMA node
1073 * @avail_size: Available size in the memory
1074 * @kdev - [IN] GPU device
1075 * @sub_type_hdr: Memory into which io link info will be filled in
1076 * @proximity_domain - proximity domain of the GPU node
1077 *
1078 * Return 0 if successful else return -ve value
1079 */
1080static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
1081 struct kfd_dev *kdev,
1082 struct crat_subtype_iolink *sub_type_hdr,
1083 uint32_t proximity_domain)
1084{
1085 *avail_size -= sizeof(struct crat_subtype_iolink);
1086 if (*avail_size < 0)
1087 return -ENOMEM;
1088
1089 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1090
1091 /* Fill in subtype header data */
1092 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1093 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1094 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1095 if (kfd_dev_is_large_bar(kdev))
1096 sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
1097
1098 /* Fill in IOLINK subtype.
1099 * TODO: Fill-in other fields of iolink subtype
1100 */
1101 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
1102 sub_type_hdr->proximity_domain_from = proximity_domain;
1103#ifdef CONFIG_NUMA
1104 if (kdev->pdev->dev.numa_node == NUMA_NO_NODE)
1105 sub_type_hdr->proximity_domain_to = 0;
1106 else
1107 sub_type_hdr->proximity_domain_to = kdev->pdev->dev.numa_node;
1108#else
1109 sub_type_hdr->proximity_domain_to = 0;
1110#endif
1111 return 0;
1112}
1113
1114static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size,
1115 struct kfd_dev *kdev,
1116 struct kfd_dev *peer_kdev,
1117 struct crat_subtype_iolink *sub_type_hdr,
1118 uint32_t proximity_domain_from,
1119 uint32_t proximity_domain_to)
1120{
1121 *avail_size -= sizeof(struct crat_subtype_iolink);
1122 if (*avail_size < 0)
1123 return -ENOMEM;
1124
1125 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1126
1127 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1128 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1129 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED |
1130 CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
1131
1132 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
1133 sub_type_hdr->proximity_domain_from = proximity_domain_from;
1134 sub_type_hdr->proximity_domain_to = proximity_domain_to;
1135 sub_type_hdr->num_hops_xgmi =
1136 amdgpu_amdkfd_get_xgmi_hops_count(kdev->kgd, peer_kdev->kgd);
1137 return 0;
1138}
1139
1140/* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU
1141 *
1142 * @pcrat_image: Fill in VCRAT for GPU
1143 * @size: [IN] allocated size of crat_image.
1144 * [OUT] actual size of data filled in crat_image
1145 */
1146static int kfd_create_vcrat_image_gpu(void *pcrat_image,
1147 size_t *size, struct kfd_dev *kdev,
1148 uint32_t proximity_domain)
1149{
1150 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
1151 struct crat_subtype_generic *sub_type_hdr;
1152 struct kfd_local_mem_info local_mem_info;
1153 struct kfd_topology_device *peer_dev;
1154 struct crat_subtype_computeunit *cu;
1155 struct kfd_cu_info cu_info;
1156 int avail_size = *size;
1157 uint32_t total_num_of_cu;
1158 int num_of_cache_entries = 0;
1159 int cache_mem_filled = 0;
1160 uint32_t nid = 0;
1161 int ret = 0;
1162
1163 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
1164 return -EINVAL;
1165
1166 /* Fill the CRAT Header.
1167 * Modify length and total_entries as subunits are added.
1168 */
1169 avail_size -= sizeof(struct crat_header);
1170 if (avail_size < 0)
1171 return -ENOMEM;
1172
1173 memset(crat_table, 0, sizeof(struct crat_header));
1174
1175 memcpy(&crat_table->signature, CRAT_SIGNATURE,
1176 sizeof(crat_table->signature));
1177 /* Change length as we add more subtypes*/
1178 crat_table->length = sizeof(struct crat_header);
1179 crat_table->num_domains = 1;
1180 crat_table->total_entries = 0;
1181
1182 /* Fill in Subtype: Compute Unit
1183 * First fill in the sub type header and then sub type data
1184 */
1185 avail_size -= sizeof(struct crat_subtype_computeunit);
1186 if (avail_size < 0)
1187 return -ENOMEM;
1188
1189 sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
1190 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
1191
1192 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
1193 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
1194 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1195
1196 /* Fill CU subtype data */
1197 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
1198 cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
1199 cu->proximity_domain = proximity_domain;
1200
1201 amdgpu_amdkfd_get_cu_info(kdev->kgd, &cu_info);
1202 cu->num_simd_per_cu = cu_info.simd_per_cu;
1203 cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number;
1204 cu->max_waves_simd = cu_info.max_waves_per_simd;
1205
1206 cu->wave_front_size = cu_info.wave_front_size;
1207 cu->array_count = cu_info.num_shader_arrays_per_engine *
1208 cu_info.num_shader_engines;
1209 total_num_of_cu = (cu->array_count * cu_info.num_cu_per_sh);
1210 cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu);
1211 cu->num_cu_per_array = cu_info.num_cu_per_sh;
1212 cu->max_slots_scatch_cu = cu_info.max_scratch_slots_per_cu;
1213 cu->num_banks = cu_info.num_shader_engines;
1214 cu->lds_size_in_kb = cu_info.lds_size;
1215
1216 cu->hsa_capability = 0;
1217
1218 /* Check if this node supports IOMMU. During parsing this flag will
1219 * translate to HSA_CAP_ATS_PRESENT
1220 */
1221 if (!kfd_iommu_check_device(kdev))
1222 cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT;
1223
1224 crat_table->length += sub_type_hdr->length;
1225 crat_table->total_entries++;
1226
1227 /* Fill in Subtype: Memory. Only on systems with large BAR (no
1228 * private FB), report memory as public. On other systems
1229 * report the total FB size (public+private) as a single
1230 * private heap.
1231 */
1232 amdgpu_amdkfd_get_local_mem_info(kdev->kgd, &local_mem_info);
1233 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1234 sub_type_hdr->length);
1235
1236 if (debug_largebar)
1237 local_mem_info.local_mem_size_private = 0;
1238
1239 if (local_mem_info.local_mem_size_private == 0)
1240 ret = kfd_fill_gpu_memory_affinity(&avail_size,
1241 kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
1242 local_mem_info.local_mem_size_public,
1243 (struct crat_subtype_memory *)sub_type_hdr,
1244 proximity_domain,
1245 &local_mem_info);
1246 else
1247 ret = kfd_fill_gpu_memory_affinity(&avail_size,
1248 kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE,
1249 local_mem_info.local_mem_size_public +
1250 local_mem_info.local_mem_size_private,
1251 (struct crat_subtype_memory *)sub_type_hdr,
1252 proximity_domain,
1253 &local_mem_info);
1254 if (ret < 0)
1255 return ret;
1256
1257 crat_table->length += sizeof(struct crat_subtype_memory);
1258 crat_table->total_entries++;
1259
1260 /* TODO: Fill in cache information. This information is NOT readily
1261 * available in KGD
1262 */
1263 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1264 sub_type_hdr->length);
1265 ret = kfd_fill_gpu_cache_info(kdev, cu->processor_id_low,
1266 avail_size,
1267 &cu_info,
1268 (struct crat_subtype_cache *)sub_type_hdr,
1269 &cache_mem_filled,
1270 &num_of_cache_entries);
1271
1272 if (ret < 0)
1273 return ret;
1274
1275 crat_table->length += cache_mem_filled;
1276 crat_table->total_entries += num_of_cache_entries;
1277 avail_size -= cache_mem_filled;
1278
1279 /* Fill in Subtype: IO_LINKS
1280 * Only direct links are added here which is Link from GPU to
1281 * to its NUMA node. Indirect links are added by userspace.
1282 */
1283 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1284 cache_mem_filled);
1285 ret = kfd_fill_gpu_direct_io_link_to_cpu(&avail_size, kdev,
1286 (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain);
1287
1288 if (ret < 0)
1289 return ret;
1290
1291 crat_table->length += sub_type_hdr->length;
1292 crat_table->total_entries++;
1293
1294
1295 /* Fill in Subtype: IO_LINKS
1296 * Direct links from GPU to other GPUs through xGMI.
1297 * We will loop GPUs that already be processed (with lower value
1298 * of proximity_domain), add the link for the GPUs with same
1299 * hive id (from this GPU to other GPU) . The reversed iolink
1300 * (from other GPU to this GPU) will be added
1301 * in kfd_parse_subtype_iolink.
1302 */
1303 if (kdev->hive_id) {
1304 for (nid = 0; nid < proximity_domain; ++nid) {
1305 peer_dev = kfd_topology_device_by_proximity_domain(nid);
1306 if (!peer_dev->gpu)
1307 continue;
1308 if (peer_dev->gpu->hive_id != kdev->hive_id)
1309 continue;
1310 sub_type_hdr = (typeof(sub_type_hdr))(
1311 (char *)sub_type_hdr +
1312 sizeof(struct crat_subtype_iolink));
1313 ret = kfd_fill_gpu_xgmi_link_to_gpu(
1314 &avail_size, kdev, peer_dev->gpu,
1315 (struct crat_subtype_iolink *)sub_type_hdr,
1316 proximity_domain, nid);
1317 if (ret < 0)
1318 return ret;
1319 crat_table->length += sub_type_hdr->length;
1320 crat_table->total_entries++;
1321 }
1322 }
1323 *size = crat_table->length;
1324 pr_info("Virtual CRAT table created for GPU\n");
1325
1326 return ret;
1327}
1328
1329/* kfd_create_crat_image_virtual - Allocates memory for CRAT image and
1330 * creates a Virtual CRAT (VCRAT) image
1331 *
1332 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
1333 *
1334 * @crat_image: VCRAT image created because ACPI does not have a
1335 * CRAT for this device
1336 * @size: [OUT] size of virtual crat_image
1337 * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device
1338 * COMPUTE_UNIT_GPU - Create VCRAT for GPU
1339 * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU
1340 * -- this option is not currently implemented.
1341 * The assumption is that all AMD APUs will have CRAT
1342 * @kdev: Valid kfd_device required if flags contain COMPUTE_UNIT_GPU
1343 *
1344 * Return 0 if successful else return -ve value
1345 */
1346int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
1347 int flags, struct kfd_dev *kdev,
1348 uint32_t proximity_domain)
1349{
1350 void *pcrat_image = NULL;
1351 int ret = 0;
1352
1353 if (!crat_image)
1354 return -EINVAL;
1355
1356 *crat_image = NULL;
1357
1358 /* Allocate one VCRAT_SIZE_FOR_CPU for CPU virtual CRAT image and
1359 * VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image. This should cover
1360 * all the current conditions. A check is put not to overwrite beyond
1361 * allocated size
1362 */
1363 switch (flags) {
1364 case COMPUTE_UNIT_CPU:
1365 pcrat_image = kmalloc(VCRAT_SIZE_FOR_CPU, GFP_KERNEL);
1366 if (!pcrat_image)
1367 return -ENOMEM;
1368 *size = VCRAT_SIZE_FOR_CPU;
1369 ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
1370 break;
1371 case COMPUTE_UNIT_GPU:
1372 if (!kdev)
1373 return -EINVAL;
1374 pcrat_image = kmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL);
1375 if (!pcrat_image)
1376 return -ENOMEM;
1377 *size = VCRAT_SIZE_FOR_GPU;
1378 ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev,
1379 proximity_domain);
1380 break;
1381 case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU):
1382 /* TODO: */
1383 ret = -EINVAL;
1384 pr_err("VCRAT not implemented for APU\n");
1385 break;
1386 default:
1387 ret = -EINVAL;
1388 }
1389
1390 if (!ret)
1391 *crat_image = pcrat_image;
1392 else
1393 kfree(pcrat_image);
1394
1395 return ret;
1396}
1397
1398
1399/* kfd_destroy_crat_image
1400 *
1401 * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..)
1402 *
1403 */
1404void kfd_destroy_crat_image(void *crat_image)
1405{
1406 kfree(crat_image);
1407}
1/*
2 * Copyright 2015-2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/pci.h>
24#include <linux/acpi.h>
25#include "kfd_crat.h"
26#include "kfd_priv.h"
27#include "kfd_topology.h"
28#include "kfd_iommu.h"
29
30/* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
31 * GPU processor ID are expressed with Bit[31]=1.
32 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
33 * used in the CRAT.
34 */
35static uint32_t gpu_processor_id_low = 0x80001000;
36
37/* Return the next available gpu_processor_id and increment it for next GPU
38 * @total_cu_count - Total CUs present in the GPU including ones
39 * masked off
40 */
41static inline unsigned int get_and_inc_gpu_processor_id(
42 unsigned int total_cu_count)
43{
44 int current_id = gpu_processor_id_low;
45
46 gpu_processor_id_low += total_cu_count;
47 return current_id;
48}
49
50/* Static table to describe GPU Cache information */
51struct kfd_gpu_cache_info {
52 uint32_t cache_size;
53 uint32_t cache_level;
54 uint32_t flags;
55 /* Indicates how many Compute Units share this cache
56 * Value = 1 indicates the cache is not shared
57 */
58 uint32_t num_cu_shared;
59};
60
61static struct kfd_gpu_cache_info kaveri_cache_info[] = {
62 {
63 /* TCP L1 Cache per CU */
64 .cache_size = 16,
65 .cache_level = 1,
66 .flags = (CRAT_CACHE_FLAGS_ENABLED |
67 CRAT_CACHE_FLAGS_DATA_CACHE |
68 CRAT_CACHE_FLAGS_SIMD_CACHE),
69 .num_cu_shared = 1,
70
71 },
72 {
73 /* Scalar L1 Instruction Cache (in SQC module) per bank */
74 .cache_size = 16,
75 .cache_level = 1,
76 .flags = (CRAT_CACHE_FLAGS_ENABLED |
77 CRAT_CACHE_FLAGS_INST_CACHE |
78 CRAT_CACHE_FLAGS_SIMD_CACHE),
79 .num_cu_shared = 2,
80 },
81 {
82 /* Scalar L1 Data Cache (in SQC module) per bank */
83 .cache_size = 8,
84 .cache_level = 1,
85 .flags = (CRAT_CACHE_FLAGS_ENABLED |
86 CRAT_CACHE_FLAGS_DATA_CACHE |
87 CRAT_CACHE_FLAGS_SIMD_CACHE),
88 .num_cu_shared = 2,
89 },
90
91 /* TODO: Add L2 Cache information */
92};
93
94
95static struct kfd_gpu_cache_info carrizo_cache_info[] = {
96 {
97 /* TCP L1 Cache per CU */
98 .cache_size = 16,
99 .cache_level = 1,
100 .flags = (CRAT_CACHE_FLAGS_ENABLED |
101 CRAT_CACHE_FLAGS_DATA_CACHE |
102 CRAT_CACHE_FLAGS_SIMD_CACHE),
103 .num_cu_shared = 1,
104 },
105 {
106 /* Scalar L1 Instruction Cache (in SQC module) per bank */
107 .cache_size = 8,
108 .cache_level = 1,
109 .flags = (CRAT_CACHE_FLAGS_ENABLED |
110 CRAT_CACHE_FLAGS_INST_CACHE |
111 CRAT_CACHE_FLAGS_SIMD_CACHE),
112 .num_cu_shared = 4,
113 },
114 {
115 /* Scalar L1 Data Cache (in SQC module) per bank. */
116 .cache_size = 4,
117 .cache_level = 1,
118 .flags = (CRAT_CACHE_FLAGS_ENABLED |
119 CRAT_CACHE_FLAGS_DATA_CACHE |
120 CRAT_CACHE_FLAGS_SIMD_CACHE),
121 .num_cu_shared = 4,
122 },
123
124 /* TODO: Add L2 Cache information */
125};
126
127/* NOTE: In future if more information is added to struct kfd_gpu_cache_info
128 * the following ASICs may need a separate table.
129 */
130#define hawaii_cache_info kaveri_cache_info
131#define tonga_cache_info carrizo_cache_info
132#define fiji_cache_info carrizo_cache_info
133#define polaris10_cache_info carrizo_cache_info
134#define polaris11_cache_info carrizo_cache_info
135
136static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
137 struct crat_subtype_computeunit *cu)
138{
139 dev->node_props.cpu_cores_count = cu->num_cpu_cores;
140 dev->node_props.cpu_core_id_base = cu->processor_id_low;
141 if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
142 dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
143
144 pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
145 cu->processor_id_low);
146}
147
148static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
149 struct crat_subtype_computeunit *cu)
150{
151 dev->node_props.simd_id_base = cu->processor_id_low;
152 dev->node_props.simd_count = cu->num_simd_cores;
153 dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
154 dev->node_props.max_waves_per_simd = cu->max_waves_simd;
155 dev->node_props.wave_front_size = cu->wave_front_size;
156 dev->node_props.array_count = cu->array_count;
157 dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
158 dev->node_props.simd_per_cu = cu->num_simd_per_cu;
159 dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
160 if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
161 dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
162 pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low);
163}
164
165/* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct
166 * topology device present in the device_list
167 */
168static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu,
169 struct list_head *device_list)
170{
171 struct kfd_topology_device *dev;
172
173 pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
174 cu->proximity_domain, cu->hsa_capability);
175 list_for_each_entry(dev, device_list, list) {
176 if (cu->proximity_domain == dev->proximity_domain) {
177 if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
178 kfd_populated_cu_info_cpu(dev, cu);
179
180 if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
181 kfd_populated_cu_info_gpu(dev, cu);
182 break;
183 }
184 }
185
186 return 0;
187}
188
189/* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
190 * topology device present in the device_list
191 */
192static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem,
193 struct list_head *device_list)
194{
195 struct kfd_mem_properties *props;
196 struct kfd_topology_device *dev;
197
198 pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
199 mem->proximity_domain);
200 list_for_each_entry(dev, device_list, list) {
201 if (mem->proximity_domain == dev->proximity_domain) {
202 props = kfd_alloc_struct(props);
203 if (!props)
204 return -ENOMEM;
205
206 /* We're on GPU node */
207 if (dev->node_props.cpu_cores_count == 0) {
208 /* APU */
209 if (mem->visibility_type == 0)
210 props->heap_type =
211 HSA_MEM_HEAP_TYPE_FB_PRIVATE;
212 /* dGPU */
213 else
214 props->heap_type = mem->visibility_type;
215 } else
216 props->heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
217
218 if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
219 props->flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
220 if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
221 props->flags |= HSA_MEM_FLAGS_NON_VOLATILE;
222
223 props->size_in_bytes =
224 ((uint64_t)mem->length_high << 32) +
225 mem->length_low;
226 props->width = mem->width;
227
228 dev->node_props.mem_banks_count++;
229 list_add_tail(&props->list, &dev->mem_props);
230
231 break;
232 }
233 }
234
235 return 0;
236}
237
238/* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct
239 * topology device present in the device_list
240 */
241static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache,
242 struct list_head *device_list)
243{
244 struct kfd_cache_properties *props;
245 struct kfd_topology_device *dev;
246 uint32_t id;
247 uint32_t total_num_of_cu;
248
249 id = cache->processor_id_low;
250
251 pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
252 list_for_each_entry(dev, device_list, list) {
253 total_num_of_cu = (dev->node_props.array_count *
254 dev->node_props.cu_per_simd_array);
255
256 /* Cache infomration in CRAT doesn't have proximity_domain
257 * information as it is associated with a CPU core or GPU
258 * Compute Unit. So map the cache using CPU core Id or SIMD
259 * (GPU) ID.
260 * TODO: This works because currently we can safely assume that
261 * Compute Units are parsed before caches are parsed. In
262 * future, remove this dependency
263 */
264 if ((id >= dev->node_props.cpu_core_id_base &&
265 id <= dev->node_props.cpu_core_id_base +
266 dev->node_props.cpu_cores_count) ||
267 (id >= dev->node_props.simd_id_base &&
268 id < dev->node_props.simd_id_base +
269 total_num_of_cu)) {
270 props = kfd_alloc_struct(props);
271 if (!props)
272 return -ENOMEM;
273
274 props->processor_id_low = id;
275 props->cache_level = cache->cache_level;
276 props->cache_size = cache->cache_size;
277 props->cacheline_size = cache->cache_line_size;
278 props->cachelines_per_tag = cache->lines_per_tag;
279 props->cache_assoc = cache->associativity;
280 props->cache_latency = cache->cache_latency;
281 memcpy(props->sibling_map, cache->sibling_map,
282 sizeof(props->sibling_map));
283
284 if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
285 props->cache_type |= HSA_CACHE_TYPE_DATA;
286 if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
287 props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
288 if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
289 props->cache_type |= HSA_CACHE_TYPE_CPU;
290 if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
291 props->cache_type |= HSA_CACHE_TYPE_HSACU;
292
293 dev->cache_count++;
294 dev->node_props.caches_count++;
295 list_add_tail(&props->list, &dev->cache_props);
296
297 break;
298 }
299 }
300
301 return 0;
302}
303
304/* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct
305 * topology device present in the device_list
306 */
307static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
308 struct list_head *device_list)
309{
310 struct kfd_iolink_properties *props = NULL, *props2;
311 struct kfd_topology_device *dev, *cpu_dev;
312 uint32_t id_from;
313 uint32_t id_to;
314
315 id_from = iolink->proximity_domain_from;
316 id_to = iolink->proximity_domain_to;
317
318 pr_debug("Found IO link entry in CRAT table with id_from=%d\n",
319 id_from);
320 list_for_each_entry(dev, device_list, list) {
321 if (id_from == dev->proximity_domain) {
322 props = kfd_alloc_struct(props);
323 if (!props)
324 return -ENOMEM;
325
326 props->node_from = id_from;
327 props->node_to = id_to;
328 props->ver_maj = iolink->version_major;
329 props->ver_min = iolink->version_minor;
330 props->iolink_type = iolink->io_interface_type;
331
332 if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
333 props->weight = 20;
334 else
335 props->weight = node_distance(id_from, id_to);
336
337 props->min_latency = iolink->minimum_latency;
338 props->max_latency = iolink->maximum_latency;
339 props->min_bandwidth = iolink->minimum_bandwidth_mbs;
340 props->max_bandwidth = iolink->maximum_bandwidth_mbs;
341 props->rec_transfer_size =
342 iolink->recommended_transfer_size;
343
344 dev->io_link_count++;
345 dev->node_props.io_links_count++;
346 list_add_tail(&props->list, &dev->io_link_props);
347 break;
348 }
349 }
350
351 /* CPU topology is created before GPUs are detected, so CPU->GPU
352 * links are not built at that time. If a PCIe type is discovered, it
353 * means a GPU is detected and we are adding GPU->CPU to the topology.
354 * At this time, also add the corresponded CPU->GPU link.
355 */
356 if (props && props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS) {
357 cpu_dev = kfd_topology_device_by_proximity_domain(id_to);
358 if (!cpu_dev)
359 return -ENODEV;
360 /* same everything but the other direction */
361 props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL);
362 props2->node_from = id_to;
363 props2->node_to = id_from;
364 props2->kobj = NULL;
365 cpu_dev->io_link_count++;
366 cpu_dev->node_props.io_links_count++;
367 list_add_tail(&props2->list, &cpu_dev->io_link_props);
368 }
369
370 return 0;
371}
372
373/* kfd_parse_subtype - parse subtypes and attach it to correct topology device
374 * present in the device_list
375 * @sub_type_hdr - subtype section of crat_image
376 * @device_list - list of topology devices present in this crat_image
377 */
378static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr,
379 struct list_head *device_list)
380{
381 struct crat_subtype_computeunit *cu;
382 struct crat_subtype_memory *mem;
383 struct crat_subtype_cache *cache;
384 struct crat_subtype_iolink *iolink;
385 int ret = 0;
386
387 switch (sub_type_hdr->type) {
388 case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
389 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
390 ret = kfd_parse_subtype_cu(cu, device_list);
391 break;
392 case CRAT_SUBTYPE_MEMORY_AFFINITY:
393 mem = (struct crat_subtype_memory *)sub_type_hdr;
394 ret = kfd_parse_subtype_mem(mem, device_list);
395 break;
396 case CRAT_SUBTYPE_CACHE_AFFINITY:
397 cache = (struct crat_subtype_cache *)sub_type_hdr;
398 ret = kfd_parse_subtype_cache(cache, device_list);
399 break;
400 case CRAT_SUBTYPE_TLB_AFFINITY:
401 /*
402 * For now, nothing to do here
403 */
404 pr_debug("Found TLB entry in CRAT table (not processing)\n");
405 break;
406 case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
407 /*
408 * For now, nothing to do here
409 */
410 pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n");
411 break;
412 case CRAT_SUBTYPE_IOLINK_AFFINITY:
413 iolink = (struct crat_subtype_iolink *)sub_type_hdr;
414 ret = kfd_parse_subtype_iolink(iolink, device_list);
415 break;
416 default:
417 pr_warn("Unknown subtype %d in CRAT\n",
418 sub_type_hdr->type);
419 }
420
421 return ret;
422}
423
424/* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT
425 * create a kfd_topology_device and add in to device_list. Also parse
426 * CRAT subtypes and attach it to appropriate kfd_topology_device
427 * @crat_image - input image containing CRAT
428 * @device_list - [OUT] list of kfd_topology_device generated after
429 * parsing crat_image
430 * @proximity_domain - Proximity domain of the first device in the table
431 *
432 * Return - 0 if successful else -ve value
433 */
434int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
435 uint32_t proximity_domain)
436{
437 struct kfd_topology_device *top_dev = NULL;
438 struct crat_subtype_generic *sub_type_hdr;
439 uint16_t node_id;
440 int ret = 0;
441 struct crat_header *crat_table = (struct crat_header *)crat_image;
442 uint16_t num_nodes;
443 uint32_t image_len;
444
445 if (!crat_image)
446 return -EINVAL;
447
448 if (!list_empty(device_list)) {
449 pr_warn("Error device list should be empty\n");
450 return -EINVAL;
451 }
452
453 num_nodes = crat_table->num_domains;
454 image_len = crat_table->length;
455
456 pr_info("Parsing CRAT table with %d nodes\n", num_nodes);
457
458 for (node_id = 0; node_id < num_nodes; node_id++) {
459 top_dev = kfd_create_topology_device(device_list);
460 if (!top_dev)
461 break;
462 top_dev->proximity_domain = proximity_domain++;
463 }
464
465 if (!top_dev) {
466 ret = -ENOMEM;
467 goto err;
468 }
469
470 memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH);
471 memcpy(top_dev->oem_table_id, crat_table->oem_table_id,
472 CRAT_OEMTABLEID_LENGTH);
473 top_dev->oem_revision = crat_table->oem_revision;
474
475 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
476 while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
477 ((char *)crat_image) + image_len) {
478 if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
479 ret = kfd_parse_subtype(sub_type_hdr, device_list);
480 if (ret)
481 break;
482 }
483
484 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
485 sub_type_hdr->length);
486 }
487
488err:
489 if (ret)
490 kfd_release_topology_device_list(device_list);
491
492 return ret;
493}
494
495/* Helper function. See kfd_fill_gpu_cache_info for parameter description */
496static int fill_in_pcache(struct crat_subtype_cache *pcache,
497 struct kfd_gpu_cache_info *pcache_info,
498 struct kfd_cu_info *cu_info,
499 int mem_available,
500 int cu_bitmask,
501 int cache_type, unsigned int cu_processor_id,
502 int cu_block)
503{
504 unsigned int cu_sibling_map_mask;
505 int first_active_cu;
506
507 /* First check if enough memory is available */
508 if (sizeof(struct crat_subtype_cache) > mem_available)
509 return -ENOMEM;
510
511 cu_sibling_map_mask = cu_bitmask;
512 cu_sibling_map_mask >>= cu_block;
513 cu_sibling_map_mask &=
514 ((1 << pcache_info[cache_type].num_cu_shared) - 1);
515 first_active_cu = ffs(cu_sibling_map_mask);
516
517 /* CU could be inactive. In case of shared cache find the first active
518 * CU. and incase of non-shared cache check if the CU is inactive. If
519 * inactive active skip it
520 */
521 if (first_active_cu) {
522 memset(pcache, 0, sizeof(struct crat_subtype_cache));
523 pcache->type = CRAT_SUBTYPE_CACHE_AFFINITY;
524 pcache->length = sizeof(struct crat_subtype_cache);
525 pcache->flags = pcache_info[cache_type].flags;
526 pcache->processor_id_low = cu_processor_id
527 + (first_active_cu - 1);
528 pcache->cache_level = pcache_info[cache_type].cache_level;
529 pcache->cache_size = pcache_info[cache_type].cache_size;
530
531 /* Sibling map is w.r.t processor_id_low, so shift out
532 * inactive CU
533 */
534 cu_sibling_map_mask =
535 cu_sibling_map_mask >> (first_active_cu - 1);
536
537 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
538 pcache->sibling_map[1] =
539 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
540 pcache->sibling_map[2] =
541 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
542 pcache->sibling_map[3] =
543 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
544 return 0;
545 }
546 return 1;
547}
548
549/* kfd_fill_gpu_cache_info - Fill GPU cache info using kfd_gpu_cache_info
550 * tables
551 *
552 * @kdev - [IN] GPU device
553 * @gpu_processor_id - [IN] GPU processor ID to which these caches
554 * associate
555 * @available_size - [IN] Amount of memory available in pcache
556 * @cu_info - [IN] Compute Unit info obtained from KGD
557 * @pcache - [OUT] memory into which cache data is to be filled in.
558 * @size_filled - [OUT] amount of data used up in pcache.
559 * @num_of_entries - [OUT] number of caches added
560 */
561static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
562 int gpu_processor_id,
563 int available_size,
564 struct kfd_cu_info *cu_info,
565 struct crat_subtype_cache *pcache,
566 int *size_filled,
567 int *num_of_entries)
568{
569 struct kfd_gpu_cache_info *pcache_info;
570 int num_of_cache_types = 0;
571 int i, j, k;
572 int ct = 0;
573 int mem_available = available_size;
574 unsigned int cu_processor_id;
575 int ret;
576
577 switch (kdev->device_info->asic_family) {
578 case CHIP_KAVERI:
579 pcache_info = kaveri_cache_info;
580 num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
581 break;
582 case CHIP_HAWAII:
583 pcache_info = hawaii_cache_info;
584 num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
585 break;
586 case CHIP_CARRIZO:
587 pcache_info = carrizo_cache_info;
588 num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);
589 break;
590 case CHIP_TONGA:
591 pcache_info = tonga_cache_info;
592 num_of_cache_types = ARRAY_SIZE(tonga_cache_info);
593 break;
594 case CHIP_FIJI:
595 pcache_info = fiji_cache_info;
596 num_of_cache_types = ARRAY_SIZE(fiji_cache_info);
597 break;
598 case CHIP_POLARIS10:
599 pcache_info = polaris10_cache_info;
600 num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);
601 break;
602 case CHIP_POLARIS11:
603 pcache_info = polaris11_cache_info;
604 num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
605 break;
606 default:
607 return -EINVAL;
608 }
609
610 *size_filled = 0;
611 *num_of_entries = 0;
612
613 /* For each type of cache listed in the kfd_gpu_cache_info table,
614 * go through all available Compute Units.
615 * The [i,j,k] loop will
616 * if kfd_gpu_cache_info.num_cu_shared = 1
617 * will parse through all available CU
618 * If (kfd_gpu_cache_info.num_cu_shared != 1)
619 * then it will consider only one CU from
620 * the shared unit
621 */
622
623 for (ct = 0; ct < num_of_cache_types; ct++) {
624 cu_processor_id = gpu_processor_id;
625 for (i = 0; i < cu_info->num_shader_engines; i++) {
626 for (j = 0; j < cu_info->num_shader_arrays_per_engine;
627 j++) {
628 for (k = 0; k < cu_info->num_cu_per_sh;
629 k += pcache_info[ct].num_cu_shared) {
630
631 ret = fill_in_pcache(pcache,
632 pcache_info,
633 cu_info,
634 mem_available,
635 cu_info->cu_bitmap[i][j],
636 ct,
637 cu_processor_id,
638 k);
639
640 if (ret < 0)
641 break;
642
643 if (!ret) {
644 pcache++;
645 (*num_of_entries)++;
646 mem_available -=
647 sizeof(*pcache);
648 (*size_filled) +=
649 sizeof(*pcache);
650 }
651
652 /* Move to next CU block */
653 cu_processor_id +=
654 pcache_info[ct].num_cu_shared;
655 }
656 }
657 }
658 }
659
660 pr_debug("Added [%d] GPU cache entries\n", *num_of_entries);
661
662 return 0;
663}
664
665/*
666 * kfd_create_crat_image_acpi - Allocates memory for CRAT image and
667 * copies CRAT from ACPI (if available).
668 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
669 *
670 * @crat_image: CRAT read from ACPI. If no CRAT in ACPI then
671 * crat_image will be NULL
672 * @size: [OUT] size of crat_image
673 *
674 * Return 0 if successful else return error code
675 */
676int kfd_create_crat_image_acpi(void **crat_image, size_t *size)
677{
678 struct acpi_table_header *crat_table;
679 acpi_status status;
680 void *pcrat_image;
681
682 if (!crat_image)
683 return -EINVAL;
684
685 *crat_image = NULL;
686
687 /* Fetch the CRAT table from ACPI */
688 status = acpi_get_table(CRAT_SIGNATURE, 0, &crat_table);
689 if (status == AE_NOT_FOUND) {
690 pr_warn("CRAT table not found\n");
691 return -ENODATA;
692 } else if (ACPI_FAILURE(status)) {
693 const char *err = acpi_format_exception(status);
694
695 pr_err("CRAT table error: %s\n", err);
696 return -EINVAL;
697 }
698
699 if (ignore_crat) {
700 pr_info("CRAT table disabled by module option\n");
701 return -ENODATA;
702 }
703
704 pcrat_image = kmalloc(crat_table->length, GFP_KERNEL);
705 if (!pcrat_image)
706 return -ENOMEM;
707
708 memcpy(pcrat_image, crat_table, crat_table->length);
709
710 *crat_image = pcrat_image;
711 *size = crat_table->length;
712
713 return 0;
714}
715
716/* Memory required to create Virtual CRAT.
717 * Since there is no easy way to predict the amount of memory required, the
718 * following amount are allocated for CPU and GPU Virtual CRAT. This is
719 * expected to cover all known conditions. But to be safe additional check
720 * is put in the code to ensure we don't overwrite.
721 */
722#define VCRAT_SIZE_FOR_CPU (2 * PAGE_SIZE)
723#define VCRAT_SIZE_FOR_GPU (3 * PAGE_SIZE)
724
725/* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
726 *
727 * @numa_node_id: CPU NUMA node id
728 * @avail_size: Available size in the memory
729 * @sub_type_hdr: Memory into which compute info will be filled in
730 *
731 * Return 0 if successful else return -ve value
732 */
733static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size,
734 int proximity_domain,
735 struct crat_subtype_computeunit *sub_type_hdr)
736{
737 const struct cpumask *cpumask;
738
739 *avail_size -= sizeof(struct crat_subtype_computeunit);
740 if (*avail_size < 0)
741 return -ENOMEM;
742
743 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
744
745 /* Fill in subtype header data */
746 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
747 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
748 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
749
750 cpumask = cpumask_of_node(numa_node_id);
751
752 /* Fill in CU data */
753 sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
754 sub_type_hdr->proximity_domain = proximity_domain;
755 sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id);
756 if (sub_type_hdr->processor_id_low == -1)
757 return -EINVAL;
758
759 sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask);
760
761 return 0;
762}
763
764/* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node
765 *
766 * @numa_node_id: CPU NUMA node id
767 * @avail_size: Available size in the memory
768 * @sub_type_hdr: Memory into which compute info will be filled in
769 *
770 * Return 0 if successful else return -ve value
771 */
772static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
773 int proximity_domain,
774 struct crat_subtype_memory *sub_type_hdr)
775{
776 uint64_t mem_in_bytes = 0;
777 pg_data_t *pgdat;
778 int zone_type;
779
780 *avail_size -= sizeof(struct crat_subtype_memory);
781 if (*avail_size < 0)
782 return -ENOMEM;
783
784 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
785
786 /* Fill in subtype header data */
787 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
788 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
789 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
790
791 /* Fill in Memory Subunit data */
792
793 /* Unlike si_meminfo, si_meminfo_node is not exported. So
794 * the following lines are duplicated from si_meminfo_node
795 * function
796 */
797 pgdat = NODE_DATA(numa_node_id);
798 for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
799 mem_in_bytes += pgdat->node_zones[zone_type].managed_pages;
800 mem_in_bytes <<= PAGE_SHIFT;
801
802 sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
803 sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
804 sub_type_hdr->proximity_domain = proximity_domain;
805
806 return 0;
807}
808
809static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
810 uint32_t *num_entries,
811 struct crat_subtype_iolink *sub_type_hdr)
812{
813 int nid;
814 struct cpuinfo_x86 *c = &cpu_data(0);
815 uint8_t link_type;
816
817 if (c->x86_vendor == X86_VENDOR_AMD)
818 link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT;
819 else
820 link_type = CRAT_IOLINK_TYPE_QPI_1_1;
821
822 *num_entries = 0;
823
824 /* Create IO links from this node to other CPU nodes */
825 for_each_online_node(nid) {
826 if (nid == numa_node_id) /* node itself */
827 continue;
828
829 *avail_size -= sizeof(struct crat_subtype_iolink);
830 if (*avail_size < 0)
831 return -ENOMEM;
832
833 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
834
835 /* Fill in subtype header data */
836 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
837 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
838 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
839
840 /* Fill in IO link data */
841 sub_type_hdr->proximity_domain_from = numa_node_id;
842 sub_type_hdr->proximity_domain_to = nid;
843 sub_type_hdr->io_interface_type = link_type;
844
845 (*num_entries)++;
846 sub_type_hdr++;
847 }
848
849 return 0;
850}
851
852/* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
853 *
854 * @pcrat_image: Fill in VCRAT for CPU
855 * @size: [IN] allocated size of crat_image.
856 * [OUT] actual size of data filled in crat_image
857 */
858static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
859{
860 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
861 struct acpi_table_header *acpi_table;
862 acpi_status status;
863 struct crat_subtype_generic *sub_type_hdr;
864 int avail_size = *size;
865 int numa_node_id;
866 uint32_t entries = 0;
867 int ret = 0;
868
869 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_CPU)
870 return -EINVAL;
871
872 /* Fill in CRAT Header.
873 * Modify length and total_entries as subunits are added.
874 */
875 avail_size -= sizeof(struct crat_header);
876 if (avail_size < 0)
877 return -ENOMEM;
878
879 memset(crat_table, 0, sizeof(struct crat_header));
880 memcpy(&crat_table->signature, CRAT_SIGNATURE,
881 sizeof(crat_table->signature));
882 crat_table->length = sizeof(struct crat_header);
883
884 status = acpi_get_table("DSDT", 0, &acpi_table);
885 if (status != AE_OK)
886 pr_warn("DSDT table not found for OEM information\n");
887 else {
888 crat_table->oem_revision = acpi_table->revision;
889 memcpy(crat_table->oem_id, acpi_table->oem_id,
890 CRAT_OEMID_LENGTH);
891 memcpy(crat_table->oem_table_id, acpi_table->oem_table_id,
892 CRAT_OEMTABLEID_LENGTH);
893 }
894 crat_table->total_entries = 0;
895 crat_table->num_domains = 0;
896
897 sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
898
899 for_each_online_node(numa_node_id) {
900 if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
901 continue;
902
903 /* Fill in Subtype: Compute Unit */
904 ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
905 crat_table->num_domains,
906 (struct crat_subtype_computeunit *)sub_type_hdr);
907 if (ret < 0)
908 return ret;
909 crat_table->length += sub_type_hdr->length;
910 crat_table->total_entries++;
911
912 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
913 sub_type_hdr->length);
914
915 /* Fill in Subtype: Memory */
916 ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size,
917 crat_table->num_domains,
918 (struct crat_subtype_memory *)sub_type_hdr);
919 if (ret < 0)
920 return ret;
921 crat_table->length += sub_type_hdr->length;
922 crat_table->total_entries++;
923
924 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
925 sub_type_hdr->length);
926
927 /* Fill in Subtype: IO Link */
928 ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
929 &entries,
930 (struct crat_subtype_iolink *)sub_type_hdr);
931 if (ret < 0)
932 return ret;
933 crat_table->length += (sub_type_hdr->length * entries);
934 crat_table->total_entries += entries;
935
936 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
937 sub_type_hdr->length * entries);
938
939 crat_table->num_domains++;
940 }
941
942 /* TODO: Add cache Subtype for CPU.
943 * Currently, CPU cache information is available in function
944 * detect_cache_attributes(cpu) defined in the file
945 * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not
946 * exported and to get the same information the code needs to be
947 * duplicated.
948 */
949
950 *size = crat_table->length;
951 pr_info("Virtual CRAT table created for CPU\n");
952
953 return 0;
954}
955
956static int kfd_fill_gpu_memory_affinity(int *avail_size,
957 struct kfd_dev *kdev, uint8_t type, uint64_t size,
958 struct crat_subtype_memory *sub_type_hdr,
959 uint32_t proximity_domain,
960 const struct kfd_local_mem_info *local_mem_info)
961{
962 *avail_size -= sizeof(struct crat_subtype_memory);
963 if (*avail_size < 0)
964 return -ENOMEM;
965
966 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
967 sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
968 sub_type_hdr->length = sizeof(struct crat_subtype_memory);
969 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
970
971 sub_type_hdr->proximity_domain = proximity_domain;
972
973 pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n",
974 type, size);
975
976 sub_type_hdr->length_low = lower_32_bits(size);
977 sub_type_hdr->length_high = upper_32_bits(size);
978
979 sub_type_hdr->width = local_mem_info->vram_width;
980 sub_type_hdr->visibility_type = type;
981
982 return 0;
983}
984
985/* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
986 * to its NUMA node
987 * @avail_size: Available size in the memory
988 * @kdev - [IN] GPU device
989 * @sub_type_hdr: Memory into which io link info will be filled in
990 * @proximity_domain - proximity domain of the GPU node
991 *
992 * Return 0 if successful else return -ve value
993 */
994static int kfd_fill_gpu_direct_io_link(int *avail_size,
995 struct kfd_dev *kdev,
996 struct crat_subtype_iolink *sub_type_hdr,
997 uint32_t proximity_domain)
998{
999 *avail_size -= sizeof(struct crat_subtype_iolink);
1000 if (*avail_size < 0)
1001 return -ENOMEM;
1002
1003 memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1004
1005 /* Fill in subtype header data */
1006 sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1007 sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1008 sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1009
1010 /* Fill in IOLINK subtype.
1011 * TODO: Fill-in other fields of iolink subtype
1012 */
1013 sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
1014 sub_type_hdr->proximity_domain_from = proximity_domain;
1015#ifdef CONFIG_NUMA
1016 if (kdev->pdev->dev.numa_node == NUMA_NO_NODE)
1017 sub_type_hdr->proximity_domain_to = 0;
1018 else
1019 sub_type_hdr->proximity_domain_to = kdev->pdev->dev.numa_node;
1020#else
1021 sub_type_hdr->proximity_domain_to = 0;
1022#endif
1023 return 0;
1024}
1025
1026/* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU
1027 *
1028 * @pcrat_image: Fill in VCRAT for GPU
1029 * @size: [IN] allocated size of crat_image.
1030 * [OUT] actual size of data filled in crat_image
1031 */
1032static int kfd_create_vcrat_image_gpu(void *pcrat_image,
1033 size_t *size, struct kfd_dev *kdev,
1034 uint32_t proximity_domain)
1035{
1036 struct crat_header *crat_table = (struct crat_header *)pcrat_image;
1037 struct crat_subtype_generic *sub_type_hdr;
1038 struct crat_subtype_computeunit *cu;
1039 struct kfd_cu_info cu_info;
1040 int avail_size = *size;
1041 uint32_t total_num_of_cu;
1042 int num_of_cache_entries = 0;
1043 int cache_mem_filled = 0;
1044 int ret = 0;
1045 struct kfd_local_mem_info local_mem_info;
1046
1047 if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
1048 return -EINVAL;
1049
1050 /* Fill the CRAT Header.
1051 * Modify length and total_entries as subunits are added.
1052 */
1053 avail_size -= sizeof(struct crat_header);
1054 if (avail_size < 0)
1055 return -ENOMEM;
1056
1057 memset(crat_table, 0, sizeof(struct crat_header));
1058
1059 memcpy(&crat_table->signature, CRAT_SIGNATURE,
1060 sizeof(crat_table->signature));
1061 /* Change length as we add more subtypes*/
1062 crat_table->length = sizeof(struct crat_header);
1063 crat_table->num_domains = 1;
1064 crat_table->total_entries = 0;
1065
1066 /* Fill in Subtype: Compute Unit
1067 * First fill in the sub type header and then sub type data
1068 */
1069 avail_size -= sizeof(struct crat_subtype_computeunit);
1070 if (avail_size < 0)
1071 return -ENOMEM;
1072
1073 sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
1074 memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
1075
1076 sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
1077 sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
1078 sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1079
1080 /* Fill CU subtype data */
1081 cu = (struct crat_subtype_computeunit *)sub_type_hdr;
1082 cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
1083 cu->proximity_domain = proximity_domain;
1084
1085 kdev->kfd2kgd->get_cu_info(kdev->kgd, &cu_info);
1086 cu->num_simd_per_cu = cu_info.simd_per_cu;
1087 cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number;
1088 cu->max_waves_simd = cu_info.max_waves_per_simd;
1089
1090 cu->wave_front_size = cu_info.wave_front_size;
1091 cu->array_count = cu_info.num_shader_arrays_per_engine *
1092 cu_info.num_shader_engines;
1093 total_num_of_cu = (cu->array_count * cu_info.num_cu_per_sh);
1094 cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu);
1095 cu->num_cu_per_array = cu_info.num_cu_per_sh;
1096 cu->max_slots_scatch_cu = cu_info.max_scratch_slots_per_cu;
1097 cu->num_banks = cu_info.num_shader_engines;
1098 cu->lds_size_in_kb = cu_info.lds_size;
1099
1100 cu->hsa_capability = 0;
1101
1102 /* Check if this node supports IOMMU. During parsing this flag will
1103 * translate to HSA_CAP_ATS_PRESENT
1104 */
1105 if (!kfd_iommu_check_device(kdev))
1106 cu->hsa_capability |= CRAT_CU_FLAGS_IOMMU_PRESENT;
1107
1108 crat_table->length += sub_type_hdr->length;
1109 crat_table->total_entries++;
1110
1111 /* Fill in Subtype: Memory. Only on systems with large BAR (no
1112 * private FB), report memory as public. On other systems
1113 * report the total FB size (public+private) as a single
1114 * private heap.
1115 */
1116 kdev->kfd2kgd->get_local_mem_info(kdev->kgd, &local_mem_info);
1117 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1118 sub_type_hdr->length);
1119
1120 if (debug_largebar)
1121 local_mem_info.local_mem_size_private = 0;
1122
1123 if (local_mem_info.local_mem_size_private == 0)
1124 ret = kfd_fill_gpu_memory_affinity(&avail_size,
1125 kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
1126 local_mem_info.local_mem_size_public,
1127 (struct crat_subtype_memory *)sub_type_hdr,
1128 proximity_domain,
1129 &local_mem_info);
1130 else
1131 ret = kfd_fill_gpu_memory_affinity(&avail_size,
1132 kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE,
1133 local_mem_info.local_mem_size_public +
1134 local_mem_info.local_mem_size_private,
1135 (struct crat_subtype_memory *)sub_type_hdr,
1136 proximity_domain,
1137 &local_mem_info);
1138 if (ret < 0)
1139 return ret;
1140
1141 crat_table->length += sizeof(struct crat_subtype_memory);
1142 crat_table->total_entries++;
1143
1144 /* TODO: Fill in cache information. This information is NOT readily
1145 * available in KGD
1146 */
1147 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1148 sub_type_hdr->length);
1149 ret = kfd_fill_gpu_cache_info(kdev, cu->processor_id_low,
1150 avail_size,
1151 &cu_info,
1152 (struct crat_subtype_cache *)sub_type_hdr,
1153 &cache_mem_filled,
1154 &num_of_cache_entries);
1155
1156 if (ret < 0)
1157 return ret;
1158
1159 crat_table->length += cache_mem_filled;
1160 crat_table->total_entries += num_of_cache_entries;
1161 avail_size -= cache_mem_filled;
1162
1163 /* Fill in Subtype: IO_LINKS
1164 * Only direct links are added here which is Link from GPU to
1165 * to its NUMA node. Indirect links are added by userspace.
1166 */
1167 sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1168 cache_mem_filled);
1169 ret = kfd_fill_gpu_direct_io_link(&avail_size, kdev,
1170 (struct crat_subtype_iolink *)sub_type_hdr, proximity_domain);
1171
1172 if (ret < 0)
1173 return ret;
1174
1175 crat_table->length += sub_type_hdr->length;
1176 crat_table->total_entries++;
1177
1178 *size = crat_table->length;
1179 pr_info("Virtual CRAT table created for GPU\n");
1180
1181 return ret;
1182}
1183
1184/* kfd_create_crat_image_virtual - Allocates memory for CRAT image and
1185 * creates a Virtual CRAT (VCRAT) image
1186 *
1187 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
1188 *
1189 * @crat_image: VCRAT image created because ACPI does not have a
1190 * CRAT for this device
1191 * @size: [OUT] size of virtual crat_image
1192 * @flags: COMPUTE_UNIT_CPU - Create VCRAT for CPU device
1193 * COMPUTE_UNIT_GPU - Create VCRAT for GPU
1194 * (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU
1195 * -- this option is not currently implemented.
1196 * The assumption is that all AMD APUs will have CRAT
1197 * @kdev: Valid kfd_device required if flags contain COMPUTE_UNIT_GPU
1198 *
1199 * Return 0 if successful else return -ve value
1200 */
1201int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
1202 int flags, struct kfd_dev *kdev,
1203 uint32_t proximity_domain)
1204{
1205 void *pcrat_image = NULL;
1206 int ret = 0;
1207
1208 if (!crat_image)
1209 return -EINVAL;
1210
1211 *crat_image = NULL;
1212
1213 /* Allocate one VCRAT_SIZE_FOR_CPU for CPU virtual CRAT image and
1214 * VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image. This should cover
1215 * all the current conditions. A check is put not to overwrite beyond
1216 * allocated size
1217 */
1218 switch (flags) {
1219 case COMPUTE_UNIT_CPU:
1220 pcrat_image = kmalloc(VCRAT_SIZE_FOR_CPU, GFP_KERNEL);
1221 if (!pcrat_image)
1222 return -ENOMEM;
1223 *size = VCRAT_SIZE_FOR_CPU;
1224 ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
1225 break;
1226 case COMPUTE_UNIT_GPU:
1227 if (!kdev)
1228 return -EINVAL;
1229 pcrat_image = kmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL);
1230 if (!pcrat_image)
1231 return -ENOMEM;
1232 *size = VCRAT_SIZE_FOR_GPU;
1233 ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev,
1234 proximity_domain);
1235 break;
1236 case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU):
1237 /* TODO: */
1238 ret = -EINVAL;
1239 pr_err("VCRAT not implemented for APU\n");
1240 break;
1241 default:
1242 ret = -EINVAL;
1243 }
1244
1245 if (!ret)
1246 *crat_image = pcrat_image;
1247 else
1248 kfree(pcrat_image);
1249
1250 return ret;
1251}
1252
1253
1254/* kfd_destroy_crat_image
1255 *
1256 * @crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..)
1257 *
1258 */
1259void kfd_destroy_crat_image(void *crat_image)
1260{
1261 kfree(crat_image);
1262}