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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
4 */
5#include <linux/platform_device.h>
6#include <linux/init.h>
7#include <linux/cpumask.h>
8#include <linux/export.h>
9#include <linux/dma-mapping.h>
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/qcom_scm.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_platform.h>
16#include <linux/clk.h>
17#include <linux/reset-controller.h>
18#include <linux/arm-smccc.h>
19
20#include "qcom_scm.h"
21
22static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
23module_param(download_mode, bool, 0);
24
25#define SCM_HAS_CORE_CLK BIT(0)
26#define SCM_HAS_IFACE_CLK BIT(1)
27#define SCM_HAS_BUS_CLK BIT(2)
28
29struct qcom_scm {
30 struct device *dev;
31 struct clk *core_clk;
32 struct clk *iface_clk;
33 struct clk *bus_clk;
34 struct reset_controller_dev reset;
35
36 u64 dload_mode_addr;
37};
38
39struct qcom_scm_current_perm_info {
40 __le32 vmid;
41 __le32 perm;
42 __le64 ctx;
43 __le32 ctx_size;
44 __le32 unused;
45};
46
47struct qcom_scm_mem_map_info {
48 __le64 mem_addr;
49 __le64 mem_size;
50};
51
52#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
53#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
54#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
55#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
56
57#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
58#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
59#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
60#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
61
62struct qcom_scm_wb_entry {
63 int flag;
64 void *entry;
65};
66
67static struct qcom_scm_wb_entry qcom_scm_wb[] = {
68 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
69 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
70 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
71 { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
72};
73
74static const char *qcom_scm_convention_names[] = {
75 [SMC_CONVENTION_UNKNOWN] = "unknown",
76 [SMC_CONVENTION_ARM_32] = "smc arm 32",
77 [SMC_CONVENTION_ARM_64] = "smc arm 64",
78 [SMC_CONVENTION_LEGACY] = "smc legacy",
79};
80
81static struct qcom_scm *__scm;
82
83static int qcom_scm_clk_enable(void)
84{
85 int ret;
86
87 ret = clk_prepare_enable(__scm->core_clk);
88 if (ret)
89 goto bail;
90
91 ret = clk_prepare_enable(__scm->iface_clk);
92 if (ret)
93 goto disable_core;
94
95 ret = clk_prepare_enable(__scm->bus_clk);
96 if (ret)
97 goto disable_iface;
98
99 return 0;
100
101disable_iface:
102 clk_disable_unprepare(__scm->iface_clk);
103disable_core:
104 clk_disable_unprepare(__scm->core_clk);
105bail:
106 return ret;
107}
108
109static void qcom_scm_clk_disable(void)
110{
111 clk_disable_unprepare(__scm->core_clk);
112 clk_disable_unprepare(__scm->iface_clk);
113 clk_disable_unprepare(__scm->bus_clk);
114}
115
116static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
117 u32 cmd_id);
118
119enum qcom_scm_convention qcom_scm_convention;
120static bool has_queried __read_mostly;
121static DEFINE_SPINLOCK(query_lock);
122
123static void __query_convention(void)
124{
125 unsigned long flags;
126 struct qcom_scm_desc desc = {
127 .svc = QCOM_SCM_SVC_INFO,
128 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
129 .args[0] = SCM_SMC_FNID(QCOM_SCM_SVC_INFO,
130 QCOM_SCM_INFO_IS_CALL_AVAIL) |
131 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT),
132 .arginfo = QCOM_SCM_ARGS(1),
133 .owner = ARM_SMCCC_OWNER_SIP,
134 };
135 struct qcom_scm_res res;
136 int ret;
137
138 spin_lock_irqsave(&query_lock, flags);
139 if (has_queried)
140 goto out;
141
142 qcom_scm_convention = SMC_CONVENTION_ARM_64;
143 // Device isn't required as there is only one argument - no device
144 // needed to dma_map_single to secure world
145 ret = scm_smc_call(NULL, &desc, &res, true);
146 if (!ret && res.result[0] == 1)
147 goto out;
148
149 qcom_scm_convention = SMC_CONVENTION_ARM_32;
150 ret = scm_smc_call(NULL, &desc, &res, true);
151 if (!ret && res.result[0] == 1)
152 goto out;
153
154 qcom_scm_convention = SMC_CONVENTION_LEGACY;
155out:
156 has_queried = true;
157 spin_unlock_irqrestore(&query_lock, flags);
158 pr_info("qcom_scm: convention: %s\n",
159 qcom_scm_convention_names[qcom_scm_convention]);
160}
161
162static inline enum qcom_scm_convention __get_convention(void)
163{
164 if (unlikely(!has_queried))
165 __query_convention();
166 return qcom_scm_convention;
167}
168
169/**
170 * qcom_scm_call() - Invoke a syscall in the secure world
171 * @dev: device
172 * @svc_id: service identifier
173 * @cmd_id: command identifier
174 * @desc: Descriptor structure containing arguments and return values
175 *
176 * Sends a command to the SCM and waits for the command to finish processing.
177 * This should *only* be called in pre-emptible context.
178 */
179static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
180 struct qcom_scm_res *res)
181{
182 might_sleep();
183 switch (__get_convention()) {
184 case SMC_CONVENTION_ARM_32:
185 case SMC_CONVENTION_ARM_64:
186 return scm_smc_call(dev, desc, res, false);
187 case SMC_CONVENTION_LEGACY:
188 return scm_legacy_call(dev, desc, res);
189 default:
190 pr_err("Unknown current SCM calling convention.\n");
191 return -EINVAL;
192 }
193}
194
195/**
196 * qcom_scm_call_atomic() - atomic variation of qcom_scm_call()
197 * @dev: device
198 * @svc_id: service identifier
199 * @cmd_id: command identifier
200 * @desc: Descriptor structure containing arguments and return values
201 * @res: Structure containing results from SMC/HVC call
202 *
203 * Sends a command to the SCM and waits for the command to finish processing.
204 * This can be called in atomic context.
205 */
206static int qcom_scm_call_atomic(struct device *dev,
207 const struct qcom_scm_desc *desc,
208 struct qcom_scm_res *res)
209{
210 switch (__get_convention()) {
211 case SMC_CONVENTION_ARM_32:
212 case SMC_CONVENTION_ARM_64:
213 return scm_smc_call(dev, desc, res, true);
214 case SMC_CONVENTION_LEGACY:
215 return scm_legacy_call_atomic(dev, desc, res);
216 default:
217 pr_err("Unknown current SCM calling convention.\n");
218 return -EINVAL;
219 }
220}
221
222static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
223 u32 cmd_id)
224{
225 int ret;
226 struct qcom_scm_desc desc = {
227 .svc = QCOM_SCM_SVC_INFO,
228 .cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
229 .owner = ARM_SMCCC_OWNER_SIP,
230 };
231 struct qcom_scm_res res;
232
233 desc.arginfo = QCOM_SCM_ARGS(1);
234 switch (__get_convention()) {
235 case SMC_CONVENTION_ARM_32:
236 case SMC_CONVENTION_ARM_64:
237 desc.args[0] = SCM_SMC_FNID(svc_id, cmd_id) |
238 (ARM_SMCCC_OWNER_SIP << ARM_SMCCC_OWNER_SHIFT);
239 break;
240 case SMC_CONVENTION_LEGACY:
241 desc.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id);
242 break;
243 default:
244 pr_err("Unknown SMC convention being used\n");
245 return -EINVAL;
246 }
247
248 ret = qcom_scm_call(dev, &desc, &res);
249
250 return ret ? : res.result[0];
251}
252
253/**
254 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
255 * @entry: Entry point function for the cpus
256 * @cpus: The cpumask of cpus that will use the entry point
257 *
258 * Set the Linux entry point for the SCM to transfer control to when coming
259 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
260 */
261int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
262{
263 int ret;
264 int flags = 0;
265 int cpu;
266 struct qcom_scm_desc desc = {
267 .svc = QCOM_SCM_SVC_BOOT,
268 .cmd = QCOM_SCM_BOOT_SET_ADDR,
269 .arginfo = QCOM_SCM_ARGS(2),
270 };
271
272 /*
273 * Reassign only if we are switching from hotplug entry point
274 * to cpuidle entry point or vice versa.
275 */
276 for_each_cpu(cpu, cpus) {
277 if (entry == qcom_scm_wb[cpu].entry)
278 continue;
279 flags |= qcom_scm_wb[cpu].flag;
280 }
281
282 /* No change in entry function */
283 if (!flags)
284 return 0;
285
286 desc.args[0] = flags;
287 desc.args[1] = virt_to_phys(entry);
288
289 ret = qcom_scm_call(__scm->dev, &desc, NULL);
290 if (!ret) {
291 for_each_cpu(cpu, cpus)
292 qcom_scm_wb[cpu].entry = entry;
293 }
294
295 return ret;
296}
297EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
298
299/**
300 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
301 * @entry: Entry point function for the cpus
302 * @cpus: The cpumask of cpus that will use the entry point
303 *
304 * Set the cold boot address of the cpus. Any cpu outside the supported
305 * range would be removed from the cpu present mask.
306 */
307int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
308{
309 int flags = 0;
310 int cpu;
311 int scm_cb_flags[] = {
312 QCOM_SCM_FLAG_COLDBOOT_CPU0,
313 QCOM_SCM_FLAG_COLDBOOT_CPU1,
314 QCOM_SCM_FLAG_COLDBOOT_CPU2,
315 QCOM_SCM_FLAG_COLDBOOT_CPU3,
316 };
317 struct qcom_scm_desc desc = {
318 .svc = QCOM_SCM_SVC_BOOT,
319 .cmd = QCOM_SCM_BOOT_SET_ADDR,
320 .arginfo = QCOM_SCM_ARGS(2),
321 .owner = ARM_SMCCC_OWNER_SIP,
322 };
323
324 if (!cpus || (cpus && cpumask_empty(cpus)))
325 return -EINVAL;
326
327 for_each_cpu(cpu, cpus) {
328 if (cpu < ARRAY_SIZE(scm_cb_flags))
329 flags |= scm_cb_flags[cpu];
330 else
331 set_cpu_present(cpu, false);
332 }
333
334 desc.args[0] = flags;
335 desc.args[1] = virt_to_phys(entry);
336
337 return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
338}
339EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
340
341/**
342 * qcom_scm_cpu_power_down() - Power down the cpu
343 * @flags - Flags to flush cache
344 *
345 * This is an end point to power down cpu. If there was a pending interrupt,
346 * the control would return from this function, otherwise, the cpu jumps to the
347 * warm boot entry point set for this cpu upon reset.
348 */
349void qcom_scm_cpu_power_down(u32 flags)
350{
351 struct qcom_scm_desc desc = {
352 .svc = QCOM_SCM_SVC_BOOT,
353 .cmd = QCOM_SCM_BOOT_TERMINATE_PC,
354 .args[0] = flags & QCOM_SCM_FLUSH_FLAG_MASK,
355 .arginfo = QCOM_SCM_ARGS(1),
356 .owner = ARM_SMCCC_OWNER_SIP,
357 };
358
359 qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
360}
361EXPORT_SYMBOL(qcom_scm_cpu_power_down);
362
363int qcom_scm_set_remote_state(u32 state, u32 id)
364{
365 struct qcom_scm_desc desc = {
366 .svc = QCOM_SCM_SVC_BOOT,
367 .cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
368 .arginfo = QCOM_SCM_ARGS(2),
369 .args[0] = state,
370 .args[1] = id,
371 .owner = ARM_SMCCC_OWNER_SIP,
372 };
373 struct qcom_scm_res res;
374 int ret;
375
376 ret = qcom_scm_call(__scm->dev, &desc, &res);
377
378 return ret ? : res.result[0];
379}
380EXPORT_SYMBOL(qcom_scm_set_remote_state);
381
382static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
383{
384 struct qcom_scm_desc desc = {
385 .svc = QCOM_SCM_SVC_BOOT,
386 .cmd = QCOM_SCM_BOOT_SET_DLOAD_MODE,
387 .arginfo = QCOM_SCM_ARGS(2),
388 .args[0] = QCOM_SCM_BOOT_SET_DLOAD_MODE,
389 .owner = ARM_SMCCC_OWNER_SIP,
390 };
391
392 desc.args[1] = enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0;
393
394 return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
395}
396
397static void qcom_scm_set_download_mode(bool enable)
398{
399 bool avail;
400 int ret = 0;
401
402 avail = __qcom_scm_is_call_available(__scm->dev,
403 QCOM_SCM_SVC_BOOT,
404 QCOM_SCM_BOOT_SET_DLOAD_MODE);
405 if (avail) {
406 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
407 } else if (__scm->dload_mode_addr) {
408 ret = qcom_scm_io_writel(__scm->dload_mode_addr,
409 enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
410 } else {
411 dev_err(__scm->dev,
412 "No available mechanism for setting download mode\n");
413 }
414
415 if (ret)
416 dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
417}
418
419/**
420 * qcom_scm_pas_init_image() - Initialize peripheral authentication service
421 * state machine for a given peripheral, using the
422 * metadata
423 * @peripheral: peripheral id
424 * @metadata: pointer to memory containing ELF header, program header table
425 * and optional blob of data used for authenticating the metadata
426 * and the rest of the firmware
427 * @size: size of the metadata
428 *
429 * Returns 0 on success.
430 */
431int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
432{
433 dma_addr_t mdata_phys;
434 void *mdata_buf;
435 int ret;
436 struct qcom_scm_desc desc = {
437 .svc = QCOM_SCM_SVC_PIL,
438 .cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
439 .arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW),
440 .args[0] = peripheral,
441 .owner = ARM_SMCCC_OWNER_SIP,
442 };
443 struct qcom_scm_res res;
444
445 /*
446 * During the scm call memory protection will be enabled for the meta
447 * data blob, so make sure it's physically contiguous, 4K aligned and
448 * non-cachable to avoid XPU violations.
449 */
450 mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
451 GFP_KERNEL);
452 if (!mdata_buf) {
453 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
454 return -ENOMEM;
455 }
456 memcpy(mdata_buf, metadata, size);
457
458 ret = qcom_scm_clk_enable();
459 if (ret)
460 goto free_metadata;
461
462 desc.args[1] = mdata_phys;
463
464 ret = qcom_scm_call(__scm->dev, &desc, &res);
465
466 qcom_scm_clk_disable();
467
468free_metadata:
469 dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
470
471 return ret ? : res.result[0];
472}
473EXPORT_SYMBOL(qcom_scm_pas_init_image);
474
475/**
476 * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
477 * for firmware loading
478 * @peripheral: peripheral id
479 * @addr: start address of memory area to prepare
480 * @size: size of the memory area to prepare
481 *
482 * Returns 0 on success.
483 */
484int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
485{
486 int ret;
487 struct qcom_scm_desc desc = {
488 .svc = QCOM_SCM_SVC_PIL,
489 .cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
490 .arginfo = QCOM_SCM_ARGS(3),
491 .args[0] = peripheral,
492 .args[1] = addr,
493 .args[2] = size,
494 .owner = ARM_SMCCC_OWNER_SIP,
495 };
496 struct qcom_scm_res res;
497
498 ret = qcom_scm_clk_enable();
499 if (ret)
500 return ret;
501
502 ret = qcom_scm_call(__scm->dev, &desc, &res);
503 qcom_scm_clk_disable();
504
505 return ret ? : res.result[0];
506}
507EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
508
509/**
510 * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
511 * and reset the remote processor
512 * @peripheral: peripheral id
513 *
514 * Return 0 on success.
515 */
516int qcom_scm_pas_auth_and_reset(u32 peripheral)
517{
518 int ret;
519 struct qcom_scm_desc desc = {
520 .svc = QCOM_SCM_SVC_PIL,
521 .cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
522 .arginfo = QCOM_SCM_ARGS(1),
523 .args[0] = peripheral,
524 .owner = ARM_SMCCC_OWNER_SIP,
525 };
526 struct qcom_scm_res res;
527
528 ret = qcom_scm_clk_enable();
529 if (ret)
530 return ret;
531
532 ret = qcom_scm_call(__scm->dev, &desc, &res);
533 qcom_scm_clk_disable();
534
535 return ret ? : res.result[0];
536}
537EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
538
539/**
540 * qcom_scm_pas_shutdown() - Shut down the remote processor
541 * @peripheral: peripheral id
542 *
543 * Returns 0 on success.
544 */
545int qcom_scm_pas_shutdown(u32 peripheral)
546{
547 int ret;
548 struct qcom_scm_desc desc = {
549 .svc = QCOM_SCM_SVC_PIL,
550 .cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
551 .arginfo = QCOM_SCM_ARGS(1),
552 .args[0] = peripheral,
553 .owner = ARM_SMCCC_OWNER_SIP,
554 };
555 struct qcom_scm_res res;
556
557 ret = qcom_scm_clk_enable();
558 if (ret)
559 return ret;
560
561 ret = qcom_scm_call(__scm->dev, &desc, &res);
562
563 qcom_scm_clk_disable();
564
565 return ret ? : res.result[0];
566}
567EXPORT_SYMBOL(qcom_scm_pas_shutdown);
568
569/**
570 * qcom_scm_pas_supported() - Check if the peripheral authentication service is
571 * available for the given peripherial
572 * @peripheral: peripheral id
573 *
574 * Returns true if PAS is supported for this peripheral, otherwise false.
575 */
576bool qcom_scm_pas_supported(u32 peripheral)
577{
578 int ret;
579 struct qcom_scm_desc desc = {
580 .svc = QCOM_SCM_SVC_PIL,
581 .cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
582 .arginfo = QCOM_SCM_ARGS(1),
583 .args[0] = peripheral,
584 .owner = ARM_SMCCC_OWNER_SIP,
585 };
586 struct qcom_scm_res res;
587
588 ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
589 QCOM_SCM_PIL_PAS_IS_SUPPORTED);
590 if (ret <= 0)
591 return false;
592
593 ret = qcom_scm_call(__scm->dev, &desc, &res);
594
595 return ret ? false : !!res.result[0];
596}
597EXPORT_SYMBOL(qcom_scm_pas_supported);
598
599static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
600{
601 struct qcom_scm_desc desc = {
602 .svc = QCOM_SCM_SVC_PIL,
603 .cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
604 .arginfo = QCOM_SCM_ARGS(2),
605 .args[0] = reset,
606 .args[1] = 0,
607 .owner = ARM_SMCCC_OWNER_SIP,
608 };
609 struct qcom_scm_res res;
610 int ret;
611
612 ret = qcom_scm_call(__scm->dev, &desc, &res);
613
614 return ret ? : res.result[0];
615}
616
617static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
618 unsigned long idx)
619{
620 if (idx != 0)
621 return -EINVAL;
622
623 return __qcom_scm_pas_mss_reset(__scm->dev, 1);
624}
625
626static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
627 unsigned long idx)
628{
629 if (idx != 0)
630 return -EINVAL;
631
632 return __qcom_scm_pas_mss_reset(__scm->dev, 0);
633}
634
635static const struct reset_control_ops qcom_scm_pas_reset_ops = {
636 .assert = qcom_scm_pas_reset_assert,
637 .deassert = qcom_scm_pas_reset_deassert,
638};
639
640int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
641{
642 struct qcom_scm_desc desc = {
643 .svc = QCOM_SCM_SVC_IO,
644 .cmd = QCOM_SCM_IO_READ,
645 .arginfo = QCOM_SCM_ARGS(1),
646 .args[0] = addr,
647 .owner = ARM_SMCCC_OWNER_SIP,
648 };
649 struct qcom_scm_res res;
650 int ret;
651
652
653 ret = qcom_scm_call_atomic(__scm->dev, &desc, &res);
654 if (ret >= 0)
655 *val = res.result[0];
656
657 return ret < 0 ? ret : 0;
658}
659EXPORT_SYMBOL(qcom_scm_io_readl);
660
661int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
662{
663 struct qcom_scm_desc desc = {
664 .svc = QCOM_SCM_SVC_IO,
665 .cmd = QCOM_SCM_IO_WRITE,
666 .arginfo = QCOM_SCM_ARGS(2),
667 .args[0] = addr,
668 .args[1] = val,
669 .owner = ARM_SMCCC_OWNER_SIP,
670 };
671
672 return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
673}
674EXPORT_SYMBOL(qcom_scm_io_writel);
675
676/**
677 * qcom_scm_restore_sec_cfg_available() - Check if secure environment
678 * supports restore security config interface.
679 *
680 * Return true if restore-cfg interface is supported, false if not.
681 */
682bool qcom_scm_restore_sec_cfg_available(void)
683{
684 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
685 QCOM_SCM_MP_RESTORE_SEC_CFG);
686}
687EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
688
689int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
690{
691 struct qcom_scm_desc desc = {
692 .svc = QCOM_SCM_SVC_MP,
693 .cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
694 .arginfo = QCOM_SCM_ARGS(2),
695 .args[0] = device_id,
696 .args[1] = spare,
697 .owner = ARM_SMCCC_OWNER_SIP,
698 };
699 struct qcom_scm_res res;
700 int ret;
701
702 ret = qcom_scm_call(__scm->dev, &desc, &res);
703
704 return ret ? : res.result[0];
705}
706EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
707
708int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
709{
710 struct qcom_scm_desc desc = {
711 .svc = QCOM_SCM_SVC_MP,
712 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE,
713 .arginfo = QCOM_SCM_ARGS(1),
714 .args[0] = spare,
715 .owner = ARM_SMCCC_OWNER_SIP,
716 };
717 struct qcom_scm_res res;
718 int ret;
719
720 ret = qcom_scm_call(__scm->dev, &desc, &res);
721
722 if (size)
723 *size = res.result[0];
724
725 return ret ? : res.result[1];
726}
727EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
728
729int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
730{
731 struct qcom_scm_desc desc = {
732 .svc = QCOM_SCM_SVC_MP,
733 .cmd = QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT,
734 .arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
735 QCOM_SCM_VAL),
736 .args[0] = addr,
737 .args[1] = size,
738 .args[2] = spare,
739 .owner = ARM_SMCCC_OWNER_SIP,
740 };
741 int ret;
742
743 desc.args[0] = addr;
744 desc.args[1] = size;
745 desc.args[2] = spare;
746 desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL,
747 QCOM_SCM_VAL);
748
749 ret = qcom_scm_call(__scm->dev, &desc, NULL);
750
751 /* the pg table has been initialized already, ignore the error */
752 if (ret == -EPERM)
753 ret = 0;
754
755 return ret;
756}
757EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
758
759static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
760 size_t mem_sz, phys_addr_t src, size_t src_sz,
761 phys_addr_t dest, size_t dest_sz)
762{
763 int ret;
764 struct qcom_scm_desc desc = {
765 .svc = QCOM_SCM_SVC_MP,
766 .cmd = QCOM_SCM_MP_ASSIGN,
767 .arginfo = QCOM_SCM_ARGS(7, QCOM_SCM_RO, QCOM_SCM_VAL,
768 QCOM_SCM_RO, QCOM_SCM_VAL, QCOM_SCM_RO,
769 QCOM_SCM_VAL, QCOM_SCM_VAL),
770 .args[0] = mem_region,
771 .args[1] = mem_sz,
772 .args[2] = src,
773 .args[3] = src_sz,
774 .args[4] = dest,
775 .args[5] = dest_sz,
776 .args[6] = 0,
777 .owner = ARM_SMCCC_OWNER_SIP,
778 };
779 struct qcom_scm_res res;
780
781 ret = qcom_scm_call(dev, &desc, &res);
782
783 return ret ? : res.result[0];
784}
785
786/**
787 * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
788 * @mem_addr: mem region whose ownership need to be reassigned
789 * @mem_sz: size of the region.
790 * @srcvm: vmid for current set of owners, each set bit in
791 * flag indicate a unique owner
792 * @newvm: array having new owners and corresponding permission
793 * flags
794 * @dest_cnt: number of owners in next set.
795 *
796 * Return negative errno on failure or 0 on success with @srcvm updated.
797 */
798int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
799 unsigned int *srcvm,
800 const struct qcom_scm_vmperm *newvm,
801 unsigned int dest_cnt)
802{
803 struct qcom_scm_current_perm_info *destvm;
804 struct qcom_scm_mem_map_info *mem_to_map;
805 phys_addr_t mem_to_map_phys;
806 phys_addr_t dest_phys;
807 dma_addr_t ptr_phys;
808 size_t mem_to_map_sz;
809 size_t dest_sz;
810 size_t src_sz;
811 size_t ptr_sz;
812 int next_vm;
813 __le32 *src;
814 void *ptr;
815 int ret, i, b;
816 unsigned long srcvm_bits = *srcvm;
817
818 src_sz = hweight_long(srcvm_bits) * sizeof(*src);
819 mem_to_map_sz = sizeof(*mem_to_map);
820 dest_sz = dest_cnt * sizeof(*destvm);
821 ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
822 ALIGN(dest_sz, SZ_64);
823
824 ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
825 if (!ptr)
826 return -ENOMEM;
827
828 /* Fill source vmid detail */
829 src = ptr;
830 i = 0;
831 for_each_set_bit(b, &srcvm_bits, BITS_PER_LONG)
832 src[i++] = cpu_to_le32(b);
833
834 /* Fill details of mem buff to map */
835 mem_to_map = ptr + ALIGN(src_sz, SZ_64);
836 mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
837 mem_to_map->mem_addr = cpu_to_le64(mem_addr);
838 mem_to_map->mem_size = cpu_to_le64(mem_sz);
839
840 next_vm = 0;
841 /* Fill details of next vmid detail */
842 destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
843 dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
844 for (i = 0; i < dest_cnt; i++, destvm++, newvm++) {
845 destvm->vmid = cpu_to_le32(newvm->vmid);
846 destvm->perm = cpu_to_le32(newvm->perm);
847 destvm->ctx = 0;
848 destvm->ctx_size = 0;
849 next_vm |= BIT(newvm->vmid);
850 }
851
852 ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
853 ptr_phys, src_sz, dest_phys, dest_sz);
854 dma_free_coherent(__scm->dev, ptr_sz, ptr, ptr_phys);
855 if (ret) {
856 dev_err(__scm->dev,
857 "Assign memory protection call failed %d\n", ret);
858 return -EINVAL;
859 }
860
861 *srcvm = next_vm;
862 return 0;
863}
864EXPORT_SYMBOL(qcom_scm_assign_mem);
865
866/**
867 * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
868 */
869bool qcom_scm_ocmem_lock_available(void)
870{
871 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
872 QCOM_SCM_OCMEM_LOCK_CMD);
873}
874EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
875
876/**
877 * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
878 * region to the specified initiator
879 *
880 * @id: tz initiator id
881 * @offset: OCMEM offset
882 * @size: OCMEM size
883 * @mode: access mode (WIDE/NARROW)
884 */
885int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
886 u32 mode)
887{
888 struct qcom_scm_desc desc = {
889 .svc = QCOM_SCM_SVC_OCMEM,
890 .cmd = QCOM_SCM_OCMEM_LOCK_CMD,
891 .args[0] = id,
892 .args[1] = offset,
893 .args[2] = size,
894 .args[3] = mode,
895 .arginfo = QCOM_SCM_ARGS(4),
896 };
897
898 return qcom_scm_call(__scm->dev, &desc, NULL);
899}
900EXPORT_SYMBOL(qcom_scm_ocmem_lock);
901
902/**
903 * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
904 * region from the specified initiator
905 *
906 * @id: tz initiator id
907 * @offset: OCMEM offset
908 * @size: OCMEM size
909 */
910int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size)
911{
912 struct qcom_scm_desc desc = {
913 .svc = QCOM_SCM_SVC_OCMEM,
914 .cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
915 .args[0] = id,
916 .args[1] = offset,
917 .args[2] = size,
918 .arginfo = QCOM_SCM_ARGS(3),
919 };
920
921 return qcom_scm_call(__scm->dev, &desc, NULL);
922}
923EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
924
925/**
926 * qcom_scm_ice_available() - Is the ICE key programming interface available?
927 *
928 * Return: true iff the SCM calls wrapped by qcom_scm_ice_invalidate_key() and
929 * qcom_scm_ice_set_key() are available.
930 */
931bool qcom_scm_ice_available(void)
932{
933 return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
934 QCOM_SCM_ES_INVALIDATE_ICE_KEY) &&
935 __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
936 QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
937}
938EXPORT_SYMBOL(qcom_scm_ice_available);
939
940/**
941 * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
942 * @index: the keyslot to invalidate
943 *
944 * The UFSHCI standard defines a standard way to do this, but it doesn't work on
945 * these SoCs; only this SCM call does.
946 *
947 * Return: 0 on success; -errno on failure.
948 */
949int qcom_scm_ice_invalidate_key(u32 index)
950{
951 struct qcom_scm_desc desc = {
952 .svc = QCOM_SCM_SVC_ES,
953 .cmd = QCOM_SCM_ES_INVALIDATE_ICE_KEY,
954 .arginfo = QCOM_SCM_ARGS(1),
955 .args[0] = index,
956 .owner = ARM_SMCCC_OWNER_SIP,
957 };
958
959 return qcom_scm_call(__scm->dev, &desc, NULL);
960}
961EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
962
963/**
964 * qcom_scm_ice_set_key() - Set an inline encryption key
965 * @index: the keyslot into which to set the key
966 * @key: the key to program
967 * @key_size: the size of the key in bytes
968 * @cipher: the encryption algorithm the key is for
969 * @data_unit_size: the encryption data unit size, i.e. the size of each
970 * individual plaintext and ciphertext. Given in 512-byte
971 * units, e.g. 1 = 512 bytes, 8 = 4096 bytes, etc.
972 *
973 * Program a key into a keyslot of Qualcomm ICE (Inline Crypto Engine), where it
974 * can then be used to encrypt/decrypt UFS I/O requests inline.
975 *
976 * The UFSHCI standard defines a standard way to do this, but it doesn't work on
977 * these SoCs; only this SCM call does.
978 *
979 * Return: 0 on success; -errno on failure.
980 */
981int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
982 enum qcom_scm_ice_cipher cipher, u32 data_unit_size)
983{
984 struct qcom_scm_desc desc = {
985 .svc = QCOM_SCM_SVC_ES,
986 .cmd = QCOM_SCM_ES_CONFIG_SET_ICE_KEY,
987 .arginfo = QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RW,
988 QCOM_SCM_VAL, QCOM_SCM_VAL,
989 QCOM_SCM_VAL),
990 .args[0] = index,
991 .args[2] = key_size,
992 .args[3] = cipher,
993 .args[4] = data_unit_size,
994 .owner = ARM_SMCCC_OWNER_SIP,
995 };
996 void *keybuf;
997 dma_addr_t key_phys;
998 int ret;
999
1000 /*
1001 * 'key' may point to vmalloc()'ed memory, but we need to pass a
1002 * physical address that's been properly flushed. The sanctioned way to
1003 * do this is by using the DMA API. But as is best practice for crypto
1004 * keys, we also must wipe the key after use. This makes kmemdup() +
1005 * dma_map_single() not clearly correct, since the DMA API can use
1006 * bounce buffers. Instead, just use dma_alloc_coherent(). Programming
1007 * keys is normally rare and thus not performance-critical.
1008 */
1009
1010 keybuf = dma_alloc_coherent(__scm->dev, key_size, &key_phys,
1011 GFP_KERNEL);
1012 if (!keybuf)
1013 return -ENOMEM;
1014 memcpy(keybuf, key, key_size);
1015 desc.args[1] = key_phys;
1016
1017 ret = qcom_scm_call(__scm->dev, &desc, NULL);
1018
1019 memzero_explicit(keybuf, key_size);
1020
1021 dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
1022 return ret;
1023}
1024EXPORT_SYMBOL(qcom_scm_ice_set_key);
1025
1026/**
1027 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
1028 *
1029 * Return true if HDCP is supported, false if not.
1030 */
1031bool qcom_scm_hdcp_available(void)
1032{
1033 int ret = qcom_scm_clk_enable();
1034
1035 if (ret)
1036 return ret;
1037
1038 ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
1039 QCOM_SCM_HDCP_INVOKE);
1040
1041 qcom_scm_clk_disable();
1042
1043 return ret > 0;
1044}
1045EXPORT_SYMBOL(qcom_scm_hdcp_available);
1046
1047/**
1048 * qcom_scm_hdcp_req() - Send HDCP request.
1049 * @req: HDCP request array
1050 * @req_cnt: HDCP request array count
1051 * @resp: response buffer passed to SCM
1052 *
1053 * Write HDCP register(s) through SCM.
1054 */
1055int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
1056{
1057 int ret;
1058 struct qcom_scm_desc desc = {
1059 .svc = QCOM_SCM_SVC_HDCP,
1060 .cmd = QCOM_SCM_HDCP_INVOKE,
1061 .arginfo = QCOM_SCM_ARGS(10),
1062 .args = {
1063 req[0].addr,
1064 req[0].val,
1065 req[1].addr,
1066 req[1].val,
1067 req[2].addr,
1068 req[2].val,
1069 req[3].addr,
1070 req[3].val,
1071 req[4].addr,
1072 req[4].val
1073 },
1074 .owner = ARM_SMCCC_OWNER_SIP,
1075 };
1076 struct qcom_scm_res res;
1077
1078 if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
1079 return -ERANGE;
1080
1081 ret = qcom_scm_clk_enable();
1082 if (ret)
1083 return ret;
1084
1085 ret = qcom_scm_call(__scm->dev, &desc, &res);
1086 *resp = res.result[0];
1087
1088 qcom_scm_clk_disable();
1089
1090 return ret;
1091}
1092EXPORT_SYMBOL(qcom_scm_hdcp_req);
1093
1094int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
1095{
1096 struct qcom_scm_desc desc = {
1097 .svc = QCOM_SCM_SVC_SMMU_PROGRAM,
1098 .cmd = QCOM_SCM_SMMU_CONFIG_ERRATA1,
1099 .arginfo = QCOM_SCM_ARGS(2),
1100 .args[0] = QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL,
1101 .args[1] = en,
1102 .owner = ARM_SMCCC_OWNER_SIP,
1103 };
1104
1105
1106 return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
1107}
1108EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
1109
1110static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
1111{
1112 struct device_node *tcsr;
1113 struct device_node *np = dev->of_node;
1114 struct resource res;
1115 u32 offset;
1116 int ret;
1117
1118 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
1119 if (!tcsr)
1120 return 0;
1121
1122 ret = of_address_to_resource(tcsr, 0, &res);
1123 of_node_put(tcsr);
1124 if (ret)
1125 return ret;
1126
1127 ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
1128 if (ret < 0)
1129 return ret;
1130
1131 *addr = res.start + offset;
1132
1133 return 0;
1134}
1135
1136/**
1137 * qcom_scm_is_available() - Checks if SCM is available
1138 */
1139bool qcom_scm_is_available(void)
1140{
1141 return !!__scm;
1142}
1143EXPORT_SYMBOL(qcom_scm_is_available);
1144
1145static int qcom_scm_probe(struct platform_device *pdev)
1146{
1147 struct qcom_scm *scm;
1148 unsigned long clks;
1149 int ret;
1150
1151 scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
1152 if (!scm)
1153 return -ENOMEM;
1154
1155 ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
1156 if (ret < 0)
1157 return ret;
1158
1159 clks = (unsigned long)of_device_get_match_data(&pdev->dev);
1160
1161 scm->core_clk = devm_clk_get(&pdev->dev, "core");
1162 if (IS_ERR(scm->core_clk)) {
1163 if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
1164 return PTR_ERR(scm->core_clk);
1165
1166 if (clks & SCM_HAS_CORE_CLK) {
1167 dev_err(&pdev->dev, "failed to acquire core clk\n");
1168 return PTR_ERR(scm->core_clk);
1169 }
1170
1171 scm->core_clk = NULL;
1172 }
1173
1174 scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
1175 if (IS_ERR(scm->iface_clk)) {
1176 if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
1177 return PTR_ERR(scm->iface_clk);
1178
1179 if (clks & SCM_HAS_IFACE_CLK) {
1180 dev_err(&pdev->dev, "failed to acquire iface clk\n");
1181 return PTR_ERR(scm->iface_clk);
1182 }
1183
1184 scm->iface_clk = NULL;
1185 }
1186
1187 scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
1188 if (IS_ERR(scm->bus_clk)) {
1189 if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
1190 return PTR_ERR(scm->bus_clk);
1191
1192 if (clks & SCM_HAS_BUS_CLK) {
1193 dev_err(&pdev->dev, "failed to acquire bus clk\n");
1194 return PTR_ERR(scm->bus_clk);
1195 }
1196
1197 scm->bus_clk = NULL;
1198 }
1199
1200 scm->reset.ops = &qcom_scm_pas_reset_ops;
1201 scm->reset.nr_resets = 1;
1202 scm->reset.of_node = pdev->dev.of_node;
1203 ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
1204 if (ret)
1205 return ret;
1206
1207 /* vote for max clk rate for highest performance */
1208 ret = clk_set_rate(scm->core_clk, INT_MAX);
1209 if (ret)
1210 return ret;
1211
1212 __scm = scm;
1213 __scm->dev = &pdev->dev;
1214
1215 __query_convention();
1216
1217 /*
1218 * If requested enable "download mode", from this point on warmboot
1219 * will cause the the boot stages to enter download mode, unless
1220 * disabled below by a clean shutdown/reboot.
1221 */
1222 if (download_mode)
1223 qcom_scm_set_download_mode(true);
1224
1225 return 0;
1226}
1227
1228static void qcom_scm_shutdown(struct platform_device *pdev)
1229{
1230 /* Clean shutdown, disable download mode to allow normal restart */
1231 if (download_mode)
1232 qcom_scm_set_download_mode(false);
1233}
1234
1235static const struct of_device_id qcom_scm_dt_match[] = {
1236 { .compatible = "qcom,scm-apq8064",
1237 /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
1238 },
1239 { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
1240 SCM_HAS_IFACE_CLK |
1241 SCM_HAS_BUS_CLK)
1242 },
1243 { .compatible = "qcom,scm-ipq4019" },
1244 { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
1245 { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
1246 { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
1247 SCM_HAS_IFACE_CLK |
1248 SCM_HAS_BUS_CLK)
1249 },
1250 { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
1251 SCM_HAS_IFACE_CLK |
1252 SCM_HAS_BUS_CLK)
1253 },
1254 { .compatible = "qcom,scm-msm8994" },
1255 { .compatible = "qcom,scm-msm8996" },
1256 { .compatible = "qcom,scm" },
1257 {}
1258};
1259
1260static struct platform_driver qcom_scm_driver = {
1261 .driver = {
1262 .name = "qcom_scm",
1263 .of_match_table = qcom_scm_dt_match,
1264 },
1265 .probe = qcom_scm_probe,
1266 .shutdown = qcom_scm_shutdown,
1267};
1268
1269static int __init qcom_scm_init(void)
1270{
1271 return platform_driver_register(&qcom_scm_driver);
1272}
1273subsys_initcall(qcom_scm_init);
1/*
2 * Qualcomm SCM driver
3 *
4 * Copyright (c) 2010,2015, The Linux Foundation. All rights reserved.
5 * Copyright (C) 2015 Linaro Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 and
9 * only version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17#include <linux/platform_device.h>
18#include <linux/init.h>
19#include <linux/cpumask.h>
20#include <linux/export.h>
21#include <linux/dma-mapping.h>
22#include <linux/module.h>
23#include <linux/types.h>
24#include <linux/qcom_scm.h>
25#include <linux/of.h>
26#include <linux/of_address.h>
27#include <linux/of_platform.h>
28#include <linux/clk.h>
29#include <linux/reset-controller.h>
30
31#include "qcom_scm.h"
32
33static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
34module_param(download_mode, bool, 0);
35
36#define SCM_HAS_CORE_CLK BIT(0)
37#define SCM_HAS_IFACE_CLK BIT(1)
38#define SCM_HAS_BUS_CLK BIT(2)
39
40struct qcom_scm {
41 struct device *dev;
42 struct clk *core_clk;
43 struct clk *iface_clk;
44 struct clk *bus_clk;
45 struct reset_controller_dev reset;
46
47 u64 dload_mode_addr;
48};
49
50struct qcom_scm_current_perm_info {
51 __le32 vmid;
52 __le32 perm;
53 __le64 ctx;
54 __le32 ctx_size;
55 __le32 unused;
56};
57
58struct qcom_scm_mem_map_info {
59 __le64 mem_addr;
60 __le64 mem_size;
61};
62
63static struct qcom_scm *__scm;
64
65static int qcom_scm_clk_enable(void)
66{
67 int ret;
68
69 ret = clk_prepare_enable(__scm->core_clk);
70 if (ret)
71 goto bail;
72
73 ret = clk_prepare_enable(__scm->iface_clk);
74 if (ret)
75 goto disable_core;
76
77 ret = clk_prepare_enable(__scm->bus_clk);
78 if (ret)
79 goto disable_iface;
80
81 return 0;
82
83disable_iface:
84 clk_disable_unprepare(__scm->iface_clk);
85disable_core:
86 clk_disable_unprepare(__scm->core_clk);
87bail:
88 return ret;
89}
90
91static void qcom_scm_clk_disable(void)
92{
93 clk_disable_unprepare(__scm->core_clk);
94 clk_disable_unprepare(__scm->iface_clk);
95 clk_disable_unprepare(__scm->bus_clk);
96}
97
98/**
99 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
100 * @entry: Entry point function for the cpus
101 * @cpus: The cpumask of cpus that will use the entry point
102 *
103 * Set the cold boot address of the cpus. Any cpu outside the supported
104 * range would be removed from the cpu present mask.
105 */
106int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
107{
108 return __qcom_scm_set_cold_boot_addr(entry, cpus);
109}
110EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
111
112/**
113 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
114 * @entry: Entry point function for the cpus
115 * @cpus: The cpumask of cpus that will use the entry point
116 *
117 * Set the Linux entry point for the SCM to transfer control to when coming
118 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
119 */
120int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
121{
122 return __qcom_scm_set_warm_boot_addr(__scm->dev, entry, cpus);
123}
124EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
125
126/**
127 * qcom_scm_cpu_power_down() - Power down the cpu
128 * @flags - Flags to flush cache
129 *
130 * This is an end point to power down cpu. If there was a pending interrupt,
131 * the control would return from this function, otherwise, the cpu jumps to the
132 * warm boot entry point set for this cpu upon reset.
133 */
134void qcom_scm_cpu_power_down(u32 flags)
135{
136 __qcom_scm_cpu_power_down(flags);
137}
138EXPORT_SYMBOL(qcom_scm_cpu_power_down);
139
140/**
141 * qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
142 *
143 * Return true if HDCP is supported, false if not.
144 */
145bool qcom_scm_hdcp_available(void)
146{
147 int ret = qcom_scm_clk_enable();
148
149 if (ret)
150 return ret;
151
152 ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_HDCP,
153 QCOM_SCM_CMD_HDCP);
154
155 qcom_scm_clk_disable();
156
157 return ret > 0 ? true : false;
158}
159EXPORT_SYMBOL(qcom_scm_hdcp_available);
160
161/**
162 * qcom_scm_hdcp_req() - Send HDCP request.
163 * @req: HDCP request array
164 * @req_cnt: HDCP request array count
165 * @resp: response buffer passed to SCM
166 *
167 * Write HDCP register(s) through SCM.
168 */
169int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp)
170{
171 int ret = qcom_scm_clk_enable();
172
173 if (ret)
174 return ret;
175
176 ret = __qcom_scm_hdcp_req(__scm->dev, req, req_cnt, resp);
177 qcom_scm_clk_disable();
178 return ret;
179}
180EXPORT_SYMBOL(qcom_scm_hdcp_req);
181
182/**
183 * qcom_scm_pas_supported() - Check if the peripheral authentication service is
184 * available for the given peripherial
185 * @peripheral: peripheral id
186 *
187 * Returns true if PAS is supported for this peripheral, otherwise false.
188 */
189bool qcom_scm_pas_supported(u32 peripheral)
190{
191 int ret;
192
193 ret = __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL,
194 QCOM_SCM_PAS_IS_SUPPORTED_CMD);
195 if (ret <= 0)
196 return false;
197
198 return __qcom_scm_pas_supported(__scm->dev, peripheral);
199}
200EXPORT_SYMBOL(qcom_scm_pas_supported);
201
202/**
203 * qcom_scm_pas_init_image() - Initialize peripheral authentication service
204 * state machine for a given peripheral, using the
205 * metadata
206 * @peripheral: peripheral id
207 * @metadata: pointer to memory containing ELF header, program header table
208 * and optional blob of data used for authenticating the metadata
209 * and the rest of the firmware
210 * @size: size of the metadata
211 *
212 * Returns 0 on success.
213 */
214int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size)
215{
216 dma_addr_t mdata_phys;
217 void *mdata_buf;
218 int ret;
219
220 /*
221 * During the scm call memory protection will be enabled for the meta
222 * data blob, so make sure it's physically contiguous, 4K aligned and
223 * non-cachable to avoid XPU violations.
224 */
225 mdata_buf = dma_alloc_coherent(__scm->dev, size, &mdata_phys,
226 GFP_KERNEL);
227 if (!mdata_buf) {
228 dev_err(__scm->dev, "Allocation of metadata buffer failed.\n");
229 return -ENOMEM;
230 }
231 memcpy(mdata_buf, metadata, size);
232
233 ret = qcom_scm_clk_enable();
234 if (ret)
235 goto free_metadata;
236
237 ret = __qcom_scm_pas_init_image(__scm->dev, peripheral, mdata_phys);
238
239 qcom_scm_clk_disable();
240
241free_metadata:
242 dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys);
243
244 return ret;
245}
246EXPORT_SYMBOL(qcom_scm_pas_init_image);
247
248/**
249 * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
250 * for firmware loading
251 * @peripheral: peripheral id
252 * @addr: start address of memory area to prepare
253 * @size: size of the memory area to prepare
254 *
255 * Returns 0 on success.
256 */
257int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size)
258{
259 int ret;
260
261 ret = qcom_scm_clk_enable();
262 if (ret)
263 return ret;
264
265 ret = __qcom_scm_pas_mem_setup(__scm->dev, peripheral, addr, size);
266 qcom_scm_clk_disable();
267
268 return ret;
269}
270EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
271
272/**
273 * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
274 * and reset the remote processor
275 * @peripheral: peripheral id
276 *
277 * Return 0 on success.
278 */
279int qcom_scm_pas_auth_and_reset(u32 peripheral)
280{
281 int ret;
282
283 ret = qcom_scm_clk_enable();
284 if (ret)
285 return ret;
286
287 ret = __qcom_scm_pas_auth_and_reset(__scm->dev, peripheral);
288 qcom_scm_clk_disable();
289
290 return ret;
291}
292EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
293
294/**
295 * qcom_scm_pas_shutdown() - Shut down the remote processor
296 * @peripheral: peripheral id
297 *
298 * Returns 0 on success.
299 */
300int qcom_scm_pas_shutdown(u32 peripheral)
301{
302 int ret;
303
304 ret = qcom_scm_clk_enable();
305 if (ret)
306 return ret;
307
308 ret = __qcom_scm_pas_shutdown(__scm->dev, peripheral);
309 qcom_scm_clk_disable();
310
311 return ret;
312}
313EXPORT_SYMBOL(qcom_scm_pas_shutdown);
314
315static int qcom_scm_pas_reset_assert(struct reset_controller_dev *rcdev,
316 unsigned long idx)
317{
318 if (idx != 0)
319 return -EINVAL;
320
321 return __qcom_scm_pas_mss_reset(__scm->dev, 1);
322}
323
324static int qcom_scm_pas_reset_deassert(struct reset_controller_dev *rcdev,
325 unsigned long idx)
326{
327 if (idx != 0)
328 return -EINVAL;
329
330 return __qcom_scm_pas_mss_reset(__scm->dev, 0);
331}
332
333static const struct reset_control_ops qcom_scm_pas_reset_ops = {
334 .assert = qcom_scm_pas_reset_assert,
335 .deassert = qcom_scm_pas_reset_deassert,
336};
337
338int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
339{
340 return __qcom_scm_restore_sec_cfg(__scm->dev, device_id, spare);
341}
342EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
343
344int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
345{
346 return __qcom_scm_iommu_secure_ptbl_size(__scm->dev, spare, size);
347}
348EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
349
350int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
351{
352 return __qcom_scm_iommu_secure_ptbl_init(__scm->dev, addr, size, spare);
353}
354EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
355
356int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val)
357{
358 return __qcom_scm_io_readl(__scm->dev, addr, val);
359}
360EXPORT_SYMBOL(qcom_scm_io_readl);
361
362int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
363{
364 return __qcom_scm_io_writel(__scm->dev, addr, val);
365}
366EXPORT_SYMBOL(qcom_scm_io_writel);
367
368static void qcom_scm_set_download_mode(bool enable)
369{
370 bool avail;
371 int ret = 0;
372
373 avail = __qcom_scm_is_call_available(__scm->dev,
374 QCOM_SCM_SVC_BOOT,
375 QCOM_SCM_SET_DLOAD_MODE);
376 if (avail) {
377 ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
378 } else if (__scm->dload_mode_addr) {
379 ret = __qcom_scm_io_writel(__scm->dev, __scm->dload_mode_addr,
380 enable ? QCOM_SCM_SET_DLOAD_MODE : 0);
381 } else {
382 dev_err(__scm->dev,
383 "No available mechanism for setting download mode\n");
384 }
385
386 if (ret)
387 dev_err(__scm->dev, "failed to set download mode: %d\n", ret);
388}
389
390static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
391{
392 struct device_node *tcsr;
393 struct device_node *np = dev->of_node;
394 struct resource res;
395 u32 offset;
396 int ret;
397
398 tcsr = of_parse_phandle(np, "qcom,dload-mode", 0);
399 if (!tcsr)
400 return 0;
401
402 ret = of_address_to_resource(tcsr, 0, &res);
403 of_node_put(tcsr);
404 if (ret)
405 return ret;
406
407 ret = of_property_read_u32_index(np, "qcom,dload-mode", 1, &offset);
408 if (ret < 0)
409 return ret;
410
411 *addr = res.start + offset;
412
413 return 0;
414}
415
416/**
417 * qcom_scm_is_available() - Checks if SCM is available
418 */
419bool qcom_scm_is_available(void)
420{
421 return !!__scm;
422}
423EXPORT_SYMBOL(qcom_scm_is_available);
424
425int qcom_scm_set_remote_state(u32 state, u32 id)
426{
427 return __qcom_scm_set_remote_state(__scm->dev, state, id);
428}
429EXPORT_SYMBOL(qcom_scm_set_remote_state);
430
431/**
432 * qcom_scm_assign_mem() - Make a secure call to reassign memory ownership
433 * @mem_addr: mem region whose ownership need to be reassigned
434 * @mem_sz: size of the region.
435 * @srcvm: vmid for current set of owners, each set bit in
436 * flag indicate a unique owner
437 * @newvm: array having new owners and corrsponding permission
438 * flags
439 * @dest_cnt: number of owners in next set.
440 *
441 * Return negative errno on failure, 0 on success, with @srcvm updated.
442 */
443int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
444 unsigned int *srcvm,
445 struct qcom_scm_vmperm *newvm, int dest_cnt)
446{
447 struct qcom_scm_current_perm_info *destvm;
448 struct qcom_scm_mem_map_info *mem_to_map;
449 phys_addr_t mem_to_map_phys;
450 phys_addr_t dest_phys;
451 phys_addr_t ptr_phys;
452 size_t mem_to_map_sz;
453 size_t dest_sz;
454 size_t src_sz;
455 size_t ptr_sz;
456 int next_vm;
457 __le32 *src;
458 void *ptr;
459 int ret;
460 int len;
461 int i;
462
463 src_sz = hweight_long(*srcvm) * sizeof(*src);
464 mem_to_map_sz = sizeof(*mem_to_map);
465 dest_sz = dest_cnt * sizeof(*destvm);
466 ptr_sz = ALIGN(src_sz, SZ_64) + ALIGN(mem_to_map_sz, SZ_64) +
467 ALIGN(dest_sz, SZ_64);
468
469 ptr = dma_alloc_coherent(__scm->dev, ptr_sz, &ptr_phys, GFP_KERNEL);
470 if (!ptr)
471 return -ENOMEM;
472
473 /* Fill source vmid detail */
474 src = ptr;
475 len = hweight_long(*srcvm);
476 for (i = 0; i < len; i++) {
477 src[i] = cpu_to_le32(ffs(*srcvm) - 1);
478 *srcvm ^= 1 << (ffs(*srcvm) - 1);
479 }
480
481 /* Fill details of mem buff to map */
482 mem_to_map = ptr + ALIGN(src_sz, SZ_64);
483 mem_to_map_phys = ptr_phys + ALIGN(src_sz, SZ_64);
484 mem_to_map[0].mem_addr = cpu_to_le64(mem_addr);
485 mem_to_map[0].mem_size = cpu_to_le64(mem_sz);
486
487 next_vm = 0;
488 /* Fill details of next vmid detail */
489 destvm = ptr + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
490 dest_phys = ptr_phys + ALIGN(mem_to_map_sz, SZ_64) + ALIGN(src_sz, SZ_64);
491 for (i = 0; i < dest_cnt; i++) {
492 destvm[i].vmid = cpu_to_le32(newvm[i].vmid);
493 destvm[i].perm = cpu_to_le32(newvm[i].perm);
494 destvm[i].ctx = 0;
495 destvm[i].ctx_size = 0;
496 next_vm |= BIT(newvm[i].vmid);
497 }
498
499 ret = __qcom_scm_assign_mem(__scm->dev, mem_to_map_phys, mem_to_map_sz,
500 ptr_phys, src_sz, dest_phys, dest_sz);
501 dma_free_coherent(__scm->dev, ALIGN(ptr_sz, SZ_64), ptr, ptr_phys);
502 if (ret) {
503 dev_err(__scm->dev,
504 "Assign memory protection call failed %d.\n", ret);
505 return -EINVAL;
506 }
507
508 *srcvm = next_vm;
509 return 0;
510}
511EXPORT_SYMBOL(qcom_scm_assign_mem);
512
513static int qcom_scm_probe(struct platform_device *pdev)
514{
515 struct qcom_scm *scm;
516 unsigned long clks;
517 int ret;
518
519 scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
520 if (!scm)
521 return -ENOMEM;
522
523 ret = qcom_scm_find_dload_address(&pdev->dev, &scm->dload_mode_addr);
524 if (ret < 0)
525 return ret;
526
527 clks = (unsigned long)of_device_get_match_data(&pdev->dev);
528 if (clks & SCM_HAS_CORE_CLK) {
529 scm->core_clk = devm_clk_get(&pdev->dev, "core");
530 if (IS_ERR(scm->core_clk)) {
531 if (PTR_ERR(scm->core_clk) != -EPROBE_DEFER)
532 dev_err(&pdev->dev,
533 "failed to acquire core clk\n");
534 return PTR_ERR(scm->core_clk);
535 }
536 }
537
538 if (clks & SCM_HAS_IFACE_CLK) {
539 scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
540 if (IS_ERR(scm->iface_clk)) {
541 if (PTR_ERR(scm->iface_clk) != -EPROBE_DEFER)
542 dev_err(&pdev->dev,
543 "failed to acquire iface clk\n");
544 return PTR_ERR(scm->iface_clk);
545 }
546 }
547
548 if (clks & SCM_HAS_BUS_CLK) {
549 scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
550 if (IS_ERR(scm->bus_clk)) {
551 if (PTR_ERR(scm->bus_clk) != -EPROBE_DEFER)
552 dev_err(&pdev->dev,
553 "failed to acquire bus clk\n");
554 return PTR_ERR(scm->bus_clk);
555 }
556 }
557
558 scm->reset.ops = &qcom_scm_pas_reset_ops;
559 scm->reset.nr_resets = 1;
560 scm->reset.of_node = pdev->dev.of_node;
561 ret = devm_reset_controller_register(&pdev->dev, &scm->reset);
562 if (ret)
563 return ret;
564
565 /* vote for max clk rate for highest performance */
566 ret = clk_set_rate(scm->core_clk, INT_MAX);
567 if (ret)
568 return ret;
569
570 __scm = scm;
571 __scm->dev = &pdev->dev;
572
573 __qcom_scm_init();
574
575 /*
576 * If requested enable "download mode", from this point on warmboot
577 * will cause the the boot stages to enter download mode, unless
578 * disabled below by a clean shutdown/reboot.
579 */
580 if (download_mode)
581 qcom_scm_set_download_mode(true);
582
583 return 0;
584}
585
586static void qcom_scm_shutdown(struct platform_device *pdev)
587{
588 /* Clean shutdown, disable download mode to allow normal restart */
589 if (download_mode)
590 qcom_scm_set_download_mode(false);
591}
592
593static const struct of_device_id qcom_scm_dt_match[] = {
594 { .compatible = "qcom,scm-apq8064",
595 /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
596 },
597 { .compatible = "qcom,scm-msm8660",
598 .data = (void *) SCM_HAS_CORE_CLK,
599 },
600 { .compatible = "qcom,scm-msm8960",
601 .data = (void *) SCM_HAS_CORE_CLK,
602 },
603 { .compatible = "qcom,scm-msm8996",
604 .data = NULL, /* no clocks */
605 },
606 { .compatible = "qcom,scm",
607 .data = (void *)(SCM_HAS_CORE_CLK
608 | SCM_HAS_IFACE_CLK
609 | SCM_HAS_BUS_CLK),
610 },
611 {}
612};
613
614static struct platform_driver qcom_scm_driver = {
615 .driver = {
616 .name = "qcom_scm",
617 .of_match_table = qcom_scm_dt_match,
618 },
619 .probe = qcom_scm_probe,
620 .shutdown = qcom_scm_shutdown,
621};
622
623static int __init qcom_scm_init(void)
624{
625 return platform_driver_register(&qcom_scm_driver);
626}
627subsys_initcall(qcom_scm_init);