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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8
9#include <drm/drm_atomic_helper.h>
10#include <drm/drm_panel.h>
11#include <drm/drm_simple_kms_helper.h>
12
13#include "drm.h"
14#include "dc.h"
15
16struct tegra_rgb {
17 struct tegra_output output;
18 struct tegra_dc *dc;
19
20 struct clk *clk_parent;
21 struct clk *clk;
22};
23
24static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
25{
26 return container_of(output, struct tegra_rgb, output);
27}
28
29struct reg_entry {
30 unsigned long offset;
31 unsigned long value;
32};
33
34static const struct reg_entry rgb_enable[] = {
35 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
36 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
37 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
43 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
52 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
53 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
54};
55
56static const struct reg_entry rgb_disable[] = {
57 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
58 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
59 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
65 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
66 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
69 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
70 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
73 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
74 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
75 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
76};
77
78static void tegra_dc_write_regs(struct tegra_dc *dc,
79 const struct reg_entry *table,
80 unsigned int num)
81{
82 unsigned int i;
83
84 for (i = 0; i < num; i++)
85 tegra_dc_writel(dc, table[i].value, table[i].offset);
86}
87
88static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
89 .reset = drm_atomic_helper_connector_reset,
90 .detect = tegra_output_connector_detect,
91 .fill_modes = drm_helper_probe_single_connector_modes,
92 .destroy = tegra_output_connector_destroy,
93 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
94 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
95};
96
97static enum drm_mode_status
98tegra_rgb_connector_mode_valid(struct drm_connector *connector,
99 struct drm_display_mode *mode)
100{
101 /*
102 * FIXME: For now, always assume that the mode is okay. There are
103 * unresolved issues with clk_round_rate(), which doesn't always
104 * reliably report whether a frequency can be set or not.
105 */
106 return MODE_OK;
107}
108
109static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
110 .get_modes = tegra_output_connector_get_modes,
111 .mode_valid = tegra_rgb_connector_mode_valid,
112};
113
114static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
115{
116 struct tegra_output *output = encoder_to_output(encoder);
117 struct tegra_rgb *rgb = to_rgb(output);
118
119 if (output->panel)
120 drm_panel_disable(output->panel);
121
122 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
123 tegra_dc_commit(rgb->dc);
124
125 if (output->panel)
126 drm_panel_unprepare(output->panel);
127}
128
129static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
130{
131 struct tegra_output *output = encoder_to_output(encoder);
132 struct tegra_rgb *rgb = to_rgb(output);
133 u32 value;
134
135 if (output->panel)
136 drm_panel_prepare(output->panel);
137
138 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
139
140 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
141 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
142
143 /* XXX: parameterize? */
144 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
145 value &= ~LVS_OUTPUT_POLARITY_LOW;
146 value &= ~LHS_OUTPUT_POLARITY_LOW;
147 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
148
149 /* XXX: parameterize? */
150 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
151 DISP_ORDER_RED_BLUE;
152 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
153
154 /* XXX: parameterize? */
155 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
156 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
157
158 tegra_dc_commit(rgb->dc);
159
160 if (output->panel)
161 drm_panel_enable(output->panel);
162}
163
164static int
165tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
166 struct drm_crtc_state *crtc_state,
167 struct drm_connector_state *conn_state)
168{
169 struct tegra_output *output = encoder_to_output(encoder);
170 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
171 unsigned long pclk = crtc_state->mode.clock * 1000;
172 struct tegra_rgb *rgb = to_rgb(output);
173 unsigned int div;
174 int err;
175
176 /*
177 * We may not want to change the frequency of the parent clock, since
178 * it may be a parent for other peripherals. This is due to the fact
179 * that on Tegra20 there's only a single clock dedicated to display
180 * (pll_d_out0), whereas later generations have a second one that can
181 * be used to independently drive a second output (pll_d2_out0).
182 *
183 * As a way to support multiple outputs on Tegra20 as well, pll_p is
184 * typically used as the parent clock for the display controllers.
185 * But this comes at a cost: pll_p is the parent of several other
186 * peripherals, so its frequency shouldn't change out of the blue.
187 *
188 * The best we can do at this point is to use the shift clock divider
189 * and hope that the desired frequency can be matched (or at least
190 * matched sufficiently close that the panel will still work).
191 */
192 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
193 pclk = 0;
194
195 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
196 pclk, div);
197 if (err < 0) {
198 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
199 return err;
200 }
201
202 return err;
203}
204
205static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
206 .disable = tegra_rgb_encoder_disable,
207 .enable = tegra_rgb_encoder_enable,
208 .atomic_check = tegra_rgb_encoder_atomic_check,
209};
210
211int tegra_dc_rgb_probe(struct tegra_dc *dc)
212{
213 struct device_node *np;
214 struct tegra_rgb *rgb;
215 int err;
216
217 np = of_get_child_by_name(dc->dev->of_node, "rgb");
218 if (!np || !of_device_is_available(np))
219 return -ENODEV;
220
221 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
222 if (!rgb)
223 return -ENOMEM;
224
225 rgb->output.dev = dc->dev;
226 rgb->output.of_node = np;
227 rgb->dc = dc;
228
229 err = tegra_output_probe(&rgb->output);
230 if (err < 0)
231 return err;
232
233 rgb->clk = devm_clk_get(dc->dev, NULL);
234 if (IS_ERR(rgb->clk)) {
235 dev_err(dc->dev, "failed to get clock\n");
236 return PTR_ERR(rgb->clk);
237 }
238
239 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
240 if (IS_ERR(rgb->clk_parent)) {
241 dev_err(dc->dev, "failed to get parent clock\n");
242 return PTR_ERR(rgb->clk_parent);
243 }
244
245 err = clk_set_parent(rgb->clk, rgb->clk_parent);
246 if (err < 0) {
247 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
248 return err;
249 }
250
251 dc->rgb = &rgb->output;
252
253 return 0;
254}
255
256int tegra_dc_rgb_remove(struct tegra_dc *dc)
257{
258 if (!dc->rgb)
259 return 0;
260
261 tegra_output_remove(dc->rgb);
262 dc->rgb = NULL;
263
264 return 0;
265}
266
267int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
268{
269 struct tegra_output *output = dc->rgb;
270 int err;
271
272 if (!dc->rgb)
273 return -ENODEV;
274
275 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
276 DRM_MODE_CONNECTOR_LVDS);
277 drm_connector_helper_add(&output->connector,
278 &tegra_rgb_connector_helper_funcs);
279 output->connector.dpms = DRM_MODE_DPMS_OFF;
280
281 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS);
282 drm_encoder_helper_add(&output->encoder,
283 &tegra_rgb_encoder_helper_funcs);
284
285 drm_connector_attach_encoder(&output->connector,
286 &output->encoder);
287 drm_connector_register(&output->connector);
288
289 err = tegra_output_init(drm, output);
290 if (err < 0) {
291 dev_err(output->dev, "failed to initialize output: %d\n", err);
292 return err;
293 }
294
295 /*
296 * Other outputs can be attached to either display controller. The RGB
297 * outputs are an exception and work only with their parent display
298 * controller.
299 */
300 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
301
302 return 0;
303}
304
305int tegra_dc_rgb_exit(struct tegra_dc *dc)
306{
307 if (dc->rgb)
308 tegra_output_exit(dc->rgb);
309
310 return 0;
311}
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11
12#include <drm/drm_atomic_helper.h>
13#include <drm/drm_panel.h>
14
15#include "drm.h"
16#include "dc.h"
17
18struct tegra_rgb {
19 struct tegra_output output;
20 struct tegra_dc *dc;
21
22 struct clk *clk_parent;
23 struct clk *clk;
24};
25
26static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
27{
28 return container_of(output, struct tegra_rgb, output);
29}
30
31struct reg_entry {
32 unsigned long offset;
33 unsigned long value;
34};
35
36static const struct reg_entry rgb_enable[] = {
37 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
43 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
52 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
53 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
54 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
55 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
56};
57
58static const struct reg_entry rgb_disable[] = {
59 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
65 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
66 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
69 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
70 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
73 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
74 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
75 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
76 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
77 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
78};
79
80static void tegra_dc_write_regs(struct tegra_dc *dc,
81 const struct reg_entry *table,
82 unsigned int num)
83{
84 unsigned int i;
85
86 for (i = 0; i < num; i++)
87 tegra_dc_writel(dc, table[i].value, table[i].offset);
88}
89
90static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
91 .dpms = drm_atomic_helper_connector_dpms,
92 .reset = drm_atomic_helper_connector_reset,
93 .detect = tegra_output_connector_detect,
94 .fill_modes = drm_helper_probe_single_connector_modes,
95 .destroy = tegra_output_connector_destroy,
96 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
97 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98};
99
100static enum drm_mode_status
101tegra_rgb_connector_mode_valid(struct drm_connector *connector,
102 struct drm_display_mode *mode)
103{
104 /*
105 * FIXME: For now, always assume that the mode is okay. There are
106 * unresolved issues with clk_round_rate(), which doesn't always
107 * reliably report whether a frequency can be set or not.
108 */
109 return MODE_OK;
110}
111
112static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
113 .get_modes = tegra_output_connector_get_modes,
114 .mode_valid = tegra_rgb_connector_mode_valid,
115};
116
117static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
118 .destroy = tegra_output_encoder_destroy,
119};
120
121static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
122{
123 struct tegra_output *output = encoder_to_output(encoder);
124 struct tegra_rgb *rgb = to_rgb(output);
125
126 if (output->panel)
127 drm_panel_disable(output->panel);
128
129 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
130 tegra_dc_commit(rgb->dc);
131
132 if (output->panel)
133 drm_panel_unprepare(output->panel);
134}
135
136static void tegra_rgb_encoder_enable(struct drm_encoder *encoder)
137{
138 struct tegra_output *output = encoder_to_output(encoder);
139 struct tegra_rgb *rgb = to_rgb(output);
140 u32 value;
141
142 if (output->panel)
143 drm_panel_prepare(output->panel);
144
145 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
146
147 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
148 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
149
150 /* XXX: parameterize? */
151 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
152 value &= ~LVS_OUTPUT_POLARITY_LOW;
153 value &= ~LHS_OUTPUT_POLARITY_LOW;
154 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
155
156 /* XXX: parameterize? */
157 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
158 DISP_ORDER_RED_BLUE;
159 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
160
161 /* XXX: parameterize? */
162 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
163 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
164
165 tegra_dc_commit(rgb->dc);
166
167 if (output->panel)
168 drm_panel_enable(output->panel);
169}
170
171static int
172tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder,
173 struct drm_crtc_state *crtc_state,
174 struct drm_connector_state *conn_state)
175{
176 struct tegra_output *output = encoder_to_output(encoder);
177 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
178 unsigned long pclk = crtc_state->mode.clock * 1000;
179 struct tegra_rgb *rgb = to_rgb(output);
180 unsigned int div;
181 int err;
182
183 /*
184 * We may not want to change the frequency of the parent clock, since
185 * it may be a parent for other peripherals. This is due to the fact
186 * that on Tegra20 there's only a single clock dedicated to display
187 * (pll_d_out0), whereas later generations have a second one that can
188 * be used to independently drive a second output (pll_d2_out0).
189 *
190 * As a way to support multiple outputs on Tegra20 as well, pll_p is
191 * typically used as the parent clock for the display controllers.
192 * But this comes at a cost: pll_p is the parent of several other
193 * peripherals, so its frequency shouldn't change out of the blue.
194 *
195 * The best we can do at this point is to use the shift clock divider
196 * and hope that the desired frequency can be matched (or at least
197 * matched sufficiently close that the panel will still work).
198 */
199 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
200 pclk = 0;
201
202 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent,
203 pclk, div);
204 if (err < 0) {
205 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
206 return err;
207 }
208
209 return err;
210}
211
212static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
213 .disable = tegra_rgb_encoder_disable,
214 .enable = tegra_rgb_encoder_enable,
215 .atomic_check = tegra_rgb_encoder_atomic_check,
216};
217
218int tegra_dc_rgb_probe(struct tegra_dc *dc)
219{
220 struct device_node *np;
221 struct tegra_rgb *rgb;
222 int err;
223
224 np = of_get_child_by_name(dc->dev->of_node, "rgb");
225 if (!np || !of_device_is_available(np))
226 return -ENODEV;
227
228 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
229 if (!rgb)
230 return -ENOMEM;
231
232 rgb->output.dev = dc->dev;
233 rgb->output.of_node = np;
234 rgb->dc = dc;
235
236 err = tegra_output_probe(&rgb->output);
237 if (err < 0)
238 return err;
239
240 rgb->clk = devm_clk_get(dc->dev, NULL);
241 if (IS_ERR(rgb->clk)) {
242 dev_err(dc->dev, "failed to get clock\n");
243 return PTR_ERR(rgb->clk);
244 }
245
246 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
247 if (IS_ERR(rgb->clk_parent)) {
248 dev_err(dc->dev, "failed to get parent clock\n");
249 return PTR_ERR(rgb->clk_parent);
250 }
251
252 err = clk_set_parent(rgb->clk, rgb->clk_parent);
253 if (err < 0) {
254 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
255 return err;
256 }
257
258 dc->rgb = &rgb->output;
259
260 return 0;
261}
262
263int tegra_dc_rgb_remove(struct tegra_dc *dc)
264{
265 if (!dc->rgb)
266 return 0;
267
268 tegra_output_remove(dc->rgb);
269 dc->rgb = NULL;
270
271 return 0;
272}
273
274int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
275{
276 struct tegra_output *output = dc->rgb;
277 int err;
278
279 if (!dc->rgb)
280 return -ENODEV;
281
282 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
283 DRM_MODE_CONNECTOR_LVDS);
284 drm_connector_helper_add(&output->connector,
285 &tegra_rgb_connector_helper_funcs);
286 output->connector.dpms = DRM_MODE_DPMS_OFF;
287
288 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
289 DRM_MODE_ENCODER_LVDS, NULL);
290 drm_encoder_helper_add(&output->encoder,
291 &tegra_rgb_encoder_helper_funcs);
292
293 drm_mode_connector_attach_encoder(&output->connector,
294 &output->encoder);
295 drm_connector_register(&output->connector);
296
297 err = tegra_output_init(drm, output);
298 if (err < 0) {
299 dev_err(output->dev, "failed to initialize output: %d\n", err);
300 return err;
301 }
302
303 /*
304 * Other outputs can be attached to either display controller. The RGB
305 * outputs are an exception and work only with their parent display
306 * controller.
307 */
308 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
309
310 return 0;
311}
312
313int tegra_dc_rgb_exit(struct tegra_dc *dc)
314{
315 if (dc->rgb)
316 tegra_output_exit(dc->rgb);
317
318 return 0;
319}