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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * BCM2835 DMA engine support
4 *
5 * Author: Florian Meier <florian.meier@koalo.de>
6 * Copyright 2013
7 *
8 * Based on
9 * OMAP DMAengine support by Russell King
10 *
11 * BCM2708 DMA Driver
12 * Copyright (C) 2010 Broadcom
13 *
14 * Raspberry Pi PCM I2S ALSA Driver
15 * Copyright (c) by Phil Poole 2013
16 *
17 * MARVELL MMP Peripheral DMA Driver
18 * Copyright 2012 Marvell International Ltd.
19 */
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/dmapool.h>
23#include <linux/err.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/list.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/io.h>
31#include <linux/spinlock.h>
32#include <linux/of.h>
33#include <linux/of_dma.h>
34
35#include "virt-dma.h"
36
37#define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
38#define BCM2835_DMA_CHAN_NAME_SIZE 8
39
40/**
41 * struct bcm2835_dmadev - BCM2835 DMA controller
42 * @ddev: DMA device
43 * @base: base address of register map
44 * @dma_parms: DMA parameters (to convey 1 GByte max segment size to clients)
45 * @zero_page: bus address of zero page (to detect transactions copying from
46 * zero page and avoid accessing memory if so)
47 */
48struct bcm2835_dmadev {
49 struct dma_device ddev;
50 void __iomem *base;
51 struct device_dma_parameters dma_parms;
52 dma_addr_t zero_page;
53};
54
55struct bcm2835_dma_cb {
56 uint32_t info;
57 uint32_t src;
58 uint32_t dst;
59 uint32_t length;
60 uint32_t stride;
61 uint32_t next;
62 uint32_t pad[2];
63};
64
65struct bcm2835_cb_entry {
66 struct bcm2835_dma_cb *cb;
67 dma_addr_t paddr;
68};
69
70struct bcm2835_chan {
71 struct virt_dma_chan vc;
72
73 struct dma_slave_config cfg;
74 unsigned int dreq;
75
76 int ch;
77 struct bcm2835_desc *desc;
78 struct dma_pool *cb_pool;
79
80 void __iomem *chan_base;
81 int irq_number;
82 unsigned int irq_flags;
83
84 bool is_lite_channel;
85};
86
87struct bcm2835_desc {
88 struct bcm2835_chan *c;
89 struct virt_dma_desc vd;
90 enum dma_transfer_direction dir;
91
92 unsigned int frames;
93 size_t size;
94
95 bool cyclic;
96
97 struct bcm2835_cb_entry cb_list[];
98};
99
100#define BCM2835_DMA_CS 0x00
101#define BCM2835_DMA_ADDR 0x04
102#define BCM2835_DMA_TI 0x08
103#define BCM2835_DMA_SOURCE_AD 0x0c
104#define BCM2835_DMA_DEST_AD 0x10
105#define BCM2835_DMA_LEN 0x14
106#define BCM2835_DMA_STRIDE 0x18
107#define BCM2835_DMA_NEXTCB 0x1c
108#define BCM2835_DMA_DEBUG 0x20
109
110/* DMA CS Control and Status bits */
111#define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */
112#define BCM2835_DMA_END BIT(1) /* current CB has ended */
113#define BCM2835_DMA_INT BIT(2) /* interrupt status */
114#define BCM2835_DMA_DREQ BIT(3) /* DREQ state */
115#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
116#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
117#define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
118 * AXI-write to ack
119 */
120#define BCM2835_DMA_ERR BIT(8)
121#define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
122#define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
123/* current value of TI.BCM2835_DMA_WAIT_RESP */
124#define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
125#define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */
126#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
127#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
128
129/* Transfer information bits - also bcm2835_cb.info field */
130#define BCM2835_DMA_INT_EN BIT(0)
131#define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */
132#define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */
133#define BCM2835_DMA_D_INC BIT(4)
134#define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */
135#define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */
136#define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */
137#define BCM2835_DMA_S_INC BIT(8)
138#define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */
139#define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */
140#define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */
141#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
142#define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
143#define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */
144#define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
145
146/* debug register bits */
147#define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0)
148#define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1)
149#define BCM2835_DMA_DEBUG_READ_ERR BIT(2)
150#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
151#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
152#define BCM2835_DMA_DEBUG_ID_SHIFT 16
153#define BCM2835_DMA_DEBUG_ID_BITS 9
154#define BCM2835_DMA_DEBUG_STATE_SHIFT 16
155#define BCM2835_DMA_DEBUG_STATE_BITS 9
156#define BCM2835_DMA_DEBUG_VERSION_SHIFT 25
157#define BCM2835_DMA_DEBUG_VERSION_BITS 3
158#define BCM2835_DMA_DEBUG_LITE BIT(28)
159
160/* shared registers for all dma channels */
161#define BCM2835_DMA_INT_STATUS 0xfe0
162#define BCM2835_DMA_ENABLE 0xff0
163
164#define BCM2835_DMA_DATA_TYPE_S8 1
165#define BCM2835_DMA_DATA_TYPE_S16 2
166#define BCM2835_DMA_DATA_TYPE_S32 4
167#define BCM2835_DMA_DATA_TYPE_S128 16
168
169/* Valid only for channels 0 - 14, 15 has its own base address */
170#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
171#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
172
173/* the max dma length for different channels */
174#define MAX_DMA_LEN SZ_1G
175#define MAX_LITE_DMA_LEN (SZ_64K - 4)
176
177static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
178{
179 /* lite and normal channels have different max frame length */
180 return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
181}
182
183/* how many frames of max_len size do we need to transfer len bytes */
184static inline size_t bcm2835_dma_frames_for_length(size_t len,
185 size_t max_len)
186{
187 return DIV_ROUND_UP(len, max_len);
188}
189
190static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
191{
192 return container_of(d, struct bcm2835_dmadev, ddev);
193}
194
195static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
196{
197 return container_of(c, struct bcm2835_chan, vc.chan);
198}
199
200static inline struct bcm2835_desc *to_bcm2835_dma_desc(
201 struct dma_async_tx_descriptor *t)
202{
203 return container_of(t, struct bcm2835_desc, vd.tx);
204}
205
206static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
207{
208 size_t i;
209
210 for (i = 0; i < desc->frames; i++)
211 dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
212 desc->cb_list[i].paddr);
213
214 kfree(desc);
215}
216
217static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
218{
219 bcm2835_dma_free_cb_chain(
220 container_of(vd, struct bcm2835_desc, vd));
221}
222
223static void bcm2835_dma_create_cb_set_length(
224 struct bcm2835_chan *chan,
225 struct bcm2835_dma_cb *control_block,
226 size_t len,
227 size_t period_len,
228 size_t *total_len,
229 u32 finalextrainfo)
230{
231 size_t max_len = bcm2835_dma_max_frame_length(chan);
232
233 /* set the length taking lite-channel limitations into account */
234 control_block->length = min_t(u32, len, max_len);
235
236 /* finished if we have no period_length */
237 if (!period_len)
238 return;
239
240 /*
241 * period_len means: that we need to generate
242 * transfers that are terminating at every
243 * multiple of period_len - this is typically
244 * used to set the interrupt flag in info
245 * which is required during cyclic transfers
246 */
247
248 /* have we filled in period_length yet? */
249 if (*total_len + control_block->length < period_len) {
250 /* update number of bytes in this period so far */
251 *total_len += control_block->length;
252 return;
253 }
254
255 /* calculate the length that remains to reach period_length */
256 control_block->length = period_len - *total_len;
257
258 /* reset total_length for next period */
259 *total_len = 0;
260
261 /* add extrainfo bits in info */
262 control_block->info |= finalextrainfo;
263}
264
265static inline size_t bcm2835_dma_count_frames_for_sg(
266 struct bcm2835_chan *c,
267 struct scatterlist *sgl,
268 unsigned int sg_len)
269{
270 size_t frames = 0;
271 struct scatterlist *sgent;
272 unsigned int i;
273 size_t plength = bcm2835_dma_max_frame_length(c);
274
275 for_each_sg(sgl, sgent, sg_len, i)
276 frames += bcm2835_dma_frames_for_length(
277 sg_dma_len(sgent), plength);
278
279 return frames;
280}
281
282/**
283 * bcm2835_dma_create_cb_chain - create a control block and fills data in
284 *
285 * @chan: the @dma_chan for which we run this
286 * @direction: the direction in which we transfer
287 * @cyclic: it is a cyclic transfer
288 * @info: the default info bits to apply per controlblock
289 * @frames: number of controlblocks to allocate
290 * @src: the src address to assign (if the S_INC bit is set
291 * in @info, then it gets incremented)
292 * @dst: the dst address to assign (if the D_INC bit is set
293 * in @info, then it gets incremented)
294 * @buf_len: the full buffer length (may also be 0)
295 * @period_len: the period length when to apply @finalextrainfo
296 * in addition to the last transfer
297 * this will also break some control-blocks early
298 * @finalextrainfo: additional bits in last controlblock
299 * (or when period_len is reached in case of cyclic)
300 * @gfp: the GFP flag to use for allocation
301 */
302static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
303 struct dma_chan *chan, enum dma_transfer_direction direction,
304 bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
305 dma_addr_t src, dma_addr_t dst, size_t buf_len,
306 size_t period_len, gfp_t gfp)
307{
308 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
309 size_t len = buf_len, total_len;
310 size_t frame;
311 struct bcm2835_desc *d;
312 struct bcm2835_cb_entry *cb_entry;
313 struct bcm2835_dma_cb *control_block;
314
315 if (!frames)
316 return NULL;
317
318 /* allocate and setup the descriptor. */
319 d = kzalloc(struct_size(d, cb_list, frames), gfp);
320 if (!d)
321 return NULL;
322
323 d->c = c;
324 d->dir = direction;
325 d->cyclic = cyclic;
326
327 /*
328 * Iterate over all frames, create a control block
329 * for each frame and link them together.
330 */
331 for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
332 cb_entry = &d->cb_list[frame];
333 cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
334 &cb_entry->paddr);
335 if (!cb_entry->cb)
336 goto error_cb;
337
338 /* fill in the control block */
339 control_block = cb_entry->cb;
340 control_block->info = info;
341 control_block->src = src;
342 control_block->dst = dst;
343 control_block->stride = 0;
344 control_block->next = 0;
345 /* set up length in control_block if requested */
346 if (buf_len) {
347 /* calculate length honoring period_length */
348 bcm2835_dma_create_cb_set_length(
349 c, control_block,
350 len, period_len, &total_len,
351 cyclic ? finalextrainfo : 0);
352
353 /* calculate new remaining length */
354 len -= control_block->length;
355 }
356
357 /* link this the last controlblock */
358 if (frame)
359 d->cb_list[frame - 1].cb->next = cb_entry->paddr;
360
361 /* update src and dst and length */
362 if (src && (info & BCM2835_DMA_S_INC))
363 src += control_block->length;
364 if (dst && (info & BCM2835_DMA_D_INC))
365 dst += control_block->length;
366
367 /* Length of total transfer */
368 d->size += control_block->length;
369 }
370
371 /* the last frame requires extra flags */
372 d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
373
374 /* detect a size missmatch */
375 if (buf_len && (d->size != buf_len))
376 goto error_cb;
377
378 return d;
379error_cb:
380 bcm2835_dma_free_cb_chain(d);
381
382 return NULL;
383}
384
385static void bcm2835_dma_fill_cb_chain_with_sg(
386 struct dma_chan *chan,
387 enum dma_transfer_direction direction,
388 struct bcm2835_cb_entry *cb,
389 struct scatterlist *sgl,
390 unsigned int sg_len)
391{
392 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
393 size_t len, max_len;
394 unsigned int i;
395 dma_addr_t addr;
396 struct scatterlist *sgent;
397
398 max_len = bcm2835_dma_max_frame_length(c);
399 for_each_sg(sgl, sgent, sg_len, i) {
400 for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
401 len > 0;
402 addr += cb->cb->length, len -= cb->cb->length, cb++) {
403 if (direction == DMA_DEV_TO_MEM)
404 cb->cb->dst = addr;
405 else
406 cb->cb->src = addr;
407 cb->cb->length = min(len, max_len);
408 }
409 }
410}
411
412static void bcm2835_dma_abort(struct bcm2835_chan *c)
413{
414 void __iomem *chan_base = c->chan_base;
415 long int timeout = 10000;
416
417 /*
418 * A zero control block address means the channel is idle.
419 * (The ACTIVE flag in the CS register is not a reliable indicator.)
420 */
421 if (!readl(chan_base + BCM2835_DMA_ADDR))
422 return;
423
424 /* Write 0 to the active bit - Pause the DMA */
425 writel(0, chan_base + BCM2835_DMA_CS);
426
427 /* Wait for any current AXI transfer to complete */
428 while ((readl(chan_base + BCM2835_DMA_CS) &
429 BCM2835_DMA_WAITING_FOR_WRITES) && --timeout)
430 cpu_relax();
431
432 /* Peripheral might be stuck and fail to signal AXI write responses */
433 if (!timeout)
434 dev_err(c->vc.chan.device->dev,
435 "failed to complete outstanding writes\n");
436
437 writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
438}
439
440static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
441{
442 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
443 struct bcm2835_desc *d;
444
445 if (!vd) {
446 c->desc = NULL;
447 return;
448 }
449
450 list_del(&vd->node);
451
452 c->desc = d = to_bcm2835_dma_desc(&vd->tx);
453
454 writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
455 writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
456}
457
458static irqreturn_t bcm2835_dma_callback(int irq, void *data)
459{
460 struct bcm2835_chan *c = data;
461 struct bcm2835_desc *d;
462 unsigned long flags;
463
464 /* check the shared interrupt */
465 if (c->irq_flags & IRQF_SHARED) {
466 /* check if the interrupt is enabled */
467 flags = readl(c->chan_base + BCM2835_DMA_CS);
468 /* if not set then we are not the reason for the irq */
469 if (!(flags & BCM2835_DMA_INT))
470 return IRQ_NONE;
471 }
472
473 spin_lock_irqsave(&c->vc.lock, flags);
474
475 /*
476 * Clear the INT flag to receive further interrupts. Keep the channel
477 * active in case the descriptor is cyclic or in case the client has
478 * already terminated the descriptor and issued a new one. (May happen
479 * if this IRQ handler is threaded.) If the channel is finished, it
480 * will remain idle despite the ACTIVE flag being set.
481 */
482 writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,
483 c->chan_base + BCM2835_DMA_CS);
484
485 d = c->desc;
486
487 if (d) {
488 if (d->cyclic) {
489 /* call the cyclic callback */
490 vchan_cyclic_callback(&d->vd);
491 } else if (!readl(c->chan_base + BCM2835_DMA_ADDR)) {
492 vchan_cookie_complete(&c->desc->vd);
493 bcm2835_dma_start_desc(c);
494 }
495 }
496
497 spin_unlock_irqrestore(&c->vc.lock, flags);
498
499 return IRQ_HANDLED;
500}
501
502static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
503{
504 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
505 struct device *dev = c->vc.chan.device->dev;
506
507 dev_dbg(dev, "Allocating DMA channel %d\n", c->ch);
508
509 /*
510 * Control blocks are 256 bit in length and must start at a 256 bit
511 * (32 byte) aligned address (BCM2835 ARM Peripherals, sec. 4.2.1.1).
512 */
513 c->cb_pool = dma_pool_create(dev_name(dev), dev,
514 sizeof(struct bcm2835_dma_cb), 32, 0);
515 if (!c->cb_pool) {
516 dev_err(dev, "unable to allocate descriptor pool\n");
517 return -ENOMEM;
518 }
519
520 return request_irq(c->irq_number, bcm2835_dma_callback,
521 c->irq_flags, "DMA IRQ", c);
522}
523
524static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
525{
526 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
527
528 vchan_free_chan_resources(&c->vc);
529 free_irq(c->irq_number, c);
530 dma_pool_destroy(c->cb_pool);
531
532 dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
533}
534
535static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
536{
537 return d->size;
538}
539
540static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
541{
542 unsigned int i;
543 size_t size;
544
545 for (size = i = 0; i < d->frames; i++) {
546 struct bcm2835_dma_cb *control_block = d->cb_list[i].cb;
547 size_t this_size = control_block->length;
548 dma_addr_t dma;
549
550 if (d->dir == DMA_DEV_TO_MEM)
551 dma = control_block->dst;
552 else
553 dma = control_block->src;
554
555 if (size)
556 size += this_size;
557 else if (addr >= dma && addr < dma + this_size)
558 size += dma + this_size - addr;
559 }
560
561 return size;
562}
563
564static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
565 dma_cookie_t cookie, struct dma_tx_state *txstate)
566{
567 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
568 struct virt_dma_desc *vd;
569 enum dma_status ret;
570 unsigned long flags;
571
572 ret = dma_cookie_status(chan, cookie, txstate);
573 if (ret == DMA_COMPLETE || !txstate)
574 return ret;
575
576 spin_lock_irqsave(&c->vc.lock, flags);
577 vd = vchan_find_desc(&c->vc, cookie);
578 if (vd) {
579 txstate->residue =
580 bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
581 } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
582 struct bcm2835_desc *d = c->desc;
583 dma_addr_t pos;
584
585 if (d->dir == DMA_MEM_TO_DEV)
586 pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
587 else if (d->dir == DMA_DEV_TO_MEM)
588 pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
589 else
590 pos = 0;
591
592 txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
593 } else {
594 txstate->residue = 0;
595 }
596
597 spin_unlock_irqrestore(&c->vc.lock, flags);
598
599 return ret;
600}
601
602static void bcm2835_dma_issue_pending(struct dma_chan *chan)
603{
604 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
605 unsigned long flags;
606
607 spin_lock_irqsave(&c->vc.lock, flags);
608 if (vchan_issue_pending(&c->vc) && !c->desc)
609 bcm2835_dma_start_desc(c);
610
611 spin_unlock_irqrestore(&c->vc.lock, flags);
612}
613
614static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy(
615 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
616 size_t len, unsigned long flags)
617{
618 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
619 struct bcm2835_desc *d;
620 u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;
621 u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;
622 size_t max_len = bcm2835_dma_max_frame_length(c);
623 size_t frames;
624
625 /* if src, dst or len is not given return with an error */
626 if (!src || !dst || !len)
627 return NULL;
628
629 /* calculate number of frames */
630 frames = bcm2835_dma_frames_for_length(len, max_len);
631
632 /* allocate the CB chain - this also fills in the pointers */
633 d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
634 info, extra, frames,
635 src, dst, len, 0, GFP_KERNEL);
636 if (!d)
637 return NULL;
638
639 return vchan_tx_prep(&c->vc, &d->vd, flags);
640}
641
642static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
643 struct dma_chan *chan,
644 struct scatterlist *sgl, unsigned int sg_len,
645 enum dma_transfer_direction direction,
646 unsigned long flags, void *context)
647{
648 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
649 struct bcm2835_desc *d;
650 dma_addr_t src = 0, dst = 0;
651 u32 info = BCM2835_DMA_WAIT_RESP;
652 u32 extra = BCM2835_DMA_INT_EN;
653 size_t frames;
654
655 if (!is_slave_direction(direction)) {
656 dev_err(chan->device->dev,
657 "%s: bad direction?\n", __func__);
658 return NULL;
659 }
660
661 if (c->dreq != 0)
662 info |= BCM2835_DMA_PER_MAP(c->dreq);
663
664 if (direction == DMA_DEV_TO_MEM) {
665 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
666 return NULL;
667 src = c->cfg.src_addr;
668 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
669 } else {
670 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
671 return NULL;
672 dst = c->cfg.dst_addr;
673 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
674 }
675
676 /* count frames in sg list */
677 frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
678
679 /* allocate the CB chain */
680 d = bcm2835_dma_create_cb_chain(chan, direction, false,
681 info, extra,
682 frames, src, dst, 0, 0,
683 GFP_NOWAIT);
684 if (!d)
685 return NULL;
686
687 /* fill in frames with scatterlist pointers */
688 bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
689 sgl, sg_len);
690
691 return vchan_tx_prep(&c->vc, &d->vd, flags);
692}
693
694static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
695 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
696 size_t period_len, enum dma_transfer_direction direction,
697 unsigned long flags)
698{
699 struct bcm2835_dmadev *od = to_bcm2835_dma_dev(chan->device);
700 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
701 struct bcm2835_desc *d;
702 dma_addr_t src, dst;
703 u32 info = BCM2835_DMA_WAIT_RESP;
704 u32 extra = 0;
705 size_t max_len = bcm2835_dma_max_frame_length(c);
706 size_t frames;
707
708 /* Grab configuration */
709 if (!is_slave_direction(direction)) {
710 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
711 return NULL;
712 }
713
714 if (!buf_len) {
715 dev_err(chan->device->dev,
716 "%s: bad buffer length (= 0)\n", __func__);
717 return NULL;
718 }
719
720 if (flags & DMA_PREP_INTERRUPT)
721 extra |= BCM2835_DMA_INT_EN;
722 else
723 period_len = buf_len;
724
725 /*
726 * warn if buf_len is not a multiple of period_len - this may leed
727 * to unexpected latencies for interrupts and thus audiable clicks
728 */
729 if (buf_len % period_len)
730 dev_warn_once(chan->device->dev,
731 "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
732 __func__, buf_len, period_len);
733
734 /* Setup DREQ channel */
735 if (c->dreq != 0)
736 info |= BCM2835_DMA_PER_MAP(c->dreq);
737
738 if (direction == DMA_DEV_TO_MEM) {
739 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
740 return NULL;
741 src = c->cfg.src_addr;
742 dst = buf_addr;
743 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
744 } else {
745 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
746 return NULL;
747 dst = c->cfg.dst_addr;
748 src = buf_addr;
749 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
750
751 /* non-lite channels can write zeroes w/o accessing memory */
752 if (buf_addr == od->zero_page && !c->is_lite_channel)
753 info |= BCM2835_DMA_S_IGNORE;
754 }
755
756 /* calculate number of frames */
757 frames = /* number of periods */
758 DIV_ROUND_UP(buf_len, period_len) *
759 /* number of frames per period */
760 bcm2835_dma_frames_for_length(period_len, max_len);
761
762 /*
763 * allocate the CB chain
764 * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
765 * implementation calls prep_dma_cyclic with interrupts disabled.
766 */
767 d = bcm2835_dma_create_cb_chain(chan, direction, true,
768 info, extra,
769 frames, src, dst, buf_len,
770 period_len, GFP_NOWAIT);
771 if (!d)
772 return NULL;
773
774 /* wrap around into a loop */
775 d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
776
777 return vchan_tx_prep(&c->vc, &d->vd, flags);
778}
779
780static int bcm2835_dma_slave_config(struct dma_chan *chan,
781 struct dma_slave_config *cfg)
782{
783 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
784
785 c->cfg = *cfg;
786
787 return 0;
788}
789
790static int bcm2835_dma_terminate_all(struct dma_chan *chan)
791{
792 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
793 unsigned long flags;
794 LIST_HEAD(head);
795
796 spin_lock_irqsave(&c->vc.lock, flags);
797
798 /* stop DMA activity */
799 if (c->desc) {
800 vchan_terminate_vdesc(&c->desc->vd);
801 c->desc = NULL;
802 bcm2835_dma_abort(c);
803 }
804
805 vchan_get_all_descriptors(&c->vc, &head);
806 spin_unlock_irqrestore(&c->vc.lock, flags);
807 vchan_dma_desc_free_list(&c->vc, &head);
808
809 return 0;
810}
811
812static void bcm2835_dma_synchronize(struct dma_chan *chan)
813{
814 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
815
816 vchan_synchronize(&c->vc);
817}
818
819static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
820 int irq, unsigned int irq_flags)
821{
822 struct bcm2835_chan *c;
823
824 c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
825 if (!c)
826 return -ENOMEM;
827
828 c->vc.desc_free = bcm2835_dma_desc_free;
829 vchan_init(&c->vc, &d->ddev);
830
831 c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
832 c->ch = chan_id;
833 c->irq_number = irq;
834 c->irq_flags = irq_flags;
835
836 /* check in DEBUG register if this is a LITE channel */
837 if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
838 BCM2835_DMA_DEBUG_LITE)
839 c->is_lite_channel = true;
840
841 return 0;
842}
843
844static void bcm2835_dma_free(struct bcm2835_dmadev *od)
845{
846 struct bcm2835_chan *c, *next;
847
848 list_for_each_entry_safe(c, next, &od->ddev.channels,
849 vc.chan.device_node) {
850 list_del(&c->vc.chan.device_node);
851 tasklet_kill(&c->vc.task);
852 }
853
854 dma_unmap_page_attrs(od->ddev.dev, od->zero_page, PAGE_SIZE,
855 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
856}
857
858static const struct of_device_id bcm2835_dma_of_match[] = {
859 { .compatible = "brcm,bcm2835-dma", },
860 {},
861};
862MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
863
864static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
865 struct of_dma *ofdma)
866{
867 struct bcm2835_dmadev *d = ofdma->of_dma_data;
868 struct dma_chan *chan;
869
870 chan = dma_get_any_slave_channel(&d->ddev);
871 if (!chan)
872 return NULL;
873
874 /* Set DREQ from param */
875 to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
876
877 return chan;
878}
879
880static int bcm2835_dma_probe(struct platform_device *pdev)
881{
882 struct bcm2835_dmadev *od;
883 struct resource *res;
884 void __iomem *base;
885 int rc;
886 int i, j;
887 int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1];
888 int irq_flags;
889 uint32_t chans_available;
890 char chan_name[BCM2835_DMA_CHAN_NAME_SIZE];
891
892 if (!pdev->dev.dma_mask)
893 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
894
895 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
896 if (rc) {
897 dev_err(&pdev->dev, "Unable to set DMA mask\n");
898 return rc;
899 }
900
901 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
902 if (!od)
903 return -ENOMEM;
904
905 pdev->dev.dma_parms = &od->dma_parms;
906 dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
907
908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
909 base = devm_ioremap_resource(&pdev->dev, res);
910 if (IS_ERR(base))
911 return PTR_ERR(base);
912
913 od->base = base;
914
915 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
916 dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
917 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
918 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
919 od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
920 od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
921 od->ddev.device_tx_status = bcm2835_dma_tx_status;
922 od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
923 od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
924 od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
925 od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy;
926 od->ddev.device_config = bcm2835_dma_slave_config;
927 od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
928 od->ddev.device_synchronize = bcm2835_dma_synchronize;
929 od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
930 od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
931 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
932 BIT(DMA_MEM_TO_MEM);
933 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
934 od->ddev.descriptor_reuse = true;
935 od->ddev.dev = &pdev->dev;
936 INIT_LIST_HEAD(&od->ddev.channels);
937
938 platform_set_drvdata(pdev, od);
939
940 od->zero_page = dma_map_page_attrs(od->ddev.dev, ZERO_PAGE(0), 0,
941 PAGE_SIZE, DMA_TO_DEVICE,
942 DMA_ATTR_SKIP_CPU_SYNC);
943 if (dma_mapping_error(od->ddev.dev, od->zero_page)) {
944 dev_err(&pdev->dev, "Failed to map zero page\n");
945 return -ENOMEM;
946 }
947
948 /* Request DMA channel mask from device tree */
949 if (of_property_read_u32(pdev->dev.of_node,
950 "brcm,dma-channel-mask",
951 &chans_available)) {
952 dev_err(&pdev->dev, "Failed to get channel mask\n");
953 rc = -EINVAL;
954 goto err_no_dma;
955 }
956
957 /* get irqs for each channel that we support */
958 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
959 /* skip masked out channels */
960 if (!(chans_available & (1 << i))) {
961 irq[i] = -1;
962 continue;
963 }
964
965 /* get the named irq */
966 snprintf(chan_name, sizeof(chan_name), "dma%i", i);
967 irq[i] = platform_get_irq_byname(pdev, chan_name);
968 if (irq[i] >= 0)
969 continue;
970
971 /* legacy device tree case handling */
972 dev_warn_once(&pdev->dev,
973 "missing interrupt-names property in device tree - legacy interpretation is used\n");
974 /*
975 * in case of channel >= 11
976 * use the 11th interrupt and that is shared
977 */
978 irq[i] = platform_get_irq(pdev, i < 11 ? i : 11);
979 }
980
981 /* get irqs for each channel */
982 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
983 /* skip channels without irq */
984 if (irq[i] < 0)
985 continue;
986
987 /* check if there are other channels that also use this irq */
988 irq_flags = 0;
989 for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)
990 if ((i != j) && (irq[j] == irq[i])) {
991 irq_flags = IRQF_SHARED;
992 break;
993 }
994
995 /* initialize the channel */
996 rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);
997 if (rc)
998 goto err_no_dma;
999 }
1000
1001 dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
1002
1003 /* Device-tree DMA controller registration */
1004 rc = of_dma_controller_register(pdev->dev.of_node,
1005 bcm2835_dma_xlate, od);
1006 if (rc) {
1007 dev_err(&pdev->dev, "Failed to register DMA controller\n");
1008 goto err_no_dma;
1009 }
1010
1011 rc = dma_async_device_register(&od->ddev);
1012 if (rc) {
1013 dev_err(&pdev->dev,
1014 "Failed to register slave DMA engine device: %d\n", rc);
1015 goto err_no_dma;
1016 }
1017
1018 dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
1019
1020 return 0;
1021
1022err_no_dma:
1023 bcm2835_dma_free(od);
1024 return rc;
1025}
1026
1027static int bcm2835_dma_remove(struct platform_device *pdev)
1028{
1029 struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
1030
1031 dma_async_device_unregister(&od->ddev);
1032 bcm2835_dma_free(od);
1033
1034 return 0;
1035}
1036
1037static struct platform_driver bcm2835_dma_driver = {
1038 .probe = bcm2835_dma_probe,
1039 .remove = bcm2835_dma_remove,
1040 .driver = {
1041 .name = "bcm2835-dma",
1042 .of_match_table = of_match_ptr(bcm2835_dma_of_match),
1043 },
1044};
1045
1046module_platform_driver(bcm2835_dma_driver);
1047
1048MODULE_ALIAS("platform:bcm2835-dma");
1049MODULE_DESCRIPTION("BCM2835 DMA engine driver");
1050MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1051MODULE_LICENSE("GPL");
1/*
2 * BCM2835 DMA engine support
3 *
4 * This driver only supports cyclic DMA transfers
5 * as needed for the I2S module.
6 *
7 * Author: Florian Meier <florian.meier@koalo.de>
8 * Copyright 2013
9 *
10 * Based on
11 * OMAP DMAengine support by Russell King
12 *
13 * BCM2708 DMA Driver
14 * Copyright (C) 2010 Broadcom
15 *
16 * Raspberry Pi PCM I2S ALSA Driver
17 * Copyright (c) by Phil Poole 2013
18 *
19 * MARVELL MMP Peripheral DMA Driver
20 * Copyright 2012 Marvell International Ltd.
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License as published by
24 * the Free Software Foundation; either version 2 of the License, or
25 * (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 */
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/dmapool.h>
35#include <linux/err.h>
36#include <linux/init.h>
37#include <linux/interrupt.h>
38#include <linux/list.h>
39#include <linux/module.h>
40#include <linux/platform_device.h>
41#include <linux/slab.h>
42#include <linux/io.h>
43#include <linux/spinlock.h>
44#include <linux/of.h>
45#include <linux/of_dma.h>
46
47#include "virt-dma.h"
48
49#define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
50#define BCM2835_DMA_CHAN_NAME_SIZE 8
51
52struct bcm2835_dmadev {
53 struct dma_device ddev;
54 spinlock_t lock;
55 void __iomem *base;
56 struct device_dma_parameters dma_parms;
57};
58
59struct bcm2835_dma_cb {
60 uint32_t info;
61 uint32_t src;
62 uint32_t dst;
63 uint32_t length;
64 uint32_t stride;
65 uint32_t next;
66 uint32_t pad[2];
67};
68
69struct bcm2835_cb_entry {
70 struct bcm2835_dma_cb *cb;
71 dma_addr_t paddr;
72};
73
74struct bcm2835_chan {
75 struct virt_dma_chan vc;
76 struct list_head node;
77
78 struct dma_slave_config cfg;
79 unsigned int dreq;
80
81 int ch;
82 struct bcm2835_desc *desc;
83 struct dma_pool *cb_pool;
84
85 void __iomem *chan_base;
86 int irq_number;
87 unsigned int irq_flags;
88
89 bool is_lite_channel;
90};
91
92struct bcm2835_desc {
93 struct bcm2835_chan *c;
94 struct virt_dma_desc vd;
95 enum dma_transfer_direction dir;
96
97 unsigned int frames;
98 size_t size;
99
100 bool cyclic;
101
102 struct bcm2835_cb_entry cb_list[];
103};
104
105#define BCM2835_DMA_CS 0x00
106#define BCM2835_DMA_ADDR 0x04
107#define BCM2835_DMA_TI 0x08
108#define BCM2835_DMA_SOURCE_AD 0x0c
109#define BCM2835_DMA_DEST_AD 0x10
110#define BCM2835_DMA_LEN 0x14
111#define BCM2835_DMA_STRIDE 0x18
112#define BCM2835_DMA_NEXTCB 0x1c
113#define BCM2835_DMA_DEBUG 0x20
114
115/* DMA CS Control and Status bits */
116#define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */
117#define BCM2835_DMA_END BIT(1) /* current CB has ended */
118#define BCM2835_DMA_INT BIT(2) /* interrupt status */
119#define BCM2835_DMA_DREQ BIT(3) /* DREQ state */
120#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
121#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
122#define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
123 * AXI-write to ack
124 */
125#define BCM2835_DMA_ERR BIT(8)
126#define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
127#define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
128/* current value of TI.BCM2835_DMA_WAIT_RESP */
129#define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
130#define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */
131#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
132#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
133
134/* Transfer information bits - also bcm2835_cb.info field */
135#define BCM2835_DMA_INT_EN BIT(0)
136#define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */
137#define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */
138#define BCM2835_DMA_D_INC BIT(4)
139#define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */
140#define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */
141#define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */
142#define BCM2835_DMA_S_INC BIT(8)
143#define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */
144#define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */
145#define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */
146#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
147#define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
148#define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */
149#define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
150
151/* debug register bits */
152#define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0)
153#define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1)
154#define BCM2835_DMA_DEBUG_READ_ERR BIT(2)
155#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
156#define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
157#define BCM2835_DMA_DEBUG_ID_SHIFT 16
158#define BCM2835_DMA_DEBUG_ID_BITS 9
159#define BCM2835_DMA_DEBUG_STATE_SHIFT 16
160#define BCM2835_DMA_DEBUG_STATE_BITS 9
161#define BCM2835_DMA_DEBUG_VERSION_SHIFT 25
162#define BCM2835_DMA_DEBUG_VERSION_BITS 3
163#define BCM2835_DMA_DEBUG_LITE BIT(28)
164
165/* shared registers for all dma channels */
166#define BCM2835_DMA_INT_STATUS 0xfe0
167#define BCM2835_DMA_ENABLE 0xff0
168
169#define BCM2835_DMA_DATA_TYPE_S8 1
170#define BCM2835_DMA_DATA_TYPE_S16 2
171#define BCM2835_DMA_DATA_TYPE_S32 4
172#define BCM2835_DMA_DATA_TYPE_S128 16
173
174/* Valid only for channels 0 - 14, 15 has its own base address */
175#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
176#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
177
178/* the max dma length for different channels */
179#define MAX_DMA_LEN SZ_1G
180#define MAX_LITE_DMA_LEN (SZ_64K - 4)
181
182static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
183{
184 /* lite and normal channels have different max frame length */
185 return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
186}
187
188/* how many frames of max_len size do we need to transfer len bytes */
189static inline size_t bcm2835_dma_frames_for_length(size_t len,
190 size_t max_len)
191{
192 return DIV_ROUND_UP(len, max_len);
193}
194
195static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
196{
197 return container_of(d, struct bcm2835_dmadev, ddev);
198}
199
200static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
201{
202 return container_of(c, struct bcm2835_chan, vc.chan);
203}
204
205static inline struct bcm2835_desc *to_bcm2835_dma_desc(
206 struct dma_async_tx_descriptor *t)
207{
208 return container_of(t, struct bcm2835_desc, vd.tx);
209}
210
211static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
212{
213 size_t i;
214
215 for (i = 0; i < desc->frames; i++)
216 dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
217 desc->cb_list[i].paddr);
218
219 kfree(desc);
220}
221
222static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
223{
224 bcm2835_dma_free_cb_chain(
225 container_of(vd, struct bcm2835_desc, vd));
226}
227
228static void bcm2835_dma_create_cb_set_length(
229 struct bcm2835_chan *chan,
230 struct bcm2835_dma_cb *control_block,
231 size_t len,
232 size_t period_len,
233 size_t *total_len,
234 u32 finalextrainfo)
235{
236 size_t max_len = bcm2835_dma_max_frame_length(chan);
237
238 /* set the length taking lite-channel limitations into account */
239 control_block->length = min_t(u32, len, max_len);
240
241 /* finished if we have no period_length */
242 if (!period_len)
243 return;
244
245 /*
246 * period_len means: that we need to generate
247 * transfers that are terminating at every
248 * multiple of period_len - this is typically
249 * used to set the interrupt flag in info
250 * which is required during cyclic transfers
251 */
252
253 /* have we filled in period_length yet? */
254 if (*total_len + control_block->length < period_len)
255 return;
256
257 /* calculate the length that remains to reach period_length */
258 control_block->length = period_len - *total_len;
259
260 /* reset total_length for next period */
261 *total_len = 0;
262
263 /* add extrainfo bits in info */
264 control_block->info |= finalextrainfo;
265}
266
267static inline size_t bcm2835_dma_count_frames_for_sg(
268 struct bcm2835_chan *c,
269 struct scatterlist *sgl,
270 unsigned int sg_len)
271{
272 size_t frames = 0;
273 struct scatterlist *sgent;
274 unsigned int i;
275 size_t plength = bcm2835_dma_max_frame_length(c);
276
277 for_each_sg(sgl, sgent, sg_len, i)
278 frames += bcm2835_dma_frames_for_length(
279 sg_dma_len(sgent), plength);
280
281 return frames;
282}
283
284/**
285 * bcm2835_dma_create_cb_chain - create a control block and fills data in
286 *
287 * @chan: the @dma_chan for which we run this
288 * @direction: the direction in which we transfer
289 * @cyclic: it is a cyclic transfer
290 * @info: the default info bits to apply per controlblock
291 * @frames: number of controlblocks to allocate
292 * @src: the src address to assign (if the S_INC bit is set
293 * in @info, then it gets incremented)
294 * @dst: the dst address to assign (if the D_INC bit is set
295 * in @info, then it gets incremented)
296 * @buf_len: the full buffer length (may also be 0)
297 * @period_len: the period length when to apply @finalextrainfo
298 * in addition to the last transfer
299 * this will also break some control-blocks early
300 * @finalextrainfo: additional bits in last controlblock
301 * (or when period_len is reached in case of cyclic)
302 * @gfp: the GFP flag to use for allocation
303 */
304static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
305 struct dma_chan *chan, enum dma_transfer_direction direction,
306 bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
307 dma_addr_t src, dma_addr_t dst, size_t buf_len,
308 size_t period_len, gfp_t gfp)
309{
310 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
311 size_t len = buf_len, total_len;
312 size_t frame;
313 struct bcm2835_desc *d;
314 struct bcm2835_cb_entry *cb_entry;
315 struct bcm2835_dma_cb *control_block;
316
317 if (!frames)
318 return NULL;
319
320 /* allocate and setup the descriptor. */
321 d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry),
322 gfp);
323 if (!d)
324 return NULL;
325
326 d->c = c;
327 d->dir = direction;
328 d->cyclic = cyclic;
329
330 /*
331 * Iterate over all frames, create a control block
332 * for each frame and link them together.
333 */
334 for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
335 cb_entry = &d->cb_list[frame];
336 cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
337 &cb_entry->paddr);
338 if (!cb_entry->cb)
339 goto error_cb;
340
341 /* fill in the control block */
342 control_block = cb_entry->cb;
343 control_block->info = info;
344 control_block->src = src;
345 control_block->dst = dst;
346 control_block->stride = 0;
347 control_block->next = 0;
348 /* set up length in control_block if requested */
349 if (buf_len) {
350 /* calculate length honoring period_length */
351 bcm2835_dma_create_cb_set_length(
352 c, control_block,
353 len, period_len, &total_len,
354 cyclic ? finalextrainfo : 0);
355
356 /* calculate new remaining length */
357 len -= control_block->length;
358 }
359
360 /* link this the last controlblock */
361 if (frame)
362 d->cb_list[frame - 1].cb->next = cb_entry->paddr;
363
364 /* update src and dst and length */
365 if (src && (info & BCM2835_DMA_S_INC))
366 src += control_block->length;
367 if (dst && (info & BCM2835_DMA_D_INC))
368 dst += control_block->length;
369
370 /* Length of total transfer */
371 d->size += control_block->length;
372 }
373
374 /* the last frame requires extra flags */
375 d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
376
377 /* detect a size missmatch */
378 if (buf_len && (d->size != buf_len))
379 goto error_cb;
380
381 return d;
382error_cb:
383 bcm2835_dma_free_cb_chain(d);
384
385 return NULL;
386}
387
388static void bcm2835_dma_fill_cb_chain_with_sg(
389 struct dma_chan *chan,
390 enum dma_transfer_direction direction,
391 struct bcm2835_cb_entry *cb,
392 struct scatterlist *sgl,
393 unsigned int sg_len)
394{
395 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
396 size_t len, max_len;
397 unsigned int i;
398 dma_addr_t addr;
399 struct scatterlist *sgent;
400
401 max_len = bcm2835_dma_max_frame_length(c);
402 for_each_sg(sgl, sgent, sg_len, i) {
403 for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
404 len > 0;
405 addr += cb->cb->length, len -= cb->cb->length, cb++) {
406 if (direction == DMA_DEV_TO_MEM)
407 cb->cb->dst = addr;
408 else
409 cb->cb->src = addr;
410 cb->cb->length = min(len, max_len);
411 }
412 }
413}
414
415static int bcm2835_dma_abort(void __iomem *chan_base)
416{
417 unsigned long cs;
418 long int timeout = 10000;
419
420 cs = readl(chan_base + BCM2835_DMA_CS);
421 if (!(cs & BCM2835_DMA_ACTIVE))
422 return 0;
423
424 /* Write 0 to the active bit - Pause the DMA */
425 writel(0, chan_base + BCM2835_DMA_CS);
426
427 /* Wait for any current AXI transfer to complete */
428 while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
429 cpu_relax();
430 cs = readl(chan_base + BCM2835_DMA_CS);
431 }
432
433 /* We'll un-pause when we set of our next DMA */
434 if (!timeout)
435 return -ETIMEDOUT;
436
437 if (!(cs & BCM2835_DMA_ACTIVE))
438 return 0;
439
440 /* Terminate the control block chain */
441 writel(0, chan_base + BCM2835_DMA_NEXTCB);
442
443 /* Abort the whole DMA */
444 writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
445 chan_base + BCM2835_DMA_CS);
446
447 return 0;
448}
449
450static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
451{
452 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
453 struct bcm2835_desc *d;
454
455 if (!vd) {
456 c->desc = NULL;
457 return;
458 }
459
460 list_del(&vd->node);
461
462 c->desc = d = to_bcm2835_dma_desc(&vd->tx);
463
464 writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
465 writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
466}
467
468static irqreturn_t bcm2835_dma_callback(int irq, void *data)
469{
470 struct bcm2835_chan *c = data;
471 struct bcm2835_desc *d;
472 unsigned long flags;
473
474 /* check the shared interrupt */
475 if (c->irq_flags & IRQF_SHARED) {
476 /* check if the interrupt is enabled */
477 flags = readl(c->chan_base + BCM2835_DMA_CS);
478 /* if not set then we are not the reason for the irq */
479 if (!(flags & BCM2835_DMA_INT))
480 return IRQ_NONE;
481 }
482
483 spin_lock_irqsave(&c->vc.lock, flags);
484
485 /* Acknowledge interrupt */
486 writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
487
488 d = c->desc;
489
490 if (d) {
491 if (d->cyclic) {
492 /* call the cyclic callback */
493 vchan_cyclic_callback(&d->vd);
494
495 /* Keep the DMA engine running */
496 writel(BCM2835_DMA_ACTIVE,
497 c->chan_base + BCM2835_DMA_CS);
498 } else {
499 vchan_cookie_complete(&c->desc->vd);
500 bcm2835_dma_start_desc(c);
501 }
502 }
503
504 spin_unlock_irqrestore(&c->vc.lock, flags);
505
506 return IRQ_HANDLED;
507}
508
509static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
510{
511 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
512 struct device *dev = c->vc.chan.device->dev;
513
514 dev_dbg(dev, "Allocating DMA channel %d\n", c->ch);
515
516 c->cb_pool = dma_pool_create(dev_name(dev), dev,
517 sizeof(struct bcm2835_dma_cb), 0, 0);
518 if (!c->cb_pool) {
519 dev_err(dev, "unable to allocate descriptor pool\n");
520 return -ENOMEM;
521 }
522
523 return request_irq(c->irq_number, bcm2835_dma_callback,
524 c->irq_flags, "DMA IRQ", c);
525}
526
527static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
528{
529 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
530
531 vchan_free_chan_resources(&c->vc);
532 free_irq(c->irq_number, c);
533 dma_pool_destroy(c->cb_pool);
534
535 dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
536}
537
538static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
539{
540 return d->size;
541}
542
543static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
544{
545 unsigned int i;
546 size_t size;
547
548 for (size = i = 0; i < d->frames; i++) {
549 struct bcm2835_dma_cb *control_block = d->cb_list[i].cb;
550 size_t this_size = control_block->length;
551 dma_addr_t dma;
552
553 if (d->dir == DMA_DEV_TO_MEM)
554 dma = control_block->dst;
555 else
556 dma = control_block->src;
557
558 if (size)
559 size += this_size;
560 else if (addr >= dma && addr < dma + this_size)
561 size += dma + this_size - addr;
562 }
563
564 return size;
565}
566
567static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
568 dma_cookie_t cookie, struct dma_tx_state *txstate)
569{
570 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
571 struct virt_dma_desc *vd;
572 enum dma_status ret;
573 unsigned long flags;
574
575 ret = dma_cookie_status(chan, cookie, txstate);
576 if (ret == DMA_COMPLETE || !txstate)
577 return ret;
578
579 spin_lock_irqsave(&c->vc.lock, flags);
580 vd = vchan_find_desc(&c->vc, cookie);
581 if (vd) {
582 txstate->residue =
583 bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
584 } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
585 struct bcm2835_desc *d = c->desc;
586 dma_addr_t pos;
587
588 if (d->dir == DMA_MEM_TO_DEV)
589 pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
590 else if (d->dir == DMA_DEV_TO_MEM)
591 pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
592 else
593 pos = 0;
594
595 txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
596 } else {
597 txstate->residue = 0;
598 }
599
600 spin_unlock_irqrestore(&c->vc.lock, flags);
601
602 return ret;
603}
604
605static void bcm2835_dma_issue_pending(struct dma_chan *chan)
606{
607 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
608 unsigned long flags;
609
610 spin_lock_irqsave(&c->vc.lock, flags);
611 if (vchan_issue_pending(&c->vc) && !c->desc)
612 bcm2835_dma_start_desc(c);
613
614 spin_unlock_irqrestore(&c->vc.lock, flags);
615}
616
617static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy(
618 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
619 size_t len, unsigned long flags)
620{
621 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
622 struct bcm2835_desc *d;
623 u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;
624 u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;
625 size_t max_len = bcm2835_dma_max_frame_length(c);
626 size_t frames;
627
628 /* if src, dst or len is not given return with an error */
629 if (!src || !dst || !len)
630 return NULL;
631
632 /* calculate number of frames */
633 frames = bcm2835_dma_frames_for_length(len, max_len);
634
635 /* allocate the CB chain - this also fills in the pointers */
636 d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
637 info, extra, frames,
638 src, dst, len, 0, GFP_KERNEL);
639 if (!d)
640 return NULL;
641
642 return vchan_tx_prep(&c->vc, &d->vd, flags);
643}
644
645static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
646 struct dma_chan *chan,
647 struct scatterlist *sgl, unsigned int sg_len,
648 enum dma_transfer_direction direction,
649 unsigned long flags, void *context)
650{
651 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
652 struct bcm2835_desc *d;
653 dma_addr_t src = 0, dst = 0;
654 u32 info = BCM2835_DMA_WAIT_RESP;
655 u32 extra = BCM2835_DMA_INT_EN;
656 size_t frames;
657
658 if (!is_slave_direction(direction)) {
659 dev_err(chan->device->dev,
660 "%s: bad direction?\n", __func__);
661 return NULL;
662 }
663
664 if (c->dreq != 0)
665 info |= BCM2835_DMA_PER_MAP(c->dreq);
666
667 if (direction == DMA_DEV_TO_MEM) {
668 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
669 return NULL;
670 src = c->cfg.src_addr;
671 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
672 } else {
673 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
674 return NULL;
675 dst = c->cfg.dst_addr;
676 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
677 }
678
679 /* count frames in sg list */
680 frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
681
682 /* allocate the CB chain */
683 d = bcm2835_dma_create_cb_chain(chan, direction, false,
684 info, extra,
685 frames, src, dst, 0, 0,
686 GFP_KERNEL);
687 if (!d)
688 return NULL;
689
690 /* fill in frames with scatterlist pointers */
691 bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
692 sgl, sg_len);
693
694 return vchan_tx_prep(&c->vc, &d->vd, flags);
695}
696
697static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
698 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
699 size_t period_len, enum dma_transfer_direction direction,
700 unsigned long flags)
701{
702 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
703 struct bcm2835_desc *d;
704 dma_addr_t src, dst;
705 u32 info = BCM2835_DMA_WAIT_RESP;
706 u32 extra = BCM2835_DMA_INT_EN;
707 size_t max_len = bcm2835_dma_max_frame_length(c);
708 size_t frames;
709
710 /* Grab configuration */
711 if (!is_slave_direction(direction)) {
712 dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
713 return NULL;
714 }
715
716 if (!buf_len) {
717 dev_err(chan->device->dev,
718 "%s: bad buffer length (= 0)\n", __func__);
719 return NULL;
720 }
721
722 /*
723 * warn if buf_len is not a multiple of period_len - this may leed
724 * to unexpected latencies for interrupts and thus audiable clicks
725 */
726 if (buf_len % period_len)
727 dev_warn_once(chan->device->dev,
728 "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
729 __func__, buf_len, period_len);
730
731 /* Setup DREQ channel */
732 if (c->dreq != 0)
733 info |= BCM2835_DMA_PER_MAP(c->dreq);
734
735 if (direction == DMA_DEV_TO_MEM) {
736 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
737 return NULL;
738 src = c->cfg.src_addr;
739 dst = buf_addr;
740 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
741 } else {
742 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
743 return NULL;
744 dst = c->cfg.dst_addr;
745 src = buf_addr;
746 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
747 }
748
749 /* calculate number of frames */
750 frames = /* number of periods */
751 DIV_ROUND_UP(buf_len, period_len) *
752 /* number of frames per period */
753 bcm2835_dma_frames_for_length(period_len, max_len);
754
755 /*
756 * allocate the CB chain
757 * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
758 * implementation calls prep_dma_cyclic with interrupts disabled.
759 */
760 d = bcm2835_dma_create_cb_chain(chan, direction, true,
761 info, extra,
762 frames, src, dst, buf_len,
763 period_len, GFP_NOWAIT);
764 if (!d)
765 return NULL;
766
767 /* wrap around into a loop */
768 d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
769
770 return vchan_tx_prep(&c->vc, &d->vd, flags);
771}
772
773static int bcm2835_dma_slave_config(struct dma_chan *chan,
774 struct dma_slave_config *cfg)
775{
776 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
777
778 if ((cfg->direction == DMA_DEV_TO_MEM &&
779 cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
780 (cfg->direction == DMA_MEM_TO_DEV &&
781 cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
782 !is_slave_direction(cfg->direction)) {
783 return -EINVAL;
784 }
785
786 c->cfg = *cfg;
787
788 return 0;
789}
790
791static int bcm2835_dma_terminate_all(struct dma_chan *chan)
792{
793 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
794 struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
795 unsigned long flags;
796 int timeout = 10000;
797 LIST_HEAD(head);
798
799 spin_lock_irqsave(&c->vc.lock, flags);
800
801 /* Prevent this channel being scheduled */
802 spin_lock(&d->lock);
803 list_del_init(&c->node);
804 spin_unlock(&d->lock);
805
806 /*
807 * Stop DMA activity: we assume the callback will not be called
808 * after bcm_dma_abort() returns (even if it does, it will see
809 * c->desc is NULL and exit.)
810 */
811 if (c->desc) {
812 bcm2835_dma_desc_free(&c->desc->vd);
813 c->desc = NULL;
814 bcm2835_dma_abort(c->chan_base);
815
816 /* Wait for stopping */
817 while (--timeout) {
818 if (!(readl(c->chan_base + BCM2835_DMA_CS) &
819 BCM2835_DMA_ACTIVE))
820 break;
821
822 cpu_relax();
823 }
824
825 if (!timeout)
826 dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
827 }
828
829 vchan_get_all_descriptors(&c->vc, &head);
830 spin_unlock_irqrestore(&c->vc.lock, flags);
831 vchan_dma_desc_free_list(&c->vc, &head);
832
833 return 0;
834}
835
836static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
837 int irq, unsigned int irq_flags)
838{
839 struct bcm2835_chan *c;
840
841 c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
842 if (!c)
843 return -ENOMEM;
844
845 c->vc.desc_free = bcm2835_dma_desc_free;
846 vchan_init(&c->vc, &d->ddev);
847 INIT_LIST_HEAD(&c->node);
848
849 c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
850 c->ch = chan_id;
851 c->irq_number = irq;
852 c->irq_flags = irq_flags;
853
854 /* check in DEBUG register if this is a LITE channel */
855 if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
856 BCM2835_DMA_DEBUG_LITE)
857 c->is_lite_channel = true;
858
859 return 0;
860}
861
862static void bcm2835_dma_free(struct bcm2835_dmadev *od)
863{
864 struct bcm2835_chan *c, *next;
865
866 list_for_each_entry_safe(c, next, &od->ddev.channels,
867 vc.chan.device_node) {
868 list_del(&c->vc.chan.device_node);
869 tasklet_kill(&c->vc.task);
870 }
871}
872
873static const struct of_device_id bcm2835_dma_of_match[] = {
874 { .compatible = "brcm,bcm2835-dma", },
875 {},
876};
877MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
878
879static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
880 struct of_dma *ofdma)
881{
882 struct bcm2835_dmadev *d = ofdma->of_dma_data;
883 struct dma_chan *chan;
884
885 chan = dma_get_any_slave_channel(&d->ddev);
886 if (!chan)
887 return NULL;
888
889 /* Set DREQ from param */
890 to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
891
892 return chan;
893}
894
895static int bcm2835_dma_probe(struct platform_device *pdev)
896{
897 struct bcm2835_dmadev *od;
898 struct resource *res;
899 void __iomem *base;
900 int rc;
901 int i, j;
902 int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1];
903 int irq_flags;
904 uint32_t chans_available;
905 char chan_name[BCM2835_DMA_CHAN_NAME_SIZE];
906
907 if (!pdev->dev.dma_mask)
908 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
909
910 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
911 if (rc)
912 return rc;
913
914 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
915 if (!od)
916 return -ENOMEM;
917
918 pdev->dev.dma_parms = &od->dma_parms;
919 dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
920
921 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
922 base = devm_ioremap_resource(&pdev->dev, res);
923 if (IS_ERR(base))
924 return PTR_ERR(base);
925
926 od->base = base;
927
928 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
929 dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
930 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
931 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
932 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
933 od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
934 od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
935 od->ddev.device_tx_status = bcm2835_dma_tx_status;
936 od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
937 od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
938 od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
939 od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy;
940 od->ddev.device_config = bcm2835_dma_slave_config;
941 od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
942 od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
943 od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
944 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
945 BIT(DMA_MEM_TO_MEM);
946 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
947 od->ddev.dev = &pdev->dev;
948 INIT_LIST_HEAD(&od->ddev.channels);
949 spin_lock_init(&od->lock);
950
951 platform_set_drvdata(pdev, od);
952
953 /* Request DMA channel mask from device tree */
954 if (of_property_read_u32(pdev->dev.of_node,
955 "brcm,dma-channel-mask",
956 &chans_available)) {
957 dev_err(&pdev->dev, "Failed to get channel mask\n");
958 rc = -EINVAL;
959 goto err_no_dma;
960 }
961
962 /* get irqs for each channel that we support */
963 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
964 /* skip masked out channels */
965 if (!(chans_available & (1 << i))) {
966 irq[i] = -1;
967 continue;
968 }
969
970 /* get the named irq */
971 snprintf(chan_name, sizeof(chan_name), "dma%i", i);
972 irq[i] = platform_get_irq_byname(pdev, chan_name);
973 if (irq[i] >= 0)
974 continue;
975
976 /* legacy device tree case handling */
977 dev_warn_once(&pdev->dev,
978 "missing interrupt-names property in device tree - legacy interpretation is used\n");
979 /*
980 * in case of channel >= 11
981 * use the 11th interrupt and that is shared
982 */
983 irq[i] = platform_get_irq(pdev, i < 11 ? i : 11);
984 }
985
986 /* get irqs for each channel */
987 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
988 /* skip channels without irq */
989 if (irq[i] < 0)
990 continue;
991
992 /* check if there are other channels that also use this irq */
993 irq_flags = 0;
994 for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)
995 if ((i != j) && (irq[j] == irq[i])) {
996 irq_flags = IRQF_SHARED;
997 break;
998 }
999
1000 /* initialize the channel */
1001 rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);
1002 if (rc)
1003 goto err_no_dma;
1004 }
1005
1006 dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
1007
1008 /* Device-tree DMA controller registration */
1009 rc = of_dma_controller_register(pdev->dev.of_node,
1010 bcm2835_dma_xlate, od);
1011 if (rc) {
1012 dev_err(&pdev->dev, "Failed to register DMA controller\n");
1013 goto err_no_dma;
1014 }
1015
1016 rc = dma_async_device_register(&od->ddev);
1017 if (rc) {
1018 dev_err(&pdev->dev,
1019 "Failed to register slave DMA engine device: %d\n", rc);
1020 goto err_no_dma;
1021 }
1022
1023 dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
1024
1025 return 0;
1026
1027err_no_dma:
1028 bcm2835_dma_free(od);
1029 return rc;
1030}
1031
1032static int bcm2835_dma_remove(struct platform_device *pdev)
1033{
1034 struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
1035
1036 dma_async_device_unregister(&od->ddev);
1037 bcm2835_dma_free(od);
1038
1039 return 0;
1040}
1041
1042static struct platform_driver bcm2835_dma_driver = {
1043 .probe = bcm2835_dma_probe,
1044 .remove = bcm2835_dma_remove,
1045 .driver = {
1046 .name = "bcm2835-dma",
1047 .of_match_table = of_match_ptr(bcm2835_dma_of_match),
1048 },
1049};
1050
1051module_platform_driver(bcm2835_dma_driver);
1052
1053MODULE_ALIAS("platform:bcm2835-dma");
1054MODULE_DESCRIPTION("BCM2835 DMA engine driver");
1055MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1056MODULE_LICENSE("GPL v2");