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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell OcteonTx2 RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef MBOX_H
12#define MBOX_H
13
14#include <linux/etherdevice.h>
15#include <linux/sizes.h>
16
17#include "rvu_struct.h"
18#include "common.h"
19
20#define MBOX_SIZE SZ_64K
21
22/* AF/PF: PF initiated, PF/VF VF initiated */
23#define MBOX_DOWN_RX_START 0
24#define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26#define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27/* AF/PF: AF initiated, PF/VF PF initiated */
28#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29#define MBOX_UP_RX_SIZE SZ_1K
30#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31#define MBOX_UP_TX_SIZE SZ_1K
32
33#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34# error "incorrect mailbox area sizes"
35#endif
36
37#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38
39#define MBOX_RSP_TIMEOUT 2000 /* Time(ms) to wait for mbox response */
40
41#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
42
43/* Mailbox directions */
44#define MBOX_DIR_AFPF 0 /* AF replies to PF */
45#define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46#define MBOX_DIR_PFVF 2 /* PF replies to VF */
47#define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
52
53struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
55 spinlock_t mbox_lock;
56 u16 msg_size; /* Total msg size to be sent */
57 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
58 u16 num_msgs; /* No of msgs sent or waiting for response */
59 u16 msgs_acked; /* No of msgs for which response is received */
60};
61
62struct otx2_mbox {
63 struct pci_dev *pdev;
64 void *hwbase; /* Mbox region advertised by HW */
65 void *reg_base;/* CSR base for this dev */
66 u64 trigger; /* Trigger mbox notification */
67 u16 tr_shift; /* Mbox trigger shift */
68 u64 rx_start; /* Offset of Rx region in mbox memory */
69 u64 tx_start; /* Offset of Tx region in mbox memory */
70 u16 rx_size; /* Size of Rx region */
71 u16 tx_size; /* Size of Tx region */
72 u16 ndevs; /* The number of peers */
73 struct otx2_mbox_dev *dev;
74};
75
76/* Header which preceeds all mbox messages */
77struct mbox_hdr {
78 u64 msg_size; /* Total msgs size embedded */
79 u16 num_msgs; /* No of msgs embedded */
80};
81
82/* Header which preceeds every msg and is also part of it */
83struct mbox_msghdr {
84 u16 pcifunc; /* Who's sending this msg */
85 u16 id; /* Mbox message ID */
86#define OTX2_MBOX_REQ_SIG (0xdead)
87#define OTX2_MBOX_RSP_SIG (0xbeef)
88 u16 sig; /* Signature, for validating corrupted msgs */
89#define OTX2_MBOX_VERSION (0x0001)
90 u16 ver; /* Version of msg's structure for this ID */
91 u16 next_msgoff; /* Offset of next msg within mailbox region */
92 int rc; /* Msg process'ed response code */
93};
94
95void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
96void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
97void otx2_mbox_destroy(struct otx2_mbox *mbox);
98int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
99 struct pci_dev *pdev, void __force *reg_base,
100 int direction, int ndevs);
101void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
102int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
103int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
104struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
105 int size, int size_rsp);
106struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
107 struct mbox_msghdr *msg);
108int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
109int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
110 u16 pcifunc, u16 id);
111bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
112const char *otx2_mbox_id2name(u16 id);
113static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
114 int devid, int size)
115{
116 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
117}
118
119/* Mailbox message types */
120#define MBOX_MSG_MASK 0xFFFF
121#define MBOX_MSG_INVALID 0xFFFE
122#define MBOX_MSG_MAX 0xFFFF
123
124#define MBOX_MESSAGES \
125/* Generic mbox IDs (range 0x000 - 0x1FF) */ \
126M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
127M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
128M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
129M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
130M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
131M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
132/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
133M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
134M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
135M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
136M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
137 cgx_mac_addr_set_or_get) \
138M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
139 cgx_mac_addr_set_or_get) \
140M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
141M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
142M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
143M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
144M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
145M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
146M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
147M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
148 cgx_pause_frm_cfg) \
149/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
150M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
151 npa_lf_alloc_req, npa_lf_alloc_rsp) \
152M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
153M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
154M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
155/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
156/* TIM mbox IDs (range 0x800 - 0x9FF) */ \
157/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
158/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
159M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
160 npc_mcam_alloc_entry_rsp) \
161M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
162 npc_mcam_free_entry_req, msg_rsp) \
163M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
164 npc_mcam_write_entry_req, msg_rsp) \
165M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
166 npc_mcam_ena_dis_entry_req, msg_rsp) \
167M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
168 npc_mcam_ena_dis_entry_req, msg_rsp) \
169M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
170 npc_mcam_shift_entry_rsp) \
171M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
172 npc_mcam_alloc_counter_req, \
173 npc_mcam_alloc_counter_rsp) \
174M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
175 npc_mcam_oper_counter_req, msg_rsp) \
176M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
177 npc_mcam_unmap_counter_req, msg_rsp) \
178M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
179 npc_mcam_oper_counter_req, msg_rsp) \
180M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
181 npc_mcam_oper_counter_req, \
182 npc_mcam_oper_counter_rsp) \
183M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
184 npc_mcam_alloc_and_write_entry_req, \
185 npc_mcam_alloc_and_write_entry_rsp) \
186M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
187 msg_req, npc_get_kex_cfg_rsp) \
188/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
189M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
190 nix_lf_alloc_req, nix_lf_alloc_rsp) \
191M(NIX_LF_FREE, 0x8001, nix_lf_free, msg_req, msg_rsp) \
192M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
193M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
194 hwctx_disable_req, msg_rsp) \
195M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
196 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
197M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
198M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \
199M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
200M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
201M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
202 nix_rss_flowkey_cfg, \
203 nix_rss_flowkey_cfg_rsp) \
204M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
205M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
206M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
207M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
208M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
209M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
210 nix_mark_format_cfg, \
211 nix_mark_format_cfg_rsp) \
212M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
213M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
214 nix_lso_format_cfg, \
215 nix_lso_format_cfg_rsp) \
216M(NIX_RXVLAN_ALLOC, 0x8012, nix_rxvlan_alloc, msg_req, msg_rsp) \
217M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
218 nix_bp_cfg_rsp) \
219M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
220M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
221
222/* Messages initiated by AF (range 0xC00 - 0xDFF) */
223#define MBOX_UP_CGX_MESSAGES \
224M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
225
226enum {
227#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
228MBOX_MESSAGES
229MBOX_UP_CGX_MESSAGES
230#undef M
231};
232
233/* Mailbox message formats */
234
235#define RVU_DEFAULT_PF_FUNC 0xFFFF
236
237/* Generic request msg used for those mbox messages which
238 * don't send any data in the request.
239 */
240struct msg_req {
241 struct mbox_msghdr hdr;
242};
243
244/* Generic rsponse msg used a ack or response for those mbox
245 * messages which doesn't have a specific rsp msg format.
246 */
247struct msg_rsp {
248 struct mbox_msghdr hdr;
249};
250
251/* RVU mailbox error codes
252 * Range 256 - 300.
253 */
254enum rvu_af_status {
255 RVU_INVALID_VF_ID = -256,
256};
257
258struct ready_msg_rsp {
259 struct mbox_msghdr hdr;
260 u16 sclk_freq; /* SCLK frequency (in MHz) */
261 u16 rclk_freq; /* RCLK frequency (in MHz) */
262};
263
264/* Structure for requesting resource provisioning.
265 * 'modify' flag to be used when either requesting more
266 * or to detach partial of a cetain resource type.
267 * Rest of the fields specify how many of what type to
268 * be attached.
269 */
270struct rsrc_attach {
271 struct mbox_msghdr hdr;
272 u8 modify:1;
273 u8 npalf:1;
274 u8 nixlf:1;
275 u16 sso;
276 u16 ssow;
277 u16 timlfs;
278 u16 cptlfs;
279};
280
281/* Structure for relinquishing resources.
282 * 'partial' flag to be used when relinquishing all resources
283 * but only of a certain type. If not set, all resources of all
284 * types provisioned to the RVU function will be detached.
285 */
286struct rsrc_detach {
287 struct mbox_msghdr hdr;
288 u8 partial:1;
289 u8 npalf:1;
290 u8 nixlf:1;
291 u8 sso:1;
292 u8 ssow:1;
293 u8 timlfs:1;
294 u8 cptlfs:1;
295};
296
297#define MSIX_VECTOR_INVALID 0xFFFF
298#define MAX_RVU_BLKLF_CNT 256
299
300struct msix_offset_rsp {
301 struct mbox_msghdr hdr;
302 u16 npa_msixoff;
303 u16 nix_msixoff;
304 u8 sso;
305 u8 ssow;
306 u8 timlfs;
307 u8 cptlfs;
308 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
309 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
310 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
311 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
312};
313
314struct get_hw_cap_rsp {
315 struct mbox_msghdr hdr;
316 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
317 u8 nix_shaping; /* Is shaping and coloring supported */
318};
319
320/* CGX mbox message formats */
321
322struct cgx_stats_rsp {
323 struct mbox_msghdr hdr;
324#define CGX_RX_STATS_COUNT 13
325#define CGX_TX_STATS_COUNT 18
326 u64 rx_stats[CGX_RX_STATS_COUNT];
327 u64 tx_stats[CGX_TX_STATS_COUNT];
328};
329
330/* Structure for requesting the operation for
331 * setting/getting mac address in the CGX interface
332 */
333struct cgx_mac_addr_set_or_get {
334 struct mbox_msghdr hdr;
335 u8 mac_addr[ETH_ALEN];
336};
337
338struct cgx_link_user_info {
339 uint64_t link_up:1;
340 uint64_t full_duplex:1;
341 uint64_t lmac_type_id:4;
342 uint64_t speed:20; /* speed in Mbps */
343#define LMACTYPE_STR_LEN 16
344 char lmac_type[LMACTYPE_STR_LEN];
345};
346
347struct cgx_link_info_msg {
348 struct mbox_msghdr hdr;
349 struct cgx_link_user_info link_info;
350};
351
352struct cgx_pause_frm_cfg {
353 struct mbox_msghdr hdr;
354 u8 set;
355 /* set = 1 if the request is to config pause frames */
356 /* set = 0 if the request is to fetch pause frames config */
357 u8 rx_pause;
358 u8 tx_pause;
359};
360
361/* NPA mbox message formats */
362
363/* NPA mailbox error codes
364 * Range 301 - 400.
365 */
366enum npa_af_status {
367 NPA_AF_ERR_PARAM = -301,
368 NPA_AF_ERR_AQ_FULL = -302,
369 NPA_AF_ERR_AQ_ENQUEUE = -303,
370 NPA_AF_ERR_AF_LF_INVALID = -304,
371 NPA_AF_ERR_AF_LF_ALLOC = -305,
372 NPA_AF_ERR_LF_RESET = -306,
373};
374
375/* For NPA LF context alloc and init */
376struct npa_lf_alloc_req {
377 struct mbox_msghdr hdr;
378 int node;
379 int aura_sz; /* No of auras */
380 u32 nr_pools; /* No of pools */
381 u64 way_mask;
382};
383
384struct npa_lf_alloc_rsp {
385 struct mbox_msghdr hdr;
386 u32 stack_pg_ptrs; /* No of ptrs per stack page */
387 u32 stack_pg_bytes; /* Size of stack page */
388 u16 qints; /* NPA_AF_CONST::QINTS */
389};
390
391/* NPA AQ enqueue msg */
392struct npa_aq_enq_req {
393 struct mbox_msghdr hdr;
394 u32 aura_id;
395 u8 ctype;
396 u8 op;
397 union {
398 /* Valid when op == WRITE/INIT and ctype == AURA.
399 * LF fills the pool_id in aura.pool_addr. AF will translate
400 * the pool_id to pool context pointer.
401 */
402 struct npa_aura_s aura;
403 /* Valid when op == WRITE/INIT and ctype == POOL */
404 struct npa_pool_s pool;
405 };
406 /* Mask data when op == WRITE (1=write, 0=don't write) */
407 union {
408 /* Valid when op == WRITE and ctype == AURA */
409 struct npa_aura_s aura_mask;
410 /* Valid when op == WRITE and ctype == POOL */
411 struct npa_pool_s pool_mask;
412 };
413};
414
415struct npa_aq_enq_rsp {
416 struct mbox_msghdr hdr;
417 union {
418 /* Valid when op == READ and ctype == AURA */
419 struct npa_aura_s aura;
420 /* Valid when op == READ and ctype == POOL */
421 struct npa_pool_s pool;
422 };
423};
424
425/* Disable all contexts of type 'ctype' */
426struct hwctx_disable_req {
427 struct mbox_msghdr hdr;
428 u8 ctype;
429};
430
431/* NIX mbox message formats */
432
433/* NIX mailbox error codes
434 * Range 401 - 500.
435 */
436enum nix_af_status {
437 NIX_AF_ERR_PARAM = -401,
438 NIX_AF_ERR_AQ_FULL = -402,
439 NIX_AF_ERR_AQ_ENQUEUE = -403,
440 NIX_AF_ERR_AF_LF_INVALID = -404,
441 NIX_AF_ERR_AF_LF_ALLOC = -405,
442 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
443 NIX_AF_ERR_TLX_INVALID = -407,
444 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
445 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
446 NIX_AF_ERR_FRS_INVALID = -410,
447 NIX_AF_ERR_RX_LINK_INVALID = -411,
448 NIX_AF_INVAL_TXSCHQ_CFG = -412,
449 NIX_AF_SMQ_FLUSH_FAILED = -413,
450 NIX_AF_ERR_LF_RESET = -414,
451 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
452 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
453 NIX_AF_ERR_MARK_CFG_FAIL = -417,
454 NIX_AF_ERR_LSO_CFG_FAIL = -418,
455 NIX_AF_INVAL_NPA_PF_FUNC = -419,
456 NIX_AF_INVAL_SSO_PF_FUNC = -420,
457};
458
459/* For NIX LF context alloc and init */
460struct nix_lf_alloc_req {
461 struct mbox_msghdr hdr;
462 int node;
463 u32 rq_cnt; /* No of receive queues */
464 u32 sq_cnt; /* No of send queues */
465 u32 cq_cnt; /* No of completion queues */
466 u8 xqe_sz;
467 u16 rss_sz;
468 u8 rss_grps;
469 u16 npa_func;
470 u16 sso_func;
471 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
472 u64 way_mask;
473};
474
475struct nix_lf_alloc_rsp {
476 struct mbox_msghdr hdr;
477 u16 sqb_size;
478 u16 rx_chan_base;
479 u16 tx_chan_base;
480 u8 rx_chan_cnt; /* total number of RX channels */
481 u8 tx_chan_cnt; /* total number of TX channels */
482 u8 lso_tsov4_idx;
483 u8 lso_tsov6_idx;
484 u8 mac_addr[ETH_ALEN];
485 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
486 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
487 u16 cints; /* NIX_AF_CONST2::CINTS */
488 u16 qints; /* NIX_AF_CONST2::QINTS */
489};
490
491/* NIX AQ enqueue msg */
492struct nix_aq_enq_req {
493 struct mbox_msghdr hdr;
494 u32 qidx;
495 u8 ctype;
496 u8 op;
497 union {
498 struct nix_rq_ctx_s rq;
499 struct nix_sq_ctx_s sq;
500 struct nix_cq_ctx_s cq;
501 struct nix_rsse_s rss;
502 struct nix_rx_mce_s mce;
503 };
504 union {
505 struct nix_rq_ctx_s rq_mask;
506 struct nix_sq_ctx_s sq_mask;
507 struct nix_cq_ctx_s cq_mask;
508 struct nix_rsse_s rss_mask;
509 struct nix_rx_mce_s mce_mask;
510 };
511};
512
513struct nix_aq_enq_rsp {
514 struct mbox_msghdr hdr;
515 union {
516 struct nix_rq_ctx_s rq;
517 struct nix_sq_ctx_s sq;
518 struct nix_cq_ctx_s cq;
519 struct nix_rsse_s rss;
520 struct nix_rx_mce_s mce;
521 };
522};
523
524/* Tx scheduler/shaper mailbox messages */
525
526#define MAX_TXSCHQ_PER_FUNC 128
527
528struct nix_txsch_alloc_req {
529 struct mbox_msghdr hdr;
530 /* Scheduler queue count request at each level */
531 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
532 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
533};
534
535struct nix_txsch_alloc_rsp {
536 struct mbox_msghdr hdr;
537 /* Scheduler queue count allocated at each level */
538 u16 schq_contig[NIX_TXSCH_LVL_CNT];
539 u16 schq[NIX_TXSCH_LVL_CNT];
540 /* Scheduler queue list allocated at each level */
541 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
542 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
543 u8 aggr_level; /* Traffic aggregation scheduler level */
544 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
545 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
546};
547
548struct nix_txsch_free_req {
549 struct mbox_msghdr hdr;
550#define TXSCHQ_FREE_ALL BIT_ULL(0)
551 u16 flags;
552 /* Scheduler queue level to be freed */
553 u16 schq_lvl;
554 /* List of scheduler queues to be freed */
555 u16 schq;
556};
557
558struct nix_txschq_config {
559 struct mbox_msghdr hdr;
560 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
561#define TXSCHQ_IDX_SHIFT 16
562#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
563#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
564 u8 num_regs;
565#define MAX_REGS_PER_MBOX_MSG 20
566 u64 reg[MAX_REGS_PER_MBOX_MSG];
567 u64 regval[MAX_REGS_PER_MBOX_MSG];
568};
569
570struct nix_vtag_config {
571 struct mbox_msghdr hdr;
572 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
573 u8 vtag_size;
574 /* cfg_type is '0' for tx vlan cfg
575 * cfg_type is '1' for rx vlan cfg
576 */
577 u8 cfg_type;
578 union {
579 /* valid when cfg_type is '0' */
580 struct {
581 /* tx vlan0 tag(C-VLAN) */
582 u64 vlan0;
583 /* tx vlan1 tag(S-VLAN) */
584 u64 vlan1;
585 /* insert tx vlan tag */
586 u8 insert_vlan :1;
587 /* insert tx double vlan tag */
588 u8 double_vlan :1;
589 } tx;
590
591 /* valid when cfg_type is '1' */
592 struct {
593 /* rx vtag type index, valid values are in 0..7 range */
594 u8 vtag_type;
595 /* rx vtag strip */
596 u8 strip_vtag :1;
597 /* rx vtag capture */
598 u8 capture_vtag :1;
599 } rx;
600 };
601};
602
603struct nix_rss_flowkey_cfg {
604 struct mbox_msghdr hdr;
605 int mcam_index; /* MCAM entry index to modify */
606#define NIX_FLOW_KEY_TYPE_PORT BIT(0)
607#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
608#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
609#define NIX_FLOW_KEY_TYPE_TCP BIT(3)
610#define NIX_FLOW_KEY_TYPE_UDP BIT(4)
611#define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
612#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
613#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
614#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
615#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
616#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
617#define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
618#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
619#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
620#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
621#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
622#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
623#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
624 u32 flowkey_cfg; /* Flowkey types selected */
625 u8 group; /* RSS context or group */
626};
627
628struct nix_rss_flowkey_cfg_rsp {
629 struct mbox_msghdr hdr;
630 u8 alg_idx; /* Selected algo index */
631};
632
633struct nix_set_mac_addr {
634 struct mbox_msghdr hdr;
635 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
636};
637
638struct nix_get_mac_addr_rsp {
639 struct mbox_msghdr hdr;
640 u8 mac_addr[ETH_ALEN];
641};
642
643struct nix_mark_format_cfg {
644 struct mbox_msghdr hdr;
645 u8 offset;
646 u8 y_mask;
647 u8 y_val;
648 u8 r_mask;
649 u8 r_val;
650};
651
652struct nix_mark_format_cfg_rsp {
653 struct mbox_msghdr hdr;
654 u8 mark_format_idx;
655};
656
657struct nix_rx_mode {
658 struct mbox_msghdr hdr;
659#define NIX_RX_MODE_UCAST BIT(0)
660#define NIX_RX_MODE_PROMISC BIT(1)
661#define NIX_RX_MODE_ALLMULTI BIT(2)
662 u16 mode;
663};
664
665struct nix_rx_cfg {
666 struct mbox_msghdr hdr;
667#define NIX_RX_OL3_VERIFY BIT(0)
668#define NIX_RX_OL4_VERIFY BIT(1)
669 u8 len_verify; /* Outer L3/L4 len check */
670#define NIX_RX_CSUM_OL4_VERIFY BIT(0)
671 u8 csum_verify; /* Outer L4 checksum verification */
672};
673
674struct nix_frs_cfg {
675 struct mbox_msghdr hdr;
676 u8 update_smq; /* Update SMQ's min/max lens */
677 u8 update_minlen; /* Set minlen also */
678 u8 sdp_link; /* Set SDP RX link */
679 u16 maxlen;
680 u16 minlen;
681};
682
683struct nix_lso_format_cfg {
684 struct mbox_msghdr hdr;
685 u64 field_mask;
686#define NIX_LSO_FIELD_MAX 8
687 u64 fields[NIX_LSO_FIELD_MAX];
688};
689
690struct nix_lso_format_cfg_rsp {
691 struct mbox_msghdr hdr;
692 u8 lso_format_idx;
693};
694
695struct nix_bp_cfg_req {
696 struct mbox_msghdr hdr;
697 u16 chan_base; /* Starting channel number */
698 u8 chan_cnt; /* Number of channels */
699 u8 bpid_per_chan;
700 /* bpid_per_chan = 0 assigns single bp id for range of channels */
701 /* bpid_per_chan = 1 assigns separate bp id for each channel */
702};
703
704/* PF can be mapped to either CGX or LBK interface,
705 * so maximum 64 channels are possible.
706 */
707#define NIX_MAX_BPID_CHAN 64
708struct nix_bp_cfg_rsp {
709 struct mbox_msghdr hdr;
710 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
711 u8 chan_cnt; /* Number of channel for which bpids are assigned */
712};
713
714/* NPC mbox message structs */
715
716#define NPC_MCAM_ENTRY_INVALID 0xFFFF
717#define NPC_MCAM_INVALID_MAP 0xFFFF
718
719/* NPC mailbox error codes
720 * Range 701 - 800.
721 */
722enum npc_af_status {
723 NPC_MCAM_INVALID_REQ = -701,
724 NPC_MCAM_ALLOC_DENIED = -702,
725 NPC_MCAM_ALLOC_FAILED = -703,
726 NPC_MCAM_PERM_DENIED = -704,
727};
728
729struct npc_mcam_alloc_entry_req {
730 struct mbox_msghdr hdr;
731#define NPC_MAX_NONCONTIG_ENTRIES 256
732 u8 contig; /* Contiguous entries ? */
733#define NPC_MCAM_ANY_PRIO 0
734#define NPC_MCAM_LOWER_PRIO 1
735#define NPC_MCAM_HIGHER_PRIO 2
736 u8 priority; /* Lower or higher w.r.t ref_entry */
737 u16 ref_entry;
738 u16 count; /* Number of entries requested */
739};
740
741struct npc_mcam_alloc_entry_rsp {
742 struct mbox_msghdr hdr;
743 u16 entry; /* Entry allocated or start index if contiguous.
744 * Invalid incase of non-contiguous.
745 */
746 u16 count; /* Number of entries allocated */
747 u16 free_count; /* Number of entries available */
748 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
749};
750
751struct npc_mcam_free_entry_req {
752 struct mbox_msghdr hdr;
753 u16 entry; /* Entry index to be freed */
754 u8 all; /* If all entries allocated to this PFVF to be freed */
755};
756
757struct mcam_entry {
758#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
759 u64 kw[NPC_MAX_KWS_IN_KEY];
760 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
761 u64 action;
762 u64 vtag_action;
763};
764
765struct npc_mcam_write_entry_req {
766 struct mbox_msghdr hdr;
767 struct mcam_entry entry_data;
768 u16 entry; /* MCAM entry to write this match key */
769 u16 cntr; /* Counter for this MCAM entry */
770 u8 intf; /* Rx or Tx interface */
771 u8 enable_entry;/* Enable this MCAM entry ? */
772 u8 set_cntr; /* Set counter for this entry ? */
773};
774
775/* Enable/Disable a given entry */
776struct npc_mcam_ena_dis_entry_req {
777 struct mbox_msghdr hdr;
778 u16 entry;
779};
780
781struct npc_mcam_shift_entry_req {
782 struct mbox_msghdr hdr;
783#define NPC_MCAM_MAX_SHIFTS 64
784 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
785 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
786 u16 shift_count; /* Number of entries to shift */
787};
788
789struct npc_mcam_shift_entry_rsp {
790 struct mbox_msghdr hdr;
791 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
792};
793
794struct npc_mcam_alloc_counter_req {
795 struct mbox_msghdr hdr;
796 u8 contig; /* Contiguous counters ? */
797#define NPC_MAX_NONCONTIG_COUNTERS 64
798 u16 count; /* Number of counters requested */
799};
800
801struct npc_mcam_alloc_counter_rsp {
802 struct mbox_msghdr hdr;
803 u16 cntr; /* Counter allocated or start index if contiguous.
804 * Invalid incase of non-contiguous.
805 */
806 u16 count; /* Number of counters allocated */
807 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
808};
809
810struct npc_mcam_oper_counter_req {
811 struct mbox_msghdr hdr;
812 u16 cntr; /* Free a counter or clear/fetch it's stats */
813};
814
815struct npc_mcam_oper_counter_rsp {
816 struct mbox_msghdr hdr;
817 u64 stat; /* valid only while fetching counter's stats */
818};
819
820struct npc_mcam_unmap_counter_req {
821 struct mbox_msghdr hdr;
822 u16 cntr;
823 u16 entry; /* Entry and counter to be unmapped */
824 u8 all; /* Unmap all entries using this counter ? */
825};
826
827struct npc_mcam_alloc_and_write_entry_req {
828 struct mbox_msghdr hdr;
829 struct mcam_entry entry_data;
830 u16 ref_entry;
831 u8 priority; /* Lower or higher w.r.t ref_entry */
832 u8 intf; /* Rx or Tx interface */
833 u8 enable_entry;/* Enable this MCAM entry ? */
834 u8 alloc_cntr; /* Allocate counter and map ? */
835};
836
837struct npc_mcam_alloc_and_write_entry_rsp {
838 struct mbox_msghdr hdr;
839 u16 entry;
840 u16 cntr;
841};
842
843struct npc_get_kex_cfg_rsp {
844 struct mbox_msghdr hdr;
845 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
846 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
847#define NPC_MAX_INTF 2
848#define NPC_MAX_LID 8
849#define NPC_MAX_LT 16
850#define NPC_MAX_LD 2
851#define NPC_MAX_LFL 16
852 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
853 u64 kex_ld_flags[NPC_MAX_LD];
854 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
855 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
856 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
857 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
858#define MKEX_NAME_LEN 128
859 u8 mkex_pfl_name[MKEX_NAME_LEN];
860};
861
862#endif /* MBOX_H */