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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8#ifndef MBOX_H
9#define MBOX_H
10
11#include <linux/etherdevice.h>
12#include <linux/sizes.h>
13
14#include "rvu_struct.h"
15#include "common.h"
16
17#define MBOX_SIZE SZ_64K
18
19#define MBOX_DOWN_MSG 1
20#define MBOX_UP_MSG 2
21
22/* AF/PF: PF initiated, PF/VF VF initiated */
23#define MBOX_DOWN_RX_START 0
24#define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
25#define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
26#define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
27/* AF/PF: AF initiated, PF/VF PF initiated */
28#define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
29#define MBOX_UP_RX_SIZE SZ_1K
30#define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
31#define MBOX_UP_TX_SIZE SZ_1K
32
33#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
34# error "incorrect mailbox area sizes"
35#endif
36
37#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
38
39#define MBOX_RSP_TIMEOUT 6000 /* Time(ms) to wait for mbox response */
40
41#define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
42
43/* Mailbox directions */
44#define MBOX_DIR_AFPF 0 /* AF replies to PF */
45#define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
46#define MBOX_DIR_PFVF 2 /* PF replies to VF */
47#define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
48#define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
49#define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
50#define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
51#define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
52
53struct otx2_mbox_dev {
54 void *mbase; /* This dev's mbox region */
55 void *hwbase;
56 spinlock_t mbox_lock;
57 u16 msg_size; /* Total msg size to be sent */
58 u16 rsp_size; /* Total rsp size to be sure the reply is ok */
59 u16 num_msgs; /* No of msgs sent or waiting for response */
60 u16 msgs_acked; /* No of msgs for which response is received */
61};
62
63struct otx2_mbox {
64 struct pci_dev *pdev;
65 void *hwbase; /* Mbox region advertised by HW */
66 void *reg_base;/* CSR base for this dev */
67 u64 trigger; /* Trigger mbox notification */
68 u16 tr_shift; /* Mbox trigger shift */
69 u64 rx_start; /* Offset of Rx region in mbox memory */
70 u64 tx_start; /* Offset of Tx region in mbox memory */
71 u16 rx_size; /* Size of Rx region */
72 u16 tx_size; /* Size of Tx region */
73 u16 ndevs; /* The number of peers */
74 struct otx2_mbox_dev *dev;
75};
76
77/* Header which precedes all mbox messages */
78struct mbox_hdr {
79 u64 msg_size; /* Total msgs size embedded */
80 u16 num_msgs; /* No of msgs embedded */
81};
82
83/* Header which precedes every msg and is also part of it */
84struct mbox_msghdr {
85 u16 pcifunc; /* Who's sending this msg */
86 u16 id; /* Mbox message ID */
87#define OTX2_MBOX_REQ_SIG (0xdead)
88#define OTX2_MBOX_RSP_SIG (0xbeef)
89 u16 sig; /* Signature, for validating corrupted msgs */
90#define OTX2_MBOX_VERSION (0x000a)
91 u16 ver; /* Version of msg's structure for this ID */
92 u16 next_msgoff; /* Offset of next msg within mailbox region */
93 int rc; /* Msg process'ed response code */
94};
95
96void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
97void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
98void otx2_mbox_destroy(struct otx2_mbox *mbox);
99int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
100 struct pci_dev *pdev, void __force *reg_base,
101 int direction, int ndevs);
102
103int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
104 struct pci_dev *pdev, void __force *reg_base,
105 int direction, int ndevs, unsigned long *bmap);
106void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
107void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid);
108int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
109int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
110struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
111 int size, int size_rsp);
112struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
113 struct mbox_msghdr *msg);
114int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
115int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
116 u16 pcifunc, u16 id);
117bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
118const char *otx2_mbox_id2name(u16 id);
119static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
120 int devid, int size)
121{
122 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
123}
124
125bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid);
126
127/* Mailbox message types */
128#define MBOX_MSG_MASK 0xFFFF
129#define MBOX_MSG_INVALID 0xFFFE
130#define MBOX_MSG_MAX 0xFFFF
131
132#define MBOX_MESSAGES \
133/* Generic mbox IDs (range 0x000 - 0x1FF) */ \
134M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
135M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
136M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
137M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
138M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
139M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
140M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
141M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
142M(LMTST_TBL_SETUP, 0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req, \
143 msg_rsp) \
144M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
145M(PTP_GET_CAP, 0x00c, ptp_get_cap, msg_req, ptp_get_cap_rsp) \
146/* CGX mbox IDs (range 0x200 - 0x3FF) */ \
147M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
148M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
149M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
150M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get, \
151 cgx_mac_addr_set_or_get) \
152M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get, \
153 cgx_mac_addr_set_or_get) \
154M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
155M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
156M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
157M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
158M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
159M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
160M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
161M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
162M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
163M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
164 cgx_pause_frm_cfg) \
165M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
166M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
167M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
168 cgx_mac_addr_add_rsp) \
169M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
170 msg_rsp) \
171M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
172 cgx_max_dmac_entries_get_rsp) \
173M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
174M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
175 cgx_set_link_mode_rsp) \
176M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
177M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req, \
178 cgx_features_info_msg) \
179M(RPM_STATS, 0x21C, rpm_stats, msg_req, rpm_stats_rsp) \
180M(CGX_MAC_ADDR_RESET, 0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
181 msg_rsp) \
182M(CGX_MAC_ADDR_UPDATE, 0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
183 cgx_mac_addr_update_rsp) \
184M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg, \
185 cgx_pfc_rsp) \
186/* NPA mbox IDs (range 0x400 - 0x5FF) */ \
187M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, \
188 npa_lf_alloc_req, npa_lf_alloc_rsp) \
189M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
190M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp) \
191M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
192/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
193/* TIM mbox IDs (range 0x800 - 0x9FF) */ \
194/* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
195M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
196 msg_rsp) \
197M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
198M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
199 cpt_rd_wr_reg_msg) \
200M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
201 cpt_inline_ipsec_cfg_msg, msg_rsp) \
202M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
203M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
204 msg_rsp) \
205M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
206M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
207M(CPT_FLT_ENG_INFO, 0xA09, cpt_flt_eng_info, cpt_flt_eng_info_req, \
208 cpt_flt_eng_info_rsp) \
209/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
210M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
211M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
212/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
213M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
214 npc_mcam_alloc_entry_rsp) \
215M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
216 npc_mcam_free_entry_req, msg_rsp) \
217M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
218 npc_mcam_write_entry_req, msg_rsp) \
219M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
220 npc_mcam_ena_dis_entry_req, msg_rsp) \
221M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
222 npc_mcam_ena_dis_entry_req, msg_rsp) \
223M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
224 npc_mcam_shift_entry_rsp) \
225M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
226 npc_mcam_alloc_counter_req, \
227 npc_mcam_alloc_counter_rsp) \
228M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
229 npc_mcam_oper_counter_req, msg_rsp) \
230M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
231 npc_mcam_unmap_counter_req, msg_rsp) \
232M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
233 npc_mcam_oper_counter_req, msg_rsp) \
234M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
235 npc_mcam_oper_counter_req, \
236 npc_mcam_oper_counter_rsp) \
237M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry, \
238 npc_mcam_alloc_and_write_entry_req, \
239 npc_mcam_alloc_and_write_entry_rsp) \
240M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, \
241 msg_req, npc_get_kex_cfg_rsp) \
242M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
243 npc_install_flow_req, npc_install_flow_rsp) \
244M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
245 npc_delete_flow_req, npc_delete_flow_rsp) \
246M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
247 npc_mcam_read_entry_req, \
248 npc_mcam_read_entry_rsp) \
249M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
250 npc_set_pkind, msg_rsp) \
251M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, \
252 msg_req, npc_mcam_read_base_rule_rsp) \
253M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats, \
254 npc_mcam_get_stats_req, \
255 npc_mcam_get_stats_rsp) \
256M(NPC_GET_FIELD_HASH_INFO, 0x6013, npc_get_field_hash_info, \
257 npc_get_field_hash_info_req, \
258 npc_get_field_hash_info_rsp) \
259M(NPC_GET_FIELD_STATUS, 0x6014, npc_get_field_status, \
260 npc_get_field_status_req, \
261 npc_get_field_status_rsp) \
262/* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
263M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, \
264 nix_lf_alloc_req, nix_lf_alloc_rsp) \
265M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
266M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp) \
267M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, \
268 hwctx_disable_req, msg_rsp) \
269M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, \
270 nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
271M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
272M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
273 nix_txschq_config) \
274M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
275M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, \
276 nix_vtag_config_rsp) \
277M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
278 nix_rss_flowkey_cfg, \
279 nix_rss_flowkey_cfg_rsp) \
280M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
281M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
282M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
283M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
284M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
285M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
286 nix_mark_format_cfg, \
287 nix_mark_format_cfg_rsp) \
288M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
289M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, \
290 nix_lso_format_cfg, \
291 nix_lso_format_cfg_rsp) \
292M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
293M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
294M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
295 nix_bp_cfg_rsp) \
296M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
297M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
298M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
299 nix_inline_ipsec_cfg, msg_rsp) \
300M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg, \
301 nix_inline_ipsec_lf_cfg, msg_rsp) \
302M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
303 nix_cn10k_aq_enq_rsp) \
304M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \
305M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
306 nix_bandprof_alloc_rsp) \
307M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \
308 msg_rsp) \
309M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req, \
310 nix_bandprof_get_hwinfo_rsp) \
311M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
312 msg_req, nix_inline_ipsec_cfg) \
313M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
314 nix_mcast_grp_create_rsp) \
315M(NIX_MCAST_GRP_DESTROY, 0x802c, nix_mcast_grp_destroy, nix_mcast_grp_destroy_req, \
316 msg_rsp) \
317M(NIX_MCAST_GRP_UPDATE, 0x802d, nix_mcast_grp_update, \
318 nix_mcast_grp_update_req, \
319 nix_mcast_grp_update_rsp) \
320/* MCS mbox IDs (range 0xA000 - 0xBFFF) */ \
321M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \
322 mcs_alloc_rsrc_rsp) \
323M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
324M(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, mcs_flowid_entry_write_req, \
325 msg_rsp) \
326M(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, mcs_secy_plcy_write_req, \
327 msg_rsp) \
328M(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, mcs_rx_sc_cam_write_req, \
329 msg_rsp) \
330M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, \
331 msg_rsp) \
332M(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, mcs_tx_sc_sa_map, \
333 msg_rsp) \
334M(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, mcs_rx_sc_sa_map, \
335 msg_rsp) \
336M(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, mcs_flowid_ena_dis_entry, \
337 msg_rsp) \
338M(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, mcs_pn_table_write_req, \
339 msg_rsp) \
340M(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, mcs_set_active_lmac, \
341 msg_rsp) \
342M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \
343M(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \
344 mcs_flowid_stats) \
345M(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \
346 mcs_secy_stats) \
347M(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, mcs_sc_stats) \
348M(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, mcs_sa_stats) \
349M(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \
350 mcs_port_stats) \
351M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
352M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
353M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
354M(MCS_SET_PN_THRESHOLD, 0xa014, mcs_set_pn_threshold, mcs_set_pn_threshold, \
355 msg_rsp) \
356M(MCS_ALLOC_CTRL_PKT_RULE, 0xa015, mcs_alloc_ctrl_pkt_rule, \
357 mcs_alloc_ctrl_pkt_rule_req, \
358 mcs_alloc_ctrl_pkt_rule_rsp) \
359M(MCS_FREE_CTRL_PKT_RULE, 0xa016, mcs_free_ctrl_pkt_rule, \
360 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
361M(MCS_CTRL_PKT_RULE_WRITE, 0xa017, mcs_ctrl_pkt_rule_write, \
362 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
363M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
364M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
365M(MCS_PORT_CFG_GET, 0xa020, mcs_port_cfg_get, mcs_port_cfg_get_req, \
366 mcs_port_cfg_get_rsp) \
367M(MCS_CUSTOM_TAG_CFG_GET, 0xa021, mcs_custom_tag_cfg_get, \
368 mcs_custom_tag_cfg_get_req, \
369 mcs_custom_tag_cfg_get_rsp)
370
371/* Messages initiated by AF (range 0xC00 - 0xEFF) */
372#define MBOX_UP_CGX_MESSAGES \
373M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
374
375#define MBOX_UP_CPT_MESSAGES \
376M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
377
378#define MBOX_UP_MCS_MESSAGES \
379M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
380
381enum {
382#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
383MBOX_MESSAGES
384MBOX_UP_CGX_MESSAGES
385MBOX_UP_CPT_MESSAGES
386MBOX_UP_MCS_MESSAGES
387#undef M
388};
389
390/* Mailbox message formats */
391
392#define RVU_DEFAULT_PF_FUNC 0xFFFF
393
394/* Generic request msg used for those mbox messages which
395 * don't send any data in the request.
396 */
397struct msg_req {
398 struct mbox_msghdr hdr;
399};
400
401/* Generic response msg used an ack or response for those mbox
402 * messages which don't have a specific rsp msg format.
403 */
404struct msg_rsp {
405 struct mbox_msghdr hdr;
406};
407
408/* RVU mailbox error codes
409 * Range 256 - 300.
410 */
411enum rvu_af_status {
412 RVU_INVALID_VF_ID = -256,
413};
414
415struct ready_msg_rsp {
416 struct mbox_msghdr hdr;
417 u16 sclk_freq; /* SCLK frequency (in MHz) */
418 u16 rclk_freq; /* RCLK frequency (in MHz) */
419};
420
421/* Structure for requesting resource provisioning.
422 * 'modify' flag to be used when either requesting more
423 * or to detach partial of a certain resource type.
424 * Rest of the fields specify how many of what type to
425 * be attached.
426 * To request LFs from two blocks of same type this mailbox
427 * can be sent twice as below:
428 * struct rsrc_attach *attach;
429 * .. Allocate memory for message ..
430 * attach->cptlfs = 3; <3 LFs from CPT0>
431 * .. Send message ..
432 * .. Allocate memory for message ..
433 * attach->modify = 1;
434 * attach->cpt_blkaddr = BLKADDR_CPT1;
435 * attach->cptlfs = 2; <2 LFs from CPT1>
436 * .. Send message ..
437 */
438struct rsrc_attach {
439 struct mbox_msghdr hdr;
440 u8 modify:1;
441 u8 npalf:1;
442 u8 nixlf:1;
443 u16 sso;
444 u16 ssow;
445 u16 timlfs;
446 u16 cptlfs;
447 int cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
448};
449
450/* Structure for relinquishing resources.
451 * 'partial' flag to be used when relinquishing all resources
452 * but only of a certain type. If not set, all resources of all
453 * types provisioned to the RVU function will be detached.
454 */
455struct rsrc_detach {
456 struct mbox_msghdr hdr;
457 u8 partial:1;
458 u8 npalf:1;
459 u8 nixlf:1;
460 u8 sso:1;
461 u8 ssow:1;
462 u8 timlfs:1;
463 u8 cptlfs:1;
464};
465
466/* Number of resources available to the caller.
467 * In reply to MBOX_MSG_FREE_RSRC_CNT.
468 */
469struct free_rsrcs_rsp {
470 struct mbox_msghdr hdr;
471 u16 schq[NIX_TXSCH_LVL_CNT];
472 u16 sso;
473 u16 tim;
474 u16 ssow;
475 u16 cpt;
476 u8 npa;
477 u8 nix;
478 u16 schq_nix1[NIX_TXSCH_LVL_CNT];
479 u8 nix1;
480 u8 cpt1;
481 u8 ree0;
482 u8 ree1;
483};
484
485#define MSIX_VECTOR_INVALID 0xFFFF
486#define MAX_RVU_BLKLF_CNT 256
487
488struct msix_offset_rsp {
489 struct mbox_msghdr hdr;
490 u16 npa_msixoff;
491 u16 nix_msixoff;
492 u16 sso;
493 u16 ssow;
494 u16 timlfs;
495 u16 cptlfs;
496 u16 sso_msixoff[MAX_RVU_BLKLF_CNT];
497 u16 ssow_msixoff[MAX_RVU_BLKLF_CNT];
498 u16 timlf_msixoff[MAX_RVU_BLKLF_CNT];
499 u16 cptlf_msixoff[MAX_RVU_BLKLF_CNT];
500 u16 cpt1_lfs;
501 u16 ree0_lfs;
502 u16 ree1_lfs;
503 u16 cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
504 u16 ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
505 u16 ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
506};
507
508struct get_hw_cap_rsp {
509 struct mbox_msghdr hdr;
510 u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
511 u8 nix_shaping; /* Is shaping and coloring supported */
512 u8 npc_hash_extract; /* Is hash extract supported */
513};
514
515/* CGX mbox message formats */
516
517struct cgx_stats_rsp {
518 struct mbox_msghdr hdr;
519#define CGX_RX_STATS_COUNT 9
520#define CGX_TX_STATS_COUNT 18
521 u64 rx_stats[CGX_RX_STATS_COUNT];
522 u64 tx_stats[CGX_TX_STATS_COUNT];
523};
524
525struct cgx_fec_stats_rsp {
526 struct mbox_msghdr hdr;
527 u64 fec_corr_blks;
528 u64 fec_uncorr_blks;
529};
530/* Structure for requesting the operation for
531 * setting/getting mac address in the CGX interface
532 */
533struct cgx_mac_addr_set_or_get {
534 struct mbox_msghdr hdr;
535 u8 mac_addr[ETH_ALEN];
536 u32 index;
537};
538
539/* Structure for requesting the operation to
540 * add DMAC filter entry into CGX interface
541 */
542struct cgx_mac_addr_add_req {
543 struct mbox_msghdr hdr;
544 u8 mac_addr[ETH_ALEN];
545};
546
547/* Structure for response against the operation to
548 * add DMAC filter entry into CGX interface
549 */
550struct cgx_mac_addr_add_rsp {
551 struct mbox_msghdr hdr;
552 u32 index;
553};
554
555/* Structure for requesting the operation to
556 * delete DMAC filter entry from CGX interface
557 */
558struct cgx_mac_addr_del_req {
559 struct mbox_msghdr hdr;
560 u32 index;
561};
562
563/* Structure for response against the operation to
564 * get maximum supported DMAC filter entries
565 */
566struct cgx_max_dmac_entries_get_rsp {
567 struct mbox_msghdr hdr;
568 u32 max_dmac_filters;
569};
570
571struct cgx_link_user_info {
572 uint64_t link_up:1;
573 uint64_t full_duplex:1;
574 uint64_t lmac_type_id:4;
575 uint64_t speed:20; /* speed in Mbps */
576 uint64_t an:1; /* AN supported or not */
577 uint64_t fec:2; /* FEC type if enabled else 0 */
578#define LMACTYPE_STR_LEN 16
579 char lmac_type[LMACTYPE_STR_LEN];
580};
581
582struct cgx_link_info_msg {
583 struct mbox_msghdr hdr;
584 struct cgx_link_user_info link_info;
585};
586
587struct cgx_pause_frm_cfg {
588 struct mbox_msghdr hdr;
589 u8 set;
590 /* set = 1 if the request is to config pause frames */
591 /* set = 0 if the request is to fetch pause frames config */
592 u8 rx_pause;
593 u8 tx_pause;
594};
595
596enum fec_type {
597 OTX2_FEC_NONE,
598 OTX2_FEC_BASER,
599 OTX2_FEC_RS,
600 OTX2_FEC_STATS_CNT = 2,
601 OTX2_FEC_OFF,
602};
603
604struct fec_mode {
605 struct mbox_msghdr hdr;
606 int fec;
607};
608
609struct sfp_eeprom_s {
610#define SFP_EEPROM_SIZE 256
611 u16 sff_id;
612 u8 buf[SFP_EEPROM_SIZE];
613 u64 reserved;
614};
615
616struct phy_s {
617 struct {
618 u64 can_change_mod_type:1;
619 u64 mod_type:1;
620 u64 has_fec_stats:1;
621 } misc;
622 struct fec_stats_s {
623 u32 rsfec_corr_cws;
624 u32 rsfec_uncorr_cws;
625 u32 brfec_corr_blks;
626 u32 brfec_uncorr_blks;
627 } fec_stats;
628};
629
630struct cgx_lmac_fwdata_s {
631 u16 rw_valid;
632 u64 supported_fec;
633 u64 supported_an;
634 u64 supported_link_modes;
635 /* only applicable if AN is supported */
636 u64 advertised_fec;
637 u64 advertised_link_modes;
638 /* Only applicable if SFP/QSFP slot is present */
639 struct sfp_eeprom_s sfp_eeprom;
640 struct phy_s phy;
641#define LMAC_FWDATA_RESERVED_MEM 1021
642 u64 reserved[LMAC_FWDATA_RESERVED_MEM];
643};
644
645struct cgx_fw_data {
646 struct mbox_msghdr hdr;
647 struct cgx_lmac_fwdata_s fwdata;
648};
649
650struct cgx_set_link_mode_args {
651 u32 speed;
652 u8 duplex;
653 u8 an;
654 u8 ports;
655 u64 mode;
656};
657
658struct cgx_set_link_mode_req {
659#define AUTONEG_UNKNOWN 0xff
660 struct mbox_msghdr hdr;
661 struct cgx_set_link_mode_args args;
662};
663
664struct cgx_set_link_mode_rsp {
665 struct mbox_msghdr hdr;
666 int status;
667};
668
669struct cgx_mac_addr_reset_req {
670 struct mbox_msghdr hdr;
671 u32 index;
672};
673
674struct cgx_mac_addr_update_req {
675 struct mbox_msghdr hdr;
676 u8 mac_addr[ETH_ALEN];
677 u32 index;
678};
679
680struct cgx_mac_addr_update_rsp {
681 struct mbox_msghdr hdr;
682 u32 index;
683};
684
685#define RVU_LMAC_FEAT_FC BIT_ULL(0) /* pause frames */
686#define RVU_LMAC_FEAT_HIGIG2 BIT_ULL(1)
687 /* flow control from physical link higig2 messages */
688#define RVU_LMAC_FEAT_PTP BIT_ULL(2) /* precison time protocol */
689#define RVU_LMAC_FEAT_DMACF BIT_ULL(3) /* DMAC FILTER */
690#define RVU_MAC_VERSION BIT_ULL(4)
691#define RVU_MAC_CGX BIT_ULL(5)
692#define RVU_MAC_RPM BIT_ULL(6)
693
694struct cgx_features_info_msg {
695 struct mbox_msghdr hdr;
696 u64 lmac_features;
697};
698
699struct rpm_stats_rsp {
700 struct mbox_msghdr hdr;
701#define RPM_RX_STATS_COUNT 43
702#define RPM_TX_STATS_COUNT 34
703 u64 rx_stats[RPM_RX_STATS_COUNT];
704 u64 tx_stats[RPM_TX_STATS_COUNT];
705};
706
707struct cgx_pfc_cfg {
708 struct mbox_msghdr hdr;
709 u8 rx_pause;
710 u8 tx_pause;
711 u16 pfc_en; /* bitmap indicating pfc enabled traffic classes */
712};
713
714struct cgx_pfc_rsp {
715 struct mbox_msghdr hdr;
716 u8 rx_pause;
717 u8 tx_pause;
718};
719
720 /* NPA mbox message formats */
721
722struct npc_set_pkind {
723 struct mbox_msghdr hdr;
724#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
725#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
726 u64 mode;
727#define PKIND_TX BIT_ULL(0)
728#define PKIND_RX BIT_ULL(1)
729 u8 dir;
730 u8 pkind; /* valid only in case custom flag */
731 u8 var_len_off; /* Offset of custom header length field.
732 * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
733 */
734 u8 var_len_off_mask; /* Mask for length with in offset */
735 u8 shift_dir; /* shift direction to get length of the header at var_len_off */
736};
737
738/* NPA mbox message formats */
739
740/* NPA mailbox error codes
741 * Range 301 - 400.
742 */
743enum npa_af_status {
744 NPA_AF_ERR_PARAM = -301,
745 NPA_AF_ERR_AQ_FULL = -302,
746 NPA_AF_ERR_AQ_ENQUEUE = -303,
747 NPA_AF_ERR_AF_LF_INVALID = -304,
748 NPA_AF_ERR_AF_LF_ALLOC = -305,
749 NPA_AF_ERR_LF_RESET = -306,
750};
751
752/* For NPA LF context alloc and init */
753struct npa_lf_alloc_req {
754 struct mbox_msghdr hdr;
755 int node;
756 int aura_sz; /* No of auras */
757 u32 nr_pools; /* No of pools */
758 u64 way_mask;
759};
760
761struct npa_lf_alloc_rsp {
762 struct mbox_msghdr hdr;
763 u32 stack_pg_ptrs; /* No of ptrs per stack page */
764 u32 stack_pg_bytes; /* Size of stack page */
765 u16 qints; /* NPA_AF_CONST::QINTS */
766 u8 cache_lines; /*BATCH ALLOC DMA */
767};
768
769/* NPA AQ enqueue msg */
770struct npa_aq_enq_req {
771 struct mbox_msghdr hdr;
772 u32 aura_id;
773 u8 ctype;
774 u8 op;
775 union {
776 /* Valid when op == WRITE/INIT and ctype == AURA.
777 * LF fills the pool_id in aura.pool_addr. AF will translate
778 * the pool_id to pool context pointer.
779 */
780 struct npa_aura_s aura;
781 /* Valid when op == WRITE/INIT and ctype == POOL */
782 struct npa_pool_s pool;
783 };
784 /* Mask data when op == WRITE (1=write, 0=don't write) */
785 union {
786 /* Valid when op == WRITE and ctype == AURA */
787 struct npa_aura_s aura_mask;
788 /* Valid when op == WRITE and ctype == POOL */
789 struct npa_pool_s pool_mask;
790 };
791};
792
793struct npa_aq_enq_rsp {
794 struct mbox_msghdr hdr;
795 union {
796 /* Valid when op == READ and ctype == AURA */
797 struct npa_aura_s aura;
798 /* Valid when op == READ and ctype == POOL */
799 struct npa_pool_s pool;
800 };
801};
802
803/* Disable all contexts of type 'ctype' */
804struct hwctx_disable_req {
805 struct mbox_msghdr hdr;
806 u8 ctype;
807};
808
809/* NIX mbox message formats */
810
811/* NIX mailbox error codes
812 * Range 401 - 500.
813 */
814enum nix_af_status {
815 NIX_AF_ERR_PARAM = -401,
816 NIX_AF_ERR_AQ_FULL = -402,
817 NIX_AF_ERR_AQ_ENQUEUE = -403,
818 NIX_AF_ERR_AF_LF_INVALID = -404,
819 NIX_AF_ERR_AF_LF_ALLOC = -405,
820 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
821 NIX_AF_ERR_TLX_INVALID = -407,
822 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
823 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
824 NIX_AF_ERR_FRS_INVALID = -410,
825 NIX_AF_ERR_RX_LINK_INVALID = -411,
826 NIX_AF_INVAL_TXSCHQ_CFG = -412,
827 NIX_AF_SMQ_FLUSH_FAILED = -413,
828 NIX_AF_ERR_LF_RESET = -414,
829 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
830 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
831 NIX_AF_ERR_MARK_CFG_FAIL = -417,
832 NIX_AF_ERR_LSO_CFG_FAIL = -418,
833 NIX_AF_INVAL_NPA_PF_FUNC = -419,
834 NIX_AF_INVAL_SSO_PF_FUNC = -420,
835 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
836 NIX_AF_ERR_RX_VTAG_INUSE = -422,
837 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
838 NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
839 NIX_AF_ERR_INVALID_NIXBLK = -425,
840 NIX_AF_ERR_INVALID_BANDPROF = -426,
841 NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
842 NIX_AF_ERR_BANDPROF_INVAL_REQ = -428,
843 NIX_AF_ERR_CQ_CTX_WRITE_ERR = -429,
844 NIX_AF_ERR_AQ_CTX_RETRY_WRITE = -430,
845 NIX_AF_ERR_LINK_CREDITS = -431,
846 NIX_AF_ERR_INVALID_BPID = -434,
847 NIX_AF_ERR_INVALID_BPID_REQ = -435,
848 NIX_AF_ERR_INVALID_MCAST_GRP = -436,
849 NIX_AF_ERR_INVALID_MCAST_DEL_REQ = -437,
850 NIX_AF_ERR_NON_CONTIG_MCE_LIST = -438,
851};
852
853/* For NIX RX vtag action */
854enum nix_rx_vtag0_type {
855 NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
856 NIX_AF_LFX_RX_VTAG_TYPE1,
857 NIX_AF_LFX_RX_VTAG_TYPE2,
858 NIX_AF_LFX_RX_VTAG_TYPE3,
859 NIX_AF_LFX_RX_VTAG_TYPE4,
860 NIX_AF_LFX_RX_VTAG_TYPE5,
861 NIX_AF_LFX_RX_VTAG_TYPE6,
862 NIX_AF_LFX_RX_VTAG_TYPE7,
863};
864
865/* For NIX LF context alloc and init */
866struct nix_lf_alloc_req {
867 struct mbox_msghdr hdr;
868 int node;
869 u32 rq_cnt; /* No of receive queues */
870 u32 sq_cnt; /* No of send queues */
871 u32 cq_cnt; /* No of completion queues */
872 u8 xqe_sz;
873 u16 rss_sz;
874 u8 rss_grps;
875 u16 npa_func;
876 u16 sso_func;
877 u64 rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
878 u64 way_mask;
879#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
880#define NIX_LF_LBK_BLK_SEL BIT_ULL(1)
881 u64 flags;
882};
883
884struct nix_lf_alloc_rsp {
885 struct mbox_msghdr hdr;
886 u16 sqb_size;
887 u16 rx_chan_base;
888 u16 tx_chan_base;
889 u8 rx_chan_cnt; /* total number of RX channels */
890 u8 tx_chan_cnt; /* total number of TX channels */
891 u8 lso_tsov4_idx;
892 u8 lso_tsov6_idx;
893 u8 mac_addr[ETH_ALEN];
894 u8 lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
895 u8 lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
896 u16 cints; /* NIX_AF_CONST2::CINTS */
897 u16 qints; /* NIX_AF_CONST2::QINTS */
898 u8 cgx_links; /* No. of CGX links present in HW */
899 u8 lbk_links; /* No. of LBK links present in HW */
900 u8 sdp_links; /* No. of SDP links present in HW */
901 u8 tx_link; /* Transmit channel link number */
902};
903
904struct nix_lf_free_req {
905 struct mbox_msghdr hdr;
906#define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
907#define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
908 u64 flags;
909};
910
911/* CN10K NIX AQ enqueue msg */
912struct nix_cn10k_aq_enq_req {
913 struct mbox_msghdr hdr;
914 u32 qidx;
915 u8 ctype;
916 u8 op;
917 union {
918 struct nix_cn10k_rq_ctx_s rq;
919 struct nix_cn10k_sq_ctx_s sq;
920 struct nix_cq_ctx_s cq;
921 struct nix_rsse_s rss;
922 struct nix_rx_mce_s mce;
923 struct nix_bandprof_s prof;
924 };
925 union {
926 struct nix_cn10k_rq_ctx_s rq_mask;
927 struct nix_cn10k_sq_ctx_s sq_mask;
928 struct nix_cq_ctx_s cq_mask;
929 struct nix_rsse_s rss_mask;
930 struct nix_rx_mce_s mce_mask;
931 struct nix_bandprof_s prof_mask;
932 };
933};
934
935struct nix_cn10k_aq_enq_rsp {
936 struct mbox_msghdr hdr;
937 union {
938 struct nix_cn10k_rq_ctx_s rq;
939 struct nix_cn10k_sq_ctx_s sq;
940 struct nix_cq_ctx_s cq;
941 struct nix_rsse_s rss;
942 struct nix_rx_mce_s mce;
943 struct nix_bandprof_s prof;
944 };
945};
946
947/* NIX AQ enqueue msg */
948struct nix_aq_enq_req {
949 struct mbox_msghdr hdr;
950 u32 qidx;
951 u8 ctype;
952 u8 op;
953 union {
954 struct nix_rq_ctx_s rq;
955 struct nix_sq_ctx_s sq;
956 struct nix_cq_ctx_s cq;
957 struct nix_rsse_s rss;
958 struct nix_rx_mce_s mce;
959 struct nix_bandprof_s prof;
960 };
961 union {
962 struct nix_rq_ctx_s rq_mask;
963 struct nix_sq_ctx_s sq_mask;
964 struct nix_cq_ctx_s cq_mask;
965 struct nix_rsse_s rss_mask;
966 struct nix_rx_mce_s mce_mask;
967 struct nix_bandprof_s prof_mask;
968 };
969};
970
971struct nix_aq_enq_rsp {
972 struct mbox_msghdr hdr;
973 union {
974 struct nix_rq_ctx_s rq;
975 struct nix_sq_ctx_s sq;
976 struct nix_cq_ctx_s cq;
977 struct nix_rsse_s rss;
978 struct nix_rx_mce_s mce;
979 struct nix_bandprof_s prof;
980 };
981};
982
983/* Tx scheduler/shaper mailbox messages */
984
985#define MAX_TXSCHQ_PER_FUNC 128
986
987struct nix_txsch_alloc_req {
988 struct mbox_msghdr hdr;
989 /* Scheduler queue count request at each level */
990 u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
991 u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
992};
993
994struct nix_txsch_alloc_rsp {
995 struct mbox_msghdr hdr;
996 /* Scheduler queue count allocated at each level */
997 u16 schq_contig[NIX_TXSCH_LVL_CNT];
998 u16 schq[NIX_TXSCH_LVL_CNT];
999 /* Scheduler queue list allocated at each level */
1000 u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1001 u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
1002 u8 aggr_level; /* Traffic aggregation scheduler level */
1003 u8 aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
1004 u8 link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
1005};
1006
1007struct nix_txsch_free_req {
1008 struct mbox_msghdr hdr;
1009#define TXSCHQ_FREE_ALL BIT_ULL(0)
1010 u16 flags;
1011 /* Scheduler queue level to be freed */
1012 u16 schq_lvl;
1013 /* List of scheduler queues to be freed */
1014 u16 schq;
1015};
1016
1017struct nix_txschq_config {
1018 struct mbox_msghdr hdr;
1019 u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
1020 u8 read;
1021#define TXSCHQ_IDX_SHIFT 16
1022#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
1023#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
1024 u8 num_regs;
1025#define MAX_REGS_PER_MBOX_MSG 20
1026 u64 reg[MAX_REGS_PER_MBOX_MSG];
1027 u64 regval[MAX_REGS_PER_MBOX_MSG];
1028 /* All 0's => overwrite with new value */
1029 u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
1030};
1031
1032struct nix_vtag_config {
1033 struct mbox_msghdr hdr;
1034 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
1035 u8 vtag_size;
1036 /* cfg_type is '0' for tx vlan cfg
1037 * cfg_type is '1' for rx vlan cfg
1038 */
1039 u8 cfg_type;
1040 union {
1041 /* valid when cfg_type is '0' */
1042 struct {
1043 u64 vtag0;
1044 u64 vtag1;
1045
1046 /* cfg_vtag0 & cfg_vtag1 fields are valid
1047 * when free_vtag0 & free_vtag1 are '0's.
1048 */
1049 /* cfg_vtag0 = 1 to configure vtag0 */
1050 u8 cfg_vtag0 :1;
1051 /* cfg_vtag1 = 1 to configure vtag1 */
1052 u8 cfg_vtag1 :1;
1053
1054 /* vtag0_idx & vtag1_idx are only valid when
1055 * both cfg_vtag0 & cfg_vtag1 are '0's,
1056 * these fields are used along with free_vtag0
1057 * & free_vtag1 to free the nix lf's tx_vlan
1058 * configuration.
1059 *
1060 * Denotes the indices of tx_vtag def registers
1061 * that needs to be cleared and freed.
1062 */
1063 int vtag0_idx;
1064 int vtag1_idx;
1065
1066 /* free_vtag0 & free_vtag1 fields are valid
1067 * when cfg_vtag0 & cfg_vtag1 are '0's.
1068 */
1069 /* free_vtag0 = 1 clears vtag0 configuration
1070 * vtag0_idx denotes the index to be cleared.
1071 */
1072 u8 free_vtag0 :1;
1073 /* free_vtag1 = 1 clears vtag1 configuration
1074 * vtag1_idx denotes the index to be cleared.
1075 */
1076 u8 free_vtag1 :1;
1077 } tx;
1078
1079 /* valid when cfg_type is '1' */
1080 struct {
1081 /* rx vtag type index, valid values are in 0..7 range */
1082 u8 vtag_type;
1083 /* rx vtag strip */
1084 u8 strip_vtag :1;
1085 /* rx vtag capture */
1086 u8 capture_vtag :1;
1087 } rx;
1088 };
1089};
1090
1091struct nix_vtag_config_rsp {
1092 struct mbox_msghdr hdr;
1093 int vtag0_idx;
1094 int vtag1_idx;
1095 /* Indices of tx_vtag def registers used to configure
1096 * tx vtag0 & vtag1 headers, these indices are valid
1097 * when nix_vtag_config mbox requested for vtag0 and/
1098 * or vtag1 configuration.
1099 */
1100};
1101
1102#define NIX_FLOW_KEY_TYPE_L3_L4_MASK (~(0xf << 28))
1103
1104struct nix_rss_flowkey_cfg {
1105 struct mbox_msghdr hdr;
1106 int mcam_index; /* MCAM entry index to modify */
1107#define NIX_FLOW_KEY_TYPE_PORT BIT(0)
1108#define NIX_FLOW_KEY_TYPE_IPV4 BIT(1)
1109#define NIX_FLOW_KEY_TYPE_IPV6 BIT(2)
1110#define NIX_FLOW_KEY_TYPE_TCP BIT(3)
1111#define NIX_FLOW_KEY_TYPE_UDP BIT(4)
1112#define NIX_FLOW_KEY_TYPE_SCTP BIT(5)
1113#define NIX_FLOW_KEY_TYPE_NVGRE BIT(6)
1114#define NIX_FLOW_KEY_TYPE_VXLAN BIT(7)
1115#define NIX_FLOW_KEY_TYPE_GENEVE BIT(8)
1116#define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1117#define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1118#define NIX_FLOW_KEY_TYPE_GTPU BIT(11)
1119#define NIX_FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
1120#define NIX_FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
1121#define NIX_FLOW_KEY_TYPE_INNR_TCP BIT(14)
1122#define NIX_FLOW_KEY_TYPE_INNR_UDP BIT(15)
1123#define NIX_FLOW_KEY_TYPE_INNR_SCTP BIT(16)
1124#define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1125#define NIX_FLOW_KEY_TYPE_CUSTOM0 BIT(19)
1126#define NIX_FLOW_KEY_TYPE_VLAN BIT(20)
1127#define NIX_FLOW_KEY_TYPE_IPV4_PROTO BIT(21)
1128#define NIX_FLOW_KEY_TYPE_AH BIT(22)
1129#define NIX_FLOW_KEY_TYPE_ESP BIT(23)
1130#define NIX_FLOW_KEY_TYPE_L4_DST_ONLY BIT(28)
1131#define NIX_FLOW_KEY_TYPE_L4_SRC_ONLY BIT(29)
1132#define NIX_FLOW_KEY_TYPE_L3_DST_ONLY BIT(30)
1133#define NIX_FLOW_KEY_TYPE_L3_SRC_ONLY BIT(31)
1134 u32 flowkey_cfg; /* Flowkey types selected */
1135 u8 group; /* RSS context or group */
1136};
1137
1138struct nix_rss_flowkey_cfg_rsp {
1139 struct mbox_msghdr hdr;
1140 u8 alg_idx; /* Selected algo index */
1141};
1142
1143struct nix_set_mac_addr {
1144 struct mbox_msghdr hdr;
1145 u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1146};
1147
1148struct nix_get_mac_addr_rsp {
1149 struct mbox_msghdr hdr;
1150 u8 mac_addr[ETH_ALEN];
1151};
1152
1153struct nix_mark_format_cfg {
1154 struct mbox_msghdr hdr;
1155 u8 offset;
1156 u8 y_mask;
1157 u8 y_val;
1158 u8 r_mask;
1159 u8 r_val;
1160};
1161
1162struct nix_mark_format_cfg_rsp {
1163 struct mbox_msghdr hdr;
1164 u8 mark_format_idx;
1165};
1166
1167struct nix_rx_mode {
1168 struct mbox_msghdr hdr;
1169#define NIX_RX_MODE_UCAST BIT(0)
1170#define NIX_RX_MODE_PROMISC BIT(1)
1171#define NIX_RX_MODE_ALLMULTI BIT(2)
1172#define NIX_RX_MODE_USE_MCE BIT(3)
1173 u16 mode;
1174};
1175
1176struct nix_rx_cfg {
1177 struct mbox_msghdr hdr;
1178#define NIX_RX_OL3_VERIFY BIT(0)
1179#define NIX_RX_OL4_VERIFY BIT(1)
1180#define NIX_RX_DROP_RE BIT(2)
1181 u8 len_verify; /* Outer L3/L4 len check */
1182#define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1183 u8 csum_verify; /* Outer L4 checksum verification */
1184};
1185
1186struct nix_frs_cfg {
1187 struct mbox_msghdr hdr;
1188 u8 update_smq; /* Update SMQ's min/max lens */
1189 u8 update_minlen; /* Set minlen also */
1190 u8 sdp_link; /* Set SDP RX link */
1191 u16 maxlen;
1192 u16 minlen;
1193};
1194
1195struct nix_lso_format_cfg {
1196 struct mbox_msghdr hdr;
1197 u64 field_mask;
1198#define NIX_LSO_FIELD_MAX 8
1199 u64 fields[NIX_LSO_FIELD_MAX];
1200};
1201
1202struct nix_lso_format_cfg_rsp {
1203 struct mbox_msghdr hdr;
1204 u8 lso_format_idx;
1205};
1206
1207struct nix_bp_cfg_req {
1208 struct mbox_msghdr hdr;
1209 u16 chan_base; /* Starting channel number */
1210 u8 chan_cnt; /* Number of channels */
1211 u8 bpid_per_chan;
1212 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1213 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1214};
1215
1216/* PF can be mapped to either CGX or LBK interface,
1217 * so maximum 64 channels are possible.
1218 */
1219#define NIX_MAX_BPID_CHAN 64
1220struct nix_bp_cfg_rsp {
1221 struct mbox_msghdr hdr;
1222 u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1223 u8 chan_cnt; /* Number of channel for which bpids are assigned */
1224};
1225
1226struct nix_mcast_grp_create_req {
1227 struct mbox_msghdr hdr;
1228#define NIX_MCAST_INGRESS 0
1229#define NIX_MCAST_EGRESS 1
1230 u8 dir;
1231 u8 reserved[11];
1232 /* Reserving few bytes for future requirement */
1233};
1234
1235struct nix_mcast_grp_create_rsp {
1236 struct mbox_msghdr hdr;
1237 /* This mcast_grp_idx should be passed during MCAM
1238 * write entry for multicast. AF will identify the
1239 * corresponding multicast table index associated
1240 * with the group id and program the same to MCAM entry.
1241 * This group id is also needed during group delete
1242 * and update request.
1243 */
1244 u32 mcast_grp_idx;
1245};
1246
1247struct nix_mcast_grp_destroy_req {
1248 struct mbox_msghdr hdr;
1249 /* Group id returned by nix_mcast_grp_create_rsp */
1250 u32 mcast_grp_idx;
1251 /* If AF is requesting for destroy, then set
1252 * it to '1'. Otherwise keep it to '0'
1253 */
1254 u8 is_af;
1255};
1256
1257struct nix_mcast_grp_update_req {
1258 struct mbox_msghdr hdr;
1259 /* Group id returned by nix_mcast_grp_create_rsp */
1260 u32 mcast_grp_idx;
1261 /* Number of multicast/mirror entries requested */
1262 u32 num_mce_entry;
1263#define NIX_MCE_ENTRY_MAX 64
1264#define NIX_RX_RQ 0
1265#define NIX_RX_RSS 1
1266 /* Receive queue or RSS index within pf_func */
1267 u32 rq_rss_index[NIX_MCE_ENTRY_MAX];
1268 /* pcifunc is required for both ingress and egress multicast */
1269 u16 pcifunc[NIX_MCE_ENTRY_MAX];
1270 /* channel is required for egress multicast */
1271 u16 channel[NIX_MCE_ENTRY_MAX];
1272#define NIX_MCAST_OP_ADD_ENTRY 0
1273#define NIX_MCAST_OP_DEL_ENTRY 1
1274 /* Destination type. 0:Receive queue, 1:RSS*/
1275 u8 dest_type[NIX_MCE_ENTRY_MAX];
1276 u8 op;
1277 /* If AF is requesting for update, then set
1278 * it to '1'. Otherwise keep it to '0'
1279 */
1280 u8 is_af;
1281};
1282
1283struct nix_mcast_grp_update_rsp {
1284 struct mbox_msghdr hdr;
1285 u32 mce_start_index;
1286};
1287
1288/* Global NIX inline IPSec configuration */
1289struct nix_inline_ipsec_cfg {
1290 struct mbox_msghdr hdr;
1291 u32 cpt_credit;
1292 struct {
1293 u8 egrp;
1294 u16 opcode;
1295 u16 param1;
1296 u16 param2;
1297 } gen_cfg;
1298 struct {
1299 u16 cpt_pf_func;
1300 u8 cpt_slot;
1301 } inst_qsel;
1302 u8 enable;
1303 u16 bpid;
1304 u32 credit_th;
1305};
1306
1307/* Per NIX LF inline IPSec configuration */
1308struct nix_inline_ipsec_lf_cfg {
1309 struct mbox_msghdr hdr;
1310 u64 sa_base_addr;
1311 struct {
1312 u32 tag_const;
1313 u16 lenm1_max;
1314 u8 sa_pow2_size;
1315 u8 tt;
1316 } ipsec_cfg0;
1317 struct {
1318 u32 sa_idx_max;
1319 u8 sa_idx_w;
1320 } ipsec_cfg1;
1321 u8 enable;
1322};
1323
1324struct nix_hw_info {
1325 struct mbox_msghdr hdr;
1326 u16 rsvs16;
1327 u16 max_mtu;
1328 u16 min_mtu;
1329 u32 rpm_dwrr_mtu;
1330 u32 sdp_dwrr_mtu;
1331 u32 lbk_dwrr_mtu;
1332 u32 rsvd32[1];
1333 u64 rsvd[15]; /* Add reserved fields for future expansion */
1334};
1335
1336struct nix_bandprof_alloc_req {
1337 struct mbox_msghdr hdr;
1338 /* Count of profiles needed per layer */
1339 u16 prof_count[BAND_PROF_NUM_LAYERS];
1340};
1341
1342struct nix_bandprof_alloc_rsp {
1343 struct mbox_msghdr hdr;
1344 u16 prof_count[BAND_PROF_NUM_LAYERS];
1345
1346 /* There is no need to allocate morethan 1 bandwidth profile
1347 * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1348 * profiles to 64 per PF_FUNC.
1349 */
1350#define MAX_BANDPROF_PER_PFFUNC 64
1351 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1352};
1353
1354struct nix_bandprof_free_req {
1355 struct mbox_msghdr hdr;
1356 u8 free_all;
1357 u16 prof_count[BAND_PROF_NUM_LAYERS];
1358 u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1359};
1360
1361struct nix_bandprof_get_hwinfo_rsp {
1362 struct mbox_msghdr hdr;
1363 u16 prof_count[BAND_PROF_NUM_LAYERS];
1364 u32 policer_timeunit;
1365};
1366
1367/* NPC mbox message structs */
1368
1369#define NPC_MCAM_ENTRY_INVALID 0xFFFF
1370#define NPC_MCAM_INVALID_MAP 0xFFFF
1371
1372/* NPC mailbox error codes
1373 * Range 701 - 800.
1374 */
1375enum npc_af_status {
1376 NPC_MCAM_INVALID_REQ = -701,
1377 NPC_MCAM_ALLOC_DENIED = -702,
1378 NPC_MCAM_ALLOC_FAILED = -703,
1379 NPC_MCAM_PERM_DENIED = -704,
1380 NPC_FLOW_INTF_INVALID = -707,
1381 NPC_FLOW_CHAN_INVALID = -708,
1382 NPC_FLOW_NO_NIXLF = -709,
1383 NPC_FLOW_NOT_SUPPORTED = -710,
1384 NPC_FLOW_VF_PERM_DENIED = -711,
1385 NPC_FLOW_VF_NOT_INIT = -712,
1386 NPC_FLOW_VF_OVERLAP = -713,
1387};
1388
1389struct npc_mcam_alloc_entry_req {
1390 struct mbox_msghdr hdr;
1391#define NPC_MAX_NONCONTIG_ENTRIES 256
1392 u8 contig; /* Contiguous entries ? */
1393#define NPC_MCAM_ANY_PRIO 0
1394#define NPC_MCAM_LOWER_PRIO 1
1395#define NPC_MCAM_HIGHER_PRIO 2
1396 u8 priority; /* Lower or higher w.r.t ref_entry */
1397 u16 ref_entry;
1398 u16 count; /* Number of entries requested */
1399};
1400
1401struct npc_mcam_alloc_entry_rsp {
1402 struct mbox_msghdr hdr;
1403 u16 entry; /* Entry allocated or start index if contiguous.
1404 * Invalid incase of non-contiguous.
1405 */
1406 u16 count; /* Number of entries allocated */
1407 u16 free_count; /* Number of entries available */
1408 u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1409};
1410
1411struct npc_mcam_free_entry_req {
1412 struct mbox_msghdr hdr;
1413 u16 entry; /* Entry index to be freed */
1414 u8 all; /* If all entries allocated to this PFVF to be freed */
1415};
1416
1417struct mcam_entry {
1418#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
1419 u64 kw[NPC_MAX_KWS_IN_KEY];
1420 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1421 u64 action;
1422 u64 vtag_action;
1423};
1424
1425struct npc_mcam_write_entry_req {
1426 struct mbox_msghdr hdr;
1427 struct mcam_entry entry_data;
1428 u16 entry; /* MCAM entry to write this match key */
1429 u16 cntr; /* Counter for this MCAM entry */
1430 u8 intf; /* Rx or Tx interface */
1431 u8 enable_entry;/* Enable this MCAM entry ? */
1432 u8 set_cntr; /* Set counter for this entry ? */
1433};
1434
1435/* Enable/Disable a given entry */
1436struct npc_mcam_ena_dis_entry_req {
1437 struct mbox_msghdr hdr;
1438 u16 entry;
1439};
1440
1441struct npc_mcam_shift_entry_req {
1442 struct mbox_msghdr hdr;
1443#define NPC_MCAM_MAX_SHIFTS 64
1444 u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1445 u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1446 u16 shift_count; /* Number of entries to shift */
1447};
1448
1449struct npc_mcam_shift_entry_rsp {
1450 struct mbox_msghdr hdr;
1451 u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1452};
1453
1454struct npc_mcam_alloc_counter_req {
1455 struct mbox_msghdr hdr;
1456 u8 contig; /* Contiguous counters ? */
1457#define NPC_MAX_NONCONTIG_COUNTERS 64
1458 u16 count; /* Number of counters requested */
1459};
1460
1461struct npc_mcam_alloc_counter_rsp {
1462 struct mbox_msghdr hdr;
1463 u16 cntr; /* Counter allocated or start index if contiguous.
1464 * Invalid incase of non-contiguous.
1465 */
1466 u16 count; /* Number of counters allocated */
1467 u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1468};
1469
1470struct npc_mcam_oper_counter_req {
1471 struct mbox_msghdr hdr;
1472 u16 cntr; /* Free a counter or clear/fetch it's stats */
1473};
1474
1475struct npc_mcam_oper_counter_rsp {
1476 struct mbox_msghdr hdr;
1477 u64 stat; /* valid only while fetching counter's stats */
1478};
1479
1480struct npc_mcam_unmap_counter_req {
1481 struct mbox_msghdr hdr;
1482 u16 cntr;
1483 u16 entry; /* Entry and counter to be unmapped */
1484 u8 all; /* Unmap all entries using this counter ? */
1485};
1486
1487struct npc_mcam_alloc_and_write_entry_req {
1488 struct mbox_msghdr hdr;
1489 struct mcam_entry entry_data;
1490 u16 ref_entry;
1491 u8 priority; /* Lower or higher w.r.t ref_entry */
1492 u8 intf; /* Rx or Tx interface */
1493 u8 enable_entry;/* Enable this MCAM entry ? */
1494 u8 alloc_cntr; /* Allocate counter and map ? */
1495};
1496
1497struct npc_mcam_alloc_and_write_entry_rsp {
1498 struct mbox_msghdr hdr;
1499 u16 entry;
1500 u16 cntr;
1501};
1502
1503struct npc_get_kex_cfg_rsp {
1504 struct mbox_msghdr hdr;
1505 u64 rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1506 u64 tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1507#define NPC_MAX_INTF 2
1508#define NPC_MAX_LID 8
1509#define NPC_MAX_LT 16
1510#define NPC_MAX_LD 2
1511#define NPC_MAX_LFL 16
1512 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1513 u64 kex_ld_flags[NPC_MAX_LD];
1514 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1515 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1516 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1517 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1518#define MKEX_NAME_LEN 128
1519 u8 mkex_pfl_name[MKEX_NAME_LEN];
1520};
1521
1522struct ptp_get_cap_rsp {
1523 struct mbox_msghdr hdr;
1524#define PTP_CAP_HW_ATOMIC_UPDATE BIT_ULL(0)
1525 u64 cap;
1526};
1527
1528struct flow_msg {
1529 unsigned char dmac[6];
1530 unsigned char smac[6];
1531 __be16 etype;
1532 __be16 vlan_etype;
1533 __be16 vlan_tci;
1534 union {
1535 __be32 ip4src;
1536 __be32 ip6src[4];
1537 };
1538 union {
1539 __be32 ip4dst;
1540 __be32 ip6dst[4];
1541 };
1542 union {
1543 __be32 spi;
1544 };
1545
1546 u8 tos;
1547 u8 ip_ver;
1548 u8 ip_proto;
1549 u8 tc;
1550 __be16 sport;
1551 __be16 dport;
1552 union {
1553 u8 ip_flag;
1554 u8 next_header;
1555 };
1556 __be16 vlan_itci;
1557#define OTX2_FLOWER_MASK_MPLS_LB GENMASK(31, 12)
1558#define OTX2_FLOWER_MASK_MPLS_TC GENMASK(11, 9)
1559#define OTX2_FLOWER_MASK_MPLS_BOS BIT(8)
1560#define OTX2_FLOWER_MASK_MPLS_TTL GENMASK(7, 0)
1561#define OTX2_FLOWER_MASK_MPLS_NON_TTL GENMASK(31, 8)
1562 u32 mpls_lse[4];
1563 u8 icmp_type;
1564 u8 icmp_code;
1565 __be16 tcp_flags;
1566};
1567
1568struct npc_install_flow_req {
1569 struct mbox_msghdr hdr;
1570 struct flow_msg packet;
1571 struct flow_msg mask;
1572 u64 features;
1573 u16 entry;
1574 u16 channel;
1575 u16 chan_mask;
1576 u8 intf;
1577 u8 set_cntr; /* If counter is available set counter for this entry ? */
1578 u8 default_rule;
1579 u8 append; /* overwrite(0) or append(1) flow to default rule? */
1580 u16 vf;
1581 /* action */
1582 u32 index;
1583 u16 match_id;
1584 u8 flow_key_alg;
1585 u8 op;
1586 /* vtag rx action */
1587 u8 vtag0_type;
1588 u8 vtag0_valid;
1589 u8 vtag1_type;
1590 u8 vtag1_valid;
1591 /* vtag tx action */
1592 u16 vtag0_def;
1593 u8 vtag0_op;
1594 u16 vtag1_def;
1595 u8 vtag1_op;
1596 /* old counter value */
1597 u16 cntr_val;
1598};
1599
1600struct npc_install_flow_rsp {
1601 struct mbox_msghdr hdr;
1602 int counter; /* negative if no counter else counter number */
1603};
1604
1605struct npc_delete_flow_req {
1606 struct mbox_msghdr hdr;
1607 u16 entry;
1608 u16 start;/*Disable range of entries */
1609 u16 end;
1610 u8 all; /* PF + VFs */
1611};
1612
1613struct npc_delete_flow_rsp {
1614 struct mbox_msghdr hdr;
1615 u16 cntr_val;
1616};
1617
1618struct npc_mcam_read_entry_req {
1619 struct mbox_msghdr hdr;
1620 u16 entry; /* MCAM entry to read */
1621};
1622
1623struct npc_mcam_read_entry_rsp {
1624 struct mbox_msghdr hdr;
1625 struct mcam_entry entry_data;
1626 u8 intf;
1627 u8 enable;
1628};
1629
1630struct npc_mcam_read_base_rule_rsp {
1631 struct mbox_msghdr hdr;
1632 struct mcam_entry entry;
1633};
1634
1635struct npc_mcam_get_stats_req {
1636 struct mbox_msghdr hdr;
1637 u16 entry; /* mcam entry */
1638};
1639
1640struct npc_mcam_get_stats_rsp {
1641 struct mbox_msghdr hdr;
1642 u64 stat; /* counter stats */
1643 u8 stat_ena; /* enabled */
1644};
1645
1646struct npc_get_field_hash_info_req {
1647 struct mbox_msghdr hdr;
1648 u8 intf;
1649};
1650
1651struct npc_get_field_hash_info_rsp {
1652 struct mbox_msghdr hdr;
1653 u64 secret_key[3];
1654#define NPC_MAX_HASH 2
1655#define NPC_MAX_HASH_MASK 2
1656 /* NPC_AF_INTF(0..1)_HASH(0..1)_MASK(0..1) */
1657 u64 hash_mask[NPC_MAX_INTF][NPC_MAX_HASH][NPC_MAX_HASH_MASK];
1658 /* NPC_AF_INTF(0..1)_HASH(0..1)_RESULT_CTRL */
1659 u64 hash_ctrl[NPC_MAX_INTF][NPC_MAX_HASH];
1660};
1661
1662enum ptp_op {
1663 PTP_OP_ADJFINE = 0,
1664 PTP_OP_GET_CLOCK = 1,
1665 PTP_OP_GET_TSTMP = 2,
1666 PTP_OP_SET_THRESH = 3,
1667 PTP_OP_PPS_ON = 4,
1668 PTP_OP_ADJTIME = 5,
1669 PTP_OP_SET_CLOCK = 6,
1670};
1671
1672struct ptp_req {
1673 struct mbox_msghdr hdr;
1674 u8 op;
1675 s64 scaled_ppm;
1676 u64 thresh;
1677 u64 period;
1678 int pps_on;
1679 s64 delta;
1680 u64 clk;
1681};
1682
1683struct ptp_rsp {
1684 struct mbox_msghdr hdr;
1685 u64 clk;
1686 u64 tsc;
1687};
1688
1689struct npc_get_field_status_req {
1690 struct mbox_msghdr hdr;
1691 u8 intf;
1692 u8 field;
1693};
1694
1695struct npc_get_field_status_rsp {
1696 struct mbox_msghdr hdr;
1697 u8 enable;
1698};
1699
1700struct set_vf_perm {
1701 struct mbox_msghdr hdr;
1702 u16 vf;
1703#define RESET_VF_PERM BIT_ULL(0)
1704#define VF_TRUSTED BIT_ULL(1)
1705 u64 flags;
1706};
1707
1708struct lmtst_tbl_setup_req {
1709 struct mbox_msghdr hdr;
1710 u64 dis_sched_early_comp :1;
1711 u64 sch_ena :1;
1712 u64 dis_line_pref :1;
1713 u64 ssow_pf_func :13;
1714 u16 base_pcifunc;
1715 u8 use_local_lmt_region;
1716 u64 lmt_iova;
1717 u64 rsvd[4];
1718};
1719
1720/* CPT mailbox error codes
1721 * Range 901 - 1000.
1722 */
1723enum cpt_af_status {
1724 CPT_AF_ERR_PARAM = -901,
1725 CPT_AF_ERR_GRP_INVALID = -902,
1726 CPT_AF_ERR_LF_INVALID = -903,
1727 CPT_AF_ERR_ACCESS_DENIED = -904,
1728 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1729 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1730 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1731 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1732};
1733
1734/* CPT mbox message formats */
1735struct cpt_rd_wr_reg_msg {
1736 struct mbox_msghdr hdr;
1737 u64 reg_offset;
1738 u64 *ret_val;
1739 u64 val;
1740 u8 is_write;
1741 int blkaddr;
1742};
1743
1744struct cpt_lf_alloc_req_msg {
1745 struct mbox_msghdr hdr;
1746 u16 nix_pf_func;
1747 u16 sso_pf_func;
1748 u16 eng_grpmsk;
1749 int blkaddr;
1750 u8 ctx_ilen_valid : 1;
1751 u8 ctx_ilen : 7;
1752};
1753
1754#define CPT_INLINE_INBOUND 0
1755#define CPT_INLINE_OUTBOUND 1
1756
1757/* Mailbox message request format for CPT IPsec
1758 * inline inbound and outbound configuration.
1759 */
1760struct cpt_inline_ipsec_cfg_msg {
1761 struct mbox_msghdr hdr;
1762 u8 enable;
1763 u8 slot;
1764 u8 dir;
1765 u8 sso_pf_func_ovrd;
1766 u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1767 u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1768};
1769
1770/* Mailbox message request and response format for CPT stats. */
1771struct cpt_sts_req {
1772 struct mbox_msghdr hdr;
1773 u8 blkaddr;
1774};
1775
1776struct cpt_sts_rsp {
1777 struct mbox_msghdr hdr;
1778 u64 inst_req_pc;
1779 u64 inst_lat_pc;
1780 u64 rd_req_pc;
1781 u64 rd_lat_pc;
1782 u64 rd_uc_pc;
1783 u64 active_cycles_pc;
1784 u64 ctx_mis_pc;
1785 u64 ctx_hit_pc;
1786 u64 ctx_aop_pc;
1787 u64 ctx_aop_lat_pc;
1788 u64 ctx_ifetch_pc;
1789 u64 ctx_ifetch_lat_pc;
1790 u64 ctx_ffetch_pc;
1791 u64 ctx_ffetch_lat_pc;
1792 u64 ctx_wback_pc;
1793 u64 ctx_wback_lat_pc;
1794 u64 ctx_psh_pc;
1795 u64 ctx_psh_lat_pc;
1796 u64 ctx_err;
1797 u64 ctx_enc_id;
1798 u64 ctx_flush_timer;
1799 u64 rxc_time;
1800 u64 rxc_time_cfg;
1801 u64 rxc_active_sts;
1802 u64 rxc_zombie_sts;
1803 u64 busy_sts_ae;
1804 u64 free_sts_ae;
1805 u64 busy_sts_se;
1806 u64 free_sts_se;
1807 u64 busy_sts_ie;
1808 u64 free_sts_ie;
1809 u64 exe_err_info;
1810 u64 cptclk_cnt;
1811 u64 diag;
1812 u64 rxc_dfrg;
1813 u64 x2p_link_cfg0;
1814 u64 x2p_link_cfg1;
1815};
1816
1817/* Mailbox message request format to configure reassembly timeout. */
1818struct cpt_rxc_time_cfg_req {
1819 struct mbox_msghdr hdr;
1820 int blkaddr;
1821 u32 step;
1822 u16 zombie_thres;
1823 u16 zombie_limit;
1824 u16 active_thres;
1825 u16 active_limit;
1826};
1827
1828/* Mailbox message request format to request for CPT_INST_S lmtst. */
1829struct cpt_inst_lmtst_req {
1830 struct mbox_msghdr hdr;
1831 u64 inst[8];
1832 u64 rsvd;
1833};
1834
1835/* Mailbox message format to request for CPT LF reset */
1836struct cpt_lf_rst_req {
1837 struct mbox_msghdr hdr;
1838 u32 slot;
1839 u32 rsvd;
1840};
1841
1842/* Mailbox message format to request for CPT faulted engines */
1843struct cpt_flt_eng_info_req {
1844 struct mbox_msghdr hdr;
1845 int blkaddr;
1846 bool reset;
1847 u32 rsvd;
1848};
1849
1850struct cpt_flt_eng_info_rsp {
1851 struct mbox_msghdr hdr;
1852 u64 flt_eng_map[CPT_10K_AF_INT_VEC_RVU];
1853 u64 rcvrd_eng_map[CPT_10K_AF_INT_VEC_RVU];
1854 u64 rsvd;
1855};
1856
1857struct sdp_node_info {
1858 /* Node to which this PF belons to */
1859 u8 node_id;
1860 u8 max_vfs;
1861 u8 num_pf_rings;
1862 u8 pf_srn;
1863#define SDP_MAX_VFS 128
1864 u8 vf_rings[SDP_MAX_VFS];
1865};
1866
1867struct sdp_chan_info_msg {
1868 struct mbox_msghdr hdr;
1869 struct sdp_node_info info;
1870};
1871
1872struct sdp_get_chan_info_msg {
1873 struct mbox_msghdr hdr;
1874 u16 chan_base;
1875 u16 num_chan;
1876};
1877
1878/* CGX mailbox error codes
1879 * Range 1101 - 1200.
1880 */
1881enum cgx_af_status {
1882 LMAC_AF_ERR_INVALID_PARAM = -1101,
1883 LMAC_AF_ERR_PF_NOT_MAPPED = -1102,
1884 LMAC_AF_ERR_PERM_DENIED = -1103,
1885 LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED = -1104,
1886 LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1887 LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1888 LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1889 LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1890 LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1891 LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1892};
1893
1894enum mcs_direction {
1895 MCS_RX,
1896 MCS_TX,
1897};
1898
1899enum mcs_rsrc_type {
1900 MCS_RSRC_TYPE_FLOWID,
1901 MCS_RSRC_TYPE_SECY,
1902 MCS_RSRC_TYPE_SC,
1903 MCS_RSRC_TYPE_SA,
1904};
1905
1906struct mcs_alloc_rsrc_req {
1907 struct mbox_msghdr hdr;
1908 u8 rsrc_type;
1909 u8 rsrc_cnt; /* Resources count */
1910 u8 mcs_id; /* MCS block ID */
1911 u8 dir; /* Macsec ingress or egress side */
1912 u8 all; /* Allocate all resource type one each */
1913 u64 rsvd;
1914};
1915
1916struct mcs_alloc_rsrc_rsp {
1917 struct mbox_msghdr hdr;
1918 u8 flow_ids[128]; /* Index of reserved entries */
1919 u8 secy_ids[128];
1920 u8 sc_ids[128];
1921 u8 sa_ids[256];
1922 u8 rsrc_type;
1923 u8 rsrc_cnt; /* No of entries reserved */
1924 u8 mcs_id;
1925 u8 dir;
1926 u8 all;
1927 u8 rsvd[256]; /* reserved fields for future expansion */
1928};
1929
1930struct mcs_free_rsrc_req {
1931 struct mbox_msghdr hdr;
1932 u8 rsrc_id; /* Index of the entry to be freed */
1933 u8 rsrc_type;
1934 u8 mcs_id;
1935 u8 dir;
1936 u8 all; /* Free all the cam resources */
1937 u64 rsvd;
1938};
1939
1940struct mcs_flowid_entry_write_req {
1941 struct mbox_msghdr hdr;
1942 u64 data[4];
1943 u64 mask[4];
1944 u64 sci; /* CNF10K-B for tx_secy_mem_map */
1945 u8 flow_id;
1946 u8 secy_id; /* secyid for which flowid is mapped */
1947 u8 sc_id; /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */
1948 u8 ena; /* Enable tcam entry */
1949 u8 ctrl_pkt;
1950 u8 mcs_id;
1951 u8 dir;
1952 u64 rsvd;
1953};
1954
1955struct mcs_secy_plcy_write_req {
1956 struct mbox_msghdr hdr;
1957 u64 plcy;
1958 u8 secy_id;
1959 u8 mcs_id;
1960 u8 dir;
1961 u64 rsvd;
1962};
1963
1964/* RX SC_CAM mapping */
1965struct mcs_rx_sc_cam_write_req {
1966 struct mbox_msghdr hdr;
1967 u64 sci; /* SCI */
1968 u64 secy_id; /* secy index mapped to SC */
1969 u8 sc_id; /* SC CAM entry index */
1970 u8 mcs_id;
1971 u64 rsvd;
1972};
1973
1974struct mcs_sa_plcy_write_req {
1975 struct mbox_msghdr hdr;
1976 u64 plcy[2][9]; /* Support 2 SA policy */
1977 u8 sa_index[2];
1978 u8 sa_cnt;
1979 u8 mcs_id;
1980 u8 dir;
1981 u64 rsvd;
1982};
1983
1984struct mcs_tx_sc_sa_map {
1985 struct mbox_msghdr hdr;
1986 u8 sa_index0;
1987 u8 sa_index1;
1988 u8 rekey_ena;
1989 u8 sa_index0_vld;
1990 u8 sa_index1_vld;
1991 u8 tx_sa_active;
1992 u64 sectag_sci;
1993 u8 sc_id; /* used as index for SA_MEM_MAP */
1994 u8 mcs_id;
1995 u64 rsvd;
1996};
1997
1998struct mcs_rx_sc_sa_map {
1999 struct mbox_msghdr hdr;
2000 u8 sa_index;
2001 u8 sa_in_use;
2002 u8 sc_id;
2003 u8 an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */
2004 u8 mcs_id;
2005 u64 rsvd;
2006};
2007
2008struct mcs_flowid_ena_dis_entry {
2009 struct mbox_msghdr hdr;
2010 u8 flow_id;
2011 u8 ena;
2012 u8 mcs_id;
2013 u8 dir;
2014 u64 rsvd;
2015};
2016
2017struct mcs_pn_table_write_req {
2018 struct mbox_msghdr hdr;
2019 u64 next_pn;
2020 u8 pn_id;
2021 u8 mcs_id;
2022 u8 dir;
2023 u64 rsvd;
2024};
2025
2026struct mcs_hw_info {
2027 struct mbox_msghdr hdr;
2028 u8 num_mcs_blks; /* Number of MCS blocks */
2029 u8 tcam_entries; /* RX/TX Tcam entries per mcs block */
2030 u8 secy_entries; /* RX/TX SECY entries per mcs block */
2031 u8 sc_entries; /* RX/TX SC CAM entries per mcs block */
2032 u16 sa_entries; /* PN table entries = SA entries */
2033 u64 rsvd[16];
2034};
2035
2036struct mcs_set_active_lmac {
2037 struct mbox_msghdr hdr;
2038 u32 lmac_bmap; /* bitmap of active lmac per mcs block */
2039 u8 mcs_id;
2040 u16 chan_base; /* MCS channel base */
2041 u64 rsvd;
2042};
2043
2044struct mcs_set_lmac_mode {
2045 struct mbox_msghdr hdr;
2046 u8 mode; /* 1:Bypass 0:Operational */
2047 u8 lmac_id;
2048 u8 mcs_id;
2049 u64 rsvd;
2050};
2051
2052struct mcs_port_reset_req {
2053 struct mbox_msghdr hdr;
2054 u8 reset;
2055 u8 mcs_id;
2056 u8 port_id;
2057 u64 rsvd;
2058};
2059
2060struct mcs_port_cfg_set_req {
2061 struct mbox_msghdr hdr;
2062 u8 cstm_tag_rel_mode_sel;
2063 u8 custom_hdr_enb;
2064 u8 fifo_skid;
2065 u8 port_mode;
2066 u8 port_id;
2067 u8 mcs_id;
2068 u64 rsvd;
2069};
2070
2071struct mcs_port_cfg_get_req {
2072 struct mbox_msghdr hdr;
2073 u8 port_id;
2074 u8 mcs_id;
2075 u64 rsvd;
2076};
2077
2078struct mcs_port_cfg_get_rsp {
2079 struct mbox_msghdr hdr;
2080 u8 cstm_tag_rel_mode_sel;
2081 u8 custom_hdr_enb;
2082 u8 fifo_skid;
2083 u8 port_mode;
2084 u8 port_id;
2085 u8 mcs_id;
2086 u64 rsvd;
2087};
2088
2089struct mcs_custom_tag_cfg_get_req {
2090 struct mbox_msghdr hdr;
2091 u8 mcs_id;
2092 u8 dir;
2093 u64 rsvd;
2094};
2095
2096struct mcs_custom_tag_cfg_get_rsp {
2097 struct mbox_msghdr hdr;
2098 u16 cstm_etype[8];
2099 u8 cstm_indx[8];
2100 u8 cstm_etype_en;
2101 u8 mcs_id;
2102 u8 dir;
2103 u64 rsvd;
2104};
2105
2106/* MCS mailbox error codes
2107 * Range 1201 - 1300.
2108 */
2109enum mcs_af_status {
2110 MCS_AF_ERR_INVALID_MCSID = -1201,
2111 MCS_AF_ERR_NOT_MAPPED = -1202,
2112};
2113
2114struct mcs_set_pn_threshold {
2115 struct mbox_msghdr hdr;
2116 u64 threshold;
2117 u8 xpn; /* '1' for setting xpn threshold */
2118 u8 mcs_id;
2119 u8 dir;
2120 u64 rsvd;
2121};
2122
2123enum mcs_ctrl_pkt_rulew_type {
2124 MCS_CTRL_PKT_RULE_TYPE_ETH,
2125 MCS_CTRL_PKT_RULE_TYPE_DA,
2126 MCS_CTRL_PKT_RULE_TYPE_RANGE,
2127 MCS_CTRL_PKT_RULE_TYPE_COMBO,
2128 MCS_CTRL_PKT_RULE_TYPE_MAC,
2129};
2130
2131struct mcs_alloc_ctrl_pkt_rule_req {
2132 struct mbox_msghdr hdr;
2133 u8 rule_type;
2134 u8 mcs_id; /* MCS block ID */
2135 u8 dir; /* Macsec ingress or egress side */
2136 u64 rsvd;
2137};
2138
2139struct mcs_alloc_ctrl_pkt_rule_rsp {
2140 struct mbox_msghdr hdr;
2141 u8 rule_idx;
2142 u8 rule_type;
2143 u8 mcs_id;
2144 u8 dir;
2145 u64 rsvd;
2146};
2147
2148struct mcs_free_ctrl_pkt_rule_req {
2149 struct mbox_msghdr hdr;
2150 u8 rule_idx;
2151 u8 rule_type;
2152 u8 mcs_id;
2153 u8 dir;
2154 u8 all;
2155 u64 rsvd;
2156};
2157
2158struct mcs_ctrl_pkt_rule_write_req {
2159 struct mbox_msghdr hdr;
2160 u64 data0;
2161 u64 data1;
2162 u64 data2;
2163 u8 rule_idx;
2164 u8 rule_type;
2165 u8 mcs_id;
2166 u8 dir;
2167 u64 rsvd;
2168};
2169
2170struct mcs_stats_req {
2171 struct mbox_msghdr hdr;
2172 u8 id;
2173 u8 mcs_id;
2174 u8 dir;
2175 u64 rsvd;
2176};
2177
2178struct mcs_flowid_stats {
2179 struct mbox_msghdr hdr;
2180 u64 tcam_hit_cnt;
2181 u64 rsvd;
2182};
2183
2184struct mcs_secy_stats {
2185 struct mbox_msghdr hdr;
2186 u64 ctl_pkt_bcast_cnt;
2187 u64 ctl_pkt_mcast_cnt;
2188 u64 ctl_pkt_ucast_cnt;
2189 u64 ctl_octet_cnt;
2190 u64 unctl_pkt_bcast_cnt;
2191 u64 unctl_pkt_mcast_cnt;
2192 u64 unctl_pkt_ucast_cnt;
2193 u64 unctl_octet_cnt;
2194 /* Valid only for RX */
2195 u64 octet_decrypted_cnt;
2196 u64 octet_validated_cnt;
2197 u64 pkt_port_disabled_cnt;
2198 u64 pkt_badtag_cnt;
2199 u64 pkt_nosa_cnt;
2200 u64 pkt_nosaerror_cnt;
2201 u64 pkt_tagged_ctl_cnt;
2202 u64 pkt_untaged_cnt;
2203 u64 pkt_ctl_cnt; /* CN10K-B */
2204 u64 pkt_notag_cnt; /* CNF10K-B */
2205 /* Valid only for TX */
2206 u64 octet_encrypted_cnt;
2207 u64 octet_protected_cnt;
2208 u64 pkt_noactivesa_cnt;
2209 u64 pkt_toolong_cnt;
2210 u64 pkt_untagged_cnt;
2211 u64 rsvd[4];
2212};
2213
2214struct mcs_port_stats {
2215 struct mbox_msghdr hdr;
2216 u64 tcam_miss_cnt;
2217 u64 parser_err_cnt;
2218 u64 preempt_err_cnt; /* CNF10K-B */
2219 u64 sectag_insert_err_cnt;
2220 u64 rsvd[4];
2221};
2222
2223/* Only for CN10K-B */
2224struct mcs_sa_stats {
2225 struct mbox_msghdr hdr;
2226 /* RX */
2227 u64 pkt_invalid_cnt;
2228 u64 pkt_nosaerror_cnt;
2229 u64 pkt_notvalid_cnt;
2230 u64 pkt_ok_cnt;
2231 u64 pkt_nosa_cnt;
2232 /* TX */
2233 u64 pkt_encrypt_cnt;
2234 u64 pkt_protected_cnt;
2235 u64 rsvd[4];
2236};
2237
2238struct mcs_sc_stats {
2239 struct mbox_msghdr hdr;
2240 /* RX */
2241 u64 hit_cnt;
2242 u64 pkt_invalid_cnt;
2243 u64 pkt_late_cnt;
2244 u64 pkt_notvalid_cnt;
2245 u64 pkt_unchecked_cnt;
2246 u64 pkt_delay_cnt; /* CNF10K-B */
2247 u64 pkt_ok_cnt; /* CNF10K-B */
2248 u64 octet_decrypt_cnt; /* CN10K-B */
2249 u64 octet_validate_cnt; /* CN10K-B */
2250 /* TX */
2251 u64 pkt_encrypt_cnt;
2252 u64 pkt_protected_cnt;
2253 u64 octet_encrypt_cnt; /* CN10K-B */
2254 u64 octet_protected_cnt; /* CN10K-B */
2255 u64 rsvd[4];
2256};
2257
2258struct mcs_clear_stats {
2259 struct mbox_msghdr hdr;
2260#define MCS_FLOWID_STATS 0
2261#define MCS_SECY_STATS 1
2262#define MCS_SC_STATS 2
2263#define MCS_SA_STATS 3
2264#define MCS_PORT_STATS 4
2265 u8 type; /* FLOWID, SECY, SC, SA, PORT */
2266 u8 id; /* type = PORT, If id = FF(invalid) port no is derived from pcifunc */
2267 u8 mcs_id;
2268 u8 dir;
2269 u8 all; /* All resources stats mapped to PF are cleared */
2270};
2271
2272struct mcs_intr_cfg {
2273 struct mbox_msghdr hdr;
2274#define MCS_CPM_RX_SECTAG_V_EQ1_INT BIT_ULL(0)
2275#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT BIT_ULL(1)
2276#define MCS_CPM_RX_SECTAG_SL_GTE48_INT BIT_ULL(2)
2277#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT BIT_ULL(3)
2278#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)
2279#define MCS_CPM_RX_PACKET_XPN_EQ0_INT BIT_ULL(5)
2280#define MCS_CPM_RX_PN_THRESH_REACHED_INT BIT_ULL(6)
2281#define MCS_CPM_TX_PACKET_XPN_EQ0_INT BIT_ULL(7)
2282#define MCS_CPM_TX_PN_THRESH_REACHED_INT BIT_ULL(8)
2283#define MCS_CPM_TX_SA_NOT_VALID_INT BIT_ULL(9)
2284#define MCS_BBE_RX_DFIFO_OVERFLOW_INT BIT_ULL(10)
2285#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT BIT_ULL(11)
2286#define MCS_BBE_TX_DFIFO_OVERFLOW_INT BIT_ULL(12)
2287#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT BIT_ULL(13)
2288#define MCS_PAB_RX_CHAN_OVERFLOW_INT BIT_ULL(14)
2289#define MCS_PAB_TX_CHAN_OVERFLOW_INT BIT_ULL(15)
2290 u64 intr_mask; /* Interrupt enable mask */
2291 u8 mcs_id;
2292 u8 lmac_id;
2293 u64 rsvd;
2294};
2295
2296struct mcs_intr_info {
2297 struct mbox_msghdr hdr;
2298 u64 intr_mask;
2299 int sa_id;
2300 u8 mcs_id;
2301 u8 lmac_id;
2302 u64 rsvd;
2303};
2304
2305#endif /* MBOX_H */