1// SPDX-License-Identifier: GPL-2.0
   2//
   3// regmap based irq_chip
   4//
   5// Copyright 2011 Wolfson Microelectronics plc
   6//
   7// Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 
 
 
 
   8
   9#include <linux/device.h>
  10#include <linux/export.h>
  11#include <linux/interrupt.h>
 
  12#include <linux/irq.h>
 
  13#include <linux/irqdomain.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/regmap.h>
  16#include <linux/slab.h>
  17
  18#include "internal.h"
  19
  20struct regmap_irq_chip_data {
  21	struct mutex lock;
  22	struct irq_chip irq_chip;
  23
  24	struct regmap *map;
  25	const struct regmap_irq_chip *chip;
  26
  27	int irq_base;
  28	struct irq_domain *domain;
  29
  30	int irq;
  31	int wake_count;
  32
  33	void *status_reg_buf;
  34	unsigned int *main_status_buf;
  35	unsigned int *status_buf;
  36	unsigned int *mask_buf;
  37	unsigned int *mask_buf_def;
  38	unsigned int *wake_buf;
  39	unsigned int *type_buf;
  40	unsigned int *type_buf_def;
  41
  42	unsigned int irq_reg_stride;
  43	unsigned int type_reg_stride;
  44
  45	bool clear_status:1;
  46};
  47
  48static inline const
  49struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data,
  50				     int irq)
  51{
  52	return &data->chip->irqs[irq];
  53}
  54
  55static void regmap_irq_lock(struct irq_data *data)
  56{
  57	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  58
  59	mutex_lock(&d->lock);
  60}
  61
  62static int regmap_irq_update_bits(struct regmap_irq_chip_data *d,
  63				  unsigned int reg, unsigned int mask,
  64				  unsigned int val)
  65{
  66	if (d->chip->mask_writeonly)
  67		return regmap_write_bits(d->map, reg, mask, val);
  68	else
  69		return regmap_update_bits(d->map, reg, mask, val);
  70}
  71
  72static void regmap_irq_sync_unlock(struct irq_data *data)
  73{
  74	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
  75	struct regmap *map = d->map;
  76	int i, ret;
  77	u32 reg;
  78	u32 unmask_offset;
  79	u32 val;
  80
  81	if (d->chip->runtime_pm) {
  82		ret = pm_runtime_get_sync(map->dev);
  83		if (ret < 0)
  84			dev_err(map->dev, "IRQ sync failed to resume: %d\n",
  85				ret);
  86	}
  87
  88	if (d->clear_status) {
  89		for (i = 0; i < d->chip->num_regs; i++) {
  90			reg = d->chip->status_base +
  91				(i * map->reg_stride * d->irq_reg_stride);
  92
  93			ret = regmap_read(map, reg, &val);
  94			if (ret)
  95				dev_err(d->map->dev,
  96					"Failed to clear the interrupt status bits\n");
  97		}
  98
  99		d->clear_status = false;
 100	}
 101
 102	/*
 103	 * If there's been a change in the mask write it back to the
 104	 * hardware.  We rely on the use of the regmap core cache to
 105	 * suppress pointless writes.
 106	 */
 107	for (i = 0; i < d->chip->num_regs; i++) {
 108		if (!d->chip->mask_base)
 109			continue;
 110
 111		reg = d->chip->mask_base +
 112			(i * map->reg_stride * d->irq_reg_stride);
 113		if (d->chip->mask_invert) {
 114			ret = regmap_irq_update_bits(d, reg,
 115					 d->mask_buf_def[i], ~d->mask_buf[i]);
 116		} else if (d->chip->unmask_base) {
 117			/* set mask with mask_base register */
 118			ret = regmap_irq_update_bits(d, reg,
 119					d->mask_buf_def[i], ~d->mask_buf[i]);
 120			if (ret < 0)
 121				dev_err(d->map->dev,
 122					"Failed to sync unmasks in %x\n",
 123					reg);
 124			unmask_offset = d->chip->unmask_base -
 125							d->chip->mask_base;
 126			/* clear mask with unmask_base register */
 127			ret = regmap_irq_update_bits(d,
 128					reg + unmask_offset,
 129					d->mask_buf_def[i],
 130					d->mask_buf[i]);
 131		} else {
 132			ret = regmap_irq_update_bits(d, reg,
 133					 d->mask_buf_def[i], d->mask_buf[i]);
 134		}
 135		if (ret != 0)
 136			dev_err(d->map->dev, "Failed to sync masks in %x\n",
 137				reg);
 138
 139		reg = d->chip->wake_base +
 140			(i * map->reg_stride * d->irq_reg_stride);
 141		if (d->wake_buf) {
 142			if (d->chip->wake_invert)
 143				ret = regmap_irq_update_bits(d, reg,
 144							 d->mask_buf_def[i],
 145							 ~d->wake_buf[i]);
 146			else
 147				ret = regmap_irq_update_bits(d, reg,
 148							 d->mask_buf_def[i],
 149							 d->wake_buf[i]);
 150			if (ret != 0)
 151				dev_err(d->map->dev,
 152					"Failed to sync wakes in %x: %d\n",
 153					reg, ret);
 154		}
 155
 156		if (!d->chip->init_ack_masked)
 157			continue;
 158		/*
 159		 * Ack all the masked interrupts unconditionally,
 160		 * OR if there is masked interrupt which hasn't been Acked,
 161		 * it'll be ignored in irq handler, then may introduce irq storm
 162		 */
 163		if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) {
 164			reg = d->chip->ack_base +
 165				(i * map->reg_stride * d->irq_reg_stride);
 166			/* some chips ack by write 0 */
 167			if (d->chip->ack_invert)
 168				ret = regmap_write(map, reg, ~d->mask_buf[i]);
 169			else
 170				ret = regmap_write(map, reg, d->mask_buf[i]);
 171			if (ret != 0)
 172				dev_err(d->map->dev, "Failed to ack 0x%x: %d\n",
 173					reg, ret);
 174		}
 175	}
 176
 177	/* Don't update the type bits if we're using mask bits for irq type. */
 178	if (!d->chip->type_in_mask) {
 179		for (i = 0; i < d->chip->num_type_reg; i++) {
 180			if (!d->type_buf_def[i])
 181				continue;
 182			reg = d->chip->type_base +
 183				(i * map->reg_stride * d->type_reg_stride);
 184			if (d->chip->type_invert)
 185				ret = regmap_irq_update_bits(d, reg,
 186					d->type_buf_def[i], ~d->type_buf[i]);
 187			else
 188				ret = regmap_irq_update_bits(d, reg,
 189					d->type_buf_def[i], d->type_buf[i]);
 190			if (ret != 0)
 191				dev_err(d->map->dev, "Failed to sync type in %x\n",
 192					reg);
 193		}
 194	}
 195
 196	if (d->chip->runtime_pm)
 197		pm_runtime_put(map->dev);
 198
 199	/* If we've changed our wakeup count propagate it to the parent */
 200	if (d->wake_count < 0)
 201		for (i = d->wake_count; i < 0; i++)
 202			irq_set_irq_wake(d->irq, 0);
 203	else if (d->wake_count > 0)
 204		for (i = 0; i < d->wake_count; i++)
 205			irq_set_irq_wake(d->irq, 1);
 206
 207	d->wake_count = 0;
 208
 209	mutex_unlock(&d->lock);
 210}
 211
 212static void regmap_irq_enable(struct irq_data *data)
 213{
 214	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 215	struct regmap *map = d->map;
 216	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 217	unsigned int mask, type;
 218
 219	type = irq_data->type.type_falling_val | irq_data->type.type_rising_val;
 220
 221	/*
 222	 * The type_in_mask flag means that the underlying hardware uses
 223	 * separate mask bits for rising and falling edge interrupts, but
 224	 * we want to make them into a single virtual interrupt with
 225	 * configurable edge.
 226	 *
 227	 * If the interrupt we're enabling defines the falling or rising
 228	 * masks then instead of using the regular mask bits for this
 229	 * interrupt, use the value previously written to the type buffer
 230	 * at the corresponding offset in regmap_irq_set_type().
 231	 */
 232	if (d->chip->type_in_mask && type)
 233		mask = d->type_buf[irq_data->reg_offset / map->reg_stride];
 234	else
 235		mask = irq_data->mask;
 236
 237	if (d->chip->clear_on_unmask)
 238		d->clear_status = true;
 239
 240	d->mask_buf[irq_data->reg_offset / map->reg_stride] &= ~mask;
 241}
 242
 243static void regmap_irq_disable(struct irq_data *data)
 244{
 245	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 246	struct regmap *map = d->map;
 247	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 248
 249	d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
 250}
 251
 252static int regmap_irq_set_type(struct irq_data *data, unsigned int type)
 253{
 254	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 255	struct regmap *map = d->map;
 256	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 257	int reg;
 258	const struct regmap_irq_type *t = &irq_data->type;
 259
 260	if ((t->types_supported & type) != type)
 261		return 0;
 262
 263	reg = t->type_reg_offset / map->reg_stride;
 264
 265	if (t->type_reg_mask)
 266		d->type_buf[reg] &= ~t->type_reg_mask;
 267	else
 268		d->type_buf[reg] &= ~(t->type_falling_val |
 269				      t->type_rising_val |
 270				      t->type_level_low_val |
 271				      t->type_level_high_val);
 272	switch (type) {
 273	case IRQ_TYPE_EDGE_FALLING:
 274		d->type_buf[reg] |= t->type_falling_val;
 275		break;
 276
 277	case IRQ_TYPE_EDGE_RISING:
 278		d->type_buf[reg] |= t->type_rising_val;
 279		break;
 280
 281	case IRQ_TYPE_EDGE_BOTH:
 282		d->type_buf[reg] |= (t->type_falling_val |
 283					t->type_rising_val);
 284		break;
 285
 286	case IRQ_TYPE_LEVEL_HIGH:
 287		d->type_buf[reg] |= t->type_level_high_val;
 288		break;
 289
 290	case IRQ_TYPE_LEVEL_LOW:
 291		d->type_buf[reg] |= t->type_level_low_val;
 292		break;
 293	default:
 294		return -EINVAL;
 295	}
 296	return 0;
 297}
 298
 299static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
 300{
 301	struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
 302	struct regmap *map = d->map;
 303	const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
 304
 305	if (on) {
 306		if (d->wake_buf)
 307			d->wake_buf[irq_data->reg_offset / map->reg_stride]
 308				&= ~irq_data->mask;
 309		d->wake_count++;
 310	} else {
 311		if (d->wake_buf)
 312			d->wake_buf[irq_data->reg_offset / map->reg_stride]
 313				|= irq_data->mask;
 314		d->wake_count--;
 315	}
 316
 317	return 0;
 318}
 319
 320static const struct irq_chip regmap_irq_chip = {
 321	.irq_bus_lock		= regmap_irq_lock,
 322	.irq_bus_sync_unlock	= regmap_irq_sync_unlock,
 323	.irq_disable		= regmap_irq_disable,
 324	.irq_enable		= regmap_irq_enable,
 325	.irq_set_type		= regmap_irq_set_type,
 326	.irq_set_wake		= regmap_irq_set_wake,
 327};
 328
 329static inline int read_sub_irq_data(struct regmap_irq_chip_data *data,
 330					   unsigned int b)
 331{
 332	const struct regmap_irq_chip *chip = data->chip;
 333	struct regmap *map = data->map;
 334	struct regmap_irq_sub_irq_map *subreg;
 335	int i, ret = 0;
 336
 337	if (!chip->sub_reg_offsets) {
 338		/* Assume linear mapping */
 339		ret = regmap_read(map, chip->status_base +
 340				  (b * map->reg_stride * data->irq_reg_stride),
 341				   &data->status_buf[b]);
 342	} else {
 343		subreg = &chip->sub_reg_offsets[b];
 344		for (i = 0; i < subreg->num_regs; i++) {
 345			unsigned int offset = subreg->offset[i];
 346
 347			ret = regmap_read(map, chip->status_base + offset,
 348					  &data->status_buf[offset]);
 349			if (ret)
 350				break;
 351		}
 352	}
 353	return ret;
 354}
 355
 356static irqreturn_t regmap_irq_thread(int irq, void *d)
 357{
 358	struct regmap_irq_chip_data *data = d;
 359	const struct regmap_irq_chip *chip = data->chip;
 360	struct regmap *map = data->map;
 361	int ret, i;
 362	bool handled = false;
 363	u32 reg;
 364
 365	if (chip->handle_pre_irq)
 366		chip->handle_pre_irq(chip->irq_drv_data);
 367
 368	if (chip->runtime_pm) {
 369		ret = pm_runtime_get_sync(map->dev);
 370		if (ret < 0) {
 371			dev_err(map->dev, "IRQ thread failed to resume: %d\n",
 372				ret);
 373			goto exit;
 374		}
 375	}
 376
 377	/*
 378	 * Read only registers with active IRQs if the chip has 'main status
 379	 * register'. Else read in the statuses, using a single bulk read if
 380	 * possible in order to reduce the I/O overheads.
 
 
 381	 */
 382
 383	if (chip->num_main_regs) {
 384		unsigned int max_main_bits;
 385		unsigned long size;
 386
 387		size = chip->num_regs * sizeof(unsigned int);
 388
 389		max_main_bits = (chip->num_main_status_bits) ?
 390				 chip->num_main_status_bits : chip->num_regs;
 391		/* Clear the status buf as we don't read all status regs */
 392		memset(data->status_buf, 0, size);
 393
 394		/* We could support bulk read for main status registers
 395		 * but I don't expect to see devices with really many main
 396		 * status registers so let's only support single reads for the
 397		 * sake of simplicity. and add bulk reads only if needed
 398		 */
 399		for (i = 0; i < chip->num_main_regs; i++) {
 400			ret = regmap_read(map, chip->main_status +
 401				  (i * map->reg_stride
 402				   * data->irq_reg_stride),
 403				  &data->main_status_buf[i]);
 404			if (ret) {
 405				dev_err(map->dev,
 406					"Failed to read IRQ status %d\n",
 407					ret);
 408				goto exit;
 409			}
 410		}
 411
 412		/* Read sub registers with active IRQs */
 413		for (i = 0; i < chip->num_main_regs; i++) {
 414			unsigned int b;
 415			const unsigned long mreg = data->main_status_buf[i];
 416
 417			for_each_set_bit(b, &mreg, map->format.val_bytes * 8) {
 418				if (i * map->format.val_bytes * 8 + b >
 419				    max_main_bits)
 420					break;
 421				ret = read_sub_irq_data(data, b);
 422
 423				if (ret != 0) {
 424					dev_err(map->dev,
 425						"Failed to read IRQ status %d\n",
 426						ret);
 427					goto exit;
 428				}
 429			}
 430
 431		}
 432	} else if (!map->use_single_read && map->reg_stride == 1 &&
 433		   data->irq_reg_stride == 1) {
 434
 435		u8 *buf8 = data->status_reg_buf;
 436		u16 *buf16 = data->status_reg_buf;
 437		u32 *buf32 = data->status_reg_buf;
 438
 439		BUG_ON(!data->status_reg_buf);
 440
 441		ret = regmap_bulk_read(map, chip->status_base,
 442				       data->status_reg_buf,
 443				       chip->num_regs);
 444		if (ret != 0) {
 445			dev_err(map->dev, "Failed to read IRQ status: %d\n",
 446				ret);
 447			goto exit;
 448		}
 449
 450		for (i = 0; i < data->chip->num_regs; i++) {
 451			switch (map->format.val_bytes) {
 452			case 1:
 453				data->status_buf[i] = buf8[i];
 454				break;
 455			case 2:
 456				data->status_buf[i] = buf16[i];
 457				break;
 458			case 4:
 459				data->status_buf[i] = buf32[i];
 460				break;
 461			default:
 462				BUG();
 463				goto exit;
 464			}
 465		}
 466
 467	} else {
 468		for (i = 0; i < data->chip->num_regs; i++) {
 469			ret = regmap_read(map, chip->status_base +
 470					  (i * map->reg_stride
 471					   * data->irq_reg_stride),
 472					  &data->status_buf[i]);
 473
 474			if (ret != 0) {
 475				dev_err(map->dev,
 476					"Failed to read IRQ status: %d\n",
 477					ret);
 478				goto exit;
 479			}
 480		}
 481	}
 482
 483	/*
 484	 * Ignore masked IRQs and ack if we need to; we ack early so
 485	 * there is no race between handling and acknowleding the
 486	 * interrupt.  We assume that typically few of the interrupts
 487	 * will fire simultaneously so don't worry about overhead from
 488	 * doing a write per register.
 489	 */
 490	for (i = 0; i < data->chip->num_regs; i++) {
 491		data->status_buf[i] &= ~data->mask_buf[i];
 492
 493		if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 494			reg = chip->ack_base +
 495				(i * map->reg_stride * data->irq_reg_stride);
 496			ret = regmap_write(map, reg, data->status_buf[i]);
 
 497			if (ret != 0)
 498				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 499					reg, ret);
 
 500		}
 501	}
 502
 503	for (i = 0; i < chip->num_irqs; i++) {
 504		if (data->status_buf[chip->irqs[i].reg_offset /
 505				     map->reg_stride] & chip->irqs[i].mask) {
 506			handle_nested_irq(irq_find_mapping(data->domain, i));
 507			handled = true;
 508		}
 509	}
 510
 511exit:
 512	if (chip->runtime_pm)
 513		pm_runtime_put(map->dev);
 514
 515	if (chip->handle_post_irq)
 516		chip->handle_post_irq(chip->irq_drv_data);
 517
 518	if (handled)
 519		return IRQ_HANDLED;
 520	else
 521		return IRQ_NONE;
 522}
 523
 524static int regmap_irq_map(struct irq_domain *h, unsigned int virq,
 525			  irq_hw_number_t hw)
 526{
 527	struct regmap_irq_chip_data *data = h->host_data;
 528
 529	irq_set_chip_data(virq, data);
 530	irq_set_chip(virq, &data->irq_chip);
 531	irq_set_nested_thread(virq, 1);
 532	irq_set_parent(virq, data->irq);
 
 
 
 
 
 533	irq_set_noprobe(virq);
 
 534
 535	return 0;
 536}
 537
 538static const struct irq_domain_ops regmap_domain_ops = {
 539	.map	= regmap_irq_map,
 540	.xlate	= irq_domain_xlate_onetwocell,
 541};
 542
 543/**
 544 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
 545 *
 546 * @fwnode: The firmware node where the IRQ domain should be added to.
 547 * @map: The regmap for the device.
 548 * @irq: The IRQ the device uses to signal interrupts.
 549 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 550 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 551 * @chip: Configuration for the interrupt controller.
 552 * @data: Runtime data structure for the controller, allocated on success.
 553 *
 554 * Returns 0 on success or an errno on failure.
 555 *
 556 * In order for this to be efficient the chip really should use a
 557 * register cache.  The chip driver is responsible for restoring the
 558 * register values used by the IRQ controller over suspend and resume.
 559 */
 560int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode,
 561			       struct regmap *map, int irq,
 562			       int irq_flags, int irq_base,
 563			       const struct regmap_irq_chip *chip,
 564			       struct regmap_irq_chip_data **data)
 565{
 566	struct regmap_irq_chip_data *d;
 567	int i;
 568	int ret = -ENOMEM;
 569	int num_type_reg;
 570	u32 reg;
 571	u32 unmask_offset;
 572
 573	if (chip->num_regs <= 0)
 574		return -EINVAL;
 575
 576	if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack))
 577		return -EINVAL;
 578
 579	for (i = 0; i < chip->num_irqs; i++) {
 580		if (chip->irqs[i].reg_offset % map->reg_stride)
 581			return -EINVAL;
 582		if (chip->irqs[i].reg_offset / map->reg_stride >=
 583		    chip->num_regs)
 584			return -EINVAL;
 585	}
 586
 587	if (irq_base) {
 588		irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0);
 589		if (irq_base < 0) {
 590			dev_warn(map->dev, "Failed to allocate IRQs: %d\n",
 591				 irq_base);
 592			return irq_base;
 593		}
 594	}
 595
 596	d = kzalloc(sizeof(*d), GFP_KERNEL);
 597	if (!d)
 598		return -ENOMEM;
 599
 600	if (chip->num_main_regs) {
 601		d->main_status_buf = kcalloc(chip->num_main_regs,
 602					     sizeof(unsigned int),
 603					     GFP_KERNEL);
 604
 605		if (!d->main_status_buf)
 606			goto err_alloc;
 607	}
 608
 609	d->status_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 610				GFP_KERNEL);
 611	if (!d->status_buf)
 612		goto err_alloc;
 613
 614	d->mask_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 615			      GFP_KERNEL);
 616	if (!d->mask_buf)
 617		goto err_alloc;
 618
 619	d->mask_buf_def = kcalloc(chip->num_regs, sizeof(unsigned int),
 620				  GFP_KERNEL);
 621	if (!d->mask_buf_def)
 622		goto err_alloc;
 623
 624	if (chip->wake_base) {
 625		d->wake_buf = kcalloc(chip->num_regs, sizeof(unsigned int),
 626				      GFP_KERNEL);
 627		if (!d->wake_buf)
 628			goto err_alloc;
 629	}
 630
 631	num_type_reg = chip->type_in_mask ? chip->num_regs : chip->num_type_reg;
 632	if (num_type_reg) {
 633		d->type_buf_def = kcalloc(num_type_reg,
 634					  sizeof(unsigned int), GFP_KERNEL);
 635		if (!d->type_buf_def)
 636			goto err_alloc;
 637
 638		d->type_buf = kcalloc(num_type_reg, sizeof(unsigned int),
 639				      GFP_KERNEL);
 640		if (!d->type_buf)
 641			goto err_alloc;
 642	}
 643
 644	d->irq_chip = regmap_irq_chip;
 645	d->irq_chip.name = chip->name;
 646	d->irq = irq;
 647	d->map = map;
 648	d->chip = chip;
 649	d->irq_base = irq_base;
 650
 651	if (chip->irq_reg_stride)
 652		d->irq_reg_stride = chip->irq_reg_stride;
 653	else
 654		d->irq_reg_stride = 1;
 655
 656	if (chip->type_reg_stride)
 657		d->type_reg_stride = chip->type_reg_stride;
 658	else
 659		d->type_reg_stride = 1;
 660
 661	if (!map->use_single_read && map->reg_stride == 1 &&
 662	    d->irq_reg_stride == 1) {
 663		d->status_reg_buf = kmalloc_array(chip->num_regs,
 664						  map->format.val_bytes,
 665						  GFP_KERNEL);
 666		if (!d->status_reg_buf)
 667			goto err_alloc;
 668	}
 669
 670	mutex_init(&d->lock);
 671
 672	for (i = 0; i < chip->num_irqs; i++)
 673		d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride]
 674			|= chip->irqs[i].mask;
 675
 676	/* Mask all the interrupts by default */
 677	for (i = 0; i < chip->num_regs; i++) {
 678		d->mask_buf[i] = d->mask_buf_def[i];
 679		if (!chip->mask_base)
 680			continue;
 681
 682		reg = chip->mask_base +
 683			(i * map->reg_stride * d->irq_reg_stride);
 684		if (chip->mask_invert)
 685			ret = regmap_irq_update_bits(d, reg,
 686					 d->mask_buf[i], ~d->mask_buf[i]);
 687		else if (d->chip->unmask_base) {
 688			unmask_offset = d->chip->unmask_base -
 689					d->chip->mask_base;
 690			ret = regmap_irq_update_bits(d,
 691					reg + unmask_offset,
 692					d->mask_buf[i],
 693					d->mask_buf[i]);
 694		} else
 695			ret = regmap_irq_update_bits(d, reg,
 696					 d->mask_buf[i], d->mask_buf[i]);
 697		if (ret != 0) {
 698			dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 699				reg, ret);
 700			goto err_alloc;
 701		}
 702
 703		if (!chip->init_ack_masked)
 704			continue;
 705
 706		/* Ack masked but set interrupts */
 707		reg = chip->status_base +
 708			(i * map->reg_stride * d->irq_reg_stride);
 709		ret = regmap_read(map, reg, &d->status_buf[i]);
 710		if (ret != 0) {
 711			dev_err(map->dev, "Failed to read IRQ status: %d\n",
 712				ret);
 713			goto err_alloc;
 714		}
 715
 716		if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) {
 717			reg = chip->ack_base +
 718				(i * map->reg_stride * d->irq_reg_stride);
 719			if (chip->ack_invert)
 720				ret = regmap_write(map, reg,
 721					~(d->status_buf[i] & d->mask_buf[i]));
 722			else
 723				ret = regmap_write(map, reg,
 724					d->status_buf[i] & d->mask_buf[i]);
 725			if (ret != 0) {
 726				dev_err(map->dev, "Failed to ack 0x%x: %d\n",
 727					reg, ret);
 728				goto err_alloc;
 729			}
 730		}
 731	}
 732
 733	/* Wake is disabled by default */
 734	if (d->wake_buf) {
 735		for (i = 0; i < chip->num_regs; i++) {
 736			d->wake_buf[i] = d->mask_buf_def[i];
 737			reg = chip->wake_base +
 738				(i * map->reg_stride * d->irq_reg_stride);
 739
 740			if (chip->wake_invert)
 741				ret = regmap_irq_update_bits(d, reg,
 742							 d->mask_buf_def[i],
 743							 0);
 744			else
 745				ret = regmap_irq_update_bits(d, reg,
 746							 d->mask_buf_def[i],
 747							 d->wake_buf[i]);
 748			if (ret != 0) {
 749				dev_err(map->dev, "Failed to set masks in 0x%x: %d\n",
 750					reg, ret);
 751				goto err_alloc;
 752			}
 753		}
 754	}
 755
 756	if (chip->num_type_reg && !chip->type_in_mask) {
 757		for (i = 0; i < chip->num_type_reg; ++i) {
 758			reg = chip->type_base +
 759				(i * map->reg_stride * d->type_reg_stride);
 760
 761			ret = regmap_read(map, reg, &d->type_buf_def[i]);
 762
 763			if (d->chip->type_invert)
 764				d->type_buf_def[i] = ~d->type_buf_def[i];
 765
 766			if (ret) {
 767				dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n",
 768					reg, ret);
 769				goto err_alloc;
 770			}
 771		}
 772	}
 773
 774	if (irq_base)
 775		d->domain = irq_domain_add_legacy(to_of_node(fwnode),
 776						  chip->num_irqs, irq_base,
 777						  0, &regmap_domain_ops, d);
 778	else
 779		d->domain = irq_domain_add_linear(to_of_node(fwnode),
 780						  chip->num_irqs,
 781						  &regmap_domain_ops, d);
 782	if (!d->domain) {
 783		dev_err(map->dev, "Failed to create IRQ domain\n");
 784		ret = -ENOMEM;
 785		goto err_alloc;
 786	}
 787
 788	ret = request_threaded_irq(irq, NULL, regmap_irq_thread,
 789				   irq_flags | IRQF_ONESHOT,
 790				   chip->name, d);
 791	if (ret != 0) {
 792		dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n",
 793			irq, chip->name, ret);
 794		goto err_domain;
 795	}
 796
 797	*data = d;
 798
 799	return 0;
 800
 801err_domain:
 802	/* Should really dispose of the domain but... */
 803err_alloc:
 804	kfree(d->type_buf);
 805	kfree(d->type_buf_def);
 806	kfree(d->wake_buf);
 807	kfree(d->mask_buf_def);
 808	kfree(d->mask_buf);
 809	kfree(d->status_buf);
 810	kfree(d->status_reg_buf);
 811	kfree(d);
 812	return ret;
 813}
 814EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode);
 815
 816/**
 817 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
 818 *
 819 * @map: The regmap for the device.
 820 * @irq: The IRQ the device uses to signal interrupts.
 821 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 822 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 823 * @chip: Configuration for the interrupt controller.
 824 * @data: Runtime data structure for the controller, allocated on success.
 825 *
 826 * Returns 0 on success or an errno on failure.
 827 *
 828 * This is the same as regmap_add_irq_chip_fwnode, except that the firmware
 829 * node of the regmap is used.
 830 */
 831int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
 832			int irq_base, const struct regmap_irq_chip *chip,
 833			struct regmap_irq_chip_data **data)
 834{
 835	return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq,
 836					  irq_flags, irq_base, chip, data);
 837}
 838EXPORT_SYMBOL_GPL(regmap_add_irq_chip);
 839
 840/**
 841 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
 842 *
 843 * @irq: Primary IRQ for the device
 844 * @d: &regmap_irq_chip_data allocated by regmap_add_irq_chip()
 845 *
 846 * This function also disposes of all mapped IRQs on the chip.
 847 */
 848void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
 849{
 850	unsigned int virq;
 851	int hwirq;
 852
 853	if (!d)
 854		return;
 855
 856	free_irq(irq, d);
 857
 858	/* Dispose all virtual irq from irq domain before removing it */
 859	for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) {
 860		/* Ignore hwirq if holes in the IRQ list */
 861		if (!d->chip->irqs[hwirq].mask)
 862			continue;
 863
 864		/*
 865		 * Find the virtual irq of hwirq on chip and if it is
 866		 * there then dispose it
 867		 */
 868		virq = irq_find_mapping(d->domain, hwirq);
 869		if (virq)
 870			irq_dispose_mapping(virq);
 871	}
 872
 873	irq_domain_remove(d->domain);
 874	kfree(d->type_buf);
 875	kfree(d->type_buf_def);
 876	kfree(d->wake_buf);
 877	kfree(d->mask_buf_def);
 878	kfree(d->mask_buf);
 879	kfree(d->status_reg_buf);
 880	kfree(d->status_buf);
 881	kfree(d);
 882}
 883EXPORT_SYMBOL_GPL(regmap_del_irq_chip);
 884
 885static void devm_regmap_irq_chip_release(struct device *dev, void *res)
 886{
 887	struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res;
 888
 889	regmap_del_irq_chip(d->irq, d);
 890}
 891
 892static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data)
 893
 894{
 895	struct regmap_irq_chip_data **r = res;
 896
 897	if (!r || !*r) {
 898		WARN_ON(!r || !*r);
 899		return 0;
 900	}
 901	return *r == data;
 902}
 903
 904/**
 905 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
 906 *
 907 * @dev: The device pointer on which irq_chip belongs to.
 908 * @fwnode: The firmware node where the IRQ domain should be added to.
 909 * @map: The regmap for the device.
 910 * @irq: The IRQ the device uses to signal interrupts
 911 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 912 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 913 * @chip: Configuration for the interrupt controller.
 914 * @data: Runtime data structure for the controller, allocated on success
 915 *
 916 * Returns 0 on success or an errno on failure.
 917 *
 918 * The &regmap_irq_chip_data will be automatically released when the device is
 919 * unbound.
 920 */
 921int devm_regmap_add_irq_chip_fwnode(struct device *dev,
 922				    struct fwnode_handle *fwnode,
 923				    struct regmap *map, int irq,
 924				    int irq_flags, int irq_base,
 925				    const struct regmap_irq_chip *chip,
 926				    struct regmap_irq_chip_data **data)
 927{
 928	struct regmap_irq_chip_data **ptr, *d;
 929	int ret;
 930
 931	ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr),
 932			   GFP_KERNEL);
 933	if (!ptr)
 934		return -ENOMEM;
 935
 936	ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base,
 937					 chip, &d);
 938	if (ret < 0) {
 939		devres_free(ptr);
 940		return ret;
 941	}
 942
 943	*ptr = d;
 944	devres_add(dev, ptr);
 945	*data = d;
 946	return 0;
 947}
 948EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode);
 949
 950/**
 951 * devm_regmap_add_irq_chip() - Resource manager regmap_add_irq_chip()
 952 *
 953 * @dev: The device pointer on which irq_chip belongs to.
 954 * @map: The regmap for the device.
 955 * @irq: The IRQ the device uses to signal interrupts
 956 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
 957 * @irq_base: Allocate at specific IRQ number if irq_base > 0.
 958 * @chip: Configuration for the interrupt controller.
 959 * @data: Runtime data structure for the controller, allocated on success
 960 *
 961 * Returns 0 on success or an errno on failure.
 962 *
 963 * The &regmap_irq_chip_data will be automatically released when the device is
 964 * unbound.
 965 */
 966int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq,
 967			     int irq_flags, int irq_base,
 968			     const struct regmap_irq_chip *chip,
 969			     struct regmap_irq_chip_data **data)
 970{
 971	return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map,
 972					       irq, irq_flags, irq_base, chip,
 973					       data);
 974}
 975EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip);
 976
 977/**
 978 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
 979 *
 980 * @dev: Device for which which resource was allocated.
 981 * @irq: Primary IRQ for the device.
 982 * @data: &regmap_irq_chip_data allocated by regmap_add_irq_chip().
 983 *
 984 * A resource managed version of regmap_del_irq_chip().
 985 */
 986void devm_regmap_del_irq_chip(struct device *dev, int irq,
 987			      struct regmap_irq_chip_data *data)
 988{
 989	int rc;
 990
 991	WARN_ON(irq != data->irq);
 992	rc = devres_release(dev, devm_regmap_irq_chip_release,
 993			    devm_regmap_irq_chip_match, data);
 994
 995	if (rc != 0)
 996		WARN_ON(rc);
 997}
 998EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip);
 999
1000/**
1001 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1002 *
1003 * @data: regmap irq controller to operate on.
1004 *
1005 * Useful for drivers to request their own IRQs.
 
 
1006 */
1007int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data)
1008{
1009	WARN_ON(!data->irq_base);
1010	return data->irq_base;
1011}
1012EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
1013
1014/**
1015 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1016 *
1017 * @data: regmap irq controller to operate on.
1018 * @irq: index of the interrupt requested in the chip IRQs.
1019 *
1020 * Useful for drivers to request their own IRQs.
 
 
 
1021 */
1022int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
1023{
1024	/* Handle holes in the IRQ list */
1025	if (!data->chip->irqs[irq].mask)
1026		return -EINVAL;
1027
1028	return irq_create_mapping(data->domain, irq);
1029}
1030EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
1031
1032/**
1033 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1034 *
1035 * @data: regmap_irq controller to operate on.
1036 *
1037 * Useful for drivers to request their own IRQs and for integration
1038 * with subsystems.  For ease of integration NULL is accepted as a
1039 * domain, allowing devices to just call this even if no domain is
1040 * allocated.
1041 */
1042struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data)
1043{
1044	if (data)
1045		return data->domain;
1046	else
1047		return NULL;
1048}
1049EXPORT_SYMBOL_GPL(regmap_irq_get_domain);