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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35#include "hda_controller.h"
36
37static bool static_hdmi_pcm;
38module_param(static_hdmi_pcm, bool, 0644);
39MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41static bool enable_acomp = true;
42module_param(enable_acomp, bool, 0444);
43MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45static bool enable_silent_stream =
46IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47module_param(enable_silent_stream, bool, 0644);
48MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50struct hdmi_spec_per_cvt {
51 hda_nid_t cvt_nid;
52 int assigned;
53 unsigned int channels_min;
54 unsigned int channels_max;
55 u32 rates;
56 u64 formats;
57 unsigned int maxbps;
58};
59
60/* max. connections to a widget */
61#define HDA_MAX_CONNECTIONS 32
62
63struct hdmi_spec_per_pin {
64 hda_nid_t pin_nid;
65 int dev_id;
66 /* pin idx, different device entries on the same pin use the same idx */
67 int pin_nid_idx;
68 int num_mux_nids;
69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
70 int mux_idx;
71 hda_nid_t cvt_nid;
72
73 struct hda_codec *codec;
74 struct hdmi_eld sink_eld;
75 struct mutex lock;
76 struct delayed_work work;
77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
79 int repoll_count;
80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
82 bool non_pcm;
83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
85#ifdef CONFIG_SND_PROC_FS
86 struct snd_info_entry *proc_entry;
87#endif
88};
89
90/* operations used by generic code that can be overridden by patches */
91struct hdmi_ops {
92 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
93 int dev_id, unsigned char *buf, int *eld_size);
94
95 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int dev_id,
97 int ca, int active_channels, int conn_type);
98
99 /* enable/disable HBR (HD passthrough) */
100 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int dev_id, bool hbr);
102
103 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
104 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
105 int format);
106
107 void (*pin_cvt_fixup)(struct hda_codec *codec,
108 struct hdmi_spec_per_pin *per_pin,
109 hda_nid_t cvt_nid);
110};
111
112struct hdmi_pcm {
113 struct hda_pcm *pcm;
114 struct snd_jack *jack;
115 struct snd_kcontrol *eld_ctl;
116};
117
118struct hdmi_spec {
119 struct hda_codec *codec;
120 int num_cvts;
121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
122 hda_nid_t cvt_nids[4]; /* only for haswell fix */
123
124 /*
125 * num_pins is the number of virtual pins
126 * for example, there are 3 pins, and each pin
127 * has 4 device entries, then the num_pins is 12
128 */
129 int num_pins;
130 /*
131 * num_nids is the number of real pins
132 * In the above example, num_nids is 3
133 */
134 int num_nids;
135 /*
136 * dev_num is the number of device entries
137 * on each pin.
138 * In the above example, dev_num is 4
139 */
140 int dev_num;
141 struct snd_array pins; /* struct hdmi_spec_per_pin */
142 struct hdmi_pcm pcm_rec[16];
143 struct mutex pcm_lock;
144 struct mutex bind_lock; /* for audio component binding */
145 /* pcm_bitmap means which pcms have been assigned to pins*/
146 unsigned long pcm_bitmap;
147 int pcm_used; /* counter of pcm_rec[] */
148 /* bitmap shows whether the pcm is opened in user space
149 * bit 0 means the first playback PCM (PCM3);
150 * bit 1 means the second playback PCM, and so on.
151 */
152 unsigned long pcm_in_use;
153
154 struct hdmi_eld temp_eld;
155 struct hdmi_ops ops;
156
157 bool dyn_pin_out;
158 bool dyn_pcm_assign;
159 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
160 /*
161 * Non-generic VIA/NVIDIA specific
162 */
163 struct hda_multi_out multiout;
164 struct hda_pcm_stream pcm_playback;
165
166 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
167 bool acomp_registered; /* audio component registered in this driver */
168 bool force_connect; /* force connectivity */
169 struct drm_audio_component_audio_ops drm_audio_ops;
170 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
171
172 struct hdac_chmap chmap;
173 hda_nid_t vendor_nid;
174 const int *port_map;
175 int port_num;
176 bool send_silent_stream; /* Flag to enable silent stream feature */
177};
178
179#ifdef CONFIG_SND_HDA_COMPONENT
180static inline bool codec_has_acomp(struct hda_codec *codec)
181{
182 struct hdmi_spec *spec = codec->spec;
183 return spec->use_acomp_notifier;
184}
185#else
186#define codec_has_acomp(codec) false
187#endif
188
189struct hdmi_audio_infoframe {
190 u8 type; /* 0x84 */
191 u8 ver; /* 0x01 */
192 u8 len; /* 0x0a */
193
194 u8 checksum;
195
196 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
197 u8 SS01_SF24;
198 u8 CXT04;
199 u8 CA;
200 u8 LFEPBL01_LSV36_DM_INH7;
201};
202
203struct dp_audio_infoframe {
204 u8 type; /* 0x84 */
205 u8 len; /* 0x1b */
206 u8 ver; /* 0x11 << 2 */
207
208 u8 CC02_CT47; /* match with HDMI infoframe from this on */
209 u8 SS01_SF24;
210 u8 CXT04;
211 u8 CA;
212 u8 LFEPBL01_LSV36_DM_INH7;
213};
214
215union audio_infoframe {
216 struct hdmi_audio_infoframe hdmi;
217 struct dp_audio_infoframe dp;
218 u8 bytes[0];
219};
220
221/*
222 * HDMI routines
223 */
224
225#define get_pin(spec, idx) \
226 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
227#define get_cvt(spec, idx) \
228 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
229/* obtain hdmi_pcm object assigned to idx */
230#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
231/* obtain hda_pcm object assigned to idx */
232#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
233
234static int pin_id_to_pin_index(struct hda_codec *codec,
235 hda_nid_t pin_nid, int dev_id)
236{
237 struct hdmi_spec *spec = codec->spec;
238 int pin_idx;
239 struct hdmi_spec_per_pin *per_pin;
240
241 /*
242 * (dev_id == -1) means it is NON-MST pin
243 * return the first virtual pin on this port
244 */
245 if (dev_id == -1)
246 dev_id = 0;
247
248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
249 per_pin = get_pin(spec, pin_idx);
250 if ((per_pin->pin_nid == pin_nid) &&
251 (per_pin->dev_id == dev_id))
252 return pin_idx;
253 }
254
255 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
256 return -EINVAL;
257}
258
259static int hinfo_to_pcm_index(struct hda_codec *codec,
260 struct hda_pcm_stream *hinfo)
261{
262 struct hdmi_spec *spec = codec->spec;
263 int pcm_idx;
264
265 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
266 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
267 return pcm_idx;
268
269 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
270 return -EINVAL;
271}
272
273static int hinfo_to_pin_index(struct hda_codec *codec,
274 struct hda_pcm_stream *hinfo)
275{
276 struct hdmi_spec *spec = codec->spec;
277 struct hdmi_spec_per_pin *per_pin;
278 int pin_idx;
279
280 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
281 per_pin = get_pin(spec, pin_idx);
282 if (per_pin->pcm &&
283 per_pin->pcm->pcm->stream == hinfo)
284 return pin_idx;
285 }
286
287 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
288 hinfo_to_pcm_index(codec, hinfo));
289 return -EINVAL;
290}
291
292static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
293 int pcm_idx)
294{
295 int i;
296 struct hdmi_spec_per_pin *per_pin;
297
298 for (i = 0; i < spec->num_pins; i++) {
299 per_pin = get_pin(spec, i);
300 if (per_pin->pcm_idx == pcm_idx)
301 return per_pin;
302 }
303 return NULL;
304}
305
306static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
307{
308 struct hdmi_spec *spec = codec->spec;
309 int cvt_idx;
310
311 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
312 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
313 return cvt_idx;
314
315 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
316 return -EINVAL;
317}
318
319static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
320 struct snd_ctl_elem_info *uinfo)
321{
322 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
323 struct hdmi_spec *spec = codec->spec;
324 struct hdmi_spec_per_pin *per_pin;
325 struct hdmi_eld *eld;
326 int pcm_idx;
327
328 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
329
330 pcm_idx = kcontrol->private_value;
331 mutex_lock(&spec->pcm_lock);
332 per_pin = pcm_idx_to_pin(spec, pcm_idx);
333 if (!per_pin) {
334 /* no pin is bound to the pcm */
335 uinfo->count = 0;
336 goto unlock;
337 }
338 eld = &per_pin->sink_eld;
339 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
340
341 unlock:
342 mutex_unlock(&spec->pcm_lock);
343 return 0;
344}
345
346static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
350 struct hdmi_spec *spec = codec->spec;
351 struct hdmi_spec_per_pin *per_pin;
352 struct hdmi_eld *eld;
353 int pcm_idx;
354 int err = 0;
355
356 pcm_idx = kcontrol->private_value;
357 mutex_lock(&spec->pcm_lock);
358 per_pin = pcm_idx_to_pin(spec, pcm_idx);
359 if (!per_pin) {
360 /* no pin is bound to the pcm */
361 memset(ucontrol->value.bytes.data, 0,
362 ARRAY_SIZE(ucontrol->value.bytes.data));
363 goto unlock;
364 }
365
366 eld = &per_pin->sink_eld;
367 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
368 eld->eld_size > ELD_MAX_SIZE) {
369 snd_BUG();
370 err = -EINVAL;
371 goto unlock;
372 }
373
374 memset(ucontrol->value.bytes.data, 0,
375 ARRAY_SIZE(ucontrol->value.bytes.data));
376 if (eld->eld_valid)
377 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
378 eld->eld_size);
379
380 unlock:
381 mutex_unlock(&spec->pcm_lock);
382 return err;
383}
384
385static const struct snd_kcontrol_new eld_bytes_ctl = {
386 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
387 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
388 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
389 .name = "ELD",
390 .info = hdmi_eld_ctl_info,
391 .get = hdmi_eld_ctl_get,
392};
393
394static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
395 int device)
396{
397 struct snd_kcontrol *kctl;
398 struct hdmi_spec *spec = codec->spec;
399 int err;
400
401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
402 if (!kctl)
403 return -ENOMEM;
404 kctl->private_value = pcm_idx;
405 kctl->id.device = device;
406
407 /* no pin nid is associated with the kctl now
408 * tbd: associate pin nid to eld ctl later
409 */
410 err = snd_hda_ctl_add(codec, 0, kctl);
411 if (err < 0)
412 return err;
413
414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
415 return 0;
416}
417
418#ifdef BE_PARANOID
419static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
420 int *packet_index, int *byte_index)
421{
422 int val;
423
424 val = snd_hda_codec_read(codec, pin_nid, 0,
425 AC_VERB_GET_HDMI_DIP_INDEX, 0);
426
427 *packet_index = val >> 5;
428 *byte_index = val & 0x1f;
429}
430#endif
431
432static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
433 int packet_index, int byte_index)
434{
435 int val;
436
437 val = (packet_index << 5) | (byte_index & 0x1f);
438
439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
440}
441
442static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
443 unsigned char val)
444{
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
446}
447
448static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
449{
450 struct hdmi_spec *spec = codec->spec;
451 int pin_out;
452
453 /* Unmute */
454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
455 snd_hda_codec_write(codec, pin_nid, 0,
456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
457
458 if (spec->dyn_pin_out)
459 /* Disable pin out until stream is active */
460 pin_out = 0;
461 else
462 /* Enable pin out: some machines with GM965 gets broken output
463 * when the pin is disabled or changed while using with HDMI
464 */
465 pin_out = PIN_OUT;
466
467 snd_hda_codec_write(codec, pin_nid, 0,
468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
469}
470
471/*
472 * ELD proc files
473 */
474
475#ifdef CONFIG_SND_PROC_FS
476static void print_eld_info(struct snd_info_entry *entry,
477 struct snd_info_buffer *buffer)
478{
479 struct hdmi_spec_per_pin *per_pin = entry->private_data;
480
481 mutex_lock(&per_pin->lock);
482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
483 mutex_unlock(&per_pin->lock);
484}
485
486static void write_eld_info(struct snd_info_entry *entry,
487 struct snd_info_buffer *buffer)
488{
489 struct hdmi_spec_per_pin *per_pin = entry->private_data;
490
491 mutex_lock(&per_pin->lock);
492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
493 mutex_unlock(&per_pin->lock);
494}
495
496static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
497{
498 char name[32];
499 struct hda_codec *codec = per_pin->codec;
500 struct snd_info_entry *entry;
501 int err;
502
503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
504 err = snd_card_proc_new(codec->card, name, &entry);
505 if (err < 0)
506 return err;
507
508 snd_info_set_text_ops(entry, per_pin, print_eld_info);
509 entry->c.text.write = write_eld_info;
510 entry->mode |= 0200;
511 per_pin->proc_entry = entry;
512
513 return 0;
514}
515
516static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
517{
518 if (!per_pin->codec->bus->shutdown) {
519 snd_info_free_entry(per_pin->proc_entry);
520 per_pin->proc_entry = NULL;
521 }
522}
523#else
524static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
525 int index)
526{
527 return 0;
528}
529static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
530{
531}
532#endif
533
534/*
535 * Audio InfoFrame routines
536 */
537
538/*
539 * Enable Audio InfoFrame Transmission
540 */
541static void hdmi_start_infoframe_trans(struct hda_codec *codec,
542 hda_nid_t pin_nid)
543{
544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
546 AC_DIPXMIT_BEST);
547}
548
549/*
550 * Disable Audio InfoFrame Transmission
551 */
552static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
553 hda_nid_t pin_nid)
554{
555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
557 AC_DIPXMIT_DISABLE);
558}
559
560static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
561{
562#ifdef CONFIG_SND_DEBUG_VERBOSE
563 int i;
564 int size;
565
566 size = snd_hdmi_get_eld_size(codec, pin_nid);
567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
568
569 for (i = 0; i < 8; i++) {
570 size = snd_hda_codec_read(codec, pin_nid, 0,
571 AC_VERB_GET_HDMI_DIP_SIZE, i);
572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
573 }
574#endif
575}
576
577static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
578{
579#ifdef BE_PARANOID
580 int i, j;
581 int size;
582 int pi, bi;
583 for (i = 0; i < 8; i++) {
584 size = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_DIP_SIZE, i);
586 if (size == 0)
587 continue;
588
589 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
590 for (j = 1; j < 1000; j++) {
591 hdmi_write_dip_byte(codec, pin_nid, 0x0);
592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
593 if (pi != i)
594 codec_dbg(codec, "dip index %d: %d != %d\n",
595 bi, pi, i);
596 if (bi == 0) /* byte index wrapped around */
597 break;
598 }
599 codec_dbg(codec,
600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
601 i, size, j);
602 }
603#endif
604}
605
606static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
607{
608 u8 *bytes = (u8 *)hdmi_ai;
609 u8 sum = 0;
610 int i;
611
612 hdmi_ai->checksum = 0;
613
614 for (i = 0; i < sizeof(*hdmi_ai); i++)
615 sum += bytes[i];
616
617 hdmi_ai->checksum = -sum;
618}
619
620static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
621 hda_nid_t pin_nid,
622 u8 *dip, int size)
623{
624 int i;
625
626 hdmi_debug_dip_size(codec, pin_nid);
627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
628
629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
630 for (i = 0; i < size; i++)
631 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
632}
633
634static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
635 u8 *dip, int size)
636{
637 u8 val;
638 int i;
639
640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
641 != AC_DIPXMIT_BEST)
642 return false;
643
644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
645 for (i = 0; i < size; i++) {
646 val = snd_hda_codec_read(codec, pin_nid, 0,
647 AC_VERB_GET_HDMI_DIP_DATA, 0);
648 if (val != dip[i])
649 return false;
650 }
651
652 return true;
653}
654
655static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
656 int dev_id, unsigned char *buf, int *eld_size)
657{
658 snd_hda_set_dev_select(codec, nid, dev_id);
659
660 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
661}
662
663static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
664 hda_nid_t pin_nid, int dev_id,
665 int ca, int active_channels,
666 int conn_type)
667{
668 union audio_infoframe ai;
669
670 memset(&ai, 0, sizeof(ai));
671 if (conn_type == 0) { /* HDMI */
672 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
673
674 hdmi_ai->type = 0x84;
675 hdmi_ai->ver = 0x01;
676 hdmi_ai->len = 0x0a;
677 hdmi_ai->CC02_CT47 = active_channels - 1;
678 hdmi_ai->CA = ca;
679 hdmi_checksum_audio_infoframe(hdmi_ai);
680 } else if (conn_type == 1) { /* DisplayPort */
681 struct dp_audio_infoframe *dp_ai = &ai.dp;
682
683 dp_ai->type = 0x84;
684 dp_ai->len = 0x1b;
685 dp_ai->ver = 0x11 << 2;
686 dp_ai->CC02_CT47 = active_channels - 1;
687 dp_ai->CA = ca;
688 } else {
689 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
690 pin_nid);
691 return;
692 }
693
694 snd_hda_set_dev_select(codec, pin_nid, dev_id);
695
696 /*
697 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
698 * sizeof(*dp_ai) to avoid partial match/update problems when
699 * the user switches between HDMI/DP monitors.
700 */
701 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
702 sizeof(ai))) {
703 codec_dbg(codec,
704 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
705 pin_nid,
706 active_channels, ca);
707 hdmi_stop_infoframe_trans(codec, pin_nid);
708 hdmi_fill_audio_infoframe(codec, pin_nid,
709 ai.bytes, sizeof(ai));
710 hdmi_start_infoframe_trans(codec, pin_nid);
711 }
712}
713
714static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
715 struct hdmi_spec_per_pin *per_pin,
716 bool non_pcm)
717{
718 struct hdmi_spec *spec = codec->spec;
719 struct hdac_chmap *chmap = &spec->chmap;
720 hda_nid_t pin_nid = per_pin->pin_nid;
721 int dev_id = per_pin->dev_id;
722 int channels = per_pin->channels;
723 int active_channels;
724 struct hdmi_eld *eld;
725 int ca;
726
727 if (!channels)
728 return;
729
730 snd_hda_set_dev_select(codec, pin_nid, dev_id);
731
732 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
733 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
734 snd_hda_codec_write(codec, pin_nid, 0,
735 AC_VERB_SET_AMP_GAIN_MUTE,
736 AMP_OUT_UNMUTE);
737
738 eld = &per_pin->sink_eld;
739
740 ca = snd_hdac_channel_allocation(&codec->core,
741 eld->info.spk_alloc, channels,
742 per_pin->chmap_set, non_pcm, per_pin->chmap);
743
744 active_channels = snd_hdac_get_active_channels(ca);
745
746 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
747 active_channels);
748
749 /*
750 * always configure channel mapping, it may have been changed by the
751 * user in the meantime
752 */
753 snd_hdac_setup_channel_mapping(&spec->chmap,
754 pin_nid, non_pcm, ca, channels,
755 per_pin->chmap, per_pin->chmap_set);
756
757 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
758 ca, active_channels, eld->info.conn_type);
759
760 per_pin->non_pcm = non_pcm;
761}
762
763/*
764 * Unsolicited events
765 */
766
767static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
768
769static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
770 int dev_id)
771{
772 struct hdmi_spec *spec = codec->spec;
773 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
774
775 if (pin_idx < 0)
776 return;
777 mutex_lock(&spec->pcm_lock);
778 hdmi_present_sense(get_pin(spec, pin_idx), 1);
779 mutex_unlock(&spec->pcm_lock);
780}
781
782static void jack_callback(struct hda_codec *codec,
783 struct hda_jack_callback *jack)
784{
785 /* stop polling when notification is enabled */
786 if (codec_has_acomp(codec))
787 return;
788
789 check_presence_and_report(codec, jack->nid, jack->dev_id);
790}
791
792static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
793 struct hda_jack_tbl *jack)
794{
795 jack->jack_dirty = 1;
796
797 codec_dbg(codec,
798 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
799 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
800 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
801
802 check_presence_and_report(codec, jack->nid, jack->dev_id);
803}
804
805static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
806{
807 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
808 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
809 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
810 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
811
812 codec_info(codec,
813 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
814 codec->addr,
815 tag,
816 subtag,
817 cp_state,
818 cp_ready);
819
820 /* TODO */
821 if (cp_state) {
822 ;
823 }
824 if (cp_ready) {
825 ;
826 }
827}
828
829
830static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
831{
832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
834 struct hda_jack_tbl *jack;
835
836 if (codec_has_acomp(codec))
837 return;
838
839 if (codec->dp_mst) {
840 int dev_entry =
841 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
842
843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
844 } else {
845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
846 }
847
848 if (!jack) {
849 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
850 return;
851 }
852
853 if (subtag == 0)
854 hdmi_intrinsic_event(codec, res, jack);
855 else
856 hdmi_non_intrinsic_event(codec, res);
857}
858
859static void haswell_verify_D0(struct hda_codec *codec,
860 hda_nid_t cvt_nid, hda_nid_t nid)
861{
862 int pwr;
863
864 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
865 * thus pins could only choose converter 0 for use. Make sure the
866 * converters are in correct power state */
867 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
868 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
869
870 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
871 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
872 AC_PWRST_D0);
873 msleep(40);
874 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
875 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
876 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
877 }
878}
879
880/*
881 * Callbacks
882 */
883
884/* HBR should be Non-PCM, 8 channels */
885#define is_hbr_format(format) \
886 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
887
888static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
889 int dev_id, bool hbr)
890{
891 int pinctl, new_pinctl;
892
893 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
894 snd_hda_set_dev_select(codec, pin_nid, dev_id);
895 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
897
898 if (pinctl < 0)
899 return hbr ? -EINVAL : 0;
900
901 new_pinctl = pinctl & ~AC_PINCTL_EPT;
902 if (hbr)
903 new_pinctl |= AC_PINCTL_EPT_HBR;
904 else
905 new_pinctl |= AC_PINCTL_EPT_NATIVE;
906
907 codec_dbg(codec,
908 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
909 pin_nid,
910 pinctl == new_pinctl ? "" : "new-",
911 new_pinctl);
912
913 if (pinctl != new_pinctl)
914 snd_hda_codec_write(codec, pin_nid, 0,
915 AC_VERB_SET_PIN_WIDGET_CONTROL,
916 new_pinctl);
917 } else if (hbr)
918 return -EINVAL;
919
920 return 0;
921}
922
923static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
924 hda_nid_t pin_nid, int dev_id,
925 u32 stream_tag, int format)
926{
927 struct hdmi_spec *spec = codec->spec;
928 unsigned int param;
929 int err;
930
931 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
932 is_hbr_format(format));
933
934 if (err) {
935 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
936 return err;
937 }
938
939 if (spec->intel_hsw_fixup) {
940
941 /*
942 * on recent platforms IEC Coding Type is required for HBR
943 * support, read current Digital Converter settings and set
944 * ICT bitfield if needed.
945 */
946 param = snd_hda_codec_read(codec, cvt_nid, 0,
947 AC_VERB_GET_DIGI_CONVERT_1, 0);
948
949 param = (param >> 16) & ~(AC_DIG3_ICT);
950
951 /* on recent platforms ICT mode is required for HBR support */
952 if (is_hbr_format(format))
953 param |= 0x1;
954
955 snd_hda_codec_write(codec, cvt_nid, 0,
956 AC_VERB_SET_DIGI_CONVERT_3, param);
957 }
958
959 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
960 return 0;
961}
962
963/* Try to find an available converter
964 * If pin_idx is less then zero, just try to find an available converter.
965 * Otherwise, try to find an available converter and get the cvt mux index
966 * of the pin.
967 */
968static int hdmi_choose_cvt(struct hda_codec *codec,
969 int pin_idx, int *cvt_id)
970{
971 struct hdmi_spec *spec = codec->spec;
972 struct hdmi_spec_per_pin *per_pin;
973 struct hdmi_spec_per_cvt *per_cvt = NULL;
974 int cvt_idx, mux_idx = 0;
975
976 /* pin_idx < 0 means no pin will be bound to the converter */
977 if (pin_idx < 0)
978 per_pin = NULL;
979 else
980 per_pin = get_pin(spec, pin_idx);
981
982 /* Dynamically assign converter to stream */
983 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
984 per_cvt = get_cvt(spec, cvt_idx);
985
986 /* Must not already be assigned */
987 if (per_cvt->assigned)
988 continue;
989 if (per_pin == NULL)
990 break;
991 /* Must be in pin's mux's list of converters */
992 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
993 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
994 break;
995 /* Not in mux list */
996 if (mux_idx == per_pin->num_mux_nids)
997 continue;
998 break;
999 }
1000
1001 /* No free converters */
1002 if (cvt_idx == spec->num_cvts)
1003 return -EBUSY;
1004
1005 if (per_pin != NULL)
1006 per_pin->mux_idx = mux_idx;
1007
1008 if (cvt_id)
1009 *cvt_id = cvt_idx;
1010
1011 return 0;
1012}
1013
1014/* Assure the pin select the right convetor */
1015static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1016 struct hdmi_spec_per_pin *per_pin)
1017{
1018 hda_nid_t pin_nid = per_pin->pin_nid;
1019 int mux_idx, curr;
1020
1021 mux_idx = per_pin->mux_idx;
1022 curr = snd_hda_codec_read(codec, pin_nid, 0,
1023 AC_VERB_GET_CONNECT_SEL, 0);
1024 if (curr != mux_idx)
1025 snd_hda_codec_write_cache(codec, pin_nid, 0,
1026 AC_VERB_SET_CONNECT_SEL,
1027 mux_idx);
1028}
1029
1030/* get the mux index for the converter of the pins
1031 * converter's mux index is the same for all pins on Intel platform
1032 */
1033static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1034 hda_nid_t cvt_nid)
1035{
1036 int i;
1037
1038 for (i = 0; i < spec->num_cvts; i++)
1039 if (spec->cvt_nids[i] == cvt_nid)
1040 return i;
1041 return -EINVAL;
1042}
1043
1044/* Intel HDMI workaround to fix audio routing issue:
1045 * For some Intel display codecs, pins share the same connection list.
1046 * So a conveter can be selected by multiple pins and playback on any of these
1047 * pins will generate sound on the external display, because audio flows from
1048 * the same converter to the display pipeline. Also muting one pin may make
1049 * other pins have no sound output.
1050 * So this function assures that an assigned converter for a pin is not selected
1051 * by any other pins.
1052 */
1053static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1054 hda_nid_t pin_nid,
1055 int dev_id, int mux_idx)
1056{
1057 struct hdmi_spec *spec = codec->spec;
1058 hda_nid_t nid;
1059 int cvt_idx, curr;
1060 struct hdmi_spec_per_cvt *per_cvt;
1061 struct hdmi_spec_per_pin *per_pin;
1062 int pin_idx;
1063
1064 /* configure the pins connections */
1065 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1066 int dev_id_saved;
1067 int dev_num;
1068
1069 per_pin = get_pin(spec, pin_idx);
1070 /*
1071 * pin not connected to monitor
1072 * no need to operate on it
1073 */
1074 if (!per_pin->pcm)
1075 continue;
1076
1077 if ((per_pin->pin_nid == pin_nid) &&
1078 (per_pin->dev_id == dev_id))
1079 continue;
1080
1081 /*
1082 * if per_pin->dev_id >= dev_num,
1083 * snd_hda_get_dev_select() will fail,
1084 * and the following operation is unpredictable.
1085 * So skip this situation.
1086 */
1087 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1088 if (per_pin->dev_id >= dev_num)
1089 continue;
1090
1091 nid = per_pin->pin_nid;
1092
1093 /*
1094 * Calling this function should not impact
1095 * on the device entry selection
1096 * So let's save the dev id for each pin,
1097 * and restore it when return
1098 */
1099 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1100 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1101 curr = snd_hda_codec_read(codec, nid, 0,
1102 AC_VERB_GET_CONNECT_SEL, 0);
1103 if (curr != mux_idx) {
1104 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1105 continue;
1106 }
1107
1108
1109 /* choose an unassigned converter. The conveters in the
1110 * connection list are in the same order as in the codec.
1111 */
1112 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1113 per_cvt = get_cvt(spec, cvt_idx);
1114 if (!per_cvt->assigned) {
1115 codec_dbg(codec,
1116 "choose cvt %d for pin nid %d\n",
1117 cvt_idx, nid);
1118 snd_hda_codec_write_cache(codec, nid, 0,
1119 AC_VERB_SET_CONNECT_SEL,
1120 cvt_idx);
1121 break;
1122 }
1123 }
1124 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1125 }
1126}
1127
1128/* A wrapper of intel_not_share_asigned_cvt() */
1129static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1130 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1131{
1132 int mux_idx;
1133 struct hdmi_spec *spec = codec->spec;
1134
1135 /* On Intel platform, the mapping of converter nid to
1136 * mux index of the pins are always the same.
1137 * The pin nid may be 0, this means all pins will not
1138 * share the converter.
1139 */
1140 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1141 if (mux_idx >= 0)
1142 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1143}
1144
1145/* skeleton caller of pin_cvt_fixup ops */
1146static void pin_cvt_fixup(struct hda_codec *codec,
1147 struct hdmi_spec_per_pin *per_pin,
1148 hda_nid_t cvt_nid)
1149{
1150 struct hdmi_spec *spec = codec->spec;
1151
1152 if (spec->ops.pin_cvt_fixup)
1153 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1154}
1155
1156/* called in hdmi_pcm_open when no pin is assigned to the PCM
1157 * in dyn_pcm_assign mode.
1158 */
1159static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1160 struct hda_codec *codec,
1161 struct snd_pcm_substream *substream)
1162{
1163 struct hdmi_spec *spec = codec->spec;
1164 struct snd_pcm_runtime *runtime = substream->runtime;
1165 int cvt_idx, pcm_idx;
1166 struct hdmi_spec_per_cvt *per_cvt = NULL;
1167 int err;
1168
1169 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1170 if (pcm_idx < 0)
1171 return -EINVAL;
1172
1173 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1174 if (err)
1175 return err;
1176
1177 per_cvt = get_cvt(spec, cvt_idx);
1178 per_cvt->assigned = 1;
1179 hinfo->nid = per_cvt->cvt_nid;
1180
1181 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1182
1183 set_bit(pcm_idx, &spec->pcm_in_use);
1184 /* todo: setup spdif ctls assign */
1185
1186 /* Initially set the converter's capabilities */
1187 hinfo->channels_min = per_cvt->channels_min;
1188 hinfo->channels_max = per_cvt->channels_max;
1189 hinfo->rates = per_cvt->rates;
1190 hinfo->formats = per_cvt->formats;
1191 hinfo->maxbps = per_cvt->maxbps;
1192
1193 /* Store the updated parameters */
1194 runtime->hw.channels_min = hinfo->channels_min;
1195 runtime->hw.channels_max = hinfo->channels_max;
1196 runtime->hw.formats = hinfo->formats;
1197 runtime->hw.rates = hinfo->rates;
1198
1199 snd_pcm_hw_constraint_step(substream->runtime, 0,
1200 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1201 return 0;
1202}
1203
1204/*
1205 * HDA PCM callbacks
1206 */
1207static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1208 struct hda_codec *codec,
1209 struct snd_pcm_substream *substream)
1210{
1211 struct hdmi_spec *spec = codec->spec;
1212 struct snd_pcm_runtime *runtime = substream->runtime;
1213 int pin_idx, cvt_idx, pcm_idx;
1214 struct hdmi_spec_per_pin *per_pin;
1215 struct hdmi_eld *eld;
1216 struct hdmi_spec_per_cvt *per_cvt = NULL;
1217 int err;
1218
1219 /* Validate hinfo */
1220 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1221 if (pcm_idx < 0)
1222 return -EINVAL;
1223
1224 mutex_lock(&spec->pcm_lock);
1225 pin_idx = hinfo_to_pin_index(codec, hinfo);
1226 if (!spec->dyn_pcm_assign) {
1227 if (snd_BUG_ON(pin_idx < 0)) {
1228 err = -EINVAL;
1229 goto unlock;
1230 }
1231 } else {
1232 /* no pin is assigned to the PCM
1233 * PA need pcm open successfully when probe
1234 */
1235 if (pin_idx < 0) {
1236 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1237 goto unlock;
1238 }
1239 }
1240
1241 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1242 if (err < 0)
1243 goto unlock;
1244
1245 per_cvt = get_cvt(spec, cvt_idx);
1246 /* Claim converter */
1247 per_cvt->assigned = 1;
1248
1249 set_bit(pcm_idx, &spec->pcm_in_use);
1250 per_pin = get_pin(spec, pin_idx);
1251 per_pin->cvt_nid = per_cvt->cvt_nid;
1252 hinfo->nid = per_cvt->cvt_nid;
1253
1254 /* flip stripe flag for the assigned stream if supported */
1255 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1256 azx_stream(get_azx_dev(substream))->stripe = 1;
1257
1258 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1259 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1260 AC_VERB_SET_CONNECT_SEL,
1261 per_pin->mux_idx);
1262
1263 /* configure unused pins to choose other converters */
1264 pin_cvt_fixup(codec, per_pin, 0);
1265
1266 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1267
1268 /* Initially set the converter's capabilities */
1269 hinfo->channels_min = per_cvt->channels_min;
1270 hinfo->channels_max = per_cvt->channels_max;
1271 hinfo->rates = per_cvt->rates;
1272 hinfo->formats = per_cvt->formats;
1273 hinfo->maxbps = per_cvt->maxbps;
1274
1275 eld = &per_pin->sink_eld;
1276 /* Restrict capabilities by ELD if this isn't disabled */
1277 if (!static_hdmi_pcm && eld->eld_valid) {
1278 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1279 if (hinfo->channels_min > hinfo->channels_max ||
1280 !hinfo->rates || !hinfo->formats) {
1281 per_cvt->assigned = 0;
1282 hinfo->nid = 0;
1283 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1284 err = -ENODEV;
1285 goto unlock;
1286 }
1287 }
1288
1289 /* Store the updated parameters */
1290 runtime->hw.channels_min = hinfo->channels_min;
1291 runtime->hw.channels_max = hinfo->channels_max;
1292 runtime->hw.formats = hinfo->formats;
1293 runtime->hw.rates = hinfo->rates;
1294
1295 snd_pcm_hw_constraint_step(substream->runtime, 0,
1296 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1297 unlock:
1298 mutex_unlock(&spec->pcm_lock);
1299 return err;
1300}
1301
1302/*
1303 * HDA/HDMI auto parsing
1304 */
1305static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1306{
1307 struct hdmi_spec *spec = codec->spec;
1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1309 hda_nid_t pin_nid = per_pin->pin_nid;
1310 int dev_id = per_pin->dev_id;
1311 int conns;
1312
1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1314 codec_warn(codec,
1315 "HDMI: pin %d wcaps %#x does not support connection list\n",
1316 pin_nid, get_wcaps(codec, pin_nid));
1317 return -EINVAL;
1318 }
1319
1320 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1321
1322 if (spec->intel_hsw_fixup) {
1323 conns = spec->num_cvts;
1324 memcpy(per_pin->mux_nids, spec->cvt_nids,
1325 sizeof(hda_nid_t) * conns);
1326 } else {
1327 conns = snd_hda_get_raw_connections(codec, pin_nid,
1328 per_pin->mux_nids,
1329 HDA_MAX_CONNECTIONS);
1330 }
1331
1332 /* all the device entries on the same pin have the same conn list */
1333 per_pin->num_mux_nids = conns;
1334
1335 return 0;
1336}
1337
1338static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1339 struct hdmi_spec_per_pin *per_pin)
1340{
1341 int i;
1342
1343 /*
1344 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1345 * platforms (with maximum of 'num_nids + dev_num - 1')
1346 *
1347 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1348 * if m==0. This guarantees that dynamic pcm assignments are compatible
1349 * with the legacy static per_pin-pcm assignment that existed in the
1350 * days before DP-MST.
1351 *
1352 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1353 *
1354 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1355 */
1356
1357 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1358 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1359 return per_pin->pin_nid_idx;
1360 } else {
1361 i = spec->num_nids + (per_pin->dev_id - 1);
1362 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1363 return i;
1364 }
1365
1366 /* have a second try; check the area over num_nids */
1367 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1368 if (!test_bit(i, &spec->pcm_bitmap))
1369 return i;
1370 }
1371
1372 /* the last try; check the empty slots in pins */
1373 for (i = 0; i < spec->num_nids; i++) {
1374 if (!test_bit(i, &spec->pcm_bitmap))
1375 return i;
1376 }
1377 return -EBUSY;
1378}
1379
1380static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1381 struct hdmi_spec_per_pin *per_pin)
1382{
1383 int idx;
1384
1385 /* pcm already be attached to the pin */
1386 if (per_pin->pcm)
1387 return;
1388 idx = hdmi_find_pcm_slot(spec, per_pin);
1389 if (idx == -EBUSY)
1390 return;
1391 per_pin->pcm_idx = idx;
1392 per_pin->pcm = get_hdmi_pcm(spec, idx);
1393 set_bit(idx, &spec->pcm_bitmap);
1394}
1395
1396static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1397 struct hdmi_spec_per_pin *per_pin)
1398{
1399 int idx;
1400
1401 /* pcm already be detached from the pin */
1402 if (!per_pin->pcm)
1403 return;
1404 idx = per_pin->pcm_idx;
1405 per_pin->pcm_idx = -1;
1406 per_pin->pcm = NULL;
1407 if (idx >= 0 && idx < spec->pcm_used)
1408 clear_bit(idx, &spec->pcm_bitmap);
1409}
1410
1411static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1412 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1413{
1414 int mux_idx;
1415
1416 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1417 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1418 break;
1419 return mux_idx;
1420}
1421
1422static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1423
1424static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1425 struct hdmi_spec_per_pin *per_pin)
1426{
1427 struct hda_codec *codec = per_pin->codec;
1428 struct hda_pcm *pcm;
1429 struct hda_pcm_stream *hinfo;
1430 struct snd_pcm_substream *substream;
1431 int mux_idx;
1432 bool non_pcm;
1433
1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1435 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1436 else
1437 return;
1438 if (!pcm->pcm)
1439 return;
1440 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1441 return;
1442
1443 /* hdmi audio only uses playback and one substream */
1444 hinfo = pcm->stream;
1445 substream = pcm->pcm->streams[0].substream;
1446
1447 per_pin->cvt_nid = hinfo->nid;
1448
1449 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1450 if (mux_idx < per_pin->num_mux_nids) {
1451 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1452 per_pin->dev_id);
1453 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1454 AC_VERB_SET_CONNECT_SEL,
1455 mux_idx);
1456 }
1457 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1458
1459 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1460 if (substream->runtime)
1461 per_pin->channels = substream->runtime->channels;
1462 per_pin->setup = true;
1463 per_pin->mux_idx = mux_idx;
1464
1465 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1466}
1467
1468static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1469 struct hdmi_spec_per_pin *per_pin)
1470{
1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1472 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1473
1474 per_pin->chmap_set = false;
1475 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1476
1477 per_pin->setup = false;
1478 per_pin->channels = 0;
1479}
1480
1481static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1482 struct hdmi_spec_per_pin *per_pin)
1483{
1484 struct hdmi_spec *spec = codec->spec;
1485
1486 if (per_pin->pcm_idx >= 0)
1487 return spec->pcm_rec[per_pin->pcm_idx].jack;
1488 else
1489 return NULL;
1490}
1491
1492/* update per_pin ELD from the given new ELD;
1493 * setup info frame and notification accordingly
1494 * also notify ELD kctl and report jack status changes
1495 */
1496static void update_eld(struct hda_codec *codec,
1497 struct hdmi_spec_per_pin *per_pin,
1498 struct hdmi_eld *eld,
1499 int repoll)
1500{
1501 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1502 struct hdmi_spec *spec = codec->spec;
1503 struct snd_jack *pcm_jack;
1504 bool old_eld_valid = pin_eld->eld_valid;
1505 bool eld_changed;
1506 int pcm_idx;
1507
1508 if (eld->eld_valid) {
1509 if (eld->eld_size <= 0 ||
1510 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1511 eld->eld_size) < 0) {
1512 eld->eld_valid = false;
1513 if (repoll) {
1514 schedule_delayed_work(&per_pin->work,
1515 msecs_to_jiffies(300));
1516 return;
1517 }
1518 }
1519 }
1520
1521 if (!eld->eld_valid || eld->eld_size <= 0) {
1522 eld->eld_valid = false;
1523 eld->eld_size = 0;
1524 }
1525
1526 /* for monitor disconnection, save pcm_idx firstly */
1527 pcm_idx = per_pin->pcm_idx;
1528
1529 /*
1530 * pcm_idx >=0 before update_eld() means it is in monitor
1531 * disconnected event. Jack must be fetched before update_eld().
1532 */
1533 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1534
1535 if (spec->dyn_pcm_assign) {
1536 if (eld->eld_valid) {
1537 hdmi_attach_hda_pcm(spec, per_pin);
1538 hdmi_pcm_setup_pin(spec, per_pin);
1539 } else {
1540 hdmi_pcm_reset_pin(spec, per_pin);
1541 hdmi_detach_hda_pcm(spec, per_pin);
1542 }
1543 }
1544 /* if pcm_idx == -1, it means this is in monitor connection event
1545 * we can get the correct pcm_idx now.
1546 */
1547 if (pcm_idx == -1)
1548 pcm_idx = per_pin->pcm_idx;
1549 if (!pcm_jack)
1550 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1551
1552 if (eld->eld_valid)
1553 snd_hdmi_show_eld(codec, &eld->info);
1554
1555 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1556 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1557 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1558 if (pin_eld->eld_size != eld->eld_size ||
1559 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1560 eld->eld_size) != 0)
1561 eld_changed = true;
1562
1563 if (eld_changed) {
1564 pin_eld->monitor_present = eld->monitor_present;
1565 pin_eld->eld_valid = eld->eld_valid;
1566 pin_eld->eld_size = eld->eld_size;
1567 if (eld->eld_valid)
1568 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1569 eld->eld_size);
1570 pin_eld->info = eld->info;
1571 }
1572
1573 /*
1574 * Re-setup pin and infoframe. This is needed e.g. when
1575 * - sink is first plugged-in
1576 * - transcoder can change during stream playback on Haswell
1577 * and this can make HW reset converter selection on a pin.
1578 */
1579 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1580 pin_cvt_fixup(codec, per_pin, 0);
1581 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1582 }
1583
1584 if (eld_changed && pcm_idx >= 0)
1585 snd_ctl_notify(codec->card,
1586 SNDRV_CTL_EVENT_MASK_VALUE |
1587 SNDRV_CTL_EVENT_MASK_INFO,
1588 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1589
1590 if (eld_changed && pcm_jack)
1591 snd_jack_report(pcm_jack,
1592 (eld->monitor_present && eld->eld_valid) ?
1593 SND_JACK_AVOUT : 0);
1594}
1595
1596/* update ELD and jack state via HD-audio verbs */
1597static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1598 int repoll)
1599{
1600 struct hda_codec *codec = per_pin->codec;
1601 struct hdmi_spec *spec = codec->spec;
1602 struct hdmi_eld *eld = &spec->temp_eld;
1603 hda_nid_t pin_nid = per_pin->pin_nid;
1604 int dev_id = per_pin->dev_id;
1605 /*
1606 * Always execute a GetPinSense verb here, even when called from
1607 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1608 * response's PD bit is not the real PD value, but indicates that
1609 * the real PD value changed. An older version of the HD-audio
1610 * specification worked this way. Hence, we just ignore the data in
1611 * the unsolicited response to avoid custom WARs.
1612 */
1613 int present;
1614 int ret;
1615
1616 ret = snd_hda_power_up_pm(codec);
1617 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec)))
1618 goto out;
1619
1620 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1621
1622 mutex_lock(&per_pin->lock);
1623 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1624 if (eld->monitor_present)
1625 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1626 else
1627 eld->eld_valid = false;
1628
1629 codec_dbg(codec,
1630 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1631 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1632
1633 if (eld->eld_valid) {
1634 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1635 eld->eld_buffer, &eld->eld_size) < 0)
1636 eld->eld_valid = false;
1637 }
1638
1639 update_eld(codec, per_pin, eld, repoll);
1640 mutex_unlock(&per_pin->lock);
1641 out:
1642 snd_hda_power_down_pm(codec);
1643}
1644
1645static void silent_stream_enable(struct hda_codec *codec,
1646 struct hdmi_spec_per_pin *per_pin)
1647{
1648 unsigned int newval, oldval;
1649
1650 codec_dbg(codec, "hdmi: enabling silent stream for NID %d\n",
1651 per_pin->pin_nid);
1652
1653 mutex_lock(&per_pin->lock);
1654
1655 if (!per_pin->channels)
1656 per_pin->channels = 2;
1657
1658 oldval = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1659 AC_VERB_GET_CONV, 0);
1660 newval = (oldval & 0xF0) | 0xF;
1661 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1662 AC_VERB_SET_CHANNEL_STREAMID, newval);
1663
1664 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1665
1666 mutex_unlock(&per_pin->lock);
1667}
1668
1669/* update ELD and jack state via audio component */
1670static void sync_eld_via_acomp(struct hda_codec *codec,
1671 struct hdmi_spec_per_pin *per_pin)
1672{
1673 struct hdmi_spec *spec = codec->spec;
1674 struct hdmi_eld *eld = &spec->temp_eld;
1675 bool monitor_prev, monitor_next;
1676
1677 mutex_lock(&per_pin->lock);
1678 eld->monitor_present = false;
1679 monitor_prev = per_pin->sink_eld.monitor_present;
1680 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1681 per_pin->dev_id, &eld->monitor_present,
1682 eld->eld_buffer, ELD_MAX_SIZE);
1683 eld->eld_valid = (eld->eld_size > 0);
1684 update_eld(codec, per_pin, eld, 0);
1685 monitor_next = per_pin->sink_eld.monitor_present;
1686 mutex_unlock(&per_pin->lock);
1687
1688 /*
1689 * Power-up will call hdmi_present_sense, so the PM calls
1690 * have to be done without mutex held.
1691 */
1692
1693 if (spec->send_silent_stream) {
1694 int pm_ret;
1695
1696 if (!monitor_prev && monitor_next) {
1697 pm_ret = snd_hda_power_up_pm(codec);
1698 if (pm_ret < 0)
1699 codec_err(codec,
1700 "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
1701 pm_ret);
1702 silent_stream_enable(codec, per_pin);
1703 } else if (monitor_prev && !monitor_next) {
1704 pm_ret = snd_hda_power_down_pm(codec);
1705 if (pm_ret < 0)
1706 codec_err(codec,
1707 "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
1708 pm_ret);
1709 }
1710 }
1711}
1712
1713static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1714{
1715 struct hda_codec *codec = per_pin->codec;
1716
1717 if (!codec_has_acomp(codec))
1718 hdmi_present_sense_via_verbs(per_pin, repoll);
1719 else
1720 sync_eld_via_acomp(codec, per_pin);
1721}
1722
1723static void hdmi_repoll_eld(struct work_struct *work)
1724{
1725 struct hdmi_spec_per_pin *per_pin =
1726 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1727 struct hda_codec *codec = per_pin->codec;
1728 struct hdmi_spec *spec = codec->spec;
1729 struct hda_jack_tbl *jack;
1730
1731 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1732 per_pin->dev_id);
1733 if (jack)
1734 jack->jack_dirty = 1;
1735
1736 if (per_pin->repoll_count++ > 6)
1737 per_pin->repoll_count = 0;
1738
1739 mutex_lock(&spec->pcm_lock);
1740 hdmi_present_sense(per_pin, per_pin->repoll_count);
1741 mutex_unlock(&spec->pcm_lock);
1742}
1743
1744static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1745{
1746 struct hdmi_spec *spec = codec->spec;
1747 unsigned int caps, config;
1748 int pin_idx;
1749 struct hdmi_spec_per_pin *per_pin;
1750 int err;
1751 int dev_num, i;
1752
1753 caps = snd_hda_query_pin_caps(codec, pin_nid);
1754 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1755 return 0;
1756
1757 /*
1758 * For DP MST audio, Configuration Default is the same for
1759 * all device entries on the same pin
1760 */
1761 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1762 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1763 !spec->force_connect)
1764 return 0;
1765
1766 /*
1767 * To simplify the implementation, malloc all
1768 * the virtual pins in the initialization statically
1769 */
1770 if (spec->intel_hsw_fixup) {
1771 /*
1772 * On Intel platforms, device entries number is
1773 * changed dynamically. If there is a DP MST
1774 * hub connected, the device entries number is 3.
1775 * Otherwise, it is 1.
1776 * Here we manually set dev_num to 3, so that
1777 * we can initialize all the device entries when
1778 * bootup statically.
1779 */
1780 dev_num = 3;
1781 spec->dev_num = 3;
1782 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1783 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1784 /*
1785 * spec->dev_num is the maxinum number of device entries
1786 * among all the pins
1787 */
1788 spec->dev_num = (spec->dev_num > dev_num) ?
1789 spec->dev_num : dev_num;
1790 } else {
1791 /*
1792 * If the platform doesn't support DP MST,
1793 * manually set dev_num to 1. This means
1794 * the pin has only one device entry.
1795 */
1796 dev_num = 1;
1797 spec->dev_num = 1;
1798 }
1799
1800 for (i = 0; i < dev_num; i++) {
1801 pin_idx = spec->num_pins;
1802 per_pin = snd_array_new(&spec->pins);
1803
1804 if (!per_pin)
1805 return -ENOMEM;
1806
1807 if (spec->dyn_pcm_assign) {
1808 per_pin->pcm = NULL;
1809 per_pin->pcm_idx = -1;
1810 } else {
1811 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1812 per_pin->pcm_idx = pin_idx;
1813 }
1814 per_pin->pin_nid = pin_nid;
1815 per_pin->pin_nid_idx = spec->num_nids;
1816 per_pin->dev_id = i;
1817 per_pin->non_pcm = false;
1818 snd_hda_set_dev_select(codec, pin_nid, i);
1819 err = hdmi_read_pin_conn(codec, pin_idx);
1820 if (err < 0)
1821 return err;
1822 spec->num_pins++;
1823 }
1824 spec->num_nids++;
1825
1826 return 0;
1827}
1828
1829static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1830{
1831 struct hdmi_spec *spec = codec->spec;
1832 struct hdmi_spec_per_cvt *per_cvt;
1833 unsigned int chans;
1834 int err;
1835
1836 chans = get_wcaps(codec, cvt_nid);
1837 chans = get_wcaps_channels(chans);
1838
1839 per_cvt = snd_array_new(&spec->cvts);
1840 if (!per_cvt)
1841 return -ENOMEM;
1842
1843 per_cvt->cvt_nid = cvt_nid;
1844 per_cvt->channels_min = 2;
1845 if (chans <= 16) {
1846 per_cvt->channels_max = chans;
1847 if (chans > spec->chmap.channels_max)
1848 spec->chmap.channels_max = chans;
1849 }
1850
1851 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1852 &per_cvt->rates,
1853 &per_cvt->formats,
1854 &per_cvt->maxbps);
1855 if (err < 0)
1856 return err;
1857
1858 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1859 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1860 spec->num_cvts++;
1861
1862 return 0;
1863}
1864
1865static const struct snd_pci_quirk force_connect_list[] = {
1866 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1867 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1868 {}
1869};
1870
1871static int hdmi_parse_codec(struct hda_codec *codec)
1872{
1873 struct hdmi_spec *spec = codec->spec;
1874 hda_nid_t start_nid;
1875 unsigned int caps;
1876 int i, nodes;
1877 const struct snd_pci_quirk *q;
1878
1879 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1880 if (!start_nid || nodes < 0) {
1881 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1882 return -EINVAL;
1883 }
1884
1885 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
1886
1887 if (q && q->value)
1888 spec->force_connect = true;
1889
1890 /*
1891 * hdmi_add_pin() assumes total amount of converters to
1892 * be known, so first discover all converters
1893 */
1894 for (i = 0; i < nodes; i++) {
1895 hda_nid_t nid = start_nid + i;
1896
1897 caps = get_wcaps(codec, nid);
1898
1899 if (!(caps & AC_WCAP_DIGITAL))
1900 continue;
1901
1902 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
1903 hdmi_add_cvt(codec, nid);
1904 }
1905
1906 /* discover audio pins */
1907 for (i = 0; i < nodes; i++) {
1908 hda_nid_t nid = start_nid + i;
1909
1910 caps = get_wcaps(codec, nid);
1911
1912 if (!(caps & AC_WCAP_DIGITAL))
1913 continue;
1914
1915 if (get_wcaps_type(caps) == AC_WID_PIN)
1916 hdmi_add_pin(codec, nid);
1917 }
1918
1919 return 0;
1920}
1921
1922/*
1923 */
1924static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1925{
1926 struct hda_spdif_out *spdif;
1927 bool non_pcm;
1928
1929 mutex_lock(&codec->spdif_mutex);
1930 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1931 /* Add sanity check to pass klockwork check.
1932 * This should never happen.
1933 */
1934 if (WARN_ON(spdif == NULL)) {
1935 mutex_unlock(&codec->spdif_mutex);
1936 return true;
1937 }
1938 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1939 mutex_unlock(&codec->spdif_mutex);
1940 return non_pcm;
1941}
1942
1943/*
1944 * HDMI callbacks
1945 */
1946
1947static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1948 struct hda_codec *codec,
1949 unsigned int stream_tag,
1950 unsigned int format,
1951 struct snd_pcm_substream *substream)
1952{
1953 hda_nid_t cvt_nid = hinfo->nid;
1954 struct hdmi_spec *spec = codec->spec;
1955 int pin_idx;
1956 struct hdmi_spec_per_pin *per_pin;
1957 struct snd_pcm_runtime *runtime = substream->runtime;
1958 bool non_pcm;
1959 int pinctl, stripe;
1960 int err = 0;
1961
1962 mutex_lock(&spec->pcm_lock);
1963 pin_idx = hinfo_to_pin_index(codec, hinfo);
1964 if (spec->dyn_pcm_assign && pin_idx < 0) {
1965 /* when dyn_pcm_assign and pcm is not bound to a pin
1966 * skip pin setup and return 0 to make audio playback
1967 * be ongoing
1968 */
1969 pin_cvt_fixup(codec, NULL, cvt_nid);
1970 snd_hda_codec_setup_stream(codec, cvt_nid,
1971 stream_tag, 0, format);
1972 goto unlock;
1973 }
1974
1975 if (snd_BUG_ON(pin_idx < 0)) {
1976 err = -EINVAL;
1977 goto unlock;
1978 }
1979 per_pin = get_pin(spec, pin_idx);
1980
1981 /* Verify pin:cvt selections to avoid silent audio after S3.
1982 * After S3, the audio driver restores pin:cvt selections
1983 * but this can happen before gfx is ready and such selection
1984 * is overlooked by HW. Thus multiple pins can share a same
1985 * default convertor and mute control will affect each other,
1986 * which can cause a resumed audio playback become silent
1987 * after S3.
1988 */
1989 pin_cvt_fixup(codec, per_pin, 0);
1990
1991 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1992 /* Todo: add DP1.2 MST audio support later */
1993 if (codec_has_acomp(codec))
1994 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1995 per_pin->dev_id, runtime->rate);
1996
1997 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1998 mutex_lock(&per_pin->lock);
1999 per_pin->channels = substream->runtime->channels;
2000 per_pin->setup = true;
2001
2002 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2003 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2004 substream);
2005 snd_hda_codec_write(codec, cvt_nid, 0,
2006 AC_VERB_SET_STRIPE_CONTROL,
2007 stripe);
2008 }
2009
2010 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2011 mutex_unlock(&per_pin->lock);
2012 if (spec->dyn_pin_out) {
2013 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2014 per_pin->dev_id);
2015 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2016 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2017 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2018 AC_VERB_SET_PIN_WIDGET_CONTROL,
2019 pinctl | PIN_OUT);
2020 }
2021
2022 /* snd_hda_set_dev_select() has been called before */
2023 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2024 per_pin->dev_id, stream_tag, format);
2025 unlock:
2026 mutex_unlock(&spec->pcm_lock);
2027 return err;
2028}
2029
2030static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2031 struct hda_codec *codec,
2032 struct snd_pcm_substream *substream)
2033{
2034 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2035 return 0;
2036}
2037
2038static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2039 struct hda_codec *codec,
2040 struct snd_pcm_substream *substream)
2041{
2042 struct hdmi_spec *spec = codec->spec;
2043 int cvt_idx, pin_idx, pcm_idx;
2044 struct hdmi_spec_per_cvt *per_cvt;
2045 struct hdmi_spec_per_pin *per_pin;
2046 int pinctl;
2047 int err = 0;
2048
2049 if (hinfo->nid) {
2050 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2051 if (snd_BUG_ON(pcm_idx < 0))
2052 return -EINVAL;
2053 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2054 if (snd_BUG_ON(cvt_idx < 0))
2055 return -EINVAL;
2056 per_cvt = get_cvt(spec, cvt_idx);
2057
2058 snd_BUG_ON(!per_cvt->assigned);
2059 per_cvt->assigned = 0;
2060 hinfo->nid = 0;
2061
2062 azx_stream(get_azx_dev(substream))->stripe = 0;
2063
2064 mutex_lock(&spec->pcm_lock);
2065 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2066 clear_bit(pcm_idx, &spec->pcm_in_use);
2067 pin_idx = hinfo_to_pin_index(codec, hinfo);
2068 if (spec->dyn_pcm_assign && pin_idx < 0)
2069 goto unlock;
2070
2071 if (snd_BUG_ON(pin_idx < 0)) {
2072 err = -EINVAL;
2073 goto unlock;
2074 }
2075 per_pin = get_pin(spec, pin_idx);
2076
2077 if (spec->dyn_pin_out) {
2078 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2079 per_pin->dev_id);
2080 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2081 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2082 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2083 AC_VERB_SET_PIN_WIDGET_CONTROL,
2084 pinctl & ~PIN_OUT);
2085 }
2086
2087 mutex_lock(&per_pin->lock);
2088 per_pin->chmap_set = false;
2089 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2090
2091 per_pin->setup = false;
2092 per_pin->channels = 0;
2093 mutex_unlock(&per_pin->lock);
2094 unlock:
2095 mutex_unlock(&spec->pcm_lock);
2096 }
2097
2098 return err;
2099}
2100
2101static const struct hda_pcm_ops generic_ops = {
2102 .open = hdmi_pcm_open,
2103 .close = hdmi_pcm_close,
2104 .prepare = generic_hdmi_playback_pcm_prepare,
2105 .cleanup = generic_hdmi_playback_pcm_cleanup,
2106};
2107
2108static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2109{
2110 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2111 struct hdmi_spec *spec = codec->spec;
2112 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2113
2114 if (!per_pin)
2115 return 0;
2116
2117 return per_pin->sink_eld.info.spk_alloc;
2118}
2119
2120static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2121 unsigned char *chmap)
2122{
2123 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2124 struct hdmi_spec *spec = codec->spec;
2125 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2126
2127 /* chmap is already set to 0 in caller */
2128 if (!per_pin)
2129 return;
2130
2131 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2132}
2133
2134static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2135 unsigned char *chmap, int prepared)
2136{
2137 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2138 struct hdmi_spec *spec = codec->spec;
2139 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2140
2141 if (!per_pin)
2142 return;
2143 mutex_lock(&per_pin->lock);
2144 per_pin->chmap_set = true;
2145 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2146 if (prepared)
2147 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2148 mutex_unlock(&per_pin->lock);
2149}
2150
2151static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2152{
2153 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2154 struct hdmi_spec *spec = codec->spec;
2155 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2156
2157 return per_pin ? true:false;
2158}
2159
2160static int generic_hdmi_build_pcms(struct hda_codec *codec)
2161{
2162 struct hdmi_spec *spec = codec->spec;
2163 int idx, pcm_num;
2164
2165 /*
2166 * for non-mst mode, pcm number is the same as before
2167 * for DP MST mode without extra PCM, pcm number is same
2168 * for DP MST mode with extra PCMs, pcm number is
2169 * (nid number + dev_num - 1)
2170 * dev_num is the device entry number in a pin
2171 */
2172
2173 if (codec->mst_no_extra_pcms)
2174 pcm_num = spec->num_nids;
2175 else
2176 pcm_num = spec->num_nids + spec->dev_num - 1;
2177
2178 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2179
2180 for (idx = 0; idx < pcm_num; idx++) {
2181 struct hda_pcm *info;
2182 struct hda_pcm_stream *pstr;
2183
2184 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2185 if (!info)
2186 return -ENOMEM;
2187
2188 spec->pcm_rec[idx].pcm = info;
2189 spec->pcm_used++;
2190 info->pcm_type = HDA_PCM_TYPE_HDMI;
2191 info->own_chmap = true;
2192
2193 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2194 pstr->substreams = 1;
2195 pstr->ops = generic_ops;
2196 /* pcm number is less than 16 */
2197 if (spec->pcm_used >= 16)
2198 break;
2199 /* other pstr fields are set in open */
2200 }
2201
2202 return 0;
2203}
2204
2205static void free_hdmi_jack_priv(struct snd_jack *jack)
2206{
2207 struct hdmi_pcm *pcm = jack->private_data;
2208
2209 pcm->jack = NULL;
2210}
2211
2212static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2213{
2214 char hdmi_str[32] = "HDMI/DP";
2215 struct hdmi_spec *spec = codec->spec;
2216 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2217 struct snd_jack *jack;
2218 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2219 int err;
2220
2221 if (pcmdev > 0)
2222 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2223 if (!spec->dyn_pcm_assign &&
2224 !is_jack_detectable(codec, per_pin->pin_nid))
2225 strncat(hdmi_str, " Phantom",
2226 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2227
2228 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2229 true, false);
2230 if (err < 0)
2231 return err;
2232
2233 spec->pcm_rec[pcm_idx].jack = jack;
2234 jack->private_data = &spec->pcm_rec[pcm_idx];
2235 jack->private_free = free_hdmi_jack_priv;
2236 return 0;
2237}
2238
2239static int generic_hdmi_build_controls(struct hda_codec *codec)
2240{
2241 struct hdmi_spec *spec = codec->spec;
2242 int dev, err;
2243 int pin_idx, pcm_idx;
2244
2245 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2246 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2247 /* no PCM: mark this for skipping permanently */
2248 set_bit(pcm_idx, &spec->pcm_bitmap);
2249 continue;
2250 }
2251
2252 err = generic_hdmi_build_jack(codec, pcm_idx);
2253 if (err < 0)
2254 return err;
2255
2256 /* create the spdif for each pcm
2257 * pin will be bound when monitor is connected
2258 */
2259 if (spec->dyn_pcm_assign)
2260 err = snd_hda_create_dig_out_ctls(codec,
2261 0, spec->cvt_nids[0],
2262 HDA_PCM_TYPE_HDMI);
2263 else {
2264 struct hdmi_spec_per_pin *per_pin =
2265 get_pin(spec, pcm_idx);
2266 err = snd_hda_create_dig_out_ctls(codec,
2267 per_pin->pin_nid,
2268 per_pin->mux_nids[0],
2269 HDA_PCM_TYPE_HDMI);
2270 }
2271 if (err < 0)
2272 return err;
2273 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2274
2275 dev = get_pcm_rec(spec, pcm_idx)->device;
2276 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2277 /* add control for ELD Bytes */
2278 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2279 if (err < 0)
2280 return err;
2281 }
2282 }
2283
2284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2285 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2286 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2287
2288 pin_eld->eld_valid = false;
2289 hdmi_present_sense(per_pin, 0);
2290 }
2291
2292 /* add channel maps */
2293 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2294 struct hda_pcm *pcm;
2295
2296 pcm = get_pcm_rec(spec, pcm_idx);
2297 if (!pcm || !pcm->pcm)
2298 break;
2299 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2300 if (err < 0)
2301 return err;
2302 }
2303
2304 return 0;
2305}
2306
2307static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec = codec->spec;
2310 int pin_idx;
2311
2312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2313 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2314
2315 per_pin->codec = codec;
2316 mutex_init(&per_pin->lock);
2317 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2318 eld_proc_new(per_pin, pin_idx);
2319 }
2320 return 0;
2321}
2322
2323static int generic_hdmi_init(struct hda_codec *codec)
2324{
2325 struct hdmi_spec *spec = codec->spec;
2326 int pin_idx;
2327
2328 mutex_lock(&spec->bind_lock);
2329 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2330 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2331 hda_nid_t pin_nid = per_pin->pin_nid;
2332 int dev_id = per_pin->dev_id;
2333
2334 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2335 hdmi_init_pin(codec, pin_nid);
2336 if (codec_has_acomp(codec))
2337 continue;
2338 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2339 jack_callback);
2340 }
2341 mutex_unlock(&spec->bind_lock);
2342 return 0;
2343}
2344
2345static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2346{
2347 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2348 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2349}
2350
2351static void hdmi_array_free(struct hdmi_spec *spec)
2352{
2353 snd_array_free(&spec->pins);
2354 snd_array_free(&spec->cvts);
2355}
2356
2357static void generic_spec_free(struct hda_codec *codec)
2358{
2359 struct hdmi_spec *spec = codec->spec;
2360
2361 if (spec) {
2362 hdmi_array_free(spec);
2363 kfree(spec);
2364 codec->spec = NULL;
2365 }
2366 codec->dp_mst = false;
2367}
2368
2369static void generic_hdmi_free(struct hda_codec *codec)
2370{
2371 struct hdmi_spec *spec = codec->spec;
2372 int pin_idx, pcm_idx;
2373
2374 if (spec->acomp_registered) {
2375 snd_hdac_acomp_exit(&codec->bus->core);
2376 } else if (codec_has_acomp(codec)) {
2377 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2378 }
2379 codec->relaxed_resume = 0;
2380
2381 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2382 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2383 cancel_delayed_work_sync(&per_pin->work);
2384 eld_proc_free(per_pin);
2385 }
2386
2387 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2388 if (spec->pcm_rec[pcm_idx].jack == NULL)
2389 continue;
2390 if (spec->dyn_pcm_assign)
2391 snd_device_free(codec->card,
2392 spec->pcm_rec[pcm_idx].jack);
2393 else
2394 spec->pcm_rec[pcm_idx].jack = NULL;
2395 }
2396
2397 generic_spec_free(codec);
2398}
2399
2400#ifdef CONFIG_PM
2401static int generic_hdmi_resume(struct hda_codec *codec)
2402{
2403 struct hdmi_spec *spec = codec->spec;
2404 int pin_idx;
2405
2406 codec->patch_ops.init(codec);
2407 snd_hda_regmap_sync(codec);
2408
2409 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2410 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2411 hdmi_present_sense(per_pin, 1);
2412 }
2413 return 0;
2414}
2415#endif
2416
2417static const struct hda_codec_ops generic_hdmi_patch_ops = {
2418 .init = generic_hdmi_init,
2419 .free = generic_hdmi_free,
2420 .build_pcms = generic_hdmi_build_pcms,
2421 .build_controls = generic_hdmi_build_controls,
2422 .unsol_event = hdmi_unsol_event,
2423#ifdef CONFIG_PM
2424 .resume = generic_hdmi_resume,
2425#endif
2426};
2427
2428static const struct hdmi_ops generic_standard_hdmi_ops = {
2429 .pin_get_eld = hdmi_pin_get_eld,
2430 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2431 .pin_hbr_setup = hdmi_pin_hbr_setup,
2432 .setup_stream = hdmi_setup_stream,
2433};
2434
2435/* allocate codec->spec and assign/initialize generic parser ops */
2436static int alloc_generic_hdmi(struct hda_codec *codec)
2437{
2438 struct hdmi_spec *spec;
2439
2440 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2441 if (!spec)
2442 return -ENOMEM;
2443
2444 spec->codec = codec;
2445 spec->ops = generic_standard_hdmi_ops;
2446 spec->dev_num = 1; /* initialize to 1 */
2447 mutex_init(&spec->pcm_lock);
2448 mutex_init(&spec->bind_lock);
2449 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2450
2451 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2452 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2453 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2454 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2455
2456 codec->spec = spec;
2457 hdmi_array_init(spec, 4);
2458
2459 codec->patch_ops = generic_hdmi_patch_ops;
2460
2461 return 0;
2462}
2463
2464/* generic HDMI parser */
2465static int patch_generic_hdmi(struct hda_codec *codec)
2466{
2467 int err;
2468
2469 err = alloc_generic_hdmi(codec);
2470 if (err < 0)
2471 return err;
2472
2473 err = hdmi_parse_codec(codec);
2474 if (err < 0) {
2475 generic_spec_free(codec);
2476 return err;
2477 }
2478
2479 generic_hdmi_init_per_pins(codec);
2480 return 0;
2481}
2482
2483/*
2484 * generic audio component binding
2485 */
2486
2487/* turn on / off the unsol event jack detection dynamically */
2488static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2489 int dev_id, bool use_acomp)
2490{
2491 struct hda_jack_tbl *tbl;
2492
2493 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2494 if (tbl) {
2495 /* clear unsol even if component notifier is used, or re-enable
2496 * if notifier is cleared
2497 */
2498 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2499 snd_hda_codec_write_cache(codec, nid, 0,
2500 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2501 }
2502}
2503
2504/* set up / clear component notifier dynamically */
2505static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2506 bool use_acomp)
2507{
2508 struct hdmi_spec *spec;
2509 int i;
2510
2511 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2512 mutex_lock(&spec->bind_lock);
2513 spec->use_acomp_notifier = use_acomp;
2514 spec->codec->relaxed_resume = use_acomp;
2515 spec->codec->bus->keep_power = 0;
2516 /* reprogram each jack detection logic depending on the notifier */
2517 for (i = 0; i < spec->num_pins; i++)
2518 reprogram_jack_detect(spec->codec,
2519 get_pin(spec, i)->pin_nid,
2520 get_pin(spec, i)->dev_id,
2521 use_acomp);
2522 mutex_unlock(&spec->bind_lock);
2523}
2524
2525/* enable / disable the notifier via master bind / unbind */
2526static int generic_acomp_master_bind(struct device *dev,
2527 struct drm_audio_component *acomp)
2528{
2529 generic_acomp_notifier_set(acomp, true);
2530 return 0;
2531}
2532
2533static void generic_acomp_master_unbind(struct device *dev,
2534 struct drm_audio_component *acomp)
2535{
2536 generic_acomp_notifier_set(acomp, false);
2537}
2538
2539/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2540static int match_bound_vga(struct device *dev, int subtype, void *data)
2541{
2542 struct hdac_bus *bus = data;
2543 struct pci_dev *pci, *master;
2544
2545 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2546 return 0;
2547 master = to_pci_dev(bus->dev);
2548 pci = to_pci_dev(dev);
2549 return master->bus == pci->bus;
2550}
2551
2552/* audio component notifier for AMD/Nvidia HDMI codecs */
2553static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2554{
2555 struct hda_codec *codec = audio_ptr;
2556 struct hdmi_spec *spec = codec->spec;
2557 hda_nid_t pin_nid = spec->port2pin(codec, port);
2558
2559 if (!pin_nid)
2560 return;
2561 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2562 return;
2563 /* skip notification during system suspend (but not in runtime PM);
2564 * the state will be updated at resume
2565 */
2566 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2567 return;
2568 /* ditto during suspend/resume process itself */
2569 if (snd_hdac_is_in_pm(&codec->core))
2570 return;
2571
2572 check_presence_and_report(codec, pin_nid, dev_id);
2573}
2574
2575/* set up the private drm_audio_ops from the template */
2576static void setup_drm_audio_ops(struct hda_codec *codec,
2577 const struct drm_audio_component_audio_ops *ops)
2578{
2579 struct hdmi_spec *spec = codec->spec;
2580
2581 spec->drm_audio_ops.audio_ptr = codec;
2582 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2583 * will call pin_eld_notify with using audio_ptr pointer
2584 * We need make sure audio_ptr is really setup
2585 */
2586 wmb();
2587 spec->drm_audio_ops.pin2port = ops->pin2port;
2588 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2589 spec->drm_audio_ops.master_bind = ops->master_bind;
2590 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2591}
2592
2593/* initialize the generic HDMI audio component */
2594static void generic_acomp_init(struct hda_codec *codec,
2595 const struct drm_audio_component_audio_ops *ops,
2596 int (*port2pin)(struct hda_codec *, int))
2597{
2598 struct hdmi_spec *spec = codec->spec;
2599
2600 if (!enable_acomp) {
2601 codec_info(codec, "audio component disabled by module option\n");
2602 return;
2603 }
2604
2605 spec->port2pin = port2pin;
2606 setup_drm_audio_ops(codec, ops);
2607 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2608 match_bound_vga, 0)) {
2609 spec->acomp_registered = true;
2610 }
2611}
2612
2613/*
2614 * Intel codec parsers and helpers
2615 */
2616
2617#define INTEL_GET_VENDOR_VERB 0xf81
2618#define INTEL_SET_VENDOR_VERB 0x781
2619#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2620#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2621
2622static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2623 bool update_tree)
2624{
2625 unsigned int vendor_param;
2626 struct hdmi_spec *spec = codec->spec;
2627
2628 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2629 INTEL_GET_VENDOR_VERB, 0);
2630 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2631 return;
2632
2633 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2634 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2635 INTEL_SET_VENDOR_VERB, vendor_param);
2636 if (vendor_param == -1)
2637 return;
2638
2639 if (update_tree)
2640 snd_hda_codec_update_widgets(codec);
2641}
2642
2643static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2644{
2645 unsigned int vendor_param;
2646 struct hdmi_spec *spec = codec->spec;
2647
2648 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2649 INTEL_GET_VENDOR_VERB, 0);
2650 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2651 return;
2652
2653 /* enable DP1.2 mode */
2654 vendor_param |= INTEL_EN_DP12;
2655 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2656 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2657 INTEL_SET_VENDOR_VERB, vendor_param);
2658}
2659
2660/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2661 * Otherwise you may get severe h/w communication errors.
2662 */
2663static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2664 unsigned int power_state)
2665{
2666 if (power_state == AC_PWRST_D0) {
2667 intel_haswell_enable_all_pins(codec, false);
2668 intel_haswell_fixup_enable_dp12(codec);
2669 }
2670
2671 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2672 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2673}
2674
2675/* There is a fixed mapping between audio pin node and display port.
2676 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2677 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2678 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2679 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2680 *
2681 * on VLV, ILK:
2682 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2683 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2684 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2685 */
2686static int intel_base_nid(struct hda_codec *codec)
2687{
2688 switch (codec->core.vendor_id) {
2689 case 0x80860054: /* ILK */
2690 case 0x80862804: /* ILK */
2691 case 0x80862882: /* VLV */
2692 return 4;
2693 default:
2694 return 5;
2695 }
2696}
2697
2698static int intel_pin2port(void *audio_ptr, int pin_nid)
2699{
2700 struct hda_codec *codec = audio_ptr;
2701 struct hdmi_spec *spec = codec->spec;
2702 int base_nid, i;
2703
2704 if (!spec->port_num) {
2705 base_nid = intel_base_nid(codec);
2706 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2707 return -1;
2708 return pin_nid - base_nid + 1;
2709 }
2710
2711 /*
2712 * looking for the pin number in the mapping table and return
2713 * the index which indicate the port number
2714 */
2715 for (i = 0; i < spec->port_num; i++) {
2716 if (pin_nid == spec->port_map[i])
2717 return i;
2718 }
2719
2720 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2721 return -1;
2722}
2723
2724static int intel_port2pin(struct hda_codec *codec, int port)
2725{
2726 struct hdmi_spec *spec = codec->spec;
2727
2728 if (!spec->port_num) {
2729 /* we assume only from port-B to port-D */
2730 if (port < 1 || port > 3)
2731 return 0;
2732 return port + intel_base_nid(codec) - 1;
2733 }
2734
2735 if (port < 0 || port >= spec->port_num)
2736 return 0;
2737 return spec->port_map[port];
2738}
2739
2740static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2741{
2742 struct hda_codec *codec = audio_ptr;
2743 int pin_nid;
2744 int dev_id = pipe;
2745
2746 pin_nid = intel_port2pin(codec, port);
2747 if (!pin_nid)
2748 return;
2749 /* skip notification during system suspend (but not in runtime PM);
2750 * the state will be updated at resume
2751 */
2752 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2753 return;
2754 /* ditto during suspend/resume process itself */
2755 if (snd_hdac_is_in_pm(&codec->core))
2756 return;
2757
2758 snd_hdac_i915_set_bclk(&codec->bus->core);
2759 check_presence_and_report(codec, pin_nid, dev_id);
2760}
2761
2762static const struct drm_audio_component_audio_ops intel_audio_ops = {
2763 .pin2port = intel_pin2port,
2764 .pin_eld_notify = intel_pin_eld_notify,
2765};
2766
2767/* register i915 component pin_eld_notify callback */
2768static void register_i915_notifier(struct hda_codec *codec)
2769{
2770 struct hdmi_spec *spec = codec->spec;
2771
2772 spec->use_acomp_notifier = true;
2773 spec->port2pin = intel_port2pin;
2774 setup_drm_audio_ops(codec, &intel_audio_ops);
2775 snd_hdac_acomp_register_notifier(&codec->bus->core,
2776 &spec->drm_audio_ops);
2777 /* no need for forcible resume for jack check thanks to notifier */
2778 codec->relaxed_resume = 1;
2779}
2780
2781/* setup_stream ops override for HSW+ */
2782static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2783 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2784 int format)
2785{
2786 haswell_verify_D0(codec, cvt_nid, pin_nid);
2787 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2788 stream_tag, format);
2789}
2790
2791/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2792static void i915_pin_cvt_fixup(struct hda_codec *codec,
2793 struct hdmi_spec_per_pin *per_pin,
2794 hda_nid_t cvt_nid)
2795{
2796 if (per_pin) {
2797 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2798 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2799 per_pin->dev_id);
2800 intel_verify_pin_cvt_connect(codec, per_pin);
2801 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2802 per_pin->dev_id, per_pin->mux_idx);
2803 } else {
2804 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2805 }
2806}
2807
2808/* precondition and allocation for Intel codecs */
2809static int alloc_intel_hdmi(struct hda_codec *codec)
2810{
2811 int err;
2812
2813 /* requires i915 binding */
2814 if (!codec->bus->core.audio_component) {
2815 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2816 /* set probe_id here to prevent generic fallback binding */
2817 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2818 return -ENODEV;
2819 }
2820
2821 err = alloc_generic_hdmi(codec);
2822 if (err < 0)
2823 return err;
2824 /* no need to handle unsol events */
2825 codec->patch_ops.unsol_event = NULL;
2826 return 0;
2827}
2828
2829/* parse and post-process for Intel codecs */
2830static int parse_intel_hdmi(struct hda_codec *codec)
2831{
2832 int err, retries = 3;
2833
2834 do {
2835 err = hdmi_parse_codec(codec);
2836 } while (err < 0 && retries--);
2837
2838 if (err < 0) {
2839 generic_spec_free(codec);
2840 return err;
2841 }
2842
2843 generic_hdmi_init_per_pins(codec);
2844 register_i915_notifier(codec);
2845 return 0;
2846}
2847
2848/* Intel Haswell and onwards; audio component with eld notifier */
2849static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2850 const int *port_map, int port_num)
2851{
2852 struct hdmi_spec *spec;
2853 int err;
2854
2855 err = alloc_intel_hdmi(codec);
2856 if (err < 0)
2857 return err;
2858 spec = codec->spec;
2859 codec->dp_mst = true;
2860 spec->dyn_pcm_assign = true;
2861 spec->vendor_nid = vendor_nid;
2862 spec->port_map = port_map;
2863 spec->port_num = port_num;
2864 spec->intel_hsw_fixup = true;
2865
2866 intel_haswell_enable_all_pins(codec, true);
2867 intel_haswell_fixup_enable_dp12(codec);
2868
2869 codec->display_power_control = 1;
2870
2871 codec->patch_ops.set_power_state = haswell_set_power_state;
2872 codec->depop_delay = 0;
2873 codec->auto_runtime_pm = 1;
2874
2875 spec->ops.setup_stream = i915_hsw_setup_stream;
2876 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2877
2878 /*
2879 * Enable silent stream feature, if it is enabled via
2880 * module param or Kconfig option
2881 */
2882 if (enable_silent_stream)
2883 spec->send_silent_stream = true;
2884
2885 return parse_intel_hdmi(codec);
2886}
2887
2888static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2889{
2890 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2891}
2892
2893static int patch_i915_glk_hdmi(struct hda_codec *codec)
2894{
2895 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2896}
2897
2898static int patch_i915_icl_hdmi(struct hda_codec *codec)
2899{
2900 /*
2901 * pin to port mapping table where the value indicate the pin number and
2902 * the index indicate the port number.
2903 */
2904 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
2905
2906 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2907}
2908
2909static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2910{
2911 /*
2912 * pin to port mapping table where the value indicate the pin number and
2913 * the index indicate the port number.
2914 */
2915 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2916
2917 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2918}
2919
2920/* Intel Baytrail and Braswell; with eld notifier */
2921static int patch_i915_byt_hdmi(struct hda_codec *codec)
2922{
2923 struct hdmi_spec *spec;
2924 int err;
2925
2926 err = alloc_intel_hdmi(codec);
2927 if (err < 0)
2928 return err;
2929 spec = codec->spec;
2930
2931 /* For Valleyview/Cherryview, only the display codec is in the display
2932 * power well and can use link_power ops to request/release the power.
2933 */
2934 codec->display_power_control = 1;
2935
2936 codec->depop_delay = 0;
2937 codec->auto_runtime_pm = 1;
2938
2939 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2940
2941 return parse_intel_hdmi(codec);
2942}
2943
2944/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2945static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2946{
2947 int err;
2948
2949 err = alloc_intel_hdmi(codec);
2950 if (err < 0)
2951 return err;
2952 return parse_intel_hdmi(codec);
2953}
2954
2955/*
2956 * Shared non-generic implementations
2957 */
2958
2959static int simple_playback_build_pcms(struct hda_codec *codec)
2960{
2961 struct hdmi_spec *spec = codec->spec;
2962 struct hda_pcm *info;
2963 unsigned int chans;
2964 struct hda_pcm_stream *pstr;
2965 struct hdmi_spec_per_cvt *per_cvt;
2966
2967 per_cvt = get_cvt(spec, 0);
2968 chans = get_wcaps(codec, per_cvt->cvt_nid);
2969 chans = get_wcaps_channels(chans);
2970
2971 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2972 if (!info)
2973 return -ENOMEM;
2974 spec->pcm_rec[0].pcm = info;
2975 info->pcm_type = HDA_PCM_TYPE_HDMI;
2976 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2977 *pstr = spec->pcm_playback;
2978 pstr->nid = per_cvt->cvt_nid;
2979 if (pstr->channels_max <= 2 && chans && chans <= 16)
2980 pstr->channels_max = chans;
2981
2982 return 0;
2983}
2984
2985/* unsolicited event for jack sensing */
2986static void simple_hdmi_unsol_event(struct hda_codec *codec,
2987 unsigned int res)
2988{
2989 snd_hda_jack_set_dirty_all(codec);
2990 snd_hda_jack_report_sync(codec);
2991}
2992
2993/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2994 * as long as spec->pins[] is set correctly
2995 */
2996#define simple_hdmi_build_jack generic_hdmi_build_jack
2997
2998static int simple_playback_build_controls(struct hda_codec *codec)
2999{
3000 struct hdmi_spec *spec = codec->spec;
3001 struct hdmi_spec_per_cvt *per_cvt;
3002 int err;
3003
3004 per_cvt = get_cvt(spec, 0);
3005 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3006 per_cvt->cvt_nid,
3007 HDA_PCM_TYPE_HDMI);
3008 if (err < 0)
3009 return err;
3010 return simple_hdmi_build_jack(codec, 0);
3011}
3012
3013static int simple_playback_init(struct hda_codec *codec)
3014{
3015 struct hdmi_spec *spec = codec->spec;
3016 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3017 hda_nid_t pin = per_pin->pin_nid;
3018
3019 snd_hda_codec_write(codec, pin, 0,
3020 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3021 /* some codecs require to unmute the pin */
3022 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3023 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3024 AMP_OUT_UNMUTE);
3025 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3026 return 0;
3027}
3028
3029static void simple_playback_free(struct hda_codec *codec)
3030{
3031 struct hdmi_spec *spec = codec->spec;
3032
3033 hdmi_array_free(spec);
3034 kfree(spec);
3035}
3036
3037/*
3038 * Nvidia specific implementations
3039 */
3040
3041#define Nv_VERB_SET_Channel_Allocation 0xF79
3042#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3043#define Nv_VERB_SET_Audio_Protection_On 0xF98
3044#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3045
3046#define nvhdmi_master_con_nid_7x 0x04
3047#define nvhdmi_master_pin_nid_7x 0x05
3048
3049static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3050 /*front, rear, clfe, rear_surr */
3051 0x6, 0x8, 0xa, 0xc,
3052};
3053
3054static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3055 /* set audio protect on */
3056 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3057 /* enable digital output on pin widget */
3058 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3059 {} /* terminator */
3060};
3061
3062static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3063 /* set audio protect on */
3064 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3065 /* enable digital output on pin widget */
3066 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3067 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3068 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3069 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3070 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3071 {} /* terminator */
3072};
3073
3074#ifdef LIMITED_RATE_FMT_SUPPORT
3075/* support only the safe format and rate */
3076#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3077#define SUPPORTED_MAXBPS 16
3078#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3079#else
3080/* support all rates and formats */
3081#define SUPPORTED_RATES \
3082 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3083 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3084 SNDRV_PCM_RATE_192000)
3085#define SUPPORTED_MAXBPS 24
3086#define SUPPORTED_FORMATS \
3087 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3088#endif
3089
3090static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3091{
3092 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3093 return 0;
3094}
3095
3096static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3097{
3098 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3099 return 0;
3100}
3101
3102static const unsigned int channels_2_6_8[] = {
3103 2, 6, 8
3104};
3105
3106static const unsigned int channels_2_8[] = {
3107 2, 8
3108};
3109
3110static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3111 .count = ARRAY_SIZE(channels_2_6_8),
3112 .list = channels_2_6_8,
3113 .mask = 0,
3114};
3115
3116static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3117 .count = ARRAY_SIZE(channels_2_8),
3118 .list = channels_2_8,
3119 .mask = 0,
3120};
3121
3122static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3123 struct hda_codec *codec,
3124 struct snd_pcm_substream *substream)
3125{
3126 struct hdmi_spec *spec = codec->spec;
3127 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3128
3129 switch (codec->preset->vendor_id) {
3130 case 0x10de0002:
3131 case 0x10de0003:
3132 case 0x10de0005:
3133 case 0x10de0006:
3134 hw_constraints_channels = &hw_constraints_2_8_channels;
3135 break;
3136 case 0x10de0007:
3137 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3138 break;
3139 default:
3140 break;
3141 }
3142
3143 if (hw_constraints_channels != NULL) {
3144 snd_pcm_hw_constraint_list(substream->runtime, 0,
3145 SNDRV_PCM_HW_PARAM_CHANNELS,
3146 hw_constraints_channels);
3147 } else {
3148 snd_pcm_hw_constraint_step(substream->runtime, 0,
3149 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3150 }
3151
3152 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3153}
3154
3155static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3156 struct hda_codec *codec,
3157 struct snd_pcm_substream *substream)
3158{
3159 struct hdmi_spec *spec = codec->spec;
3160 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3161}
3162
3163static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3164 struct hda_codec *codec,
3165 unsigned int stream_tag,
3166 unsigned int format,
3167 struct snd_pcm_substream *substream)
3168{
3169 struct hdmi_spec *spec = codec->spec;
3170 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3171 stream_tag, format, substream);
3172}
3173
3174static const struct hda_pcm_stream simple_pcm_playback = {
3175 .substreams = 1,
3176 .channels_min = 2,
3177 .channels_max = 2,
3178 .ops = {
3179 .open = simple_playback_pcm_open,
3180 .close = simple_playback_pcm_close,
3181 .prepare = simple_playback_pcm_prepare
3182 },
3183};
3184
3185static const struct hda_codec_ops simple_hdmi_patch_ops = {
3186 .build_controls = simple_playback_build_controls,
3187 .build_pcms = simple_playback_build_pcms,
3188 .init = simple_playback_init,
3189 .free = simple_playback_free,
3190 .unsol_event = simple_hdmi_unsol_event,
3191};
3192
3193static int patch_simple_hdmi(struct hda_codec *codec,
3194 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3195{
3196 struct hdmi_spec *spec;
3197 struct hdmi_spec_per_cvt *per_cvt;
3198 struct hdmi_spec_per_pin *per_pin;
3199
3200 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3201 if (!spec)
3202 return -ENOMEM;
3203
3204 spec->codec = codec;
3205 codec->spec = spec;
3206 hdmi_array_init(spec, 1);
3207
3208 spec->multiout.num_dacs = 0; /* no analog */
3209 spec->multiout.max_channels = 2;
3210 spec->multiout.dig_out_nid = cvt_nid;
3211 spec->num_cvts = 1;
3212 spec->num_pins = 1;
3213 per_pin = snd_array_new(&spec->pins);
3214 per_cvt = snd_array_new(&spec->cvts);
3215 if (!per_pin || !per_cvt) {
3216 simple_playback_free(codec);
3217 return -ENOMEM;
3218 }
3219 per_cvt->cvt_nid = cvt_nid;
3220 per_pin->pin_nid = pin_nid;
3221 spec->pcm_playback = simple_pcm_playback;
3222
3223 codec->patch_ops = simple_hdmi_patch_ops;
3224
3225 return 0;
3226}
3227
3228static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3229 int channels)
3230{
3231 unsigned int chanmask;
3232 int chan = channels ? (channels - 1) : 1;
3233
3234 switch (channels) {
3235 default:
3236 case 0:
3237 case 2:
3238 chanmask = 0x00;
3239 break;
3240 case 4:
3241 chanmask = 0x08;
3242 break;
3243 case 6:
3244 chanmask = 0x0b;
3245 break;
3246 case 8:
3247 chanmask = 0x13;
3248 break;
3249 }
3250
3251 /* Set the audio infoframe channel allocation and checksum fields. The
3252 * channel count is computed implicitly by the hardware. */
3253 snd_hda_codec_write(codec, 0x1, 0,
3254 Nv_VERB_SET_Channel_Allocation, chanmask);
3255
3256 snd_hda_codec_write(codec, 0x1, 0,
3257 Nv_VERB_SET_Info_Frame_Checksum,
3258 (0x71 - chan - chanmask));
3259}
3260
3261static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3262 struct hda_codec *codec,
3263 struct snd_pcm_substream *substream)
3264{
3265 struct hdmi_spec *spec = codec->spec;
3266 int i;
3267
3268 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3269 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3270 for (i = 0; i < 4; i++) {
3271 /* set the stream id */
3272 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3273 AC_VERB_SET_CHANNEL_STREAMID, 0);
3274 /* set the stream format */
3275 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3276 AC_VERB_SET_STREAM_FORMAT, 0);
3277 }
3278
3279 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3280 * streams are disabled. */
3281 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3282
3283 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3284}
3285
3286static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3287 struct hda_codec *codec,
3288 unsigned int stream_tag,
3289 unsigned int format,
3290 struct snd_pcm_substream *substream)
3291{
3292 int chs;
3293 unsigned int dataDCC2, channel_id;
3294 int i;
3295 struct hdmi_spec *spec = codec->spec;
3296 struct hda_spdif_out *spdif;
3297 struct hdmi_spec_per_cvt *per_cvt;
3298
3299 mutex_lock(&codec->spdif_mutex);
3300 per_cvt = get_cvt(spec, 0);
3301 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3302
3303 chs = substream->runtime->channels;
3304
3305 dataDCC2 = 0x2;
3306
3307 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3308 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3309 snd_hda_codec_write(codec,
3310 nvhdmi_master_con_nid_7x,
3311 0,
3312 AC_VERB_SET_DIGI_CONVERT_1,
3313 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3314
3315 /* set the stream id */
3316 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3317 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3318
3319 /* set the stream format */
3320 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3321 AC_VERB_SET_STREAM_FORMAT, format);
3322
3323 /* turn on again (if needed) */
3324 /* enable and set the channel status audio/data flag */
3325 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3326 snd_hda_codec_write(codec,
3327 nvhdmi_master_con_nid_7x,
3328 0,
3329 AC_VERB_SET_DIGI_CONVERT_1,
3330 spdif->ctls & 0xff);
3331 snd_hda_codec_write(codec,
3332 nvhdmi_master_con_nid_7x,
3333 0,
3334 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3335 }
3336
3337 for (i = 0; i < 4; i++) {
3338 if (chs == 2)
3339 channel_id = 0;
3340 else
3341 channel_id = i * 2;
3342
3343 /* turn off SPDIF once;
3344 *otherwise the IEC958 bits won't be updated
3345 */
3346 if (codec->spdif_status_reset &&
3347 (spdif->ctls & AC_DIG1_ENABLE))
3348 snd_hda_codec_write(codec,
3349 nvhdmi_con_nids_7x[i],
3350 0,
3351 AC_VERB_SET_DIGI_CONVERT_1,
3352 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3353 /* set the stream id */
3354 snd_hda_codec_write(codec,
3355 nvhdmi_con_nids_7x[i],
3356 0,
3357 AC_VERB_SET_CHANNEL_STREAMID,
3358 (stream_tag << 4) | channel_id);
3359 /* set the stream format */
3360 snd_hda_codec_write(codec,
3361 nvhdmi_con_nids_7x[i],
3362 0,
3363 AC_VERB_SET_STREAM_FORMAT,
3364 format);
3365 /* turn on again (if needed) */
3366 /* enable and set the channel status audio/data flag */
3367 if (codec->spdif_status_reset &&
3368 (spdif->ctls & AC_DIG1_ENABLE)) {
3369 snd_hda_codec_write(codec,
3370 nvhdmi_con_nids_7x[i],
3371 0,
3372 AC_VERB_SET_DIGI_CONVERT_1,
3373 spdif->ctls & 0xff);
3374 snd_hda_codec_write(codec,
3375 nvhdmi_con_nids_7x[i],
3376 0,
3377 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3378 }
3379 }
3380
3381 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3382
3383 mutex_unlock(&codec->spdif_mutex);
3384 return 0;
3385}
3386
3387static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3388 .substreams = 1,
3389 .channels_min = 2,
3390 .channels_max = 8,
3391 .nid = nvhdmi_master_con_nid_7x,
3392 .rates = SUPPORTED_RATES,
3393 .maxbps = SUPPORTED_MAXBPS,
3394 .formats = SUPPORTED_FORMATS,
3395 .ops = {
3396 .open = simple_playback_pcm_open,
3397 .close = nvhdmi_8ch_7x_pcm_close,
3398 .prepare = nvhdmi_8ch_7x_pcm_prepare
3399 },
3400};
3401
3402static int patch_nvhdmi_2ch(struct hda_codec *codec)
3403{
3404 struct hdmi_spec *spec;
3405 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3406 nvhdmi_master_pin_nid_7x);
3407 if (err < 0)
3408 return err;
3409
3410 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3411 /* override the PCM rates, etc, as the codec doesn't give full list */
3412 spec = codec->spec;
3413 spec->pcm_playback.rates = SUPPORTED_RATES;
3414 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3415 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3416 return 0;
3417}
3418
3419static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3420{
3421 struct hdmi_spec *spec = codec->spec;
3422 int err = simple_playback_build_pcms(codec);
3423 if (!err) {
3424 struct hda_pcm *info = get_pcm_rec(spec, 0);
3425 info->own_chmap = true;
3426 }
3427 return err;
3428}
3429
3430static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3431{
3432 struct hdmi_spec *spec = codec->spec;
3433 struct hda_pcm *info;
3434 struct snd_pcm_chmap *chmap;
3435 int err;
3436
3437 err = simple_playback_build_controls(codec);
3438 if (err < 0)
3439 return err;
3440
3441 /* add channel maps */
3442 info = get_pcm_rec(spec, 0);
3443 err = snd_pcm_add_chmap_ctls(info->pcm,
3444 SNDRV_PCM_STREAM_PLAYBACK,
3445 snd_pcm_alt_chmaps, 8, 0, &chmap);
3446 if (err < 0)
3447 return err;
3448 switch (codec->preset->vendor_id) {
3449 case 0x10de0002:
3450 case 0x10de0003:
3451 case 0x10de0005:
3452 case 0x10de0006:
3453 chmap->channel_mask = (1U << 2) | (1U << 8);
3454 break;
3455 case 0x10de0007:
3456 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3457 }
3458 return 0;
3459}
3460
3461static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3462{
3463 struct hdmi_spec *spec;
3464 int err = patch_nvhdmi_2ch(codec);
3465 if (err < 0)
3466 return err;
3467 spec = codec->spec;
3468 spec->multiout.max_channels = 8;
3469 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3470 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3471 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3472 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3473
3474 /* Initialize the audio infoframe channel mask and checksum to something
3475 * valid */
3476 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3477
3478 return 0;
3479}
3480
3481/*
3482 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3483 * - 0x10de0015
3484 * - 0x10de0040
3485 */
3486static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3487 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3488{
3489 if (cap->ca_index == 0x00 && channels == 2)
3490 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3491
3492 /* If the speaker allocation matches the channel count, it is OK. */
3493 if (cap->channels != channels)
3494 return -1;
3495
3496 /* all channels are remappable freely */
3497 return SNDRV_CTL_TLVT_CHMAP_VAR;
3498}
3499
3500static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3501 int ca, int chs, unsigned char *map)
3502{
3503 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3504 return -EINVAL;
3505
3506 return 0;
3507}
3508
3509/* map from pin NID to port; port is 0-based */
3510/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3511static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3512{
3513 return pin_nid - 4;
3514}
3515
3516/* reverse-map from port to pin NID: see above */
3517static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3518{
3519 return port + 4;
3520}
3521
3522static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3523 .pin2port = nvhdmi_pin2port,
3524 .pin_eld_notify = generic_acomp_pin_eld_notify,
3525 .master_bind = generic_acomp_master_bind,
3526 .master_unbind = generic_acomp_master_unbind,
3527};
3528
3529static int patch_nvhdmi(struct hda_codec *codec)
3530{
3531 struct hdmi_spec *spec;
3532 int err;
3533
3534 err = alloc_generic_hdmi(codec);
3535 if (err < 0)
3536 return err;
3537 codec->dp_mst = true;
3538
3539 spec = codec->spec;
3540 spec->dyn_pcm_assign = true;
3541
3542 err = hdmi_parse_codec(codec);
3543 if (err < 0) {
3544 generic_spec_free(codec);
3545 return err;
3546 }
3547
3548 generic_hdmi_init_per_pins(codec);
3549
3550 spec->dyn_pin_out = true;
3551
3552 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3553 nvhdmi_chmap_cea_alloc_validate_get_type;
3554 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3555
3556 codec->link_down_at_suspend = 1;
3557
3558 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3559
3560 return 0;
3561}
3562
3563static int patch_nvhdmi_legacy(struct hda_codec *codec)
3564{
3565 struct hdmi_spec *spec;
3566 int err;
3567
3568 err = patch_generic_hdmi(codec);
3569 if (err)
3570 return err;
3571
3572 spec = codec->spec;
3573 spec->dyn_pin_out = true;
3574
3575 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3576 nvhdmi_chmap_cea_alloc_validate_get_type;
3577 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3578
3579 codec->link_down_at_suspend = 1;
3580
3581 return 0;
3582}
3583
3584/*
3585 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3586 * accessed using vendor-defined verbs. These registers can be used for
3587 * interoperability between the HDA and HDMI drivers.
3588 */
3589
3590/* Audio Function Group node */
3591#define NVIDIA_AFG_NID 0x01
3592
3593/*
3594 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3595 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3596 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3597 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3598 * additional bit (at position 30) to signal the validity of the format.
3599 *
3600 * | 31 | 30 | 29 16 | 15 0 |
3601 * +---------+-------+--------+--------+
3602 * | TRIGGER | VALID | UNUSED | FORMAT |
3603 * +-----------------------------------|
3604 *
3605 * Note that for the trigger bit to take effect it needs to change value
3606 * (i.e. it needs to be toggled).
3607 */
3608#define NVIDIA_GET_SCRATCH0 0xfa6
3609#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3610#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3611#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3612#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3613#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3614#define NVIDIA_SCRATCH_VALID (1 << 6)
3615
3616#define NVIDIA_GET_SCRATCH1 0xfab
3617#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3618#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3619#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3620#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3621
3622/*
3623 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3624 * the format is invalidated so that the HDMI codec can be disabled.
3625 */
3626static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3627{
3628 unsigned int value;
3629
3630 /* bits [31:30] contain the trigger and valid bits */
3631 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3632 NVIDIA_GET_SCRATCH0, 0);
3633 value = (value >> 24) & 0xff;
3634
3635 /* bits [15:0] are used to store the HDA format */
3636 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3637 NVIDIA_SET_SCRATCH0_BYTE0,
3638 (format >> 0) & 0xff);
3639 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3640 NVIDIA_SET_SCRATCH0_BYTE1,
3641 (format >> 8) & 0xff);
3642
3643 /* bits [16:24] are unused */
3644 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3645 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3646
3647 /*
3648 * Bit 30 signals that the data is valid and hence that HDMI audio can
3649 * be enabled.
3650 */
3651 if (format == 0)
3652 value &= ~NVIDIA_SCRATCH_VALID;
3653 else
3654 value |= NVIDIA_SCRATCH_VALID;
3655
3656 /*
3657 * Whenever the trigger bit is toggled, an interrupt is raised in the
3658 * HDMI codec. The HDMI driver will use that as trigger to update its
3659 * configuration.
3660 */
3661 value ^= NVIDIA_SCRATCH_TRIGGER;
3662
3663 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3664 NVIDIA_SET_SCRATCH0_BYTE3, value);
3665}
3666
3667static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3668 struct hda_codec *codec,
3669 unsigned int stream_tag,
3670 unsigned int format,
3671 struct snd_pcm_substream *substream)
3672{
3673 int err;
3674
3675 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3676 format, substream);
3677 if (err < 0)
3678 return err;
3679
3680 /* notify the HDMI codec of the format change */
3681 tegra_hdmi_set_format(codec, format);
3682
3683 return 0;
3684}
3685
3686static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3687 struct hda_codec *codec,
3688 struct snd_pcm_substream *substream)
3689{
3690 /* invalidate the format in the HDMI codec */
3691 tegra_hdmi_set_format(codec, 0);
3692
3693 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3694}
3695
3696static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3697{
3698 struct hdmi_spec *spec = codec->spec;
3699 unsigned int i;
3700
3701 for (i = 0; i < spec->num_pins; i++) {
3702 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3703
3704 if (pcm->pcm_type == type)
3705 return pcm;
3706 }
3707
3708 return NULL;
3709}
3710
3711static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3712{
3713 struct hda_pcm_stream *stream;
3714 struct hda_pcm *pcm;
3715 int err;
3716
3717 err = generic_hdmi_build_pcms(codec);
3718 if (err < 0)
3719 return err;
3720
3721 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3722 if (!pcm)
3723 return -ENODEV;
3724
3725 /*
3726 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3727 * codec about format changes.
3728 */
3729 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3730 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3731 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3732
3733 return 0;
3734}
3735
3736static int patch_tegra_hdmi(struct hda_codec *codec)
3737{
3738 struct hdmi_spec *spec;
3739 int err;
3740
3741 err = patch_generic_hdmi(codec);
3742 if (err)
3743 return err;
3744
3745 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3746 spec = codec->spec;
3747 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3748 nvhdmi_chmap_cea_alloc_validate_get_type;
3749 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3750
3751 return 0;
3752}
3753
3754/*
3755 * ATI/AMD-specific implementations
3756 */
3757
3758#define is_amdhdmi_rev3_or_later(codec) \
3759 ((codec)->core.vendor_id == 0x1002aa01 && \
3760 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3761#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3762
3763/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3764#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3765#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3766#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3767#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3768#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3769#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3770#define ATI_VERB_SET_HBR_CONTROL 0x77c
3771#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3772#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3773#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3774#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3775#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3776#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3777#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3778#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3779#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3780#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3781#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3782#define ATI_VERB_GET_HBR_CONTROL 0xf7c
3783#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3784#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3785#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3786#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3787#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3788
3789/* AMD specific HDA cvt verbs */
3790#define ATI_VERB_SET_RAMP_RATE 0x770
3791#define ATI_VERB_GET_RAMP_RATE 0xf70
3792
3793#define ATI_OUT_ENABLE 0x1
3794
3795#define ATI_MULTICHANNEL_MODE_PAIRED 0
3796#define ATI_MULTICHANNEL_MODE_SINGLE 1
3797
3798#define ATI_HBR_CAPABLE 0x01
3799#define ATI_HBR_ENABLE 0x10
3800
3801static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3802 int dev_id, unsigned char *buf, int *eld_size)
3803{
3804 WARN_ON(dev_id != 0);
3805 /* call hda_eld.c ATI/AMD-specific function */
3806 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3807 is_amdhdmi_rev3_or_later(codec));
3808}
3809
3810static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3811 hda_nid_t pin_nid, int dev_id, int ca,
3812 int active_channels, int conn_type)
3813{
3814 WARN_ON(dev_id != 0);
3815 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3816}
3817
3818static int atihdmi_paired_swap_fc_lfe(int pos)
3819{
3820 /*
3821 * ATI/AMD have automatic FC/LFE swap built-in
3822 * when in pairwise mapping mode.
3823 */
3824
3825 switch (pos) {
3826 /* see channel_allocations[].speakers[] */
3827 case 2: return 3;
3828 case 3: return 2;
3829 default: break;
3830 }
3831
3832 return pos;
3833}
3834
3835static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3836 int ca, int chs, unsigned char *map)
3837{
3838 struct hdac_cea_channel_speaker_allocation *cap;
3839 int i, j;
3840
3841 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3842
3843 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3844 for (i = 0; i < chs; ++i) {
3845 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3846 bool ok = false;
3847 bool companion_ok = false;
3848
3849 if (!mask)
3850 continue;
3851
3852 for (j = 0 + i % 2; j < 8; j += 2) {
3853 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3854 if (cap->speakers[chan_idx] == mask) {
3855 /* channel is in a supported position */
3856 ok = true;
3857
3858 if (i % 2 == 0 && i + 1 < chs) {
3859 /* even channel, check the odd companion */
3860 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3861 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3862 int comp_mask_act = cap->speakers[comp_chan_idx];
3863
3864 if (comp_mask_req == comp_mask_act)
3865 companion_ok = true;
3866 else
3867 return -EINVAL;
3868 }
3869 break;
3870 }
3871 }
3872
3873 if (!ok)
3874 return -EINVAL;
3875
3876 if (companion_ok)
3877 i++; /* companion channel already checked */
3878 }
3879
3880 return 0;
3881}
3882
3883static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3884 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3885{
3886 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3887 int verb;
3888 int ati_channel_setup = 0;
3889
3890 if (hdmi_slot > 7)
3891 return -EINVAL;
3892
3893 if (!has_amd_full_remap_support(codec)) {
3894 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3895
3896 /* In case this is an odd slot but without stream channel, do not
3897 * disable the slot since the corresponding even slot could have a
3898 * channel. In case neither have a channel, the slot pair will be
3899 * disabled when this function is called for the even slot. */
3900 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3901 return 0;
3902
3903 hdmi_slot -= hdmi_slot % 2;
3904
3905 if (stream_channel != 0xf)
3906 stream_channel -= stream_channel % 2;
3907 }
3908
3909 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3910
3911 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3912
3913 if (stream_channel != 0xf)
3914 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3915
3916 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3917}
3918
3919static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3920 hda_nid_t pin_nid, int asp_slot)
3921{
3922 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3923 bool was_odd = false;
3924 int ati_asp_slot = asp_slot;
3925 int verb;
3926 int ati_channel_setup;
3927
3928 if (asp_slot > 7)
3929 return -EINVAL;
3930
3931 if (!has_amd_full_remap_support(codec)) {
3932 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3933 if (ati_asp_slot % 2 != 0) {
3934 ati_asp_slot -= 1;
3935 was_odd = true;
3936 }
3937 }
3938
3939 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3940
3941 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3942
3943 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3944 return 0xf;
3945
3946 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3947}
3948
3949static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3950 struct hdac_chmap *chmap,
3951 struct hdac_cea_channel_speaker_allocation *cap,
3952 int channels)
3953{
3954 int c;
3955
3956 /*
3957 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3958 * we need to take that into account (a single channel may take 2
3959 * channel slots if we need to carry a silent channel next to it).
3960 * On Rev3+ AMD codecs this function is not used.
3961 */
3962 int chanpairs = 0;
3963
3964 /* We only produce even-numbered channel count TLVs */
3965 if ((channels % 2) != 0)
3966 return -1;
3967
3968 for (c = 0; c < 7; c += 2) {
3969 if (cap->speakers[c] || cap->speakers[c+1])
3970 chanpairs++;
3971 }
3972
3973 if (chanpairs * 2 != channels)
3974 return -1;
3975
3976 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3977}
3978
3979static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3980 struct hdac_cea_channel_speaker_allocation *cap,
3981 unsigned int *chmap, int channels)
3982{
3983 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3984 int count = 0;
3985 int c;
3986
3987 for (c = 7; c >= 0; c--) {
3988 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3989 int spk = cap->speakers[chan];
3990 if (!spk) {
3991 /* add N/A channel if the companion channel is occupied */
3992 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3993 chmap[count++] = SNDRV_CHMAP_NA;
3994
3995 continue;
3996 }
3997
3998 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3999 }
4000
4001 WARN_ON(count != channels);
4002}
4003
4004static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4005 int dev_id, bool hbr)
4006{
4007 int hbr_ctl, hbr_ctl_new;
4008
4009 WARN_ON(dev_id != 0);
4010
4011 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4012 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4013 if (hbr)
4014 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4015 else
4016 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4017
4018 codec_dbg(codec,
4019 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4020 pin_nid,
4021 hbr_ctl == hbr_ctl_new ? "" : "new-",
4022 hbr_ctl_new);
4023
4024 if (hbr_ctl != hbr_ctl_new)
4025 snd_hda_codec_write(codec, pin_nid, 0,
4026 ATI_VERB_SET_HBR_CONTROL,
4027 hbr_ctl_new);
4028
4029 } else if (hbr)
4030 return -EINVAL;
4031
4032 return 0;
4033}
4034
4035static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4036 hda_nid_t pin_nid, int dev_id,
4037 u32 stream_tag, int format)
4038{
4039 if (is_amdhdmi_rev3_or_later(codec)) {
4040 int ramp_rate = 180; /* default as per AMD spec */
4041 /* disable ramp-up/down for non-pcm as per AMD spec */
4042 if (format & AC_FMT_TYPE_NON_PCM)
4043 ramp_rate = 0;
4044
4045 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4046 }
4047
4048 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4049 stream_tag, format);
4050}
4051
4052
4053static int atihdmi_init(struct hda_codec *codec)
4054{
4055 struct hdmi_spec *spec = codec->spec;
4056 int pin_idx, err;
4057
4058 err = generic_hdmi_init(codec);
4059
4060 if (err)
4061 return err;
4062
4063 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4064 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4065
4066 /* make sure downmix information in infoframe is zero */
4067 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4068
4069 /* enable channel-wise remap mode if supported */
4070 if (has_amd_full_remap_support(codec))
4071 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4072 ATI_VERB_SET_MULTICHANNEL_MODE,
4073 ATI_MULTICHANNEL_MODE_SINGLE);
4074 }
4075 codec->auto_runtime_pm = 1;
4076
4077 return 0;
4078}
4079
4080/* map from pin NID to port; port is 0-based */
4081/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4082static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4083{
4084 return pin_nid / 2 - 1;
4085}
4086
4087/* reverse-map from port to pin NID: see above */
4088static int atihdmi_port2pin(struct hda_codec *codec, int port)
4089{
4090 return port * 2 + 3;
4091}
4092
4093static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4094 .pin2port = atihdmi_pin2port,
4095 .pin_eld_notify = generic_acomp_pin_eld_notify,
4096 .master_bind = generic_acomp_master_bind,
4097 .master_unbind = generic_acomp_master_unbind,
4098};
4099
4100static int patch_atihdmi(struct hda_codec *codec)
4101{
4102 struct hdmi_spec *spec;
4103 struct hdmi_spec_per_cvt *per_cvt;
4104 int err, cvt_idx;
4105
4106 err = patch_generic_hdmi(codec);
4107
4108 if (err)
4109 return err;
4110
4111 codec->patch_ops.init = atihdmi_init;
4112
4113 spec = codec->spec;
4114
4115 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4116 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4117 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4118 spec->ops.setup_stream = atihdmi_setup_stream;
4119
4120 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4121 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4122
4123 if (!has_amd_full_remap_support(codec)) {
4124 /* override to ATI/AMD-specific versions with pairwise mapping */
4125 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4126 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4127 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4128 atihdmi_paired_cea_alloc_to_tlv_chmap;
4129 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4130 }
4131
4132 /* ATI/AMD converters do not advertise all of their capabilities */
4133 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4134 per_cvt = get_cvt(spec, cvt_idx);
4135 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4136 per_cvt->rates |= SUPPORTED_RATES;
4137 per_cvt->formats |= SUPPORTED_FORMATS;
4138 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4139 }
4140
4141 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4142
4143 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4144 * the link-down as is. Tell the core to allow it.
4145 */
4146 codec->link_down_at_suspend = 1;
4147
4148 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4149
4150 return 0;
4151}
4152
4153/* VIA HDMI Implementation */
4154#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4155#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4156
4157static int patch_via_hdmi(struct hda_codec *codec)
4158{
4159 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4160}
4161
4162/*
4163 * patch entries
4164 */
4165static const struct hda_device_id snd_hda_id_hdmi[] = {
4166HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4167HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4168HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4169HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4170HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4171HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4172HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4173HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4174HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4175HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4176HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4177HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4178HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4179HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4180HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4181HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4182HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4183HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4184HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4185HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4186HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4187HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4188HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4189HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4190HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4191HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4192HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4193/* 17 is known to be absent */
4194HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4195HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4196HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4197HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4198HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4199HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4200HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4201HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4202HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4203HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4204HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4205HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4206HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4207HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4208HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4209HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4210HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4211HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4212HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4213HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4214HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4215HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4216HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4217HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4218HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4219HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4220HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4221HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4222HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4223HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4224HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4225HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4226HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4227HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4228HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4229HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4230HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4231HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4232HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4233HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4234HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4235HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4236HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4237HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4238HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4239HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4240HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4241HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4242HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4243HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4244HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4245HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4246HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4247HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4248HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4249HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4250HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4251HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4252HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4253HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4254HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4255HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4256HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4257HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4258HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4259HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4260HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4261HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4262HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4263HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4264HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4265HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4266HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4267HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4268HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4269HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4270HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4271HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4272HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4273HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4274HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4275HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4276HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4277HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4278HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4279/* special ID for generic HDMI */
4280HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4281{} /* terminator */
4282};
4283MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4284
4285MODULE_LICENSE("GPL");
4286MODULE_DESCRIPTION("HDMI HD-audio codec");
4287MODULE_ALIAS("snd-hda-codec-intelhdmi");
4288MODULE_ALIAS("snd-hda-codec-nvhdmi");
4289MODULE_ALIAS("snd-hda-codec-atihdmi");
4290
4291static struct hda_codec_driver hdmi_driver = {
4292 .id = snd_hda_id_hdmi,
4293};
4294
4295module_hda_codec_driver(hdmi_driver);
1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#include <linux/init.h>
33#include <linux/delay.h>
34#include <linux/slab.h>
35#include <linux/module.h>
36#include <sound/core.h>
37#include <sound/jack.h>
38#include <sound/asoundef.h>
39#include <sound/tlv.h>
40#include "hda_codec.h"
41#include "hda_local.h"
42#include "hda_jack.h"
43
44static bool static_hdmi_pcm;
45module_param(static_hdmi_pcm, bool, 0644);
46MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47
48#define is_haswell(codec) ((codec)->vendor_id == 0x80862807)
49#define is_broadwell(codec) ((codec)->vendor_id == 0x80862808)
50#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec))
51
52#define is_valleyview(codec) ((codec)->vendor_id == 0x80862882)
53
54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
63
64/* max. connections to a widget */
65#define HDA_MAX_CONNECTIONS 32
66
67struct hdmi_spec_per_pin {
68 hda_nid_t pin_nid;
69 int num_mux_nids;
70 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
71 int mux_idx;
72 hda_nid_t cvt_nid;
73
74 struct hda_codec *codec;
75 struct hdmi_eld sink_eld;
76 struct mutex lock;
77 struct delayed_work work;
78 struct snd_kcontrol *eld_ctl;
79 int repoll_count;
80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
82 bool non_pcm;
83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
85 char pcm_name[8]; /* filled in build_pcm callbacks */
86#ifdef CONFIG_PROC_FS
87 struct snd_info_entry *proc_entry;
88#endif
89};
90
91struct cea_channel_speaker_allocation;
92
93/* operations used by generic code that can be overridden by patches */
94struct hdmi_ops {
95 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
96 unsigned char *buf, int *eld_size);
97
98 /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
99 int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int asp_slot);
101 int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int asp_slot, int channel);
103
104 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
105 int ca, int active_channels, int conn_type);
106
107 /* enable/disable HBR (HD passthrough) */
108 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
109
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, u32 stream_tag, int format);
112
113 /* Helpers for producing the channel map TLVs. These can be overridden
114 * for devices that have non-standard mapping requirements. */
115 int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
116 int channels);
117 void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
118 unsigned int *chmap, int channels);
119
120 /* check that the user-given chmap is supported */
121 int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
122};
123
124struct hdmi_spec {
125 int num_cvts;
126 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
127 hda_nid_t cvt_nids[4]; /* only for haswell fix */
128
129 int num_pins;
130 struct snd_array pins; /* struct hdmi_spec_per_pin */
131 struct snd_array pcm_rec; /* struct hda_pcm */
132 unsigned int channels_max; /* max over all cvts */
133
134 struct hdmi_eld temp_eld;
135 struct hdmi_ops ops;
136
137 bool dyn_pin_out;
138
139 /*
140 * Non-generic VIA/NVIDIA specific
141 */
142 struct hda_multi_out multiout;
143 struct hda_pcm_stream pcm_playback;
144};
145
146
147struct hdmi_audio_infoframe {
148 u8 type; /* 0x84 */
149 u8 ver; /* 0x01 */
150 u8 len; /* 0x0a */
151
152 u8 checksum;
153
154 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
155 u8 SS01_SF24;
156 u8 CXT04;
157 u8 CA;
158 u8 LFEPBL01_LSV36_DM_INH7;
159};
160
161struct dp_audio_infoframe {
162 u8 type; /* 0x84 */
163 u8 len; /* 0x1b */
164 u8 ver; /* 0x11 << 2 */
165
166 u8 CC02_CT47; /* match with HDMI infoframe from this on */
167 u8 SS01_SF24;
168 u8 CXT04;
169 u8 CA;
170 u8 LFEPBL01_LSV36_DM_INH7;
171};
172
173union audio_infoframe {
174 struct hdmi_audio_infoframe hdmi;
175 struct dp_audio_infoframe dp;
176 u8 bytes[0];
177};
178
179/*
180 * CEA speaker placement:
181 *
182 * FLH FCH FRH
183 * FLW FL FLC FC FRC FR FRW
184 *
185 * LFE
186 * TC
187 *
188 * RL RLC RC RRC RR
189 *
190 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
191 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
192 */
193enum cea_speaker_placement {
194 FL = (1 << 0), /* Front Left */
195 FC = (1 << 1), /* Front Center */
196 FR = (1 << 2), /* Front Right */
197 FLC = (1 << 3), /* Front Left Center */
198 FRC = (1 << 4), /* Front Right Center */
199 RL = (1 << 5), /* Rear Left */
200 RC = (1 << 6), /* Rear Center */
201 RR = (1 << 7), /* Rear Right */
202 RLC = (1 << 8), /* Rear Left Center */
203 RRC = (1 << 9), /* Rear Right Center */
204 LFE = (1 << 10), /* Low Frequency Effect */
205 FLW = (1 << 11), /* Front Left Wide */
206 FRW = (1 << 12), /* Front Right Wide */
207 FLH = (1 << 13), /* Front Left High */
208 FCH = (1 << 14), /* Front Center High */
209 FRH = (1 << 15), /* Front Right High */
210 TC = (1 << 16), /* Top Center */
211};
212
213/*
214 * ELD SA bits in the CEA Speaker Allocation data block
215 */
216static int eld_speaker_allocation_bits[] = {
217 [0] = FL | FR,
218 [1] = LFE,
219 [2] = FC,
220 [3] = RL | RR,
221 [4] = RC,
222 [5] = FLC | FRC,
223 [6] = RLC | RRC,
224 /* the following are not defined in ELD yet */
225 [7] = FLW | FRW,
226 [8] = FLH | FRH,
227 [9] = TC,
228 [10] = FCH,
229};
230
231struct cea_channel_speaker_allocation {
232 int ca_index;
233 int speakers[8];
234
235 /* derived values, just for convenience */
236 int channels;
237 int spk_mask;
238};
239
240/*
241 * ALSA sequence is:
242 *
243 * surround40 surround41 surround50 surround51 surround71
244 * ch0 front left = = = =
245 * ch1 front right = = = =
246 * ch2 rear left = = = =
247 * ch3 rear right = = = =
248 * ch4 LFE center center center
249 * ch5 LFE LFE
250 * ch6 side left
251 * ch7 side right
252 *
253 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
254 */
255static int hdmi_channel_mapping[0x32][8] = {
256 /* stereo */
257 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
258 /* 2.1 */
259 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
260 /* Dolby Surround */
261 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
262 /* surround40 */
263 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
264 /* 4ch */
265 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
266 /* surround41 */
267 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
268 /* surround50 */
269 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
270 /* surround51 */
271 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
272 /* 7.1 */
273 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
274};
275
276/*
277 * This is an ordered list!
278 *
279 * The preceding ones have better chances to be selected by
280 * hdmi_channel_allocation().
281 */
282static struct cea_channel_speaker_allocation channel_allocations[] = {
283/* channel: 7 6 5 4 3 2 1 0 */
284{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
285 /* 2.1 */
286{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
287 /* Dolby Surround */
288{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
289 /* surround40 */
290{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
291 /* surround41 */
292{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
293 /* surround50 */
294{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
295 /* surround51 */
296{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
297 /* 6.1 */
298{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
299 /* surround71 */
300{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
301
302{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
303{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
304{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
305{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
306{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
307{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
308{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
309{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
310{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
311{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
312{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
313{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
314{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
315{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
316{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
317{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
318{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
319{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
320{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
321{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
322{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
323{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
324{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
325{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
326{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
327{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
328{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
329{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
330{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
331{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
332{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
333{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
334{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
335{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
336{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
337{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
338{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
339{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
340{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
341{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
342{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
343};
344
345
346/*
347 * HDMI routines
348 */
349
350#define get_pin(spec, idx) \
351 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
352#define get_cvt(spec, idx) \
353 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
354#define get_pcm_rec(spec, idx) \
355 ((struct hda_pcm *)snd_array_elem(&spec->pcm_rec, idx))
356
357static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
358{
359 struct hdmi_spec *spec = codec->spec;
360 int pin_idx;
361
362 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
363 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
364 return pin_idx;
365
366 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
367 return -EINVAL;
368}
369
370static int hinfo_to_pin_index(struct hda_codec *codec,
371 struct hda_pcm_stream *hinfo)
372{
373 struct hdmi_spec *spec = codec->spec;
374 int pin_idx;
375
376 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
377 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
378 return pin_idx;
379
380 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
381 return -EINVAL;
382}
383
384static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
385{
386 struct hdmi_spec *spec = codec->spec;
387 int cvt_idx;
388
389 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
390 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
391 return cvt_idx;
392
393 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
394 return -EINVAL;
395}
396
397static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_info *uinfo)
399{
400 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
401 struct hdmi_spec *spec = codec->spec;
402 struct hdmi_spec_per_pin *per_pin;
403 struct hdmi_eld *eld;
404 int pin_idx;
405
406 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
407
408 pin_idx = kcontrol->private_value;
409 per_pin = get_pin(spec, pin_idx);
410 eld = &per_pin->sink_eld;
411
412 mutex_lock(&per_pin->lock);
413 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
414 mutex_unlock(&per_pin->lock);
415
416 return 0;
417}
418
419static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol)
421{
422 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
423 struct hdmi_spec *spec = codec->spec;
424 struct hdmi_spec_per_pin *per_pin;
425 struct hdmi_eld *eld;
426 int pin_idx;
427
428 pin_idx = kcontrol->private_value;
429 per_pin = get_pin(spec, pin_idx);
430 eld = &per_pin->sink_eld;
431
432 mutex_lock(&per_pin->lock);
433 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
434 mutex_unlock(&per_pin->lock);
435 snd_BUG();
436 return -EINVAL;
437 }
438
439 memset(ucontrol->value.bytes.data, 0,
440 ARRAY_SIZE(ucontrol->value.bytes.data));
441 if (eld->eld_valid)
442 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
443 eld->eld_size);
444 mutex_unlock(&per_pin->lock);
445
446 return 0;
447}
448
449static struct snd_kcontrol_new eld_bytes_ctl = {
450 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
451 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
452 .name = "ELD",
453 .info = hdmi_eld_ctl_info,
454 .get = hdmi_eld_ctl_get,
455};
456
457static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
458 int device)
459{
460 struct snd_kcontrol *kctl;
461 struct hdmi_spec *spec = codec->spec;
462 int err;
463
464 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
465 if (!kctl)
466 return -ENOMEM;
467 kctl->private_value = pin_idx;
468 kctl->id.device = device;
469
470 err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
471 if (err < 0)
472 return err;
473
474 get_pin(spec, pin_idx)->eld_ctl = kctl;
475 return 0;
476}
477
478#ifdef BE_PARANOID
479static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
480 int *packet_index, int *byte_index)
481{
482 int val;
483
484 val = snd_hda_codec_read(codec, pin_nid, 0,
485 AC_VERB_GET_HDMI_DIP_INDEX, 0);
486
487 *packet_index = val >> 5;
488 *byte_index = val & 0x1f;
489}
490#endif
491
492static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
493 int packet_index, int byte_index)
494{
495 int val;
496
497 val = (packet_index << 5) | (byte_index & 0x1f);
498
499 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
500}
501
502static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
503 unsigned char val)
504{
505 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
506}
507
508static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
509{
510 struct hdmi_spec *spec = codec->spec;
511 int pin_out;
512
513 /* Unmute */
514 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
515 snd_hda_codec_write(codec, pin_nid, 0,
516 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
517
518 if (spec->dyn_pin_out)
519 /* Disable pin out until stream is active */
520 pin_out = 0;
521 else
522 /* Enable pin out: some machines with GM965 gets broken output
523 * when the pin is disabled or changed while using with HDMI
524 */
525 pin_out = PIN_OUT;
526
527 snd_hda_codec_write(codec, pin_nid, 0,
528 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
529}
530
531static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
532{
533 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
534 AC_VERB_GET_CVT_CHAN_COUNT, 0);
535}
536
537static void hdmi_set_channel_count(struct hda_codec *codec,
538 hda_nid_t cvt_nid, int chs)
539{
540 if (chs != hdmi_get_channel_count(codec, cvt_nid))
541 snd_hda_codec_write(codec, cvt_nid, 0,
542 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
543}
544
545/*
546 * ELD proc files
547 */
548
549#ifdef CONFIG_PROC_FS
550static void print_eld_info(struct snd_info_entry *entry,
551 struct snd_info_buffer *buffer)
552{
553 struct hdmi_spec_per_pin *per_pin = entry->private_data;
554
555 mutex_lock(&per_pin->lock);
556 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
557 mutex_unlock(&per_pin->lock);
558}
559
560static void write_eld_info(struct snd_info_entry *entry,
561 struct snd_info_buffer *buffer)
562{
563 struct hdmi_spec_per_pin *per_pin = entry->private_data;
564
565 mutex_lock(&per_pin->lock);
566 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
567 mutex_unlock(&per_pin->lock);
568}
569
570static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
571{
572 char name[32];
573 struct hda_codec *codec = per_pin->codec;
574 struct snd_info_entry *entry;
575 int err;
576
577 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
578 err = snd_card_proc_new(codec->bus->card, name, &entry);
579 if (err < 0)
580 return err;
581
582 snd_info_set_text_ops(entry, per_pin, print_eld_info);
583 entry->c.text.write = write_eld_info;
584 entry->mode |= S_IWUSR;
585 per_pin->proc_entry = entry;
586
587 return 0;
588}
589
590static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
591{
592 if (!per_pin->codec->bus->shutdown && per_pin->proc_entry) {
593 snd_device_free(per_pin->codec->bus->card, per_pin->proc_entry);
594 per_pin->proc_entry = NULL;
595 }
596}
597#else
598static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
599 int index)
600{
601 return 0;
602}
603static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
604{
605}
606#endif
607
608/*
609 * Channel mapping routines
610 */
611
612/*
613 * Compute derived values in channel_allocations[].
614 */
615static void init_channel_allocations(void)
616{
617 int i, j;
618 struct cea_channel_speaker_allocation *p;
619
620 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
621 p = channel_allocations + i;
622 p->channels = 0;
623 p->spk_mask = 0;
624 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
625 if (p->speakers[j]) {
626 p->channels++;
627 p->spk_mask |= p->speakers[j];
628 }
629 }
630}
631
632static int get_channel_allocation_order(int ca)
633{
634 int i;
635
636 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
637 if (channel_allocations[i].ca_index == ca)
638 break;
639 }
640 return i;
641}
642
643/*
644 * The transformation takes two steps:
645 *
646 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
647 * spk_mask => (channel_allocations[]) => ai->CA
648 *
649 * TODO: it could select the wrong CA from multiple candidates.
650*/
651static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
652{
653 int i;
654 int ca = 0;
655 int spk_mask = 0;
656 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
657
658 /*
659 * CA defaults to 0 for basic stereo audio
660 */
661 if (channels <= 2)
662 return 0;
663
664 /*
665 * expand ELD's speaker allocation mask
666 *
667 * ELD tells the speaker mask in a compact(paired) form,
668 * expand ELD's notions to match the ones used by Audio InfoFrame.
669 */
670 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
671 if (eld->info.spk_alloc & (1 << i))
672 spk_mask |= eld_speaker_allocation_bits[i];
673 }
674
675 /* search for the first working match in the CA table */
676 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
677 if (channels == channel_allocations[i].channels &&
678 (spk_mask & channel_allocations[i].spk_mask) ==
679 channel_allocations[i].spk_mask) {
680 ca = channel_allocations[i].ca_index;
681 break;
682 }
683 }
684
685 if (!ca) {
686 /* if there was no match, select the regular ALSA channel
687 * allocation with the matching number of channels */
688 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
689 if (channels == channel_allocations[i].channels) {
690 ca = channel_allocations[i].ca_index;
691 break;
692 }
693 }
694 }
695
696 snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
697 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
698 ca, channels, buf);
699
700 return ca;
701}
702
703static void hdmi_debug_channel_mapping(struct hda_codec *codec,
704 hda_nid_t pin_nid)
705{
706#ifdef CONFIG_SND_DEBUG_VERBOSE
707 struct hdmi_spec *spec = codec->spec;
708 int i;
709 int channel;
710
711 for (i = 0; i < 8; i++) {
712 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
713 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
714 channel, i);
715 }
716#endif
717}
718
719static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
720 hda_nid_t pin_nid,
721 bool non_pcm,
722 int ca)
723{
724 struct hdmi_spec *spec = codec->spec;
725 struct cea_channel_speaker_allocation *ch_alloc;
726 int i;
727 int err;
728 int order;
729 int non_pcm_mapping[8];
730
731 order = get_channel_allocation_order(ca);
732 ch_alloc = &channel_allocations[order];
733
734 if (hdmi_channel_mapping[ca][1] == 0) {
735 int hdmi_slot = 0;
736 /* fill actual channel mappings in ALSA channel (i) order */
737 for (i = 0; i < ch_alloc->channels; i++) {
738 while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
739 hdmi_slot++; /* skip zero slots */
740
741 hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
742 }
743 /* fill the rest of the slots with ALSA channel 0xf */
744 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
745 if (!ch_alloc->speakers[7 - hdmi_slot])
746 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
747 }
748
749 if (non_pcm) {
750 for (i = 0; i < ch_alloc->channels; i++)
751 non_pcm_mapping[i] = (i << 4) | i;
752 for (; i < 8; i++)
753 non_pcm_mapping[i] = (0xf << 4) | i;
754 }
755
756 for (i = 0; i < 8; i++) {
757 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
758 int hdmi_slot = slotsetup & 0x0f;
759 int channel = (slotsetup & 0xf0) >> 4;
760 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
761 if (err) {
762 codec_dbg(codec, "HDMI: channel mapping failed\n");
763 break;
764 }
765 }
766}
767
768struct channel_map_table {
769 unsigned char map; /* ALSA API channel map position */
770 int spk_mask; /* speaker position bit mask */
771};
772
773static struct channel_map_table map_tables[] = {
774 { SNDRV_CHMAP_FL, FL },
775 { SNDRV_CHMAP_FR, FR },
776 { SNDRV_CHMAP_RL, RL },
777 { SNDRV_CHMAP_RR, RR },
778 { SNDRV_CHMAP_LFE, LFE },
779 { SNDRV_CHMAP_FC, FC },
780 { SNDRV_CHMAP_RLC, RLC },
781 { SNDRV_CHMAP_RRC, RRC },
782 { SNDRV_CHMAP_RC, RC },
783 { SNDRV_CHMAP_FLC, FLC },
784 { SNDRV_CHMAP_FRC, FRC },
785 { SNDRV_CHMAP_TFL, FLH },
786 { SNDRV_CHMAP_TFR, FRH },
787 { SNDRV_CHMAP_FLW, FLW },
788 { SNDRV_CHMAP_FRW, FRW },
789 { SNDRV_CHMAP_TC, TC },
790 { SNDRV_CHMAP_TFC, FCH },
791 {} /* terminator */
792};
793
794/* from ALSA API channel position to speaker bit mask */
795static int to_spk_mask(unsigned char c)
796{
797 struct channel_map_table *t = map_tables;
798 for (; t->map; t++) {
799 if (t->map == c)
800 return t->spk_mask;
801 }
802 return 0;
803}
804
805/* from ALSA API channel position to CEA slot */
806static int to_cea_slot(int ordered_ca, unsigned char pos)
807{
808 int mask = to_spk_mask(pos);
809 int i;
810
811 if (mask) {
812 for (i = 0; i < 8; i++) {
813 if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
814 return i;
815 }
816 }
817
818 return -1;
819}
820
821/* from speaker bit mask to ALSA API channel position */
822static int spk_to_chmap(int spk)
823{
824 struct channel_map_table *t = map_tables;
825 for (; t->map; t++) {
826 if (t->spk_mask == spk)
827 return t->map;
828 }
829 return 0;
830}
831
832/* from CEA slot to ALSA API channel position */
833static int from_cea_slot(int ordered_ca, unsigned char slot)
834{
835 int mask = channel_allocations[ordered_ca].speakers[7 - slot];
836
837 return spk_to_chmap(mask);
838}
839
840/* get the CA index corresponding to the given ALSA API channel map */
841static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
842{
843 int i, spks = 0, spk_mask = 0;
844
845 for (i = 0; i < chs; i++) {
846 int mask = to_spk_mask(map[i]);
847 if (mask) {
848 spk_mask |= mask;
849 spks++;
850 }
851 }
852
853 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
854 if ((chs == channel_allocations[i].channels ||
855 spks == channel_allocations[i].channels) &&
856 (spk_mask & channel_allocations[i].spk_mask) ==
857 channel_allocations[i].spk_mask)
858 return channel_allocations[i].ca_index;
859 }
860 return -1;
861}
862
863/* set up the channel slots for the given ALSA API channel map */
864static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
865 hda_nid_t pin_nid,
866 int chs, unsigned char *map,
867 int ca)
868{
869 struct hdmi_spec *spec = codec->spec;
870 int ordered_ca = get_channel_allocation_order(ca);
871 int alsa_pos, hdmi_slot;
872 int assignments[8] = {[0 ... 7] = 0xf};
873
874 for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
875
876 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
877
878 if (hdmi_slot < 0)
879 continue; /* unassigned channel */
880
881 assignments[hdmi_slot] = alsa_pos;
882 }
883
884 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
885 int err;
886
887 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
888 assignments[hdmi_slot]);
889 if (err)
890 return -EINVAL;
891 }
892 return 0;
893}
894
895/* store ALSA API channel map from the current default map */
896static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
897{
898 int i;
899 int ordered_ca = get_channel_allocation_order(ca);
900 for (i = 0; i < 8; i++) {
901 if (i < channel_allocations[ordered_ca].channels)
902 map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
903 else
904 map[i] = 0;
905 }
906}
907
908static void hdmi_setup_channel_mapping(struct hda_codec *codec,
909 hda_nid_t pin_nid, bool non_pcm, int ca,
910 int channels, unsigned char *map,
911 bool chmap_set)
912{
913 if (!non_pcm && chmap_set) {
914 hdmi_manual_setup_channel_mapping(codec, pin_nid,
915 channels, map, ca);
916 } else {
917 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
918 hdmi_setup_fake_chmap(map, ca);
919 }
920
921 hdmi_debug_channel_mapping(codec, pin_nid);
922}
923
924static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
925 int asp_slot, int channel)
926{
927 return snd_hda_codec_write(codec, pin_nid, 0,
928 AC_VERB_SET_HDMI_CHAN_SLOT,
929 (channel << 4) | asp_slot);
930}
931
932static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
933 int asp_slot)
934{
935 return (snd_hda_codec_read(codec, pin_nid, 0,
936 AC_VERB_GET_HDMI_CHAN_SLOT,
937 asp_slot) & 0xf0) >> 4;
938}
939
940/*
941 * Audio InfoFrame routines
942 */
943
944/*
945 * Enable Audio InfoFrame Transmission
946 */
947static void hdmi_start_infoframe_trans(struct hda_codec *codec,
948 hda_nid_t pin_nid)
949{
950 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
951 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
952 AC_DIPXMIT_BEST);
953}
954
955/*
956 * Disable Audio InfoFrame Transmission
957 */
958static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
959 hda_nid_t pin_nid)
960{
961 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
962 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
963 AC_DIPXMIT_DISABLE);
964}
965
966static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
967{
968#ifdef CONFIG_SND_DEBUG_VERBOSE
969 int i;
970 int size;
971
972 size = snd_hdmi_get_eld_size(codec, pin_nid);
973 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
974
975 for (i = 0; i < 8; i++) {
976 size = snd_hda_codec_read(codec, pin_nid, 0,
977 AC_VERB_GET_HDMI_DIP_SIZE, i);
978 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
979 }
980#endif
981}
982
983static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
984{
985#ifdef BE_PARANOID
986 int i, j;
987 int size;
988 int pi, bi;
989 for (i = 0; i < 8; i++) {
990 size = snd_hda_codec_read(codec, pin_nid, 0,
991 AC_VERB_GET_HDMI_DIP_SIZE, i);
992 if (size == 0)
993 continue;
994
995 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
996 for (j = 1; j < 1000; j++) {
997 hdmi_write_dip_byte(codec, pin_nid, 0x0);
998 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
999 if (pi != i)
1000 codec_dbg(codec, "dip index %d: %d != %d\n",
1001 bi, pi, i);
1002 if (bi == 0) /* byte index wrapped around */
1003 break;
1004 }
1005 codec_dbg(codec,
1006 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1007 i, size, j);
1008 }
1009#endif
1010}
1011
1012static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1013{
1014 u8 *bytes = (u8 *)hdmi_ai;
1015 u8 sum = 0;
1016 int i;
1017
1018 hdmi_ai->checksum = 0;
1019
1020 for (i = 0; i < sizeof(*hdmi_ai); i++)
1021 sum += bytes[i];
1022
1023 hdmi_ai->checksum = -sum;
1024}
1025
1026static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1027 hda_nid_t pin_nid,
1028 u8 *dip, int size)
1029{
1030 int i;
1031
1032 hdmi_debug_dip_size(codec, pin_nid);
1033 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1034
1035 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1036 for (i = 0; i < size; i++)
1037 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1038}
1039
1040static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1041 u8 *dip, int size)
1042{
1043 u8 val;
1044 int i;
1045
1046 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1047 != AC_DIPXMIT_BEST)
1048 return false;
1049
1050 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1051 for (i = 0; i < size; i++) {
1052 val = snd_hda_codec_read(codec, pin_nid, 0,
1053 AC_VERB_GET_HDMI_DIP_DATA, 0);
1054 if (val != dip[i])
1055 return false;
1056 }
1057
1058 return true;
1059}
1060
1061static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1062 hda_nid_t pin_nid,
1063 int ca, int active_channels,
1064 int conn_type)
1065{
1066 union audio_infoframe ai;
1067
1068 memset(&ai, 0, sizeof(ai));
1069 if (conn_type == 0) { /* HDMI */
1070 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1071
1072 hdmi_ai->type = 0x84;
1073 hdmi_ai->ver = 0x01;
1074 hdmi_ai->len = 0x0a;
1075 hdmi_ai->CC02_CT47 = active_channels - 1;
1076 hdmi_ai->CA = ca;
1077 hdmi_checksum_audio_infoframe(hdmi_ai);
1078 } else if (conn_type == 1) { /* DisplayPort */
1079 struct dp_audio_infoframe *dp_ai = &ai.dp;
1080
1081 dp_ai->type = 0x84;
1082 dp_ai->len = 0x1b;
1083 dp_ai->ver = 0x11 << 2;
1084 dp_ai->CC02_CT47 = active_channels - 1;
1085 dp_ai->CA = ca;
1086 } else {
1087 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1088 pin_nid);
1089 return;
1090 }
1091
1092 /*
1093 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1094 * sizeof(*dp_ai) to avoid partial match/update problems when
1095 * the user switches between HDMI/DP monitors.
1096 */
1097 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1098 sizeof(ai))) {
1099 codec_dbg(codec,
1100 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1101 pin_nid,
1102 active_channels, ca);
1103 hdmi_stop_infoframe_trans(codec, pin_nid);
1104 hdmi_fill_audio_infoframe(codec, pin_nid,
1105 ai.bytes, sizeof(ai));
1106 hdmi_start_infoframe_trans(codec, pin_nid);
1107 }
1108}
1109
1110static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1111 struct hdmi_spec_per_pin *per_pin,
1112 bool non_pcm)
1113{
1114 struct hdmi_spec *spec = codec->spec;
1115 hda_nid_t pin_nid = per_pin->pin_nid;
1116 int channels = per_pin->channels;
1117 int active_channels;
1118 struct hdmi_eld *eld;
1119 int ca, ordered_ca;
1120
1121 if (!channels)
1122 return;
1123
1124 if (is_haswell_plus(codec))
1125 snd_hda_codec_write(codec, pin_nid, 0,
1126 AC_VERB_SET_AMP_GAIN_MUTE,
1127 AMP_OUT_UNMUTE);
1128
1129 eld = &per_pin->sink_eld;
1130 if (!eld->monitor_present) {
1131 hdmi_set_channel_count(codec, per_pin->cvt_nid, channels);
1132 return;
1133 }
1134
1135 if (!non_pcm && per_pin->chmap_set)
1136 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1137 else
1138 ca = hdmi_channel_allocation(eld, channels);
1139 if (ca < 0)
1140 ca = 0;
1141
1142 ordered_ca = get_channel_allocation_order(ca);
1143 active_channels = channel_allocations[ordered_ca].channels;
1144
1145 hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1146
1147 /*
1148 * always configure channel mapping, it may have been changed by the
1149 * user in the meantime
1150 */
1151 hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1152 channels, per_pin->chmap,
1153 per_pin->chmap_set);
1154
1155 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1156 eld->info.conn_type);
1157
1158 per_pin->non_pcm = non_pcm;
1159}
1160
1161/*
1162 * Unsolicited events
1163 */
1164
1165static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1166
1167static void jack_callback(struct hda_codec *codec, struct hda_jack_tbl *jack)
1168{
1169 struct hdmi_spec *spec = codec->spec;
1170 int pin_idx = pin_nid_to_pin_index(codec, jack->nid);
1171 if (pin_idx < 0)
1172 return;
1173
1174 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1175 snd_hda_jack_report_sync(codec);
1176}
1177
1178static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1179{
1180 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1181 struct hda_jack_tbl *jack;
1182 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1183
1184 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1185 if (!jack)
1186 return;
1187 jack->jack_dirty = 1;
1188
1189 codec_dbg(codec,
1190 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1191 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1192 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1193
1194 jack_callback(codec, jack);
1195}
1196
1197static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1198{
1199 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1200 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1201 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1202 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1203
1204 codec_info(codec,
1205 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1206 codec->addr,
1207 tag,
1208 subtag,
1209 cp_state,
1210 cp_ready);
1211
1212 /* TODO */
1213 if (cp_state)
1214 ;
1215 if (cp_ready)
1216 ;
1217}
1218
1219
1220static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1221{
1222 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1223 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1224
1225 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1226 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1227 return;
1228 }
1229
1230 if (subtag == 0)
1231 hdmi_intrinsic_event(codec, res);
1232 else
1233 hdmi_non_intrinsic_event(codec, res);
1234}
1235
1236static void haswell_verify_D0(struct hda_codec *codec,
1237 hda_nid_t cvt_nid, hda_nid_t nid)
1238{
1239 int pwr;
1240
1241 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1242 * thus pins could only choose converter 0 for use. Make sure the
1243 * converters are in correct power state */
1244 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1245 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1246
1247 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1248 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1249 AC_PWRST_D0);
1250 msleep(40);
1251 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1252 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1253 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1254 }
1255}
1256
1257/*
1258 * Callbacks
1259 */
1260
1261/* HBR should be Non-PCM, 8 channels */
1262#define is_hbr_format(format) \
1263 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1264
1265static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1266 bool hbr)
1267{
1268 int pinctl, new_pinctl;
1269
1270 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1271 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1272 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1273
1274 if (pinctl < 0)
1275 return hbr ? -EINVAL : 0;
1276
1277 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1278 if (hbr)
1279 new_pinctl |= AC_PINCTL_EPT_HBR;
1280 else
1281 new_pinctl |= AC_PINCTL_EPT_NATIVE;
1282
1283 codec_dbg(codec,
1284 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1285 pin_nid,
1286 pinctl == new_pinctl ? "" : "new-",
1287 new_pinctl);
1288
1289 if (pinctl != new_pinctl)
1290 snd_hda_codec_write(codec, pin_nid, 0,
1291 AC_VERB_SET_PIN_WIDGET_CONTROL,
1292 new_pinctl);
1293 } else if (hbr)
1294 return -EINVAL;
1295
1296 return 0;
1297}
1298
1299static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1300 hda_nid_t pin_nid, u32 stream_tag, int format)
1301{
1302 struct hdmi_spec *spec = codec->spec;
1303 int err;
1304
1305 if (is_haswell_plus(codec))
1306 haswell_verify_D0(codec, cvt_nid, pin_nid);
1307
1308 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1309
1310 if (err) {
1311 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1312 return err;
1313 }
1314
1315 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1316 return 0;
1317}
1318
1319static int hdmi_choose_cvt(struct hda_codec *codec,
1320 int pin_idx, int *cvt_id, int *mux_id)
1321{
1322 struct hdmi_spec *spec = codec->spec;
1323 struct hdmi_spec_per_pin *per_pin;
1324 struct hdmi_spec_per_cvt *per_cvt = NULL;
1325 int cvt_idx, mux_idx = 0;
1326
1327 per_pin = get_pin(spec, pin_idx);
1328
1329 /* Dynamically assign converter to stream */
1330 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1331 per_cvt = get_cvt(spec, cvt_idx);
1332
1333 /* Must not already be assigned */
1334 if (per_cvt->assigned)
1335 continue;
1336 /* Must be in pin's mux's list of converters */
1337 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1338 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1339 break;
1340 /* Not in mux list */
1341 if (mux_idx == per_pin->num_mux_nids)
1342 continue;
1343 break;
1344 }
1345
1346 /* No free converters */
1347 if (cvt_idx == spec->num_cvts)
1348 return -ENODEV;
1349
1350 per_pin->mux_idx = mux_idx;
1351
1352 if (cvt_id)
1353 *cvt_id = cvt_idx;
1354 if (mux_id)
1355 *mux_id = mux_idx;
1356
1357 return 0;
1358}
1359
1360/* Assure the pin select the right convetor */
1361static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1362 struct hdmi_spec_per_pin *per_pin)
1363{
1364 hda_nid_t pin_nid = per_pin->pin_nid;
1365 int mux_idx, curr;
1366
1367 mux_idx = per_pin->mux_idx;
1368 curr = snd_hda_codec_read(codec, pin_nid, 0,
1369 AC_VERB_GET_CONNECT_SEL, 0);
1370 if (curr != mux_idx)
1371 snd_hda_codec_write_cache(codec, pin_nid, 0,
1372 AC_VERB_SET_CONNECT_SEL,
1373 mux_idx);
1374}
1375
1376/* Intel HDMI workaround to fix audio routing issue:
1377 * For some Intel display codecs, pins share the same connection list.
1378 * So a conveter can be selected by multiple pins and playback on any of these
1379 * pins will generate sound on the external display, because audio flows from
1380 * the same converter to the display pipeline. Also muting one pin may make
1381 * other pins have no sound output.
1382 * So this function assures that an assigned converter for a pin is not selected
1383 * by any other pins.
1384 */
1385static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1386 hda_nid_t pin_nid, int mux_idx)
1387{
1388 struct hdmi_spec *spec = codec->spec;
1389 hda_nid_t nid, end_nid;
1390 int cvt_idx, curr;
1391 struct hdmi_spec_per_cvt *per_cvt;
1392
1393 /* configure all pins, including "no physical connection" ones */
1394 end_nid = codec->start_nid + codec->num_nodes;
1395 for (nid = codec->start_nid; nid < end_nid; nid++) {
1396 unsigned int wid_caps = get_wcaps(codec, nid);
1397 unsigned int wid_type = get_wcaps_type(wid_caps);
1398
1399 if (wid_type != AC_WID_PIN)
1400 continue;
1401
1402 if (nid == pin_nid)
1403 continue;
1404
1405 curr = snd_hda_codec_read(codec, nid, 0,
1406 AC_VERB_GET_CONNECT_SEL, 0);
1407 if (curr != mux_idx)
1408 continue;
1409
1410 /* choose an unassigned converter. The conveters in the
1411 * connection list are in the same order as in the codec.
1412 */
1413 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1414 per_cvt = get_cvt(spec, cvt_idx);
1415 if (!per_cvt->assigned) {
1416 codec_dbg(codec,
1417 "choose cvt %d for pin nid %d\n",
1418 cvt_idx, nid);
1419 snd_hda_codec_write_cache(codec, nid, 0,
1420 AC_VERB_SET_CONNECT_SEL,
1421 cvt_idx);
1422 break;
1423 }
1424 }
1425 }
1426}
1427
1428/*
1429 * HDA PCM callbacks
1430 */
1431static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1432 struct hda_codec *codec,
1433 struct snd_pcm_substream *substream)
1434{
1435 struct hdmi_spec *spec = codec->spec;
1436 struct snd_pcm_runtime *runtime = substream->runtime;
1437 int pin_idx, cvt_idx, mux_idx = 0;
1438 struct hdmi_spec_per_pin *per_pin;
1439 struct hdmi_eld *eld;
1440 struct hdmi_spec_per_cvt *per_cvt = NULL;
1441 int err;
1442
1443 /* Validate hinfo */
1444 pin_idx = hinfo_to_pin_index(codec, hinfo);
1445 if (snd_BUG_ON(pin_idx < 0))
1446 return -EINVAL;
1447 per_pin = get_pin(spec, pin_idx);
1448 eld = &per_pin->sink_eld;
1449
1450 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1451 if (err < 0)
1452 return err;
1453
1454 per_cvt = get_cvt(spec, cvt_idx);
1455 /* Claim converter */
1456 per_cvt->assigned = 1;
1457 per_pin->cvt_nid = per_cvt->cvt_nid;
1458 hinfo->nid = per_cvt->cvt_nid;
1459
1460 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1461 AC_VERB_SET_CONNECT_SEL,
1462 mux_idx);
1463
1464 /* configure unused pins to choose other converters */
1465 if (is_haswell_plus(codec) || is_valleyview(codec))
1466 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1467
1468 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1469
1470 /* Initially set the converter's capabilities */
1471 hinfo->channels_min = per_cvt->channels_min;
1472 hinfo->channels_max = per_cvt->channels_max;
1473 hinfo->rates = per_cvt->rates;
1474 hinfo->formats = per_cvt->formats;
1475 hinfo->maxbps = per_cvt->maxbps;
1476
1477 /* Restrict capabilities by ELD if this isn't disabled */
1478 if (!static_hdmi_pcm && eld->eld_valid) {
1479 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1480 if (hinfo->channels_min > hinfo->channels_max ||
1481 !hinfo->rates || !hinfo->formats) {
1482 per_cvt->assigned = 0;
1483 hinfo->nid = 0;
1484 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1485 return -ENODEV;
1486 }
1487 }
1488
1489 /* Store the updated parameters */
1490 runtime->hw.channels_min = hinfo->channels_min;
1491 runtime->hw.channels_max = hinfo->channels_max;
1492 runtime->hw.formats = hinfo->formats;
1493 runtime->hw.rates = hinfo->rates;
1494
1495 snd_pcm_hw_constraint_step(substream->runtime, 0,
1496 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1497 return 0;
1498}
1499
1500/*
1501 * HDA/HDMI auto parsing
1502 */
1503static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1504{
1505 struct hdmi_spec *spec = codec->spec;
1506 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1507 hda_nid_t pin_nid = per_pin->pin_nid;
1508
1509 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1510 codec_warn(codec,
1511 "HDMI: pin %d wcaps %#x does not support connection list\n",
1512 pin_nid, get_wcaps(codec, pin_nid));
1513 return -EINVAL;
1514 }
1515
1516 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1517 per_pin->mux_nids,
1518 HDA_MAX_CONNECTIONS);
1519
1520 return 0;
1521}
1522
1523static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1524{
1525 struct hda_jack_tbl *jack;
1526 struct hda_codec *codec = per_pin->codec;
1527 struct hdmi_spec *spec = codec->spec;
1528 struct hdmi_eld *eld = &spec->temp_eld;
1529 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1530 hda_nid_t pin_nid = per_pin->pin_nid;
1531 /*
1532 * Always execute a GetPinSense verb here, even when called from
1533 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1534 * response's PD bit is not the real PD value, but indicates that
1535 * the real PD value changed. An older version of the HD-audio
1536 * specification worked this way. Hence, we just ignore the data in
1537 * the unsolicited response to avoid custom WARs.
1538 */
1539 int present;
1540 bool update_eld = false;
1541 bool eld_changed = false;
1542 bool ret;
1543
1544 snd_hda_power_up(codec);
1545 present = snd_hda_pin_sense(codec, pin_nid);
1546
1547 mutex_lock(&per_pin->lock);
1548 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1549 if (pin_eld->monitor_present)
1550 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1551 else
1552 eld->eld_valid = false;
1553
1554 codec_dbg(codec,
1555 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1556 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1557
1558 if (eld->eld_valid) {
1559 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1560 &eld->eld_size) < 0)
1561 eld->eld_valid = false;
1562 else {
1563 memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1564 if (snd_hdmi_parse_eld(&eld->info, eld->eld_buffer,
1565 eld->eld_size) < 0)
1566 eld->eld_valid = false;
1567 }
1568
1569 if (eld->eld_valid) {
1570 snd_hdmi_show_eld(&eld->info);
1571 update_eld = true;
1572 }
1573 else if (repoll) {
1574 queue_delayed_work(codec->bus->workq,
1575 &per_pin->work,
1576 msecs_to_jiffies(300));
1577 goto unlock;
1578 }
1579 }
1580
1581 if (pin_eld->eld_valid && !eld->eld_valid) {
1582 update_eld = true;
1583 eld_changed = true;
1584 }
1585 if (update_eld) {
1586 bool old_eld_valid = pin_eld->eld_valid;
1587 pin_eld->eld_valid = eld->eld_valid;
1588 eld_changed = pin_eld->eld_size != eld->eld_size ||
1589 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1590 eld->eld_size) != 0;
1591 if (eld_changed)
1592 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1593 eld->eld_size);
1594 pin_eld->eld_size = eld->eld_size;
1595 pin_eld->info = eld->info;
1596
1597 /*
1598 * Re-setup pin and infoframe. This is needed e.g. when
1599 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1600 * - transcoder can change during stream playback on Haswell
1601 */
1602 if (eld->eld_valid && !old_eld_valid && per_pin->setup)
1603 hdmi_setup_audio_infoframe(codec, per_pin,
1604 per_pin->non_pcm);
1605 }
1606
1607 if (eld_changed)
1608 snd_ctl_notify(codec->bus->card,
1609 SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1610 &per_pin->eld_ctl->id);
1611 unlock:
1612 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1613
1614 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1615 if (jack)
1616 jack->block_report = !ret;
1617
1618 mutex_unlock(&per_pin->lock);
1619 snd_hda_power_down(codec);
1620 return ret;
1621}
1622
1623static void hdmi_repoll_eld(struct work_struct *work)
1624{
1625 struct hdmi_spec_per_pin *per_pin =
1626 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1627
1628 if (per_pin->repoll_count++ > 6)
1629 per_pin->repoll_count = 0;
1630
1631 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1632 snd_hda_jack_report_sync(per_pin->codec);
1633}
1634
1635static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1636 hda_nid_t nid);
1637
1638static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1639{
1640 struct hdmi_spec *spec = codec->spec;
1641 unsigned int caps, config;
1642 int pin_idx;
1643 struct hdmi_spec_per_pin *per_pin;
1644 int err;
1645
1646 caps = snd_hda_query_pin_caps(codec, pin_nid);
1647 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1648 return 0;
1649
1650 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1651 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1652 return 0;
1653
1654 if (is_haswell_plus(codec))
1655 intel_haswell_fixup_connect_list(codec, pin_nid);
1656
1657 pin_idx = spec->num_pins;
1658 per_pin = snd_array_new(&spec->pins);
1659 if (!per_pin)
1660 return -ENOMEM;
1661
1662 per_pin->pin_nid = pin_nid;
1663 per_pin->non_pcm = false;
1664
1665 err = hdmi_read_pin_conn(codec, pin_idx);
1666 if (err < 0)
1667 return err;
1668
1669 spec->num_pins++;
1670
1671 return 0;
1672}
1673
1674static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1675{
1676 struct hdmi_spec *spec = codec->spec;
1677 struct hdmi_spec_per_cvt *per_cvt;
1678 unsigned int chans;
1679 int err;
1680
1681 chans = get_wcaps(codec, cvt_nid);
1682 chans = get_wcaps_channels(chans);
1683
1684 per_cvt = snd_array_new(&spec->cvts);
1685 if (!per_cvt)
1686 return -ENOMEM;
1687
1688 per_cvt->cvt_nid = cvt_nid;
1689 per_cvt->channels_min = 2;
1690 if (chans <= 16) {
1691 per_cvt->channels_max = chans;
1692 if (chans > spec->channels_max)
1693 spec->channels_max = chans;
1694 }
1695
1696 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1697 &per_cvt->rates,
1698 &per_cvt->formats,
1699 &per_cvt->maxbps);
1700 if (err < 0)
1701 return err;
1702
1703 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1704 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1705 spec->num_cvts++;
1706
1707 return 0;
1708}
1709
1710static int hdmi_parse_codec(struct hda_codec *codec)
1711{
1712 hda_nid_t nid;
1713 int i, nodes;
1714
1715 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1716 if (!nid || nodes < 0) {
1717 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1718 return -EINVAL;
1719 }
1720
1721 for (i = 0; i < nodes; i++, nid++) {
1722 unsigned int caps;
1723 unsigned int type;
1724
1725 caps = get_wcaps(codec, nid);
1726 type = get_wcaps_type(caps);
1727
1728 if (!(caps & AC_WCAP_DIGITAL))
1729 continue;
1730
1731 switch (type) {
1732 case AC_WID_AUD_OUT:
1733 hdmi_add_cvt(codec, nid);
1734 break;
1735 case AC_WID_PIN:
1736 hdmi_add_pin(codec, nid);
1737 break;
1738 }
1739 }
1740
1741 return 0;
1742}
1743
1744/*
1745 */
1746static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1747{
1748 struct hda_spdif_out *spdif;
1749 bool non_pcm;
1750
1751 mutex_lock(&codec->spdif_mutex);
1752 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1753 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1754 mutex_unlock(&codec->spdif_mutex);
1755 return non_pcm;
1756}
1757
1758
1759/*
1760 * HDMI callbacks
1761 */
1762
1763static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1764 struct hda_codec *codec,
1765 unsigned int stream_tag,
1766 unsigned int format,
1767 struct snd_pcm_substream *substream)
1768{
1769 hda_nid_t cvt_nid = hinfo->nid;
1770 struct hdmi_spec *spec = codec->spec;
1771 int pin_idx = hinfo_to_pin_index(codec, hinfo);
1772 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1773 hda_nid_t pin_nid = per_pin->pin_nid;
1774 bool non_pcm;
1775 int pinctl;
1776
1777 if (is_haswell_plus(codec) || is_valleyview(codec)) {
1778 /* Verify pin:cvt selections to avoid silent audio after S3.
1779 * After S3, the audio driver restores pin:cvt selections
1780 * but this can happen before gfx is ready and such selection
1781 * is overlooked by HW. Thus multiple pins can share a same
1782 * default convertor and mute control will affect each other,
1783 * which can cause a resumed audio playback become silent
1784 * after S3.
1785 */
1786 intel_verify_pin_cvt_connect(codec, per_pin);
1787 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1788 }
1789
1790 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1791 mutex_lock(&per_pin->lock);
1792 per_pin->channels = substream->runtime->channels;
1793 per_pin->setup = true;
1794
1795 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1796 mutex_unlock(&per_pin->lock);
1797
1798 if (spec->dyn_pin_out) {
1799 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1800 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1801 snd_hda_codec_write(codec, pin_nid, 0,
1802 AC_VERB_SET_PIN_WIDGET_CONTROL,
1803 pinctl | PIN_OUT);
1804 }
1805
1806 return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1807}
1808
1809static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1810 struct hda_codec *codec,
1811 struct snd_pcm_substream *substream)
1812{
1813 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1814 return 0;
1815}
1816
1817static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1818 struct hda_codec *codec,
1819 struct snd_pcm_substream *substream)
1820{
1821 struct hdmi_spec *spec = codec->spec;
1822 int cvt_idx, pin_idx;
1823 struct hdmi_spec_per_cvt *per_cvt;
1824 struct hdmi_spec_per_pin *per_pin;
1825 int pinctl;
1826
1827 if (hinfo->nid) {
1828 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1829 if (snd_BUG_ON(cvt_idx < 0))
1830 return -EINVAL;
1831 per_cvt = get_cvt(spec, cvt_idx);
1832
1833 snd_BUG_ON(!per_cvt->assigned);
1834 per_cvt->assigned = 0;
1835 hinfo->nid = 0;
1836
1837 pin_idx = hinfo_to_pin_index(codec, hinfo);
1838 if (snd_BUG_ON(pin_idx < 0))
1839 return -EINVAL;
1840 per_pin = get_pin(spec, pin_idx);
1841
1842 if (spec->dyn_pin_out) {
1843 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1844 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1845 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1846 AC_VERB_SET_PIN_WIDGET_CONTROL,
1847 pinctl & ~PIN_OUT);
1848 }
1849
1850 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1851
1852 mutex_lock(&per_pin->lock);
1853 per_pin->chmap_set = false;
1854 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1855
1856 per_pin->setup = false;
1857 per_pin->channels = 0;
1858 mutex_unlock(&per_pin->lock);
1859 }
1860
1861 return 0;
1862}
1863
1864static const struct hda_pcm_ops generic_ops = {
1865 .open = hdmi_pcm_open,
1866 .close = hdmi_pcm_close,
1867 .prepare = generic_hdmi_playback_pcm_prepare,
1868 .cleanup = generic_hdmi_playback_pcm_cleanup,
1869};
1870
1871/*
1872 * ALSA API channel-map control callbacks
1873 */
1874static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1875 struct snd_ctl_elem_info *uinfo)
1876{
1877 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1878 struct hda_codec *codec = info->private_data;
1879 struct hdmi_spec *spec = codec->spec;
1880 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1881 uinfo->count = spec->channels_max;
1882 uinfo->value.integer.min = 0;
1883 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1884 return 0;
1885}
1886
1887static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1888 int channels)
1889{
1890 /* If the speaker allocation matches the channel count, it is OK.*/
1891 if (cap->channels != channels)
1892 return -1;
1893
1894 /* all channels are remappable freely */
1895 return SNDRV_CTL_TLVT_CHMAP_VAR;
1896}
1897
1898static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1899 unsigned int *chmap, int channels)
1900{
1901 int count = 0;
1902 int c;
1903
1904 for (c = 7; c >= 0; c--) {
1905 int spk = cap->speakers[c];
1906 if (!spk)
1907 continue;
1908
1909 chmap[count++] = spk_to_chmap(spk);
1910 }
1911
1912 WARN_ON(count != channels);
1913}
1914
1915static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1916 unsigned int size, unsigned int __user *tlv)
1917{
1918 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1919 struct hda_codec *codec = info->private_data;
1920 struct hdmi_spec *spec = codec->spec;
1921 unsigned int __user *dst;
1922 int chs, count = 0;
1923
1924 if (size < 8)
1925 return -ENOMEM;
1926 if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1927 return -EFAULT;
1928 size -= 8;
1929 dst = tlv + 2;
1930 for (chs = 2; chs <= spec->channels_max; chs++) {
1931 int i;
1932 struct cea_channel_speaker_allocation *cap;
1933 cap = channel_allocations;
1934 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1935 int chs_bytes = chs * 4;
1936 int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1937 unsigned int tlv_chmap[8];
1938
1939 if (type < 0)
1940 continue;
1941 if (size < 8)
1942 return -ENOMEM;
1943 if (put_user(type, dst) ||
1944 put_user(chs_bytes, dst + 1))
1945 return -EFAULT;
1946 dst += 2;
1947 size -= 8;
1948 count += 8;
1949 if (size < chs_bytes)
1950 return -ENOMEM;
1951 size -= chs_bytes;
1952 count += chs_bytes;
1953 spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1954 if (copy_to_user(dst, tlv_chmap, chs_bytes))
1955 return -EFAULT;
1956 dst += chs;
1957 }
1958 }
1959 if (put_user(count, tlv + 1))
1960 return -EFAULT;
1961 return 0;
1962}
1963
1964static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1965 struct snd_ctl_elem_value *ucontrol)
1966{
1967 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1968 struct hda_codec *codec = info->private_data;
1969 struct hdmi_spec *spec = codec->spec;
1970 int pin_idx = kcontrol->private_value;
1971 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1972 int i;
1973
1974 for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1975 ucontrol->value.integer.value[i] = per_pin->chmap[i];
1976 return 0;
1977}
1978
1979static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1980 struct snd_ctl_elem_value *ucontrol)
1981{
1982 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1983 struct hda_codec *codec = info->private_data;
1984 struct hdmi_spec *spec = codec->spec;
1985 int pin_idx = kcontrol->private_value;
1986 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1987 unsigned int ctl_idx;
1988 struct snd_pcm_substream *substream;
1989 unsigned char chmap[8];
1990 int i, err, ca, prepared = 0;
1991
1992 ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
1993 substream = snd_pcm_chmap_substream(info, ctl_idx);
1994 if (!substream || !substream->runtime)
1995 return 0; /* just for avoiding error from alsactl restore */
1996 switch (substream->runtime->status->state) {
1997 case SNDRV_PCM_STATE_OPEN:
1998 case SNDRV_PCM_STATE_SETUP:
1999 break;
2000 case SNDRV_PCM_STATE_PREPARED:
2001 prepared = 1;
2002 break;
2003 default:
2004 return -EBUSY;
2005 }
2006 memset(chmap, 0, sizeof(chmap));
2007 for (i = 0; i < ARRAY_SIZE(chmap); i++)
2008 chmap[i] = ucontrol->value.integer.value[i];
2009 if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2010 return 0;
2011 ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2012 if (ca < 0)
2013 return -EINVAL;
2014 if (spec->ops.chmap_validate) {
2015 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2016 if (err)
2017 return err;
2018 }
2019 mutex_lock(&per_pin->lock);
2020 per_pin->chmap_set = true;
2021 memcpy(per_pin->chmap, chmap, sizeof(chmap));
2022 if (prepared)
2023 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2024 mutex_unlock(&per_pin->lock);
2025
2026 return 0;
2027}
2028
2029static int generic_hdmi_build_pcms(struct hda_codec *codec)
2030{
2031 struct hdmi_spec *spec = codec->spec;
2032 int pin_idx;
2033
2034 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2035 struct hda_pcm *info;
2036 struct hda_pcm_stream *pstr;
2037 struct hdmi_spec_per_pin *per_pin;
2038
2039 per_pin = get_pin(spec, pin_idx);
2040 sprintf(per_pin->pcm_name, "HDMI %d", pin_idx);
2041 info = snd_array_new(&spec->pcm_rec);
2042 if (!info)
2043 return -ENOMEM;
2044 info->name = per_pin->pcm_name;
2045 info->pcm_type = HDA_PCM_TYPE_HDMI;
2046 info->own_chmap = true;
2047
2048 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2049 pstr->substreams = 1;
2050 pstr->ops = generic_ops;
2051 /* other pstr fields are set in open */
2052 }
2053
2054 codec->num_pcms = spec->num_pins;
2055 codec->pcm_info = spec->pcm_rec.list;
2056
2057 return 0;
2058}
2059
2060static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2061{
2062 char hdmi_str[32] = "HDMI/DP";
2063 struct hdmi_spec *spec = codec->spec;
2064 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2065 int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2066
2067 if (pcmdev > 0)
2068 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2069 if (!is_jack_detectable(codec, per_pin->pin_nid))
2070 strncat(hdmi_str, " Phantom",
2071 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2072
2073 return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
2074}
2075
2076static int generic_hdmi_build_controls(struct hda_codec *codec)
2077{
2078 struct hdmi_spec *spec = codec->spec;
2079 int err;
2080 int pin_idx;
2081
2082 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2083 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2084
2085 err = generic_hdmi_build_jack(codec, pin_idx);
2086 if (err < 0)
2087 return err;
2088
2089 err = snd_hda_create_dig_out_ctls(codec,
2090 per_pin->pin_nid,
2091 per_pin->mux_nids[0],
2092 HDA_PCM_TYPE_HDMI);
2093 if (err < 0)
2094 return err;
2095 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2096
2097 /* add control for ELD Bytes */
2098 err = hdmi_create_eld_ctl(codec, pin_idx,
2099 get_pcm_rec(spec, pin_idx)->device);
2100
2101 if (err < 0)
2102 return err;
2103
2104 hdmi_present_sense(per_pin, 0);
2105 }
2106
2107 /* add channel maps */
2108 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2109 struct snd_pcm_chmap *chmap;
2110 struct snd_kcontrol *kctl;
2111 int i;
2112
2113 if (!codec->pcm_info[pin_idx].pcm)
2114 break;
2115 err = snd_pcm_add_chmap_ctls(codec->pcm_info[pin_idx].pcm,
2116 SNDRV_PCM_STREAM_PLAYBACK,
2117 NULL, 0, pin_idx, &chmap);
2118 if (err < 0)
2119 return err;
2120 /* override handlers */
2121 chmap->private_data = codec;
2122 kctl = chmap->kctl;
2123 for (i = 0; i < kctl->count; i++)
2124 kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2125 kctl->info = hdmi_chmap_ctl_info;
2126 kctl->get = hdmi_chmap_ctl_get;
2127 kctl->put = hdmi_chmap_ctl_put;
2128 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2129 }
2130
2131 return 0;
2132}
2133
2134static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2135{
2136 struct hdmi_spec *spec = codec->spec;
2137 int pin_idx;
2138
2139 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2140 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2141
2142 per_pin->codec = codec;
2143 mutex_init(&per_pin->lock);
2144 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2145 eld_proc_new(per_pin, pin_idx);
2146 }
2147 return 0;
2148}
2149
2150static int generic_hdmi_init(struct hda_codec *codec)
2151{
2152 struct hdmi_spec *spec = codec->spec;
2153 int pin_idx;
2154
2155 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2156 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2157 hda_nid_t pin_nid = per_pin->pin_nid;
2158
2159 hdmi_init_pin(codec, pin_nid);
2160 snd_hda_jack_detect_enable_callback(codec, pin_nid, pin_nid,
2161 codec->jackpoll_interval > 0 ? jack_callback : NULL);
2162 }
2163 return 0;
2164}
2165
2166static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2167{
2168 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2169 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2170 snd_array_init(&spec->pcm_rec, sizeof(struct hda_pcm), nums);
2171}
2172
2173static void hdmi_array_free(struct hdmi_spec *spec)
2174{
2175 snd_array_free(&spec->pins);
2176 snd_array_free(&spec->cvts);
2177 snd_array_free(&spec->pcm_rec);
2178}
2179
2180static void generic_hdmi_free(struct hda_codec *codec)
2181{
2182 struct hdmi_spec *spec = codec->spec;
2183 int pin_idx;
2184
2185 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2186 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2187
2188 cancel_delayed_work(&per_pin->work);
2189 eld_proc_free(per_pin);
2190 }
2191
2192 flush_workqueue(codec->bus->workq);
2193 hdmi_array_free(spec);
2194 kfree(spec);
2195}
2196
2197#ifdef CONFIG_PM
2198static int generic_hdmi_resume(struct hda_codec *codec)
2199{
2200 struct hdmi_spec *spec = codec->spec;
2201 int pin_idx;
2202
2203 generic_hdmi_init(codec);
2204 snd_hda_codec_resume_amp(codec);
2205 snd_hda_codec_resume_cache(codec);
2206
2207 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2208 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2209 hdmi_present_sense(per_pin, 1);
2210 }
2211 return 0;
2212}
2213#endif
2214
2215static const struct hda_codec_ops generic_hdmi_patch_ops = {
2216 .init = generic_hdmi_init,
2217 .free = generic_hdmi_free,
2218 .build_pcms = generic_hdmi_build_pcms,
2219 .build_controls = generic_hdmi_build_controls,
2220 .unsol_event = hdmi_unsol_event,
2221#ifdef CONFIG_PM
2222 .resume = generic_hdmi_resume,
2223#endif
2224};
2225
2226static const struct hdmi_ops generic_standard_hdmi_ops = {
2227 .pin_get_eld = snd_hdmi_get_eld,
2228 .pin_get_slot_channel = hdmi_pin_get_slot_channel,
2229 .pin_set_slot_channel = hdmi_pin_set_slot_channel,
2230 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2231 .pin_hbr_setup = hdmi_pin_hbr_setup,
2232 .setup_stream = hdmi_setup_stream,
2233 .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
2234 .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
2235};
2236
2237
2238static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2239 hda_nid_t nid)
2240{
2241 struct hdmi_spec *spec = codec->spec;
2242 hda_nid_t conns[4];
2243 int nconns;
2244
2245 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2246 if (nconns == spec->num_cvts &&
2247 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2248 return;
2249
2250 /* override pins connection list */
2251 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2252 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2253}
2254
2255#define INTEL_VENDOR_NID 0x08
2256#define INTEL_GET_VENDOR_VERB 0xf81
2257#define INTEL_SET_VENDOR_VERB 0x781
2258#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2259#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2260
2261static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2262 bool update_tree)
2263{
2264 unsigned int vendor_param;
2265
2266 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2267 INTEL_GET_VENDOR_VERB, 0);
2268 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2269 return;
2270
2271 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2272 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2273 INTEL_SET_VENDOR_VERB, vendor_param);
2274 if (vendor_param == -1)
2275 return;
2276
2277 if (update_tree)
2278 snd_hda_codec_update_widgets(codec);
2279}
2280
2281static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2282{
2283 unsigned int vendor_param;
2284
2285 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2286 INTEL_GET_VENDOR_VERB, 0);
2287 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2288 return;
2289
2290 /* enable DP1.2 mode */
2291 vendor_param |= INTEL_EN_DP12;
2292 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2293 INTEL_SET_VENDOR_VERB, vendor_param);
2294}
2295
2296/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2297 * Otherwise you may get severe h/w communication errors.
2298 */
2299static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2300 unsigned int power_state)
2301{
2302 if (power_state == AC_PWRST_D0) {
2303 intel_haswell_enable_all_pins(codec, false);
2304 intel_haswell_fixup_enable_dp12(codec);
2305 }
2306
2307 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2308 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2309}
2310
2311static int patch_generic_hdmi(struct hda_codec *codec)
2312{
2313 struct hdmi_spec *spec;
2314
2315 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2316 if (spec == NULL)
2317 return -ENOMEM;
2318
2319 spec->ops = generic_standard_hdmi_ops;
2320 codec->spec = spec;
2321 hdmi_array_init(spec, 4);
2322
2323 if (is_haswell_plus(codec)) {
2324 intel_haswell_enable_all_pins(codec, true);
2325 intel_haswell_fixup_enable_dp12(codec);
2326 }
2327
2328 if (is_haswell(codec) || is_valleyview(codec)) {
2329 codec->depop_delay = 0;
2330 }
2331
2332 if (hdmi_parse_codec(codec) < 0) {
2333 codec->spec = NULL;
2334 kfree(spec);
2335 return -EINVAL;
2336 }
2337 codec->patch_ops = generic_hdmi_patch_ops;
2338 if (is_haswell_plus(codec)) {
2339 codec->patch_ops.set_power_state = haswell_set_power_state;
2340 codec->dp_mst = true;
2341 }
2342
2343 generic_hdmi_init_per_pins(codec);
2344
2345 init_channel_allocations();
2346
2347 return 0;
2348}
2349
2350/*
2351 * Shared non-generic implementations
2352 */
2353
2354static int simple_playback_build_pcms(struct hda_codec *codec)
2355{
2356 struct hdmi_spec *spec = codec->spec;
2357 struct hda_pcm *info;
2358 unsigned int chans;
2359 struct hda_pcm_stream *pstr;
2360 struct hdmi_spec_per_cvt *per_cvt;
2361
2362 per_cvt = get_cvt(spec, 0);
2363 chans = get_wcaps(codec, per_cvt->cvt_nid);
2364 chans = get_wcaps_channels(chans);
2365
2366 info = snd_array_new(&spec->pcm_rec);
2367 if (!info)
2368 return -ENOMEM;
2369 info->name = get_pin(spec, 0)->pcm_name;
2370 sprintf(info->name, "HDMI 0");
2371 info->pcm_type = HDA_PCM_TYPE_HDMI;
2372 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2373 *pstr = spec->pcm_playback;
2374 pstr->nid = per_cvt->cvt_nid;
2375 if (pstr->channels_max <= 2 && chans && chans <= 16)
2376 pstr->channels_max = chans;
2377
2378 codec->num_pcms = 1;
2379 codec->pcm_info = info;
2380
2381 return 0;
2382}
2383
2384/* unsolicited event for jack sensing */
2385static void simple_hdmi_unsol_event(struct hda_codec *codec,
2386 unsigned int res)
2387{
2388 snd_hda_jack_set_dirty_all(codec);
2389 snd_hda_jack_report_sync(codec);
2390}
2391
2392/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2393 * as long as spec->pins[] is set correctly
2394 */
2395#define simple_hdmi_build_jack generic_hdmi_build_jack
2396
2397static int simple_playback_build_controls(struct hda_codec *codec)
2398{
2399 struct hdmi_spec *spec = codec->spec;
2400 struct hdmi_spec_per_cvt *per_cvt;
2401 int err;
2402
2403 per_cvt = get_cvt(spec, 0);
2404 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2405 per_cvt->cvt_nid,
2406 HDA_PCM_TYPE_HDMI);
2407 if (err < 0)
2408 return err;
2409 return simple_hdmi_build_jack(codec, 0);
2410}
2411
2412static int simple_playback_init(struct hda_codec *codec)
2413{
2414 struct hdmi_spec *spec = codec->spec;
2415 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2416 hda_nid_t pin = per_pin->pin_nid;
2417
2418 snd_hda_codec_write(codec, pin, 0,
2419 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2420 /* some codecs require to unmute the pin */
2421 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2422 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2423 AMP_OUT_UNMUTE);
2424 snd_hda_jack_detect_enable(codec, pin, pin);
2425 return 0;
2426}
2427
2428static void simple_playback_free(struct hda_codec *codec)
2429{
2430 struct hdmi_spec *spec = codec->spec;
2431
2432 hdmi_array_free(spec);
2433 kfree(spec);
2434}
2435
2436/*
2437 * Nvidia specific implementations
2438 */
2439
2440#define Nv_VERB_SET_Channel_Allocation 0xF79
2441#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2442#define Nv_VERB_SET_Audio_Protection_On 0xF98
2443#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2444
2445#define nvhdmi_master_con_nid_7x 0x04
2446#define nvhdmi_master_pin_nid_7x 0x05
2447
2448static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2449 /*front, rear, clfe, rear_surr */
2450 0x6, 0x8, 0xa, 0xc,
2451};
2452
2453static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2454 /* set audio protect on */
2455 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2456 /* enable digital output on pin widget */
2457 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2458 {} /* terminator */
2459};
2460
2461static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2462 /* set audio protect on */
2463 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2464 /* enable digital output on pin widget */
2465 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2466 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2467 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2468 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2469 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2470 {} /* terminator */
2471};
2472
2473#ifdef LIMITED_RATE_FMT_SUPPORT
2474/* support only the safe format and rate */
2475#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2476#define SUPPORTED_MAXBPS 16
2477#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2478#else
2479/* support all rates and formats */
2480#define SUPPORTED_RATES \
2481 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2482 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2483 SNDRV_PCM_RATE_192000)
2484#define SUPPORTED_MAXBPS 24
2485#define SUPPORTED_FORMATS \
2486 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2487#endif
2488
2489static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2490{
2491 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2492 return 0;
2493}
2494
2495static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2496{
2497 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2498 return 0;
2499}
2500
2501static unsigned int channels_2_6_8[] = {
2502 2, 6, 8
2503};
2504
2505static unsigned int channels_2_8[] = {
2506 2, 8
2507};
2508
2509static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2510 .count = ARRAY_SIZE(channels_2_6_8),
2511 .list = channels_2_6_8,
2512 .mask = 0,
2513};
2514
2515static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2516 .count = ARRAY_SIZE(channels_2_8),
2517 .list = channels_2_8,
2518 .mask = 0,
2519};
2520
2521static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2522 struct hda_codec *codec,
2523 struct snd_pcm_substream *substream)
2524{
2525 struct hdmi_spec *spec = codec->spec;
2526 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2527
2528 switch (codec->preset->id) {
2529 case 0x10de0002:
2530 case 0x10de0003:
2531 case 0x10de0005:
2532 case 0x10de0006:
2533 hw_constraints_channels = &hw_constraints_2_8_channels;
2534 break;
2535 case 0x10de0007:
2536 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2537 break;
2538 default:
2539 break;
2540 }
2541
2542 if (hw_constraints_channels != NULL) {
2543 snd_pcm_hw_constraint_list(substream->runtime, 0,
2544 SNDRV_PCM_HW_PARAM_CHANNELS,
2545 hw_constraints_channels);
2546 } else {
2547 snd_pcm_hw_constraint_step(substream->runtime, 0,
2548 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2549 }
2550
2551 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2552}
2553
2554static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2555 struct hda_codec *codec,
2556 struct snd_pcm_substream *substream)
2557{
2558 struct hdmi_spec *spec = codec->spec;
2559 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2560}
2561
2562static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2563 struct hda_codec *codec,
2564 unsigned int stream_tag,
2565 unsigned int format,
2566 struct snd_pcm_substream *substream)
2567{
2568 struct hdmi_spec *spec = codec->spec;
2569 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2570 stream_tag, format, substream);
2571}
2572
2573static const struct hda_pcm_stream simple_pcm_playback = {
2574 .substreams = 1,
2575 .channels_min = 2,
2576 .channels_max = 2,
2577 .ops = {
2578 .open = simple_playback_pcm_open,
2579 .close = simple_playback_pcm_close,
2580 .prepare = simple_playback_pcm_prepare
2581 },
2582};
2583
2584static const struct hda_codec_ops simple_hdmi_patch_ops = {
2585 .build_controls = simple_playback_build_controls,
2586 .build_pcms = simple_playback_build_pcms,
2587 .init = simple_playback_init,
2588 .free = simple_playback_free,
2589 .unsol_event = simple_hdmi_unsol_event,
2590};
2591
2592static int patch_simple_hdmi(struct hda_codec *codec,
2593 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2594{
2595 struct hdmi_spec *spec;
2596 struct hdmi_spec_per_cvt *per_cvt;
2597 struct hdmi_spec_per_pin *per_pin;
2598
2599 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2600 if (!spec)
2601 return -ENOMEM;
2602
2603 codec->spec = spec;
2604 hdmi_array_init(spec, 1);
2605
2606 spec->multiout.num_dacs = 0; /* no analog */
2607 spec->multiout.max_channels = 2;
2608 spec->multiout.dig_out_nid = cvt_nid;
2609 spec->num_cvts = 1;
2610 spec->num_pins = 1;
2611 per_pin = snd_array_new(&spec->pins);
2612 per_cvt = snd_array_new(&spec->cvts);
2613 if (!per_pin || !per_cvt) {
2614 simple_playback_free(codec);
2615 return -ENOMEM;
2616 }
2617 per_cvt->cvt_nid = cvt_nid;
2618 per_pin->pin_nid = pin_nid;
2619 spec->pcm_playback = simple_pcm_playback;
2620
2621 codec->patch_ops = simple_hdmi_patch_ops;
2622
2623 return 0;
2624}
2625
2626static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2627 int channels)
2628{
2629 unsigned int chanmask;
2630 int chan = channels ? (channels - 1) : 1;
2631
2632 switch (channels) {
2633 default:
2634 case 0:
2635 case 2:
2636 chanmask = 0x00;
2637 break;
2638 case 4:
2639 chanmask = 0x08;
2640 break;
2641 case 6:
2642 chanmask = 0x0b;
2643 break;
2644 case 8:
2645 chanmask = 0x13;
2646 break;
2647 }
2648
2649 /* Set the audio infoframe channel allocation and checksum fields. The
2650 * channel count is computed implicitly by the hardware. */
2651 snd_hda_codec_write(codec, 0x1, 0,
2652 Nv_VERB_SET_Channel_Allocation, chanmask);
2653
2654 snd_hda_codec_write(codec, 0x1, 0,
2655 Nv_VERB_SET_Info_Frame_Checksum,
2656 (0x71 - chan - chanmask));
2657}
2658
2659static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2660 struct hda_codec *codec,
2661 struct snd_pcm_substream *substream)
2662{
2663 struct hdmi_spec *spec = codec->spec;
2664 int i;
2665
2666 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2667 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2668 for (i = 0; i < 4; i++) {
2669 /* set the stream id */
2670 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2671 AC_VERB_SET_CHANNEL_STREAMID, 0);
2672 /* set the stream format */
2673 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2674 AC_VERB_SET_STREAM_FORMAT, 0);
2675 }
2676
2677 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2678 * streams are disabled. */
2679 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2680
2681 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2682}
2683
2684static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2685 struct hda_codec *codec,
2686 unsigned int stream_tag,
2687 unsigned int format,
2688 struct snd_pcm_substream *substream)
2689{
2690 int chs;
2691 unsigned int dataDCC2, channel_id;
2692 int i;
2693 struct hdmi_spec *spec = codec->spec;
2694 struct hda_spdif_out *spdif;
2695 struct hdmi_spec_per_cvt *per_cvt;
2696
2697 mutex_lock(&codec->spdif_mutex);
2698 per_cvt = get_cvt(spec, 0);
2699 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2700
2701 chs = substream->runtime->channels;
2702
2703 dataDCC2 = 0x2;
2704
2705 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2706 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2707 snd_hda_codec_write(codec,
2708 nvhdmi_master_con_nid_7x,
2709 0,
2710 AC_VERB_SET_DIGI_CONVERT_1,
2711 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2712
2713 /* set the stream id */
2714 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2715 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2716
2717 /* set the stream format */
2718 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2719 AC_VERB_SET_STREAM_FORMAT, format);
2720
2721 /* turn on again (if needed) */
2722 /* enable and set the channel status audio/data flag */
2723 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2724 snd_hda_codec_write(codec,
2725 nvhdmi_master_con_nid_7x,
2726 0,
2727 AC_VERB_SET_DIGI_CONVERT_1,
2728 spdif->ctls & 0xff);
2729 snd_hda_codec_write(codec,
2730 nvhdmi_master_con_nid_7x,
2731 0,
2732 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2733 }
2734
2735 for (i = 0; i < 4; i++) {
2736 if (chs == 2)
2737 channel_id = 0;
2738 else
2739 channel_id = i * 2;
2740
2741 /* turn off SPDIF once;
2742 *otherwise the IEC958 bits won't be updated
2743 */
2744 if (codec->spdif_status_reset &&
2745 (spdif->ctls & AC_DIG1_ENABLE))
2746 snd_hda_codec_write(codec,
2747 nvhdmi_con_nids_7x[i],
2748 0,
2749 AC_VERB_SET_DIGI_CONVERT_1,
2750 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2751 /* set the stream id */
2752 snd_hda_codec_write(codec,
2753 nvhdmi_con_nids_7x[i],
2754 0,
2755 AC_VERB_SET_CHANNEL_STREAMID,
2756 (stream_tag << 4) | channel_id);
2757 /* set the stream format */
2758 snd_hda_codec_write(codec,
2759 nvhdmi_con_nids_7x[i],
2760 0,
2761 AC_VERB_SET_STREAM_FORMAT,
2762 format);
2763 /* turn on again (if needed) */
2764 /* enable and set the channel status audio/data flag */
2765 if (codec->spdif_status_reset &&
2766 (spdif->ctls & AC_DIG1_ENABLE)) {
2767 snd_hda_codec_write(codec,
2768 nvhdmi_con_nids_7x[i],
2769 0,
2770 AC_VERB_SET_DIGI_CONVERT_1,
2771 spdif->ctls & 0xff);
2772 snd_hda_codec_write(codec,
2773 nvhdmi_con_nids_7x[i],
2774 0,
2775 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2776 }
2777 }
2778
2779 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2780
2781 mutex_unlock(&codec->spdif_mutex);
2782 return 0;
2783}
2784
2785static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2786 .substreams = 1,
2787 .channels_min = 2,
2788 .channels_max = 8,
2789 .nid = nvhdmi_master_con_nid_7x,
2790 .rates = SUPPORTED_RATES,
2791 .maxbps = SUPPORTED_MAXBPS,
2792 .formats = SUPPORTED_FORMATS,
2793 .ops = {
2794 .open = simple_playback_pcm_open,
2795 .close = nvhdmi_8ch_7x_pcm_close,
2796 .prepare = nvhdmi_8ch_7x_pcm_prepare
2797 },
2798};
2799
2800static int patch_nvhdmi_2ch(struct hda_codec *codec)
2801{
2802 struct hdmi_spec *spec;
2803 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2804 nvhdmi_master_pin_nid_7x);
2805 if (err < 0)
2806 return err;
2807
2808 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2809 /* override the PCM rates, etc, as the codec doesn't give full list */
2810 spec = codec->spec;
2811 spec->pcm_playback.rates = SUPPORTED_RATES;
2812 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2813 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2814 return 0;
2815}
2816
2817static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2818{
2819 struct hdmi_spec *spec = codec->spec;
2820 int err = simple_playback_build_pcms(codec);
2821 if (!err) {
2822 struct hda_pcm *info = get_pcm_rec(spec, 0);
2823 info->own_chmap = true;
2824 }
2825 return err;
2826}
2827
2828static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2829{
2830 struct hdmi_spec *spec = codec->spec;
2831 struct hda_pcm *info;
2832 struct snd_pcm_chmap *chmap;
2833 int err;
2834
2835 err = simple_playback_build_controls(codec);
2836 if (err < 0)
2837 return err;
2838
2839 /* add channel maps */
2840 info = get_pcm_rec(spec, 0);
2841 err = snd_pcm_add_chmap_ctls(info->pcm,
2842 SNDRV_PCM_STREAM_PLAYBACK,
2843 snd_pcm_alt_chmaps, 8, 0, &chmap);
2844 if (err < 0)
2845 return err;
2846 switch (codec->preset->id) {
2847 case 0x10de0002:
2848 case 0x10de0003:
2849 case 0x10de0005:
2850 case 0x10de0006:
2851 chmap->channel_mask = (1U << 2) | (1U << 8);
2852 break;
2853 case 0x10de0007:
2854 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2855 }
2856 return 0;
2857}
2858
2859static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2860{
2861 struct hdmi_spec *spec;
2862 int err = patch_nvhdmi_2ch(codec);
2863 if (err < 0)
2864 return err;
2865 spec = codec->spec;
2866 spec->multiout.max_channels = 8;
2867 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2868 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2869 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2870 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2871
2872 /* Initialize the audio infoframe channel mask and checksum to something
2873 * valid */
2874 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2875
2876 return 0;
2877}
2878
2879/*
2880 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2881 * - 0x10de0015
2882 * - 0x10de0040
2883 */
2884static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2885 int channels)
2886{
2887 if (cap->ca_index == 0x00 && channels == 2)
2888 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2889
2890 return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2891}
2892
2893static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2894{
2895 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2896 return -EINVAL;
2897
2898 return 0;
2899}
2900
2901static int patch_nvhdmi(struct hda_codec *codec)
2902{
2903 struct hdmi_spec *spec;
2904 int err;
2905
2906 err = patch_generic_hdmi(codec);
2907 if (err)
2908 return err;
2909
2910 spec = codec->spec;
2911 spec->dyn_pin_out = true;
2912
2913 spec->ops.chmap_cea_alloc_validate_get_type =
2914 nvhdmi_chmap_cea_alloc_validate_get_type;
2915 spec->ops.chmap_validate = nvhdmi_chmap_validate;
2916
2917 return 0;
2918}
2919
2920/*
2921 * ATI/AMD-specific implementations
2922 */
2923
2924#define is_amdhdmi_rev3_or_later(codec) \
2925 ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300)
2926#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
2927
2928/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
2929#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
2930#define ATI_VERB_SET_DOWNMIX_INFO 0x772
2931#define ATI_VERB_SET_MULTICHANNEL_01 0x777
2932#define ATI_VERB_SET_MULTICHANNEL_23 0x778
2933#define ATI_VERB_SET_MULTICHANNEL_45 0x779
2934#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
2935#define ATI_VERB_SET_HBR_CONTROL 0x77c
2936#define ATI_VERB_SET_MULTICHANNEL_1 0x785
2937#define ATI_VERB_SET_MULTICHANNEL_3 0x786
2938#define ATI_VERB_SET_MULTICHANNEL_5 0x787
2939#define ATI_VERB_SET_MULTICHANNEL_7 0x788
2940#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
2941#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
2942#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
2943#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
2944#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
2945#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
2946#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
2947#define ATI_VERB_GET_HBR_CONTROL 0xf7c
2948#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
2949#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
2950#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
2951#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
2952#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
2953
2954/* AMD specific HDA cvt verbs */
2955#define ATI_VERB_SET_RAMP_RATE 0x770
2956#define ATI_VERB_GET_RAMP_RATE 0xf70
2957
2958#define ATI_OUT_ENABLE 0x1
2959
2960#define ATI_MULTICHANNEL_MODE_PAIRED 0
2961#define ATI_MULTICHANNEL_MODE_SINGLE 1
2962
2963#define ATI_HBR_CAPABLE 0x01
2964#define ATI_HBR_ENABLE 0x10
2965
2966static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
2967 unsigned char *buf, int *eld_size)
2968{
2969 /* call hda_eld.c ATI/AMD-specific function */
2970 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
2971 is_amdhdmi_rev3_or_later(codec));
2972}
2973
2974static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
2975 int active_channels, int conn_type)
2976{
2977 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
2978}
2979
2980static int atihdmi_paired_swap_fc_lfe(int pos)
2981{
2982 /*
2983 * ATI/AMD have automatic FC/LFE swap built-in
2984 * when in pairwise mapping mode.
2985 */
2986
2987 switch (pos) {
2988 /* see channel_allocations[].speakers[] */
2989 case 2: return 3;
2990 case 3: return 2;
2991 default: break;
2992 }
2993
2994 return pos;
2995}
2996
2997static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
2998{
2999 struct cea_channel_speaker_allocation *cap;
3000 int i, j;
3001
3002 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3003
3004 cap = &channel_allocations[get_channel_allocation_order(ca)];
3005 for (i = 0; i < chs; ++i) {
3006 int mask = to_spk_mask(map[i]);
3007 bool ok = false;
3008 bool companion_ok = false;
3009
3010 if (!mask)
3011 continue;
3012
3013 for (j = 0 + i % 2; j < 8; j += 2) {
3014 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3015 if (cap->speakers[chan_idx] == mask) {
3016 /* channel is in a supported position */
3017 ok = true;
3018
3019 if (i % 2 == 0 && i + 1 < chs) {
3020 /* even channel, check the odd companion */
3021 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3022 int comp_mask_req = to_spk_mask(map[i+1]);
3023 int comp_mask_act = cap->speakers[comp_chan_idx];
3024
3025 if (comp_mask_req == comp_mask_act)
3026 companion_ok = true;
3027 else
3028 return -EINVAL;
3029 }
3030 break;
3031 }
3032 }
3033
3034 if (!ok)
3035 return -EINVAL;
3036
3037 if (companion_ok)
3038 i++; /* companion channel already checked */
3039 }
3040
3041 return 0;
3042}
3043
3044static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3045 int hdmi_slot, int stream_channel)
3046{
3047 int verb;
3048 int ati_channel_setup = 0;
3049
3050 if (hdmi_slot > 7)
3051 return -EINVAL;
3052
3053 if (!has_amd_full_remap_support(codec)) {
3054 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3055
3056 /* In case this is an odd slot but without stream channel, do not
3057 * disable the slot since the corresponding even slot could have a
3058 * channel. In case neither have a channel, the slot pair will be
3059 * disabled when this function is called for the even slot. */
3060 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3061 return 0;
3062
3063 hdmi_slot -= hdmi_slot % 2;
3064
3065 if (stream_channel != 0xf)
3066 stream_channel -= stream_channel % 2;
3067 }
3068
3069 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3070
3071 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3072
3073 if (stream_channel != 0xf)
3074 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3075
3076 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3077}
3078
3079static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3080 int asp_slot)
3081{
3082 bool was_odd = false;
3083 int ati_asp_slot = asp_slot;
3084 int verb;
3085 int ati_channel_setup;
3086
3087 if (asp_slot > 7)
3088 return -EINVAL;
3089
3090 if (!has_amd_full_remap_support(codec)) {
3091 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3092 if (ati_asp_slot % 2 != 0) {
3093 ati_asp_slot -= 1;
3094 was_odd = true;
3095 }
3096 }
3097
3098 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3099
3100 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3101
3102 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3103 return 0xf;
3104
3105 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3106}
3107
3108static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3109 int channels)
3110{
3111 int c;
3112
3113 /*
3114 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3115 * we need to take that into account (a single channel may take 2
3116 * channel slots if we need to carry a silent channel next to it).
3117 * On Rev3+ AMD codecs this function is not used.
3118 */
3119 int chanpairs = 0;
3120
3121 /* We only produce even-numbered channel count TLVs */
3122 if ((channels % 2) != 0)
3123 return -1;
3124
3125 for (c = 0; c < 7; c += 2) {
3126 if (cap->speakers[c] || cap->speakers[c+1])
3127 chanpairs++;
3128 }
3129
3130 if (chanpairs * 2 != channels)
3131 return -1;
3132
3133 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3134}
3135
3136static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3137 unsigned int *chmap, int channels)
3138{
3139 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3140 int count = 0;
3141 int c;
3142
3143 for (c = 7; c >= 0; c--) {
3144 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3145 int spk = cap->speakers[chan];
3146 if (!spk) {
3147 /* add N/A channel if the companion channel is occupied */
3148 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3149 chmap[count++] = SNDRV_CHMAP_NA;
3150
3151 continue;
3152 }
3153
3154 chmap[count++] = spk_to_chmap(spk);
3155 }
3156
3157 WARN_ON(count != channels);
3158}
3159
3160static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3161 bool hbr)
3162{
3163 int hbr_ctl, hbr_ctl_new;
3164
3165 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3166 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3167 if (hbr)
3168 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3169 else
3170 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3171
3172 codec_dbg(codec,
3173 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3174 pin_nid,
3175 hbr_ctl == hbr_ctl_new ? "" : "new-",
3176 hbr_ctl_new);
3177
3178 if (hbr_ctl != hbr_ctl_new)
3179 snd_hda_codec_write(codec, pin_nid, 0,
3180 ATI_VERB_SET_HBR_CONTROL,
3181 hbr_ctl_new);
3182
3183 } else if (hbr)
3184 return -EINVAL;
3185
3186 return 0;
3187}
3188
3189static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3190 hda_nid_t pin_nid, u32 stream_tag, int format)
3191{
3192
3193 if (is_amdhdmi_rev3_or_later(codec)) {
3194 int ramp_rate = 180; /* default as per AMD spec */
3195 /* disable ramp-up/down for non-pcm as per AMD spec */
3196 if (format & AC_FMT_TYPE_NON_PCM)
3197 ramp_rate = 0;
3198
3199 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3200 }
3201
3202 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3203}
3204
3205
3206static int atihdmi_init(struct hda_codec *codec)
3207{
3208 struct hdmi_spec *spec = codec->spec;
3209 int pin_idx, err;
3210
3211 err = generic_hdmi_init(codec);
3212
3213 if (err)
3214 return err;
3215
3216 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3217 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3218
3219 /* make sure downmix information in infoframe is zero */
3220 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3221
3222 /* enable channel-wise remap mode if supported */
3223 if (has_amd_full_remap_support(codec))
3224 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3225 ATI_VERB_SET_MULTICHANNEL_MODE,
3226 ATI_MULTICHANNEL_MODE_SINGLE);
3227 }
3228
3229 return 0;
3230}
3231
3232static int patch_atihdmi(struct hda_codec *codec)
3233{
3234 struct hdmi_spec *spec;
3235 struct hdmi_spec_per_cvt *per_cvt;
3236 int err, cvt_idx;
3237
3238 err = patch_generic_hdmi(codec);
3239
3240 if (err)
3241 return err;
3242
3243 codec->patch_ops.init = atihdmi_init;
3244
3245 spec = codec->spec;
3246
3247 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3248 spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3249 spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3250 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3251 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3252 spec->ops.setup_stream = atihdmi_setup_stream;
3253
3254 if (!has_amd_full_remap_support(codec)) {
3255 /* override to ATI/AMD-specific versions with pairwise mapping */
3256 spec->ops.chmap_cea_alloc_validate_get_type =
3257 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3258 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3259 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3260 }
3261
3262 /* ATI/AMD converters do not advertise all of their capabilities */
3263 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3264 per_cvt = get_cvt(spec, cvt_idx);
3265 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3266 per_cvt->rates |= SUPPORTED_RATES;
3267 per_cvt->formats |= SUPPORTED_FORMATS;
3268 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3269 }
3270
3271 spec->channels_max = max(spec->channels_max, 8u);
3272
3273 return 0;
3274}
3275
3276/* VIA HDMI Implementation */
3277#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3278#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3279
3280static int patch_via_hdmi(struct hda_codec *codec)
3281{
3282 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3283}
3284
3285/*
3286 * called from hda_codec.c for generic HDMI support
3287 */
3288int snd_hda_parse_hdmi_codec(struct hda_codec *codec)
3289{
3290 return patch_generic_hdmi(codec);
3291}
3292EXPORT_SYMBOL_GPL(snd_hda_parse_hdmi_codec);
3293
3294/*
3295 * patch entries
3296 */
3297static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3298{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
3299{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
3300{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
3301{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi },
3302{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
3303{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
3304{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
3305{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3306{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3307{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3308{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
3309{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
3310{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi },
3311{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi },
3312{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi },
3313{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi },
3314{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi },
3315{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi },
3316{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi },
3317{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi },
3318{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi },
3319{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi },
3320{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi },
3321/* 17 is known to be absent */
3322{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi },
3323{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi },
3324{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi },
3325{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi },
3326{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi },
3327{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi },
3328{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi },
3329{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi },
3330{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi },
3331{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi },
3332{ .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_nvhdmi },
3333{ .id = 0x10de0060, .name = "GPU 60 HDMI/DP", .patch = patch_nvhdmi },
3334{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
3335{ .id = 0x10de0071, .name = "GPU 71 HDMI/DP", .patch = patch_nvhdmi },
3336{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
3337{ .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3338{ .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
3339{ .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3340{ .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
3341{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3342{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
3343{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
3344{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
3345{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
3346{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
3347{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3348{ .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
3349{ .id = 0x80862808, .name = "Broadwell HDMI", .patch = patch_generic_hdmi },
3350{ .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
3351{ .id = 0x80862882, .name = "Valleyview2 HDMI", .patch = patch_generic_hdmi },
3352{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
3353{} /* terminator */
3354};
3355
3356MODULE_ALIAS("snd-hda-codec-id:1002793c");
3357MODULE_ALIAS("snd-hda-codec-id:10027919");
3358MODULE_ALIAS("snd-hda-codec-id:1002791a");
3359MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3360MODULE_ALIAS("snd-hda-codec-id:10951390");
3361MODULE_ALIAS("snd-hda-codec-id:10951392");
3362MODULE_ALIAS("snd-hda-codec-id:10de0002");
3363MODULE_ALIAS("snd-hda-codec-id:10de0003");
3364MODULE_ALIAS("snd-hda-codec-id:10de0005");
3365MODULE_ALIAS("snd-hda-codec-id:10de0006");
3366MODULE_ALIAS("snd-hda-codec-id:10de0007");
3367MODULE_ALIAS("snd-hda-codec-id:10de000a");
3368MODULE_ALIAS("snd-hda-codec-id:10de000b");
3369MODULE_ALIAS("snd-hda-codec-id:10de000c");
3370MODULE_ALIAS("snd-hda-codec-id:10de000d");
3371MODULE_ALIAS("snd-hda-codec-id:10de0010");
3372MODULE_ALIAS("snd-hda-codec-id:10de0011");
3373MODULE_ALIAS("snd-hda-codec-id:10de0012");
3374MODULE_ALIAS("snd-hda-codec-id:10de0013");
3375MODULE_ALIAS("snd-hda-codec-id:10de0014");
3376MODULE_ALIAS("snd-hda-codec-id:10de0015");
3377MODULE_ALIAS("snd-hda-codec-id:10de0016");
3378MODULE_ALIAS("snd-hda-codec-id:10de0018");
3379MODULE_ALIAS("snd-hda-codec-id:10de0019");
3380MODULE_ALIAS("snd-hda-codec-id:10de001a");
3381MODULE_ALIAS("snd-hda-codec-id:10de001b");
3382MODULE_ALIAS("snd-hda-codec-id:10de001c");
3383MODULE_ALIAS("snd-hda-codec-id:10de0040");
3384MODULE_ALIAS("snd-hda-codec-id:10de0041");
3385MODULE_ALIAS("snd-hda-codec-id:10de0042");
3386MODULE_ALIAS("snd-hda-codec-id:10de0043");
3387MODULE_ALIAS("snd-hda-codec-id:10de0044");
3388MODULE_ALIAS("snd-hda-codec-id:10de0051");
3389MODULE_ALIAS("snd-hda-codec-id:10de0060");
3390MODULE_ALIAS("snd-hda-codec-id:10de0067");
3391MODULE_ALIAS("snd-hda-codec-id:10de0071");
3392MODULE_ALIAS("snd-hda-codec-id:10de8001");
3393MODULE_ALIAS("snd-hda-codec-id:11069f80");
3394MODULE_ALIAS("snd-hda-codec-id:11069f81");
3395MODULE_ALIAS("snd-hda-codec-id:11069f84");
3396MODULE_ALIAS("snd-hda-codec-id:11069f85");
3397MODULE_ALIAS("snd-hda-codec-id:17e80047");
3398MODULE_ALIAS("snd-hda-codec-id:80860054");
3399MODULE_ALIAS("snd-hda-codec-id:80862801");
3400MODULE_ALIAS("snd-hda-codec-id:80862802");
3401MODULE_ALIAS("snd-hda-codec-id:80862803");
3402MODULE_ALIAS("snd-hda-codec-id:80862804");
3403MODULE_ALIAS("snd-hda-codec-id:80862805");
3404MODULE_ALIAS("snd-hda-codec-id:80862806");
3405MODULE_ALIAS("snd-hda-codec-id:80862807");
3406MODULE_ALIAS("snd-hda-codec-id:80862808");
3407MODULE_ALIAS("snd-hda-codec-id:80862880");
3408MODULE_ALIAS("snd-hda-codec-id:80862882");
3409MODULE_ALIAS("snd-hda-codec-id:808629fb");
3410
3411MODULE_LICENSE("GPL");
3412MODULE_DESCRIPTION("HDMI HD-audio codec");
3413MODULE_ALIAS("snd-hda-codec-intelhdmi");
3414MODULE_ALIAS("snd-hda-codec-nvhdmi");
3415MODULE_ALIAS("snd-hda-codec-atihdmi");
3416
3417static struct hda_codec_preset_list intel_list = {
3418 .preset = snd_hda_preset_hdmi,
3419 .owner = THIS_MODULE,
3420};
3421
3422static int __init patch_hdmi_init(void)
3423{
3424 return snd_hda_add_codec_preset(&intel_list);
3425}
3426
3427static void __exit patch_hdmi_exit(void)
3428{
3429 snd_hda_delete_codec_preset(&intel_list);
3430}
3431
3432module_init(patch_hdmi_init)
3433module_exit(patch_hdmi_exit)