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1/*
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_INTERFACE_H_
27#define DC_INTERFACE_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31#include "logger_types.h"
32#include "gpio_types.h"
33#include "link_service_types.h"
34#include "grph_object_ctrl_defs.h"
35#include <inc/hw/opp.h>
36
37#include "inc/hw_sequencer.h"
38#include "inc/compressor.h"
39#include "inc/hw/dmcu.h"
40#include "dml/display_mode_lib.h"
41
42#define DC_VER "3.2.48"
43
44#define MAX_SURFACES 3
45#define MAX_PLANES 6
46#define MAX_STREAMS 6
47#define MAX_SINKS_PER_LINK 4
48
49/*******************************************************************************
50 * Display Core Interfaces
51 ******************************************************************************/
52struct dc_versions {
53 const char *dc_ver;
54 struct dmcu_version dmcu_version;
55};
56
57enum dc_plane_type {
58 DC_PLANE_TYPE_INVALID,
59 DC_PLANE_TYPE_DCE_RGB,
60 DC_PLANE_TYPE_DCE_UNDERLAY,
61 DC_PLANE_TYPE_DCN_UNIVERSAL,
62};
63
64struct dc_plane_cap {
65 enum dc_plane_type type;
66 uint32_t blends_with_above : 1;
67 uint32_t blends_with_below : 1;
68 uint32_t per_pixel_alpha : 1;
69 struct {
70 uint32_t argb8888 : 1;
71 uint32_t nv12 : 1;
72 uint32_t fp16 : 1;
73 uint32_t p010 : 1;
74 uint32_t ayuv : 1;
75 } pixel_format_support;
76 // max upscaling factor x1000
77 // upscaling factors are always >= 1
78 // for example, 1080p -> 8K is 4.0, or 4000 raw value
79 struct {
80 uint32_t argb8888;
81 uint32_t nv12;
82 uint32_t fp16;
83 } max_upscale_factor;
84 // max downscale factor x1000
85 // downscale factors are always <= 1
86 // for example, 8K -> 1080p is 0.25, or 250 raw value
87 struct {
88 uint32_t argb8888;
89 uint32_t nv12;
90 uint32_t fp16;
91 } max_downscale_factor;
92};
93
94struct dc_caps {
95 uint32_t max_streams;
96 uint32_t max_links;
97 uint32_t max_audios;
98 uint32_t max_slave_planes;
99 uint32_t max_planes;
100 uint32_t max_downscale_ratio;
101 uint32_t i2c_speed_in_khz;
102 uint32_t dmdata_alloc_size;
103 unsigned int max_cursor_size;
104 unsigned int max_video_width;
105 int linear_pitch_alignment;
106 bool dcc_const_color;
107 bool dynamic_audio;
108 bool is_apu;
109 bool dual_link_dvi;
110 bool post_blend_color_processing;
111 bool force_dp_tps4_for_cp2520;
112 bool disable_dp_clk_share;
113 bool psp_setup_panel_mode;
114#ifdef CONFIG_DRM_AMD_DC_DCN2_0
115 bool hw_3d_lut;
116#endif
117 struct dc_plane_cap planes[MAX_PLANES];
118};
119
120#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
121struct dc_bug_wa {
122 bool no_connect_phy_config;
123 bool dedcn20_305_wa;
124 bool skip_clock_update;
125};
126#endif
127
128struct dc_dcc_surface_param {
129 struct dc_size surface_size;
130 enum surface_pixel_format format;
131 enum swizzle_mode_values swizzle_mode;
132 enum dc_scan_direction scan;
133};
134
135struct dc_dcc_setting {
136 unsigned int max_compressed_blk_size;
137 unsigned int max_uncompressed_blk_size;
138 bool independent_64b_blks;
139};
140
141struct dc_surface_dcc_cap {
142 union {
143 struct {
144 struct dc_dcc_setting rgb;
145 } grph;
146
147 struct {
148 struct dc_dcc_setting luma;
149 struct dc_dcc_setting chroma;
150 } video;
151 };
152
153 bool capable;
154 bool const_color_support;
155};
156
157struct dc_static_screen_events {
158 bool force_trigger;
159 bool cursor_update;
160 bool surface_update;
161 bool overlay_update;
162};
163
164
165/* Surface update type is used by dc_update_surfaces_and_stream
166 * The update type is determined at the very beginning of the function based
167 * on parameters passed in and decides how much programming (or updating) is
168 * going to be done during the call.
169 *
170 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
171 * logical calculations or hardware register programming. This update MUST be
172 * ISR safe on windows. Currently fast update will only be used to flip surface
173 * address.
174 *
175 * UPDATE_TYPE_MED is used for slower updates which require significant hw
176 * re-programming however do not affect bandwidth consumption or clock
177 * requirements. At present, this is the level at which front end updates
178 * that do not require us to run bw_calcs happen. These are in/out transfer func
179 * updates, viewport offset changes, recout size changes and pixel depth changes.
180 * This update can be done at ISR, but we want to minimize how often this happens.
181 *
182 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
183 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
184 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
185 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
186 * a full update. This cannot be done at ISR level and should be a rare event.
187 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
188 * underscan we don't expect to see this call at all.
189 */
190
191enum surface_update_type {
192 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
193 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
194 UPDATE_TYPE_FULL, /* may need to shuffle resources */
195};
196
197/* Forward declaration*/
198struct dc;
199struct dc_plane_state;
200struct dc_state;
201
202
203struct dc_cap_funcs {
204 bool (*get_dcc_compression_cap)(const struct dc *dc,
205 const struct dc_dcc_surface_param *input,
206 struct dc_surface_dcc_cap *output);
207};
208
209struct link_training_settings;
210
211
212/* Structure to hold configuration flags set by dm at dc creation. */
213struct dc_config {
214 bool gpu_vm_support;
215 bool disable_disp_pll_sharing;
216 bool fbc_support;
217 bool optimize_edp_link_rate;
218 bool disable_fractional_pwm;
219 bool allow_seamless_boot_optimization;
220 bool power_down_display_on_boot;
221 bool edp_not_connected;
222 bool forced_clocks;
223 bool multi_mon_pp_mclk_switch;
224};
225
226enum visual_confirm {
227 VISUAL_CONFIRM_DISABLE = 0,
228 VISUAL_CONFIRM_SURFACE = 1,
229 VISUAL_CONFIRM_HDR = 2,
230};
231
232enum dcc_option {
233 DCC_ENABLE = 0,
234 DCC_DISABLE = 1,
235 DCC_HALF_REQ_DISALBE = 2,
236};
237
238enum pipe_split_policy {
239 MPC_SPLIT_DYNAMIC = 0,
240 MPC_SPLIT_AVOID = 1,
241 MPC_SPLIT_AVOID_MULT_DISP = 2,
242};
243
244enum wm_report_mode {
245 WM_REPORT_DEFAULT = 0,
246 WM_REPORT_OVERRIDE = 1,
247};
248
249/*
250 * For any clocks that may differ per pipe
251 * only the max is stored in this structure
252 */
253struct dc_clocks {
254 int dispclk_khz;
255 int max_supported_dppclk_khz;
256 int max_supported_dispclk_khz;
257 int dppclk_khz;
258 int bw_dppclk_khz; /*a copy of dppclk_khz*/
259 int bw_dispclk_khz;
260 int dcfclk_khz;
261 int socclk_khz;
262 int dcfclk_deep_sleep_khz;
263 int fclk_khz;
264 int phyclk_khz;
265 int dramclk_khz;
266 bool p_state_change_support;
267
268 /*
269 * Elements below are not compared for the purposes of
270 * optimization required
271 */
272 bool prev_p_state_change_support;
273};
274
275struct dc_bw_validation_profile {
276 bool enable;
277
278 unsigned long long total_ticks;
279 unsigned long long voltage_level_ticks;
280 unsigned long long watermark_ticks;
281 unsigned long long rq_dlg_ticks;
282
283 unsigned long long total_count;
284 unsigned long long skip_fast_count;
285 unsigned long long skip_pass_count;
286 unsigned long long skip_fail_count;
287};
288
289#define BW_VAL_TRACE_SETUP() \
290 unsigned long long end_tick = 0; \
291 unsigned long long voltage_level_tick = 0; \
292 unsigned long long watermark_tick = 0; \
293 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
294 dm_get_timestamp(dc->ctx) : 0
295
296#define BW_VAL_TRACE_COUNT() \
297 if (dc->debug.bw_val_profile.enable) \
298 dc->debug.bw_val_profile.total_count++
299
300#define BW_VAL_TRACE_SKIP(status) \
301 if (dc->debug.bw_val_profile.enable) { \
302 if (!voltage_level_tick) \
303 voltage_level_tick = dm_get_timestamp(dc->ctx); \
304 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
305 }
306
307#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
308 if (dc->debug.bw_val_profile.enable) \
309 voltage_level_tick = dm_get_timestamp(dc->ctx)
310
311#define BW_VAL_TRACE_END_WATERMARKS() \
312 if (dc->debug.bw_val_profile.enable) \
313 watermark_tick = dm_get_timestamp(dc->ctx)
314
315#define BW_VAL_TRACE_FINISH() \
316 if (dc->debug.bw_val_profile.enable) { \
317 end_tick = dm_get_timestamp(dc->ctx); \
318 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
319 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
320 if (watermark_tick) { \
321 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
322 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
323 } \
324 }
325
326struct dc_debug_options {
327 enum visual_confirm visual_confirm;
328 bool sanity_checks;
329 bool max_disp_clk;
330 bool surface_trace;
331 bool timing_trace;
332 bool clock_trace;
333 bool validation_trace;
334 bool bandwidth_calcs_trace;
335 int max_downscale_src_width;
336
337 /* stutter efficiency related */
338 bool disable_stutter;
339 bool use_max_lb;
340 enum dcc_option disable_dcc;
341 enum pipe_split_policy pipe_split_policy;
342 bool force_single_disp_pipe_split;
343 bool voltage_align_fclk;
344
345 bool disable_dfs_bypass;
346 bool disable_dpp_power_gate;
347 bool disable_hubp_power_gate;
348#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
349 bool disable_dsc_power_gate;
350#endif
351 bool disable_pplib_wm_range;
352 enum wm_report_mode pplib_wm_report_mode;
353 unsigned int min_disp_clk_khz;
354 unsigned int min_dpp_clk_khz;
355 int sr_exit_time_dpm0_ns;
356 int sr_enter_plus_exit_time_dpm0_ns;
357 int sr_exit_time_ns;
358 int sr_enter_plus_exit_time_ns;
359 int urgent_latency_ns;
360 uint32_t underflow_assert_delay_us;
361 int percent_of_ideal_drambw;
362 int dram_clock_change_latency_ns;
363 bool optimized_watermark;
364 int always_scale;
365 bool disable_pplib_clock_request;
366 bool disable_clock_gate;
367 bool disable_dmcu;
368 bool disable_psr;
369 bool force_abm_enable;
370 bool disable_stereo_support;
371 bool vsr_support;
372 bool performance_trace;
373 bool az_endpoint_mute_only;
374 bool always_use_regamma;
375 bool p010_mpo_support;
376 bool recovery_enabled;
377 bool avoid_vbios_exec_table;
378 bool scl_reset_length10;
379 bool hdmi20_disable;
380 bool skip_detection_link_training;
381 bool remove_disconnect_edp;
382 unsigned int force_odm_combine; //bit vector based on otg inst
383 unsigned int force_fclk_khz;
384 bool disable_tri_buf;
385 struct dc_bw_validation_profile bw_val_profile;
386#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
387 bool disable_fec;
388#endif
389#ifdef CONFIG_DRM_AMD_DC_DCN2_1
390 bool disable_48mhz_pwrdwn;
391#endif
392 /* This forces a hard min on the DCFCLK requested to SMU/PP
393 * watermarks are not affected.
394 */
395 unsigned int force_min_dcfclk_mhz;
396 bool disable_timing_sync;
397#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
398 bool cm_in_bypass;
399#endif
400 int force_clock_mode;/*every mode change.*/
401};
402
403struct dc_debug_data {
404 uint32_t ltFailCount;
405 uint32_t i2cErrorCount;
406 uint32_t auxErrorCount;
407};
408
409#ifdef CONFIG_DRM_AMD_DC_DCN2_0
410struct dc_phy_addr_space_config {
411 struct {
412 uint64_t start_addr;
413 uint64_t end_addr;
414 uint64_t fb_top;
415 uint64_t fb_offset;
416 uint64_t fb_base;
417 uint64_t agp_top;
418 uint64_t agp_bot;
419 uint64_t agp_base;
420 } system_aperture;
421
422 struct {
423 uint64_t page_table_start_addr;
424 uint64_t page_table_end_addr;
425 uint64_t page_table_base_addr;
426 } gart_config;
427
428 bool valid;
429 uint64_t page_table_default_page_addr;
430};
431
432struct dc_virtual_addr_space_config {
433 uint64_t page_table_base_addr;
434 uint64_t page_table_start_addr;
435 uint64_t page_table_end_addr;
436 uint32_t page_table_block_size_in_bytes;
437 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
438};
439#endif
440
441struct dc_bounding_box_overrides {
442 int sr_exit_time_ns;
443 int sr_enter_plus_exit_time_ns;
444 int urgent_latency_ns;
445 int percent_of_ideal_drambw;
446 int dram_clock_change_latency_ns;
447 /* This forces a hard min on the DCFCLK we use
448 * for DML. Unlike the debug option for forcing
449 * DCFCLK, this override affects watermark calculations
450 */
451 int min_dcfclk_mhz;
452};
453
454struct dc_state;
455struct resource_pool;
456struct dce_hwseq;
457struct gpu_info_soc_bounding_box_v1_0;
458struct dc {
459 struct dc_versions versions;
460 struct dc_caps caps;
461 struct dc_cap_funcs cap_funcs;
462 struct dc_config config;
463 struct dc_debug_options debug;
464 struct dc_bounding_box_overrides bb_overrides;
465#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
466 struct dc_bug_wa work_arounds;
467#endif
468 struct dc_context *ctx;
469#ifdef CONFIG_DRM_AMD_DC_DCN2_0
470 struct dc_phy_addr_space_config vm_pa_config;
471#endif
472
473 uint8_t link_count;
474 struct dc_link *links[MAX_PIPES * 2];
475
476 struct dc_state *current_state;
477 struct resource_pool *res_pool;
478
479 struct clk_mgr *clk_mgr;
480
481 /* Display Engine Clock levels */
482 struct dm_pp_clock_levels sclk_lvls;
483
484 /* Inputs into BW and WM calculations. */
485 struct bw_calcs_dceip *bw_dceip;
486 struct bw_calcs_vbios *bw_vbios;
487#ifdef CONFIG_DRM_AMD_DC_DCN1_0
488 struct dcn_soc_bounding_box *dcn_soc;
489 struct dcn_ip_params *dcn_ip;
490 struct display_mode_lib dml;
491#endif
492
493 /* HW functions */
494 struct hw_sequencer_funcs hwss;
495 struct dce_hwseq *hwseq;
496
497 /* Require to optimize clocks and bandwidth for added/removed planes */
498 bool optimized_required;
499
500 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
501 bool optimize_seamless_boot;
502
503 /* FBC compressor */
504 struct compressor *fbc_compressor;
505
506 struct dc_debug_data debug_data;
507
508 const char *build_id;
509#ifdef CONFIG_DRM_AMD_DC_DCN2_0
510 struct vm_helper *vm_helper;
511 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
512#endif
513};
514
515enum frame_buffer_mode {
516 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
517 FRAME_BUFFER_MODE_ZFB_ONLY,
518 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
519} ;
520
521struct dchub_init_data {
522 int64_t zfb_phys_addr_base;
523 int64_t zfb_mc_base_addr;
524 uint64_t zfb_size_in_byte;
525 enum frame_buffer_mode fb_mode;
526 bool dchub_initialzied;
527 bool dchub_info_valid;
528};
529
530struct dc_init_data {
531 struct hw_asic_id asic_id;
532 void *driver; /* ctx */
533 struct cgs_device *cgs_device;
534 struct dc_bounding_box_overrides bb_overrides;
535
536 int num_virtual_links;
537 /*
538 * If 'vbios_override' not NULL, it will be called instead
539 * of the real VBIOS. Intended use is Diagnostics on FPGA.
540 */
541 struct dc_bios *vbios_override;
542 enum dce_environment dce_environment;
543
544 struct dc_config flags;
545 uint32_t log_mask;
546#ifdef CONFIG_DRM_AMD_DC_DCN2_0
547 /**
548 * gpu_info FW provided soc bounding box struct or 0 if not
549 * available in FW
550 */
551 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
552#endif
553};
554
555struct dc_callback_init {
556 uint8_t reserved;
557};
558
559struct dc *dc_create(const struct dc_init_data *init_params);
560int dc_get_vmid_use_vector(struct dc *dc);
561#ifdef CONFIG_DRM_AMD_DC_DCN2_0
562void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
563/* Returns the number of vmids supported */
564int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
565#endif
566void dc_init_callbacks(struct dc *dc,
567 const struct dc_callback_init *init_params);
568void dc_destroy(struct dc **dc);
569
570/*******************************************************************************
571 * Surface Interfaces
572 ******************************************************************************/
573
574enum {
575 TRANSFER_FUNC_POINTS = 1025
576};
577
578struct dc_hdr_static_metadata {
579 /* display chromaticities and white point in units of 0.00001 */
580 unsigned int chromaticity_green_x;
581 unsigned int chromaticity_green_y;
582 unsigned int chromaticity_blue_x;
583 unsigned int chromaticity_blue_y;
584 unsigned int chromaticity_red_x;
585 unsigned int chromaticity_red_y;
586 unsigned int chromaticity_white_point_x;
587 unsigned int chromaticity_white_point_y;
588
589 uint32_t min_luminance;
590 uint32_t max_luminance;
591 uint32_t maximum_content_light_level;
592 uint32_t maximum_frame_average_light_level;
593};
594
595enum dc_transfer_func_type {
596 TF_TYPE_PREDEFINED,
597 TF_TYPE_DISTRIBUTED_POINTS,
598 TF_TYPE_BYPASS,
599 TF_TYPE_HWPWL
600};
601
602struct dc_transfer_func_distributed_points {
603 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
604 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
605 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
606
607 uint16_t end_exponent;
608 uint16_t x_point_at_y1_red;
609 uint16_t x_point_at_y1_green;
610 uint16_t x_point_at_y1_blue;
611};
612
613enum dc_transfer_func_predefined {
614 TRANSFER_FUNCTION_SRGB,
615 TRANSFER_FUNCTION_BT709,
616 TRANSFER_FUNCTION_PQ,
617 TRANSFER_FUNCTION_LINEAR,
618 TRANSFER_FUNCTION_UNITY,
619 TRANSFER_FUNCTION_HLG,
620 TRANSFER_FUNCTION_HLG12,
621 TRANSFER_FUNCTION_GAMMA22,
622 TRANSFER_FUNCTION_GAMMA24,
623 TRANSFER_FUNCTION_GAMMA26
624};
625
626
627struct dc_transfer_func {
628 struct kref refcount;
629 enum dc_transfer_func_type type;
630 enum dc_transfer_func_predefined tf;
631 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
632 uint32_t sdr_ref_white_level;
633 struct dc_context *ctx;
634 union {
635 struct pwl_params pwl;
636 struct dc_transfer_func_distributed_points tf_pts;
637 };
638};
639
640#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
641
642union dc_3dlut_state {
643 struct {
644 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
645 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
646 uint32_t rmu_mux_num:3; /*index of mux to use*/
647 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
648 uint32_t mpc_rmu1_mux:4;
649 uint32_t mpc_rmu2_mux:4;
650 uint32_t reserved:15;
651 } bits;
652 uint32_t raw;
653};
654
655
656struct dc_3dlut {
657 struct kref refcount;
658 struct tetrahedral_params lut_3d;
659 uint32_t hdr_multiplier;
660 bool initialized; /*remove after diag fix*/
661 union dc_3dlut_state state;
662 struct dc_context *ctx;
663};
664#endif
665/*
666 * This structure is filled in by dc_surface_get_status and contains
667 * the last requested address and the currently active address so the called
668 * can determine if there are any outstanding flips
669 */
670struct dc_plane_status {
671 struct dc_plane_address requested_address;
672 struct dc_plane_address current_address;
673 bool is_flip_pending;
674 bool is_right_eye;
675};
676
677union surface_update_flags {
678
679 struct {
680 uint32_t addr_update:1;
681 /* Medium updates */
682 uint32_t dcc_change:1;
683 uint32_t color_space_change:1;
684 uint32_t horizontal_mirror_change:1;
685 uint32_t per_pixel_alpha_change:1;
686 uint32_t global_alpha_change:1;
687 uint32_t sdr_white_level:1;
688 uint32_t rotation_change:1;
689 uint32_t swizzle_change:1;
690 uint32_t scaling_change:1;
691 uint32_t position_change:1;
692 uint32_t in_transfer_func_change:1;
693 uint32_t input_csc_change:1;
694 uint32_t coeff_reduction_change:1;
695 uint32_t output_tf_change:1;
696 uint32_t pixel_format_change:1;
697 uint32_t plane_size_change:1;
698
699 /* Full updates */
700 uint32_t new_plane:1;
701 uint32_t bpp_change:1;
702 uint32_t gamma_change:1;
703 uint32_t bandwidth_change:1;
704 uint32_t clock_change:1;
705 uint32_t stereo_format_change:1;
706 uint32_t full_update:1;
707 } bits;
708
709 uint32_t raw;
710};
711
712struct dc_plane_state {
713 struct dc_plane_address address;
714 struct dc_plane_flip_time time;
715#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
716 bool triplebuffer_flips;
717#endif
718 struct scaling_taps scaling_quality;
719 struct rect src_rect;
720 struct rect dst_rect;
721 struct rect clip_rect;
722
723 struct plane_size plane_size;
724 union dc_tiling_info tiling_info;
725
726 struct dc_plane_dcc_param dcc;
727
728 struct dc_gamma *gamma_correction;
729 struct dc_transfer_func *in_transfer_func;
730 struct dc_bias_and_scale *bias_and_scale;
731 struct dc_csc_transform input_csc_color_matrix;
732 struct fixed31_32 coeff_reduction_factor;
733 uint32_t sdr_white_level;
734
735 // TODO: No longer used, remove
736 struct dc_hdr_static_metadata hdr_static_ctx;
737
738 enum dc_color_space color_space;
739
740#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
741 struct dc_3dlut *lut3d_func;
742 struct dc_transfer_func *in_shaper_func;
743 struct dc_transfer_func *blend_tf;
744#endif
745
746 enum surface_pixel_format format;
747 enum dc_rotation_angle rotation;
748 enum plane_stereo_format stereo_format;
749
750 bool is_tiling_rotated;
751 bool per_pixel_alpha;
752 bool global_alpha;
753 int global_alpha_value;
754 bool visible;
755 bool flip_immediate;
756 bool horizontal_mirror;
757 int layer_index;
758
759 union surface_update_flags update_flags;
760 /* private to DC core */
761 struct dc_plane_status status;
762 struct dc_context *ctx;
763
764 /* HACK: Workaround for forcing full reprogramming under some conditions */
765 bool force_full_update;
766
767 /* private to dc_surface.c */
768 enum dc_irq_source irq_source;
769 struct kref refcount;
770};
771
772struct dc_plane_info {
773 struct plane_size plane_size;
774 union dc_tiling_info tiling_info;
775 struct dc_plane_dcc_param dcc;
776 enum surface_pixel_format format;
777 enum dc_rotation_angle rotation;
778 enum plane_stereo_format stereo_format;
779 enum dc_color_space color_space;
780 unsigned int sdr_white_level;
781 bool horizontal_mirror;
782 bool visible;
783 bool per_pixel_alpha;
784 bool global_alpha;
785 int global_alpha_value;
786 bool input_csc_enabled;
787 int layer_index;
788};
789
790struct dc_scaling_info {
791 struct rect src_rect;
792 struct rect dst_rect;
793 struct rect clip_rect;
794 struct scaling_taps scaling_quality;
795};
796
797struct dc_surface_update {
798 struct dc_plane_state *surface;
799
800 /* isr safe update parameters. null means no updates */
801 const struct dc_flip_addrs *flip_addr;
802 const struct dc_plane_info *plane_info;
803 const struct dc_scaling_info *scaling_info;
804
805 /* following updates require alloc/sleep/spin that is not isr safe,
806 * null means no updates
807 */
808 const struct dc_gamma *gamma;
809 const struct dc_transfer_func *in_transfer_func;
810
811 const struct dc_csc_transform *input_csc_color_matrix;
812 const struct fixed31_32 *coeff_reduction_factor;
813#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
814 const struct dc_transfer_func *func_shaper;
815 const struct dc_3dlut *lut3d_func;
816 const struct dc_transfer_func *blend_tf;
817#endif
818};
819
820/*
821 * Create a new surface with default parameters;
822 */
823struct dc_plane_state *dc_create_plane_state(struct dc *dc);
824const struct dc_plane_status *dc_plane_get_status(
825 const struct dc_plane_state *plane_state);
826
827void dc_plane_state_retain(struct dc_plane_state *plane_state);
828void dc_plane_state_release(struct dc_plane_state *plane_state);
829
830void dc_gamma_retain(struct dc_gamma *dc_gamma);
831void dc_gamma_release(struct dc_gamma **dc_gamma);
832struct dc_gamma *dc_create_gamma(void);
833
834void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
835void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
836struct dc_transfer_func *dc_create_transfer_func(void);
837
838#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
839struct dc_3dlut *dc_create_3dlut_func(void);
840void dc_3dlut_func_release(struct dc_3dlut *lut);
841void dc_3dlut_func_retain(struct dc_3dlut *lut);
842#endif
843/*
844 * This structure holds a surface address. There could be multiple addresses
845 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
846 * as frame durations and DCC format can also be set.
847 */
848struct dc_flip_addrs {
849 struct dc_plane_address address;
850 unsigned int flip_timestamp_in_us;
851 bool flip_immediate;
852 /* TODO: add flip duration for FreeSync */
853};
854
855bool dc_post_update_surfaces_to_stream(
856 struct dc *dc);
857
858#include "dc_stream.h"
859
860/*
861 * Structure to store surface/stream associations for validation
862 */
863struct dc_validation_set {
864 struct dc_stream_state *stream;
865 struct dc_plane_state *plane_states[MAX_SURFACES];
866 uint8_t plane_count;
867};
868
869bool dc_validate_seamless_boot_timing(const struct dc *dc,
870 const struct dc_sink *sink,
871 struct dc_crtc_timing *crtc_timing);
872
873enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
874
875void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
876
877bool dc_set_generic_gpio_for_stereo(bool enable,
878 struct gpio_service *gpio_service);
879
880/*
881 * fast_validate: we return after determining if we can support the new state,
882 * but before we populate the programming info
883 */
884enum dc_status dc_validate_global_state(
885 struct dc *dc,
886 struct dc_state *new_ctx,
887 bool fast_validate);
888
889
890void dc_resource_state_construct(
891 const struct dc *dc,
892 struct dc_state *dst_ctx);
893
894void dc_resource_state_copy_construct(
895 const struct dc_state *src_ctx,
896 struct dc_state *dst_ctx);
897
898void dc_resource_state_copy_construct_current(
899 const struct dc *dc,
900 struct dc_state *dst_ctx);
901
902void dc_resource_state_destruct(struct dc_state *context);
903
904/*
905 * TODO update to make it about validation sets
906 * Set up streams and links associated to drive sinks
907 * The streams parameter is an absolute set of all active streams.
908 *
909 * After this call:
910 * Phy, Encoder, Timing Generator are programmed and enabled.
911 * New streams are enabled with blank stream; no memory read.
912 */
913bool dc_commit_state(struct dc *dc, struct dc_state *context);
914
915
916struct dc_state *dc_create_state(struct dc *dc);
917struct dc_state *dc_copy_state(struct dc_state *src_ctx);
918void dc_retain_state(struct dc_state *context);
919void dc_release_state(struct dc_state *context);
920
921/*******************************************************************************
922 * Link Interfaces
923 ******************************************************************************/
924
925struct dpcd_caps {
926 union dpcd_rev dpcd_rev;
927 union max_lane_count max_ln_count;
928 union max_down_spread max_down_spread;
929 union dprx_feature dprx_feature;
930
931 /* valid only for eDP v1.4 or higher*/
932 uint8_t edp_supported_link_rates_count;
933 enum dc_link_rate edp_supported_link_rates[8];
934
935 /* dongle type (DP converter, CV smart dongle) */
936 enum display_dongle_type dongle_type;
937 /* branch device or sink device */
938 bool is_branch_dev;
939 /* Dongle's downstream count. */
940 union sink_count sink_count;
941 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
942 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
943 struct dc_dongle_caps dongle_caps;
944
945 uint32_t sink_dev_id;
946 int8_t sink_dev_id_str[6];
947 int8_t sink_hw_revision;
948 int8_t sink_fw_revision[2];
949
950 uint32_t branch_dev_id;
951 int8_t branch_dev_name[6];
952 int8_t branch_hw_revision;
953 int8_t branch_fw_revision[2];
954
955 bool allow_invalid_MSA_timing_param;
956 bool panel_mode_edp;
957 bool dpcd_display_control_capable;
958 bool ext_receiver_cap_field_present;
959#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
960 union dpcd_fec_capability fec_cap;
961 struct dpcd_dsc_capabilities dsc_caps;
962#endif
963};
964
965#include "dc_link.h"
966
967/*******************************************************************************
968 * Sink Interfaces - A sink corresponds to a display output device
969 ******************************************************************************/
970
971struct dc_container_id {
972 // 128bit GUID in binary form
973 unsigned char guid[16];
974 // 8 byte port ID -> ELD.PortID
975 unsigned int portId[2];
976 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
977 unsigned short manufacturerName;
978 // 2 byte product code -> ELD.ProductCode
979 unsigned short productCode;
980};
981
982
983#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
984struct dc_sink_dsc_caps {
985 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
986 // 'false' if they are sink's DSC caps
987 bool is_virtual_dpcd_dsc;
988 struct dsc_dec_dpcd_caps dsc_dec_caps;
989};
990#endif
991
992/*
993 * The sink structure contains EDID and other display device properties
994 */
995struct dc_sink {
996 enum signal_type sink_signal;
997 struct dc_edid dc_edid; /* raw edid */
998 struct dc_edid_caps edid_caps; /* parse display caps */
999 struct dc_container_id *dc_container_id;
1000 uint32_t dongle_max_pix_clk;
1001 void *priv;
1002 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1003 bool converter_disable_audio;
1004
1005#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
1006 struct dc_sink_dsc_caps sink_dsc_caps;
1007#endif
1008
1009 /* private to DC core */
1010 struct dc_link *link;
1011 struct dc_context *ctx;
1012
1013 uint32_t sink_id;
1014
1015 /* private to dc_sink.c */
1016 // refcount must be the last member in dc_sink, since we want the
1017 // sink structure to be logically cloneable up to (but not including)
1018 // refcount
1019 struct kref refcount;
1020};
1021
1022void dc_sink_retain(struct dc_sink *sink);
1023void dc_sink_release(struct dc_sink *sink);
1024
1025struct dc_sink_init_data {
1026 enum signal_type sink_signal;
1027 struct dc_link *link;
1028 uint32_t dongle_max_pix_clk;
1029 bool converter_disable_audio;
1030};
1031
1032struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1033
1034/* Newer interfaces */
1035struct dc_cursor {
1036 struct dc_plane_address address;
1037 struct dc_cursor_attributes attributes;
1038};
1039
1040
1041/*******************************************************************************
1042 * Interrupt interfaces
1043 ******************************************************************************/
1044enum dc_irq_source dc_interrupt_to_irq_source(
1045 struct dc *dc,
1046 uint32_t src_id,
1047 uint32_t ext_id);
1048bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1049void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1050enum dc_irq_source dc_get_hpd_irq_source_at_index(
1051 struct dc *dc, uint32_t link_index);
1052
1053/*******************************************************************************
1054 * Power Interfaces
1055 ******************************************************************************/
1056
1057void dc_set_power_state(
1058 struct dc *dc,
1059 enum dc_acpi_cm_power_state power_state);
1060void dc_resume(struct dc *dc);
1061unsigned int dc_get_current_backlight_pwm(struct dc *dc);
1062unsigned int dc_get_target_backlight_pwm(struct dc *dc);
1063
1064bool dc_is_dmcu_initialized(struct dc *dc);
1065
1066enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1067void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1068#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
1069/*******************************************************************************
1070 * DSC Interfaces
1071 ******************************************************************************/
1072#include "dc_dsc.h"
1073#endif
1074#endif /* DC_INTERFACE_H_ */
1/*
2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_INTERFACE_H_
27#define DC_INTERFACE_H_
28
29#include "dc_types.h"
30#include "dc_state.h"
31#include "dc_plane.h"
32#include "grph_object_defs.h"
33#include "logger_types.h"
34#include "hdcp_msg_types.h"
35#include "gpio_types.h"
36#include "link_service_types.h"
37#include "grph_object_ctrl_defs.h"
38#include <inc/hw/opp.h>
39
40#include "hwss/hw_sequencer.h"
41#include "inc/compressor.h"
42#include "inc/hw/dmcu.h"
43#include "dml/display_mode_lib.h"
44
45#include "dml2/dml2_wrapper.h"
46
47struct abm_save_restore;
48
49/* forward declaration */
50struct aux_payload;
51struct set_config_cmd_payload;
52struct dmub_notification;
53
54#define DC_VER "3.2.266"
55
56#define MAX_SURFACES 3
57#define MAX_PLANES 6
58#define MAX_STREAMS 6
59#define MIN_VIEWPORT_SIZE 12
60#define MAX_NUM_EDP 2
61
62/* Display Core Interfaces */
63struct dc_versions {
64 const char *dc_ver;
65 struct dmcu_version dmcu_version;
66};
67
68enum dp_protocol_version {
69 DP_VERSION_1_4 = 0,
70 DP_VERSION_2_1,
71 DP_VERSION_UNKNOWN,
72};
73
74enum dc_plane_type {
75 DC_PLANE_TYPE_INVALID,
76 DC_PLANE_TYPE_DCE_RGB,
77 DC_PLANE_TYPE_DCE_UNDERLAY,
78 DC_PLANE_TYPE_DCN_UNIVERSAL,
79};
80
81// Sizes defined as multiples of 64KB
82enum det_size {
83 DET_SIZE_DEFAULT = 0,
84 DET_SIZE_192KB = 3,
85 DET_SIZE_256KB = 4,
86 DET_SIZE_320KB = 5,
87 DET_SIZE_384KB = 6
88};
89
90
91struct dc_plane_cap {
92 enum dc_plane_type type;
93 uint32_t per_pixel_alpha : 1;
94 struct {
95 uint32_t argb8888 : 1;
96 uint32_t nv12 : 1;
97 uint32_t fp16 : 1;
98 uint32_t p010 : 1;
99 uint32_t ayuv : 1;
100 } pixel_format_support;
101 // max upscaling factor x1000
102 // upscaling factors are always >= 1
103 // for example, 1080p -> 8K is 4.0, or 4000 raw value
104 struct {
105 uint32_t argb8888;
106 uint32_t nv12;
107 uint32_t fp16;
108 } max_upscale_factor;
109 // max downscale factor x1000
110 // downscale factors are always <= 1
111 // for example, 8K -> 1080p is 0.25, or 250 raw value
112 struct {
113 uint32_t argb8888;
114 uint32_t nv12;
115 uint32_t fp16;
116 } max_downscale_factor;
117 // minimal width/height
118 uint32_t min_width;
119 uint32_t min_height;
120};
121
122/**
123 * DOC: color-management-caps
124 *
125 * **Color management caps (DPP and MPC)**
126 *
127 * Modules/color calculates various color operations which are translated to
128 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
129 * DCN1, every new generation comes with fairly major differences in color
130 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
131 * decide mapping to HW block based on logical capabilities.
132 */
133
134/**
135 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
136 * @srgb: RGB color space transfer func
137 * @bt2020: BT.2020 transfer func
138 * @gamma2_2: standard gamma
139 * @pq: perceptual quantizer transfer function
140 * @hlg: hybrid log–gamma transfer function
141 */
142struct rom_curve_caps {
143 uint16_t srgb : 1;
144 uint16_t bt2020 : 1;
145 uint16_t gamma2_2 : 1;
146 uint16_t pq : 1;
147 uint16_t hlg : 1;
148};
149
150/**
151 * struct dpp_color_caps - color pipeline capabilities for display pipe and
152 * plane blocks
153 *
154 * @dcn_arch: all DCE generations treated the same
155 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
156 * just plain 256-entry lookup
157 * @icsc: input color space conversion
158 * @dgam_ram: programmable degamma LUT
159 * @post_csc: post color space conversion, before gamut remap
160 * @gamma_corr: degamma correction
161 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
162 * with MPC by setting mpc:shared_3d_lut flag
163 * @ogam_ram: programmable out/blend gamma LUT
164 * @ocsc: output color space conversion
165 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
166 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
167 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
168 *
169 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
170 */
171struct dpp_color_caps {
172 uint16_t dcn_arch : 1;
173 uint16_t input_lut_shared : 1;
174 uint16_t icsc : 1;
175 uint16_t dgam_ram : 1;
176 uint16_t post_csc : 1;
177 uint16_t gamma_corr : 1;
178 uint16_t hw_3d_lut : 1;
179 uint16_t ogam_ram : 1;
180 uint16_t ocsc : 1;
181 uint16_t dgam_rom_for_yuv : 1;
182 struct rom_curve_caps dgam_rom_caps;
183 struct rom_curve_caps ogam_rom_caps;
184};
185
186/**
187 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
188 * plane combined blocks
189 *
190 * @gamut_remap: color transformation matrix
191 * @ogam_ram: programmable out gamma LUT
192 * @ocsc: output color space conversion matrix
193 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
194 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
195 * instance
196 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
197 */
198struct mpc_color_caps {
199 uint16_t gamut_remap : 1;
200 uint16_t ogam_ram : 1;
201 uint16_t ocsc : 1;
202 uint16_t num_3dluts : 3;
203 uint16_t shared_3d_lut:1;
204 struct rom_curve_caps ogam_rom_caps;
205};
206
207/**
208 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
209 * @dpp: color pipes caps for DPP
210 * @mpc: color pipes caps for MPC
211 */
212struct dc_color_caps {
213 struct dpp_color_caps dpp;
214 struct mpc_color_caps mpc;
215};
216
217struct dc_dmub_caps {
218 bool psr;
219 bool mclk_sw;
220 bool subvp_psr;
221 bool gecc_enable;
222};
223
224struct dc_caps {
225 uint32_t max_streams;
226 uint32_t max_links;
227 uint32_t max_audios;
228 uint32_t max_slave_planes;
229 uint32_t max_slave_yuv_planes;
230 uint32_t max_slave_rgb_planes;
231 uint32_t max_planes;
232 uint32_t max_downscale_ratio;
233 uint32_t i2c_speed_in_khz;
234 uint32_t i2c_speed_in_khz_hdcp;
235 uint32_t dmdata_alloc_size;
236 unsigned int max_cursor_size;
237 unsigned int max_video_width;
238 /*
239 * max video plane width that can be safely assumed to be always
240 * supported by single DPP pipe.
241 */
242 unsigned int max_optimizable_video_width;
243 unsigned int min_horizontal_blanking_period;
244 int linear_pitch_alignment;
245 bool dcc_const_color;
246 bool dynamic_audio;
247 bool is_apu;
248 bool dual_link_dvi;
249 bool post_blend_color_processing;
250 bool force_dp_tps4_for_cp2520;
251 bool disable_dp_clk_share;
252 bool psp_setup_panel_mode;
253 bool extended_aux_timeout_support;
254 bool dmcub_support;
255 bool zstate_support;
256 bool ips_support;
257 uint32_t num_of_internal_disp;
258 enum dp_protocol_version max_dp_protocol_version;
259 unsigned int mall_size_per_mem_channel;
260 unsigned int mall_size_total;
261 unsigned int cursor_cache_size;
262 struct dc_plane_cap planes[MAX_PLANES];
263 struct dc_color_caps color;
264 struct dc_dmub_caps dmub_caps;
265 bool dp_hpo;
266 bool dp_hdmi21_pcon_support;
267 bool edp_dsc_support;
268 bool vbios_lttpr_aware;
269 bool vbios_lttpr_enable;
270 uint32_t max_otg_num;
271 uint32_t max_cab_allocation_bytes;
272 uint32_t cache_line_size;
273 uint32_t cache_num_ways;
274 uint16_t subvp_fw_processing_delay_us;
275 uint8_t subvp_drr_max_vblank_margin_us;
276 uint16_t subvp_prefetch_end_to_mall_start_us;
277 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
278 uint16_t subvp_pstate_allow_width_us;
279 uint16_t subvp_vertical_int_margin_us;
280 bool seamless_odm;
281 uint32_t max_v_total;
282 uint32_t max_disp_clock_khz_at_vmin;
283 uint8_t subvp_drr_vblank_start_margin_us;
284};
285
286struct dc_bug_wa {
287 bool no_connect_phy_config;
288 bool dedcn20_305_wa;
289 bool skip_clock_update;
290 bool lt_early_cr_pattern;
291 struct {
292 uint8_t uclk : 1;
293 uint8_t fclk : 1;
294 uint8_t dcfclk : 1;
295 uint8_t dcfclk_ds: 1;
296 } clock_update_disable_mask;
297};
298struct dc_dcc_surface_param {
299 struct dc_size surface_size;
300 enum surface_pixel_format format;
301 enum swizzle_mode_values swizzle_mode;
302 enum dc_scan_direction scan;
303};
304
305struct dc_dcc_setting {
306 unsigned int max_compressed_blk_size;
307 unsigned int max_uncompressed_blk_size;
308 bool independent_64b_blks;
309 //These bitfields to be used starting with DCN
310 struct {
311 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
312 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN
313 uint32_t dcc_256_128_128 : 1; //available starting with DCN
314 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN (the best compression case)
315 } dcc_controls;
316};
317
318struct dc_surface_dcc_cap {
319 union {
320 struct {
321 struct dc_dcc_setting rgb;
322 } grph;
323
324 struct {
325 struct dc_dcc_setting luma;
326 struct dc_dcc_setting chroma;
327 } video;
328 };
329
330 bool capable;
331 bool const_color_support;
332};
333
334struct dc_static_screen_params {
335 struct {
336 bool force_trigger;
337 bool cursor_update;
338 bool surface_update;
339 bool overlay_update;
340 } triggers;
341 unsigned int num_frames;
342};
343
344
345/* Surface update type is used by dc_update_surfaces_and_stream
346 * The update type is determined at the very beginning of the function based
347 * on parameters passed in and decides how much programming (or updating) is
348 * going to be done during the call.
349 *
350 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
351 * logical calculations or hardware register programming. This update MUST be
352 * ISR safe on windows. Currently fast update will only be used to flip surface
353 * address.
354 *
355 * UPDATE_TYPE_MED is used for slower updates which require significant hw
356 * re-programming however do not affect bandwidth consumption or clock
357 * requirements. At present, this is the level at which front end updates
358 * that do not require us to run bw_calcs happen. These are in/out transfer func
359 * updates, viewport offset changes, recout size changes and pixel depth changes.
360 * This update can be done at ISR, but we want to minimize how often this happens.
361 *
362 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
363 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
364 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
365 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
366 * a full update. This cannot be done at ISR level and should be a rare event.
367 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
368 * underscan we don't expect to see this call at all.
369 */
370
371enum surface_update_type {
372 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
373 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
374 UPDATE_TYPE_FULL, /* may need to shuffle resources */
375};
376
377/* Forward declaration*/
378struct dc;
379struct dc_plane_state;
380struct dc_state;
381
382
383struct dc_cap_funcs {
384 bool (*get_dcc_compression_cap)(const struct dc *dc,
385 const struct dc_dcc_surface_param *input,
386 struct dc_surface_dcc_cap *output);
387 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
388};
389
390struct link_training_settings;
391
392union allow_lttpr_non_transparent_mode {
393 struct {
394 bool DP1_4A : 1;
395 bool DP2_0 : 1;
396 } bits;
397 unsigned char raw;
398};
399
400/* Structure to hold configuration flags set by dm at dc creation. */
401struct dc_config {
402 bool gpu_vm_support;
403 bool disable_disp_pll_sharing;
404 bool fbc_support;
405 bool disable_fractional_pwm;
406 bool allow_seamless_boot_optimization;
407 bool seamless_boot_edp_requested;
408 bool edp_not_connected;
409 bool edp_no_power_sequencing;
410 bool force_enum_edp;
411 bool forced_clocks;
412 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
413 bool multi_mon_pp_mclk_switch;
414 bool disable_dmcu;
415 bool enable_4to1MPC;
416 bool enable_windowed_mpo_odm;
417 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
418 uint32_t allow_edp_hotplug_detection;
419 bool clamp_min_dcfclk;
420 uint64_t vblank_alignment_dto_params;
421 uint8_t vblank_alignment_max_frame_time_diff;
422 bool is_asymmetric_memory;
423 bool is_single_rank_dimm;
424 bool is_vmin_only_asic;
425 bool use_pipe_ctx_sync_logic;
426 bool ignore_dpref_ss;
427 bool enable_mipi_converter_optimization;
428 bool use_default_clock_table;
429 bool force_bios_enable_lttpr;
430 uint8_t force_bios_fixed_vs;
431 int sdpif_request_limit_words_per_umc;
432 bool use_old_fixed_vs_sequence;
433 bool dc_mode_clk_limit_support;
434 bool EnableMinDispClkODM;
435 bool enable_auto_dpm_test_logs;
436 unsigned int disable_ips;
437 unsigned int disable_ips_in_vpb;
438};
439
440enum visual_confirm {
441 VISUAL_CONFIRM_DISABLE = 0,
442 VISUAL_CONFIRM_SURFACE = 1,
443 VISUAL_CONFIRM_HDR = 2,
444 VISUAL_CONFIRM_MPCTREE = 4,
445 VISUAL_CONFIRM_PSR = 5,
446 VISUAL_CONFIRM_SWAPCHAIN = 6,
447 VISUAL_CONFIRM_FAMS = 7,
448 VISUAL_CONFIRM_SWIZZLE = 9,
449 VISUAL_CONFIRM_REPLAY = 12,
450 VISUAL_CONFIRM_SUBVP = 14,
451 VISUAL_CONFIRM_MCLK_SWITCH = 16,
452};
453
454enum dc_psr_power_opts {
455 psr_power_opt_invalid = 0x0,
456 psr_power_opt_smu_opt_static_screen = 0x1,
457 psr_power_opt_z10_static_screen = 0x10,
458 psr_power_opt_ds_disable_allow = 0x100,
459};
460
461enum dml_hostvm_override_opts {
462 DML_HOSTVM_NO_OVERRIDE = 0x0,
463 DML_HOSTVM_OVERRIDE_FALSE = 0x1,
464 DML_HOSTVM_OVERRIDE_TRUE = 0x2,
465};
466
467enum dc_replay_power_opts {
468 replay_power_opt_invalid = 0x0,
469 replay_power_opt_smu_opt_static_screen = 0x1,
470 replay_power_opt_z10_static_screen = 0x10,
471};
472
473enum dcc_option {
474 DCC_ENABLE = 0,
475 DCC_DISABLE = 1,
476 DCC_HALF_REQ_DISALBE = 2,
477};
478
479/**
480 * enum pipe_split_policy - Pipe split strategy supported by DCN
481 *
482 * This enum is used to define the pipe split policy supported by DCN. By
483 * default, DC favors MPC_SPLIT_DYNAMIC.
484 */
485enum pipe_split_policy {
486 /**
487 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
488 * pipe in order to bring the best trade-off between performance and
489 * power consumption. This is the recommended option.
490 */
491 MPC_SPLIT_DYNAMIC = 0,
492
493 /**
494 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
495 * try any sort of split optimization.
496 */
497 MPC_SPLIT_AVOID = 1,
498
499 /**
500 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
501 * optimize the pipe utilization when using a single display; if the
502 * user connects to a second display, DC will avoid pipe split.
503 */
504 MPC_SPLIT_AVOID_MULT_DISP = 2,
505};
506
507enum wm_report_mode {
508 WM_REPORT_DEFAULT = 0,
509 WM_REPORT_OVERRIDE = 1,
510};
511enum dtm_pstate{
512 dtm_level_p0 = 0,/*highest voltage*/
513 dtm_level_p1,
514 dtm_level_p2,
515 dtm_level_p3,
516 dtm_level_p4,/*when active_display_count = 0*/
517};
518
519enum dcn_pwr_state {
520 DCN_PWR_STATE_UNKNOWN = -1,
521 DCN_PWR_STATE_MISSION_MODE = 0,
522 DCN_PWR_STATE_LOW_POWER = 3,
523};
524
525enum dcn_zstate_support_state {
526 DCN_ZSTATE_SUPPORT_UNKNOWN,
527 DCN_ZSTATE_SUPPORT_ALLOW,
528 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
529 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
530 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
531 DCN_ZSTATE_SUPPORT_DISALLOW,
532};
533
534/*
535 * struct dc_clocks - DC pipe clocks
536 *
537 * For any clocks that may differ per pipe only the max is stored in this
538 * structure
539 */
540struct dc_clocks {
541 int dispclk_khz;
542 int actual_dispclk_khz;
543 int dppclk_khz;
544 int actual_dppclk_khz;
545 int disp_dpp_voltage_level_khz;
546 int dcfclk_khz;
547 int socclk_khz;
548 int dcfclk_deep_sleep_khz;
549 int fclk_khz;
550 int phyclk_khz;
551 int dramclk_khz;
552 bool p_state_change_support;
553 enum dcn_zstate_support_state zstate_support;
554 bool dtbclk_en;
555 int ref_dtbclk_khz;
556 bool fclk_p_state_change_support;
557 enum dcn_pwr_state pwr_state;
558 /*
559 * Elements below are not compared for the purposes of
560 * optimization required
561 */
562 bool prev_p_state_change_support;
563 bool fclk_prev_p_state_change_support;
564 int num_ways;
565
566 /*
567 * @fw_based_mclk_switching
568 *
569 * DC has a mechanism that leverage the variable refresh rate to switch
570 * memory clock in cases that we have a large latency to achieve the
571 * memory clock change and a short vblank window. DC has some
572 * requirements to enable this feature, and this field describes if the
573 * system support or not such a feature.
574 */
575 bool fw_based_mclk_switching;
576 bool fw_based_mclk_switching_shut_down;
577 int prev_num_ways;
578 enum dtm_pstate dtm_level;
579 int max_supported_dppclk_khz;
580 int max_supported_dispclk_khz;
581 int bw_dppclk_khz; /*a copy of dppclk_khz*/
582 int bw_dispclk_khz;
583};
584
585struct dc_bw_validation_profile {
586 bool enable;
587
588 unsigned long long total_ticks;
589 unsigned long long voltage_level_ticks;
590 unsigned long long watermark_ticks;
591 unsigned long long rq_dlg_ticks;
592
593 unsigned long long total_count;
594 unsigned long long skip_fast_count;
595 unsigned long long skip_pass_count;
596 unsigned long long skip_fail_count;
597};
598
599#define BW_VAL_TRACE_SETUP() \
600 unsigned long long end_tick = 0; \
601 unsigned long long voltage_level_tick = 0; \
602 unsigned long long watermark_tick = 0; \
603 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
604 dm_get_timestamp(dc->ctx) : 0
605
606#define BW_VAL_TRACE_COUNT() \
607 if (dc->debug.bw_val_profile.enable) \
608 dc->debug.bw_val_profile.total_count++
609
610#define BW_VAL_TRACE_SKIP(status) \
611 if (dc->debug.bw_val_profile.enable) { \
612 if (!voltage_level_tick) \
613 voltage_level_tick = dm_get_timestamp(dc->ctx); \
614 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
615 }
616
617#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
618 if (dc->debug.bw_val_profile.enable) \
619 voltage_level_tick = dm_get_timestamp(dc->ctx)
620
621#define BW_VAL_TRACE_END_WATERMARKS() \
622 if (dc->debug.bw_val_profile.enable) \
623 watermark_tick = dm_get_timestamp(dc->ctx)
624
625#define BW_VAL_TRACE_FINISH() \
626 if (dc->debug.bw_val_profile.enable) { \
627 end_tick = dm_get_timestamp(dc->ctx); \
628 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
629 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
630 if (watermark_tick) { \
631 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
632 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
633 } \
634 }
635
636union mem_low_power_enable_options {
637 struct {
638 bool vga: 1;
639 bool i2c: 1;
640 bool dmcu: 1;
641 bool dscl: 1;
642 bool cm: 1;
643 bool mpc: 1;
644 bool optc: 1;
645 bool vpg: 1;
646 bool afmt: 1;
647 } bits;
648 uint32_t u32All;
649};
650
651union root_clock_optimization_options {
652 struct {
653 bool dpp: 1;
654 bool dsc: 1;
655 bool hdmistream: 1;
656 bool hdmichar: 1;
657 bool dpstream: 1;
658 bool symclk32_se: 1;
659 bool symclk32_le: 1;
660 bool symclk_fe: 1;
661 bool physymclk: 1;
662 bool dpiasymclk: 1;
663 uint32_t reserved: 22;
664 } bits;
665 uint32_t u32All;
666};
667
668union fine_grain_clock_gating_enable_options {
669 struct {
670 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
671 bool dchub : 1; /* Display controller hub */
672 bool dchubbub : 1;
673 bool dpp : 1; /* Display pipes and planes */
674 bool opp : 1; /* Output pixel processing */
675 bool optc : 1; /* Output pipe timing combiner */
676 bool dio : 1; /* Display output */
677 bool dwb : 1; /* Display writeback */
678 bool mmhubbub : 1; /* Multimedia hub */
679 bool dmu : 1; /* Display core management unit */
680 bool az : 1; /* Azalia */
681 bool dchvm : 1;
682 bool dsc : 1; /* Display stream compression */
683
684 uint32_t reserved : 19;
685 } bits;
686 uint32_t u32All;
687};
688
689enum pg_hw_pipe_resources {
690 PG_HUBP = 0,
691 PG_DPP,
692 PG_DSC,
693 PG_MPCC,
694 PG_OPP,
695 PG_OPTC,
696 PG_HW_PIPE_RESOURCES_NUM_ELEMENT
697};
698
699enum pg_hw_resources {
700 PG_DCCG = 0,
701 PG_DCIO,
702 PG_DIO,
703 PG_DCHUBBUB,
704 PG_DCHVM,
705 PG_DWB,
706 PG_HPO,
707 PG_HW_RESOURCES_NUM_ELEMENT
708};
709
710struct pg_block_update {
711 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
712 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
713};
714
715union dpia_debug_options {
716 struct {
717 uint32_t disable_dpia:1; /* bit 0 */
718 uint32_t force_non_lttpr:1; /* bit 1 */
719 uint32_t extend_aux_rd_interval:1; /* bit 2 */
720 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
721 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
722 uint32_t reserved:27;
723 } bits;
724 uint32_t raw;
725};
726
727/* AUX wake work around options
728 * 0: enable/disable work around
729 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
730 * 15-2: reserved
731 * 31-16: timeout in ms
732 */
733union aux_wake_wa_options {
734 struct {
735 uint32_t enable_wa : 1;
736 uint32_t use_default_timeout : 1;
737 uint32_t rsvd: 14;
738 uint32_t timeout_ms : 16;
739 } bits;
740 uint32_t raw;
741};
742
743struct dc_debug_data {
744 uint32_t ltFailCount;
745 uint32_t i2cErrorCount;
746 uint32_t auxErrorCount;
747};
748
749struct dc_phy_addr_space_config {
750 struct {
751 uint64_t start_addr;
752 uint64_t end_addr;
753 uint64_t fb_top;
754 uint64_t fb_offset;
755 uint64_t fb_base;
756 uint64_t agp_top;
757 uint64_t agp_bot;
758 uint64_t agp_base;
759 } system_aperture;
760
761 struct {
762 uint64_t page_table_start_addr;
763 uint64_t page_table_end_addr;
764 uint64_t page_table_base_addr;
765 bool base_addr_is_mc_addr;
766 } gart_config;
767
768 bool valid;
769 bool is_hvm_enabled;
770 uint64_t page_table_default_page_addr;
771};
772
773struct dc_virtual_addr_space_config {
774 uint64_t page_table_base_addr;
775 uint64_t page_table_start_addr;
776 uint64_t page_table_end_addr;
777 uint32_t page_table_block_size_in_bytes;
778 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
779};
780
781struct dc_bounding_box_overrides {
782 int sr_exit_time_ns;
783 int sr_enter_plus_exit_time_ns;
784 int sr_exit_z8_time_ns;
785 int sr_enter_plus_exit_z8_time_ns;
786 int urgent_latency_ns;
787 int percent_of_ideal_drambw;
788 int dram_clock_change_latency_ns;
789 int dummy_clock_change_latency_ns;
790 int fclk_clock_change_latency_ns;
791 /* This forces a hard min on the DCFCLK we use
792 * for DML. Unlike the debug option for forcing
793 * DCFCLK, this override affects watermark calculations
794 */
795 int min_dcfclk_mhz;
796};
797
798struct dc_state;
799struct resource_pool;
800struct dce_hwseq;
801struct link_service;
802
803/*
804 * struct dc_debug_options - DC debug struct
805 *
806 * This struct provides a simple mechanism for developers to change some
807 * configurations, enable/disable features, and activate extra debug options.
808 * This can be very handy to narrow down whether some specific feature is
809 * causing an issue or not.
810 */
811struct dc_debug_options {
812 bool native422_support;
813 bool disable_dsc;
814 enum visual_confirm visual_confirm;
815 int visual_confirm_rect_height;
816
817 bool sanity_checks;
818 bool max_disp_clk;
819 bool surface_trace;
820 bool timing_trace;
821 bool clock_trace;
822 bool validation_trace;
823 bool bandwidth_calcs_trace;
824 int max_downscale_src_width;
825
826 /* stutter efficiency related */
827 bool disable_stutter;
828 bool use_max_lb;
829 enum dcc_option disable_dcc;
830
831 /*
832 * @pipe_split_policy: Define which pipe split policy is used by the
833 * display core.
834 */
835 enum pipe_split_policy pipe_split_policy;
836 bool force_single_disp_pipe_split;
837 bool voltage_align_fclk;
838 bool disable_min_fclk;
839
840 bool disable_dfs_bypass;
841 bool disable_dpp_power_gate;
842 bool disable_hubp_power_gate;
843 bool disable_dsc_power_gate;
844 bool disable_optc_power_gate;
845 bool disable_hpo_power_gate;
846 int dsc_min_slice_height_override;
847 int dsc_bpp_increment_div;
848 bool disable_pplib_wm_range;
849 enum wm_report_mode pplib_wm_report_mode;
850 unsigned int min_disp_clk_khz;
851 unsigned int min_dpp_clk_khz;
852 unsigned int min_dram_clk_khz;
853 int sr_exit_time_dpm0_ns;
854 int sr_enter_plus_exit_time_dpm0_ns;
855 int sr_exit_time_ns;
856 int sr_enter_plus_exit_time_ns;
857 int sr_exit_z8_time_ns;
858 int sr_enter_plus_exit_z8_time_ns;
859 int urgent_latency_ns;
860 uint32_t underflow_assert_delay_us;
861 int percent_of_ideal_drambw;
862 int dram_clock_change_latency_ns;
863 bool optimized_watermark;
864 int always_scale;
865 bool disable_pplib_clock_request;
866 bool disable_clock_gate;
867 bool disable_mem_low_power;
868 bool pstate_enabled;
869 bool disable_dmcu;
870 bool force_abm_enable;
871 bool disable_stereo_support;
872 bool vsr_support;
873 bool performance_trace;
874 bool az_endpoint_mute_only;
875 bool always_use_regamma;
876 bool recovery_enabled;
877 bool avoid_vbios_exec_table;
878 bool scl_reset_length10;
879 bool hdmi20_disable;
880 bool skip_detection_link_training;
881 uint32_t edid_read_retry_times;
882 unsigned int force_odm_combine; //bit vector based on otg inst
883 unsigned int seamless_boot_odm_combine;
884 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
885 int minimum_z8_residency_time;
886 int minimum_z10_residency_time;
887 bool disable_z9_mpc;
888 unsigned int force_fclk_khz;
889 bool enable_tri_buf;
890 bool dmub_offload_enabled;
891 bool dmcub_emulation;
892 bool disable_idle_power_optimizations;
893 unsigned int mall_size_override;
894 unsigned int mall_additional_timer_percent;
895 bool mall_error_as_fatal;
896 bool dmub_command_table; /* for testing only */
897 struct dc_bw_validation_profile bw_val_profile;
898 bool disable_fec;
899 bool disable_48mhz_pwrdwn;
900 /* This forces a hard min on the DCFCLK requested to SMU/PP
901 * watermarks are not affected.
902 */
903 unsigned int force_min_dcfclk_mhz;
904 int dwb_fi_phase;
905 bool disable_timing_sync;
906 bool cm_in_bypass;
907 int force_clock_mode;/*every mode change.*/
908
909 bool disable_dram_clock_change_vactive_support;
910 bool validate_dml_output;
911 bool enable_dmcub_surface_flip;
912 bool usbc_combo_phy_reset_wa;
913 bool enable_dram_clock_change_one_display_vactive;
914 /* TODO - remove once tested */
915 bool legacy_dp2_lt;
916 bool set_mst_en_for_sst;
917 bool disable_uhbr;
918 bool force_dp2_lt_fallback_method;
919 bool ignore_cable_id;
920 union mem_low_power_enable_options enable_mem_low_power;
921 union root_clock_optimization_options root_clock_optimization;
922 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
923 bool hpo_optimization;
924 bool force_vblank_alignment;
925
926 /* Enable dmub aux for legacy ddc */
927 bool enable_dmub_aux_for_legacy_ddc;
928 bool disable_fams;
929 bool disable_fams_gaming;
930 /* FEC/PSR1 sequence enable delay in 100us */
931 uint8_t fec_enable_delay_in100us;
932 bool enable_driver_sequence_debug;
933 enum det_size crb_alloc_policy;
934 int crb_alloc_policy_min_disp_count;
935 bool disable_z10;
936 bool enable_z9_disable_interface;
937 bool psr_skip_crtc_disable;
938 union dpia_debug_options dpia_debug;
939 bool disable_fixed_vs_aux_timeout_wa;
940 uint32_t fixed_vs_aux_delay_config_wa;
941 bool force_disable_subvp;
942 bool force_subvp_mclk_switch;
943 bool allow_sw_cursor_fallback;
944 unsigned int force_subvp_num_ways;
945 unsigned int force_mall_ss_num_ways;
946 bool alloc_extra_way_for_cursor;
947 uint32_t subvp_extra_lines;
948 bool force_usr_allow;
949 /* uses value at boot and disables switch */
950 bool disable_dtb_ref_clk_switch;
951 bool extended_blank_optimization;
952 union aux_wake_wa_options aux_wake_wa;
953 uint32_t mst_start_top_delay;
954 uint8_t psr_power_use_phy_fsm;
955 enum dml_hostvm_override_opts dml_hostvm_override;
956 bool dml_disallow_alternate_prefetch_modes;
957 bool use_legacy_soc_bb_mechanism;
958 bool exit_idle_opt_for_cursor_updates;
959 bool using_dml2;
960 bool enable_single_display_2to1_odm_policy;
961 bool enable_double_buffered_dsc_pg_support;
962 bool enable_dp_dig_pixel_rate_div_policy;
963 enum lttpr_mode lttpr_mode_override;
964 unsigned int dsc_delay_factor_wa_x1000;
965 unsigned int min_prefetch_in_strobe_ns;
966 bool disable_unbounded_requesting;
967 bool dig_fifo_off_in_blank;
968 bool override_dispclk_programming;
969 bool otg_crc_db;
970 bool disallow_dispclk_dppclk_ds;
971 bool disable_fpo_optimizations;
972 bool support_eDP1_5;
973 uint32_t fpo_vactive_margin_us;
974 bool disable_fpo_vactive;
975 bool disable_boot_optimizations;
976 bool override_odm_optimization;
977 bool minimize_dispclk_using_odm;
978 bool disable_subvp_high_refresh;
979 bool disable_dp_plus_plus_wa;
980 uint32_t fpo_vactive_min_active_margin_us;
981 uint32_t fpo_vactive_max_blank_us;
982 bool enable_hpo_pg_support;
983 bool enable_legacy_fast_update;
984 bool disable_dc_mode_overwrite;
985 bool replay_skip_crtc_disabled;
986 bool ignore_pg;/*do nothing, let pmfw control it*/
987 bool psp_disabled_wa;
988 unsigned int ips2_eval_delay_us;
989 unsigned int ips2_entry_delay_us;
990 bool disable_timeout;
991 bool disable_extblankadj;
992 unsigned int static_screen_wait_frames;
993};
994
995struct gpu_info_soc_bounding_box_v1_0;
996
997/* Generic structure that can be used to query properties of DC. More fields
998 * can be added as required.
999 */
1000struct dc_current_properties {
1001 unsigned int cursor_size_limit;
1002};
1003
1004struct dc {
1005 struct dc_debug_options debug;
1006 struct dc_versions versions;
1007 struct dc_caps caps;
1008 struct dc_cap_funcs cap_funcs;
1009 struct dc_config config;
1010 struct dc_bounding_box_overrides bb_overrides;
1011 struct dc_bug_wa work_arounds;
1012 struct dc_context *ctx;
1013 struct dc_phy_addr_space_config vm_pa_config;
1014
1015 uint8_t link_count;
1016 struct dc_link *links[MAX_PIPES * 2];
1017 struct link_service *link_srv;
1018
1019 struct dc_state *current_state;
1020 struct resource_pool *res_pool;
1021
1022 struct clk_mgr *clk_mgr;
1023
1024 /* Display Engine Clock levels */
1025 struct dm_pp_clock_levels sclk_lvls;
1026
1027 /* Inputs into BW and WM calculations. */
1028 struct bw_calcs_dceip *bw_dceip;
1029 struct bw_calcs_vbios *bw_vbios;
1030 struct dcn_soc_bounding_box *dcn_soc;
1031 struct dcn_ip_params *dcn_ip;
1032 struct display_mode_lib dml;
1033
1034 /* HW functions */
1035 struct hw_sequencer_funcs hwss;
1036 struct dce_hwseq *hwseq;
1037
1038 /* Require to optimize clocks and bandwidth for added/removed planes */
1039 bool optimized_required;
1040 bool wm_optimized_required;
1041 bool idle_optimizations_allowed;
1042 bool enable_c20_dtm_b0;
1043
1044 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
1045
1046 /* FBC compressor */
1047 struct compressor *fbc_compressor;
1048
1049 struct dc_debug_data debug_data;
1050 struct dpcd_vendor_signature vendor_signature;
1051
1052 const char *build_id;
1053 struct vm_helper *vm_helper;
1054
1055 uint32_t *dcn_reg_offsets;
1056 uint32_t *nbio_reg_offsets;
1057 uint32_t *clk_reg_offsets;
1058
1059 /* Scratch memory */
1060 struct {
1061 struct {
1062 /*
1063 * For matching clock_limits table in driver with table
1064 * from PMFW.
1065 */
1066 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1067 } update_bw_bounding_box;
1068 } scratch;
1069
1070 struct dml2_configuration_options dml2_options;
1071};
1072
1073enum frame_buffer_mode {
1074 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
1075 FRAME_BUFFER_MODE_ZFB_ONLY,
1076 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
1077} ;
1078
1079struct dchub_init_data {
1080 int64_t zfb_phys_addr_base;
1081 int64_t zfb_mc_base_addr;
1082 uint64_t zfb_size_in_byte;
1083 enum frame_buffer_mode fb_mode;
1084 bool dchub_initialzied;
1085 bool dchub_info_valid;
1086};
1087
1088struct dc_init_data {
1089 struct hw_asic_id asic_id;
1090 void *driver; /* ctx */
1091 struct cgs_device *cgs_device;
1092 struct dc_bounding_box_overrides bb_overrides;
1093
1094 int num_virtual_links;
1095 /*
1096 * If 'vbios_override' not NULL, it will be called instead
1097 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1098 */
1099 struct dc_bios *vbios_override;
1100 enum dce_environment dce_environment;
1101
1102 struct dmub_offload_funcs *dmub_if;
1103 struct dc_reg_helper_state *dmub_offload;
1104
1105 struct dc_config flags;
1106 uint64_t log_mask;
1107
1108 struct dpcd_vendor_signature vendor_signature;
1109 bool force_smu_not_present;
1110 /*
1111 * IP offset for run time initializaion of register addresses
1112 *
1113 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1114 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1115 * before them.
1116 */
1117 uint32_t *dcn_reg_offsets;
1118 uint32_t *nbio_reg_offsets;
1119 uint32_t *clk_reg_offsets;
1120};
1121
1122struct dc_callback_init {
1123 struct cp_psp cp_psp;
1124};
1125
1126struct dc *dc_create(const struct dc_init_data *init_params);
1127void dc_hardware_init(struct dc *dc);
1128
1129int dc_get_vmid_use_vector(struct dc *dc);
1130void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1131/* Returns the number of vmids supported */
1132int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1133void dc_init_callbacks(struct dc *dc,
1134 const struct dc_callback_init *init_params);
1135void dc_deinit_callbacks(struct dc *dc);
1136void dc_destroy(struct dc **dc);
1137
1138/* Surface Interfaces */
1139
1140enum {
1141 TRANSFER_FUNC_POINTS = 1025
1142};
1143
1144struct dc_hdr_static_metadata {
1145 /* display chromaticities and white point in units of 0.00001 */
1146 unsigned int chromaticity_green_x;
1147 unsigned int chromaticity_green_y;
1148 unsigned int chromaticity_blue_x;
1149 unsigned int chromaticity_blue_y;
1150 unsigned int chromaticity_red_x;
1151 unsigned int chromaticity_red_y;
1152 unsigned int chromaticity_white_point_x;
1153 unsigned int chromaticity_white_point_y;
1154
1155 uint32_t min_luminance;
1156 uint32_t max_luminance;
1157 uint32_t maximum_content_light_level;
1158 uint32_t maximum_frame_average_light_level;
1159};
1160
1161enum dc_transfer_func_type {
1162 TF_TYPE_PREDEFINED,
1163 TF_TYPE_DISTRIBUTED_POINTS,
1164 TF_TYPE_BYPASS,
1165 TF_TYPE_HWPWL
1166};
1167
1168struct dc_transfer_func_distributed_points {
1169 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1170 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1171 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1172
1173 uint16_t end_exponent;
1174 uint16_t x_point_at_y1_red;
1175 uint16_t x_point_at_y1_green;
1176 uint16_t x_point_at_y1_blue;
1177};
1178
1179enum dc_transfer_func_predefined {
1180 TRANSFER_FUNCTION_SRGB,
1181 TRANSFER_FUNCTION_BT709,
1182 TRANSFER_FUNCTION_PQ,
1183 TRANSFER_FUNCTION_LINEAR,
1184 TRANSFER_FUNCTION_UNITY,
1185 TRANSFER_FUNCTION_HLG,
1186 TRANSFER_FUNCTION_HLG12,
1187 TRANSFER_FUNCTION_GAMMA22,
1188 TRANSFER_FUNCTION_GAMMA24,
1189 TRANSFER_FUNCTION_GAMMA26
1190};
1191
1192
1193struct dc_transfer_func {
1194 struct kref refcount;
1195 enum dc_transfer_func_type type;
1196 enum dc_transfer_func_predefined tf;
1197 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1198 uint32_t sdr_ref_white_level;
1199 union {
1200 struct pwl_params pwl;
1201 struct dc_transfer_func_distributed_points tf_pts;
1202 };
1203};
1204
1205
1206union dc_3dlut_state {
1207 struct {
1208 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1209 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1210 uint32_t rmu_mux_num:3; /*index of mux to use*/
1211 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1212 uint32_t mpc_rmu1_mux:4;
1213 uint32_t mpc_rmu2_mux:4;
1214 uint32_t reserved:15;
1215 } bits;
1216 uint32_t raw;
1217};
1218
1219
1220struct dc_3dlut {
1221 struct kref refcount;
1222 struct tetrahedral_params lut_3d;
1223 struct fixed31_32 hdr_multiplier;
1224 union dc_3dlut_state state;
1225};
1226/*
1227 * This structure is filled in by dc_surface_get_status and contains
1228 * the last requested address and the currently active address so the called
1229 * can determine if there are any outstanding flips
1230 */
1231struct dc_plane_status {
1232 struct dc_plane_address requested_address;
1233 struct dc_plane_address current_address;
1234 bool is_flip_pending;
1235 bool is_right_eye;
1236};
1237
1238union surface_update_flags {
1239
1240 struct {
1241 uint32_t addr_update:1;
1242 /* Medium updates */
1243 uint32_t dcc_change:1;
1244 uint32_t color_space_change:1;
1245 uint32_t horizontal_mirror_change:1;
1246 uint32_t per_pixel_alpha_change:1;
1247 uint32_t global_alpha_change:1;
1248 uint32_t hdr_mult:1;
1249 uint32_t rotation_change:1;
1250 uint32_t swizzle_change:1;
1251 uint32_t scaling_change:1;
1252 uint32_t position_change:1;
1253 uint32_t in_transfer_func_change:1;
1254 uint32_t input_csc_change:1;
1255 uint32_t coeff_reduction_change:1;
1256 uint32_t output_tf_change:1;
1257 uint32_t pixel_format_change:1;
1258 uint32_t plane_size_change:1;
1259 uint32_t gamut_remap_change:1;
1260
1261 /* Full updates */
1262 uint32_t new_plane:1;
1263 uint32_t bpp_change:1;
1264 uint32_t gamma_change:1;
1265 uint32_t bandwidth_change:1;
1266 uint32_t clock_change:1;
1267 uint32_t stereo_format_change:1;
1268 uint32_t lut_3d:1;
1269 uint32_t tmz_changed:1;
1270 uint32_t full_update:1;
1271 } bits;
1272
1273 uint32_t raw;
1274};
1275
1276struct dc_plane_state {
1277 struct dc_plane_address address;
1278 struct dc_plane_flip_time time;
1279 bool triplebuffer_flips;
1280 struct scaling_taps scaling_quality;
1281 struct rect src_rect;
1282 struct rect dst_rect;
1283 struct rect clip_rect;
1284
1285 struct plane_size plane_size;
1286 union dc_tiling_info tiling_info;
1287
1288 struct dc_plane_dcc_param dcc;
1289
1290 struct dc_gamma *gamma_correction;
1291 struct dc_transfer_func *in_transfer_func;
1292 struct dc_bias_and_scale *bias_and_scale;
1293 struct dc_csc_transform input_csc_color_matrix;
1294 struct fixed31_32 coeff_reduction_factor;
1295 struct fixed31_32 hdr_mult;
1296 struct colorspace_transform gamut_remap_matrix;
1297
1298 // TODO: No longer used, remove
1299 struct dc_hdr_static_metadata hdr_static_ctx;
1300
1301 enum dc_color_space color_space;
1302
1303 struct dc_3dlut *lut3d_func;
1304 struct dc_transfer_func *in_shaper_func;
1305 struct dc_transfer_func *blend_tf;
1306
1307 struct dc_transfer_func *gamcor_tf;
1308 enum surface_pixel_format format;
1309 enum dc_rotation_angle rotation;
1310 enum plane_stereo_format stereo_format;
1311
1312 bool is_tiling_rotated;
1313 bool per_pixel_alpha;
1314 bool pre_multiplied_alpha;
1315 bool global_alpha;
1316 int global_alpha_value;
1317 bool visible;
1318 bool flip_immediate;
1319 bool horizontal_mirror;
1320 int layer_index;
1321
1322 union surface_update_flags update_flags;
1323 bool flip_int_enabled;
1324 bool skip_manual_trigger;
1325
1326 /* private to DC core */
1327 struct dc_plane_status status;
1328 struct dc_context *ctx;
1329
1330 /* HACK: Workaround for forcing full reprogramming under some conditions */
1331 bool force_full_update;
1332
1333 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1334
1335 /* private to dc_surface.c */
1336 enum dc_irq_source irq_source;
1337 struct kref refcount;
1338 struct tg_color visual_confirm_color;
1339
1340 bool is_statically_allocated;
1341};
1342
1343struct dc_plane_info {
1344 struct plane_size plane_size;
1345 union dc_tiling_info tiling_info;
1346 struct dc_plane_dcc_param dcc;
1347 enum surface_pixel_format format;
1348 enum dc_rotation_angle rotation;
1349 enum plane_stereo_format stereo_format;
1350 enum dc_color_space color_space;
1351 bool horizontal_mirror;
1352 bool visible;
1353 bool per_pixel_alpha;
1354 bool pre_multiplied_alpha;
1355 bool global_alpha;
1356 int global_alpha_value;
1357 bool input_csc_enabled;
1358 int layer_index;
1359};
1360
1361struct dc_scaling_info {
1362 struct rect src_rect;
1363 struct rect dst_rect;
1364 struct rect clip_rect;
1365 struct scaling_taps scaling_quality;
1366};
1367
1368struct dc_fast_update {
1369 const struct dc_flip_addrs *flip_addr;
1370 const struct dc_gamma *gamma;
1371 const struct colorspace_transform *gamut_remap_matrix;
1372 const struct dc_csc_transform *input_csc_color_matrix;
1373 const struct fixed31_32 *coeff_reduction_factor;
1374 struct dc_transfer_func *out_transfer_func;
1375 struct dc_csc_transform *output_csc_transform;
1376};
1377
1378struct dc_surface_update {
1379 struct dc_plane_state *surface;
1380
1381 /* isr safe update parameters. null means no updates */
1382 const struct dc_flip_addrs *flip_addr;
1383 const struct dc_plane_info *plane_info;
1384 const struct dc_scaling_info *scaling_info;
1385 struct fixed31_32 hdr_mult;
1386 /* following updates require alloc/sleep/spin that is not isr safe,
1387 * null means no updates
1388 */
1389 const struct dc_gamma *gamma;
1390 const struct dc_transfer_func *in_transfer_func;
1391
1392 const struct dc_csc_transform *input_csc_color_matrix;
1393 const struct fixed31_32 *coeff_reduction_factor;
1394 const struct dc_transfer_func *func_shaper;
1395 const struct dc_3dlut *lut3d_func;
1396 const struct dc_transfer_func *blend_tf;
1397 const struct colorspace_transform *gamut_remap_matrix;
1398};
1399
1400/*
1401 * Create a new surface with default parameters;
1402 */
1403void dc_gamma_retain(struct dc_gamma *dc_gamma);
1404void dc_gamma_release(struct dc_gamma **dc_gamma);
1405struct dc_gamma *dc_create_gamma(void);
1406
1407void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1408void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1409struct dc_transfer_func *dc_create_transfer_func(void);
1410
1411struct dc_3dlut *dc_create_3dlut_func(void);
1412void dc_3dlut_func_release(struct dc_3dlut *lut);
1413void dc_3dlut_func_retain(struct dc_3dlut *lut);
1414
1415void dc_post_update_surfaces_to_stream(
1416 struct dc *dc);
1417
1418#include "dc_stream.h"
1419
1420/**
1421 * struct dc_validation_set - Struct to store surface/stream associations for validation
1422 */
1423struct dc_validation_set {
1424 /**
1425 * @stream: Stream state properties
1426 */
1427 struct dc_stream_state *stream;
1428
1429 /**
1430 * @plane_states: Surface state
1431 */
1432 struct dc_plane_state *plane_states[MAX_SURFACES];
1433
1434 /**
1435 * @plane_count: Total of active planes
1436 */
1437 uint8_t plane_count;
1438};
1439
1440bool dc_validate_boot_timing(const struct dc *dc,
1441 const struct dc_sink *sink,
1442 struct dc_crtc_timing *crtc_timing);
1443
1444enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1445
1446void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1447
1448enum dc_status dc_validate_with_context(struct dc *dc,
1449 const struct dc_validation_set set[],
1450 int set_count,
1451 struct dc_state *context,
1452 bool fast_validate);
1453
1454bool dc_set_generic_gpio_for_stereo(bool enable,
1455 struct gpio_service *gpio_service);
1456
1457/*
1458 * fast_validate: we return after determining if we can support the new state,
1459 * but before we populate the programming info
1460 */
1461enum dc_status dc_validate_global_state(
1462 struct dc *dc,
1463 struct dc_state *new_ctx,
1464 bool fast_validate);
1465
1466bool dc_acquire_release_mpc_3dlut(
1467 struct dc *dc, bool acquire,
1468 struct dc_stream_state *stream,
1469 struct dc_3dlut **lut,
1470 struct dc_transfer_func **shaper);
1471
1472bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1473void get_audio_check(struct audio_info *aud_modes,
1474 struct audio_check *aud_chk);
1475
1476enum dc_status dc_commit_streams(struct dc *dc,
1477 struct dc_stream_state *streams[],
1478 uint8_t stream_count);
1479
1480
1481struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1482 struct dc_stream_state *stream,
1483 int mpcc_inst);
1484
1485
1486uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1487
1488void dc_set_disable_128b_132b_stream_overhead(bool disable);
1489
1490/* The function returns minimum bandwidth required to drive a given timing
1491 * return - minimum required timing bandwidth in kbps.
1492 */
1493uint32_t dc_bandwidth_in_kbps_from_timing(
1494 const struct dc_crtc_timing *timing,
1495 const enum dc_link_encoding_format link_encoding);
1496
1497/* Link Interfaces */
1498/*
1499 * A link contains one or more sinks and their connected status.
1500 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1501 */
1502struct dc_link {
1503 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1504 unsigned int sink_count;
1505 struct dc_sink *local_sink;
1506 unsigned int link_index;
1507 enum dc_connection_type type;
1508 enum signal_type connector_signal;
1509 enum dc_irq_source irq_source_hpd;
1510 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
1511
1512 bool is_hpd_filter_disabled;
1513 bool dp_ss_off;
1514
1515 /**
1516 * @link_state_valid:
1517 *
1518 * If there is no link and local sink, this variable should be set to
1519 * false. Otherwise, it should be set to true; usually, the function
1520 * core_link_enable_stream sets this field to true.
1521 */
1522 bool link_state_valid;
1523 bool aux_access_disabled;
1524 bool sync_lt_in_progress;
1525 bool skip_stream_reenable;
1526 bool is_internal_display;
1527 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1528 bool is_dig_mapping_flexible;
1529 bool hpd_status; /* HPD status of link without physical HPD pin. */
1530 bool is_hpd_pending; /* Indicates a new received hpd */
1531
1532 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method
1533 * for every link training. This is incompatible with DP LL compliance automation,
1534 * which expects the same link settings to be used every retry on a link loss.
1535 * This flag is used to skip the fallback when link loss occurs during automation.
1536 */
1537 bool skip_fallback_on_link_loss;
1538
1539 bool edp_sink_present;
1540
1541 struct dp_trace dp_trace;
1542
1543 /* caps is the same as reported_link_cap. link_traing use
1544 * reported_link_cap. Will clean up. TODO
1545 */
1546 struct dc_link_settings reported_link_cap;
1547 struct dc_link_settings verified_link_cap;
1548 struct dc_link_settings cur_link_settings;
1549 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1550 struct dc_link_settings preferred_link_setting;
1551 /* preferred_training_settings are override values that
1552 * come from DM. DM is responsible for the memory
1553 * management of the override pointers.
1554 */
1555 struct dc_link_training_overrides preferred_training_settings;
1556 struct dp_audio_test_data audio_test_data;
1557
1558 uint8_t ddc_hw_inst;
1559
1560 uint8_t hpd_src;
1561
1562 uint8_t link_enc_hw_inst;
1563 /* DIG link encoder ID. Used as index in link encoder resource pool.
1564 * For links with fixed mapping to DIG, this is not changed after dc_link
1565 * object creation.
1566 */
1567 enum engine_id eng_id;
1568 enum engine_id dpia_preferred_eng_id;
1569
1570 bool test_pattern_enabled;
1571 enum dp_test_pattern current_test_pattern;
1572 union compliance_test_state compliance_test_state;
1573
1574 void *priv;
1575
1576 struct ddc_service *ddc;
1577
1578 enum dp_panel_mode panel_mode;
1579 bool aux_mode;
1580
1581 /* Private to DC core */
1582
1583 const struct dc *dc;
1584
1585 struct dc_context *ctx;
1586
1587 struct panel_cntl *panel_cntl;
1588 struct link_encoder *link_enc;
1589 struct graphics_object_id link_id;
1590 /* Endpoint type distinguishes display endpoints which do not have entries
1591 * in the BIOS connector table from those that do. Helps when tracking link
1592 * encoder to display endpoint assignments.
1593 */
1594 enum display_endpoint_type ep_type;
1595 union ddi_channel_mapping ddi_channel_mapping;
1596 struct connector_device_tag_info device_tag;
1597 struct dpcd_caps dpcd_caps;
1598 uint32_t dongle_max_pix_clk;
1599 unsigned short chip_caps;
1600 unsigned int dpcd_sink_count;
1601 struct hdcp_caps hdcp_caps;
1602 enum edp_revision edp_revision;
1603 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1604
1605 struct psr_settings psr_settings;
1606
1607 struct replay_settings replay_settings;
1608
1609 /* Drive settings read from integrated info table */
1610 struct dc_lane_settings bios_forced_drive_settings;
1611
1612 /* Vendor specific LTTPR workaround variables */
1613 uint8_t vendor_specific_lttpr_link_rate_wa;
1614 bool apply_vendor_specific_lttpr_link_rate_wa;
1615
1616 /* MST record stream using this link */
1617 struct link_flags {
1618 bool dp_keep_receiver_powered;
1619 bool dp_skip_DID2;
1620 bool dp_skip_reset_segment;
1621 bool dp_skip_fs_144hz;
1622 bool dp_mot_reset_segment;
1623 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1624 bool dpia_mst_dsc_always_on;
1625 /* Forced DPIA into TBT3 compatibility mode. */
1626 bool dpia_forced_tbt3_mode;
1627 bool dongle_mode_timing_override;
1628 bool blank_stream_on_ocs_change;
1629 bool read_dpcd204h_on_irq_hpd;
1630 } wa_flags;
1631 struct link_mst_stream_allocation_table mst_stream_alloc_table;
1632
1633 struct dc_link_status link_status;
1634 struct dprx_states dprx_states;
1635
1636 struct gpio *hpd_gpio;
1637 enum dc_link_fec_state fec_state;
1638 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
1639
1640 struct dc_panel_config panel_config;
1641 struct phy_state phy_state;
1642 // BW ALLOCATON USB4 ONLY
1643 struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1644 bool skip_implict_edp_power_control;
1645};
1646
1647/* Return an enumerated dc_link.
1648 * dc_link order is constant and determined at
1649 * boot time. They cannot be created or destroyed.
1650 * Use dc_get_caps() to get number of links.
1651 */
1652struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1653
1654/* Return instance id of the edp link. Inst 0 is primary edp link. */
1655bool dc_get_edp_link_panel_inst(const struct dc *dc,
1656 const struct dc_link *link,
1657 unsigned int *inst_out);
1658
1659/* Return an array of link pointers to edp links. */
1660void dc_get_edp_links(const struct dc *dc,
1661 struct dc_link **edp_links,
1662 int *edp_num);
1663
1664void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1665 bool powerOn);
1666
1667/* The function initiates detection handshake over the given link. It first
1668 * determines if there are display connections over the link. If so it initiates
1669 * detection protocols supported by the connected receiver device. The function
1670 * contains protocol specific handshake sequences which are sometimes mandatory
1671 * to establish a proper connection between TX and RX. So it is always
1672 * recommended to call this function as the first link operation upon HPD event
1673 * or power up event. Upon completion, the function will update link structure
1674 * in place based on latest RX capabilities. The function may also cause dpms
1675 * to be reset to off for all currently enabled streams to the link. It is DM's
1676 * responsibility to serialize detection and DPMS updates.
1677 *
1678 * @reason - Indicate which event triggers this detection. dc may customize
1679 * detection flow depending on the triggering events.
1680 * return false - if detection is not fully completed. This could happen when
1681 * there is an unrecoverable error during detection or detection is partially
1682 * completed (detection has been delegated to dm mst manager ie.
1683 * link->connection_type == dc_connection_mst_branch when returning false).
1684 * return true - detection is completed, link has been fully updated with latest
1685 * detection result.
1686 */
1687bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1688
1689struct dc_sink_init_data;
1690
1691/* When link connection type is dc_connection_mst_branch, remote sink can be
1692 * added to the link. The interface creates a remote sink and associates it with
1693 * current link. The sink will be retained by link until remove remote sink is
1694 * called.
1695 *
1696 * @dc_link - link the remote sink will be added to.
1697 * @edid - byte array of EDID raw data.
1698 * @len - size of the edid in byte
1699 * @init_data -
1700 */
1701struct dc_sink *dc_link_add_remote_sink(
1702 struct dc_link *dc_link,
1703 const uint8_t *edid,
1704 int len,
1705 struct dc_sink_init_data *init_data);
1706
1707/* Remove remote sink from a link with dc_connection_mst_branch connection type.
1708 * @link - link the sink should be removed from
1709 * @sink - sink to be removed.
1710 */
1711void dc_link_remove_remote_sink(
1712 struct dc_link *link,
1713 struct dc_sink *sink);
1714
1715/* Enable HPD interrupt handler for a given link */
1716void dc_link_enable_hpd(const struct dc_link *link);
1717
1718/* Disable HPD interrupt handler for a given link */
1719void dc_link_disable_hpd(const struct dc_link *link);
1720
1721/* determine if there is a sink connected to the link
1722 *
1723 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1724 * return - false if an unexpected error occurs, true otherwise.
1725 *
1726 * NOTE: This function doesn't detect downstream sink connections i.e
1727 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1728 * return dc_connection_single if the branch device is connected despite of
1729 * downstream sink's connection status.
1730 */
1731bool dc_link_detect_connection_type(struct dc_link *link,
1732 enum dc_connection_type *type);
1733
1734/* query current hpd pin value
1735 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1736 *
1737 */
1738bool dc_link_get_hpd_state(struct dc_link *link);
1739
1740/* Getter for cached link status from given link */
1741const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1742
1743/* enable/disable hardware HPD filter.
1744 *
1745 * @link - The link the HPD pin is associated with.
1746 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1747 * handler once after no HPD change has been detected within dc default HPD
1748 * filtering interval since last HPD event. i.e if display keeps toggling hpd
1749 * pulses within default HPD interval, no HPD event will be received until HPD
1750 * toggles have stopped. Then HPD event will be queued to irq handler once after
1751 * dc default HPD filtering interval since last HPD event.
1752 *
1753 * @enable = false - disable hardware HPD filter. HPD event will be queued
1754 * immediately to irq handler after no HPD change has been detected within
1755 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1756 */
1757void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1758
1759/* submit i2c read/write payloads through ddc channel
1760 * @link_index - index to a link with ddc in i2c mode
1761 * @cmd - i2c command structure
1762 * return - true if success, false otherwise.
1763 */
1764bool dc_submit_i2c(
1765 struct dc *dc,
1766 uint32_t link_index,
1767 struct i2c_command *cmd);
1768
1769/* submit i2c read/write payloads through oem channel
1770 * @link_index - index to a link with ddc in i2c mode
1771 * @cmd - i2c command structure
1772 * return - true if success, false otherwise.
1773 */
1774bool dc_submit_i2c_oem(
1775 struct dc *dc,
1776 struct i2c_command *cmd);
1777
1778enum aux_return_code_type;
1779/* Attempt to transfer the given aux payload. This function does not perform
1780 * retries or handle error states. The reply is returned in the payload->reply
1781 * and the result through operation_result. Returns the number of bytes
1782 * transferred,or -1 on a failure.
1783 */
1784int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1785 struct aux_payload *payload,
1786 enum aux_return_code_type *operation_result);
1787
1788bool dc_is_oem_i2c_device_present(
1789 struct dc *dc,
1790 size_t slave_address
1791);
1792
1793/* return true if the connected receiver supports the hdcp version */
1794bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1795bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1796
1797/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1798 *
1799 * TODO - When defer_handling is true the function will have a different purpose.
1800 * It no longer does complete hpd rx irq handling. We should create a separate
1801 * interface specifically for this case.
1802 *
1803 * Return:
1804 * true - Downstream port status changed. DM should call DC to do the
1805 * detection.
1806 * false - no change in Downstream port status. No further action required
1807 * from DM.
1808 */
1809bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1810 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1811 bool defer_handling, bool *has_left_work);
1812/* handle DP specs define test automation sequence*/
1813void dc_link_dp_handle_automated_test(struct dc_link *link);
1814
1815/* handle DP Link loss sequence and try to recover RX link loss with best
1816 * effort
1817 */
1818void dc_link_dp_handle_link_loss(struct dc_link *link);
1819
1820/* Determine if hpd rx irq should be handled or ignored
1821 * return true - hpd rx irq should be handled.
1822 * return false - it is safe to ignore hpd rx irq event
1823 */
1824bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1825
1826/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1827 * @link - link the hpd irq data associated with
1828 * @hpd_irq_dpcd_data - input hpd irq data
1829 * return - true if hpd irq data indicates a link lost
1830 */
1831bool dc_link_check_link_loss_status(struct dc_link *link,
1832 union hpd_irq_data *hpd_irq_dpcd_data);
1833
1834/* Read hpd rx irq data from a given link
1835 * @link - link where the hpd irq data should be read from
1836 * @irq_data - output hpd irq data
1837 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1838 * read has failed.
1839 */
1840enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1841 struct dc_link *link,
1842 union hpd_irq_data *irq_data);
1843
1844/* The function clears recorded DP RX states in the link. DM should call this
1845 * function when it is resuming from S3 power state to previously connected links.
1846 *
1847 * TODO - in the future we should consider to expand link resume interface to
1848 * support clearing previous rx states. So we don't have to rely on dm to call
1849 * this interface explicitly.
1850 */
1851void dc_link_clear_dprx_states(struct dc_link *link);
1852
1853/* Destruct the mst topology of the link and reset the allocated payload table
1854 *
1855 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1856 * still wants to reset MST topology on an unplug event */
1857bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1858
1859/* The function calculates effective DP link bandwidth when a given link is
1860 * using the given link settings.
1861 *
1862 * return - total effective link bandwidth in kbps.
1863 */
1864uint32_t dc_link_bandwidth_kbps(
1865 const struct dc_link *link,
1866 const struct dc_link_settings *link_setting);
1867
1868/* The function takes a snapshot of current link resource allocation state
1869 * @dc: pointer to dc of the dm calling this
1870 * @map: a dc link resource snapshot defined internally to dc.
1871 *
1872 * DM needs to capture a snapshot of current link resource allocation mapping
1873 * and store it in its persistent storage.
1874 *
1875 * Some of the link resource is using first come first serve policy.
1876 * The allocation mapping depends on original hotplug order. This information
1877 * is lost after driver is loaded next time. The snapshot is used in order to
1878 * restore link resource to its previous state so user will get consistent
1879 * link capability allocation across reboot.
1880 *
1881 */
1882void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
1883
1884/* This function restores link resource allocation state from a snapshot
1885 * @dc: pointer to dc of the dm calling this
1886 * @map: a dc link resource snapshot defined internally to dc.
1887 *
1888 * DM needs to call this function after initial link detection on boot and
1889 * before first commit streams to restore link resource allocation state
1890 * from previous boot session.
1891 *
1892 * Some of the link resource is using first come first serve policy.
1893 * The allocation mapping depends on original hotplug order. This information
1894 * is lost after driver is loaded next time. The snapshot is used in order to
1895 * restore link resource to its previous state so user will get consistent
1896 * link capability allocation across reboot.
1897 *
1898 */
1899void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
1900
1901/* TODO: this is not meant to be exposed to DM. Should switch to stream update
1902 * interface i.e stream_update->dsc_config
1903 */
1904bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
1905
1906/* translate a raw link rate data to bandwidth in kbps */
1907uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
1908
1909/* determine the optimal bandwidth given link and required bw.
1910 * @link - current detected link
1911 * @req_bw - requested bandwidth in kbps
1912 * @link_settings - returned most optimal link settings that can fit the
1913 * requested bandwidth
1914 * return - false if link can't support requested bandwidth, true if link
1915 * settings is found.
1916 */
1917bool dc_link_decide_edp_link_settings(struct dc_link *link,
1918 struct dc_link_settings *link_settings,
1919 uint32_t req_bw);
1920
1921/* return the max dp link settings can be driven by the link without considering
1922 * connected RX device and its capability
1923 */
1924bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
1925 struct dc_link_settings *max_link_enc_cap);
1926
1927/* determine when the link is driving MST mode, what DP link channel coding
1928 * format will be used. The decision will remain unchanged until next HPD event.
1929 *
1930 * @link - a link with DP RX connection
1931 * return - if stream is committed to this link with MST signal type, type of
1932 * channel coding format dc will choose.
1933 */
1934enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
1935 const struct dc_link *link);
1936
1937/* get max dp link settings the link can enable with all things considered. (i.e
1938 * TX/RX/Cable capabilities and dp override policies.
1939 *
1940 * @link - a link with DP RX connection
1941 * return - max dp link settings the link can enable.
1942 *
1943 */
1944const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
1945
1946/* Get the highest encoding format that the link supports; highest meaning the
1947 * encoding format which supports the maximum bandwidth.
1948 *
1949 * @link - a link with DP RX connection
1950 * return - highest encoding format link supports.
1951 */
1952enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
1953
1954/* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
1955 * to a link with dp connector signal type.
1956 * @link - a link with dp connector signal type
1957 * return - true if connected, false otherwise
1958 */
1959bool dc_link_is_dp_sink_present(struct dc_link *link);
1960
1961/* Force DP lane settings update to main-link video signal and notify the change
1962 * to DP RX via DPCD. This is a debug interface used for video signal integrity
1963 * tuning purpose. The interface assumes link has already been enabled with DP
1964 * signal.
1965 *
1966 * @lt_settings - a container structure with desired hw_lane_settings
1967 */
1968void dc_link_set_drive_settings(struct dc *dc,
1969 struct link_training_settings *lt_settings,
1970 struct dc_link *link);
1971
1972/* Enable a test pattern in Link or PHY layer in an active link for compliance
1973 * test or debugging purpose. The test pattern will remain until next un-plug.
1974 *
1975 * @link - active link with DP signal output enabled.
1976 * @test_pattern - desired test pattern to output.
1977 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
1978 * @test_pattern_color_space - for video test pattern choose a desired color
1979 * space.
1980 * @p_link_settings - For PHY pattern choose a desired link settings
1981 * @p_custom_pattern - some test pattern will require a custom input to
1982 * customize some pattern details. Otherwise keep it to NULL.
1983 * @cust_pattern_size - size of the custom pattern input.
1984 *
1985 */
1986bool dc_link_dp_set_test_pattern(
1987 struct dc_link *link,
1988 enum dp_test_pattern test_pattern,
1989 enum dp_test_pattern_color_space test_pattern_color_space,
1990 const struct link_training_settings *p_link_settings,
1991 const unsigned char *p_custom_pattern,
1992 unsigned int cust_pattern_size);
1993
1994/* Force DP link settings to always use a specific value until reboot to a
1995 * specific link. If link has already been enabled, the interface will also
1996 * switch to desired link settings immediately. This is a debug interface to
1997 * generic dp issue trouble shooting.
1998 */
1999void dc_link_set_preferred_link_settings(struct dc *dc,
2000 struct dc_link_settings *link_setting,
2001 struct dc_link *link);
2002
2003/* Force DP link to customize a specific link training behavior by overriding to
2004 * standard DP specs defined protocol. This is a debug interface to trouble shoot
2005 * display specific link training issues or apply some display specific
2006 * workaround in link training.
2007 *
2008 * @link_settings - if not NULL, force preferred link settings to the link.
2009 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2010 * will apply this particular override in future link training. If NULL is
2011 * passed in, dc resets previous overrides.
2012 * NOTE: DM must keep the memory from override pointers until DM resets preferred
2013 * training settings.
2014 */
2015void dc_link_set_preferred_training_settings(struct dc *dc,
2016 struct dc_link_settings *link_setting,
2017 struct dc_link_training_overrides *lt_overrides,
2018 struct dc_link *link,
2019 bool skip_immediate_retrain);
2020
2021/* return - true if FEC is supported with connected DP RX, false otherwise */
2022bool dc_link_is_fec_supported(const struct dc_link *link);
2023
2024/* query FEC enablement policy to determine if FEC will be enabled by dc during
2025 * link enablement.
2026 * return - true if FEC should be enabled, false otherwise.
2027 */
2028bool dc_link_should_enable_fec(const struct dc_link *link);
2029
2030/* determine lttpr mode the current link should be enabled with a specific link
2031 * settings.
2032 */
2033enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
2034 struct dc_link_settings *link_setting);
2035
2036/* Force DP RX to update its power state.
2037 * NOTE: this interface doesn't update dp main-link. Calling this function will
2038 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2039 * RX power state back upon finish DM specific execution requiring DP RX in a
2040 * specific power state.
2041 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2042 * state.
2043 */
2044void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
2045
2046/* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2047 * current value read from extended receiver cap from 02200h - 0220Fh.
2048 * Some DP RX has problems of providing accurate DP receiver caps from extended
2049 * field, this interface is a workaround to revert link back to use base caps.
2050 */
2051void dc_link_overwrite_extended_receiver_cap(
2052 struct dc_link *link);
2053
2054void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
2055 bool wait_for_hpd);
2056
2057/* Set backlight level of an embedded panel (eDP, LVDS).
2058 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
2059 * and 16 bit fractional, where 1.0 is max backlight value.
2060 */
2061bool dc_link_set_backlight_level(const struct dc_link *dc_link,
2062 uint32_t backlight_pwm_u16_16,
2063 uint32_t frame_ramp);
2064
2065/* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2066bool dc_link_set_backlight_level_nits(struct dc_link *link,
2067 bool isHDR,
2068 uint32_t backlight_millinits,
2069 uint32_t transition_time_in_ms);
2070
2071bool dc_link_get_backlight_level_nits(struct dc_link *link,
2072 uint32_t *backlight_millinits,
2073 uint32_t *backlight_millinits_peak);
2074
2075int dc_link_get_backlight_level(const struct dc_link *dc_link);
2076
2077int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2078
2079bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2080 bool wait, bool force_static, const unsigned int *power_opts);
2081
2082bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2083
2084bool dc_link_setup_psr(struct dc_link *dc_link,
2085 const struct dc_stream_state *stream, struct psr_config *psr_config,
2086 struct psr_context *psr_context);
2087
2088/*
2089 * Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2090 *
2091 * @link: pointer to the dc_link struct instance
2092 * @enable: enable(active) or disable(inactive) replay
2093 * @wait: state transition need to wait the active set completed.
2094 * @force_static: force disable(inactive) the replay
2095 * @power_opts: set power optimazation parameters to DMUB.
2096 *
2097 * return: allow Replay active will return true, else will return false.
2098 */
2099bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
2100 bool wait, bool force_static, const unsigned int *power_opts);
2101
2102bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2103
2104/* On eDP links this function call will stall until T12 has elapsed.
2105 * If the panel is not in power off state, this function will return
2106 * immediately.
2107 */
2108bool dc_link_wait_for_t12(struct dc_link *link);
2109
2110/* Determine if dp trace has been initialized to reflect upto date result *
2111 * return - true if trace is initialized and has valid data. False dp trace
2112 * doesn't have valid result.
2113 */
2114bool dc_dp_trace_is_initialized(struct dc_link *link);
2115
2116/* Query a dp trace flag to indicate if the current dp trace data has been
2117 * logged before
2118 */
2119bool dc_dp_trace_is_logged(struct dc_link *link,
2120 bool in_detection);
2121
2122/* Set dp trace flag to indicate whether DM has already logged the current dp
2123 * trace data. DM can set is_logged to true upon logging and check
2124 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2125 */
2126void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
2127 bool in_detection,
2128 bool is_logged);
2129
2130/* Obtain driver time stamp for last dp link training end. The time stamp is
2131 * formatted based on dm_get_timestamp DM function.
2132 * @in_detection - true to get link training end time stamp of last link
2133 * training in detection sequence. false to get link training end time stamp
2134 * of last link training in commit (dpms) sequence
2135 */
2136unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
2137 bool in_detection);
2138
2139/* Get how many link training attempts dc has done with latest sequence.
2140 * @in_detection - true to get link training count of last link
2141 * training in detection sequence. false to get link training count of last link
2142 * training in commit (dpms) sequence
2143 */
2144const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2145 bool in_detection);
2146
2147/* Get how many link loss has happened since last link training attempts */
2148unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2149
2150/*
2151 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2152 */
2153/*
2154 * Send a request from DP-Tx requesting to allocate BW remotely after
2155 * allocating it locally. This will get processed by CM and a CB function
2156 * will be called.
2157 *
2158 * @link: pointer to the dc_link struct instance
2159 * @req_bw: The requested bw in Kbyte to allocated
2160 *
2161 * return: none
2162 */
2163void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2164
2165/*
2166 * Handle function for when the status of the Request above is complete.
2167 * We will find out the result of allocating on CM and update structs.
2168 *
2169 * @link: pointer to the dc_link struct instance
2170 * @bw: Allocated or Estimated BW depending on the result
2171 * @result: Response type
2172 *
2173 * return: none
2174 */
2175void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2176 uint8_t bw, uint8_t result);
2177
2178/*
2179 * Handle the USB4 BW Allocation related functionality here:
2180 * Plug => Try to allocate max bw from timing parameters supported by the sink
2181 * Unplug => de-allocate bw
2182 *
2183 * @link: pointer to the dc_link struct instance
2184 * @peak_bw: Peak bw used by the link/sink
2185 *
2186 * return: allocated bw else return 0
2187 */
2188int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2189 struct dc_link *link, int peak_bw);
2190
2191/*
2192 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2193 * available BW for each host router
2194 *
2195 * @dc: pointer to dc struct
2196 * @stream: pointer to all possible streams
2197 * @count: number of valid DPIA streams
2198 *
2199 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2200 */
2201bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2202 const unsigned int count);
2203
2204/* Sink Interfaces - A sink corresponds to a display output device */
2205
2206struct dc_container_id {
2207 // 128bit GUID in binary form
2208 unsigned char guid[16];
2209 // 8 byte port ID -> ELD.PortID
2210 unsigned int portId[2];
2211 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2212 unsigned short manufacturerName;
2213 // 2 byte product code -> ELD.ProductCode
2214 unsigned short productCode;
2215};
2216
2217
2218struct dc_sink_dsc_caps {
2219 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2220 // 'false' if they are sink's DSC caps
2221 bool is_virtual_dpcd_dsc;
2222#if defined(CONFIG_DRM_AMD_DC_FP)
2223 // 'true' if MST topology supports DSC passthrough for sink
2224 // 'false' if MST topology does not support DSC passthrough
2225 bool is_dsc_passthrough_supported;
2226#endif
2227 struct dsc_dec_dpcd_caps dsc_dec_caps;
2228};
2229
2230struct dc_sink_fec_caps {
2231 bool is_rx_fec_supported;
2232 bool is_topology_fec_supported;
2233};
2234
2235struct scdc_caps {
2236 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2237 union hdmi_scdc_device_id_data device_id;
2238};
2239
2240/*
2241 * The sink structure contains EDID and other display device properties
2242 */
2243struct dc_sink {
2244 enum signal_type sink_signal;
2245 struct dc_edid dc_edid; /* raw edid */
2246 struct dc_edid_caps edid_caps; /* parse display caps */
2247 struct dc_container_id *dc_container_id;
2248 uint32_t dongle_max_pix_clk;
2249 void *priv;
2250 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2251 bool converter_disable_audio;
2252
2253 struct scdc_caps scdc_caps;
2254 struct dc_sink_dsc_caps dsc_caps;
2255 struct dc_sink_fec_caps fec_caps;
2256
2257 bool is_vsc_sdp_colorimetry_supported;
2258
2259 /* private to DC core */
2260 struct dc_link *link;
2261 struct dc_context *ctx;
2262
2263 uint32_t sink_id;
2264
2265 /* private to dc_sink.c */
2266 // refcount must be the last member in dc_sink, since we want the
2267 // sink structure to be logically cloneable up to (but not including)
2268 // refcount
2269 struct kref refcount;
2270};
2271
2272void dc_sink_retain(struct dc_sink *sink);
2273void dc_sink_release(struct dc_sink *sink);
2274
2275struct dc_sink_init_data {
2276 enum signal_type sink_signal;
2277 struct dc_link *link;
2278 uint32_t dongle_max_pix_clk;
2279 bool converter_disable_audio;
2280};
2281
2282struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2283
2284/* Newer interfaces */
2285struct dc_cursor {
2286 struct dc_plane_address address;
2287 struct dc_cursor_attributes attributes;
2288};
2289
2290
2291/* Interrupt interfaces */
2292enum dc_irq_source dc_interrupt_to_irq_source(
2293 struct dc *dc,
2294 uint32_t src_id,
2295 uint32_t ext_id);
2296bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2297void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2298enum dc_irq_source dc_get_hpd_irq_source_at_index(
2299 struct dc *dc, uint32_t link_index);
2300
2301void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2302
2303/* Power Interfaces */
2304
2305void dc_set_power_state(
2306 struct dc *dc,
2307 enum dc_acpi_cm_power_state power_state);
2308void dc_resume(struct dc *dc);
2309
2310void dc_power_down_on_boot(struct dc *dc);
2311
2312/*
2313 * HDCP Interfaces
2314 */
2315enum hdcp_message_status dc_process_hdcp_msg(
2316 enum signal_type signal,
2317 struct dc_link *link,
2318 struct hdcp_protection_message *message_info);
2319bool dc_is_dmcu_initialized(struct dc *dc);
2320
2321enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2322void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2323
2324bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
2325 struct dc_cursor_attributes *cursor_attr);
2326
2327void dc_allow_idle_optimizations(struct dc *dc, bool allow);
2328bool dc_dmub_is_ips_idle_state(struct dc *dc);
2329
2330/* set min and max memory clock to lowest and highest DPM level, respectively */
2331void dc_unlock_memory_clock_frequency(struct dc *dc);
2332
2333/* set min memory clock to the min required for current mode, max to maxDPM */
2334void dc_lock_memory_clock_frequency(struct dc *dc);
2335
2336/* set soft max for memclk, to be used for AC/DC switching clock limitations */
2337void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2338
2339/* cleanup on driver unload */
2340void dc_hardware_release(struct dc *dc);
2341
2342/* disables fw based mclk switch */
2343void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2344
2345bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2346
2347bool dc_set_replay_allow_active(struct dc *dc, bool active);
2348
2349void dc_z10_restore(const struct dc *dc);
2350void dc_z10_save_init(struct dc *dc);
2351
2352bool dc_is_dmub_outbox_supported(struct dc *dc);
2353bool dc_enable_dmub_notifications(struct dc *dc);
2354
2355bool dc_abm_save_restore(
2356 struct dc *dc,
2357 struct dc_stream_state *stream,
2358 struct abm_save_restore *pData);
2359
2360void dc_enable_dmub_outbox(struct dc *dc);
2361
2362bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2363 uint32_t link_index,
2364 struct aux_payload *payload);
2365
2366/* Get dc link index from dpia port index */
2367uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2368 uint8_t dpia_port_index);
2369
2370bool dc_process_dmub_set_config_async(struct dc *dc,
2371 uint32_t link_index,
2372 struct set_config_cmd_payload *payload,
2373 struct dmub_notification *notify);
2374
2375enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2376 uint32_t link_index,
2377 uint8_t mst_alloc_slots,
2378 uint8_t *mst_slots_in_use);
2379
2380void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2381 uint32_t hpd_int_enable);
2382
2383void dc_print_dmub_diagnostic_data(const struct dc *dc);
2384
2385void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2386
2387struct dc_power_profile {
2388 int power_level; /* Lower is better */
2389};
2390
2391struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
2392
2393/* DSC Interfaces */
2394#include "dc_dsc.h"
2395
2396/* Disable acc mode Interfaces */
2397void dc_disable_accelerated_mode(struct dc *dc);
2398
2399bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2400 struct dc_stream_state *new_stream);
2401
2402#endif /* DC_INTERFACE_H_ */