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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1991, 1992 Linus Torvalds
4 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 *
7 * Pentium III FXSR, SSE support
8 * Gareth Hughes <gareth@valinux.com>, May 2000
9 */
10
11/*
12 * Handle hardware traps and faults.
13 */
14#include <linux/spinlock.h>
15#include <linux/kprobes.h>
16#include <linux/kdebug.h>
17#include <linux/sched/debug.h>
18#include <linux/nmi.h>
19#include <linux/debugfs.h>
20#include <linux/delay.h>
21#include <linux/hardirq.h>
22#include <linux/ratelimit.h>
23#include <linux/slab.h>
24#include <linux/export.h>
25#include <linux/atomic.h>
26#include <linux/sched/clock.h>
27
28#if defined(CONFIG_EDAC)
29#include <linux/edac.h>
30#endif
31
32#include <asm/cpu_entry_area.h>
33#include <asm/traps.h>
34#include <asm/mach_traps.h>
35#include <asm/nmi.h>
36#include <asm/x86_init.h>
37#include <asm/reboot.h>
38#include <asm/cache.h>
39#include <asm/nospec-branch.h>
40
41#define CREATE_TRACE_POINTS
42#include <trace/events/nmi.h>
43
44struct nmi_desc {
45 raw_spinlock_t lock;
46 struct list_head head;
47};
48
49static struct nmi_desc nmi_desc[NMI_MAX] =
50{
51 {
52 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
53 .head = LIST_HEAD_INIT(nmi_desc[0].head),
54 },
55 {
56 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
57 .head = LIST_HEAD_INIT(nmi_desc[1].head),
58 },
59 {
60 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
61 .head = LIST_HEAD_INIT(nmi_desc[2].head),
62 },
63 {
64 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
65 .head = LIST_HEAD_INIT(nmi_desc[3].head),
66 },
67
68};
69
70struct nmi_stats {
71 unsigned int normal;
72 unsigned int unknown;
73 unsigned int external;
74 unsigned int swallow;
75};
76
77static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
78
79static int ignore_nmis __read_mostly;
80
81int unknown_nmi_panic;
82/*
83 * Prevent NMI reason port (0x61) being accessed simultaneously, can
84 * only be used in NMI handler.
85 */
86static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
87
88static int __init setup_unknown_nmi_panic(char *str)
89{
90 unknown_nmi_panic = 1;
91 return 1;
92}
93__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
94
95#define nmi_to_desc(type) (&nmi_desc[type])
96
97static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC;
98
99static int __init nmi_warning_debugfs(void)
100{
101 debugfs_create_u64("nmi_longest_ns", 0644,
102 arch_debugfs_dir, &nmi_longest_ns);
103 return 0;
104}
105fs_initcall(nmi_warning_debugfs);
106
107static void nmi_max_handler(struct irq_work *w)
108{
109 struct nmiaction *a = container_of(w, struct nmiaction, irq_work);
110 int remainder_ns, decimal_msecs;
111 u64 whole_msecs = READ_ONCE(a->max_duration);
112
113 remainder_ns = do_div(whole_msecs, (1000 * 1000));
114 decimal_msecs = remainder_ns / 1000;
115
116 printk_ratelimited(KERN_INFO
117 "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
118 a->handler, whole_msecs, decimal_msecs);
119}
120
121static int nmi_handle(unsigned int type, struct pt_regs *regs)
122{
123 struct nmi_desc *desc = nmi_to_desc(type);
124 struct nmiaction *a;
125 int handled=0;
126
127 rcu_read_lock();
128
129 /*
130 * NMIs are edge-triggered, which means if you have enough
131 * of them concurrently, you can lose some because only one
132 * can be latched at any given time. Walk the whole list
133 * to handle those situations.
134 */
135 list_for_each_entry_rcu(a, &desc->head, list) {
136 int thishandled;
137 u64 delta;
138
139 delta = sched_clock();
140 thishandled = a->handler(type, regs);
141 handled += thishandled;
142 delta = sched_clock() - delta;
143 trace_nmi_handler(a->handler, (int)delta, thishandled);
144
145 if (delta < nmi_longest_ns || delta < a->max_duration)
146 continue;
147
148 a->max_duration = delta;
149 irq_work_queue(&a->irq_work);
150 }
151
152 rcu_read_unlock();
153
154 /* return total number of NMI events handled */
155 return handled;
156}
157NOKPROBE_SYMBOL(nmi_handle);
158
159int __register_nmi_handler(unsigned int type, struct nmiaction *action)
160{
161 struct nmi_desc *desc = nmi_to_desc(type);
162 unsigned long flags;
163
164 if (!action->handler)
165 return -EINVAL;
166
167 init_irq_work(&action->irq_work, nmi_max_handler);
168
169 raw_spin_lock_irqsave(&desc->lock, flags);
170
171 /*
172 * Indicate if there are multiple registrations on the
173 * internal NMI handler call chains (SERR and IO_CHECK).
174 */
175 WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
176 WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
177
178 /*
179 * some handlers need to be executed first otherwise a fake
180 * event confuses some handlers (kdump uses this flag)
181 */
182 if (action->flags & NMI_FLAG_FIRST)
183 list_add_rcu(&action->list, &desc->head);
184 else
185 list_add_tail_rcu(&action->list, &desc->head);
186
187 raw_spin_unlock_irqrestore(&desc->lock, flags);
188 return 0;
189}
190EXPORT_SYMBOL(__register_nmi_handler);
191
192void unregister_nmi_handler(unsigned int type, const char *name)
193{
194 struct nmi_desc *desc = nmi_to_desc(type);
195 struct nmiaction *n;
196 unsigned long flags;
197
198 raw_spin_lock_irqsave(&desc->lock, flags);
199
200 list_for_each_entry_rcu(n, &desc->head, list) {
201 /*
202 * the name passed in to describe the nmi handler
203 * is used as the lookup key
204 */
205 if (!strcmp(n->name, name)) {
206 WARN(in_nmi(),
207 "Trying to free NMI (%s) from NMI context!\n", n->name);
208 list_del_rcu(&n->list);
209 break;
210 }
211 }
212
213 raw_spin_unlock_irqrestore(&desc->lock, flags);
214 synchronize_rcu();
215}
216EXPORT_SYMBOL_GPL(unregister_nmi_handler);
217
218static void
219pci_serr_error(unsigned char reason, struct pt_regs *regs)
220{
221 /* check to see if anyone registered against these types of errors */
222 if (nmi_handle(NMI_SERR, regs))
223 return;
224
225 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
226 reason, smp_processor_id());
227
228 if (panic_on_unrecovered_nmi)
229 nmi_panic(regs, "NMI: Not continuing");
230
231 pr_emerg("Dazed and confused, but trying to continue\n");
232
233 /* Clear and disable the PCI SERR error line. */
234 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
235 outb(reason, NMI_REASON_PORT);
236}
237NOKPROBE_SYMBOL(pci_serr_error);
238
239static void
240io_check_error(unsigned char reason, struct pt_regs *regs)
241{
242 unsigned long i;
243
244 /* check to see if anyone registered against these types of errors */
245 if (nmi_handle(NMI_IO_CHECK, regs))
246 return;
247
248 pr_emerg(
249 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
250 reason, smp_processor_id());
251 show_regs(regs);
252
253 if (panic_on_io_nmi) {
254 nmi_panic(regs, "NMI IOCK error: Not continuing");
255
256 /*
257 * If we end up here, it means we have received an NMI while
258 * processing panic(). Simply return without delaying and
259 * re-enabling NMIs.
260 */
261 return;
262 }
263
264 /* Re-enable the IOCK line, wait for a few seconds */
265 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
266 outb(reason, NMI_REASON_PORT);
267
268 i = 20000;
269 while (--i) {
270 touch_nmi_watchdog();
271 udelay(100);
272 }
273
274 reason &= ~NMI_REASON_CLEAR_IOCHK;
275 outb(reason, NMI_REASON_PORT);
276}
277NOKPROBE_SYMBOL(io_check_error);
278
279static void
280unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
281{
282 int handled;
283
284 /*
285 * Use 'false' as back-to-back NMIs are dealt with one level up.
286 * Of course this makes having multiple 'unknown' handlers useless
287 * as only the first one is ever run (unless it can actually determine
288 * if it caused the NMI)
289 */
290 handled = nmi_handle(NMI_UNKNOWN, regs);
291 if (handled) {
292 __this_cpu_add(nmi_stats.unknown, handled);
293 return;
294 }
295
296 __this_cpu_add(nmi_stats.unknown, 1);
297
298 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
299 reason, smp_processor_id());
300
301 pr_emerg("Do you have a strange power saving mode enabled?\n");
302 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
303 nmi_panic(regs, "NMI: Not continuing");
304
305 pr_emerg("Dazed and confused, but trying to continue\n");
306}
307NOKPROBE_SYMBOL(unknown_nmi_error);
308
309static DEFINE_PER_CPU(bool, swallow_nmi);
310static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
311
312static void default_do_nmi(struct pt_regs *regs)
313{
314 unsigned char reason = 0;
315 int handled;
316 bool b2b = false;
317
318 /*
319 * CPU-specific NMI must be processed before non-CPU-specific
320 * NMI, otherwise we may lose it, because the CPU-specific
321 * NMI can not be detected/processed on other CPUs.
322 */
323
324 /*
325 * Back-to-back NMIs are interesting because they can either
326 * be two NMI or more than two NMIs (any thing over two is dropped
327 * due to NMI being edge-triggered). If this is the second half
328 * of the back-to-back NMI, assume we dropped things and process
329 * more handlers. Otherwise reset the 'swallow' NMI behaviour
330 */
331 if (regs->ip == __this_cpu_read(last_nmi_rip))
332 b2b = true;
333 else
334 __this_cpu_write(swallow_nmi, false);
335
336 __this_cpu_write(last_nmi_rip, regs->ip);
337
338 handled = nmi_handle(NMI_LOCAL, regs);
339 __this_cpu_add(nmi_stats.normal, handled);
340 if (handled) {
341 /*
342 * There are cases when a NMI handler handles multiple
343 * events in the current NMI. One of these events may
344 * be queued for in the next NMI. Because the event is
345 * already handled, the next NMI will result in an unknown
346 * NMI. Instead lets flag this for a potential NMI to
347 * swallow.
348 */
349 if (handled > 1)
350 __this_cpu_write(swallow_nmi, true);
351 return;
352 }
353
354 /*
355 * Non-CPU-specific NMI: NMI sources can be processed on any CPU.
356 *
357 * Another CPU may be processing panic routines while holding
358 * nmi_reason_lock. Check if the CPU issued the IPI for crash dumping,
359 * and if so, call its callback directly. If there is no CPU preparing
360 * crash dump, we simply loop here.
361 */
362 while (!raw_spin_trylock(&nmi_reason_lock)) {
363 run_crash_ipi_callback(regs);
364 cpu_relax();
365 }
366
367 reason = x86_platform.get_nmi_reason();
368
369 if (reason & NMI_REASON_MASK) {
370 if (reason & NMI_REASON_SERR)
371 pci_serr_error(reason, regs);
372 else if (reason & NMI_REASON_IOCHK)
373 io_check_error(reason, regs);
374#ifdef CONFIG_X86_32
375 /*
376 * Reassert NMI in case it became active
377 * meanwhile as it's edge-triggered:
378 */
379 reassert_nmi();
380#endif
381 __this_cpu_add(nmi_stats.external, 1);
382 raw_spin_unlock(&nmi_reason_lock);
383 return;
384 }
385 raw_spin_unlock(&nmi_reason_lock);
386
387 /*
388 * Only one NMI can be latched at a time. To handle
389 * this we may process multiple nmi handlers at once to
390 * cover the case where an NMI is dropped. The downside
391 * to this approach is we may process an NMI prematurely,
392 * while its real NMI is sitting latched. This will cause
393 * an unknown NMI on the next run of the NMI processing.
394 *
395 * We tried to flag that condition above, by setting the
396 * swallow_nmi flag when we process more than one event.
397 * This condition is also only present on the second half
398 * of a back-to-back NMI, so we flag that condition too.
399 *
400 * If both are true, we assume we already processed this
401 * NMI previously and we swallow it. Otherwise we reset
402 * the logic.
403 *
404 * There are scenarios where we may accidentally swallow
405 * a 'real' unknown NMI. For example, while processing
406 * a perf NMI another perf NMI comes in along with a
407 * 'real' unknown NMI. These two NMIs get combined into
408 * one (as descibed above). When the next NMI gets
409 * processed, it will be flagged by perf as handled, but
410 * noone will know that there was a 'real' unknown NMI sent
411 * also. As a result it gets swallowed. Or if the first
412 * perf NMI returns two events handled then the second
413 * NMI will get eaten by the logic below, again losing a
414 * 'real' unknown NMI. But this is the best we can do
415 * for now.
416 */
417 if (b2b && __this_cpu_read(swallow_nmi))
418 __this_cpu_add(nmi_stats.swallow, 1);
419 else
420 unknown_nmi_error(reason, regs);
421}
422NOKPROBE_SYMBOL(default_do_nmi);
423
424/*
425 * NMIs can page fault or hit breakpoints which will cause it to lose
426 * its NMI context with the CPU when the breakpoint or page fault does an IRET.
427 *
428 * As a result, NMIs can nest if NMIs get unmasked due an IRET during
429 * NMI processing. On x86_64, the asm glue protects us from nested NMIs
430 * if the outer NMI came from kernel mode, but we can still nest if the
431 * outer NMI came from user mode.
432 *
433 * To handle these nested NMIs, we have three states:
434 *
435 * 1) not running
436 * 2) executing
437 * 3) latched
438 *
439 * When no NMI is in progress, it is in the "not running" state.
440 * When an NMI comes in, it goes into the "executing" state.
441 * Normally, if another NMI is triggered, it does not interrupt
442 * the running NMI and the HW will simply latch it so that when
443 * the first NMI finishes, it will restart the second NMI.
444 * (Note, the latch is binary, thus multiple NMIs triggering,
445 * when one is running, are ignored. Only one NMI is restarted.)
446 *
447 * If an NMI executes an iret, another NMI can preempt it. We do not
448 * want to allow this new NMI to run, but we want to execute it when the
449 * first one finishes. We set the state to "latched", and the exit of
450 * the first NMI will perform a dec_return, if the result is zero
451 * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the
452 * dec_return would have set the state to NMI_EXECUTING (what we want it
453 * to be when we are running). In this case, we simply jump back to
454 * rerun the NMI handler again, and restart the 'latched' NMI.
455 *
456 * No trap (breakpoint or page fault) should be hit before nmi_restart,
457 * thus there is no race between the first check of state for NOT_RUNNING
458 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
459 * at this point.
460 *
461 * In case the NMI takes a page fault, we need to save off the CR2
462 * because the NMI could have preempted another page fault and corrupt
463 * the CR2 that is about to be read. As nested NMIs must be restarted
464 * and they can not take breakpoints or page faults, the update of the
465 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
466 * Otherwise, there would be a race of another nested NMI coming in
467 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
468 */
469enum nmi_states {
470 NMI_NOT_RUNNING = 0,
471 NMI_EXECUTING,
472 NMI_LATCHED,
473};
474static DEFINE_PER_CPU(enum nmi_states, nmi_state);
475static DEFINE_PER_CPU(unsigned long, nmi_cr2);
476
477#ifdef CONFIG_X86_64
478/*
479 * In x86_64, we need to handle breakpoint -> NMI -> breakpoint. Without
480 * some care, the inner breakpoint will clobber the outer breakpoint's
481 * stack.
482 *
483 * If a breakpoint is being processed, and the debug stack is being
484 * used, if an NMI comes in and also hits a breakpoint, the stack
485 * pointer will be set to the same fixed address as the breakpoint that
486 * was interrupted, causing that stack to be corrupted. To handle this
487 * case, check if the stack that was interrupted is the debug stack, and
488 * if so, change the IDT so that new breakpoints will use the current
489 * stack and not switch to the fixed address. On return of the NMI,
490 * switch back to the original IDT.
491 */
492static DEFINE_PER_CPU(int, update_debug_stack);
493
494static bool notrace is_debug_stack(unsigned long addr)
495{
496 struct cea_exception_stacks *cs = __this_cpu_read(cea_exception_stacks);
497 unsigned long top = CEA_ESTACK_TOP(cs, DB);
498 unsigned long bot = CEA_ESTACK_BOT(cs, DB1);
499
500 if (__this_cpu_read(debug_stack_usage))
501 return true;
502 /*
503 * Note, this covers the guard page between DB and DB1 as well to
504 * avoid two checks. But by all means @addr can never point into
505 * the guard page.
506 */
507 return addr >= bot && addr < top;
508}
509NOKPROBE_SYMBOL(is_debug_stack);
510#endif
511
512dotraplinkage notrace void
513do_nmi(struct pt_regs *regs, long error_code)
514{
515 if (IS_ENABLED(CONFIG_SMP) && cpu_is_offline(smp_processor_id()))
516 return;
517
518 if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) {
519 this_cpu_write(nmi_state, NMI_LATCHED);
520 return;
521 }
522 this_cpu_write(nmi_state, NMI_EXECUTING);
523 this_cpu_write(nmi_cr2, read_cr2());
524nmi_restart:
525
526#ifdef CONFIG_X86_64
527 /*
528 * If we interrupted a breakpoint, it is possible that
529 * the nmi handler will have breakpoints too. We need to
530 * change the IDT such that breakpoints that happen here
531 * continue to use the NMI stack.
532 */
533 if (unlikely(is_debug_stack(regs->sp))) {
534 debug_stack_set_zero();
535 this_cpu_write(update_debug_stack, 1);
536 }
537#endif
538
539 nmi_enter();
540
541 inc_irq_stat(__nmi_count);
542
543 if (!ignore_nmis)
544 default_do_nmi(regs);
545
546 nmi_exit();
547
548#ifdef CONFIG_X86_64
549 if (unlikely(this_cpu_read(update_debug_stack))) {
550 debug_stack_reset();
551 this_cpu_write(update_debug_stack, 0);
552 }
553#endif
554
555 if (unlikely(this_cpu_read(nmi_cr2) != read_cr2()))
556 write_cr2(this_cpu_read(nmi_cr2));
557 if (this_cpu_dec_return(nmi_state))
558 goto nmi_restart;
559
560 if (user_mode(regs))
561 mds_user_clear_cpu_buffers();
562}
563NOKPROBE_SYMBOL(do_nmi);
564
565void stop_nmi(void)
566{
567 ignore_nmis++;
568}
569
570void restart_nmi(void)
571{
572 ignore_nmis--;
573}
574
575/* reset the back-to-back NMI logic */
576void local_touch_nmi(void)
577{
578 __this_cpu_write(last_nmi_rip, 0);
579}
580EXPORT_SYMBOL_GPL(local_touch_nmi);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 1991, 1992 Linus Torvalds
4 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
5 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 *
7 * Pentium III FXSR, SSE support
8 * Gareth Hughes <gareth@valinux.com>, May 2000
9 */
10
11/*
12 * Handle hardware traps and faults.
13 */
14#include <linux/spinlock.h>
15#include <linux/kprobes.h>
16#include <linux/kdebug.h>
17#include <linux/sched/debug.h>
18#include <linux/nmi.h>
19#include <linux/debugfs.h>
20#include <linux/delay.h>
21#include <linux/hardirq.h>
22#include <linux/ratelimit.h>
23#include <linux/slab.h>
24#include <linux/export.h>
25#include <linux/atomic.h>
26#include <linux/sched/clock.h>
27
28#include <asm/cpu_entry_area.h>
29#include <asm/traps.h>
30#include <asm/mach_traps.h>
31#include <asm/nmi.h>
32#include <asm/x86_init.h>
33#include <asm/reboot.h>
34#include <asm/cache.h>
35#include <asm/nospec-branch.h>
36#include <asm/microcode.h>
37#include <asm/sev.h>
38
39#define CREATE_TRACE_POINTS
40#include <trace/events/nmi.h>
41
42struct nmi_desc {
43 raw_spinlock_t lock;
44 struct list_head head;
45};
46
47static struct nmi_desc nmi_desc[NMI_MAX] =
48{
49 {
50 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[0].lock),
51 .head = LIST_HEAD_INIT(nmi_desc[0].head),
52 },
53 {
54 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[1].lock),
55 .head = LIST_HEAD_INIT(nmi_desc[1].head),
56 },
57 {
58 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[2].lock),
59 .head = LIST_HEAD_INIT(nmi_desc[2].head),
60 },
61 {
62 .lock = __RAW_SPIN_LOCK_UNLOCKED(&nmi_desc[3].lock),
63 .head = LIST_HEAD_INIT(nmi_desc[3].head),
64 },
65
66};
67
68struct nmi_stats {
69 unsigned int normal;
70 unsigned int unknown;
71 unsigned int external;
72 unsigned int swallow;
73 unsigned long recv_jiffies;
74 unsigned long idt_seq;
75 unsigned long idt_nmi_seq;
76 unsigned long idt_ignored;
77 atomic_long_t idt_calls;
78 unsigned long idt_seq_snap;
79 unsigned long idt_nmi_seq_snap;
80 unsigned long idt_ignored_snap;
81 long idt_calls_snap;
82};
83
84static DEFINE_PER_CPU(struct nmi_stats, nmi_stats);
85
86static int ignore_nmis __read_mostly;
87
88int unknown_nmi_panic;
89/*
90 * Prevent NMI reason port (0x61) being accessed simultaneously, can
91 * only be used in NMI handler.
92 */
93static DEFINE_RAW_SPINLOCK(nmi_reason_lock);
94
95static int __init setup_unknown_nmi_panic(char *str)
96{
97 unknown_nmi_panic = 1;
98 return 1;
99}
100__setup("unknown_nmi_panic", setup_unknown_nmi_panic);
101
102#define nmi_to_desc(type) (&nmi_desc[type])
103
104static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC;
105
106static int __init nmi_warning_debugfs(void)
107{
108 debugfs_create_u64("nmi_longest_ns", 0644,
109 arch_debugfs_dir, &nmi_longest_ns);
110 return 0;
111}
112fs_initcall(nmi_warning_debugfs);
113
114static void nmi_check_duration(struct nmiaction *action, u64 duration)
115{
116 int remainder_ns, decimal_msecs;
117
118 if (duration < nmi_longest_ns || duration < action->max_duration)
119 return;
120
121 action->max_duration = duration;
122
123 remainder_ns = do_div(duration, (1000 * 1000));
124 decimal_msecs = remainder_ns / 1000;
125
126 printk_ratelimited(KERN_INFO
127 "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
128 action->handler, duration, decimal_msecs);
129}
130
131static int nmi_handle(unsigned int type, struct pt_regs *regs)
132{
133 struct nmi_desc *desc = nmi_to_desc(type);
134 struct nmiaction *a;
135 int handled=0;
136
137 rcu_read_lock();
138
139 /*
140 * NMIs are edge-triggered, which means if you have enough
141 * of them concurrently, you can lose some because only one
142 * can be latched at any given time. Walk the whole list
143 * to handle those situations.
144 */
145 list_for_each_entry_rcu(a, &desc->head, list) {
146 int thishandled;
147 u64 delta;
148
149 delta = sched_clock();
150 thishandled = a->handler(type, regs);
151 handled += thishandled;
152 delta = sched_clock() - delta;
153 trace_nmi_handler(a->handler, (int)delta, thishandled);
154
155 nmi_check_duration(a, delta);
156 }
157
158 rcu_read_unlock();
159
160 /* return total number of NMI events handled */
161 return handled;
162}
163NOKPROBE_SYMBOL(nmi_handle);
164
165int __register_nmi_handler(unsigned int type, struct nmiaction *action)
166{
167 struct nmi_desc *desc = nmi_to_desc(type);
168 unsigned long flags;
169
170 if (WARN_ON_ONCE(!action->handler || !list_empty(&action->list)))
171 return -EINVAL;
172
173 raw_spin_lock_irqsave(&desc->lock, flags);
174
175 /*
176 * Indicate if there are multiple registrations on the
177 * internal NMI handler call chains (SERR and IO_CHECK).
178 */
179 WARN_ON_ONCE(type == NMI_SERR && !list_empty(&desc->head));
180 WARN_ON_ONCE(type == NMI_IO_CHECK && !list_empty(&desc->head));
181
182 /*
183 * some handlers need to be executed first otherwise a fake
184 * event confuses some handlers (kdump uses this flag)
185 */
186 if (action->flags & NMI_FLAG_FIRST)
187 list_add_rcu(&action->list, &desc->head);
188 else
189 list_add_tail_rcu(&action->list, &desc->head);
190
191 raw_spin_unlock_irqrestore(&desc->lock, flags);
192 return 0;
193}
194EXPORT_SYMBOL(__register_nmi_handler);
195
196void unregister_nmi_handler(unsigned int type, const char *name)
197{
198 struct nmi_desc *desc = nmi_to_desc(type);
199 struct nmiaction *n, *found = NULL;
200 unsigned long flags;
201
202 raw_spin_lock_irqsave(&desc->lock, flags);
203
204 list_for_each_entry_rcu(n, &desc->head, list) {
205 /*
206 * the name passed in to describe the nmi handler
207 * is used as the lookup key
208 */
209 if (!strcmp(n->name, name)) {
210 WARN(in_nmi(),
211 "Trying to free NMI (%s) from NMI context!\n", n->name);
212 list_del_rcu(&n->list);
213 found = n;
214 break;
215 }
216 }
217
218 raw_spin_unlock_irqrestore(&desc->lock, flags);
219 if (found) {
220 synchronize_rcu();
221 INIT_LIST_HEAD(&found->list);
222 }
223}
224EXPORT_SYMBOL_GPL(unregister_nmi_handler);
225
226static void
227pci_serr_error(unsigned char reason, struct pt_regs *regs)
228{
229 /* check to see if anyone registered against these types of errors */
230 if (nmi_handle(NMI_SERR, regs))
231 return;
232
233 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
234 reason, smp_processor_id());
235
236 if (panic_on_unrecovered_nmi)
237 nmi_panic(regs, "NMI: Not continuing");
238
239 pr_emerg("Dazed and confused, but trying to continue\n");
240
241 /* Clear and disable the PCI SERR error line. */
242 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_SERR;
243 outb(reason, NMI_REASON_PORT);
244}
245NOKPROBE_SYMBOL(pci_serr_error);
246
247static void
248io_check_error(unsigned char reason, struct pt_regs *regs)
249{
250 unsigned long i;
251
252 /* check to see if anyone registered against these types of errors */
253 if (nmi_handle(NMI_IO_CHECK, regs))
254 return;
255
256 pr_emerg(
257 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
258 reason, smp_processor_id());
259 show_regs(regs);
260
261 if (panic_on_io_nmi) {
262 nmi_panic(regs, "NMI IOCK error: Not continuing");
263
264 /*
265 * If we end up here, it means we have received an NMI while
266 * processing panic(). Simply return without delaying and
267 * re-enabling NMIs.
268 */
269 return;
270 }
271
272 /* Re-enable the IOCK line, wait for a few seconds */
273 reason = (reason & NMI_REASON_CLEAR_MASK) | NMI_REASON_CLEAR_IOCHK;
274 outb(reason, NMI_REASON_PORT);
275
276 i = 20000;
277 while (--i) {
278 touch_nmi_watchdog();
279 udelay(100);
280 }
281
282 reason &= ~NMI_REASON_CLEAR_IOCHK;
283 outb(reason, NMI_REASON_PORT);
284}
285NOKPROBE_SYMBOL(io_check_error);
286
287static void
288unknown_nmi_error(unsigned char reason, struct pt_regs *regs)
289{
290 int handled;
291
292 /*
293 * Use 'false' as back-to-back NMIs are dealt with one level up.
294 * Of course this makes having multiple 'unknown' handlers useless
295 * as only the first one is ever run (unless it can actually determine
296 * if it caused the NMI)
297 */
298 handled = nmi_handle(NMI_UNKNOWN, regs);
299 if (handled) {
300 __this_cpu_add(nmi_stats.unknown, handled);
301 return;
302 }
303
304 __this_cpu_add(nmi_stats.unknown, 1);
305
306 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
307 reason, smp_processor_id());
308
309 if (unknown_nmi_panic || panic_on_unrecovered_nmi)
310 nmi_panic(regs, "NMI: Not continuing");
311
312 pr_emerg("Dazed and confused, but trying to continue\n");
313}
314NOKPROBE_SYMBOL(unknown_nmi_error);
315
316static DEFINE_PER_CPU(bool, swallow_nmi);
317static DEFINE_PER_CPU(unsigned long, last_nmi_rip);
318
319static noinstr void default_do_nmi(struct pt_regs *regs)
320{
321 unsigned char reason = 0;
322 int handled;
323 bool b2b = false;
324
325 /*
326 * CPU-specific NMI must be processed before non-CPU-specific
327 * NMI, otherwise we may lose it, because the CPU-specific
328 * NMI can not be detected/processed on other CPUs.
329 */
330
331 /*
332 * Back-to-back NMIs are interesting because they can either
333 * be two NMI or more than two NMIs (any thing over two is dropped
334 * due to NMI being edge-triggered). If this is the second half
335 * of the back-to-back NMI, assume we dropped things and process
336 * more handlers. Otherwise reset the 'swallow' NMI behaviour
337 */
338 if (regs->ip == __this_cpu_read(last_nmi_rip))
339 b2b = true;
340 else
341 __this_cpu_write(swallow_nmi, false);
342
343 __this_cpu_write(last_nmi_rip, regs->ip);
344
345 instrumentation_begin();
346
347 if (microcode_nmi_handler_enabled() && microcode_nmi_handler())
348 goto out;
349
350 handled = nmi_handle(NMI_LOCAL, regs);
351 __this_cpu_add(nmi_stats.normal, handled);
352 if (handled) {
353 /*
354 * There are cases when a NMI handler handles multiple
355 * events in the current NMI. One of these events may
356 * be queued for in the next NMI. Because the event is
357 * already handled, the next NMI will result in an unknown
358 * NMI. Instead lets flag this for a potential NMI to
359 * swallow.
360 */
361 if (handled > 1)
362 __this_cpu_write(swallow_nmi, true);
363 goto out;
364 }
365
366 /*
367 * Non-CPU-specific NMI: NMI sources can be processed on any CPU.
368 *
369 * Another CPU may be processing panic routines while holding
370 * nmi_reason_lock. Check if the CPU issued the IPI for crash dumping,
371 * and if so, call its callback directly. If there is no CPU preparing
372 * crash dump, we simply loop here.
373 */
374 while (!raw_spin_trylock(&nmi_reason_lock)) {
375 run_crash_ipi_callback(regs);
376 cpu_relax();
377 }
378
379 reason = x86_platform.get_nmi_reason();
380
381 if (reason & NMI_REASON_MASK) {
382 if (reason & NMI_REASON_SERR)
383 pci_serr_error(reason, regs);
384 else if (reason & NMI_REASON_IOCHK)
385 io_check_error(reason, regs);
386#ifdef CONFIG_X86_32
387 /*
388 * Reassert NMI in case it became active
389 * meanwhile as it's edge-triggered:
390 */
391 reassert_nmi();
392#endif
393 __this_cpu_add(nmi_stats.external, 1);
394 raw_spin_unlock(&nmi_reason_lock);
395 goto out;
396 }
397 raw_spin_unlock(&nmi_reason_lock);
398
399 /*
400 * Only one NMI can be latched at a time. To handle
401 * this we may process multiple nmi handlers at once to
402 * cover the case where an NMI is dropped. The downside
403 * to this approach is we may process an NMI prematurely,
404 * while its real NMI is sitting latched. This will cause
405 * an unknown NMI on the next run of the NMI processing.
406 *
407 * We tried to flag that condition above, by setting the
408 * swallow_nmi flag when we process more than one event.
409 * This condition is also only present on the second half
410 * of a back-to-back NMI, so we flag that condition too.
411 *
412 * If both are true, we assume we already processed this
413 * NMI previously and we swallow it. Otherwise we reset
414 * the logic.
415 *
416 * There are scenarios where we may accidentally swallow
417 * a 'real' unknown NMI. For example, while processing
418 * a perf NMI another perf NMI comes in along with a
419 * 'real' unknown NMI. These two NMIs get combined into
420 * one (as described above). When the next NMI gets
421 * processed, it will be flagged by perf as handled, but
422 * no one will know that there was a 'real' unknown NMI sent
423 * also. As a result it gets swallowed. Or if the first
424 * perf NMI returns two events handled then the second
425 * NMI will get eaten by the logic below, again losing a
426 * 'real' unknown NMI. But this is the best we can do
427 * for now.
428 */
429 if (b2b && __this_cpu_read(swallow_nmi))
430 __this_cpu_add(nmi_stats.swallow, 1);
431 else
432 unknown_nmi_error(reason, regs);
433
434out:
435 instrumentation_end();
436}
437
438/*
439 * NMIs can page fault or hit breakpoints which will cause it to lose
440 * its NMI context with the CPU when the breakpoint or page fault does an IRET.
441 *
442 * As a result, NMIs can nest if NMIs get unmasked due an IRET during
443 * NMI processing. On x86_64, the asm glue protects us from nested NMIs
444 * if the outer NMI came from kernel mode, but we can still nest if the
445 * outer NMI came from user mode.
446 *
447 * To handle these nested NMIs, we have three states:
448 *
449 * 1) not running
450 * 2) executing
451 * 3) latched
452 *
453 * When no NMI is in progress, it is in the "not running" state.
454 * When an NMI comes in, it goes into the "executing" state.
455 * Normally, if another NMI is triggered, it does not interrupt
456 * the running NMI and the HW will simply latch it so that when
457 * the first NMI finishes, it will restart the second NMI.
458 * (Note, the latch is binary, thus multiple NMIs triggering,
459 * when one is running, are ignored. Only one NMI is restarted.)
460 *
461 * If an NMI executes an iret, another NMI can preempt it. We do not
462 * want to allow this new NMI to run, but we want to execute it when the
463 * first one finishes. We set the state to "latched", and the exit of
464 * the first NMI will perform a dec_return, if the result is zero
465 * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the
466 * dec_return would have set the state to NMI_EXECUTING (what we want it
467 * to be when we are running). In this case, we simply jump back to
468 * rerun the NMI handler again, and restart the 'latched' NMI.
469 *
470 * No trap (breakpoint or page fault) should be hit before nmi_restart,
471 * thus there is no race between the first check of state for NOT_RUNNING
472 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
473 * at this point.
474 *
475 * In case the NMI takes a page fault, we need to save off the CR2
476 * because the NMI could have preempted another page fault and corrupt
477 * the CR2 that is about to be read. As nested NMIs must be restarted
478 * and they can not take breakpoints or page faults, the update of the
479 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
480 * Otherwise, there would be a race of another nested NMI coming in
481 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
482 */
483enum nmi_states {
484 NMI_NOT_RUNNING = 0,
485 NMI_EXECUTING,
486 NMI_LATCHED,
487};
488static DEFINE_PER_CPU(enum nmi_states, nmi_state);
489static DEFINE_PER_CPU(unsigned long, nmi_cr2);
490static DEFINE_PER_CPU(unsigned long, nmi_dr7);
491
492DEFINE_IDTENTRY_RAW(exc_nmi)
493{
494 irqentry_state_t irq_state;
495 struct nmi_stats *nsp = this_cpu_ptr(&nmi_stats);
496
497 /*
498 * Re-enable NMIs right here when running as an SEV-ES guest. This might
499 * cause nested NMIs, but those can be handled safely.
500 */
501 sev_es_nmi_complete();
502 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU))
503 raw_atomic_long_inc(&nsp->idt_calls);
504
505 if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) {
506 if (microcode_nmi_handler_enabled())
507 microcode_offline_nmi_handler();
508 return;
509 }
510
511 if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) {
512 this_cpu_write(nmi_state, NMI_LATCHED);
513 return;
514 }
515 this_cpu_write(nmi_state, NMI_EXECUTING);
516 this_cpu_write(nmi_cr2, read_cr2());
517
518nmi_restart:
519 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
520 WRITE_ONCE(nsp->idt_seq, nsp->idt_seq + 1);
521 WARN_ON_ONCE(!(nsp->idt_seq & 0x1));
522 WRITE_ONCE(nsp->recv_jiffies, jiffies);
523 }
524
525 /*
526 * Needs to happen before DR7 is accessed, because the hypervisor can
527 * intercept DR7 reads/writes, turning those into #VC exceptions.
528 */
529 sev_es_ist_enter(regs);
530
531 this_cpu_write(nmi_dr7, local_db_save());
532
533 irq_state = irqentry_nmi_enter(regs);
534
535 inc_irq_stat(__nmi_count);
536
537 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU) && ignore_nmis) {
538 WRITE_ONCE(nsp->idt_ignored, nsp->idt_ignored + 1);
539 } else if (!ignore_nmis) {
540 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
541 WRITE_ONCE(nsp->idt_nmi_seq, nsp->idt_nmi_seq + 1);
542 WARN_ON_ONCE(!(nsp->idt_nmi_seq & 0x1));
543 }
544 default_do_nmi(regs);
545 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
546 WRITE_ONCE(nsp->idt_nmi_seq, nsp->idt_nmi_seq + 1);
547 WARN_ON_ONCE(nsp->idt_nmi_seq & 0x1);
548 }
549 }
550
551 irqentry_nmi_exit(regs, irq_state);
552
553 local_db_restore(this_cpu_read(nmi_dr7));
554
555 sev_es_ist_exit();
556
557 if (unlikely(this_cpu_read(nmi_cr2) != read_cr2()))
558 write_cr2(this_cpu_read(nmi_cr2));
559 if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) {
560 WRITE_ONCE(nsp->idt_seq, nsp->idt_seq + 1);
561 WARN_ON_ONCE(nsp->idt_seq & 0x1);
562 WRITE_ONCE(nsp->recv_jiffies, jiffies);
563 }
564 if (this_cpu_dec_return(nmi_state))
565 goto nmi_restart;
566}
567
568#if IS_ENABLED(CONFIG_KVM_INTEL)
569DEFINE_IDTENTRY_RAW(exc_nmi_kvm_vmx)
570{
571 exc_nmi(regs);
572}
573#if IS_MODULE(CONFIG_KVM_INTEL)
574EXPORT_SYMBOL_GPL(asm_exc_nmi_kvm_vmx);
575#endif
576#endif
577
578#ifdef CONFIG_NMI_CHECK_CPU
579
580static char *nmi_check_stall_msg[] = {
581/* */
582/* +--------- nsp->idt_seq_snap & 0x1: CPU is in NMI handler. */
583/* | +------ cpu_is_offline(cpu) */
584/* | | +--- nsp->idt_calls_snap != atomic_long_read(&nsp->idt_calls): */
585/* | | | NMI handler has been invoked. */
586/* | | | */
587/* V V V */
588/* 0 0 0 */ "NMIs are not reaching exc_nmi() handler",
589/* 0 0 1 */ "exc_nmi() handler is ignoring NMIs",
590/* 0 1 0 */ "CPU is offline and NMIs are not reaching exc_nmi() handler",
591/* 0 1 1 */ "CPU is offline and exc_nmi() handler is legitimately ignoring NMIs",
592/* 1 0 0 */ "CPU is in exc_nmi() handler and no further NMIs are reaching handler",
593/* 1 0 1 */ "CPU is in exc_nmi() handler which is legitimately ignoring NMIs",
594/* 1 1 0 */ "CPU is offline in exc_nmi() handler and no more NMIs are reaching exc_nmi() handler",
595/* 1 1 1 */ "CPU is offline in exc_nmi() handler which is legitimately ignoring NMIs",
596};
597
598void nmi_backtrace_stall_snap(const struct cpumask *btp)
599{
600 int cpu;
601 struct nmi_stats *nsp;
602
603 for_each_cpu(cpu, btp) {
604 nsp = per_cpu_ptr(&nmi_stats, cpu);
605 nsp->idt_seq_snap = READ_ONCE(nsp->idt_seq);
606 nsp->idt_nmi_seq_snap = READ_ONCE(nsp->idt_nmi_seq);
607 nsp->idt_ignored_snap = READ_ONCE(nsp->idt_ignored);
608 nsp->idt_calls_snap = atomic_long_read(&nsp->idt_calls);
609 }
610}
611
612void nmi_backtrace_stall_check(const struct cpumask *btp)
613{
614 int cpu;
615 int idx;
616 unsigned long nmi_seq;
617 unsigned long j = jiffies;
618 char *modp;
619 char *msgp;
620 char *msghp;
621 struct nmi_stats *nsp;
622
623 for_each_cpu(cpu, btp) {
624 nsp = per_cpu_ptr(&nmi_stats, cpu);
625 modp = "";
626 msghp = "";
627 nmi_seq = READ_ONCE(nsp->idt_nmi_seq);
628 if (nsp->idt_nmi_seq_snap + 1 == nmi_seq && (nmi_seq & 0x1)) {
629 msgp = "CPU entered NMI handler function, but has not exited";
630 } else if ((nsp->idt_nmi_seq_snap & 0x1) != (nmi_seq & 0x1)) {
631 msgp = "CPU is handling NMIs";
632 } else {
633 idx = ((nsp->idt_seq_snap & 0x1) << 2) |
634 (cpu_is_offline(cpu) << 1) |
635 (nsp->idt_calls_snap != atomic_long_read(&nsp->idt_calls));
636 msgp = nmi_check_stall_msg[idx];
637 if (nsp->idt_ignored_snap != READ_ONCE(nsp->idt_ignored) && (idx & 0x1))
638 modp = ", but OK because ignore_nmis was set";
639 if (nmi_seq & ~0x1)
640 msghp = " (CPU currently in NMI handler function)";
641 else if (nsp->idt_nmi_seq_snap + 1 == nmi_seq)
642 msghp = " (CPU exited one NMI handler function)";
643 }
644 pr_alert("%s: CPU %d: %s%s%s, last activity: %lu jiffies ago.\n",
645 __func__, cpu, msgp, modp, msghp, j - READ_ONCE(nsp->recv_jiffies));
646 }
647}
648
649#endif
650
651void stop_nmi(void)
652{
653 ignore_nmis++;
654}
655
656void restart_nmi(void)
657{
658 ignore_nmis--;
659}
660
661/* reset the back-to-back NMI logic */
662void local_touch_nmi(void)
663{
664 __this_cpu_write(last_nmi_rip, 0);
665}
666EXPORT_SYMBOL_GPL(local_touch_nmi);