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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/guest.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11#include <linux/bits.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/nospec.h>
15#include <linux/kvm_host.h>
16#include <linux/module.h>
17#include <linux/stddef.h>
18#include <linux/string.h>
19#include <linux/vmalloc.h>
20#include <linux/fs.h>
21#include <kvm/arm_psci.h>
22#include <asm/cputype.h>
23#include <linux/uaccess.h>
24#include <asm/fpsimd.h>
25#include <asm/kvm.h>
26#include <asm/kvm_emulate.h>
27#include <asm/kvm_coproc.h>
28#include <asm/kvm_host.h>
29#include <asm/sigcontext.h>
30
31#include "trace.h"
32
33#define VM_STAT(x) { #x, offsetof(struct kvm, stat.x), KVM_STAT_VM }
34#define VCPU_STAT(x) { #x, offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU }
35
36struct kvm_stats_debugfs_item debugfs_entries[] = {
37 VCPU_STAT(hvc_exit_stat),
38 VCPU_STAT(wfe_exit_stat),
39 VCPU_STAT(wfi_exit_stat),
40 VCPU_STAT(mmio_exit_user),
41 VCPU_STAT(mmio_exit_kernel),
42 VCPU_STAT(exits),
43 { NULL }
44};
45
46int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
47{
48 return 0;
49}
50
51static bool core_reg_offset_is_vreg(u64 off)
52{
53 return off >= KVM_REG_ARM_CORE_REG(fp_regs.vregs) &&
54 off < KVM_REG_ARM_CORE_REG(fp_regs.fpsr);
55}
56
57static u64 core_reg_offset_from_id(u64 id)
58{
59 return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
60}
61
62static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
63{
64 int size;
65
66 switch (off) {
67 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
68 KVM_REG_ARM_CORE_REG(regs.regs[30]):
69 case KVM_REG_ARM_CORE_REG(regs.sp):
70 case KVM_REG_ARM_CORE_REG(regs.pc):
71 case KVM_REG_ARM_CORE_REG(regs.pstate):
72 case KVM_REG_ARM_CORE_REG(sp_el1):
73 case KVM_REG_ARM_CORE_REG(elr_el1):
74 case KVM_REG_ARM_CORE_REG(spsr[0]) ...
75 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]):
76 size = sizeof(__u64);
77 break;
78
79 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
80 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
81 size = sizeof(__uint128_t);
82 break;
83
84 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
85 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
86 size = sizeof(__u32);
87 break;
88
89 default:
90 return -EINVAL;
91 }
92
93 if (!IS_ALIGNED(off, size / sizeof(__u32)))
94 return -EINVAL;
95
96 /*
97 * The KVM_REG_ARM64_SVE regs must be used instead of
98 * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on
99 * SVE-enabled vcpus:
100 */
101 if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
102 return -EINVAL;
103
104 return size;
105}
106
107static int validate_core_offset(const struct kvm_vcpu *vcpu,
108 const struct kvm_one_reg *reg)
109{
110 u64 off = core_reg_offset_from_id(reg->id);
111 int size = core_reg_size_from_offset(vcpu, off);
112
113 if (size < 0)
114 return -EINVAL;
115
116 if (KVM_REG_SIZE(reg->id) != size)
117 return -EINVAL;
118
119 return 0;
120}
121
122static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
123{
124 /*
125 * Because the kvm_regs structure is a mix of 32, 64 and
126 * 128bit fields, we index it as if it was a 32bit
127 * array. Hence below, nr_regs is the number of entries, and
128 * off the index in the "array".
129 */
130 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
131 struct kvm_regs *regs = vcpu_gp_regs(vcpu);
132 int nr_regs = sizeof(*regs) / sizeof(__u32);
133 u32 off;
134
135 /* Our ID is an index into the kvm_regs struct. */
136 off = core_reg_offset_from_id(reg->id);
137 if (off >= nr_regs ||
138 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
139 return -ENOENT;
140
141 if (validate_core_offset(vcpu, reg))
142 return -EINVAL;
143
144 if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id)))
145 return -EFAULT;
146
147 return 0;
148}
149
150static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
151{
152 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
153 struct kvm_regs *regs = vcpu_gp_regs(vcpu);
154 int nr_regs = sizeof(*regs) / sizeof(__u32);
155 __uint128_t tmp;
156 void *valp = &tmp;
157 u64 off;
158 int err = 0;
159
160 /* Our ID is an index into the kvm_regs struct. */
161 off = core_reg_offset_from_id(reg->id);
162 if (off >= nr_regs ||
163 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
164 return -ENOENT;
165
166 if (validate_core_offset(vcpu, reg))
167 return -EINVAL;
168
169 if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
170 return -EINVAL;
171
172 if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
173 err = -EFAULT;
174 goto out;
175 }
176
177 if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
178 u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK;
179 switch (mode) {
180 case PSR_AA32_MODE_USR:
181 if (!system_supports_32bit_el0())
182 return -EINVAL;
183 break;
184 case PSR_AA32_MODE_FIQ:
185 case PSR_AA32_MODE_IRQ:
186 case PSR_AA32_MODE_SVC:
187 case PSR_AA32_MODE_ABT:
188 case PSR_AA32_MODE_UND:
189 if (!vcpu_el1_is_32bit(vcpu))
190 return -EINVAL;
191 break;
192 case PSR_MODE_EL0t:
193 case PSR_MODE_EL1t:
194 case PSR_MODE_EL1h:
195 if (vcpu_el1_is_32bit(vcpu))
196 return -EINVAL;
197 break;
198 default:
199 err = -EINVAL;
200 goto out;
201 }
202 }
203
204 memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id));
205out:
206 return err;
207}
208
209#define vq_word(vq) (((vq) - SVE_VQ_MIN) / 64)
210#define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64)
211#define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq)))
212
213static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
214{
215 unsigned int max_vq, vq;
216 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
217
218 if (!vcpu_has_sve(vcpu))
219 return -ENOENT;
220
221 if (WARN_ON(!sve_vl_valid(vcpu->arch.sve_max_vl)))
222 return -EINVAL;
223
224 memset(vqs, 0, sizeof(vqs));
225
226 max_vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
227 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
228 if (sve_vq_available(vq))
229 vqs[vq_word(vq)] |= vq_mask(vq);
230
231 if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs)))
232 return -EFAULT;
233
234 return 0;
235}
236
237static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
238{
239 unsigned int max_vq, vq;
240 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
241
242 if (!vcpu_has_sve(vcpu))
243 return -ENOENT;
244
245 if (kvm_arm_vcpu_sve_finalized(vcpu))
246 return -EPERM; /* too late! */
247
248 if (WARN_ON(vcpu->arch.sve_state))
249 return -EINVAL;
250
251 if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs)))
252 return -EFAULT;
253
254 max_vq = 0;
255 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; ++vq)
256 if (vq_present(vqs, vq))
257 max_vq = vq;
258
259 if (max_vq > sve_vq_from_vl(kvm_sve_max_vl))
260 return -EINVAL;
261
262 /*
263 * Vector lengths supported by the host can't currently be
264 * hidden from the guest individually: instead we can only set a
265 * maxmium via ZCR_EL2.LEN. So, make sure the available vector
266 * lengths match the set requested exactly up to the requested
267 * maximum:
268 */
269 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
270 if (vq_present(vqs, vq) != sve_vq_available(vq))
271 return -EINVAL;
272
273 /* Can't run with no vector lengths at all: */
274 if (max_vq < SVE_VQ_MIN)
275 return -EINVAL;
276
277 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */
278 vcpu->arch.sve_max_vl = sve_vl_from_vq(max_vq);
279
280 return 0;
281}
282
283#define SVE_REG_SLICE_SHIFT 0
284#define SVE_REG_SLICE_BITS 5
285#define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS)
286#define SVE_REG_ID_BITS 5
287
288#define SVE_REG_SLICE_MASK \
289 GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1, \
290 SVE_REG_SLICE_SHIFT)
291#define SVE_REG_ID_MASK \
292 GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)
293
294#define SVE_NUM_SLICES (1 << SVE_REG_SLICE_BITS)
295
296#define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0))
297#define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0))
298
299/*
300 * Number of register slices required to cover each whole SVE register.
301 * NOTE: Only the first slice every exists, for now.
302 * If you are tempted to modify this, you must also rework sve_reg_to_region()
303 * to match:
304 */
305#define vcpu_sve_slices(vcpu) 1
306
307/* Bounds of a single SVE register slice within vcpu->arch.sve_state */
308struct sve_state_reg_region {
309 unsigned int koffset; /* offset into sve_state in kernel memory */
310 unsigned int klen; /* length in kernel memory */
311 unsigned int upad; /* extra trailing padding in user memory */
312};
313
314/*
315 * Validate SVE register ID and get sanitised bounds for user/kernel SVE
316 * register copy
317 */
318static int sve_reg_to_region(struct sve_state_reg_region *region,
319 struct kvm_vcpu *vcpu,
320 const struct kvm_one_reg *reg)
321{
322 /* reg ID ranges for Z- registers */
323 const u64 zreg_id_min = KVM_REG_ARM64_SVE_ZREG(0, 0);
324 const u64 zreg_id_max = KVM_REG_ARM64_SVE_ZREG(SVE_NUM_ZREGS - 1,
325 SVE_NUM_SLICES - 1);
326
327 /* reg ID ranges for P- registers and FFR (which are contiguous) */
328 const u64 preg_id_min = KVM_REG_ARM64_SVE_PREG(0, 0);
329 const u64 preg_id_max = KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1);
330
331 unsigned int vq;
332 unsigned int reg_num;
333
334 unsigned int reqoffset, reqlen; /* User-requested offset and length */
335 unsigned int maxlen; /* Maxmimum permitted length */
336
337 size_t sve_state_size;
338
339 const u64 last_preg_id = KVM_REG_ARM64_SVE_PREG(SVE_NUM_PREGS - 1,
340 SVE_NUM_SLICES - 1);
341
342 /* Verify that the P-regs and FFR really do have contiguous IDs: */
343 BUILD_BUG_ON(KVM_REG_ARM64_SVE_FFR(0) != last_preg_id + 1);
344
345 /* Verify that we match the UAPI header: */
346 BUILD_BUG_ON(SVE_NUM_SLICES != KVM_ARM64_SVE_MAX_SLICES);
347
348 reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT;
349
350 if (reg->id >= zreg_id_min && reg->id <= zreg_id_max) {
351 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
352 return -ENOENT;
353
354 vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
355
356 reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -
357 SVE_SIG_REGS_OFFSET;
358 reqlen = KVM_SVE_ZREG_SIZE;
359 maxlen = SVE_SIG_ZREG_SIZE(vq);
360 } else if (reg->id >= preg_id_min && reg->id <= preg_id_max) {
361 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
362 return -ENOENT;
363
364 vq = sve_vq_from_vl(vcpu->arch.sve_max_vl);
365
366 reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -
367 SVE_SIG_REGS_OFFSET;
368 reqlen = KVM_SVE_PREG_SIZE;
369 maxlen = SVE_SIG_PREG_SIZE(vq);
370 } else {
371 return -EINVAL;
372 }
373
374 sve_state_size = vcpu_sve_state_size(vcpu);
375 if (WARN_ON(!sve_state_size))
376 return -EINVAL;
377
378 region->koffset = array_index_nospec(reqoffset, sve_state_size);
379 region->klen = min(maxlen, reqlen);
380 region->upad = reqlen - region->klen;
381
382 return 0;
383}
384
385static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
386{
387 int ret;
388 struct sve_state_reg_region region;
389 char __user *uptr = (char __user *)reg->addr;
390
391 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
392 if (reg->id == KVM_REG_ARM64_SVE_VLS)
393 return get_sve_vls(vcpu, reg);
394
395 /* Try to interpret reg ID as an architectural SVE register... */
396 ret = sve_reg_to_region(®ion, vcpu, reg);
397 if (ret)
398 return ret;
399
400 if (!kvm_arm_vcpu_sve_finalized(vcpu))
401 return -EPERM;
402
403 if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset,
404 region.klen) ||
405 clear_user(uptr + region.klen, region.upad))
406 return -EFAULT;
407
408 return 0;
409}
410
411static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
412{
413 int ret;
414 struct sve_state_reg_region region;
415 const char __user *uptr = (const char __user *)reg->addr;
416
417 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
418 if (reg->id == KVM_REG_ARM64_SVE_VLS)
419 return set_sve_vls(vcpu, reg);
420
421 /* Try to interpret reg ID as an architectural SVE register... */
422 ret = sve_reg_to_region(®ion, vcpu, reg);
423 if (ret)
424 return ret;
425
426 if (!kvm_arm_vcpu_sve_finalized(vcpu))
427 return -EPERM;
428
429 if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
430 region.klen))
431 return -EFAULT;
432
433 return 0;
434}
435
436int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
437{
438 return -EINVAL;
439}
440
441int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
442{
443 return -EINVAL;
444}
445
446static int copy_core_reg_indices(const struct kvm_vcpu *vcpu,
447 u64 __user *uindices)
448{
449 unsigned int i;
450 int n = 0;
451
452 for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
453 u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i;
454 int size = core_reg_size_from_offset(vcpu, i);
455
456 if (size < 0)
457 continue;
458
459 switch (size) {
460 case sizeof(__u32):
461 reg |= KVM_REG_SIZE_U32;
462 break;
463
464 case sizeof(__u64):
465 reg |= KVM_REG_SIZE_U64;
466 break;
467
468 case sizeof(__uint128_t):
469 reg |= KVM_REG_SIZE_U128;
470 break;
471
472 default:
473 WARN_ON(1);
474 continue;
475 }
476
477 if (uindices) {
478 if (put_user(reg, uindices))
479 return -EFAULT;
480 uindices++;
481 }
482
483 n++;
484 }
485
486 return n;
487}
488
489static unsigned long num_core_regs(const struct kvm_vcpu *vcpu)
490{
491 return copy_core_reg_indices(vcpu, NULL);
492}
493
494/**
495 * ARM64 versions of the TIMER registers, always available on arm64
496 */
497
498#define NUM_TIMER_REGS 3
499
500static bool is_timer_reg(u64 index)
501{
502 switch (index) {
503 case KVM_REG_ARM_TIMER_CTL:
504 case KVM_REG_ARM_TIMER_CNT:
505 case KVM_REG_ARM_TIMER_CVAL:
506 return true;
507 }
508 return false;
509}
510
511static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
512{
513 if (put_user(KVM_REG_ARM_TIMER_CTL, uindices))
514 return -EFAULT;
515 uindices++;
516 if (put_user(KVM_REG_ARM_TIMER_CNT, uindices))
517 return -EFAULT;
518 uindices++;
519 if (put_user(KVM_REG_ARM_TIMER_CVAL, uindices))
520 return -EFAULT;
521
522 return 0;
523}
524
525static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
526{
527 void __user *uaddr = (void __user *)(long)reg->addr;
528 u64 val;
529 int ret;
530
531 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
532 if (ret != 0)
533 return -EFAULT;
534
535 return kvm_arm_timer_set_reg(vcpu, reg->id, val);
536}
537
538static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
539{
540 void __user *uaddr = (void __user *)(long)reg->addr;
541 u64 val;
542
543 val = kvm_arm_timer_get_reg(vcpu, reg->id);
544 return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0;
545}
546
547static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu)
548{
549 const unsigned int slices = vcpu_sve_slices(vcpu);
550
551 if (!vcpu_has_sve(vcpu))
552 return 0;
553
554 /* Policed by KVM_GET_REG_LIST: */
555 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
556
557 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */)
558 + 1; /* KVM_REG_ARM64_SVE_VLS */
559}
560
561static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu,
562 u64 __user *uindices)
563{
564 const unsigned int slices = vcpu_sve_slices(vcpu);
565 u64 reg;
566 unsigned int i, n;
567 int num_regs = 0;
568
569 if (!vcpu_has_sve(vcpu))
570 return 0;
571
572 /* Policed by KVM_GET_REG_LIST: */
573 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
574
575 /*
576 * Enumerate this first, so that userspace can save/restore in
577 * the order reported by KVM_GET_REG_LIST:
578 */
579 reg = KVM_REG_ARM64_SVE_VLS;
580 if (put_user(reg, uindices++))
581 return -EFAULT;
582 ++num_regs;
583
584 for (i = 0; i < slices; i++) {
585 for (n = 0; n < SVE_NUM_ZREGS; n++) {
586 reg = KVM_REG_ARM64_SVE_ZREG(n, i);
587 if (put_user(reg, uindices++))
588 return -EFAULT;
589 num_regs++;
590 }
591
592 for (n = 0; n < SVE_NUM_PREGS; n++) {
593 reg = KVM_REG_ARM64_SVE_PREG(n, i);
594 if (put_user(reg, uindices++))
595 return -EFAULT;
596 num_regs++;
597 }
598
599 reg = KVM_REG_ARM64_SVE_FFR(i);
600 if (put_user(reg, uindices++))
601 return -EFAULT;
602 num_regs++;
603 }
604
605 return num_regs;
606}
607
608/**
609 * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
610 *
611 * This is for all registers.
612 */
613unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
614{
615 unsigned long res = 0;
616
617 res += num_core_regs(vcpu);
618 res += num_sve_regs(vcpu);
619 res += kvm_arm_num_sys_reg_descs(vcpu);
620 res += kvm_arm_get_fw_num_regs(vcpu);
621 res += NUM_TIMER_REGS;
622
623 return res;
624}
625
626/**
627 * kvm_arm_copy_reg_indices - get indices of all registers.
628 *
629 * We do core registers right here, then we append system regs.
630 */
631int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
632{
633 int ret;
634
635 ret = copy_core_reg_indices(vcpu, uindices);
636 if (ret < 0)
637 return ret;
638 uindices += ret;
639
640 ret = copy_sve_reg_indices(vcpu, uindices);
641 if (ret < 0)
642 return ret;
643 uindices += ret;
644
645 ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
646 if (ret < 0)
647 return ret;
648 uindices += kvm_arm_get_fw_num_regs(vcpu);
649
650 ret = copy_timer_indices(vcpu, uindices);
651 if (ret < 0)
652 return ret;
653 uindices += NUM_TIMER_REGS;
654
655 return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
656}
657
658int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
659{
660 /* We currently use nothing arch-specific in upper 32 bits */
661 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
662 return -EINVAL;
663
664 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
665 case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg);
666 case KVM_REG_ARM_FW: return kvm_arm_get_fw_reg(vcpu, reg);
667 case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg);
668 }
669
670 if (is_timer_reg(reg->id))
671 return get_timer_reg(vcpu, reg);
672
673 return kvm_arm_sys_reg_get_reg(vcpu, reg);
674}
675
676int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
677{
678 /* We currently use nothing arch-specific in upper 32 bits */
679 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
680 return -EINVAL;
681
682 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
683 case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg);
684 case KVM_REG_ARM_FW: return kvm_arm_set_fw_reg(vcpu, reg);
685 case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
686 }
687
688 if (is_timer_reg(reg->id))
689 return set_timer_reg(vcpu, reg);
690
691 return kvm_arm_sys_reg_set_reg(vcpu, reg);
692}
693
694int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
695 struct kvm_sregs *sregs)
696{
697 return -EINVAL;
698}
699
700int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
701 struct kvm_sregs *sregs)
702{
703 return -EINVAL;
704}
705
706int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
707 struct kvm_vcpu_events *events)
708{
709 events->exception.serror_pending = !!(vcpu->arch.hcr_el2 & HCR_VSE);
710 events->exception.serror_has_esr = cpus_have_const_cap(ARM64_HAS_RAS_EXTN);
711
712 if (events->exception.serror_pending && events->exception.serror_has_esr)
713 events->exception.serror_esr = vcpu_get_vsesr(vcpu);
714
715 return 0;
716}
717
718int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
719 struct kvm_vcpu_events *events)
720{
721 bool serror_pending = events->exception.serror_pending;
722 bool has_esr = events->exception.serror_has_esr;
723
724 if (serror_pending && has_esr) {
725 if (!cpus_have_const_cap(ARM64_HAS_RAS_EXTN))
726 return -EINVAL;
727
728 if (!((events->exception.serror_esr) & ~ESR_ELx_ISS_MASK))
729 kvm_set_sei_esr(vcpu, events->exception.serror_esr);
730 else
731 return -EINVAL;
732 } else if (serror_pending) {
733 kvm_inject_vabt(vcpu);
734 }
735
736 return 0;
737}
738
739int __attribute_const__ kvm_target_cpu(void)
740{
741 unsigned long implementor = read_cpuid_implementor();
742 unsigned long part_number = read_cpuid_part_number();
743
744 switch (implementor) {
745 case ARM_CPU_IMP_ARM:
746 switch (part_number) {
747 case ARM_CPU_PART_AEM_V8:
748 return KVM_ARM_TARGET_AEM_V8;
749 case ARM_CPU_PART_FOUNDATION:
750 return KVM_ARM_TARGET_FOUNDATION_V8;
751 case ARM_CPU_PART_CORTEX_A53:
752 return KVM_ARM_TARGET_CORTEX_A53;
753 case ARM_CPU_PART_CORTEX_A57:
754 return KVM_ARM_TARGET_CORTEX_A57;
755 }
756 break;
757 case ARM_CPU_IMP_APM:
758 switch (part_number) {
759 case APM_CPU_PART_POTENZA:
760 return KVM_ARM_TARGET_XGENE_POTENZA;
761 }
762 break;
763 }
764
765 /* Return a default generic target */
766 return KVM_ARM_TARGET_GENERIC_V8;
767}
768
769int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init)
770{
771 int target = kvm_target_cpu();
772
773 if (target < 0)
774 return -ENODEV;
775
776 memset(init, 0, sizeof(*init));
777
778 /*
779 * For now, we don't return any features.
780 * In future, we might use features to return target
781 * specific features available for the preferred
782 * target type.
783 */
784 init->target = (__u32)target;
785
786 return 0;
787}
788
789int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
790{
791 return -EINVAL;
792}
793
794int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
795{
796 return -EINVAL;
797}
798
799int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
800 struct kvm_translation *tr)
801{
802 return -EINVAL;
803}
804
805#define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
806 KVM_GUESTDBG_USE_SW_BP | \
807 KVM_GUESTDBG_USE_HW | \
808 KVM_GUESTDBG_SINGLESTEP)
809
810/**
811 * kvm_arch_vcpu_ioctl_set_guest_debug - set up guest debugging
812 * @kvm: pointer to the KVM struct
813 * @kvm_guest_debug: the ioctl data buffer
814 *
815 * This sets up and enables the VM for guest debugging. Userspace
816 * passes in a control flag to enable different debug types and
817 * potentially other architecture specific information in the rest of
818 * the structure.
819 */
820int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
821 struct kvm_guest_debug *dbg)
822{
823 int ret = 0;
824
825 trace_kvm_set_guest_debug(vcpu, dbg->control);
826
827 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
828 ret = -EINVAL;
829 goto out;
830 }
831
832 if (dbg->control & KVM_GUESTDBG_ENABLE) {
833 vcpu->guest_debug = dbg->control;
834
835 /* Hardware assisted Break and Watch points */
836 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
837 vcpu->arch.external_debug_state = dbg->arch;
838 }
839
840 } else {
841 /* If not enabled clear all flags */
842 vcpu->guest_debug = 0;
843 }
844
845out:
846 return ret;
847}
848
849int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
850 struct kvm_device_attr *attr)
851{
852 int ret;
853
854 switch (attr->group) {
855 case KVM_ARM_VCPU_PMU_V3_CTRL:
856 ret = kvm_arm_pmu_v3_set_attr(vcpu, attr);
857 break;
858 case KVM_ARM_VCPU_TIMER_CTRL:
859 ret = kvm_arm_timer_set_attr(vcpu, attr);
860 break;
861 default:
862 ret = -ENXIO;
863 break;
864 }
865
866 return ret;
867}
868
869int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
870 struct kvm_device_attr *attr)
871{
872 int ret;
873
874 switch (attr->group) {
875 case KVM_ARM_VCPU_PMU_V3_CTRL:
876 ret = kvm_arm_pmu_v3_get_attr(vcpu, attr);
877 break;
878 case KVM_ARM_VCPU_TIMER_CTRL:
879 ret = kvm_arm_timer_get_attr(vcpu, attr);
880 break;
881 default:
882 ret = -ENXIO;
883 break;
884 }
885
886 return ret;
887}
888
889int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
890 struct kvm_device_attr *attr)
891{
892 int ret;
893
894 switch (attr->group) {
895 case KVM_ARM_VCPU_PMU_V3_CTRL:
896 ret = kvm_arm_pmu_v3_has_attr(vcpu, attr);
897 break;
898 case KVM_ARM_VCPU_TIMER_CTRL:
899 ret = kvm_arm_timer_has_attr(vcpu, attr);
900 break;
901 default:
902 ret = -ENXIO;
903 break;
904 }
905
906 return ret;
907}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/guest.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 */
10
11#include <linux/bits.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/nospec.h>
15#include <linux/kvm_host.h>
16#include <linux/module.h>
17#include <linux/stddef.h>
18#include <linux/string.h>
19#include <linux/vmalloc.h>
20#include <linux/fs.h>
21#include <kvm/arm_hypercalls.h>
22#include <asm/cputype.h>
23#include <linux/uaccess.h>
24#include <asm/fpsimd.h>
25#include <asm/kvm.h>
26#include <asm/kvm_emulate.h>
27#include <asm/kvm_nested.h>
28#include <asm/sigcontext.h>
29
30#include "trace.h"
31
32const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
33 KVM_GENERIC_VM_STATS()
34};
35
36const struct kvm_stats_header kvm_vm_stats_header = {
37 .name_size = KVM_STATS_NAME_SIZE,
38 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
39 .id_offset = sizeof(struct kvm_stats_header),
40 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
41 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
42 sizeof(kvm_vm_stats_desc),
43};
44
45const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
46 KVM_GENERIC_VCPU_STATS(),
47 STATS_DESC_COUNTER(VCPU, hvc_exit_stat),
48 STATS_DESC_COUNTER(VCPU, wfe_exit_stat),
49 STATS_DESC_COUNTER(VCPU, wfi_exit_stat),
50 STATS_DESC_COUNTER(VCPU, mmio_exit_user),
51 STATS_DESC_COUNTER(VCPU, mmio_exit_kernel),
52 STATS_DESC_COUNTER(VCPU, signal_exits),
53 STATS_DESC_COUNTER(VCPU, exits)
54};
55
56const struct kvm_stats_header kvm_vcpu_stats_header = {
57 .name_size = KVM_STATS_NAME_SIZE,
58 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
59 .id_offset = sizeof(struct kvm_stats_header),
60 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
61 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
62 sizeof(kvm_vcpu_stats_desc),
63};
64
65static bool core_reg_offset_is_vreg(u64 off)
66{
67 return off >= KVM_REG_ARM_CORE_REG(fp_regs.vregs) &&
68 off < KVM_REG_ARM_CORE_REG(fp_regs.fpsr);
69}
70
71static u64 core_reg_offset_from_id(u64 id)
72{
73 return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
74}
75
76static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
77{
78 int size;
79
80 switch (off) {
81 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
82 KVM_REG_ARM_CORE_REG(regs.regs[30]):
83 case KVM_REG_ARM_CORE_REG(regs.sp):
84 case KVM_REG_ARM_CORE_REG(regs.pc):
85 case KVM_REG_ARM_CORE_REG(regs.pstate):
86 case KVM_REG_ARM_CORE_REG(sp_el1):
87 case KVM_REG_ARM_CORE_REG(elr_el1):
88 case KVM_REG_ARM_CORE_REG(spsr[0]) ...
89 KVM_REG_ARM_CORE_REG(spsr[KVM_NR_SPSR - 1]):
90 size = sizeof(__u64);
91 break;
92
93 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
94 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
95 size = sizeof(__uint128_t);
96 break;
97
98 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
99 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
100 size = sizeof(__u32);
101 break;
102
103 default:
104 return -EINVAL;
105 }
106
107 if (!IS_ALIGNED(off, size / sizeof(__u32)))
108 return -EINVAL;
109
110 /*
111 * The KVM_REG_ARM64_SVE regs must be used instead of
112 * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on
113 * SVE-enabled vcpus:
114 */
115 if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
116 return -EINVAL;
117
118 return size;
119}
120
121static void *core_reg_addr(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
122{
123 u64 off = core_reg_offset_from_id(reg->id);
124 int size = core_reg_size_from_offset(vcpu, off);
125
126 if (size < 0)
127 return NULL;
128
129 if (KVM_REG_SIZE(reg->id) != size)
130 return NULL;
131
132 switch (off) {
133 case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
134 KVM_REG_ARM_CORE_REG(regs.regs[30]):
135 off -= KVM_REG_ARM_CORE_REG(regs.regs[0]);
136 off /= 2;
137 return &vcpu->arch.ctxt.regs.regs[off];
138
139 case KVM_REG_ARM_CORE_REG(regs.sp):
140 return &vcpu->arch.ctxt.regs.sp;
141
142 case KVM_REG_ARM_CORE_REG(regs.pc):
143 return &vcpu->arch.ctxt.regs.pc;
144
145 case KVM_REG_ARM_CORE_REG(regs.pstate):
146 return &vcpu->arch.ctxt.regs.pstate;
147
148 case KVM_REG_ARM_CORE_REG(sp_el1):
149 return __ctxt_sys_reg(&vcpu->arch.ctxt, SP_EL1);
150
151 case KVM_REG_ARM_CORE_REG(elr_el1):
152 return __ctxt_sys_reg(&vcpu->arch.ctxt, ELR_EL1);
153
154 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_EL1]):
155 return __ctxt_sys_reg(&vcpu->arch.ctxt, SPSR_EL1);
156
157 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_ABT]):
158 return &vcpu->arch.ctxt.spsr_abt;
159
160 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_UND]):
161 return &vcpu->arch.ctxt.spsr_und;
162
163 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_IRQ]):
164 return &vcpu->arch.ctxt.spsr_irq;
165
166 case KVM_REG_ARM_CORE_REG(spsr[KVM_SPSR_FIQ]):
167 return &vcpu->arch.ctxt.spsr_fiq;
168
169 case KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]) ...
170 KVM_REG_ARM_CORE_REG(fp_regs.vregs[31]):
171 off -= KVM_REG_ARM_CORE_REG(fp_regs.vregs[0]);
172 off /= 4;
173 return &vcpu->arch.ctxt.fp_regs.vregs[off];
174
175 case KVM_REG_ARM_CORE_REG(fp_regs.fpsr):
176 return &vcpu->arch.ctxt.fp_regs.fpsr;
177
178 case KVM_REG_ARM_CORE_REG(fp_regs.fpcr):
179 return &vcpu->arch.ctxt.fp_regs.fpcr;
180
181 default:
182 return NULL;
183 }
184}
185
186static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
187{
188 /*
189 * Because the kvm_regs structure is a mix of 32, 64 and
190 * 128bit fields, we index it as if it was a 32bit
191 * array. Hence below, nr_regs is the number of entries, and
192 * off the index in the "array".
193 */
194 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
195 int nr_regs = sizeof(struct kvm_regs) / sizeof(__u32);
196 void *addr;
197 u32 off;
198
199 /* Our ID is an index into the kvm_regs struct. */
200 off = core_reg_offset_from_id(reg->id);
201 if (off >= nr_regs ||
202 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
203 return -ENOENT;
204
205 addr = core_reg_addr(vcpu, reg);
206 if (!addr)
207 return -EINVAL;
208
209 if (copy_to_user(uaddr, addr, KVM_REG_SIZE(reg->id)))
210 return -EFAULT;
211
212 return 0;
213}
214
215static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
216{
217 __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
218 int nr_regs = sizeof(struct kvm_regs) / sizeof(__u32);
219 __uint128_t tmp;
220 void *valp = &tmp, *addr;
221 u64 off;
222 int err = 0;
223
224 /* Our ID is an index into the kvm_regs struct. */
225 off = core_reg_offset_from_id(reg->id);
226 if (off >= nr_regs ||
227 (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
228 return -ENOENT;
229
230 addr = core_reg_addr(vcpu, reg);
231 if (!addr)
232 return -EINVAL;
233
234 if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
235 return -EINVAL;
236
237 if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
238 err = -EFAULT;
239 goto out;
240 }
241
242 if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
243 u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK;
244 switch (mode) {
245 case PSR_AA32_MODE_USR:
246 if (!kvm_supports_32bit_el0())
247 return -EINVAL;
248 break;
249 case PSR_AA32_MODE_FIQ:
250 case PSR_AA32_MODE_IRQ:
251 case PSR_AA32_MODE_SVC:
252 case PSR_AA32_MODE_ABT:
253 case PSR_AA32_MODE_UND:
254 if (!vcpu_el1_is_32bit(vcpu))
255 return -EINVAL;
256 break;
257 case PSR_MODE_EL2h:
258 case PSR_MODE_EL2t:
259 if (!vcpu_has_nv(vcpu))
260 return -EINVAL;
261 fallthrough;
262 case PSR_MODE_EL0t:
263 case PSR_MODE_EL1t:
264 case PSR_MODE_EL1h:
265 if (vcpu_el1_is_32bit(vcpu))
266 return -EINVAL;
267 break;
268 default:
269 err = -EINVAL;
270 goto out;
271 }
272 }
273
274 memcpy(addr, valp, KVM_REG_SIZE(reg->id));
275
276 if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) {
277 int i, nr_reg;
278
279 switch (*vcpu_cpsr(vcpu)) {
280 /*
281 * Either we are dealing with user mode, and only the
282 * first 15 registers (+ PC) must be narrowed to 32bit.
283 * AArch32 r0-r14 conveniently map to AArch64 x0-x14.
284 */
285 case PSR_AA32_MODE_USR:
286 case PSR_AA32_MODE_SYS:
287 nr_reg = 15;
288 break;
289
290 /*
291 * Otherwise, this is a privileged mode, and *all* the
292 * registers must be narrowed to 32bit.
293 */
294 default:
295 nr_reg = 31;
296 break;
297 }
298
299 for (i = 0; i < nr_reg; i++)
300 vcpu_set_reg(vcpu, i, (u32)vcpu_get_reg(vcpu, i));
301
302 *vcpu_pc(vcpu) = (u32)*vcpu_pc(vcpu);
303 }
304out:
305 return err;
306}
307
308#define vq_word(vq) (((vq) - SVE_VQ_MIN) / 64)
309#define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64)
310#define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq)))
311
312static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
313{
314 unsigned int max_vq, vq;
315 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
316
317 if (!vcpu_has_sve(vcpu))
318 return -ENOENT;
319
320 if (WARN_ON(!sve_vl_valid(vcpu->arch.sve_max_vl)))
321 return -EINVAL;
322
323 memset(vqs, 0, sizeof(vqs));
324
325 max_vq = vcpu_sve_max_vq(vcpu);
326 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
327 if (sve_vq_available(vq))
328 vqs[vq_word(vq)] |= vq_mask(vq);
329
330 if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs)))
331 return -EFAULT;
332
333 return 0;
334}
335
336static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
337{
338 unsigned int max_vq, vq;
339 u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
340
341 if (!vcpu_has_sve(vcpu))
342 return -ENOENT;
343
344 if (kvm_arm_vcpu_sve_finalized(vcpu))
345 return -EPERM; /* too late! */
346
347 if (WARN_ON(vcpu->arch.sve_state))
348 return -EINVAL;
349
350 if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs)))
351 return -EFAULT;
352
353 max_vq = 0;
354 for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; ++vq)
355 if (vq_present(vqs, vq))
356 max_vq = vq;
357
358 if (max_vq > sve_vq_from_vl(kvm_sve_max_vl))
359 return -EINVAL;
360
361 /*
362 * Vector lengths supported by the host can't currently be
363 * hidden from the guest individually: instead we can only set a
364 * maximum via ZCR_EL2.LEN. So, make sure the available vector
365 * lengths match the set requested exactly up to the requested
366 * maximum:
367 */
368 for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
369 if (vq_present(vqs, vq) != sve_vq_available(vq))
370 return -EINVAL;
371
372 /* Can't run with no vector lengths at all: */
373 if (max_vq < SVE_VQ_MIN)
374 return -EINVAL;
375
376 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */
377 vcpu->arch.sve_max_vl = sve_vl_from_vq(max_vq);
378
379 return 0;
380}
381
382#define SVE_REG_SLICE_SHIFT 0
383#define SVE_REG_SLICE_BITS 5
384#define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS)
385#define SVE_REG_ID_BITS 5
386
387#define SVE_REG_SLICE_MASK \
388 GENMASK(SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS - 1, \
389 SVE_REG_SLICE_SHIFT)
390#define SVE_REG_ID_MASK \
391 GENMASK(SVE_REG_ID_SHIFT + SVE_REG_ID_BITS - 1, SVE_REG_ID_SHIFT)
392
393#define SVE_NUM_SLICES (1 << SVE_REG_SLICE_BITS)
394
395#define KVM_SVE_ZREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_ZREG(0, 0))
396#define KVM_SVE_PREG_SIZE KVM_REG_SIZE(KVM_REG_ARM64_SVE_PREG(0, 0))
397
398/*
399 * Number of register slices required to cover each whole SVE register.
400 * NOTE: Only the first slice every exists, for now.
401 * If you are tempted to modify this, you must also rework sve_reg_to_region()
402 * to match:
403 */
404#define vcpu_sve_slices(vcpu) 1
405
406/* Bounds of a single SVE register slice within vcpu->arch.sve_state */
407struct sve_state_reg_region {
408 unsigned int koffset; /* offset into sve_state in kernel memory */
409 unsigned int klen; /* length in kernel memory */
410 unsigned int upad; /* extra trailing padding in user memory */
411};
412
413/*
414 * Validate SVE register ID and get sanitised bounds for user/kernel SVE
415 * register copy
416 */
417static int sve_reg_to_region(struct sve_state_reg_region *region,
418 struct kvm_vcpu *vcpu,
419 const struct kvm_one_reg *reg)
420{
421 /* reg ID ranges for Z- registers */
422 const u64 zreg_id_min = KVM_REG_ARM64_SVE_ZREG(0, 0);
423 const u64 zreg_id_max = KVM_REG_ARM64_SVE_ZREG(SVE_NUM_ZREGS - 1,
424 SVE_NUM_SLICES - 1);
425
426 /* reg ID ranges for P- registers and FFR (which are contiguous) */
427 const u64 preg_id_min = KVM_REG_ARM64_SVE_PREG(0, 0);
428 const u64 preg_id_max = KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1);
429
430 unsigned int vq;
431 unsigned int reg_num;
432
433 unsigned int reqoffset, reqlen; /* User-requested offset and length */
434 unsigned int maxlen; /* Maximum permitted length */
435
436 size_t sve_state_size;
437
438 const u64 last_preg_id = KVM_REG_ARM64_SVE_PREG(SVE_NUM_PREGS - 1,
439 SVE_NUM_SLICES - 1);
440
441 /* Verify that the P-regs and FFR really do have contiguous IDs: */
442 BUILD_BUG_ON(KVM_REG_ARM64_SVE_FFR(0) != last_preg_id + 1);
443
444 /* Verify that we match the UAPI header: */
445 BUILD_BUG_ON(SVE_NUM_SLICES != KVM_ARM64_SVE_MAX_SLICES);
446
447 reg_num = (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT;
448
449 if (reg->id >= zreg_id_min && reg->id <= zreg_id_max) {
450 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
451 return -ENOENT;
452
453 vq = vcpu_sve_max_vq(vcpu);
454
455 reqoffset = SVE_SIG_ZREG_OFFSET(vq, reg_num) -
456 SVE_SIG_REGS_OFFSET;
457 reqlen = KVM_SVE_ZREG_SIZE;
458 maxlen = SVE_SIG_ZREG_SIZE(vq);
459 } else if (reg->id >= preg_id_min && reg->id <= preg_id_max) {
460 if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0)
461 return -ENOENT;
462
463 vq = vcpu_sve_max_vq(vcpu);
464
465 reqoffset = SVE_SIG_PREG_OFFSET(vq, reg_num) -
466 SVE_SIG_REGS_OFFSET;
467 reqlen = KVM_SVE_PREG_SIZE;
468 maxlen = SVE_SIG_PREG_SIZE(vq);
469 } else {
470 return -EINVAL;
471 }
472
473 sve_state_size = vcpu_sve_state_size(vcpu);
474 if (WARN_ON(!sve_state_size))
475 return -EINVAL;
476
477 region->koffset = array_index_nospec(reqoffset, sve_state_size);
478 region->klen = min(maxlen, reqlen);
479 region->upad = reqlen - region->klen;
480
481 return 0;
482}
483
484static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
485{
486 int ret;
487 struct sve_state_reg_region region;
488 char __user *uptr = (char __user *)reg->addr;
489
490 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
491 if (reg->id == KVM_REG_ARM64_SVE_VLS)
492 return get_sve_vls(vcpu, reg);
493
494 /* Try to interpret reg ID as an architectural SVE register... */
495 ret = sve_reg_to_region(®ion, vcpu, reg);
496 if (ret)
497 return ret;
498
499 if (!kvm_arm_vcpu_sve_finalized(vcpu))
500 return -EPERM;
501
502 if (copy_to_user(uptr, vcpu->arch.sve_state + region.koffset,
503 region.klen) ||
504 clear_user(uptr + region.klen, region.upad))
505 return -EFAULT;
506
507 return 0;
508}
509
510static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
511{
512 int ret;
513 struct sve_state_reg_region region;
514 const char __user *uptr = (const char __user *)reg->addr;
515
516 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */
517 if (reg->id == KVM_REG_ARM64_SVE_VLS)
518 return set_sve_vls(vcpu, reg);
519
520 /* Try to interpret reg ID as an architectural SVE register... */
521 ret = sve_reg_to_region(®ion, vcpu, reg);
522 if (ret)
523 return ret;
524
525 if (!kvm_arm_vcpu_sve_finalized(vcpu))
526 return -EPERM;
527
528 if (copy_from_user(vcpu->arch.sve_state + region.koffset, uptr,
529 region.klen))
530 return -EFAULT;
531
532 return 0;
533}
534
535int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
536{
537 return -EINVAL;
538}
539
540int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
541{
542 return -EINVAL;
543}
544
545static int copy_core_reg_indices(const struct kvm_vcpu *vcpu,
546 u64 __user *uindices)
547{
548 unsigned int i;
549 int n = 0;
550
551 for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
552 u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i;
553 int size = core_reg_size_from_offset(vcpu, i);
554
555 if (size < 0)
556 continue;
557
558 switch (size) {
559 case sizeof(__u32):
560 reg |= KVM_REG_SIZE_U32;
561 break;
562
563 case sizeof(__u64):
564 reg |= KVM_REG_SIZE_U64;
565 break;
566
567 case sizeof(__uint128_t):
568 reg |= KVM_REG_SIZE_U128;
569 break;
570
571 default:
572 WARN_ON(1);
573 continue;
574 }
575
576 if (uindices) {
577 if (put_user(reg, uindices))
578 return -EFAULT;
579 uindices++;
580 }
581
582 n++;
583 }
584
585 return n;
586}
587
588static unsigned long num_core_regs(const struct kvm_vcpu *vcpu)
589{
590 return copy_core_reg_indices(vcpu, NULL);
591}
592
593static const u64 timer_reg_list[] = {
594 KVM_REG_ARM_TIMER_CTL,
595 KVM_REG_ARM_TIMER_CNT,
596 KVM_REG_ARM_TIMER_CVAL,
597 KVM_REG_ARM_PTIMER_CTL,
598 KVM_REG_ARM_PTIMER_CNT,
599 KVM_REG_ARM_PTIMER_CVAL,
600};
601
602#define NUM_TIMER_REGS ARRAY_SIZE(timer_reg_list)
603
604static bool is_timer_reg(u64 index)
605{
606 switch (index) {
607 case KVM_REG_ARM_TIMER_CTL:
608 case KVM_REG_ARM_TIMER_CNT:
609 case KVM_REG_ARM_TIMER_CVAL:
610 case KVM_REG_ARM_PTIMER_CTL:
611 case KVM_REG_ARM_PTIMER_CNT:
612 case KVM_REG_ARM_PTIMER_CVAL:
613 return true;
614 }
615 return false;
616}
617
618static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
619{
620 for (int i = 0; i < NUM_TIMER_REGS; i++) {
621 if (put_user(timer_reg_list[i], uindices))
622 return -EFAULT;
623 uindices++;
624 }
625
626 return 0;
627}
628
629static int set_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
630{
631 void __user *uaddr = (void __user *)(long)reg->addr;
632 u64 val;
633 int ret;
634
635 ret = copy_from_user(&val, uaddr, KVM_REG_SIZE(reg->id));
636 if (ret != 0)
637 return -EFAULT;
638
639 return kvm_arm_timer_set_reg(vcpu, reg->id, val);
640}
641
642static int get_timer_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
643{
644 void __user *uaddr = (void __user *)(long)reg->addr;
645 u64 val;
646
647 val = kvm_arm_timer_get_reg(vcpu, reg->id);
648 return copy_to_user(uaddr, &val, KVM_REG_SIZE(reg->id)) ? -EFAULT : 0;
649}
650
651static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu)
652{
653 const unsigned int slices = vcpu_sve_slices(vcpu);
654
655 if (!vcpu_has_sve(vcpu))
656 return 0;
657
658 /* Policed by KVM_GET_REG_LIST: */
659 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
660
661 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */)
662 + 1; /* KVM_REG_ARM64_SVE_VLS */
663}
664
665static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu,
666 u64 __user *uindices)
667{
668 const unsigned int slices = vcpu_sve_slices(vcpu);
669 u64 reg;
670 unsigned int i, n;
671 int num_regs = 0;
672
673 if (!vcpu_has_sve(vcpu))
674 return 0;
675
676 /* Policed by KVM_GET_REG_LIST: */
677 WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu));
678
679 /*
680 * Enumerate this first, so that userspace can save/restore in
681 * the order reported by KVM_GET_REG_LIST:
682 */
683 reg = KVM_REG_ARM64_SVE_VLS;
684 if (put_user(reg, uindices++))
685 return -EFAULT;
686 ++num_regs;
687
688 for (i = 0; i < slices; i++) {
689 for (n = 0; n < SVE_NUM_ZREGS; n++) {
690 reg = KVM_REG_ARM64_SVE_ZREG(n, i);
691 if (put_user(reg, uindices++))
692 return -EFAULT;
693 num_regs++;
694 }
695
696 for (n = 0; n < SVE_NUM_PREGS; n++) {
697 reg = KVM_REG_ARM64_SVE_PREG(n, i);
698 if (put_user(reg, uindices++))
699 return -EFAULT;
700 num_regs++;
701 }
702
703 reg = KVM_REG_ARM64_SVE_FFR(i);
704 if (put_user(reg, uindices++))
705 return -EFAULT;
706 num_regs++;
707 }
708
709 return num_regs;
710}
711
712/**
713 * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
714 *
715 * This is for all registers.
716 */
717unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
718{
719 unsigned long res = 0;
720
721 res += num_core_regs(vcpu);
722 res += num_sve_regs(vcpu);
723 res += kvm_arm_num_sys_reg_descs(vcpu);
724 res += kvm_arm_get_fw_num_regs(vcpu);
725 res += NUM_TIMER_REGS;
726
727 return res;
728}
729
730/**
731 * kvm_arm_copy_reg_indices - get indices of all registers.
732 *
733 * We do core registers right here, then we append system regs.
734 */
735int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
736{
737 int ret;
738
739 ret = copy_core_reg_indices(vcpu, uindices);
740 if (ret < 0)
741 return ret;
742 uindices += ret;
743
744 ret = copy_sve_reg_indices(vcpu, uindices);
745 if (ret < 0)
746 return ret;
747 uindices += ret;
748
749 ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices);
750 if (ret < 0)
751 return ret;
752 uindices += kvm_arm_get_fw_num_regs(vcpu);
753
754 ret = copy_timer_indices(vcpu, uindices);
755 if (ret < 0)
756 return ret;
757 uindices += NUM_TIMER_REGS;
758
759 return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
760}
761
762int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
763{
764 /* We currently use nothing arch-specific in upper 32 bits */
765 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
766 return -EINVAL;
767
768 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
769 case KVM_REG_ARM_CORE: return get_core_reg(vcpu, reg);
770 case KVM_REG_ARM_FW:
771 case KVM_REG_ARM_FW_FEAT_BMAP:
772 return kvm_arm_get_fw_reg(vcpu, reg);
773 case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg);
774 }
775
776 if (is_timer_reg(reg->id))
777 return get_timer_reg(vcpu, reg);
778
779 return kvm_arm_sys_reg_get_reg(vcpu, reg);
780}
781
782int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
783{
784 /* We currently use nothing arch-specific in upper 32 bits */
785 if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
786 return -EINVAL;
787
788 switch (reg->id & KVM_REG_ARM_COPROC_MASK) {
789 case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg);
790 case KVM_REG_ARM_FW:
791 case KVM_REG_ARM_FW_FEAT_BMAP:
792 return kvm_arm_set_fw_reg(vcpu, reg);
793 case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
794 }
795
796 if (is_timer_reg(reg->id))
797 return set_timer_reg(vcpu, reg);
798
799 return kvm_arm_sys_reg_set_reg(vcpu, reg);
800}
801
802int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
803 struct kvm_sregs *sregs)
804{
805 return -EINVAL;
806}
807
808int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
809 struct kvm_sregs *sregs)
810{
811 return -EINVAL;
812}
813
814int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
815 struct kvm_vcpu_events *events)
816{
817 events->exception.serror_pending = !!(vcpu->arch.hcr_el2 & HCR_VSE);
818 events->exception.serror_has_esr = cpus_have_final_cap(ARM64_HAS_RAS_EXTN);
819
820 if (events->exception.serror_pending && events->exception.serror_has_esr)
821 events->exception.serror_esr = vcpu_get_vsesr(vcpu);
822
823 /*
824 * We never return a pending ext_dabt here because we deliver it to
825 * the virtual CPU directly when setting the event and it's no longer
826 * 'pending' at this point.
827 */
828
829 return 0;
830}
831
832int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
833 struct kvm_vcpu_events *events)
834{
835 bool serror_pending = events->exception.serror_pending;
836 bool has_esr = events->exception.serror_has_esr;
837 bool ext_dabt_pending = events->exception.ext_dabt_pending;
838
839 if (serror_pending && has_esr) {
840 if (!cpus_have_final_cap(ARM64_HAS_RAS_EXTN))
841 return -EINVAL;
842
843 if (!((events->exception.serror_esr) & ~ESR_ELx_ISS_MASK))
844 kvm_set_sei_esr(vcpu, events->exception.serror_esr);
845 else
846 return -EINVAL;
847 } else if (serror_pending) {
848 kvm_inject_vabt(vcpu);
849 }
850
851 if (ext_dabt_pending)
852 kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
853
854 return 0;
855}
856
857u32 __attribute_const__ kvm_target_cpu(void)
858{
859 unsigned long implementor = read_cpuid_implementor();
860 unsigned long part_number = read_cpuid_part_number();
861
862 switch (implementor) {
863 case ARM_CPU_IMP_ARM:
864 switch (part_number) {
865 case ARM_CPU_PART_AEM_V8:
866 return KVM_ARM_TARGET_AEM_V8;
867 case ARM_CPU_PART_FOUNDATION:
868 return KVM_ARM_TARGET_FOUNDATION_V8;
869 case ARM_CPU_PART_CORTEX_A53:
870 return KVM_ARM_TARGET_CORTEX_A53;
871 case ARM_CPU_PART_CORTEX_A57:
872 return KVM_ARM_TARGET_CORTEX_A57;
873 }
874 break;
875 case ARM_CPU_IMP_APM:
876 switch (part_number) {
877 case APM_CPU_PART_XGENE:
878 return KVM_ARM_TARGET_XGENE_POTENZA;
879 }
880 break;
881 }
882
883 /* Return a default generic target */
884 return KVM_ARM_TARGET_GENERIC_V8;
885}
886
887int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
888{
889 return -EINVAL;
890}
891
892int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
893{
894 return -EINVAL;
895}
896
897int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
898 struct kvm_translation *tr)
899{
900 return -EINVAL;
901}
902
903/**
904 * kvm_arch_vcpu_ioctl_set_guest_debug - set up guest debugging
905 * @kvm: pointer to the KVM struct
906 * @kvm_guest_debug: the ioctl data buffer
907 *
908 * This sets up and enables the VM for guest debugging. Userspace
909 * passes in a control flag to enable different debug types and
910 * potentially other architecture specific information in the rest of
911 * the structure.
912 */
913int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
914 struct kvm_guest_debug *dbg)
915{
916 int ret = 0;
917
918 trace_kvm_set_guest_debug(vcpu, dbg->control);
919
920 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) {
921 ret = -EINVAL;
922 goto out;
923 }
924
925 if (dbg->control & KVM_GUESTDBG_ENABLE) {
926 vcpu->guest_debug = dbg->control;
927
928 /* Hardware assisted Break and Watch points */
929 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {
930 vcpu->arch.external_debug_state = dbg->arch;
931 }
932
933 } else {
934 /* If not enabled clear all flags */
935 vcpu->guest_debug = 0;
936 vcpu_clear_flag(vcpu, DBG_SS_ACTIVE_PENDING);
937 }
938
939out:
940 return ret;
941}
942
943int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
944 struct kvm_device_attr *attr)
945{
946 int ret;
947
948 switch (attr->group) {
949 case KVM_ARM_VCPU_PMU_V3_CTRL:
950 mutex_lock(&vcpu->kvm->arch.config_lock);
951 ret = kvm_arm_pmu_v3_set_attr(vcpu, attr);
952 mutex_unlock(&vcpu->kvm->arch.config_lock);
953 break;
954 case KVM_ARM_VCPU_TIMER_CTRL:
955 ret = kvm_arm_timer_set_attr(vcpu, attr);
956 break;
957 case KVM_ARM_VCPU_PVTIME_CTRL:
958 ret = kvm_arm_pvtime_set_attr(vcpu, attr);
959 break;
960 default:
961 ret = -ENXIO;
962 break;
963 }
964
965 return ret;
966}
967
968int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
969 struct kvm_device_attr *attr)
970{
971 int ret;
972
973 switch (attr->group) {
974 case KVM_ARM_VCPU_PMU_V3_CTRL:
975 ret = kvm_arm_pmu_v3_get_attr(vcpu, attr);
976 break;
977 case KVM_ARM_VCPU_TIMER_CTRL:
978 ret = kvm_arm_timer_get_attr(vcpu, attr);
979 break;
980 case KVM_ARM_VCPU_PVTIME_CTRL:
981 ret = kvm_arm_pvtime_get_attr(vcpu, attr);
982 break;
983 default:
984 ret = -ENXIO;
985 break;
986 }
987
988 return ret;
989}
990
991int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
992 struct kvm_device_attr *attr)
993{
994 int ret;
995
996 switch (attr->group) {
997 case KVM_ARM_VCPU_PMU_V3_CTRL:
998 ret = kvm_arm_pmu_v3_has_attr(vcpu, attr);
999 break;
1000 case KVM_ARM_VCPU_TIMER_CTRL:
1001 ret = kvm_arm_timer_has_attr(vcpu, attr);
1002 break;
1003 case KVM_ARM_VCPU_PVTIME_CTRL:
1004 ret = kvm_arm_pvtime_has_attr(vcpu, attr);
1005 break;
1006 default:
1007 ret = -ENXIO;
1008 break;
1009 }
1010
1011 return ret;
1012}
1013
1014int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1015 struct kvm_arm_copy_mte_tags *copy_tags)
1016{
1017 gpa_t guest_ipa = copy_tags->guest_ipa;
1018 size_t length = copy_tags->length;
1019 void __user *tags = copy_tags->addr;
1020 gpa_t gfn;
1021 bool write = !(copy_tags->flags & KVM_ARM_TAGS_FROM_GUEST);
1022 int ret = 0;
1023
1024 if (!kvm_has_mte(kvm))
1025 return -EINVAL;
1026
1027 if (copy_tags->reserved[0] || copy_tags->reserved[1])
1028 return -EINVAL;
1029
1030 if (copy_tags->flags & ~KVM_ARM_TAGS_FROM_GUEST)
1031 return -EINVAL;
1032
1033 if (length & ~PAGE_MASK || guest_ipa & ~PAGE_MASK)
1034 return -EINVAL;
1035
1036 /* Lengths above INT_MAX cannot be represented in the return value */
1037 if (length > INT_MAX)
1038 return -EINVAL;
1039
1040 gfn = gpa_to_gfn(guest_ipa);
1041
1042 mutex_lock(&kvm->slots_lock);
1043
1044 while (length > 0) {
1045 kvm_pfn_t pfn = gfn_to_pfn_prot(kvm, gfn, write, NULL);
1046 void *maddr;
1047 unsigned long num_tags;
1048 struct page *page;
1049
1050 if (is_error_noslot_pfn(pfn)) {
1051 ret = -EFAULT;
1052 goto out;
1053 }
1054
1055 page = pfn_to_online_page(pfn);
1056 if (!page) {
1057 /* Reject ZONE_DEVICE memory */
1058 ret = -EFAULT;
1059 goto out;
1060 }
1061 maddr = page_address(page);
1062
1063 if (!write) {
1064 if (page_mte_tagged(page))
1065 num_tags = mte_copy_tags_to_user(tags, maddr,
1066 MTE_GRANULES_PER_PAGE);
1067 else
1068 /* No tags in memory, so write zeros */
1069 num_tags = MTE_GRANULES_PER_PAGE -
1070 clear_user(tags, MTE_GRANULES_PER_PAGE);
1071 kvm_release_pfn_clean(pfn);
1072 } else {
1073 /*
1074 * Only locking to serialise with a concurrent
1075 * set_pte_at() in the VMM but still overriding the
1076 * tags, hence ignoring the return value.
1077 */
1078 try_page_mte_tagging(page);
1079 num_tags = mte_copy_tags_from_user(maddr, tags,
1080 MTE_GRANULES_PER_PAGE);
1081
1082 /* uaccess failed, don't leave stale tags */
1083 if (num_tags != MTE_GRANULES_PER_PAGE)
1084 mte_clear_page_tags(maddr);
1085 set_page_mte_tagged(page);
1086
1087 kvm_release_pfn_dirty(pfn);
1088 }
1089
1090 if (num_tags != MTE_GRANULES_PER_PAGE) {
1091 ret = -EFAULT;
1092 goto out;
1093 }
1094
1095 gfn++;
1096 tags += num_tags;
1097 length -= PAGE_SIZE;
1098 }
1099
1100out:
1101 mutex_unlock(&kvm->slots_lock);
1102 /* If some data has been copied report the number of bytes copied */
1103 if (length != copy_tags->length)
1104 return copy_tags->length - length;
1105 return ret;
1106}