1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * This file is part of STM32 ADC driver
   4 *
   5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
   6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
   7 */
   8
   9#include <linux/clk.h>
 
  10#include <linux/delay.h>
  11#include <linux/dma-mapping.h>
  12#include <linux/dmaengine.h>
  13#include <linux/iio/iio.h>
  14#include <linux/iio/buffer.h>
  15#include <linux/iio/timer/stm32-lptim-trigger.h>
  16#include <linux/iio/timer/stm32-timer-trigger.h>
  17#include <linux/iio/trigger.h>
  18#include <linux/iio/trigger_consumer.h>
  19#include <linux/iio/triggered_buffer.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/iopoll.h>
  23#include <linux/module.h>
 
 
  24#include <linux/platform_device.h>
  25#include <linux/pm_runtime.h>
  26#include <linux/of.h>
  27#include <linux/of_device.h>
  28
  29#include "stm32-adc-core.h"
  30
  31/* Number of linear calibration shadow registers / LINCALRDYW control bits */
  32#define STM32H7_LINCALFACT_NUM		6
  33
  34/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
  35#define STM32H7_BOOST_CLKRATE		20000000UL
  36
  37#define STM32_ADC_CH_MAX		20	/* max number of channels */
  38#define STM32_ADC_CH_SZ			10	/* max channel name size */
  39#define STM32_ADC_MAX_SQ		16	/* SQ1..SQ16 */
  40#define STM32_ADC_MAX_SMP		7	/* SMPx range is [0..7] */
  41#define STM32_ADC_TIMEOUT_US		100000
  42#define STM32_ADC_TIMEOUT	(msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
  43#define STM32_ADC_HW_STOP_DELAY_MS	100
 
  44
  45#define STM32_DMA_BUFFER_SIZE		PAGE_SIZE
  46
  47/* External trigger enable */
  48enum stm32_adc_exten {
  49	STM32_EXTEN_SWTRIG,
  50	STM32_EXTEN_HWTRIG_RISING_EDGE,
  51	STM32_EXTEN_HWTRIG_FALLING_EDGE,
  52	STM32_EXTEN_HWTRIG_BOTH_EDGES,
  53};
  54
  55/* extsel - trigger mux selection value */
  56enum stm32_adc_extsel {
  57	STM32_EXT0,
  58	STM32_EXT1,
  59	STM32_EXT2,
  60	STM32_EXT3,
  61	STM32_EXT4,
  62	STM32_EXT5,
  63	STM32_EXT6,
  64	STM32_EXT7,
  65	STM32_EXT8,
  66	STM32_EXT9,
  67	STM32_EXT10,
  68	STM32_EXT11,
  69	STM32_EXT12,
  70	STM32_EXT13,
  71	STM32_EXT14,
  72	STM32_EXT15,
  73	STM32_EXT16,
  74	STM32_EXT17,
  75	STM32_EXT18,
  76	STM32_EXT19,
  77	STM32_EXT20,
  78};
  79
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  80/**
  81 * struct stm32_adc_trig_info - ADC trigger info
  82 * @name:		name of the trigger, corresponding to its source
  83 * @extsel:		trigger selection
  84 */
  85struct stm32_adc_trig_info {
  86	const char *name;
  87	enum stm32_adc_extsel extsel;
  88};
  89
  90/**
  91 * struct stm32_adc_calib - optional adc calibration data
  92 * @calfact_s: Calibration offset for single ended channels
  93 * @calfact_d: Calibration offset in differential
  94 * @lincalfact: Linearity calibration factor
  95 * @calibrated: Indicates calibration status
  96 */
  97struct stm32_adc_calib {
  98	u32			calfact_s;
  99	u32			calfact_d;
 100	u32			lincalfact[STM32H7_LINCALFACT_NUM];
 101	bool			calibrated;
 102};
 103
 104/**
 105 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
 106 * @reg:		register offset
 107 * @mask:		bitfield mask
 108 * @shift:		left shift
 109 */
 110struct stm32_adc_regs {
 111	int reg;
 112	int mask;
 113	int shift;
 114};
 115
 116/**
 117 * stm32_adc_regspec - stm32 registers definition, compatible dependent data
 
 
 
 
 
 
 
 
 
 
 118 * @dr:			data register offset
 119 * @ier_eoc:		interrupt enable register & eocie bitfield
 
 120 * @isr_eoc:		interrupt status register & eoc bitfield
 
 121 * @sqr:		reference to sequence registers array
 122 * @exten:		trigger control register & bitfield
 123 * @extsel:		trigger selection register & bitfield
 124 * @res:		resolution selection register & bitfield
 
 125 * @smpr:		smpr1 & smpr2 registers offset array
 126 * @smp_bits:		smpr1 & smpr2 index and bitfields
 
 
 
 
 
 127 */
 128struct stm32_adc_regspec {
 129	const u32 dr;
 130	const struct stm32_adc_regs ier_eoc;
 
 131	const struct stm32_adc_regs isr_eoc;
 
 132	const struct stm32_adc_regs *sqr;
 133	const struct stm32_adc_regs exten;
 134	const struct stm32_adc_regs extsel;
 135	const struct stm32_adc_regs res;
 
 136	const u32 smpr[2];
 137	const struct stm32_adc_regs *smp_bits;
 
 
 
 
 
 138};
 139
 140struct stm32_adc;
 141
 142/**
 143 * stm32_adc_cfg - stm32 compatible configuration data
 144 * @regs:		registers descriptions
 145 * @adc_info:		per instance input channels definitions
 146 * @trigs:		external trigger sources
 147 * @clk_required:	clock is required
 148 * @has_vregready:	vregready status flag presence
 
 
 
 149 * @prepare:		optional prepare routine (power-up, enable)
 150 * @start_conv:		routine to start conversions
 151 * @stop_conv:		routine to stop conversions
 152 * @unprepare:		optional unprepare routine (disable, power-down)
 
 153 * @smp_cycles:		programmable sampling time (ADC clock cycles)
 
 154 */
 155struct stm32_adc_cfg {
 156	const struct stm32_adc_regspec	*regs;
 157	const struct stm32_adc_info	*adc_info;
 158	struct stm32_adc_trig_info	*trigs;
 159	bool clk_required;
 160	bool has_vregready;
 161	int (*prepare)(struct stm32_adc *);
 162	void (*start_conv)(struct stm32_adc *, bool dma);
 163	void (*stop_conv)(struct stm32_adc *);
 164	void (*unprepare)(struct stm32_adc *);
 
 
 
 
 165	const unsigned int *smp_cycles;
 
 166};
 167
 168/**
 169 * struct stm32_adc - private data of each ADC IIO instance
 170 * @common:		reference to ADC block common data
 171 * @offset:		ADC instance register offset in ADC block
 172 * @cfg:		compatible configuration data
 173 * @completion:		end of single conversion completion
 174 * @buffer:		data buffer
 175 * @clk:		clock for this adc instance
 176 * @irq:		interrupt for this adc instance
 177 * @lock:		spinlock
 178 * @bufi:		data buffer index
 179 * @num_conv:		expected number of scan conversions
 180 * @res:		data resolution (e.g. RES bitfield value)
 181 * @trigger_polarity:	external trigger polarity (e.g. exten)
 182 * @dma_chan:		dma channel
 183 * @rx_buf:		dma rx buffer cpu address
 184 * @rx_dma_buf:		dma rx buffer bus address
 185 * @rx_buf_sz:		dma rx buffer size
 186 * @difsel		bitmask to set single-ended/differential channel
 187 * @pcsel		bitmask to preselect channels on some devices
 188 * @smpr_val:		sampling time settings (e.g. smpr1 / smpr2)
 189 * @cal:		optional calibration data on some devices
 
 190 * @chan_name:		channel name array
 
 
 
 191 */
 192struct stm32_adc {
 193	struct stm32_adc_common	*common;
 194	u32			offset;
 195	const struct stm32_adc_cfg	*cfg;
 196	struct completion	completion;
 197	u16			buffer[STM32_ADC_MAX_SQ];
 198	struct clk		*clk;
 199	int			irq;
 200	spinlock_t		lock;		/* interrupt lock */
 201	unsigned int		bufi;
 202	unsigned int		num_conv;
 203	u32			res;
 204	u32			trigger_polarity;
 205	struct dma_chan		*dma_chan;
 206	u8			*rx_buf;
 207	dma_addr_t		rx_dma_buf;
 208	unsigned int		rx_buf_sz;
 209	u32			difsel;
 210	u32			pcsel;
 211	u32			smpr_val[2];
 212	struct stm32_adc_calib	cal;
 
 213	char			chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
 
 
 
 214};
 215
 216struct stm32_adc_diff_channel {
 217	u32 vinp;
 218	u32 vinn;
 219};
 220
 221/**
 222 * struct stm32_adc_info - stm32 ADC, per instance config data
 223 * @max_channels:	Number of channels
 224 * @resolutions:	available resolutions
 225 * @num_res:		number of available resolutions
 226 */
 227struct stm32_adc_info {
 228	int max_channels;
 229	const unsigned int *resolutions;
 230	const unsigned int num_res;
 231};
 232
 233static const unsigned int stm32f4_adc_resolutions[] = {
 234	/* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
 235	12, 10, 8, 6,
 236};
 237
 238/* stm32f4 can have up to 16 channels */
 239static const struct stm32_adc_info stm32f4_adc_info = {
 240	.max_channels = 16,
 241	.resolutions = stm32f4_adc_resolutions,
 242	.num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
 243};
 244
 245static const unsigned int stm32h7_adc_resolutions[] = {
 246	/* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
 247	16, 14, 12, 10, 8,
 248};
 249
 250/* stm32h7 can have up to 20 channels */
 251static const struct stm32_adc_info stm32h7_adc_info = {
 252	.max_channels = STM32_ADC_CH_MAX,
 253	.resolutions = stm32h7_adc_resolutions,
 254	.num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
 255};
 256
 257/**
 
 
 
 
 
 
 
 258 * stm32f4_sq - describe regular sequence registers
 259 * - L: sequence len (register & bit field)
 260 * - SQ1..SQ16: sequence entries (register & bit field)
 261 */
 262static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
 263	/* L: len bit field description to be kept as first element */
 264	{ STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
 265	/* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
 266	{ STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
 267	{ STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
 268	{ STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
 269	{ STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
 270	{ STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
 271	{ STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
 272	{ STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
 273	{ STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
 274	{ STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
 275	{ STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
 276	{ STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
 277	{ STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
 278	{ STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
 279	{ STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
 280	{ STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
 281	{ STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
 282};
 283
 284/* STM32F4 external trigger sources for all instances */
 285static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
 286	{ TIM1_CH1, STM32_EXT0 },
 287	{ TIM1_CH2, STM32_EXT1 },
 288	{ TIM1_CH3, STM32_EXT2 },
 289	{ TIM2_CH2, STM32_EXT3 },
 290	{ TIM2_CH3, STM32_EXT4 },
 291	{ TIM2_CH4, STM32_EXT5 },
 292	{ TIM2_TRGO, STM32_EXT6 },
 293	{ TIM3_CH1, STM32_EXT7 },
 294	{ TIM3_TRGO, STM32_EXT8 },
 295	{ TIM4_CH4, STM32_EXT9 },
 296	{ TIM5_CH1, STM32_EXT10 },
 297	{ TIM5_CH2, STM32_EXT11 },
 298	{ TIM5_CH3, STM32_EXT12 },
 299	{ TIM8_CH1, STM32_EXT13 },
 300	{ TIM8_TRGO, STM32_EXT14 },
 301	{}, /* sentinel */
 302};
 303
 304/**
 305 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
 306 * Sorted so it can be indexed by channel number.
 307 */
 308static const struct stm32_adc_regs stm32f4_smp_bits[] = {
 309	/* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
 310	{ 1, GENMASK(2, 0), 0 },
 311	{ 1, GENMASK(5, 3), 3 },
 312	{ 1, GENMASK(8, 6), 6 },
 313	{ 1, GENMASK(11, 9), 9 },
 314	{ 1, GENMASK(14, 12), 12 },
 315	{ 1, GENMASK(17, 15), 15 },
 316	{ 1, GENMASK(20, 18), 18 },
 317	{ 1, GENMASK(23, 21), 21 },
 318	{ 1, GENMASK(26, 24), 24 },
 319	{ 1, GENMASK(29, 27), 27 },
 320	/* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
 321	{ 0, GENMASK(2, 0), 0 },
 322	{ 0, GENMASK(5, 3), 3 },
 323	{ 0, GENMASK(8, 6), 6 },
 324	{ 0, GENMASK(11, 9), 9 },
 325	{ 0, GENMASK(14, 12), 12 },
 326	{ 0, GENMASK(17, 15), 15 },
 327	{ 0, GENMASK(20, 18), 18 },
 328	{ 0, GENMASK(23, 21), 21 },
 329	{ 0, GENMASK(26, 24), 24 },
 330};
 331
 332/* STM32F4 programmable sampling time (ADC clock cycles) */
 333static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
 334	3, 15, 28, 56, 84, 112, 144, 480,
 335};
 336
 337static const struct stm32_adc_regspec stm32f4_adc_regspec = {
 338	.dr = STM32F4_ADC_DR,
 339	.ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
 
 340	.isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
 
 341	.sqr = stm32f4_sq,
 342	.exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
 343	.extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
 344		    STM32F4_EXTSEL_SHIFT },
 345	.res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
 346	.smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
 347	.smp_bits = stm32f4_smp_bits,
 348};
 349
 350static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
 351	/* L: len bit field description to be kept as first element */
 352	{ STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
 353	/* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
 354	{ STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
 355	{ STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
 356	{ STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
 357	{ STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
 358	{ STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
 359	{ STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
 360	{ STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
 361	{ STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
 362	{ STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
 363	{ STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
 364	{ STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
 365	{ STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
 366	{ STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
 367	{ STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
 368	{ STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
 369	{ STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
 370};
 371
 372/* STM32H7 external trigger sources for all instances */
 373static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
 374	{ TIM1_CH1, STM32_EXT0 },
 375	{ TIM1_CH2, STM32_EXT1 },
 376	{ TIM1_CH3, STM32_EXT2 },
 377	{ TIM2_CH2, STM32_EXT3 },
 378	{ TIM3_TRGO, STM32_EXT4 },
 379	{ TIM4_CH4, STM32_EXT5 },
 380	{ TIM8_TRGO, STM32_EXT7 },
 381	{ TIM8_TRGO2, STM32_EXT8 },
 382	{ TIM1_TRGO, STM32_EXT9 },
 383	{ TIM1_TRGO2, STM32_EXT10 },
 384	{ TIM2_TRGO, STM32_EXT11 },
 385	{ TIM4_TRGO, STM32_EXT12 },
 386	{ TIM6_TRGO, STM32_EXT13 },
 387	{ TIM15_TRGO, STM32_EXT14 },
 388	{ TIM3_CH4, STM32_EXT15 },
 389	{ LPTIM1_OUT, STM32_EXT18 },
 390	{ LPTIM2_OUT, STM32_EXT19 },
 391	{ LPTIM3_OUT, STM32_EXT20 },
 392	{},
 393};
 394
 395/**
 396 * stm32h7_smp_bits - describe sampling time register index & bit fields
 397 * Sorted so it can be indexed by channel number.
 398 */
 399static const struct stm32_adc_regs stm32h7_smp_bits[] = {
 400	/* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
 401	{ 0, GENMASK(2, 0), 0 },
 402	{ 0, GENMASK(5, 3), 3 },
 403	{ 0, GENMASK(8, 6), 6 },
 404	{ 0, GENMASK(11, 9), 9 },
 405	{ 0, GENMASK(14, 12), 12 },
 406	{ 0, GENMASK(17, 15), 15 },
 407	{ 0, GENMASK(20, 18), 18 },
 408	{ 0, GENMASK(23, 21), 21 },
 409	{ 0, GENMASK(26, 24), 24 },
 410	{ 0, GENMASK(29, 27), 27 },
 411	/* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
 412	{ 1, GENMASK(2, 0), 0 },
 413	{ 1, GENMASK(5, 3), 3 },
 414	{ 1, GENMASK(8, 6), 6 },
 415	{ 1, GENMASK(11, 9), 9 },
 416	{ 1, GENMASK(14, 12), 12 },
 417	{ 1, GENMASK(17, 15), 15 },
 418	{ 1, GENMASK(20, 18), 18 },
 419	{ 1, GENMASK(23, 21), 21 },
 420	{ 1, GENMASK(26, 24), 24 },
 421	{ 1, GENMASK(29, 27), 27 },
 422};
 423
 424/* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
 425static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
 426	1, 2, 8, 16, 32, 64, 387, 810,
 427};
 428
 429static const struct stm32_adc_regspec stm32h7_adc_regspec = {
 430	.dr = STM32H7_ADC_DR,
 431	.ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
 
 432	.isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
 
 433	.sqr = stm32h7_sq,
 434	.exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
 435	.extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
 436		    STM32H7_EXTSEL_SHIFT },
 437	.res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
 
 438	.smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
 439	.smp_bits = stm32h7_smp_bits,
 440};
 441
 442/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 443 * STM32 ADC registers access routines
 444 * @adc: stm32 adc instance
 445 * @reg: reg offset in adc instance
 446 *
 447 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
 448 * for adc1, adc2 and adc3.
 449 */
 450static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
 451{
 452	return readl_relaxed(adc->common->base + adc->offset + reg);
 453}
 454
 455#define stm32_adc_readl_addr(addr)	stm32_adc_readl(adc, addr)
 456
 457#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
 458	readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
 459			   cond, sleep_us, timeout_us)
 460
 461static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
 462{
 463	return readw_relaxed(adc->common->base + adc->offset + reg);
 464}
 465
 466static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
 467{
 468	writel_relaxed(val, adc->common->base + adc->offset + reg);
 469}
 470
 471static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
 472{
 473	unsigned long flags;
 474
 475	spin_lock_irqsave(&adc->lock, flags);
 476	stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
 477	spin_unlock_irqrestore(&adc->lock, flags);
 478}
 479
 
 
 
 
 
 
 
 
 480static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
 481{
 482	unsigned long flags;
 483
 484	spin_lock_irqsave(&adc->lock, flags);
 485	stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
 486	spin_unlock_irqrestore(&adc->lock, flags);
 487}
 488
 
 
 
 
 
 
 
 
 489/**
 490 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
 491 * @adc: stm32 adc instance
 492 */
 493static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
 494{
 495	stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
 496			   adc->cfg->regs->ier_eoc.mask);
 497};
 498
 499/**
 500 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
 501 * @adc: stm32 adc instance
 502 */
 503static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
 504{
 505	stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
 506			   adc->cfg->regs->ier_eoc.mask);
 507}
 508
 
 
 
 
 
 
 
 
 
 
 
 
 509static void stm32_adc_set_res(struct stm32_adc *adc)
 510{
 511	const struct stm32_adc_regs *res = &adc->cfg->regs->res;
 512	u32 val;
 513
 514	val = stm32_adc_readl(adc, res->reg);
 515	val = (val & ~res->mask) | (adc->res << res->shift);
 516	stm32_adc_writel(adc, res->reg, val);
 517}
 518
 519static int stm32_adc_hw_stop(struct device *dev)
 520{
 521	struct stm32_adc *adc = dev_get_drvdata(dev);
 
 522
 523	if (adc->cfg->unprepare)
 524		adc->cfg->unprepare(adc);
 525
 526	if (adc->clk)
 527		clk_disable_unprepare(adc->clk);
 528
 529	return 0;
 530}
 531
 532static int stm32_adc_hw_start(struct device *dev)
 533{
 534	struct stm32_adc *adc = dev_get_drvdata(dev);
 
 535	int ret;
 536
 537	if (adc->clk) {
 538		ret = clk_prepare_enable(adc->clk);
 539		if (ret)
 540			return ret;
 541	}
 542
 543	stm32_adc_set_res(adc);
 544
 545	if (adc->cfg->prepare) {
 546		ret = adc->cfg->prepare(adc);
 547		if (ret)
 548			goto err_clk_dis;
 549	}
 550
 551	return 0;
 552
 553err_clk_dis:
 554	if (adc->clk)
 555		clk_disable_unprepare(adc->clk);
 556
 557	return ret;
 558}
 559
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 560/**
 561 * stm32f4_adc_start_conv() - Start conversions for regular channels.
 562 * @adc: stm32 adc instance
 563 * @dma: use dma to transfer conversion result
 564 *
 565 * Start conversions for regular channels.
 566 * Also take care of normal or DMA mode. Circular DMA may be used for regular
 567 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
 568 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
 569 */
 570static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
 571{
 
 
 572	stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
 573
 574	if (dma)
 575		stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
 576				   STM32F4_DMA | STM32F4_DDS);
 577
 578	stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
 579
 580	/* Wait for Power-up time (tSTAB from datasheet) */
 581	usleep_range(2, 3);
 582
 583	/* Software start ? (e.g. trigger detection disabled ?) */
 584	if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
 585		stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
 586}
 587
 588static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
 589{
 
 
 590	stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
 591	stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
 592
 593	stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
 594	stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
 595			   STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
 596}
 597
 598static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
 599{
 
 
 
 
 
 
 
 
 600	enum stm32h7_adc_dmngt dmngt;
 601	unsigned long flags;
 602	u32 val;
 603
 604	if (dma)
 605		dmngt = STM32H7_DMNGT_DMA_CIRC;
 606	else
 607		dmngt = STM32H7_DMNGT_DR_ONLY;
 608
 609	spin_lock_irqsave(&adc->lock, flags);
 610	val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
 611	val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
 612	stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
 613	spin_unlock_irqrestore(&adc->lock, flags);
 614
 615	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
 616}
 617
 618static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
 619{
 620	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 621	int ret;
 622	u32 val;
 623
 624	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
 625
 626	ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 627					   !(val & (STM32H7_ADSTART)),
 628					   100, STM32_ADC_TIMEOUT_US);
 629	if (ret)
 630		dev_warn(&indio_dev->dev, "stop failed\n");
 631
 
 632	stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
 633}
 634
 635static int stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 636{
 637	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 638	int ret;
 639	u32 val;
 640
 641	/* Exit deep power down, then enable ADC voltage regulator */
 642	stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
 643	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
 644
 645	if (adc->common->rate > STM32H7_BOOST_CLKRATE)
 
 646		stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
 647
 648	/* Wait for startup time */
 649	if (!adc->cfg->has_vregready) {
 650		usleep_range(10, 20);
 651		return 0;
 652	}
 653
 654	ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
 655					   val & STM32MP1_VREGREADY, 100,
 656					   STM32_ADC_TIMEOUT_US);
 657	if (ret) {
 658		stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
 659		dev_err(&indio_dev->dev, "Failed to exit power down\n");
 660	}
 661
 662	return ret;
 663}
 664
 665static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
 666{
 667	stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
 
 668
 669	/* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
 670	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
 671}
 672
 673static int stm32h7_adc_enable(struct stm32_adc *adc)
 674{
 675	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 676	int ret;
 677	u32 val;
 678
 679	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
 680
 681	/* Poll for ADRDY to be set (after adc startup time) */
 682	ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
 683					   val & STM32H7_ADRDY,
 684					   100, STM32_ADC_TIMEOUT_US);
 685	if (ret) {
 686		stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
 687		dev_err(&indio_dev->dev, "Failed to enable ADC\n");
 688	} else {
 689		/* Clear ADRDY by writing one */
 690		stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
 691	}
 692
 693	return ret;
 694}
 695
 696static void stm32h7_adc_disable(struct stm32_adc *adc)
 697{
 698	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 699	int ret;
 700	u32 val;
 701
 
 
 
 702	/* Disable ADC and wait until it's effectively disabled */
 703	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
 704	ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 705					   !(val & STM32H7_ADEN), 100,
 706					   STM32_ADC_TIMEOUT_US);
 707	if (ret)
 708		dev_warn(&indio_dev->dev, "Failed to disable\n");
 709}
 710
 711/**
 712 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
 713 * @adc: stm32 adc instance
 714 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
 715 */
 716static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
 717{
 718	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 719	int i, ret;
 720	u32 lincalrdyw_mask, val;
 721
 722	/* Read linearity calibration */
 723	lincalrdyw_mask = STM32H7_LINCALRDYW6;
 724	for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
 725		/* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
 726		stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
 727
 728		/* Poll: wait calib data to be ready in CALFACT2 register */
 729		ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 730						   !(val & lincalrdyw_mask),
 731						   100, STM32_ADC_TIMEOUT_US);
 732		if (ret) {
 733			dev_err(&indio_dev->dev, "Failed to read calfact\n");
 734			return ret;
 735		}
 736
 737		val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
 738		adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
 739		adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
 740
 741		lincalrdyw_mask >>= 1;
 742	}
 743
 744	/* Read offset calibration */
 745	val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
 746	adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
 747	adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
 748	adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
 749	adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
 750	adc->cal.calibrated = true;
 751
 752	return 0;
 753}
 754
 755/**
 756 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
 757 * @adc: stm32 adc instance
 758 * Note: ADC must be enabled, with no on-going conversions.
 759 */
 760static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
 761{
 762	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 763	int i, ret;
 764	u32 lincalrdyw_mask, val;
 765
 766	val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
 767		(adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
 768	stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
 769
 770	lincalrdyw_mask = STM32H7_LINCALRDYW6;
 771	for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
 772		/*
 773		 * Write saved calibration data to shadow registers:
 774		 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
 775		 * data write. Then poll to wait for complete transfer.
 776		 */
 777		val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
 778		stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
 779		stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
 780		ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 781						   val & lincalrdyw_mask,
 782						   100, STM32_ADC_TIMEOUT_US);
 783		if (ret) {
 784			dev_err(&indio_dev->dev, "Failed to write calfact\n");
 785			return ret;
 786		}
 787
 788		/*
 789		 * Read back calibration data, has two effects:
 790		 * - It ensures bits LINCALRDYW[6..1] are kept cleared
 791		 *   for next time calibration needs to be restored.
 792		 * - BTW, bit clear triggers a read, then check data has been
 793		 *   correctly written.
 794		 */
 795		stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
 796		ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 797						   !(val & lincalrdyw_mask),
 798						   100, STM32_ADC_TIMEOUT_US);
 799		if (ret) {
 800			dev_err(&indio_dev->dev, "Failed to read calfact\n");
 801			return ret;
 802		}
 803		val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
 804		if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
 805			dev_err(&indio_dev->dev, "calfact not consistent\n");
 806			return -EIO;
 807		}
 808
 809		lincalrdyw_mask >>= 1;
 810	}
 811
 812	return 0;
 813}
 814
 815/**
 816 * Fixed timeout value for ADC calibration.
 817 * worst cases:
 818 * - low clock frequency
 819 * - maximum prescalers
 820 * Calibration requires:
 821 * - 131,072 ADC clock cycle for the linear calibration
 822 * - 20 ADC clock cycle for the offset calibration
 823 *
 824 * Set to 100ms for now
 825 */
 826#define STM32H7_ADC_CALIB_TIMEOUT_US		100000
 827
 828/**
 829 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
 830 * @adc: stm32 adc instance
 
 831 * Note: Must be called once ADC is out of power down.
 
 
 
 832 */
 833static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
 834{
 835	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 836	int ret;
 
 837	u32 val;
 838
 839	if (adc->cal.calibrated)
 840		return true;
 
 
 841
 842	/*
 843	 * Select calibration mode:
 844	 * - Offset calibration for single ended inputs
 845	 * - No linearity calibration (do it later, before reading it)
 846	 */
 847	stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
 848	stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
 849
 850	/* Start calibration, then wait for completion */
 851	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
 852	ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 853					   !(val & STM32H7_ADCAL), 100,
 854					   STM32H7_ADC_CALIB_TIMEOUT_US);
 855	if (ret) {
 856		dev_err(&indio_dev->dev, "calibration failed\n");
 857		goto out;
 858	}
 859
 860	/*
 861	 * Select calibration mode, then start calibration:
 862	 * - Offset calibration for differential input
 863	 * - Linearity calibration (needs to be done only once for single/diff)
 864	 *   will run simultaneously with offset calibration.
 865	 */
 866	stm32_adc_set_bits(adc, STM32H7_ADC_CR,
 867			   STM32H7_ADCALDIF | STM32H7_ADCALLIN);
 868	stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
 869	ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
 870					   !(val & STM32H7_ADCAL), 100,
 871					   STM32H7_ADC_CALIB_TIMEOUT_US);
 872	if (ret) {
 873		dev_err(&indio_dev->dev, "calibration failed\n");
 
 874		goto out;
 875	}
 876
 877out:
 878	stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
 879			   STM32H7_ADCALDIF | STM32H7_ADCALLIN);
 880
 881	return ret;
 882}
 883
 884/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 885 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
 886 * @adc: stm32 adc instance
 887 * Leave power down mode.
 888 * Configure channels as single ended or differential before enabling ADC.
 889 * Enable ADC.
 890 * Restore calibration data.
 891 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
 892 * - Only one input is selected for single ended (e.g. 'vinp')
 893 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
 894 */
 895static int stm32h7_adc_prepare(struct stm32_adc *adc)
 896{
 897	int calib, ret;
 
 
 898
 899	ret = stm32h7_adc_exit_pwr_down(adc);
 900	if (ret)
 901		return ret;
 902
 903	ret = stm32h7_adc_selfcalib(adc);
 
 
 
 
 904	if (ret < 0)
 905		goto pwr_dwn;
 906	calib = ret;
 907
 908	stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
 909
 910	ret = stm32h7_adc_enable(adc);
 911	if (ret)
 912		goto pwr_dwn;
 913
 914	/* Either restore or read calibration result for future reference */
 915	if (calib)
 916		ret = stm32h7_adc_restore_selfcalib(adc);
 917	else
 918		ret = stm32h7_adc_read_selfcalib(adc);
 919	if (ret)
 920		goto disable;
 921
 922	stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
 
 
 
 
 
 
 
 
 
 
 
 923
 924	return 0;
 925
 926disable:
 927	stm32h7_adc_disable(adc);
 
 
 928pwr_dwn:
 929	stm32h7_adc_enter_pwr_down(adc);
 930
 931	return ret;
 932}
 933
 934static void stm32h7_adc_unprepare(struct stm32_adc *adc)
 935{
 936	stm32h7_adc_disable(adc);
 
 
 
 
 
 937	stm32h7_adc_enter_pwr_down(adc);
 938}
 939
 940/**
 941 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
 942 * @indio_dev: IIO device
 943 * @scan_mask: channels to be converted
 944 *
 945 * Conversion sequence :
 946 * Apply sampling time settings for all channels.
 947 * Configure ADC scan sequence based on selected channels in scan_mask.
 948 * Add channels to SQR registers, from scan_mask LSB to MSB, then
 949 * program sequence len.
 950 */
 951static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
 952				   const unsigned long *scan_mask)
 953{
 954	struct stm32_adc *adc = iio_priv(indio_dev);
 955	const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
 956	const struct iio_chan_spec *chan;
 957	u32 val, bit;
 958	int i = 0;
 959
 960	/* Apply sampling time settings */
 961	stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
 962	stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
 963
 964	for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
 965		chan = indio_dev->channels + bit;
 966		/*
 967		 * Assign one channel per SQ entry in regular
 968		 * sequence, starting with SQ1.
 969		 */
 970		i++;
 971		if (i > STM32_ADC_MAX_SQ)
 972			return -EINVAL;
 973
 974		dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
 975			__func__, chan->channel, i);
 976
 977		val = stm32_adc_readl(adc, sqr[i].reg);
 978		val &= ~sqr[i].mask;
 979		val |= chan->channel << sqr[i].shift;
 980		stm32_adc_writel(adc, sqr[i].reg, val);
 981	}
 982
 983	if (!i)
 984		return -EINVAL;
 985
 986	/* Sequence len */
 987	val = stm32_adc_readl(adc, sqr[0].reg);
 988	val &= ~sqr[0].mask;
 989	val |= ((i - 1) << sqr[0].shift);
 990	stm32_adc_writel(adc, sqr[0].reg, val);
 991
 992	return 0;
 993}
 994
 995/**
 996 * stm32_adc_get_trig_extsel() - Get external trigger selection
 
 997 * @trig: trigger
 998 *
 999 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1000 */
1001static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
1002				     struct iio_trigger *trig)
1003{
1004	struct stm32_adc *adc = iio_priv(indio_dev);
1005	int i;
1006
1007	/* lookup triggers registered by stm32 timer trigger driver */
1008	for (i = 0; adc->cfg->trigs[i].name; i++) {
1009		/**
1010		 * Checking both stm32 timer trigger type and trig name
1011		 * should be safe against arbitrary trigger names.
1012		 */
1013		if ((is_stm32_timer_trigger(trig) ||
1014		     is_stm32_lptim_trigger(trig)) &&
1015		    !strcmp(adc->cfg->trigs[i].name, trig->name)) {
1016			return adc->cfg->trigs[i].extsel;
1017		}
1018	}
1019
1020	return -EINVAL;
1021}
1022
1023/**
1024 * stm32_adc_set_trig() - Set a regular trigger
1025 * @indio_dev: IIO device
1026 * @trig: IIO trigger
1027 *
1028 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
1029 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1030 * - if HW trigger enabled, set source & polarity
1031 */
1032static int stm32_adc_set_trig(struct iio_dev *indio_dev,
1033			      struct iio_trigger *trig)
1034{
1035	struct stm32_adc *adc = iio_priv(indio_dev);
1036	u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
1037	unsigned long flags;
1038	int ret;
1039
1040	if (trig) {
1041		ret = stm32_adc_get_trig_extsel(indio_dev, trig);
1042		if (ret < 0)
1043			return ret;
1044
1045		/* set trigger source and polarity (default to rising edge) */
1046		extsel = ret;
1047		exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1048	}
1049
1050	spin_lock_irqsave(&adc->lock, flags);
1051	val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1052	val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1053	val |= exten << adc->cfg->regs->exten.shift;
1054	val |= extsel << adc->cfg->regs->extsel.shift;
1055	stm32_adc_writel(adc,  adc->cfg->regs->exten.reg, val);
1056	spin_unlock_irqrestore(&adc->lock, flags);
1057
1058	return 0;
1059}
1060
1061static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
1062				  const struct iio_chan_spec *chan,
1063				  unsigned int type)
1064{
1065	struct stm32_adc *adc = iio_priv(indio_dev);
1066
1067	adc->trigger_polarity = type;
1068
1069	return 0;
1070}
1071
1072static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
1073				  const struct iio_chan_spec *chan)
1074{
1075	struct stm32_adc *adc = iio_priv(indio_dev);
1076
1077	return adc->trigger_polarity;
1078}
1079
1080static const char * const stm32_trig_pol_items[] = {
1081	"rising-edge", "falling-edge", "both-edges",
1082};
1083
1084static const struct iio_enum stm32_adc_trig_pol = {
1085	.items = stm32_trig_pol_items,
1086	.num_items = ARRAY_SIZE(stm32_trig_pol_items),
1087	.get = stm32_adc_get_trig_pol,
1088	.set = stm32_adc_set_trig_pol,
1089};
1090
1091/**
1092 * stm32_adc_single_conv() - Performs a single conversion
1093 * @indio_dev: IIO device
1094 * @chan: IIO channel
1095 * @res: conversion result
1096 *
1097 * The function performs a single conversion on a given channel:
1098 * - Apply sampling time settings
1099 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1100 * - Use SW trigger
1101 * - Start conversion, then wait for interrupt completion.
1102 */
1103static int stm32_adc_single_conv(struct iio_dev *indio_dev,
1104				 const struct iio_chan_spec *chan,
1105				 int *res)
1106{
1107	struct stm32_adc *adc = iio_priv(indio_dev);
1108	struct device *dev = indio_dev->dev.parent;
1109	const struct stm32_adc_regspec *regs = adc->cfg->regs;
1110	long timeout;
1111	u32 val;
1112	int ret;
1113
1114	reinit_completion(&adc->completion);
1115
1116	adc->bufi = 0;
1117
1118	ret = pm_runtime_get_sync(dev);
1119	if (ret < 0) {
1120		pm_runtime_put_noidle(dev);
1121		return ret;
1122	}
1123
1124	/* Apply sampling time settings */
1125	stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1126	stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1127
1128	/* Program chan number in regular sequence (SQ1) */
1129	val = stm32_adc_readl(adc, regs->sqr[1].reg);
1130	val &= ~regs->sqr[1].mask;
1131	val |= chan->channel << regs->sqr[1].shift;
1132	stm32_adc_writel(adc, regs->sqr[1].reg, val);
1133
1134	/* Set regular sequence len (0 for 1 conversion) */
1135	stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1136
1137	/* Trigger detection disabled (conversion can be launched in SW) */
1138	stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1139
1140	stm32_adc_conv_irq_enable(adc);
1141
1142	adc->cfg->start_conv(adc, false);
1143
1144	timeout = wait_for_completion_interruptible_timeout(
1145					&adc->completion, STM32_ADC_TIMEOUT);
1146	if (timeout == 0) {
1147		ret = -ETIMEDOUT;
1148	} else if (timeout < 0) {
1149		ret = timeout;
1150	} else {
1151		*res = adc->buffer[0];
1152		ret = IIO_VAL_INT;
1153	}
1154
1155	adc->cfg->stop_conv(adc);
1156
1157	stm32_adc_conv_irq_disable(adc);
1158
1159	pm_runtime_mark_last_busy(dev);
1160	pm_runtime_put_autosuspend(dev);
1161
1162	return ret;
1163}
1164
1165static int stm32_adc_read_raw(struct iio_dev *indio_dev,
1166			      struct iio_chan_spec const *chan,
1167			      int *val, int *val2, long mask)
1168{
1169	struct stm32_adc *adc = iio_priv(indio_dev);
1170	int ret;
1171
1172	switch (mask) {
1173	case IIO_CHAN_INFO_RAW:
 
1174		ret = iio_device_claim_direct_mode(indio_dev);
1175		if (ret)
1176			return ret;
1177		if (chan->type == IIO_VOLTAGE)
1178			ret = stm32_adc_single_conv(indio_dev, chan, val);
1179		else
1180			ret = -EINVAL;
 
 
 
 
1181		iio_device_release_direct_mode(indio_dev);
1182		return ret;
1183
1184	case IIO_CHAN_INFO_SCALE:
1185		if (chan->differential) {
1186			*val = adc->common->vref_mv * 2;
1187			*val2 = chan->scan_type.realbits;
1188		} else {
1189			*val = adc->common->vref_mv;
1190			*val2 = chan->scan_type.realbits;
1191		}
1192		return IIO_VAL_FRACTIONAL_LOG2;
1193
1194	case IIO_CHAN_INFO_OFFSET:
1195		if (chan->differential)
1196			/* ADC_full_scale / 2 */
1197			*val = -((1 << chan->scan_type.realbits) / 2);
1198		else
1199			*val = 0;
1200		return IIO_VAL_INT;
1201
1202	default:
1203		return -EINVAL;
1204	}
1205}
1206
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1207static irqreturn_t stm32_adc_isr(int irq, void *data)
1208{
1209	struct stm32_adc *adc = data;
1210	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1211	const struct stm32_adc_regspec *regs = adc->cfg->regs;
1212	u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1213
 
 
 
 
 
 
 
 
 
 
 
 
 
1214	if (status & regs->isr_eoc.mask) {
1215		/* Reading DR also clears EOC status flag */
1216		adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1217		if (iio_buffer_enabled(indio_dev)) {
1218			adc->bufi++;
1219			if (adc->bufi >= adc->num_conv) {
1220				stm32_adc_conv_irq_disable(adc);
1221				iio_trigger_poll(indio_dev->trig);
1222			}
1223		} else {
1224			complete(&adc->completion);
1225		}
1226		return IRQ_HANDLED;
1227	}
1228
1229	return IRQ_NONE;
1230}
1231
1232/**
1233 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1234 * @indio_dev: IIO device
1235 * @trig: new trigger
1236 *
1237 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1238 * driver, -EINVAL otherwise.
1239 */
1240static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
1241				      struct iio_trigger *trig)
1242{
1243	return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1244}
1245
1246static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1247{
1248	struct stm32_adc *adc = iio_priv(indio_dev);
1249	unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
1250	unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
1251
1252	/*
1253	 * dma cyclic transfers are used, buffer is split into two periods.
1254	 * There should be :
1255	 * - always one buffer (period) dma is working on
1256	 * - one buffer (period) driver can push with iio_trigger_poll().
1257	 */
1258	watermark = min(watermark, val * (unsigned)(sizeof(u16)));
1259	adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1260
1261	return 0;
1262}
1263
1264static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
1265				      const unsigned long *scan_mask)
1266{
1267	struct stm32_adc *adc = iio_priv(indio_dev);
1268	struct device *dev = indio_dev->dev.parent;
1269	int ret;
1270
1271	ret = pm_runtime_get_sync(dev);
1272	if (ret < 0) {
1273		pm_runtime_put_noidle(dev);
1274		return ret;
1275	}
1276
1277	adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1278
1279	ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1280	pm_runtime_mark_last_busy(dev);
1281	pm_runtime_put_autosuspend(dev);
1282
1283	return ret;
1284}
1285
1286static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1287			      const struct of_phandle_args *iiospec)
1288{
1289	int i;
1290
1291	for (i = 0; i < indio_dev->num_channels; i++)
1292		if (indio_dev->channels[i].channel == iiospec->args[0])
1293			return i;
1294
1295	return -EINVAL;
1296}
1297
1298/**
1299 * stm32_adc_debugfs_reg_access - read or write register value
 
 
 
 
1300 *
1301 * To read a value from an ADC register:
1302 *   echo [ADC reg offset] > direct_reg_access
1303 *   cat direct_reg_access
1304 *
1305 * To write a value in a ADC register:
1306 *   echo [ADC_reg_offset] [value] > direct_reg_access
1307 */
1308static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
1309					unsigned reg, unsigned writeval,
1310					unsigned *readval)
1311{
1312	struct stm32_adc *adc = iio_priv(indio_dev);
1313	struct device *dev = indio_dev->dev.parent;
1314	int ret;
1315
1316	ret = pm_runtime_get_sync(dev);
1317	if (ret < 0) {
1318		pm_runtime_put_noidle(dev);
1319		return ret;
1320	}
1321
1322	if (!readval)
1323		stm32_adc_writel(adc, reg, writeval);
1324	else
1325		*readval = stm32_adc_readl(adc, reg);
1326
1327	pm_runtime_mark_last_busy(dev);
1328	pm_runtime_put_autosuspend(dev);
1329
1330	return 0;
1331}
1332
1333static const struct iio_info stm32_adc_iio_info = {
1334	.read_raw = stm32_adc_read_raw,
1335	.validate_trigger = stm32_adc_validate_trigger,
1336	.hwfifo_set_watermark = stm32_adc_set_watermark,
1337	.update_scan_mode = stm32_adc_update_scan_mode,
1338	.debugfs_reg_access = stm32_adc_debugfs_reg_access,
1339	.of_xlate = stm32_adc_of_xlate,
1340};
1341
1342static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1343{
1344	struct dma_tx_state state;
1345	enum dma_status status;
1346
1347	status = dmaengine_tx_status(adc->dma_chan,
1348				     adc->dma_chan->cookie,
1349				     &state);
1350	if (status == DMA_IN_PROGRESS) {
1351		/* Residue is size in bytes from end of buffer */
1352		unsigned int i = adc->rx_buf_sz - state.residue;
1353		unsigned int size;
1354
1355		/* Return available bytes */
1356		if (i >= adc->bufi)
1357			size = i - adc->bufi;
1358		else
1359			size = adc->rx_buf_sz + i - adc->bufi;
1360
1361		return size;
1362	}
1363
1364	return 0;
1365}
1366
1367static void stm32_adc_dma_buffer_done(void *data)
1368{
1369	struct iio_dev *indio_dev = data;
 
 
 
 
 
 
 
 
 
 
 
 
 
1370
1371	iio_trigger_poll_chained(indio_dev->trig);
 
 
 
 
 
 
 
 
 
1372}
1373
1374static int stm32_adc_dma_start(struct iio_dev *indio_dev)
1375{
1376	struct stm32_adc *adc = iio_priv(indio_dev);
1377	struct dma_async_tx_descriptor *desc;
1378	dma_cookie_t cookie;
1379	int ret;
1380
1381	if (!adc->dma_chan)
1382		return 0;
1383
1384	dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
1385		adc->rx_buf_sz, adc->rx_buf_sz / 2);
1386
1387	/* Prepare a DMA cyclic transaction */
1388	desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1389					 adc->rx_dma_buf,
1390					 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1391					 DMA_DEV_TO_MEM,
1392					 DMA_PREP_INTERRUPT);
1393	if (!desc)
1394		return -EBUSY;
1395
1396	desc->callback = stm32_adc_dma_buffer_done;
1397	desc->callback_param = indio_dev;
1398
1399	cookie = dmaengine_submit(desc);
1400	ret = dma_submit_error(cookie);
1401	if (ret) {
1402		dmaengine_terminate_sync(adc->dma_chan);
1403		return ret;
1404	}
1405
1406	/* Issue pending DMA requests */
1407	dma_async_issue_pending(adc->dma_chan);
1408
1409	return 0;
1410}
1411
1412static int __stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1413{
1414	struct stm32_adc *adc = iio_priv(indio_dev);
1415	struct device *dev = indio_dev->dev.parent;
1416	int ret;
1417
1418	ret = pm_runtime_get_sync(dev);
1419	if (ret < 0) {
1420		pm_runtime_put_noidle(dev);
1421		return ret;
1422	}
1423
1424	ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
1425	if (ret) {
1426		dev_err(&indio_dev->dev, "Can't set trigger\n");
1427		goto err_pm_put;
1428	}
1429
1430	ret = stm32_adc_dma_start(indio_dev);
1431	if (ret) {
1432		dev_err(&indio_dev->dev, "Can't start dma\n");
1433		goto err_clr_trig;
1434	}
1435
1436	/* Reset adc buffer index */
1437	adc->bufi = 0;
1438
 
 
1439	if (!adc->dma_chan)
1440		stm32_adc_conv_irq_enable(adc);
1441
1442	adc->cfg->start_conv(adc, !!adc->dma_chan);
1443
1444	return 0;
1445
1446err_clr_trig:
1447	stm32_adc_set_trig(indio_dev, NULL);
1448err_pm_put:
1449	pm_runtime_mark_last_busy(dev);
1450	pm_runtime_put_autosuspend(dev);
1451
1452	return ret;
1453}
1454
1455static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1456{
1457	int ret;
1458
1459	ret = iio_triggered_buffer_postenable(indio_dev);
1460	if (ret < 0)
1461		return ret;
1462
1463	ret = __stm32_adc_buffer_postenable(indio_dev);
1464	if (ret < 0)
1465		iio_triggered_buffer_predisable(indio_dev);
1466
1467	return ret;
1468}
1469
1470static void __stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1471{
1472	struct stm32_adc *adc = iio_priv(indio_dev);
1473	struct device *dev = indio_dev->dev.parent;
1474
1475	adc->cfg->stop_conv(adc);
1476	if (!adc->dma_chan)
1477		stm32_adc_conv_irq_disable(adc);
1478
 
 
1479	if (adc->dma_chan)
1480		dmaengine_terminate_sync(adc->dma_chan);
1481
1482	if (stm32_adc_set_trig(indio_dev, NULL))
1483		dev_err(&indio_dev->dev, "Can't clear trigger\n");
1484
1485	pm_runtime_mark_last_busy(dev);
1486	pm_runtime_put_autosuspend(dev);
1487}
1488
1489static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1490{
1491	int ret;
1492
1493	__stm32_adc_buffer_predisable(indio_dev);
1494
1495	ret = iio_triggered_buffer_predisable(indio_dev);
1496	if (ret < 0)
1497		dev_err(&indio_dev->dev, "predisable failed\n");
1498
1499	return ret;
1500}
1501
1502static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
1503	.postenable = &stm32_adc_buffer_postenable,
1504	.predisable = &stm32_adc_buffer_predisable,
1505};
1506
1507static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
1508{
1509	struct iio_poll_func *pf = p;
1510	struct iio_dev *indio_dev = pf->indio_dev;
1511	struct stm32_adc *adc = iio_priv(indio_dev);
1512
1513	dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1514
1515	if (!adc->dma_chan) {
1516		/* reset buffer index */
1517		adc->bufi = 0;
1518		iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1519						   pf->timestamp);
1520	} else {
1521		int residue = stm32_adc_dma_residue(adc);
1522
1523		while (residue >= indio_dev->scan_bytes) {
1524			u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1525
1526			iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1527							   pf->timestamp);
1528			residue -= indio_dev->scan_bytes;
1529			adc->bufi += indio_dev->scan_bytes;
1530			if (adc->bufi >= adc->rx_buf_sz)
1531				adc->bufi = 0;
1532		}
1533	}
1534
1535	iio_trigger_notify_done(indio_dev->trig);
1536
1537	/* re-enable eoc irq */
1538	if (!adc->dma_chan)
1539		stm32_adc_conv_irq_enable(adc);
1540
1541	return IRQ_HANDLED;
1542}
1543
1544static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
1545	IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
1546	{
1547		.name = "trigger_polarity_available",
1548		.shared = IIO_SHARED_BY_ALL,
1549		.read = iio_enum_available_read,
1550		.private = (uintptr_t)&stm32_adc_trig_pol,
1551	},
1552	{},
1553};
1554
1555static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1556{
1557	struct device_node *node = indio_dev->dev.of_node;
1558	struct stm32_adc *adc = iio_priv(indio_dev);
1559	unsigned int i;
1560	u32 res;
1561
1562	if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1563		res = adc->cfg->adc_info->resolutions[0];
1564
1565	for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1566		if (res == adc->cfg->adc_info->resolutions[i])
1567			break;
1568	if (i >= adc->cfg->adc_info->num_res) {
1569		dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1570		return -EINVAL;
1571	}
1572
1573	dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
1574	adc->res = i;
1575
1576	return 0;
1577}
1578
1579static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1580{
1581	const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1582	u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1583	unsigned int smp, r = smpr->reg;
 
 
 
 
 
 
 
 
1584
1585	/* Determine sampling time (ADC clock cycles) */
1586	period_ns = NSEC_PER_SEC / adc->common->rate;
1587	for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
1588		if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1589			break;
1590	if (smp > STM32_ADC_MAX_SMP)
1591		smp = STM32_ADC_MAX_SMP;
1592
1593	/* pre-build sampling time registers (e.g. smpr1, smpr2) */
1594	adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1595}
1596
1597static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
1598				    struct iio_chan_spec *chan, u32 vinp,
1599				    u32 vinn, int scan_index, bool differential)
1600{
1601	struct stm32_adc *adc = iio_priv(indio_dev);
1602	char *name = adc->chan_name[vinp];
1603
1604	chan->type = IIO_VOLTAGE;
1605	chan->channel = vinp;
1606	if (differential) {
1607		chan->differential = 1;
1608		chan->channel2 = vinn;
1609		snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn);
1610	} else {
1611		snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp);
1612	}
1613	chan->datasheet_name = name;
1614	chan->scan_index = scan_index;
1615	chan->indexed = 1;
1616	chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 
 
 
1617	chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
1618					 BIT(IIO_CHAN_INFO_OFFSET);
1619	chan->scan_type.sign = 'u';
1620	chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1621	chan->scan_type.storagebits = 16;
1622	chan->ext_info = stm32_adc_ext_info;
1623
1624	/* pre-build selected channels mask */
1625	adc->pcsel |= BIT(chan->channel);
1626	if (differential) {
1627		/* pre-build diff channels mask */
1628		adc->difsel |= BIT(chan->channel);
1629		/* Also add negative input to pre-selected channels */
1630		adc->pcsel |= BIT(chan->channel2);
1631	}
1632}
1633
1634static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
1635{
1636	struct device_node *node = indio_dev->dev.of_node;
1637	struct stm32_adc *adc = iio_priv(indio_dev);
1638	const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1639	struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
1640	struct property *prop;
1641	const __be32 *cur;
1642	struct iio_chan_spec *channels;
1643	int scan_index = 0, num_channels = 0, num_diff = 0, ret, i;
1644	u32 val, smp = 0;
1645
1646	ret = of_property_count_u32_elems(node, "st,adc-channels");
1647	if (ret > adc_info->max_channels) {
1648		dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1649		return -EINVAL;
1650	} else if (ret > 0) {
1651		num_channels += ret;
1652	}
1653
1654	ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
1655					      sizeof(*diff));
 
 
 
 
 
 
 
1656	if (ret > adc_info->max_channels) {
1657		dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1658		return -EINVAL;
1659	} else if (ret > 0) {
1660		int size = ret * sizeof(*diff) / sizeof(u32);
1661
1662		num_diff = ret;
1663		num_channels += ret;
1664		ret = of_property_read_u32_array(node, "st,adc-diff-channels",
1665						 (u32 *)diff, size);
1666		if (ret)
1667			return ret;
1668	}
1669
1670	if (!num_channels) {
1671		dev_err(&indio_dev->dev, "No channels configured\n");
1672		return -ENODATA;
1673	}
1674
1675	/* Optional sample time is provided either for each, or all channels */
1676	ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1677	if (ret > 1 && ret != num_channels) {
1678		dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1679		return -EINVAL;
1680	}
1681
1682	channels = devm_kcalloc(&indio_dev->dev, num_channels,
1683				sizeof(struct iio_chan_spec), GFP_KERNEL);
1684	if (!channels)
1685		return -ENOMEM;
1686
1687	of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1688		if (val >= adc_info->max_channels) {
1689			dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1690			return -EINVAL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1691		}
1692
1693		/* Channel can't be configured both as single-ended & diff */
1694		for (i = 0; i < num_diff; i++) {
1695			if (val == diff[i].vinp) {
1696				dev_err(&indio_dev->dev,
1697					"channel %d miss-configured\n",	val);
 
1698				return -EINVAL;
1699			}
 
 
 
 
 
1700		}
1701		stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
1702					0, scan_index, false);
1703		scan_index++;
1704	}
1705
1706	for (i = 0; i < num_diff; i++) {
1707		if (diff[i].vinp >= adc_info->max_channels ||
1708		    diff[i].vinn >= adc_info->max_channels) {
1709			dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
1710				diff[i].vinp, diff[i].vinn);
 
 
 
 
1711			return -EINVAL;
1712		}
 
 
 
 
 
 
 
 
1713		stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1714					diff[i].vinp, diff[i].vinn, scan_index,
1715					true);
1716		scan_index++;
1717	}
1718
 
 
 
 
 
 
 
1719	for (i = 0; i < scan_index; i++) {
1720		/*
1721		 * Using of_property_read_u32_index(), smp value will only be
1722		 * modified if valid u32 value can be decoded. This allows to
1723		 * get either no value, 1 shared value for all indexes, or one
1724		 * value per channel.
 
1725		 */
1726		of_property_read_u32_index(node, "st,min-sample-time-nsecs",
1727					   i, &smp);
 
1728		/* Prepare sampling time settings */
1729		stm32_adc_smpr_init(adc, channels[i].channel, smp);
1730	}
1731
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1732	indio_dev->num_channels = scan_index;
1733	indio_dev->channels = channels;
1734
1735	return 0;
1736}
1737
1738static int stm32_adc_dma_request(struct iio_dev *indio_dev)
1739{
1740	struct stm32_adc *adc = iio_priv(indio_dev);
1741	struct dma_slave_config config;
1742	int ret;
1743
1744	adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
1745	if (!adc->dma_chan)
 
 
 
 
 
 
 
1746		return 0;
 
1747
1748	adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1749					 STM32_DMA_BUFFER_SIZE,
1750					 &adc->rx_dma_buf, GFP_KERNEL);
1751	if (!adc->rx_buf) {
1752		ret = -ENOMEM;
1753		goto err_release;
1754	}
1755
1756	/* Configure DMA channel to read data register */
1757	memset(&config, 0, sizeof(config));
1758	config.src_addr = (dma_addr_t)adc->common->phys_base;
1759	config.src_addr += adc->offset + adc->cfg->regs->dr;
1760	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1761
1762	ret = dmaengine_slave_config(adc->dma_chan, &config);
1763	if (ret)
1764		goto err_free;
1765
1766	return 0;
1767
1768err_free:
1769	dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1770			  adc->rx_buf, adc->rx_dma_buf);
1771err_release:
1772	dma_release_channel(adc->dma_chan);
1773
1774	return ret;
1775}
1776
1777static int stm32_adc_probe(struct platform_device *pdev)
1778{
1779	struct iio_dev *indio_dev;
1780	struct device *dev = &pdev->dev;
 
1781	struct stm32_adc *adc;
 
1782	int ret;
1783
1784	if (!pdev->dev.of_node)
1785		return -ENODEV;
1786
1787	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1788	if (!indio_dev)
1789		return -ENOMEM;
1790
1791	adc = iio_priv(indio_dev);
1792	adc->common = dev_get_drvdata(pdev->dev.parent);
1793	spin_lock_init(&adc->lock);
1794	init_completion(&adc->completion);
1795	adc->cfg = (const struct stm32_adc_cfg *)
1796		of_match_device(dev->driver->of_match_table, dev)->data;
1797
1798	indio_dev->name = dev_name(&pdev->dev);
1799	indio_dev->dev.parent = &pdev->dev;
1800	indio_dev->dev.of_node = pdev->dev.of_node;
1801	indio_dev->info = &stm32_adc_iio_info;
1802	indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
1803
1804	platform_set_drvdata(pdev, adc);
1805
1806	ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1807	if (ret != 0) {
1808		dev_err(&pdev->dev, "missing reg property\n");
1809		return -EINVAL;
1810	}
1811
1812	adc->irq = platform_get_irq(pdev, 0);
1813	if (adc->irq < 0)
1814		return adc->irq;
1815
1816	ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1817			       0, pdev->name, adc);
 
1818	if (ret) {
1819		dev_err(&pdev->dev, "failed to request IRQ\n");
1820		return ret;
1821	}
1822
1823	adc->clk = devm_clk_get(&pdev->dev, NULL);
1824	if (IS_ERR(adc->clk)) {
1825		ret = PTR_ERR(adc->clk);
1826		if (ret == -ENOENT && !adc->cfg->clk_required) {
1827			adc->clk = NULL;
1828		} else {
1829			dev_err(&pdev->dev, "Can't get clock\n");
1830			return ret;
1831		}
1832	}
1833
1834	ret = stm32_adc_of_get_resolution(indio_dev);
1835	if (ret < 0)
1836		return ret;
1837
1838	ret = stm32_adc_chan_of_init(indio_dev);
1839	if (ret < 0)
1840		return ret;
1841
1842	ret = stm32_adc_dma_request(indio_dev);
 
 
 
 
 
 
 
 
 
1843	if (ret < 0)
1844		return ret;
1845
1846	ret = iio_triggered_buffer_setup(indio_dev,
1847					 &iio_pollfunc_store_time,
1848					 &stm32_adc_trigger_handler,
1849					 &stm32_adc_buffer_setup_ops);
1850	if (ret) {
1851		dev_err(&pdev->dev, "buffer setup failed\n");
1852		goto err_dma_disable;
1853	}
1854
1855	/* Get stm32-adc-core PM online */
1856	pm_runtime_get_noresume(dev);
1857	pm_runtime_set_active(dev);
1858	pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS);
1859	pm_runtime_use_autosuspend(dev);
1860	pm_runtime_enable(dev);
1861
1862	ret = stm32_adc_hw_start(dev);
1863	if (ret)
1864		goto err_buffer_cleanup;
1865
1866	ret = iio_device_register(indio_dev);
1867	if (ret) {
1868		dev_err(&pdev->dev, "iio dev register failed\n");
1869		goto err_hw_stop;
1870	}
1871
1872	pm_runtime_mark_last_busy(dev);
1873	pm_runtime_put_autosuspend(dev);
1874
 
 
 
1875	return 0;
1876
1877err_hw_stop:
1878	stm32_adc_hw_stop(dev);
1879
1880err_buffer_cleanup:
1881	pm_runtime_disable(dev);
1882	pm_runtime_set_suspended(dev);
1883	pm_runtime_put_noidle(dev);
1884	iio_triggered_buffer_cleanup(indio_dev);
1885
1886err_dma_disable:
1887	if (adc->dma_chan) {
1888		dma_free_coherent(adc->dma_chan->device->dev,
1889				  STM32_DMA_BUFFER_SIZE,
1890				  adc->rx_buf, adc->rx_dma_buf);
1891		dma_release_channel(adc->dma_chan);
1892	}
1893
1894	return ret;
1895}
1896
1897static int stm32_adc_remove(struct platform_device *pdev)
1898{
1899	struct stm32_adc *adc = platform_get_drvdata(pdev);
1900	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1901
1902	pm_runtime_get_sync(&pdev->dev);
 
1903	iio_device_unregister(indio_dev);
1904	stm32_adc_hw_stop(&pdev->dev);
1905	pm_runtime_disable(&pdev->dev);
1906	pm_runtime_set_suspended(&pdev->dev);
1907	pm_runtime_put_noidle(&pdev->dev);
1908	iio_triggered_buffer_cleanup(indio_dev);
1909	if (adc->dma_chan) {
1910		dma_free_coherent(adc->dma_chan->device->dev,
1911				  STM32_DMA_BUFFER_SIZE,
1912				  adc->rx_buf, adc->rx_dma_buf);
1913		dma_release_channel(adc->dma_chan);
1914	}
1915
1916	return 0;
1917}
1918
1919#if defined(CONFIG_PM_SLEEP)
1920static int stm32_adc_suspend(struct device *dev)
1921{
1922	struct stm32_adc *adc = dev_get_drvdata(dev);
1923	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1924
1925	if (iio_buffer_enabled(indio_dev))
1926		__stm32_adc_buffer_predisable(indio_dev);
1927
1928	return pm_runtime_force_suspend(dev);
1929}
1930
1931static int stm32_adc_resume(struct device *dev)
1932{
1933	struct stm32_adc *adc = dev_get_drvdata(dev);
1934	struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1935	int ret;
1936
1937	ret = pm_runtime_force_resume(dev);
1938	if (ret < 0)
1939		return ret;
1940
1941	if (!iio_buffer_enabled(indio_dev))
1942		return 0;
1943
1944	ret = stm32_adc_update_scan_mode(indio_dev,
1945					 indio_dev->active_scan_mask);
1946	if (ret < 0)
1947		return ret;
1948
1949	return __stm32_adc_buffer_postenable(indio_dev);
1950}
1951#endif
1952
1953#if defined(CONFIG_PM)
1954static int stm32_adc_runtime_suspend(struct device *dev)
1955{
1956	return stm32_adc_hw_stop(dev);
1957}
1958
1959static int stm32_adc_runtime_resume(struct device *dev)
1960{
1961	return stm32_adc_hw_start(dev);
1962}
1963#endif
1964
1965static const struct dev_pm_ops stm32_adc_pm_ops = {
1966	SET_SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume)
1967	SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume,
1968			   NULL)
1969};
1970
1971static const struct stm32_adc_cfg stm32f4_adc_cfg = {
1972	.regs = &stm32f4_adc_regspec,
1973	.adc_info = &stm32f4_adc_info,
1974	.trigs = stm32f4_adc_trigs,
1975	.clk_required = true,
1976	.start_conv = stm32f4_adc_start_conv,
1977	.stop_conv = stm32f4_adc_stop_conv,
1978	.smp_cycles = stm32f4_adc_smp_cycles,
 
1979};
1980
 
 
 
1981static const struct stm32_adc_cfg stm32h7_adc_cfg = {
1982	.regs = &stm32h7_adc_regspec,
1983	.adc_info = &stm32h7_adc_info,
1984	.trigs = stm32h7_adc_trigs,
 
 
 
1985	.start_conv = stm32h7_adc_start_conv,
1986	.stop_conv = stm32h7_adc_stop_conv,
1987	.prepare = stm32h7_adc_prepare,
1988	.unprepare = stm32h7_adc_unprepare,
1989	.smp_cycles = stm32h7_adc_smp_cycles,
 
 
1990};
1991
 
 
 
1992static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
1993	.regs = &stm32h7_adc_regspec,
1994	.adc_info = &stm32h7_adc_info,
1995	.trigs = stm32h7_adc_trigs,
1996	.has_vregready = true,
 
 
 
1997	.start_conv = stm32h7_adc_start_conv,
1998	.stop_conv = stm32h7_adc_stop_conv,
1999	.prepare = stm32h7_adc_prepare,
2000	.unprepare = stm32h7_adc_unprepare,
2001	.smp_cycles = stm32h7_adc_smp_cycles,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2002};
2003
2004static const struct of_device_id stm32_adc_of_match[] = {
2005	{ .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2006	{ .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2007	{ .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
 
2008	{},
2009};
2010MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
2011
2012static struct platform_driver stm32_adc_driver = {
2013	.probe = stm32_adc_probe,
2014	.remove = stm32_adc_remove,
2015	.driver = {
2016		.name = "stm32-adc",
2017		.of_match_table = stm32_adc_of_match,
2018		.pm = &stm32_adc_pm_ops,
2019	},
2020};
2021module_platform_driver(stm32_adc_driver);
2022
2023MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
2024MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2025MODULE_LICENSE("GPL v2");
2026MODULE_ALIAS("platform:stm32-adc");