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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * intel_pt.c: Intel Processor Trace support
4 * Copyright (c) 2013-2015, Intel Corporation.
5 */
6
7#include <inttypes.h>
8#include <stdio.h>
9#include <stdbool.h>
10#include <errno.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/types.h>
14#include <linux/zalloc.h>
15
16#include "session.h"
17#include "machine.h"
18#include "memswap.h"
19#include "sort.h"
20#include "tool.h"
21#include "event.h"
22#include "evlist.h"
23#include "evsel.h"
24#include "map.h"
25#include "color.h"
26#include "thread.h"
27#include "thread-stack.h"
28#include "symbol.h"
29#include "callchain.h"
30#include "dso.h"
31#include "debug.h"
32#include "auxtrace.h"
33#include "tsc.h"
34#include "intel-pt.h"
35#include "config.h"
36#include "util/synthetic-events.h"
37#include "time-utils.h"
38
39#include "../arch/x86/include/uapi/asm/perf_regs.h"
40
41#include "intel-pt-decoder/intel-pt-log.h"
42#include "intel-pt-decoder/intel-pt-decoder.h"
43#include "intel-pt-decoder/intel-pt-insn-decoder.h"
44#include "intel-pt-decoder/intel-pt-pkt-decoder.h"
45
46#define MAX_TIMESTAMP (~0ULL)
47
48struct range {
49 u64 start;
50 u64 end;
51};
52
53struct intel_pt {
54 struct auxtrace auxtrace;
55 struct auxtrace_queues queues;
56 struct auxtrace_heap heap;
57 u32 auxtrace_type;
58 struct perf_session *session;
59 struct machine *machine;
60 struct evsel *switch_evsel;
61 struct thread *unknown_thread;
62 bool timeless_decoding;
63 bool sampling_mode;
64 bool snapshot_mode;
65 bool per_cpu_mmaps;
66 bool have_tsc;
67 bool data_queued;
68 bool est_tsc;
69 bool sync_switch;
70 bool mispred_all;
71 int have_sched_switch;
72 u32 pmu_type;
73 u64 kernel_start;
74 u64 switch_ip;
75 u64 ptss_ip;
76
77 struct perf_tsc_conversion tc;
78 bool cap_user_time_zero;
79
80 struct itrace_synth_opts synth_opts;
81
82 bool sample_instructions;
83 u64 instructions_sample_type;
84 u64 instructions_id;
85
86 bool sample_branches;
87 u32 branches_filter;
88 u64 branches_sample_type;
89 u64 branches_id;
90
91 bool sample_transactions;
92 u64 transactions_sample_type;
93 u64 transactions_id;
94
95 bool sample_ptwrites;
96 u64 ptwrites_sample_type;
97 u64 ptwrites_id;
98
99 bool sample_pwr_events;
100 u64 pwr_events_sample_type;
101 u64 mwait_id;
102 u64 pwre_id;
103 u64 exstop_id;
104 u64 pwrx_id;
105 u64 cbr_id;
106
107 bool sample_pebs;
108 struct evsel *pebs_evsel;
109
110 u64 tsc_bit;
111 u64 mtc_bit;
112 u64 mtc_freq_bits;
113 u32 tsc_ctc_ratio_n;
114 u32 tsc_ctc_ratio_d;
115 u64 cyc_bit;
116 u64 noretcomp_bit;
117 unsigned max_non_turbo_ratio;
118 unsigned cbr2khz;
119
120 unsigned long num_events;
121
122 char *filter;
123 struct addr_filters filts;
124
125 struct range *time_ranges;
126 unsigned int range_cnt;
127};
128
129enum switch_state {
130 INTEL_PT_SS_NOT_TRACING,
131 INTEL_PT_SS_UNKNOWN,
132 INTEL_PT_SS_TRACING,
133 INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
134 INTEL_PT_SS_EXPECTING_SWITCH_IP,
135};
136
137struct intel_pt_queue {
138 struct intel_pt *pt;
139 unsigned int queue_nr;
140 struct auxtrace_buffer *buffer;
141 struct auxtrace_buffer *old_buffer;
142 void *decoder;
143 const struct intel_pt_state *state;
144 struct ip_callchain *chain;
145 struct branch_stack *last_branch;
146 struct branch_stack *last_branch_rb;
147 size_t last_branch_pos;
148 union perf_event *event_buf;
149 bool on_heap;
150 bool stop;
151 bool step_through_buffers;
152 bool use_buffer_pid_tid;
153 bool sync_switch;
154 pid_t pid, tid;
155 int cpu;
156 int switch_state;
157 pid_t next_tid;
158 struct thread *thread;
159 bool exclude_kernel;
160 bool have_sample;
161 u64 time;
162 u64 timestamp;
163 u64 sel_timestamp;
164 bool sel_start;
165 unsigned int sel_idx;
166 u32 flags;
167 u16 insn_len;
168 u64 last_insn_cnt;
169 u64 ipc_insn_cnt;
170 u64 ipc_cyc_cnt;
171 u64 last_in_insn_cnt;
172 u64 last_in_cyc_cnt;
173 u64 last_br_insn_cnt;
174 u64 last_br_cyc_cnt;
175 unsigned int cbr_seen;
176 char insn[INTEL_PT_INSN_BUF_SZ];
177};
178
179static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
180 unsigned char *buf, size_t len)
181{
182 struct intel_pt_pkt packet;
183 size_t pos = 0;
184 int ret, pkt_len, i;
185 char desc[INTEL_PT_PKT_DESC_MAX];
186 const char *color = PERF_COLOR_BLUE;
187 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX;
188
189 color_fprintf(stdout, color,
190 ". ... Intel Processor Trace data: size %zu bytes\n",
191 len);
192
193 while (len) {
194 ret = intel_pt_get_packet(buf, len, &packet, &ctx);
195 if (ret > 0)
196 pkt_len = ret;
197 else
198 pkt_len = 1;
199 printf(".");
200 color_fprintf(stdout, color, " %08x: ", pos);
201 for (i = 0; i < pkt_len; i++)
202 color_fprintf(stdout, color, " %02x", buf[i]);
203 for (; i < 16; i++)
204 color_fprintf(stdout, color, " ");
205 if (ret > 0) {
206 ret = intel_pt_pkt_desc(&packet, desc,
207 INTEL_PT_PKT_DESC_MAX);
208 if (ret > 0)
209 color_fprintf(stdout, color, " %s\n", desc);
210 } else {
211 color_fprintf(stdout, color, " Bad packet!\n");
212 }
213 pos += pkt_len;
214 buf += pkt_len;
215 len -= pkt_len;
216 }
217}
218
219static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
220 size_t len)
221{
222 printf(".\n");
223 intel_pt_dump(pt, buf, len);
224}
225
226static void intel_pt_log_event(union perf_event *event)
227{
228 FILE *f = intel_pt_log_fp();
229
230 if (!intel_pt_enable_logging || !f)
231 return;
232
233 perf_event__fprintf(event, f);
234}
235
236static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
237 struct auxtrace_buffer *b)
238{
239 bool consecutive = false;
240 void *start;
241
242 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
243 pt->have_tsc, &consecutive);
244 if (!start)
245 return -EINVAL;
246 b->use_size = b->data + b->size - start;
247 b->use_data = start;
248 if (b->use_size && consecutive)
249 b->consecutive = true;
250 return 0;
251}
252
253static int intel_pt_get_buffer(struct intel_pt_queue *ptq,
254 struct auxtrace_buffer *buffer,
255 struct auxtrace_buffer *old_buffer,
256 struct intel_pt_buffer *b)
257{
258 bool might_overlap;
259
260 if (!buffer->data) {
261 int fd = perf_data__fd(ptq->pt->session->data);
262
263 buffer->data = auxtrace_buffer__get_data(buffer, fd);
264 if (!buffer->data)
265 return -ENOMEM;
266 }
267
268 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
269 if (might_overlap && !buffer->consecutive && old_buffer &&
270 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
271 return -ENOMEM;
272
273 if (buffer->use_data) {
274 b->len = buffer->use_size;
275 b->buf = buffer->use_data;
276 } else {
277 b->len = buffer->size;
278 b->buf = buffer->data;
279 }
280 b->ref_timestamp = buffer->reference;
281
282 if (!old_buffer || (might_overlap && !buffer->consecutive)) {
283 b->consecutive = false;
284 b->trace_nr = buffer->buffer_nr + 1;
285 } else {
286 b->consecutive = true;
287 }
288
289 return 0;
290}
291
292/* Do not drop buffers with references - refer intel_pt_get_trace() */
293static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq,
294 struct auxtrace_buffer *buffer)
295{
296 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer)
297 return;
298
299 auxtrace_buffer__drop_data(buffer);
300}
301
302/* Must be serialized with respect to intel_pt_get_trace() */
303static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb,
304 void *cb_data)
305{
306 struct intel_pt_queue *ptq = data;
307 struct auxtrace_buffer *buffer = ptq->buffer;
308 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
309 struct auxtrace_queue *queue;
310 int err = 0;
311
312 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
313
314 while (1) {
315 struct intel_pt_buffer b = { .len = 0 };
316
317 buffer = auxtrace_buffer__next(queue, buffer);
318 if (!buffer)
319 break;
320
321 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b);
322 if (err)
323 break;
324
325 if (b.len) {
326 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
327 old_buffer = buffer;
328 } else {
329 intel_pt_lookahead_drop_buffer(ptq, buffer);
330 continue;
331 }
332
333 err = cb(&b, cb_data);
334 if (err)
335 break;
336 }
337
338 if (buffer != old_buffer)
339 intel_pt_lookahead_drop_buffer(ptq, buffer);
340 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
341
342 return err;
343}
344
345/*
346 * This function assumes data is processed sequentially only.
347 * Must be serialized with respect to intel_pt_lookahead()
348 */
349static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
350{
351 struct intel_pt_queue *ptq = data;
352 struct auxtrace_buffer *buffer = ptq->buffer;
353 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
354 struct auxtrace_queue *queue;
355 int err;
356
357 if (ptq->stop) {
358 b->len = 0;
359 return 0;
360 }
361
362 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
363
364 buffer = auxtrace_buffer__next(queue, buffer);
365 if (!buffer) {
366 if (old_buffer)
367 auxtrace_buffer__drop_data(old_buffer);
368 b->len = 0;
369 return 0;
370 }
371
372 ptq->buffer = buffer;
373
374 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b);
375 if (err)
376 return err;
377
378 if (ptq->step_through_buffers)
379 ptq->stop = true;
380
381 if (b->len) {
382 if (old_buffer)
383 auxtrace_buffer__drop_data(old_buffer);
384 ptq->old_buffer = buffer;
385 } else {
386 auxtrace_buffer__drop_data(buffer);
387 return intel_pt_get_trace(b, data);
388 }
389
390 return 0;
391}
392
393struct intel_pt_cache_entry {
394 struct auxtrace_cache_entry entry;
395 u64 insn_cnt;
396 u64 byte_cnt;
397 enum intel_pt_insn_op op;
398 enum intel_pt_insn_branch branch;
399 int length;
400 int32_t rel;
401 char insn[INTEL_PT_INSN_BUF_SZ];
402};
403
404static int intel_pt_config_div(const char *var, const char *value, void *data)
405{
406 int *d = data;
407 long val;
408
409 if (!strcmp(var, "intel-pt.cache-divisor")) {
410 val = strtol(value, NULL, 0);
411 if (val > 0 && val <= INT_MAX)
412 *d = val;
413 }
414
415 return 0;
416}
417
418static int intel_pt_cache_divisor(void)
419{
420 static int d;
421
422 if (d)
423 return d;
424
425 perf_config(intel_pt_config_div, &d);
426
427 if (!d)
428 d = 64;
429
430 return d;
431}
432
433static unsigned int intel_pt_cache_size(struct dso *dso,
434 struct machine *machine)
435{
436 off_t size;
437
438 size = dso__data_size(dso, machine);
439 size /= intel_pt_cache_divisor();
440 if (size < 1000)
441 return 10;
442 if (size > (1 << 21))
443 return 21;
444 return 32 - __builtin_clz(size);
445}
446
447static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
448 struct machine *machine)
449{
450 struct auxtrace_cache *c;
451 unsigned int bits;
452
453 if (dso->auxtrace_cache)
454 return dso->auxtrace_cache;
455
456 bits = intel_pt_cache_size(dso, machine);
457
458 /* Ignoring cache creation failure */
459 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
460
461 dso->auxtrace_cache = c;
462
463 return c;
464}
465
466static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
467 u64 offset, u64 insn_cnt, u64 byte_cnt,
468 struct intel_pt_insn *intel_pt_insn)
469{
470 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
471 struct intel_pt_cache_entry *e;
472 int err;
473
474 if (!c)
475 return -ENOMEM;
476
477 e = auxtrace_cache__alloc_entry(c);
478 if (!e)
479 return -ENOMEM;
480
481 e->insn_cnt = insn_cnt;
482 e->byte_cnt = byte_cnt;
483 e->op = intel_pt_insn->op;
484 e->branch = intel_pt_insn->branch;
485 e->length = intel_pt_insn->length;
486 e->rel = intel_pt_insn->rel;
487 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
488
489 err = auxtrace_cache__add(c, offset, &e->entry);
490 if (err)
491 auxtrace_cache__free_entry(c, e);
492
493 return err;
494}
495
496static struct intel_pt_cache_entry *
497intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
498{
499 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
500
501 if (!c)
502 return NULL;
503
504 return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
505}
506
507static inline u8 intel_pt_cpumode(struct intel_pt *pt, uint64_t ip)
508{
509 return ip >= pt->kernel_start ?
510 PERF_RECORD_MISC_KERNEL :
511 PERF_RECORD_MISC_USER;
512}
513
514static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
515 uint64_t *insn_cnt_ptr, uint64_t *ip,
516 uint64_t to_ip, uint64_t max_insn_cnt,
517 void *data)
518{
519 struct intel_pt_queue *ptq = data;
520 struct machine *machine = ptq->pt->machine;
521 struct thread *thread;
522 struct addr_location al;
523 unsigned char buf[INTEL_PT_INSN_BUF_SZ];
524 ssize_t len;
525 int x86_64;
526 u8 cpumode;
527 u64 offset, start_offset, start_ip;
528 u64 insn_cnt = 0;
529 bool one_map = true;
530
531 intel_pt_insn->length = 0;
532
533 if (to_ip && *ip == to_ip)
534 goto out_no_cache;
535
536 cpumode = intel_pt_cpumode(ptq->pt, *ip);
537
538 thread = ptq->thread;
539 if (!thread) {
540 if (cpumode != PERF_RECORD_MISC_KERNEL)
541 return -EINVAL;
542 thread = ptq->pt->unknown_thread;
543 }
544
545 while (1) {
546 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso)
547 return -EINVAL;
548
549 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
550 dso__data_status_seen(al.map->dso,
551 DSO_DATA_STATUS_SEEN_ITRACE))
552 return -ENOENT;
553
554 offset = al.map->map_ip(al.map, *ip);
555
556 if (!to_ip && one_map) {
557 struct intel_pt_cache_entry *e;
558
559 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
560 if (e &&
561 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
562 *insn_cnt_ptr = e->insn_cnt;
563 *ip += e->byte_cnt;
564 intel_pt_insn->op = e->op;
565 intel_pt_insn->branch = e->branch;
566 intel_pt_insn->length = e->length;
567 intel_pt_insn->rel = e->rel;
568 memcpy(intel_pt_insn->buf, e->insn,
569 INTEL_PT_INSN_BUF_SZ);
570 intel_pt_log_insn_no_data(intel_pt_insn, *ip);
571 return 0;
572 }
573 }
574
575 start_offset = offset;
576 start_ip = *ip;
577
578 /* Load maps to ensure dso->is_64_bit has been updated */
579 map__load(al.map);
580
581 x86_64 = al.map->dso->is_64_bit;
582
583 while (1) {
584 len = dso__data_read_offset(al.map->dso, machine,
585 offset, buf,
586 INTEL_PT_INSN_BUF_SZ);
587 if (len <= 0)
588 return -EINVAL;
589
590 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
591 return -EINVAL;
592
593 intel_pt_log_insn(intel_pt_insn, *ip);
594
595 insn_cnt += 1;
596
597 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH)
598 goto out;
599
600 if (max_insn_cnt && insn_cnt >= max_insn_cnt)
601 goto out_no_cache;
602
603 *ip += intel_pt_insn->length;
604
605 if (to_ip && *ip == to_ip)
606 goto out_no_cache;
607
608 if (*ip >= al.map->end)
609 break;
610
611 offset += intel_pt_insn->length;
612 }
613 one_map = false;
614 }
615out:
616 *insn_cnt_ptr = insn_cnt;
617
618 if (!one_map)
619 goto out_no_cache;
620
621 /*
622 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
623 * entries.
624 */
625 if (to_ip) {
626 struct intel_pt_cache_entry *e;
627
628 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
629 if (e)
630 return 0;
631 }
632
633 /* Ignore cache errors */
634 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
635 *ip - start_ip, intel_pt_insn);
636
637 return 0;
638
639out_no_cache:
640 *insn_cnt_ptr = insn_cnt;
641 return 0;
642}
643
644static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
645 uint64_t offset, const char *filename)
646{
647 struct addr_filter *filt;
648 bool have_filter = false;
649 bool hit_tracestop = false;
650 bool hit_filter = false;
651
652 list_for_each_entry(filt, &pt->filts.head, list) {
653 if (filt->start)
654 have_filter = true;
655
656 if ((filename && !filt->filename) ||
657 (!filename && filt->filename) ||
658 (filename && strcmp(filename, filt->filename)))
659 continue;
660
661 if (!(offset >= filt->addr && offset < filt->addr + filt->size))
662 continue;
663
664 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
665 ip, offset, filename ? filename : "[kernel]",
666 filt->start ? "filter" : "stop",
667 filt->addr, filt->size);
668
669 if (filt->start)
670 hit_filter = true;
671 else
672 hit_tracestop = true;
673 }
674
675 if (!hit_tracestop && !hit_filter)
676 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
677 ip, offset, filename ? filename : "[kernel]");
678
679 return hit_tracestop || (have_filter && !hit_filter);
680}
681
682static int __intel_pt_pgd_ip(uint64_t ip, void *data)
683{
684 struct intel_pt_queue *ptq = data;
685 struct thread *thread;
686 struct addr_location al;
687 u8 cpumode;
688 u64 offset;
689
690 if (ip >= ptq->pt->kernel_start)
691 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
692
693 cpumode = PERF_RECORD_MISC_USER;
694
695 thread = ptq->thread;
696 if (!thread)
697 return -EINVAL;
698
699 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
700 return -EINVAL;
701
702 offset = al.map->map_ip(al.map, ip);
703
704 return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
705 al.map->dso->long_name);
706}
707
708static bool intel_pt_pgd_ip(uint64_t ip, void *data)
709{
710 return __intel_pt_pgd_ip(ip, data) > 0;
711}
712
713static bool intel_pt_get_config(struct intel_pt *pt,
714 struct perf_event_attr *attr, u64 *config)
715{
716 if (attr->type == pt->pmu_type) {
717 if (config)
718 *config = attr->config;
719 return true;
720 }
721
722 return false;
723}
724
725static bool intel_pt_exclude_kernel(struct intel_pt *pt)
726{
727 struct evsel *evsel;
728
729 evlist__for_each_entry(pt->session->evlist, evsel) {
730 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
731 !evsel->core.attr.exclude_kernel)
732 return false;
733 }
734 return true;
735}
736
737static bool intel_pt_return_compression(struct intel_pt *pt)
738{
739 struct evsel *evsel;
740 u64 config;
741
742 if (!pt->noretcomp_bit)
743 return true;
744
745 evlist__for_each_entry(pt->session->evlist, evsel) {
746 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
747 (config & pt->noretcomp_bit))
748 return false;
749 }
750 return true;
751}
752
753static bool intel_pt_branch_enable(struct intel_pt *pt)
754{
755 struct evsel *evsel;
756 u64 config;
757
758 evlist__for_each_entry(pt->session->evlist, evsel) {
759 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
760 (config & 1) && !(config & 0x2000))
761 return false;
762 }
763 return true;
764}
765
766static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
767{
768 struct evsel *evsel;
769 unsigned int shift;
770 u64 config;
771
772 if (!pt->mtc_freq_bits)
773 return 0;
774
775 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
776 config >>= 1;
777
778 evlist__for_each_entry(pt->session->evlist, evsel) {
779 if (intel_pt_get_config(pt, &evsel->core.attr, &config))
780 return (config & pt->mtc_freq_bits) >> shift;
781 }
782 return 0;
783}
784
785static bool intel_pt_timeless_decoding(struct intel_pt *pt)
786{
787 struct evsel *evsel;
788 bool timeless_decoding = true;
789 u64 config;
790
791 if (!pt->tsc_bit || !pt->cap_user_time_zero)
792 return true;
793
794 evlist__for_each_entry(pt->session->evlist, evsel) {
795 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME))
796 return true;
797 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
798 if (config & pt->tsc_bit)
799 timeless_decoding = false;
800 else
801 return true;
802 }
803 }
804 return timeless_decoding;
805}
806
807static bool intel_pt_tracing_kernel(struct intel_pt *pt)
808{
809 struct evsel *evsel;
810
811 evlist__for_each_entry(pt->session->evlist, evsel) {
812 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
813 !evsel->core.attr.exclude_kernel)
814 return true;
815 }
816 return false;
817}
818
819static bool intel_pt_have_tsc(struct intel_pt *pt)
820{
821 struct evsel *evsel;
822 bool have_tsc = false;
823 u64 config;
824
825 if (!pt->tsc_bit)
826 return false;
827
828 evlist__for_each_entry(pt->session->evlist, evsel) {
829 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
830 if (config & pt->tsc_bit)
831 have_tsc = true;
832 else
833 return false;
834 }
835 }
836 return have_tsc;
837}
838
839static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
840{
841 u64 quot, rem;
842
843 quot = ns / pt->tc.time_mult;
844 rem = ns % pt->tc.time_mult;
845 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
846 pt->tc.time_mult;
847}
848
849static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
850 unsigned int queue_nr)
851{
852 struct intel_pt_params params = { .get_trace = 0, };
853 struct perf_env *env = pt->machine->env;
854 struct intel_pt_queue *ptq;
855
856 ptq = zalloc(sizeof(struct intel_pt_queue));
857 if (!ptq)
858 return NULL;
859
860 if (pt->synth_opts.callchain) {
861 size_t sz = sizeof(struct ip_callchain);
862
863 /* Add 1 to callchain_sz for callchain context */
864 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
865 ptq->chain = zalloc(sz);
866 if (!ptq->chain)
867 goto out_free;
868 }
869
870 if (pt->synth_opts.last_branch) {
871 size_t sz = sizeof(struct branch_stack);
872
873 sz += pt->synth_opts.last_branch_sz *
874 sizeof(struct branch_entry);
875 ptq->last_branch = zalloc(sz);
876 if (!ptq->last_branch)
877 goto out_free;
878 ptq->last_branch_rb = zalloc(sz);
879 if (!ptq->last_branch_rb)
880 goto out_free;
881 }
882
883 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
884 if (!ptq->event_buf)
885 goto out_free;
886
887 ptq->pt = pt;
888 ptq->queue_nr = queue_nr;
889 ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
890 ptq->pid = -1;
891 ptq->tid = -1;
892 ptq->cpu = -1;
893 ptq->next_tid = -1;
894
895 params.get_trace = intel_pt_get_trace;
896 params.walk_insn = intel_pt_walk_next_insn;
897 params.lookahead = intel_pt_lookahead;
898 params.data = ptq;
899 params.return_compression = intel_pt_return_compression(pt);
900 params.branch_enable = intel_pt_branch_enable(pt);
901 params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
902 params.mtc_period = intel_pt_mtc_period(pt);
903 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
904 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
905
906 if (pt->filts.cnt > 0)
907 params.pgd_ip = intel_pt_pgd_ip;
908
909 if (pt->synth_opts.instructions) {
910 if (pt->synth_opts.period) {
911 switch (pt->synth_opts.period_type) {
912 case PERF_ITRACE_PERIOD_INSTRUCTIONS:
913 params.period_type =
914 INTEL_PT_PERIOD_INSTRUCTIONS;
915 params.period = pt->synth_opts.period;
916 break;
917 case PERF_ITRACE_PERIOD_TICKS:
918 params.period_type = INTEL_PT_PERIOD_TICKS;
919 params.period = pt->synth_opts.period;
920 break;
921 case PERF_ITRACE_PERIOD_NANOSECS:
922 params.period_type = INTEL_PT_PERIOD_TICKS;
923 params.period = intel_pt_ns_to_ticks(pt,
924 pt->synth_opts.period);
925 break;
926 default:
927 break;
928 }
929 }
930
931 if (!params.period) {
932 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
933 params.period = 1;
934 }
935 }
936
937 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
938 params.flags |= INTEL_PT_FUP_WITH_NLIP;
939
940 ptq->decoder = intel_pt_decoder_new(¶ms);
941 if (!ptq->decoder)
942 goto out_free;
943
944 return ptq;
945
946out_free:
947 zfree(&ptq->event_buf);
948 zfree(&ptq->last_branch);
949 zfree(&ptq->last_branch_rb);
950 zfree(&ptq->chain);
951 free(ptq);
952 return NULL;
953}
954
955static void intel_pt_free_queue(void *priv)
956{
957 struct intel_pt_queue *ptq = priv;
958
959 if (!ptq)
960 return;
961 thread__zput(ptq->thread);
962 intel_pt_decoder_free(ptq->decoder);
963 zfree(&ptq->event_buf);
964 zfree(&ptq->last_branch);
965 zfree(&ptq->last_branch_rb);
966 zfree(&ptq->chain);
967 free(ptq);
968}
969
970static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
971 struct auxtrace_queue *queue)
972{
973 struct intel_pt_queue *ptq = queue->priv;
974
975 if (queue->tid == -1 || pt->have_sched_switch) {
976 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
977 thread__zput(ptq->thread);
978 }
979
980 if (!ptq->thread && ptq->tid != -1)
981 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
982
983 if (ptq->thread) {
984 ptq->pid = ptq->thread->pid_;
985 if (queue->cpu == -1)
986 ptq->cpu = ptq->thread->cpu;
987 }
988}
989
990static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
991{
992 if (ptq->state->flags & INTEL_PT_ABORT_TX) {
993 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
994 } else if (ptq->state->flags & INTEL_PT_ASYNC) {
995 if (ptq->state->to_ip)
996 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
997 PERF_IP_FLAG_ASYNC |
998 PERF_IP_FLAG_INTERRUPT;
999 else
1000 ptq->flags = PERF_IP_FLAG_BRANCH |
1001 PERF_IP_FLAG_TRACE_END;
1002 ptq->insn_len = 0;
1003 } else {
1004 if (ptq->state->from_ip)
1005 ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
1006 else
1007 ptq->flags = PERF_IP_FLAG_BRANCH |
1008 PERF_IP_FLAG_TRACE_BEGIN;
1009 if (ptq->state->flags & INTEL_PT_IN_TX)
1010 ptq->flags |= PERF_IP_FLAG_IN_TX;
1011 ptq->insn_len = ptq->state->insn_len;
1012 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
1013 }
1014
1015 if (ptq->state->type & INTEL_PT_TRACE_BEGIN)
1016 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN;
1017 if (ptq->state->type & INTEL_PT_TRACE_END)
1018 ptq->flags |= PERF_IP_FLAG_TRACE_END;
1019}
1020
1021static void intel_pt_setup_time_range(struct intel_pt *pt,
1022 struct intel_pt_queue *ptq)
1023{
1024 if (!pt->range_cnt)
1025 return;
1026
1027 ptq->sel_timestamp = pt->time_ranges[0].start;
1028 ptq->sel_idx = 0;
1029
1030 if (ptq->sel_timestamp) {
1031 ptq->sel_start = true;
1032 } else {
1033 ptq->sel_timestamp = pt->time_ranges[0].end;
1034 ptq->sel_start = false;
1035 }
1036}
1037
1038static int intel_pt_setup_queue(struct intel_pt *pt,
1039 struct auxtrace_queue *queue,
1040 unsigned int queue_nr)
1041{
1042 struct intel_pt_queue *ptq = queue->priv;
1043
1044 if (list_empty(&queue->head))
1045 return 0;
1046
1047 if (!ptq) {
1048 ptq = intel_pt_alloc_queue(pt, queue_nr);
1049 if (!ptq)
1050 return -ENOMEM;
1051 queue->priv = ptq;
1052
1053 if (queue->cpu != -1)
1054 ptq->cpu = queue->cpu;
1055 ptq->tid = queue->tid;
1056
1057 ptq->cbr_seen = UINT_MAX;
1058
1059 if (pt->sampling_mode && !pt->snapshot_mode &&
1060 pt->timeless_decoding)
1061 ptq->step_through_buffers = true;
1062
1063 ptq->sync_switch = pt->sync_switch;
1064
1065 intel_pt_setup_time_range(pt, ptq);
1066 }
1067
1068 if (!ptq->on_heap &&
1069 (!ptq->sync_switch ||
1070 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
1071 const struct intel_pt_state *state;
1072 int ret;
1073
1074 if (pt->timeless_decoding)
1075 return 0;
1076
1077 intel_pt_log("queue %u getting timestamp\n", queue_nr);
1078 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
1079 queue_nr, ptq->cpu, ptq->pid, ptq->tid);
1080
1081 if (ptq->sel_start && ptq->sel_timestamp) {
1082 ret = intel_pt_fast_forward(ptq->decoder,
1083 ptq->sel_timestamp);
1084 if (ret)
1085 return ret;
1086 }
1087
1088 while (1) {
1089 state = intel_pt_decode(ptq->decoder);
1090 if (state->err) {
1091 if (state->err == INTEL_PT_ERR_NODATA) {
1092 intel_pt_log("queue %u has no timestamp\n",
1093 queue_nr);
1094 return 0;
1095 }
1096 continue;
1097 }
1098 if (state->timestamp)
1099 break;
1100 }
1101
1102 ptq->timestamp = state->timestamp;
1103 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
1104 queue_nr, ptq->timestamp);
1105 ptq->state = state;
1106 ptq->have_sample = true;
1107 if (ptq->sel_start && ptq->sel_timestamp &&
1108 ptq->timestamp < ptq->sel_timestamp)
1109 ptq->have_sample = false;
1110 intel_pt_sample_flags(ptq);
1111 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
1112 if (ret)
1113 return ret;
1114 ptq->on_heap = true;
1115 }
1116
1117 return 0;
1118}
1119
1120static int intel_pt_setup_queues(struct intel_pt *pt)
1121{
1122 unsigned int i;
1123 int ret;
1124
1125 for (i = 0; i < pt->queues.nr_queues; i++) {
1126 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
1127 if (ret)
1128 return ret;
1129 }
1130 return 0;
1131}
1132
1133static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq)
1134{
1135 struct branch_stack *bs_src = ptq->last_branch_rb;
1136 struct branch_stack *bs_dst = ptq->last_branch;
1137 size_t nr = 0;
1138
1139 bs_dst->nr = bs_src->nr;
1140
1141 if (!bs_src->nr)
1142 return;
1143
1144 nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos;
1145 memcpy(&bs_dst->entries[0],
1146 &bs_src->entries[ptq->last_branch_pos],
1147 sizeof(struct branch_entry) * nr);
1148
1149 if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) {
1150 memcpy(&bs_dst->entries[nr],
1151 &bs_src->entries[0],
1152 sizeof(struct branch_entry) * ptq->last_branch_pos);
1153 }
1154}
1155
1156static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq)
1157{
1158 ptq->last_branch_pos = 0;
1159 ptq->last_branch_rb->nr = 0;
1160}
1161
1162static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq)
1163{
1164 const struct intel_pt_state *state = ptq->state;
1165 struct branch_stack *bs = ptq->last_branch_rb;
1166 struct branch_entry *be;
1167
1168 if (!ptq->last_branch_pos)
1169 ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz;
1170
1171 ptq->last_branch_pos -= 1;
1172
1173 be = &bs->entries[ptq->last_branch_pos];
1174 be->from = state->from_ip;
1175 be->to = state->to_ip;
1176 be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX);
1177 be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX);
1178 /* No support for mispredict */
1179 be->flags.mispred = ptq->pt->mispred_all;
1180
1181 if (bs->nr < ptq->pt->synth_opts.last_branch_sz)
1182 bs->nr += 1;
1183}
1184
1185static inline bool intel_pt_skip_event(struct intel_pt *pt)
1186{
1187 return pt->synth_opts.initial_skip &&
1188 pt->num_events++ < pt->synth_opts.initial_skip;
1189}
1190
1191/*
1192 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen.
1193 * Also ensure CBR is first non-skipped event by allowing for 4 more samples
1194 * from this decoder state.
1195 */
1196static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt)
1197{
1198 return pt->synth_opts.initial_skip &&
1199 pt->num_events + 4 < pt->synth_opts.initial_skip;
1200}
1201
1202static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq,
1203 union perf_event *event,
1204 struct perf_sample *sample)
1205{
1206 event->sample.header.type = PERF_RECORD_SAMPLE;
1207 event->sample.header.size = sizeof(struct perf_event_header);
1208
1209 sample->pid = ptq->pid;
1210 sample->tid = ptq->tid;
1211 sample->cpu = ptq->cpu;
1212 sample->insn_len = ptq->insn_len;
1213 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
1214}
1215
1216static void intel_pt_prep_b_sample(struct intel_pt *pt,
1217 struct intel_pt_queue *ptq,
1218 union perf_event *event,
1219 struct perf_sample *sample)
1220{
1221 intel_pt_prep_a_sample(ptq, event, sample);
1222
1223 if (!pt->timeless_decoding)
1224 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
1225
1226 sample->ip = ptq->state->from_ip;
1227 sample->cpumode = intel_pt_cpumode(pt, sample->ip);
1228 sample->addr = ptq->state->to_ip;
1229 sample->period = 1;
1230 sample->flags = ptq->flags;
1231
1232 event->sample.header.misc = sample->cpumode;
1233}
1234
1235static int intel_pt_inject_event(union perf_event *event,
1236 struct perf_sample *sample, u64 type)
1237{
1238 event->header.size = perf_event__sample_event_size(sample, type, 0);
1239 return perf_event__synthesize_sample(event, type, 0, sample);
1240}
1241
1242static inline int intel_pt_opt_inject(struct intel_pt *pt,
1243 union perf_event *event,
1244 struct perf_sample *sample, u64 type)
1245{
1246 if (!pt->synth_opts.inject)
1247 return 0;
1248
1249 return intel_pt_inject_event(event, sample, type);
1250}
1251
1252static int intel_pt_deliver_synth_b_event(struct intel_pt *pt,
1253 union perf_event *event,
1254 struct perf_sample *sample, u64 type)
1255{
1256 int ret;
1257
1258 ret = intel_pt_opt_inject(pt, event, sample, type);
1259 if (ret)
1260 return ret;
1261
1262 ret = perf_session__deliver_synth_event(pt->session, event, sample);
1263 if (ret)
1264 pr_err("Intel PT: failed to deliver event, error %d\n", ret);
1265
1266 return ret;
1267}
1268
1269static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
1270{
1271 struct intel_pt *pt = ptq->pt;
1272 union perf_event *event = ptq->event_buf;
1273 struct perf_sample sample = { .ip = 0, };
1274 struct dummy_branch_stack {
1275 u64 nr;
1276 struct branch_entry entries;
1277 } dummy_bs;
1278
1279 if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
1280 return 0;
1281
1282 if (intel_pt_skip_event(pt))
1283 return 0;
1284
1285 intel_pt_prep_b_sample(pt, ptq, event, &sample);
1286
1287 sample.id = ptq->pt->branches_id;
1288 sample.stream_id = ptq->pt->branches_id;
1289
1290 /*
1291 * perf report cannot handle events without a branch stack when using
1292 * SORT_MODE__BRANCH so make a dummy one.
1293 */
1294 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
1295 dummy_bs = (struct dummy_branch_stack){
1296 .nr = 1,
1297 .entries = {
1298 .from = sample.ip,
1299 .to = sample.addr,
1300 },
1301 };
1302 sample.branch_stack = (struct branch_stack *)&dummy_bs;
1303 }
1304
1305 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt;
1306 if (sample.cyc_cnt) {
1307 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt;
1308 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt;
1309 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt;
1310 }
1311
1312 return intel_pt_deliver_synth_b_event(pt, event, &sample,
1313 pt->branches_sample_type);
1314}
1315
1316static void intel_pt_prep_sample(struct intel_pt *pt,
1317 struct intel_pt_queue *ptq,
1318 union perf_event *event,
1319 struct perf_sample *sample)
1320{
1321 intel_pt_prep_b_sample(pt, ptq, event, sample);
1322
1323 if (pt->synth_opts.callchain) {
1324 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1325 pt->synth_opts.callchain_sz + 1,
1326 sample->ip, pt->kernel_start);
1327 sample->callchain = ptq->chain;
1328 }
1329
1330 if (pt->synth_opts.last_branch) {
1331 intel_pt_copy_last_branch_rb(ptq);
1332 sample->branch_stack = ptq->last_branch;
1333 }
1334}
1335
1336static inline int intel_pt_deliver_synth_event(struct intel_pt *pt,
1337 struct intel_pt_queue *ptq,
1338 union perf_event *event,
1339 struct perf_sample *sample,
1340 u64 type)
1341{
1342 int ret;
1343
1344 ret = intel_pt_deliver_synth_b_event(pt, event, sample, type);
1345
1346 if (pt->synth_opts.last_branch)
1347 intel_pt_reset_last_branch_rb(ptq);
1348
1349 return ret;
1350}
1351
1352static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
1353{
1354 struct intel_pt *pt = ptq->pt;
1355 union perf_event *event = ptq->event_buf;
1356 struct perf_sample sample = { .ip = 0, };
1357
1358 if (intel_pt_skip_event(pt))
1359 return 0;
1360
1361 intel_pt_prep_sample(pt, ptq, event, &sample);
1362
1363 sample.id = ptq->pt->instructions_id;
1364 sample.stream_id = ptq->pt->instructions_id;
1365 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
1366
1367 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt;
1368 if (sample.cyc_cnt) {
1369 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt;
1370 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt;
1371 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt;
1372 }
1373
1374 ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
1375
1376 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1377 pt->instructions_sample_type);
1378}
1379
1380static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
1381{
1382 struct intel_pt *pt = ptq->pt;
1383 union perf_event *event = ptq->event_buf;
1384 struct perf_sample sample = { .ip = 0, };
1385
1386 if (intel_pt_skip_event(pt))
1387 return 0;
1388
1389 intel_pt_prep_sample(pt, ptq, event, &sample);
1390
1391 sample.id = ptq->pt->transactions_id;
1392 sample.stream_id = ptq->pt->transactions_id;
1393
1394 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1395 pt->transactions_sample_type);
1396}
1397
1398static void intel_pt_prep_p_sample(struct intel_pt *pt,
1399 struct intel_pt_queue *ptq,
1400 union perf_event *event,
1401 struct perf_sample *sample)
1402{
1403 intel_pt_prep_sample(pt, ptq, event, sample);
1404
1405 /*
1406 * Zero IP is used to mean "trace start" but that is not the case for
1407 * power or PTWRITE events with no IP, so clear the flags.
1408 */
1409 if (!sample->ip)
1410 sample->flags = 0;
1411}
1412
1413static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
1414{
1415 struct intel_pt *pt = ptq->pt;
1416 union perf_event *event = ptq->event_buf;
1417 struct perf_sample sample = { .ip = 0, };
1418 struct perf_synth_intel_ptwrite raw;
1419
1420 if (intel_pt_skip_event(pt))
1421 return 0;
1422
1423 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1424
1425 sample.id = ptq->pt->ptwrites_id;
1426 sample.stream_id = ptq->pt->ptwrites_id;
1427
1428 raw.flags = 0;
1429 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1430 raw.payload = cpu_to_le64(ptq->state->ptw_payload);
1431
1432 sample.raw_size = perf_synth__raw_size(raw);
1433 sample.raw_data = perf_synth__raw_data(&raw);
1434
1435 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1436 pt->ptwrites_sample_type);
1437}
1438
1439static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
1440{
1441 struct intel_pt *pt = ptq->pt;
1442 union perf_event *event = ptq->event_buf;
1443 struct perf_sample sample = { .ip = 0, };
1444 struct perf_synth_intel_cbr raw;
1445 u32 flags;
1446
1447 if (intel_pt_skip_cbr_event(pt))
1448 return 0;
1449
1450 ptq->cbr_seen = ptq->state->cbr;
1451
1452 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1453
1454 sample.id = ptq->pt->cbr_id;
1455 sample.stream_id = ptq->pt->cbr_id;
1456
1457 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
1458 raw.flags = cpu_to_le32(flags);
1459 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
1460 raw.reserved3 = 0;
1461
1462 sample.raw_size = perf_synth__raw_size(raw);
1463 sample.raw_data = perf_synth__raw_data(&raw);
1464
1465 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1466 pt->pwr_events_sample_type);
1467}
1468
1469static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
1470{
1471 struct intel_pt *pt = ptq->pt;
1472 union perf_event *event = ptq->event_buf;
1473 struct perf_sample sample = { .ip = 0, };
1474 struct perf_synth_intel_mwait raw;
1475
1476 if (intel_pt_skip_event(pt))
1477 return 0;
1478
1479 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1480
1481 sample.id = ptq->pt->mwait_id;
1482 sample.stream_id = ptq->pt->mwait_id;
1483
1484 raw.reserved = 0;
1485 raw.payload = cpu_to_le64(ptq->state->mwait_payload);
1486
1487 sample.raw_size = perf_synth__raw_size(raw);
1488 sample.raw_data = perf_synth__raw_data(&raw);
1489
1490 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1491 pt->pwr_events_sample_type);
1492}
1493
1494static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
1495{
1496 struct intel_pt *pt = ptq->pt;
1497 union perf_event *event = ptq->event_buf;
1498 struct perf_sample sample = { .ip = 0, };
1499 struct perf_synth_intel_pwre raw;
1500
1501 if (intel_pt_skip_event(pt))
1502 return 0;
1503
1504 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1505
1506 sample.id = ptq->pt->pwre_id;
1507 sample.stream_id = ptq->pt->pwre_id;
1508
1509 raw.reserved = 0;
1510 raw.payload = cpu_to_le64(ptq->state->pwre_payload);
1511
1512 sample.raw_size = perf_synth__raw_size(raw);
1513 sample.raw_data = perf_synth__raw_data(&raw);
1514
1515 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1516 pt->pwr_events_sample_type);
1517}
1518
1519static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
1520{
1521 struct intel_pt *pt = ptq->pt;
1522 union perf_event *event = ptq->event_buf;
1523 struct perf_sample sample = { .ip = 0, };
1524 struct perf_synth_intel_exstop raw;
1525
1526 if (intel_pt_skip_event(pt))
1527 return 0;
1528
1529 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1530
1531 sample.id = ptq->pt->exstop_id;
1532 sample.stream_id = ptq->pt->exstop_id;
1533
1534 raw.flags = 0;
1535 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1536
1537 sample.raw_size = perf_synth__raw_size(raw);
1538 sample.raw_data = perf_synth__raw_data(&raw);
1539
1540 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1541 pt->pwr_events_sample_type);
1542}
1543
1544static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
1545{
1546 struct intel_pt *pt = ptq->pt;
1547 union perf_event *event = ptq->event_buf;
1548 struct perf_sample sample = { .ip = 0, };
1549 struct perf_synth_intel_pwrx raw;
1550
1551 if (intel_pt_skip_event(pt))
1552 return 0;
1553
1554 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1555
1556 sample.id = ptq->pt->pwrx_id;
1557 sample.stream_id = ptq->pt->pwrx_id;
1558
1559 raw.reserved = 0;
1560 raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
1561
1562 sample.raw_size = perf_synth__raw_size(raw);
1563 sample.raw_data = perf_synth__raw_data(&raw);
1564
1565 return intel_pt_deliver_synth_event(pt, ptq, event, &sample,
1566 pt->pwr_events_sample_type);
1567}
1568
1569/*
1570 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer
1571 * intel_pt_add_gp_regs().
1572 */
1573static const int pebs_gp_regs[] = {
1574 [PERF_REG_X86_FLAGS] = 1,
1575 [PERF_REG_X86_IP] = 2,
1576 [PERF_REG_X86_AX] = 3,
1577 [PERF_REG_X86_CX] = 4,
1578 [PERF_REG_X86_DX] = 5,
1579 [PERF_REG_X86_BX] = 6,
1580 [PERF_REG_X86_SP] = 7,
1581 [PERF_REG_X86_BP] = 8,
1582 [PERF_REG_X86_SI] = 9,
1583 [PERF_REG_X86_DI] = 10,
1584 [PERF_REG_X86_R8] = 11,
1585 [PERF_REG_X86_R9] = 12,
1586 [PERF_REG_X86_R10] = 13,
1587 [PERF_REG_X86_R11] = 14,
1588 [PERF_REG_X86_R12] = 15,
1589 [PERF_REG_X86_R13] = 16,
1590 [PERF_REG_X86_R14] = 17,
1591 [PERF_REG_X86_R15] = 18,
1592};
1593
1594static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
1595 const struct intel_pt_blk_items *items,
1596 u64 regs_mask)
1597{
1598 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
1599 u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
1600 u32 bit;
1601 int i;
1602
1603 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
1604 /* Get the PEBS gp_regs array index */
1605 int n = pebs_gp_regs[i] - 1;
1606
1607 if (n < 0)
1608 continue;
1609 /*
1610 * Add only registers that were requested (i.e. 'regs_mask') and
1611 * that were provided (i.e. 'mask'), and update the resulting
1612 * mask (i.e. 'intr_regs->mask') accordingly.
1613 */
1614 if (mask & 1 << n && regs_mask & bit) {
1615 intr_regs->mask |= bit;
1616 *pos++ = gp_regs[n];
1617 }
1618 }
1619
1620 return pos;
1621}
1622
1623#ifndef PERF_REG_X86_XMM0
1624#define PERF_REG_X86_XMM0 32
1625#endif
1626
1627static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos,
1628 const struct intel_pt_blk_items *items,
1629 u64 regs_mask)
1630{
1631 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0);
1632 const u64 *xmm = items->xmm;
1633
1634 /*
1635 * If there are any XMM registers, then there should be all of them.
1636 * Nevertheless, follow the logic to add only registers that were
1637 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'),
1638 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly.
1639 */
1640 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0;
1641
1642 for (; mask; mask >>= 1, xmm++) {
1643 if (mask & 1)
1644 *pos++ = *xmm;
1645 }
1646}
1647
1648#define LBR_INFO_MISPRED (1ULL << 63)
1649#define LBR_INFO_IN_TX (1ULL << 62)
1650#define LBR_INFO_ABORT (1ULL << 61)
1651#define LBR_INFO_CYCLES 0xffff
1652
1653/* Refer kernel's intel_pmu_store_pebs_lbrs() */
1654static u64 intel_pt_lbr_flags(u64 info)
1655{
1656 union {
1657 struct branch_flags flags;
1658 u64 result;
1659 } u = {
1660 .flags = {
1661 .mispred = !!(info & LBR_INFO_MISPRED),
1662 .predicted = !(info & LBR_INFO_MISPRED),
1663 .in_tx = !!(info & LBR_INFO_IN_TX),
1664 .abort = !!(info & LBR_INFO_ABORT),
1665 .cycles = info & LBR_INFO_CYCLES,
1666 }
1667 };
1668
1669 return u.result;
1670}
1671
1672static void intel_pt_add_lbrs(struct branch_stack *br_stack,
1673 const struct intel_pt_blk_items *items)
1674{
1675 u64 *to;
1676 int i;
1677
1678 br_stack->nr = 0;
1679
1680 to = &br_stack->entries[0].from;
1681
1682 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) {
1683 u32 mask = items->mask[i];
1684 const u64 *from = items->val[i];
1685
1686 for (; mask; mask >>= 3, from += 3) {
1687 if ((mask & 7) == 7) {
1688 *to++ = from[0];
1689 *to++ = from[1];
1690 *to++ = intel_pt_lbr_flags(from[2]);
1691 br_stack->nr += 1;
1692 }
1693 }
1694 }
1695}
1696
1697/* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */
1698#define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3)
1699
1700static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
1701{
1702 const struct intel_pt_blk_items *items = &ptq->state->items;
1703 struct perf_sample sample = { .ip = 0, };
1704 union perf_event *event = ptq->event_buf;
1705 struct intel_pt *pt = ptq->pt;
1706 struct evsel *evsel = pt->pebs_evsel;
1707 u64 sample_type = evsel->core.attr.sample_type;
1708 u64 id = evsel->core.id[0];
1709 u8 cpumode;
1710
1711 if (intel_pt_skip_event(pt))
1712 return 0;
1713
1714 intel_pt_prep_a_sample(ptq, event, &sample);
1715
1716 sample.id = id;
1717 sample.stream_id = id;
1718
1719 if (!evsel->core.attr.freq)
1720 sample.period = evsel->core.attr.sample_period;
1721
1722 /* No support for non-zero CS base */
1723 if (items->has_ip)
1724 sample.ip = items->ip;
1725 else if (items->has_rip)
1726 sample.ip = items->rip;
1727 else
1728 sample.ip = ptq->state->from_ip;
1729
1730 /* No support for guest mode at this time */
1731 cpumode = sample.ip < ptq->pt->kernel_start ?
1732 PERF_RECORD_MISC_USER :
1733 PERF_RECORD_MISC_KERNEL;
1734
1735 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP;
1736
1737 sample.cpumode = cpumode;
1738
1739 if (sample_type & PERF_SAMPLE_TIME) {
1740 u64 timestamp = 0;
1741
1742 if (items->has_timestamp)
1743 timestamp = items->timestamp;
1744 else if (!pt->timeless_decoding)
1745 timestamp = ptq->timestamp;
1746 if (timestamp)
1747 sample.time = tsc_to_perf_time(timestamp, &pt->tc);
1748 }
1749
1750 if (sample_type & PERF_SAMPLE_CALLCHAIN &&
1751 pt->synth_opts.callchain) {
1752 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1753 pt->synth_opts.callchain_sz, sample.ip,
1754 pt->kernel_start);
1755 sample.callchain = ptq->chain;
1756 }
1757
1758 if (sample_type & PERF_SAMPLE_REGS_INTR &&
1759 items->mask[INTEL_PT_GP_REGS_POS]) {
1760 u64 regs[sizeof(sample.intr_regs.mask)];
1761 u64 regs_mask = evsel->core.attr.sample_regs_intr;
1762 u64 *pos;
1763
1764 sample.intr_regs.abi = items->is_32_bit ?
1765 PERF_SAMPLE_REGS_ABI_32 :
1766 PERF_SAMPLE_REGS_ABI_64;
1767 sample.intr_regs.regs = regs;
1768
1769 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
1770
1771 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask);
1772 }
1773
1774 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1775 struct {
1776 struct branch_stack br_stack;
1777 struct branch_entry entries[LBRS_MAX];
1778 } br;
1779
1780 if (items->mask[INTEL_PT_LBR_0_POS] ||
1781 items->mask[INTEL_PT_LBR_1_POS] ||
1782 items->mask[INTEL_PT_LBR_2_POS]) {
1783 intel_pt_add_lbrs(&br.br_stack, items);
1784 sample.branch_stack = &br.br_stack;
1785 } else if (pt->synth_opts.last_branch) {
1786 intel_pt_copy_last_branch_rb(ptq);
1787 sample.branch_stack = ptq->last_branch;
1788 } else {
1789 br.br_stack.nr = 0;
1790 sample.branch_stack = &br.br_stack;
1791 }
1792 }
1793
1794 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address)
1795 sample.addr = items->mem_access_address;
1796
1797 if (sample_type & PERF_SAMPLE_WEIGHT) {
1798 /*
1799 * Refer kernel's setup_pebs_adaptive_sample_data() and
1800 * intel_hsw_weight().
1801 */
1802 if (items->has_mem_access_latency)
1803 sample.weight = items->mem_access_latency;
1804 if (!sample.weight && items->has_tsx_aux_info) {
1805 /* Cycles last block */
1806 sample.weight = (u32)items->tsx_aux_info;
1807 }
1808 }
1809
1810 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) {
1811 u64 ax = items->has_rax ? items->rax : 0;
1812 /* Refer kernel's intel_hsw_transaction() */
1813 u64 txn = (u8)(items->tsx_aux_info >> 32);
1814
1815 /* For RTM XABORTs also log the abort code from AX */
1816 if (txn & PERF_TXN_TRANSACTION && ax & 1)
1817 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1818 sample.transaction = txn;
1819 }
1820
1821 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, sample_type);
1822}
1823
1824static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
1825 pid_t pid, pid_t tid, u64 ip, u64 timestamp)
1826{
1827 union perf_event event;
1828 char msg[MAX_AUXTRACE_ERROR_MSG];
1829 int err;
1830
1831 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
1832
1833 auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
1834 code, cpu, pid, tid, ip, msg, timestamp);
1835
1836 err = perf_session__deliver_synth_event(pt->session, &event, NULL);
1837 if (err)
1838 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
1839 err);
1840
1841 return err;
1842}
1843
1844static int intel_ptq_synth_error(struct intel_pt_queue *ptq,
1845 const struct intel_pt_state *state)
1846{
1847 struct intel_pt *pt = ptq->pt;
1848 u64 tm = ptq->timestamp;
1849
1850 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc);
1851
1852 return intel_pt_synth_error(pt, state->err, ptq->cpu, ptq->pid,
1853 ptq->tid, state->from_ip, tm);
1854}
1855
1856static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
1857{
1858 struct auxtrace_queue *queue;
1859 pid_t tid = ptq->next_tid;
1860 int err;
1861
1862 if (tid == -1)
1863 return 0;
1864
1865 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
1866
1867 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
1868
1869 queue = &pt->queues.queue_array[ptq->queue_nr];
1870 intel_pt_set_pid_tid_cpu(pt, queue);
1871
1872 ptq->next_tid = -1;
1873
1874 return err;
1875}
1876
1877static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
1878{
1879 struct intel_pt *pt = ptq->pt;
1880
1881 return ip == pt->switch_ip &&
1882 (ptq->flags & PERF_IP_FLAG_BRANCH) &&
1883 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
1884 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
1885}
1886
1887#define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
1888 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT)
1889
1890static int intel_pt_sample(struct intel_pt_queue *ptq)
1891{
1892 const struct intel_pt_state *state = ptq->state;
1893 struct intel_pt *pt = ptq->pt;
1894 int err;
1895
1896 if (!ptq->have_sample)
1897 return 0;
1898
1899 ptq->have_sample = false;
1900
1901 if (ptq->state->tot_cyc_cnt > ptq->ipc_cyc_cnt) {
1902 /*
1903 * Cycle count and instruction count only go together to create
1904 * a valid IPC ratio when the cycle count changes.
1905 */
1906 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt;
1907 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt;
1908 }
1909
1910 /*
1911 * Do PEBS first to allow for the possibility that the PEBS timestamp
1912 * precedes the current timestamp.
1913 */
1914 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) {
1915 err = intel_pt_synth_pebs_sample(ptq);
1916 if (err)
1917 return err;
1918 }
1919
1920 if (pt->sample_pwr_events) {
1921 if (ptq->state->cbr != ptq->cbr_seen) {
1922 err = intel_pt_synth_cbr_sample(ptq);
1923 if (err)
1924 return err;
1925 }
1926 if (state->type & INTEL_PT_PWR_EVT) {
1927 if (state->type & INTEL_PT_MWAIT_OP) {
1928 err = intel_pt_synth_mwait_sample(ptq);
1929 if (err)
1930 return err;
1931 }
1932 if (state->type & INTEL_PT_PWR_ENTRY) {
1933 err = intel_pt_synth_pwre_sample(ptq);
1934 if (err)
1935 return err;
1936 }
1937 if (state->type & INTEL_PT_EX_STOP) {
1938 err = intel_pt_synth_exstop_sample(ptq);
1939 if (err)
1940 return err;
1941 }
1942 if (state->type & INTEL_PT_PWR_EXIT) {
1943 err = intel_pt_synth_pwrx_sample(ptq);
1944 if (err)
1945 return err;
1946 }
1947 }
1948 }
1949
1950 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
1951 err = intel_pt_synth_instruction_sample(ptq);
1952 if (err)
1953 return err;
1954 }
1955
1956 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
1957 err = intel_pt_synth_transaction_sample(ptq);
1958 if (err)
1959 return err;
1960 }
1961
1962 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
1963 err = intel_pt_synth_ptwrite_sample(ptq);
1964 if (err)
1965 return err;
1966 }
1967
1968 if (!(state->type & INTEL_PT_BRANCH))
1969 return 0;
1970
1971 if (pt->synth_opts.callchain || pt->synth_opts.thread_stack)
1972 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags, state->from_ip,
1973 state->to_ip, ptq->insn_len,
1974 state->trace_nr);
1975 else
1976 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr);
1977
1978 if (pt->sample_branches) {
1979 err = intel_pt_synth_branch_sample(ptq);
1980 if (err)
1981 return err;
1982 }
1983
1984 if (pt->synth_opts.last_branch)
1985 intel_pt_update_last_branch_rb(ptq);
1986
1987 if (!ptq->sync_switch)
1988 return 0;
1989
1990 if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
1991 switch (ptq->switch_state) {
1992 case INTEL_PT_SS_NOT_TRACING:
1993 case INTEL_PT_SS_UNKNOWN:
1994 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
1995 err = intel_pt_next_tid(pt, ptq);
1996 if (err)
1997 return err;
1998 ptq->switch_state = INTEL_PT_SS_TRACING;
1999 break;
2000 default:
2001 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
2002 return 1;
2003 }
2004 } else if (!state->to_ip) {
2005 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2006 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
2007 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2008 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2009 state->to_ip == pt->ptss_ip &&
2010 (ptq->flags & PERF_IP_FLAG_CALL)) {
2011 ptq->switch_state = INTEL_PT_SS_TRACING;
2012 }
2013
2014 return 0;
2015}
2016
2017static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
2018{
2019 struct machine *machine = pt->machine;
2020 struct map *map;
2021 struct symbol *sym, *start;
2022 u64 ip, switch_ip = 0;
2023 const char *ptss;
2024
2025 if (ptss_ip)
2026 *ptss_ip = 0;
2027
2028 map = machine__kernel_map(machine);
2029 if (!map)
2030 return 0;
2031
2032 if (map__load(map))
2033 return 0;
2034
2035 start = dso__first_symbol(map->dso);
2036
2037 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2038 if (sym->binding == STB_GLOBAL &&
2039 !strcmp(sym->name, "__switch_to")) {
2040 ip = map->unmap_ip(map, sym->start);
2041 if (ip >= map->start && ip < map->end) {
2042 switch_ip = ip;
2043 break;
2044 }
2045 }
2046 }
2047
2048 if (!switch_ip || !ptss_ip)
2049 return 0;
2050
2051 if (pt->have_sched_switch == 1)
2052 ptss = "perf_trace_sched_switch";
2053 else
2054 ptss = "__perf_event_task_sched_out";
2055
2056 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2057 if (!strcmp(sym->name, ptss)) {
2058 ip = map->unmap_ip(map, sym->start);
2059 if (ip >= map->start && ip < map->end) {
2060 *ptss_ip = ip;
2061 break;
2062 }
2063 }
2064 }
2065
2066 return switch_ip;
2067}
2068
2069static void intel_pt_enable_sync_switch(struct intel_pt *pt)
2070{
2071 unsigned int i;
2072
2073 pt->sync_switch = true;
2074
2075 for (i = 0; i < pt->queues.nr_queues; i++) {
2076 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2077 struct intel_pt_queue *ptq = queue->priv;
2078
2079 if (ptq)
2080 ptq->sync_switch = true;
2081 }
2082}
2083
2084/*
2085 * To filter against time ranges, it is only necessary to look at the next start
2086 * or end time.
2087 */
2088static bool intel_pt_next_time(struct intel_pt_queue *ptq)
2089{
2090 struct intel_pt *pt = ptq->pt;
2091
2092 if (ptq->sel_start) {
2093 /* Next time is an end time */
2094 ptq->sel_start = false;
2095 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end;
2096 return true;
2097 } else if (ptq->sel_idx + 1 < pt->range_cnt) {
2098 /* Next time is a start time */
2099 ptq->sel_start = true;
2100 ptq->sel_idx += 1;
2101 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start;
2102 return true;
2103 }
2104
2105 /* No next time */
2106 return false;
2107}
2108
2109static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp)
2110{
2111 int err;
2112
2113 while (1) {
2114 if (ptq->sel_start) {
2115 if (ptq->timestamp >= ptq->sel_timestamp) {
2116 /* After start time, so consider next time */
2117 intel_pt_next_time(ptq);
2118 if (!ptq->sel_timestamp) {
2119 /* No end time */
2120 return 0;
2121 }
2122 /* Check against end time */
2123 continue;
2124 }
2125 /* Before start time, so fast forward */
2126 ptq->have_sample = false;
2127 if (ptq->sel_timestamp > *ff_timestamp) {
2128 if (ptq->sync_switch) {
2129 intel_pt_next_tid(ptq->pt, ptq);
2130 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2131 }
2132 *ff_timestamp = ptq->sel_timestamp;
2133 err = intel_pt_fast_forward(ptq->decoder,
2134 ptq->sel_timestamp);
2135 if (err)
2136 return err;
2137 }
2138 return 0;
2139 } else if (ptq->timestamp > ptq->sel_timestamp) {
2140 /* After end time, so consider next time */
2141 if (!intel_pt_next_time(ptq)) {
2142 /* No next time range, so stop decoding */
2143 ptq->have_sample = false;
2144 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2145 return 1;
2146 }
2147 /* Check against next start time */
2148 continue;
2149 } else {
2150 /* Before end time */
2151 return 0;
2152 }
2153 }
2154}
2155
2156static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
2157{
2158 const struct intel_pt_state *state = ptq->state;
2159 struct intel_pt *pt = ptq->pt;
2160 u64 ff_timestamp = 0;
2161 int err;
2162
2163 if (!pt->kernel_start) {
2164 pt->kernel_start = machine__kernel_start(pt->machine);
2165 if (pt->per_cpu_mmaps &&
2166 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
2167 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
2168 !pt->sampling_mode) {
2169 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
2170 if (pt->switch_ip) {
2171 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
2172 pt->switch_ip, pt->ptss_ip);
2173 intel_pt_enable_sync_switch(pt);
2174 }
2175 }
2176 }
2177
2178 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
2179 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
2180 while (1) {
2181 err = intel_pt_sample(ptq);
2182 if (err)
2183 return err;
2184
2185 state = intel_pt_decode(ptq->decoder);
2186 if (state->err) {
2187 if (state->err == INTEL_PT_ERR_NODATA)
2188 return 1;
2189 if (ptq->sync_switch &&
2190 state->from_ip >= pt->kernel_start) {
2191 ptq->sync_switch = false;
2192 intel_pt_next_tid(pt, ptq);
2193 }
2194 if (pt->synth_opts.errors) {
2195 err = intel_ptq_synth_error(ptq, state);
2196 if (err)
2197 return err;
2198 }
2199 continue;
2200 }
2201
2202 ptq->state = state;
2203 ptq->have_sample = true;
2204 intel_pt_sample_flags(ptq);
2205
2206 /* Use estimated TSC upon return to user space */
2207 if (pt->est_tsc &&
2208 (state->from_ip >= pt->kernel_start || !state->from_ip) &&
2209 state->to_ip && state->to_ip < pt->kernel_start) {
2210 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2211 state->timestamp, state->est_timestamp);
2212 ptq->timestamp = state->est_timestamp;
2213 /* Use estimated TSC in unknown switch state */
2214 } else if (ptq->sync_switch &&
2215 ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2216 intel_pt_is_switch_ip(ptq, state->to_ip) &&
2217 ptq->next_tid == -1) {
2218 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2219 state->timestamp, state->est_timestamp);
2220 ptq->timestamp = state->est_timestamp;
2221 } else if (state->timestamp > ptq->timestamp) {
2222 ptq->timestamp = state->timestamp;
2223 }
2224
2225 if (ptq->sel_timestamp) {
2226 err = intel_pt_time_filter(ptq, &ff_timestamp);
2227 if (err)
2228 return err;
2229 }
2230
2231 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
2232 *timestamp = ptq->timestamp;
2233 return 0;
2234 }
2235 }
2236 return 0;
2237}
2238
2239static inline int intel_pt_update_queues(struct intel_pt *pt)
2240{
2241 if (pt->queues.new_data) {
2242 pt->queues.new_data = false;
2243 return intel_pt_setup_queues(pt);
2244 }
2245 return 0;
2246}
2247
2248static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
2249{
2250 unsigned int queue_nr;
2251 u64 ts;
2252 int ret;
2253
2254 while (1) {
2255 struct auxtrace_queue *queue;
2256 struct intel_pt_queue *ptq;
2257
2258 if (!pt->heap.heap_cnt)
2259 return 0;
2260
2261 if (pt->heap.heap_array[0].ordinal >= timestamp)
2262 return 0;
2263
2264 queue_nr = pt->heap.heap_array[0].queue_nr;
2265 queue = &pt->queues.queue_array[queue_nr];
2266 ptq = queue->priv;
2267
2268 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
2269 queue_nr, pt->heap.heap_array[0].ordinal,
2270 timestamp);
2271
2272 auxtrace_heap__pop(&pt->heap);
2273
2274 if (pt->heap.heap_cnt) {
2275 ts = pt->heap.heap_array[0].ordinal + 1;
2276 if (ts > timestamp)
2277 ts = timestamp;
2278 } else {
2279 ts = timestamp;
2280 }
2281
2282 intel_pt_set_pid_tid_cpu(pt, queue);
2283
2284 ret = intel_pt_run_decoder(ptq, &ts);
2285
2286 if (ret < 0) {
2287 auxtrace_heap__add(&pt->heap, queue_nr, ts);
2288 return ret;
2289 }
2290
2291 if (!ret) {
2292 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
2293 if (ret < 0)
2294 return ret;
2295 } else {
2296 ptq->on_heap = false;
2297 }
2298 }
2299
2300 return 0;
2301}
2302
2303static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
2304 u64 time_)
2305{
2306 struct auxtrace_queues *queues = &pt->queues;
2307 unsigned int i;
2308 u64 ts = 0;
2309
2310 for (i = 0; i < queues->nr_queues; i++) {
2311 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2312 struct intel_pt_queue *ptq = queue->priv;
2313
2314 if (ptq && (tid == -1 || ptq->tid == tid)) {
2315 ptq->time = time_;
2316 intel_pt_set_pid_tid_cpu(pt, queue);
2317 intel_pt_run_decoder(ptq, &ts);
2318 }
2319 }
2320 return 0;
2321}
2322
2323static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
2324{
2325 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
2326 sample->pid, sample->tid, 0, sample->time);
2327}
2328
2329static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
2330{
2331 unsigned i, j;
2332
2333 if (cpu < 0 || !pt->queues.nr_queues)
2334 return NULL;
2335
2336 if ((unsigned)cpu >= pt->queues.nr_queues)
2337 i = pt->queues.nr_queues - 1;
2338 else
2339 i = cpu;
2340
2341 if (pt->queues.queue_array[i].cpu == cpu)
2342 return pt->queues.queue_array[i].priv;
2343
2344 for (j = 0; i > 0; j++) {
2345 if (pt->queues.queue_array[--i].cpu == cpu)
2346 return pt->queues.queue_array[i].priv;
2347 }
2348
2349 for (; j < pt->queues.nr_queues; j++) {
2350 if (pt->queues.queue_array[j].cpu == cpu)
2351 return pt->queues.queue_array[j].priv;
2352 }
2353
2354 return NULL;
2355}
2356
2357static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
2358 u64 timestamp)
2359{
2360 struct intel_pt_queue *ptq;
2361 int err;
2362
2363 if (!pt->sync_switch)
2364 return 1;
2365
2366 ptq = intel_pt_cpu_to_ptq(pt, cpu);
2367 if (!ptq || !ptq->sync_switch)
2368 return 1;
2369
2370 switch (ptq->switch_state) {
2371 case INTEL_PT_SS_NOT_TRACING:
2372 break;
2373 case INTEL_PT_SS_UNKNOWN:
2374 case INTEL_PT_SS_TRACING:
2375 ptq->next_tid = tid;
2376 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
2377 return 0;
2378 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
2379 if (!ptq->on_heap) {
2380 ptq->timestamp = perf_time_to_tsc(timestamp,
2381 &pt->tc);
2382 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
2383 ptq->timestamp);
2384 if (err)
2385 return err;
2386 ptq->on_heap = true;
2387 }
2388 ptq->switch_state = INTEL_PT_SS_TRACING;
2389 break;
2390 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2391 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
2392 break;
2393 default:
2394 break;
2395 }
2396
2397 ptq->next_tid = -1;
2398
2399 return 1;
2400}
2401
2402static int intel_pt_process_switch(struct intel_pt *pt,
2403 struct perf_sample *sample)
2404{
2405 struct evsel *evsel;
2406 pid_t tid;
2407 int cpu, ret;
2408
2409 evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id);
2410 if (evsel != pt->switch_evsel)
2411 return 0;
2412
2413 tid = perf_evsel__intval(evsel, sample, "next_pid");
2414 cpu = sample->cpu;
2415
2416 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2417 cpu, tid, sample->time, perf_time_to_tsc(sample->time,
2418 &pt->tc));
2419
2420 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
2421 if (ret <= 0)
2422 return ret;
2423
2424 return machine__set_current_tid(pt->machine, cpu, -1, tid);
2425}
2426
2427static int intel_pt_context_switch_in(struct intel_pt *pt,
2428 struct perf_sample *sample)
2429{
2430 pid_t pid = sample->pid;
2431 pid_t tid = sample->tid;
2432 int cpu = sample->cpu;
2433
2434 if (pt->sync_switch) {
2435 struct intel_pt_queue *ptq;
2436
2437 ptq = intel_pt_cpu_to_ptq(pt, cpu);
2438 if (ptq && ptq->sync_switch) {
2439 ptq->next_tid = -1;
2440 switch (ptq->switch_state) {
2441 case INTEL_PT_SS_NOT_TRACING:
2442 case INTEL_PT_SS_UNKNOWN:
2443 case INTEL_PT_SS_TRACING:
2444 break;
2445 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
2446 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2447 ptq->switch_state = INTEL_PT_SS_TRACING;
2448 break;
2449 default:
2450 break;
2451 }
2452 }
2453 }
2454
2455 /*
2456 * If the current tid has not been updated yet, ensure it is now that
2457 * a "switch in" event has occurred.
2458 */
2459 if (machine__get_current_tid(pt->machine, cpu) == tid)
2460 return 0;
2461
2462 return machine__set_current_tid(pt->machine, cpu, pid, tid);
2463}
2464
2465static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
2466 struct perf_sample *sample)
2467{
2468 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
2469 pid_t pid, tid;
2470 int cpu, ret;
2471
2472 cpu = sample->cpu;
2473
2474 if (pt->have_sched_switch == 3) {
2475 if (!out)
2476 return intel_pt_context_switch_in(pt, sample);
2477 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
2478 pr_err("Expecting CPU-wide context switch event\n");
2479 return -EINVAL;
2480 }
2481 pid = event->context_switch.next_prev_pid;
2482 tid = event->context_switch.next_prev_tid;
2483 } else {
2484 if (out)
2485 return 0;
2486 pid = sample->pid;
2487 tid = sample->tid;
2488 }
2489
2490 if (tid == -1) {
2491 pr_err("context_switch event has no tid\n");
2492 return -EINVAL;
2493 }
2494
2495 intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2496 cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time,
2497 &pt->tc));
2498
2499 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
2500 if (ret <= 0)
2501 return ret;
2502
2503 return machine__set_current_tid(pt->machine, cpu, pid, tid);
2504}
2505
2506static int intel_pt_process_itrace_start(struct intel_pt *pt,
2507 union perf_event *event,
2508 struct perf_sample *sample)
2509{
2510 if (!pt->per_cpu_mmaps)
2511 return 0;
2512
2513 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
2514 sample->cpu, event->itrace_start.pid,
2515 event->itrace_start.tid, sample->time,
2516 perf_time_to_tsc(sample->time, &pt->tc));
2517
2518 return machine__set_current_tid(pt->machine, sample->cpu,
2519 event->itrace_start.pid,
2520 event->itrace_start.tid);
2521}
2522
2523static int intel_pt_process_event(struct perf_session *session,
2524 union perf_event *event,
2525 struct perf_sample *sample,
2526 struct perf_tool *tool)
2527{
2528 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2529 auxtrace);
2530 u64 timestamp;
2531 int err = 0;
2532
2533 if (dump_trace)
2534 return 0;
2535
2536 if (!tool->ordered_events) {
2537 pr_err("Intel Processor Trace requires ordered events\n");
2538 return -EINVAL;
2539 }
2540
2541 if (sample->time && sample->time != (u64)-1)
2542 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
2543 else
2544 timestamp = 0;
2545
2546 if (timestamp || pt->timeless_decoding) {
2547 err = intel_pt_update_queues(pt);
2548 if (err)
2549 return err;
2550 }
2551
2552 if (pt->timeless_decoding) {
2553 if (event->header.type == PERF_RECORD_EXIT) {
2554 err = intel_pt_process_timeless_queues(pt,
2555 event->fork.tid,
2556 sample->time);
2557 }
2558 } else if (timestamp) {
2559 err = intel_pt_process_queues(pt, timestamp);
2560 }
2561 if (err)
2562 return err;
2563
2564 if (event->header.type == PERF_RECORD_AUX &&
2565 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
2566 pt->synth_opts.errors) {
2567 err = intel_pt_lost(pt, sample);
2568 if (err)
2569 return err;
2570 }
2571
2572 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
2573 err = intel_pt_process_switch(pt, sample);
2574 else if (event->header.type == PERF_RECORD_ITRACE_START)
2575 err = intel_pt_process_itrace_start(pt, event, sample);
2576 else if (event->header.type == PERF_RECORD_SWITCH ||
2577 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
2578 err = intel_pt_context_switch(pt, event, sample);
2579
2580 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ",
2581 event->header.type, sample->cpu, sample->time, timestamp);
2582 intel_pt_log_event(event);
2583
2584 return err;
2585}
2586
2587static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
2588{
2589 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2590 auxtrace);
2591 int ret;
2592
2593 if (dump_trace)
2594 return 0;
2595
2596 if (!tool->ordered_events)
2597 return -EINVAL;
2598
2599 ret = intel_pt_update_queues(pt);
2600 if (ret < 0)
2601 return ret;
2602
2603 if (pt->timeless_decoding)
2604 return intel_pt_process_timeless_queues(pt, -1,
2605 MAX_TIMESTAMP - 1);
2606
2607 return intel_pt_process_queues(pt, MAX_TIMESTAMP);
2608}
2609
2610static void intel_pt_free_events(struct perf_session *session)
2611{
2612 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2613 auxtrace);
2614 struct auxtrace_queues *queues = &pt->queues;
2615 unsigned int i;
2616
2617 for (i = 0; i < queues->nr_queues; i++) {
2618 intel_pt_free_queue(queues->queue_array[i].priv);
2619 queues->queue_array[i].priv = NULL;
2620 }
2621 intel_pt_log_disable();
2622 auxtrace_queues__free(queues);
2623}
2624
2625static void intel_pt_free(struct perf_session *session)
2626{
2627 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2628 auxtrace);
2629
2630 auxtrace_heap__free(&pt->heap);
2631 intel_pt_free_events(session);
2632 session->auxtrace = NULL;
2633 thread__put(pt->unknown_thread);
2634 addr_filters__exit(&pt->filts);
2635 zfree(&pt->filter);
2636 zfree(&pt->time_ranges);
2637 free(pt);
2638}
2639
2640static int intel_pt_process_auxtrace_event(struct perf_session *session,
2641 union perf_event *event,
2642 struct perf_tool *tool __maybe_unused)
2643{
2644 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
2645 auxtrace);
2646
2647 if (!pt->data_queued) {
2648 struct auxtrace_buffer *buffer;
2649 off_t data_offset;
2650 int fd = perf_data__fd(session->data);
2651 int err;
2652
2653 if (perf_data__is_pipe(session->data)) {
2654 data_offset = 0;
2655 } else {
2656 data_offset = lseek(fd, 0, SEEK_CUR);
2657 if (data_offset == -1)
2658 return -errno;
2659 }
2660
2661 err = auxtrace_queues__add_event(&pt->queues, session, event,
2662 data_offset, &buffer);
2663 if (err)
2664 return err;
2665
2666 /* Dump here now we have copied a piped trace out of the pipe */
2667 if (dump_trace) {
2668 if (auxtrace_buffer__get_data(buffer, fd)) {
2669 intel_pt_dump_event(pt, buffer->data,
2670 buffer->size);
2671 auxtrace_buffer__put_data(buffer);
2672 }
2673 }
2674 }
2675
2676 return 0;
2677}
2678
2679struct intel_pt_synth {
2680 struct perf_tool dummy_tool;
2681 struct perf_session *session;
2682};
2683
2684static int intel_pt_event_synth(struct perf_tool *tool,
2685 union perf_event *event,
2686 struct perf_sample *sample __maybe_unused,
2687 struct machine *machine __maybe_unused)
2688{
2689 struct intel_pt_synth *intel_pt_synth =
2690 container_of(tool, struct intel_pt_synth, dummy_tool);
2691
2692 return perf_session__deliver_synth_event(intel_pt_synth->session, event,
2693 NULL);
2694}
2695
2696static int intel_pt_synth_event(struct perf_session *session, const char *name,
2697 struct perf_event_attr *attr, u64 id)
2698{
2699 struct intel_pt_synth intel_pt_synth;
2700 int err;
2701
2702 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
2703 name, id, (u64)attr->sample_type);
2704
2705 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
2706 intel_pt_synth.session = session;
2707
2708 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
2709 &id, intel_pt_event_synth);
2710 if (err)
2711 pr_err("%s: failed to synthesize '%s' event type\n",
2712 __func__, name);
2713
2714 return err;
2715}
2716
2717static void intel_pt_set_event_name(struct evlist *evlist, u64 id,
2718 const char *name)
2719{
2720 struct evsel *evsel;
2721
2722 evlist__for_each_entry(evlist, evsel) {
2723 if (evsel->core.id && evsel->core.id[0] == id) {
2724 if (evsel->name)
2725 zfree(&evsel->name);
2726 evsel->name = strdup(name);
2727 break;
2728 }
2729 }
2730}
2731
2732static struct evsel *intel_pt_evsel(struct intel_pt *pt,
2733 struct evlist *evlist)
2734{
2735 struct evsel *evsel;
2736
2737 evlist__for_each_entry(evlist, evsel) {
2738 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids)
2739 return evsel;
2740 }
2741
2742 return NULL;
2743}
2744
2745static int intel_pt_synth_events(struct intel_pt *pt,
2746 struct perf_session *session)
2747{
2748 struct evlist *evlist = session->evlist;
2749 struct evsel *evsel = intel_pt_evsel(pt, evlist);
2750 struct perf_event_attr attr;
2751 u64 id;
2752 int err;
2753
2754 if (!evsel) {
2755 pr_debug("There are no selected events with Intel Processor Trace data\n");
2756 return 0;
2757 }
2758
2759 memset(&attr, 0, sizeof(struct perf_event_attr));
2760 attr.size = sizeof(struct perf_event_attr);
2761 attr.type = PERF_TYPE_HARDWARE;
2762 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK;
2763 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
2764 PERF_SAMPLE_PERIOD;
2765 if (pt->timeless_decoding)
2766 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
2767 else
2768 attr.sample_type |= PERF_SAMPLE_TIME;
2769 if (!pt->per_cpu_mmaps)
2770 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
2771 attr.exclude_user = evsel->core.attr.exclude_user;
2772 attr.exclude_kernel = evsel->core.attr.exclude_kernel;
2773 attr.exclude_hv = evsel->core.attr.exclude_hv;
2774 attr.exclude_host = evsel->core.attr.exclude_host;
2775 attr.exclude_guest = evsel->core.attr.exclude_guest;
2776 attr.sample_id_all = evsel->core.attr.sample_id_all;
2777 attr.read_format = evsel->core.attr.read_format;
2778
2779 id = evsel->core.id[0] + 1000000000;
2780 if (!id)
2781 id = 1;
2782
2783 if (pt->synth_opts.branches) {
2784 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
2785 attr.sample_period = 1;
2786 attr.sample_type |= PERF_SAMPLE_ADDR;
2787 err = intel_pt_synth_event(session, "branches", &attr, id);
2788 if (err)
2789 return err;
2790 pt->sample_branches = true;
2791 pt->branches_sample_type = attr.sample_type;
2792 pt->branches_id = id;
2793 id += 1;
2794 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
2795 }
2796
2797 if (pt->synth_opts.callchain)
2798 attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
2799 if (pt->synth_opts.last_branch)
2800 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
2801
2802 if (pt->synth_opts.instructions) {
2803 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
2804 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
2805 attr.sample_period =
2806 intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
2807 else
2808 attr.sample_period = pt->synth_opts.period;
2809 err = intel_pt_synth_event(session, "instructions", &attr, id);
2810 if (err)
2811 return err;
2812 pt->sample_instructions = true;
2813 pt->instructions_sample_type = attr.sample_type;
2814 pt->instructions_id = id;
2815 id += 1;
2816 }
2817
2818 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
2819 attr.sample_period = 1;
2820
2821 if (pt->synth_opts.transactions) {
2822 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
2823 err = intel_pt_synth_event(session, "transactions", &attr, id);
2824 if (err)
2825 return err;
2826 pt->sample_transactions = true;
2827 pt->transactions_sample_type = attr.sample_type;
2828 pt->transactions_id = id;
2829 intel_pt_set_event_name(evlist, id, "transactions");
2830 id += 1;
2831 }
2832
2833 attr.type = PERF_TYPE_SYNTH;
2834 attr.sample_type |= PERF_SAMPLE_RAW;
2835
2836 if (pt->synth_opts.ptwrites) {
2837 attr.config = PERF_SYNTH_INTEL_PTWRITE;
2838 err = intel_pt_synth_event(session, "ptwrite", &attr, id);
2839 if (err)
2840 return err;
2841 pt->sample_ptwrites = true;
2842 pt->ptwrites_sample_type = attr.sample_type;
2843 pt->ptwrites_id = id;
2844 intel_pt_set_event_name(evlist, id, "ptwrite");
2845 id += 1;
2846 }
2847
2848 if (pt->synth_opts.pwr_events) {
2849 pt->sample_pwr_events = true;
2850 pt->pwr_events_sample_type = attr.sample_type;
2851
2852 attr.config = PERF_SYNTH_INTEL_CBR;
2853 err = intel_pt_synth_event(session, "cbr", &attr, id);
2854 if (err)
2855 return err;
2856 pt->cbr_id = id;
2857 intel_pt_set_event_name(evlist, id, "cbr");
2858 id += 1;
2859 }
2860
2861 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) {
2862 attr.config = PERF_SYNTH_INTEL_MWAIT;
2863 err = intel_pt_synth_event(session, "mwait", &attr, id);
2864 if (err)
2865 return err;
2866 pt->mwait_id = id;
2867 intel_pt_set_event_name(evlist, id, "mwait");
2868 id += 1;
2869
2870 attr.config = PERF_SYNTH_INTEL_PWRE;
2871 err = intel_pt_synth_event(session, "pwre", &attr, id);
2872 if (err)
2873 return err;
2874 pt->pwre_id = id;
2875 intel_pt_set_event_name(evlist, id, "pwre");
2876 id += 1;
2877
2878 attr.config = PERF_SYNTH_INTEL_EXSTOP;
2879 err = intel_pt_synth_event(session, "exstop", &attr, id);
2880 if (err)
2881 return err;
2882 pt->exstop_id = id;
2883 intel_pt_set_event_name(evlist, id, "exstop");
2884 id += 1;
2885
2886 attr.config = PERF_SYNTH_INTEL_PWRX;
2887 err = intel_pt_synth_event(session, "pwrx", &attr, id);
2888 if (err)
2889 return err;
2890 pt->pwrx_id = id;
2891 intel_pt_set_event_name(evlist, id, "pwrx");
2892 id += 1;
2893 }
2894
2895 return 0;
2896}
2897
2898static void intel_pt_setup_pebs_events(struct intel_pt *pt)
2899{
2900 struct evsel *evsel;
2901
2902 if (!pt->synth_opts.other_events)
2903 return;
2904
2905 evlist__for_each_entry(pt->session->evlist, evsel) {
2906 if (evsel->core.attr.aux_output && evsel->core.id) {
2907 pt->sample_pebs = true;
2908 pt->pebs_evsel = evsel;
2909 return;
2910 }
2911 }
2912}
2913
2914static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist)
2915{
2916 struct evsel *evsel;
2917
2918 evlist__for_each_entry_reverse(evlist, evsel) {
2919 const char *name = perf_evsel__name(evsel);
2920
2921 if (!strcmp(name, "sched:sched_switch"))
2922 return evsel;
2923 }
2924
2925 return NULL;
2926}
2927
2928static bool intel_pt_find_switch(struct evlist *evlist)
2929{
2930 struct evsel *evsel;
2931
2932 evlist__for_each_entry(evlist, evsel) {
2933 if (evsel->core.attr.context_switch)
2934 return true;
2935 }
2936
2937 return false;
2938}
2939
2940static int intel_pt_perf_config(const char *var, const char *value, void *data)
2941{
2942 struct intel_pt *pt = data;
2943
2944 if (!strcmp(var, "intel-pt.mispred-all"))
2945 pt->mispred_all = perf_config_bool(var, value);
2946
2947 return 0;
2948}
2949
2950/* Find least TSC which converts to ns or later */
2951static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt)
2952{
2953 u64 tsc, tm;
2954
2955 tsc = perf_time_to_tsc(ns, &pt->tc);
2956
2957 while (1) {
2958 tm = tsc_to_perf_time(tsc, &pt->tc);
2959 if (tm < ns)
2960 break;
2961 tsc -= 1;
2962 }
2963
2964 while (tm < ns)
2965 tm = tsc_to_perf_time(++tsc, &pt->tc);
2966
2967 return tsc;
2968}
2969
2970/* Find greatest TSC which converts to ns or earlier */
2971static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt)
2972{
2973 u64 tsc, tm;
2974
2975 tsc = perf_time_to_tsc(ns, &pt->tc);
2976
2977 while (1) {
2978 tm = tsc_to_perf_time(tsc, &pt->tc);
2979 if (tm > ns)
2980 break;
2981 tsc += 1;
2982 }
2983
2984 while (tm > ns)
2985 tm = tsc_to_perf_time(--tsc, &pt->tc);
2986
2987 return tsc;
2988}
2989
2990static int intel_pt_setup_time_ranges(struct intel_pt *pt,
2991 struct itrace_synth_opts *opts)
2992{
2993 struct perf_time_interval *p = opts->ptime_range;
2994 int n = opts->range_num;
2995 int i;
2996
2997 if (!n || !p || pt->timeless_decoding)
2998 return 0;
2999
3000 pt->time_ranges = calloc(n, sizeof(struct range));
3001 if (!pt->time_ranges)
3002 return -ENOMEM;
3003
3004 pt->range_cnt = n;
3005
3006 intel_pt_log("%s: %u range(s)\n", __func__, n);
3007
3008 for (i = 0; i < n; i++) {
3009 struct range *r = &pt->time_ranges[i];
3010 u64 ts = p[i].start;
3011 u64 te = p[i].end;
3012
3013 /*
3014 * Take care to ensure the TSC range matches the perf-time range
3015 * when converted back to perf-time.
3016 */
3017 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0;
3018 r->end = te ? intel_pt_tsc_end(te, pt) : 0;
3019
3020 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n",
3021 i, ts, te);
3022 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n",
3023 i, r->start, r->end);
3024 }
3025
3026 return 0;
3027}
3028
3029static const char * const intel_pt_info_fmts[] = {
3030 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
3031 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
3032 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
3033 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
3034 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
3035 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
3036 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
3037 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
3038 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
3039 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
3040 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
3041 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
3042 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
3043 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
3044 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
3045 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
3046};
3047
3048static void intel_pt_print_info(__u64 *arr, int start, int finish)
3049{
3050 int i;
3051
3052 if (!dump_trace)
3053 return;
3054
3055 for (i = start; i <= finish; i++)
3056 fprintf(stdout, intel_pt_info_fmts[i], arr[i]);
3057}
3058
3059static void intel_pt_print_info_str(const char *name, const char *str)
3060{
3061 if (!dump_trace)
3062 return;
3063
3064 fprintf(stdout, " %-20s%s\n", name, str ? str : "");
3065}
3066
3067static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos)
3068{
3069 return auxtrace_info->header.size >=
3070 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1));
3071}
3072
3073int intel_pt_process_auxtrace_info(union perf_event *event,
3074 struct perf_session *session)
3075{
3076 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info;
3077 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
3078 struct intel_pt *pt;
3079 void *info_end;
3080 __u64 *info;
3081 int err;
3082
3083 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) +
3084 min_sz)
3085 return -EINVAL;
3086
3087 pt = zalloc(sizeof(struct intel_pt));
3088 if (!pt)
3089 return -ENOMEM;
3090
3091 addr_filters__init(&pt->filts);
3092
3093 err = perf_config(intel_pt_perf_config, pt);
3094 if (err)
3095 goto err_free;
3096
3097 err = auxtrace_queues__init(&pt->queues);
3098 if (err)
3099 goto err_free;
3100
3101 intel_pt_log_set_name(INTEL_PT_PMU_NAME);
3102
3103 pt->session = session;
3104 pt->machine = &session->machines.host; /* No kvm support */
3105 pt->auxtrace_type = auxtrace_info->type;
3106 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
3107 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
3108 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
3109 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
3110 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
3111 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
3112 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
3113 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
3114 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
3115 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
3116 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
3117 INTEL_PT_PER_CPU_MMAPS);
3118
3119 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
3120 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
3121 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
3122 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
3123 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
3124 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
3125 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
3126 INTEL_PT_CYC_BIT);
3127 }
3128
3129 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
3130 pt->max_non_turbo_ratio =
3131 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
3132 intel_pt_print_info(&auxtrace_info->priv[0],
3133 INTEL_PT_MAX_NONTURBO_RATIO,
3134 INTEL_PT_MAX_NONTURBO_RATIO);
3135 }
3136
3137 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
3138 info_end = (void *)info + auxtrace_info->header.size;
3139
3140 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
3141 size_t len;
3142
3143 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
3144 intel_pt_print_info(&auxtrace_info->priv[0],
3145 INTEL_PT_FILTER_STR_LEN,
3146 INTEL_PT_FILTER_STR_LEN);
3147 if (len) {
3148 const char *filter = (const char *)info;
3149
3150 len = roundup(len + 1, 8);
3151 info += len >> 3;
3152 if ((void *)info > info_end) {
3153 pr_err("%s: bad filter string length\n", __func__);
3154 err = -EINVAL;
3155 goto err_free_queues;
3156 }
3157 pt->filter = memdup(filter, len);
3158 if (!pt->filter) {
3159 err = -ENOMEM;
3160 goto err_free_queues;
3161 }
3162 if (session->header.needs_swap)
3163 mem_bswap_64(pt->filter, len);
3164 if (pt->filter[len - 1]) {
3165 pr_err("%s: filter string not null terminated\n", __func__);
3166 err = -EINVAL;
3167 goto err_free_queues;
3168 }
3169 err = addr_filters__parse_bare_filter(&pt->filts,
3170 filter);
3171 if (err)
3172 goto err_free_queues;
3173 }
3174 intel_pt_print_info_str("Filter string", pt->filter);
3175 }
3176
3177 pt->timeless_decoding = intel_pt_timeless_decoding(pt);
3178 if (pt->timeless_decoding && !pt->tc.time_mult)
3179 pt->tc.time_mult = 1;
3180 pt->have_tsc = intel_pt_have_tsc(pt);
3181 pt->sampling_mode = false;
3182 pt->est_tsc = !pt->timeless_decoding;
3183
3184 pt->unknown_thread = thread__new(999999999, 999999999);
3185 if (!pt->unknown_thread) {
3186 err = -ENOMEM;
3187 goto err_free_queues;
3188 }
3189
3190 /*
3191 * Since this thread will not be kept in any rbtree not in a
3192 * list, initialize its list node so that at thread__put() the
3193 * current thread lifetime assuption is kept and we don't segfault
3194 * at list_del_init().
3195 */
3196 INIT_LIST_HEAD(&pt->unknown_thread->node);
3197
3198 err = thread__set_comm(pt->unknown_thread, "unknown", 0);
3199 if (err)
3200 goto err_delete_thread;
3201 if (thread__init_map_groups(pt->unknown_thread, pt->machine)) {
3202 err = -ENOMEM;
3203 goto err_delete_thread;
3204 }
3205
3206 pt->auxtrace.process_event = intel_pt_process_event;
3207 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
3208 pt->auxtrace.flush_events = intel_pt_flush;
3209 pt->auxtrace.free_events = intel_pt_free_events;
3210 pt->auxtrace.free = intel_pt_free;
3211 session->auxtrace = &pt->auxtrace;
3212
3213 if (dump_trace)
3214 return 0;
3215
3216 if (pt->have_sched_switch == 1) {
3217 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
3218 if (!pt->switch_evsel) {
3219 pr_err("%s: missing sched_switch event\n", __func__);
3220 err = -EINVAL;
3221 goto err_delete_thread;
3222 }
3223 } else if (pt->have_sched_switch == 2 &&
3224 !intel_pt_find_switch(session->evlist)) {
3225 pr_err("%s: missing context_switch attribute flag\n", __func__);
3226 err = -EINVAL;
3227 goto err_delete_thread;
3228 }
3229
3230 if (session->itrace_synth_opts->set) {
3231 pt->synth_opts = *session->itrace_synth_opts;
3232 } else {
3233 itrace_synth_opts__set_default(&pt->synth_opts,
3234 session->itrace_synth_opts->default_no_sample);
3235 if (!session->itrace_synth_opts->default_no_sample &&
3236 !session->itrace_synth_opts->inject) {
3237 pt->synth_opts.branches = false;
3238 pt->synth_opts.callchain = true;
3239 }
3240 pt->synth_opts.thread_stack =
3241 session->itrace_synth_opts->thread_stack;
3242 }
3243
3244 if (pt->synth_opts.log)
3245 intel_pt_log_enable();
3246
3247 /* Maximum non-turbo ratio is TSC freq / 100 MHz */
3248 if (pt->tc.time_mult) {
3249 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
3250
3251 if (!pt->max_non_turbo_ratio)
3252 pt->max_non_turbo_ratio =
3253 (tsc_freq + 50000000) / 100000000;
3254 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
3255 intel_pt_log("Maximum non-turbo ratio %u\n",
3256 pt->max_non_turbo_ratio);
3257 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
3258 }
3259
3260 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts);
3261 if (err)
3262 goto err_delete_thread;
3263
3264 if (pt->synth_opts.calls)
3265 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
3266 PERF_IP_FLAG_TRACE_END;
3267 if (pt->synth_opts.returns)
3268 pt->branches_filter |= PERF_IP_FLAG_RETURN |
3269 PERF_IP_FLAG_TRACE_BEGIN;
3270
3271 if (pt->synth_opts.callchain && !symbol_conf.use_callchain) {
3272 symbol_conf.use_callchain = true;
3273 if (callchain_register_param(&callchain_param) < 0) {
3274 symbol_conf.use_callchain = false;
3275 pt->synth_opts.callchain = false;
3276 }
3277 }
3278
3279 err = intel_pt_synth_events(pt, session);
3280 if (err)
3281 goto err_delete_thread;
3282
3283 intel_pt_setup_pebs_events(pt);
3284
3285 err = auxtrace_queues__process_index(&pt->queues, session);
3286 if (err)
3287 goto err_delete_thread;
3288
3289 if (pt->queues.populated)
3290 pt->data_queued = true;
3291
3292 if (pt->timeless_decoding)
3293 pr_debug2("Intel PT decoding without timestamps\n");
3294
3295 return 0;
3296
3297err_delete_thread:
3298 thread__zput(pt->unknown_thread);
3299err_free_queues:
3300 intel_pt_log_disable();
3301 auxtrace_queues__free(&pt->queues);
3302 session->auxtrace = NULL;
3303err_free:
3304 addr_filters__exit(&pt->filts);
3305 zfree(&pt->filter);
3306 zfree(&pt->time_ranges);
3307 free(pt);
3308 return err;
3309}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * intel_pt.c: Intel Processor Trace support
4 * Copyright (c) 2013-2015, Intel Corporation.
5 */
6
7#include <inttypes.h>
8#include <stdio.h>
9#include <stdbool.h>
10#include <errno.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/types.h>
14#include <linux/zalloc.h>
15
16#include "session.h"
17#include "machine.h"
18#include "memswap.h"
19#include "sort.h"
20#include "tool.h"
21#include "event.h"
22#include "evlist.h"
23#include "evsel.h"
24#include "map.h"
25#include "color.h"
26#include "thread.h"
27#include "thread-stack.h"
28#include "symbol.h"
29#include "callchain.h"
30#include "dso.h"
31#include "debug.h"
32#include "auxtrace.h"
33#include "tsc.h"
34#include "intel-pt.h"
35#include "config.h"
36#include "util/perf_api_probe.h"
37#include "util/synthetic-events.h"
38#include "time-utils.h"
39
40#include "../arch/x86/include/uapi/asm/perf_regs.h"
41
42#include "intel-pt-decoder/intel-pt-log.h"
43#include "intel-pt-decoder/intel-pt-decoder.h"
44#include "intel-pt-decoder/intel-pt-insn-decoder.h"
45#include "intel-pt-decoder/intel-pt-pkt-decoder.h"
46
47#define MAX_TIMESTAMP (~0ULL)
48
49#define INTEL_PT_CFG_PASS_THRU BIT_ULL(0)
50#define INTEL_PT_CFG_PWR_EVT_EN BIT_ULL(4)
51#define INTEL_PT_CFG_BRANCH_EN BIT_ULL(13)
52#define INTEL_PT_CFG_EVT_EN BIT_ULL(31)
53#define INTEL_PT_CFG_TNT_DIS BIT_ULL(55)
54
55struct range {
56 u64 start;
57 u64 end;
58};
59
60struct intel_pt {
61 struct auxtrace auxtrace;
62 struct auxtrace_queues queues;
63 struct auxtrace_heap heap;
64 u32 auxtrace_type;
65 struct perf_session *session;
66 struct machine *machine;
67 struct evsel *switch_evsel;
68 struct thread *unknown_thread;
69 bool timeless_decoding;
70 bool sampling_mode;
71 bool snapshot_mode;
72 bool per_cpu_mmaps;
73 bool have_tsc;
74 bool data_queued;
75 bool est_tsc;
76 bool sync_switch;
77 bool sync_switch_not_supported;
78 bool mispred_all;
79 bool use_thread_stack;
80 bool callstack;
81 bool cap_event_trace;
82 bool have_guest_sideband;
83 unsigned int br_stack_sz;
84 unsigned int br_stack_sz_plus;
85 int have_sched_switch;
86 u32 pmu_type;
87 u64 kernel_start;
88 u64 switch_ip;
89 u64 ptss_ip;
90 u64 first_timestamp;
91
92 struct perf_tsc_conversion tc;
93 bool cap_user_time_zero;
94
95 struct itrace_synth_opts synth_opts;
96
97 bool sample_instructions;
98 u64 instructions_sample_type;
99 u64 instructions_id;
100
101 bool sample_branches;
102 u32 branches_filter;
103 u64 branches_sample_type;
104 u64 branches_id;
105
106 bool sample_transactions;
107 u64 transactions_sample_type;
108 u64 transactions_id;
109
110 bool sample_ptwrites;
111 u64 ptwrites_sample_type;
112 u64 ptwrites_id;
113
114 bool sample_pwr_events;
115 u64 pwr_events_sample_type;
116 u64 mwait_id;
117 u64 pwre_id;
118 u64 exstop_id;
119 u64 pwrx_id;
120 u64 cbr_id;
121 u64 psb_id;
122
123 bool single_pebs;
124 bool sample_pebs;
125 struct evsel *pebs_evsel;
126
127 u64 evt_sample_type;
128 u64 evt_id;
129
130 u64 iflag_chg_sample_type;
131 u64 iflag_chg_id;
132
133 u64 tsc_bit;
134 u64 mtc_bit;
135 u64 mtc_freq_bits;
136 u32 tsc_ctc_ratio_n;
137 u32 tsc_ctc_ratio_d;
138 u64 cyc_bit;
139 u64 noretcomp_bit;
140 unsigned max_non_turbo_ratio;
141 unsigned cbr2khz;
142 int max_loops;
143
144 unsigned long num_events;
145
146 char *filter;
147 struct addr_filters filts;
148
149 struct range *time_ranges;
150 unsigned int range_cnt;
151
152 struct ip_callchain *chain;
153 struct branch_stack *br_stack;
154
155 u64 dflt_tsc_offset;
156 struct rb_root vmcs_info;
157};
158
159enum switch_state {
160 INTEL_PT_SS_NOT_TRACING,
161 INTEL_PT_SS_UNKNOWN,
162 INTEL_PT_SS_TRACING,
163 INTEL_PT_SS_EXPECTING_SWITCH_EVENT,
164 INTEL_PT_SS_EXPECTING_SWITCH_IP,
165};
166
167/* applicable_counters is 64-bits */
168#define INTEL_PT_MAX_PEBS 64
169
170struct intel_pt_pebs_event {
171 struct evsel *evsel;
172 u64 id;
173};
174
175struct intel_pt_queue {
176 struct intel_pt *pt;
177 unsigned int queue_nr;
178 struct auxtrace_buffer *buffer;
179 struct auxtrace_buffer *old_buffer;
180 void *decoder;
181 const struct intel_pt_state *state;
182 struct ip_callchain *chain;
183 struct branch_stack *last_branch;
184 union perf_event *event_buf;
185 bool on_heap;
186 bool stop;
187 bool step_through_buffers;
188 bool use_buffer_pid_tid;
189 bool sync_switch;
190 bool sample_ipc;
191 pid_t pid, tid;
192 int cpu;
193 int switch_state;
194 pid_t next_tid;
195 struct thread *thread;
196 struct machine *guest_machine;
197 struct thread *guest_thread;
198 struct thread *unknown_guest_thread;
199 pid_t guest_machine_pid;
200 pid_t guest_pid;
201 pid_t guest_tid;
202 int vcpu;
203 bool exclude_kernel;
204 bool have_sample;
205 u64 time;
206 u64 timestamp;
207 u64 sel_timestamp;
208 bool sel_start;
209 unsigned int sel_idx;
210 u32 flags;
211 u16 insn_len;
212 u64 last_insn_cnt;
213 u64 ipc_insn_cnt;
214 u64 ipc_cyc_cnt;
215 u64 last_in_insn_cnt;
216 u64 last_in_cyc_cnt;
217 u64 last_br_insn_cnt;
218 u64 last_br_cyc_cnt;
219 unsigned int cbr_seen;
220 char insn[INTEL_PT_INSN_BUF_SZ];
221 struct intel_pt_pebs_event pebs[INTEL_PT_MAX_PEBS];
222};
223
224static void intel_pt_dump(struct intel_pt *pt __maybe_unused,
225 unsigned char *buf, size_t len)
226{
227 struct intel_pt_pkt packet;
228 size_t pos = 0;
229 int ret, pkt_len, i;
230 char desc[INTEL_PT_PKT_DESC_MAX];
231 const char *color = PERF_COLOR_BLUE;
232 enum intel_pt_pkt_ctx ctx = INTEL_PT_NO_CTX;
233
234 color_fprintf(stdout, color,
235 ". ... Intel Processor Trace data: size %zu bytes\n",
236 len);
237
238 while (len) {
239 ret = intel_pt_get_packet(buf, len, &packet, &ctx);
240 if (ret > 0)
241 pkt_len = ret;
242 else
243 pkt_len = 1;
244 printf(".");
245 color_fprintf(stdout, color, " %08x: ", pos);
246 for (i = 0; i < pkt_len; i++)
247 color_fprintf(stdout, color, " %02x", buf[i]);
248 for (; i < 16; i++)
249 color_fprintf(stdout, color, " ");
250 if (ret > 0) {
251 ret = intel_pt_pkt_desc(&packet, desc,
252 INTEL_PT_PKT_DESC_MAX);
253 if (ret > 0)
254 color_fprintf(stdout, color, " %s\n", desc);
255 } else {
256 color_fprintf(stdout, color, " Bad packet!\n");
257 }
258 pos += pkt_len;
259 buf += pkt_len;
260 len -= pkt_len;
261 }
262}
263
264static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf,
265 size_t len)
266{
267 printf(".\n");
268 intel_pt_dump(pt, buf, len);
269}
270
271static void intel_pt_log_event(union perf_event *event)
272{
273 FILE *f = intel_pt_log_fp();
274
275 if (!intel_pt_enable_logging || !f)
276 return;
277
278 perf_event__fprintf(event, NULL, f);
279}
280
281static void intel_pt_dump_sample(struct perf_session *session,
282 struct perf_sample *sample)
283{
284 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
285 auxtrace);
286
287 printf("\n");
288 intel_pt_dump(pt, sample->aux_sample.data, sample->aux_sample.size);
289}
290
291static bool intel_pt_log_events(struct intel_pt *pt, u64 tm)
292{
293 struct perf_time_interval *range = pt->synth_opts.ptime_range;
294 int n = pt->synth_opts.range_num;
295
296 if (pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
297 return true;
298
299 if (pt->synth_opts.log_minus_flags & AUXTRACE_LOG_FLG_ALL_PERF_EVTS)
300 return false;
301
302 /* perf_time__ranges_skip_sample does not work if time is zero */
303 if (!tm)
304 tm = 1;
305
306 return !n || !perf_time__ranges_skip_sample(range, n, tm);
307}
308
309static struct intel_pt_vmcs_info *intel_pt_findnew_vmcs(struct rb_root *rb_root,
310 u64 vmcs,
311 u64 dflt_tsc_offset)
312{
313 struct rb_node **p = &rb_root->rb_node;
314 struct rb_node *parent = NULL;
315 struct intel_pt_vmcs_info *v;
316
317 while (*p) {
318 parent = *p;
319 v = rb_entry(parent, struct intel_pt_vmcs_info, rb_node);
320
321 if (v->vmcs == vmcs)
322 return v;
323
324 if (vmcs < v->vmcs)
325 p = &(*p)->rb_left;
326 else
327 p = &(*p)->rb_right;
328 }
329
330 v = zalloc(sizeof(*v));
331 if (v) {
332 v->vmcs = vmcs;
333 v->tsc_offset = dflt_tsc_offset;
334 v->reliable = dflt_tsc_offset;
335
336 rb_link_node(&v->rb_node, parent, p);
337 rb_insert_color(&v->rb_node, rb_root);
338 }
339
340 return v;
341}
342
343static struct intel_pt_vmcs_info *intel_pt_findnew_vmcs_info(void *data, uint64_t vmcs)
344{
345 struct intel_pt_queue *ptq = data;
346 struct intel_pt *pt = ptq->pt;
347
348 if (!vmcs && !pt->dflt_tsc_offset)
349 return NULL;
350
351 return intel_pt_findnew_vmcs(&pt->vmcs_info, vmcs, pt->dflt_tsc_offset);
352}
353
354static void intel_pt_free_vmcs_info(struct intel_pt *pt)
355{
356 struct intel_pt_vmcs_info *v;
357 struct rb_node *n;
358
359 n = rb_first(&pt->vmcs_info);
360 while (n) {
361 v = rb_entry(n, struct intel_pt_vmcs_info, rb_node);
362 n = rb_next(n);
363 rb_erase(&v->rb_node, &pt->vmcs_info);
364 free(v);
365 }
366}
367
368static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a,
369 struct auxtrace_buffer *b)
370{
371 bool consecutive = false;
372 void *start;
373
374 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size,
375 pt->have_tsc, &consecutive,
376 pt->synth_opts.vm_time_correlation);
377 if (!start)
378 return -EINVAL;
379 /*
380 * In the case of vm_time_correlation, the overlap might contain TSC
381 * packets that will not be fixed, and that will then no longer work for
382 * overlap detection. Avoid that by zeroing out the overlap.
383 */
384 if (pt->synth_opts.vm_time_correlation)
385 memset(b->data, 0, start - b->data);
386 b->use_size = b->data + b->size - start;
387 b->use_data = start;
388 if (b->use_size && consecutive)
389 b->consecutive = true;
390 return 0;
391}
392
393static int intel_pt_get_buffer(struct intel_pt_queue *ptq,
394 struct auxtrace_buffer *buffer,
395 struct auxtrace_buffer *old_buffer,
396 struct intel_pt_buffer *b)
397{
398 bool might_overlap;
399
400 if (!buffer->data) {
401 int fd = perf_data__fd(ptq->pt->session->data);
402
403 buffer->data = auxtrace_buffer__get_data(buffer, fd);
404 if (!buffer->data)
405 return -ENOMEM;
406 }
407
408 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode;
409 if (might_overlap && !buffer->consecutive && old_buffer &&
410 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer))
411 return -ENOMEM;
412
413 if (buffer->use_data) {
414 b->len = buffer->use_size;
415 b->buf = buffer->use_data;
416 } else {
417 b->len = buffer->size;
418 b->buf = buffer->data;
419 }
420 b->ref_timestamp = buffer->reference;
421
422 if (!old_buffer || (might_overlap && !buffer->consecutive)) {
423 b->consecutive = false;
424 b->trace_nr = buffer->buffer_nr + 1;
425 } else {
426 b->consecutive = true;
427 }
428
429 return 0;
430}
431
432/* Do not drop buffers with references - refer intel_pt_get_trace() */
433static void intel_pt_lookahead_drop_buffer(struct intel_pt_queue *ptq,
434 struct auxtrace_buffer *buffer)
435{
436 if (!buffer || buffer == ptq->buffer || buffer == ptq->old_buffer)
437 return;
438
439 auxtrace_buffer__drop_data(buffer);
440}
441
442/* Must be serialized with respect to intel_pt_get_trace() */
443static int intel_pt_lookahead(void *data, intel_pt_lookahead_cb_t cb,
444 void *cb_data)
445{
446 struct intel_pt_queue *ptq = data;
447 struct auxtrace_buffer *buffer = ptq->buffer;
448 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
449 struct auxtrace_queue *queue;
450 int err = 0;
451
452 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
453
454 while (1) {
455 struct intel_pt_buffer b = { .len = 0 };
456
457 buffer = auxtrace_buffer__next(queue, buffer);
458 if (!buffer)
459 break;
460
461 err = intel_pt_get_buffer(ptq, buffer, old_buffer, &b);
462 if (err)
463 break;
464
465 if (b.len) {
466 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
467 old_buffer = buffer;
468 } else {
469 intel_pt_lookahead_drop_buffer(ptq, buffer);
470 continue;
471 }
472
473 err = cb(&b, cb_data);
474 if (err)
475 break;
476 }
477
478 if (buffer != old_buffer)
479 intel_pt_lookahead_drop_buffer(ptq, buffer);
480 intel_pt_lookahead_drop_buffer(ptq, old_buffer);
481
482 return err;
483}
484
485/*
486 * This function assumes data is processed sequentially only.
487 * Must be serialized with respect to intel_pt_lookahead()
488 */
489static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data)
490{
491 struct intel_pt_queue *ptq = data;
492 struct auxtrace_buffer *buffer = ptq->buffer;
493 struct auxtrace_buffer *old_buffer = ptq->old_buffer;
494 struct auxtrace_queue *queue;
495 int err;
496
497 if (ptq->stop) {
498 b->len = 0;
499 return 0;
500 }
501
502 queue = &ptq->pt->queues.queue_array[ptq->queue_nr];
503
504 buffer = auxtrace_buffer__next(queue, buffer);
505 if (!buffer) {
506 if (old_buffer)
507 auxtrace_buffer__drop_data(old_buffer);
508 b->len = 0;
509 return 0;
510 }
511
512 ptq->buffer = buffer;
513
514 err = intel_pt_get_buffer(ptq, buffer, old_buffer, b);
515 if (err)
516 return err;
517
518 if (ptq->step_through_buffers)
519 ptq->stop = true;
520
521 if (b->len) {
522 if (old_buffer)
523 auxtrace_buffer__drop_data(old_buffer);
524 ptq->old_buffer = buffer;
525 } else {
526 auxtrace_buffer__drop_data(buffer);
527 return intel_pt_get_trace(b, data);
528 }
529
530 return 0;
531}
532
533struct intel_pt_cache_entry {
534 struct auxtrace_cache_entry entry;
535 u64 insn_cnt;
536 u64 byte_cnt;
537 enum intel_pt_insn_op op;
538 enum intel_pt_insn_branch branch;
539 bool emulated_ptwrite;
540 int length;
541 int32_t rel;
542 char insn[INTEL_PT_INSN_BUF_SZ];
543};
544
545static int intel_pt_config_div(const char *var, const char *value, void *data)
546{
547 int *d = data;
548 long val;
549
550 if (!strcmp(var, "intel-pt.cache-divisor")) {
551 val = strtol(value, NULL, 0);
552 if (val > 0 && val <= INT_MAX)
553 *d = val;
554 }
555
556 return 0;
557}
558
559static int intel_pt_cache_divisor(void)
560{
561 static int d;
562
563 if (d)
564 return d;
565
566 perf_config(intel_pt_config_div, &d);
567
568 if (!d)
569 d = 64;
570
571 return d;
572}
573
574static unsigned int intel_pt_cache_size(struct dso *dso,
575 struct machine *machine)
576{
577 off_t size;
578
579 size = dso__data_size(dso, machine);
580 size /= intel_pt_cache_divisor();
581 if (size < 1000)
582 return 10;
583 if (size > (1 << 21))
584 return 21;
585 return 32 - __builtin_clz(size);
586}
587
588static struct auxtrace_cache *intel_pt_cache(struct dso *dso,
589 struct machine *machine)
590{
591 struct auxtrace_cache *c;
592 unsigned int bits;
593
594 if (dso->auxtrace_cache)
595 return dso->auxtrace_cache;
596
597 bits = intel_pt_cache_size(dso, machine);
598
599 /* Ignoring cache creation failure */
600 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200);
601
602 dso->auxtrace_cache = c;
603
604 return c;
605}
606
607static int intel_pt_cache_add(struct dso *dso, struct machine *machine,
608 u64 offset, u64 insn_cnt, u64 byte_cnt,
609 struct intel_pt_insn *intel_pt_insn)
610{
611 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
612 struct intel_pt_cache_entry *e;
613 int err;
614
615 if (!c)
616 return -ENOMEM;
617
618 e = auxtrace_cache__alloc_entry(c);
619 if (!e)
620 return -ENOMEM;
621
622 e->insn_cnt = insn_cnt;
623 e->byte_cnt = byte_cnt;
624 e->op = intel_pt_insn->op;
625 e->branch = intel_pt_insn->branch;
626 e->emulated_ptwrite = intel_pt_insn->emulated_ptwrite;
627 e->length = intel_pt_insn->length;
628 e->rel = intel_pt_insn->rel;
629 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ);
630
631 err = auxtrace_cache__add(c, offset, &e->entry);
632 if (err)
633 auxtrace_cache__free_entry(c, e);
634
635 return err;
636}
637
638static struct intel_pt_cache_entry *
639intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset)
640{
641 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
642
643 if (!c)
644 return NULL;
645
646 return auxtrace_cache__lookup(dso->auxtrace_cache, offset);
647}
648
649static void intel_pt_cache_invalidate(struct dso *dso, struct machine *machine,
650 u64 offset)
651{
652 struct auxtrace_cache *c = intel_pt_cache(dso, machine);
653
654 if (!c)
655 return;
656
657 auxtrace_cache__remove(dso->auxtrace_cache, offset);
658}
659
660static inline bool intel_pt_guest_kernel_ip(uint64_t ip)
661{
662 /* Assumes 64-bit kernel */
663 return ip & (1ULL << 63);
664}
665
666static inline u8 intel_pt_nr_cpumode(struct intel_pt_queue *ptq, uint64_t ip, bool nr)
667{
668 if (nr) {
669 return intel_pt_guest_kernel_ip(ip) ?
670 PERF_RECORD_MISC_GUEST_KERNEL :
671 PERF_RECORD_MISC_GUEST_USER;
672 }
673
674 return ip >= ptq->pt->kernel_start ?
675 PERF_RECORD_MISC_KERNEL :
676 PERF_RECORD_MISC_USER;
677}
678
679static inline u8 intel_pt_cpumode(struct intel_pt_queue *ptq, uint64_t from_ip, uint64_t to_ip)
680{
681 /* No support for non-zero CS base */
682 if (from_ip)
683 return intel_pt_nr_cpumode(ptq, from_ip, ptq->state->from_nr);
684 return intel_pt_nr_cpumode(ptq, to_ip, ptq->state->to_nr);
685}
686
687static int intel_pt_get_guest(struct intel_pt_queue *ptq)
688{
689 struct machines *machines = &ptq->pt->session->machines;
690 struct machine *machine;
691 pid_t pid = ptq->pid <= 0 ? DEFAULT_GUEST_KERNEL_ID : ptq->pid;
692
693 if (ptq->guest_machine && pid == ptq->guest_machine->pid)
694 return 0;
695
696 ptq->guest_machine = NULL;
697 thread__zput(ptq->unknown_guest_thread);
698
699 if (symbol_conf.guest_code) {
700 thread__zput(ptq->guest_thread);
701 ptq->guest_thread = machines__findnew_guest_code(machines, pid);
702 }
703
704 machine = machines__find_guest(machines, pid);
705 if (!machine)
706 return -1;
707
708 ptq->unknown_guest_thread = machine__idle_thread(machine);
709 if (!ptq->unknown_guest_thread)
710 return -1;
711
712 ptq->guest_machine = machine;
713
714 return 0;
715}
716
717static inline bool intel_pt_jmp_16(struct intel_pt_insn *intel_pt_insn)
718{
719 return intel_pt_insn->rel == 16 && intel_pt_insn->branch == INTEL_PT_BR_UNCONDITIONAL;
720}
721
722#define PTWRITE_MAGIC "\x0f\x0bperf,ptwrite "
723#define PTWRITE_MAGIC_LEN 16
724
725static bool intel_pt_emulated_ptwrite(struct dso *dso, struct machine *machine, u64 offset)
726{
727 unsigned char buf[PTWRITE_MAGIC_LEN];
728 ssize_t len;
729
730 len = dso__data_read_offset(dso, machine, offset, buf, PTWRITE_MAGIC_LEN);
731 if (len == PTWRITE_MAGIC_LEN && !memcmp(buf, PTWRITE_MAGIC, PTWRITE_MAGIC_LEN)) {
732 intel_pt_log("Emulated ptwrite signature found\n");
733 return true;
734 }
735 intel_pt_log("Emulated ptwrite signature not found\n");
736 return false;
737}
738
739static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn,
740 uint64_t *insn_cnt_ptr, uint64_t *ip,
741 uint64_t to_ip, uint64_t max_insn_cnt,
742 void *data)
743{
744 struct intel_pt_queue *ptq = data;
745 struct machine *machine = ptq->pt->machine;
746 struct thread *thread;
747 struct addr_location al;
748 unsigned char buf[INTEL_PT_INSN_BUF_SZ];
749 ssize_t len;
750 int x86_64;
751 u8 cpumode;
752 u64 offset, start_offset, start_ip;
753 u64 insn_cnt = 0;
754 bool one_map = true;
755 bool nr;
756
757 intel_pt_insn->length = 0;
758
759 if (to_ip && *ip == to_ip)
760 goto out_no_cache;
761
762 nr = ptq->state->to_nr;
763 cpumode = intel_pt_nr_cpumode(ptq, *ip, nr);
764
765 if (nr) {
766 if (ptq->pt->have_guest_sideband) {
767 if (!ptq->guest_machine || ptq->guest_machine_pid != ptq->pid) {
768 intel_pt_log("ERROR: guest sideband but no guest machine\n");
769 return -EINVAL;
770 }
771 } else if ((!symbol_conf.guest_code && cpumode != PERF_RECORD_MISC_GUEST_KERNEL) ||
772 intel_pt_get_guest(ptq)) {
773 intel_pt_log("ERROR: no guest machine\n");
774 return -EINVAL;
775 }
776 machine = ptq->guest_machine;
777 thread = ptq->guest_thread;
778 if (!thread) {
779 if (cpumode != PERF_RECORD_MISC_GUEST_KERNEL) {
780 intel_pt_log("ERROR: no guest thread\n");
781 return -EINVAL;
782 }
783 thread = ptq->unknown_guest_thread;
784 }
785 } else {
786 thread = ptq->thread;
787 if (!thread) {
788 if (cpumode != PERF_RECORD_MISC_KERNEL) {
789 intel_pt_log("ERROR: no thread\n");
790 return -EINVAL;
791 }
792 thread = ptq->pt->unknown_thread;
793 }
794 }
795
796 while (1) {
797 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso) {
798 if (al.map)
799 intel_pt_log("ERROR: thread has no dso for %#" PRIx64 "\n", *ip);
800 else
801 intel_pt_log("ERROR: thread has no map for %#" PRIx64 "\n", *ip);
802 return -EINVAL;
803 }
804
805 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR &&
806 dso__data_status_seen(al.map->dso,
807 DSO_DATA_STATUS_SEEN_ITRACE))
808 return -ENOENT;
809
810 offset = al.map->map_ip(al.map, *ip);
811
812 if (!to_ip && one_map) {
813 struct intel_pt_cache_entry *e;
814
815 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
816 if (e &&
817 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) {
818 *insn_cnt_ptr = e->insn_cnt;
819 *ip += e->byte_cnt;
820 intel_pt_insn->op = e->op;
821 intel_pt_insn->branch = e->branch;
822 intel_pt_insn->emulated_ptwrite = e->emulated_ptwrite;
823 intel_pt_insn->length = e->length;
824 intel_pt_insn->rel = e->rel;
825 memcpy(intel_pt_insn->buf, e->insn,
826 INTEL_PT_INSN_BUF_SZ);
827 intel_pt_log_insn_no_data(intel_pt_insn, *ip);
828 return 0;
829 }
830 }
831
832 start_offset = offset;
833 start_ip = *ip;
834
835 /* Load maps to ensure dso->is_64_bit has been updated */
836 map__load(al.map);
837
838 x86_64 = al.map->dso->is_64_bit;
839
840 while (1) {
841 len = dso__data_read_offset(al.map->dso, machine,
842 offset, buf,
843 INTEL_PT_INSN_BUF_SZ);
844 if (len <= 0) {
845 intel_pt_log("ERROR: failed to read at offset %#" PRIx64 " ",
846 offset);
847 if (intel_pt_enable_logging)
848 dso__fprintf(al.map->dso, intel_pt_log_fp());
849 return -EINVAL;
850 }
851
852 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn))
853 return -EINVAL;
854
855 intel_pt_log_insn(intel_pt_insn, *ip);
856
857 insn_cnt += 1;
858
859 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH) {
860 bool eptw;
861 u64 offs;
862
863 if (!intel_pt_jmp_16(intel_pt_insn))
864 goto out;
865 /* Check for emulated ptwrite */
866 offs = offset + intel_pt_insn->length;
867 eptw = intel_pt_emulated_ptwrite(al.map->dso, machine, offs);
868 intel_pt_insn->emulated_ptwrite = eptw;
869 goto out;
870 }
871
872 if (max_insn_cnt && insn_cnt >= max_insn_cnt)
873 goto out_no_cache;
874
875 *ip += intel_pt_insn->length;
876
877 if (to_ip && *ip == to_ip) {
878 intel_pt_insn->length = 0;
879 goto out_no_cache;
880 }
881
882 if (*ip >= al.map->end)
883 break;
884
885 offset += intel_pt_insn->length;
886 }
887 one_map = false;
888 }
889out:
890 *insn_cnt_ptr = insn_cnt;
891
892 if (!one_map)
893 goto out_no_cache;
894
895 /*
896 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate
897 * entries.
898 */
899 if (to_ip) {
900 struct intel_pt_cache_entry *e;
901
902 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset);
903 if (e)
904 return 0;
905 }
906
907 /* Ignore cache errors */
908 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt,
909 *ip - start_ip, intel_pt_insn);
910
911 return 0;
912
913out_no_cache:
914 *insn_cnt_ptr = insn_cnt;
915 return 0;
916}
917
918static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip,
919 uint64_t offset, const char *filename)
920{
921 struct addr_filter *filt;
922 bool have_filter = false;
923 bool hit_tracestop = false;
924 bool hit_filter = false;
925
926 list_for_each_entry(filt, &pt->filts.head, list) {
927 if (filt->start)
928 have_filter = true;
929
930 if ((filename && !filt->filename) ||
931 (!filename && filt->filename) ||
932 (filename && strcmp(filename, filt->filename)))
933 continue;
934
935 if (!(offset >= filt->addr && offset < filt->addr + filt->size))
936 continue;
937
938 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n",
939 ip, offset, filename ? filename : "[kernel]",
940 filt->start ? "filter" : "stop",
941 filt->addr, filt->size);
942
943 if (filt->start)
944 hit_filter = true;
945 else
946 hit_tracestop = true;
947 }
948
949 if (!hit_tracestop && !hit_filter)
950 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n",
951 ip, offset, filename ? filename : "[kernel]");
952
953 return hit_tracestop || (have_filter && !hit_filter);
954}
955
956static int __intel_pt_pgd_ip(uint64_t ip, void *data)
957{
958 struct intel_pt_queue *ptq = data;
959 struct thread *thread;
960 struct addr_location al;
961 u8 cpumode;
962 u64 offset;
963
964 if (ptq->state->to_nr) {
965 if (intel_pt_guest_kernel_ip(ip))
966 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
967 /* No support for decoding guest user space */
968 return -EINVAL;
969 } else if (ip >= ptq->pt->kernel_start) {
970 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL);
971 }
972
973 cpumode = PERF_RECORD_MISC_USER;
974
975 thread = ptq->thread;
976 if (!thread)
977 return -EINVAL;
978
979 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso)
980 return -EINVAL;
981
982 offset = al.map->map_ip(al.map, ip);
983
984 return intel_pt_match_pgd_ip(ptq->pt, ip, offset,
985 al.map->dso->long_name);
986}
987
988static bool intel_pt_pgd_ip(uint64_t ip, void *data)
989{
990 return __intel_pt_pgd_ip(ip, data) > 0;
991}
992
993static bool intel_pt_get_config(struct intel_pt *pt,
994 struct perf_event_attr *attr, u64 *config)
995{
996 if (attr->type == pt->pmu_type) {
997 if (config)
998 *config = attr->config;
999 return true;
1000 }
1001
1002 return false;
1003}
1004
1005static bool intel_pt_exclude_kernel(struct intel_pt *pt)
1006{
1007 struct evsel *evsel;
1008
1009 evlist__for_each_entry(pt->session->evlist, evsel) {
1010 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
1011 !evsel->core.attr.exclude_kernel)
1012 return false;
1013 }
1014 return true;
1015}
1016
1017static bool intel_pt_return_compression(struct intel_pt *pt)
1018{
1019 struct evsel *evsel;
1020 u64 config;
1021
1022 if (!pt->noretcomp_bit)
1023 return true;
1024
1025 evlist__for_each_entry(pt->session->evlist, evsel) {
1026 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
1027 (config & pt->noretcomp_bit))
1028 return false;
1029 }
1030 return true;
1031}
1032
1033static bool intel_pt_branch_enable(struct intel_pt *pt)
1034{
1035 struct evsel *evsel;
1036 u64 config;
1037
1038 evlist__for_each_entry(pt->session->evlist, evsel) {
1039 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
1040 (config & INTEL_PT_CFG_PASS_THRU) &&
1041 !(config & INTEL_PT_CFG_BRANCH_EN))
1042 return false;
1043 }
1044 return true;
1045}
1046
1047static bool intel_pt_disabled_tnt(struct intel_pt *pt)
1048{
1049 struct evsel *evsel;
1050 u64 config;
1051
1052 evlist__for_each_entry(pt->session->evlist, evsel) {
1053 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
1054 config & INTEL_PT_CFG_TNT_DIS)
1055 return true;
1056 }
1057 return false;
1058}
1059
1060static unsigned int intel_pt_mtc_period(struct intel_pt *pt)
1061{
1062 struct evsel *evsel;
1063 unsigned int shift;
1064 u64 config;
1065
1066 if (!pt->mtc_freq_bits)
1067 return 0;
1068
1069 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++)
1070 config >>= 1;
1071
1072 evlist__for_each_entry(pt->session->evlist, evsel) {
1073 if (intel_pt_get_config(pt, &evsel->core.attr, &config))
1074 return (config & pt->mtc_freq_bits) >> shift;
1075 }
1076 return 0;
1077}
1078
1079static bool intel_pt_timeless_decoding(struct intel_pt *pt)
1080{
1081 struct evsel *evsel;
1082 bool timeless_decoding = true;
1083 u64 config;
1084
1085 if (!pt->tsc_bit || !pt->cap_user_time_zero || pt->synth_opts.timeless_decoding)
1086 return true;
1087
1088 evlist__for_each_entry(pt->session->evlist, evsel) {
1089 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_TIME))
1090 return true;
1091 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
1092 if (config & pt->tsc_bit)
1093 timeless_decoding = false;
1094 else
1095 return true;
1096 }
1097 }
1098 return timeless_decoding;
1099}
1100
1101static bool intel_pt_tracing_kernel(struct intel_pt *pt)
1102{
1103 struct evsel *evsel;
1104
1105 evlist__for_each_entry(pt->session->evlist, evsel) {
1106 if (intel_pt_get_config(pt, &evsel->core.attr, NULL) &&
1107 !evsel->core.attr.exclude_kernel)
1108 return true;
1109 }
1110 return false;
1111}
1112
1113static bool intel_pt_have_tsc(struct intel_pt *pt)
1114{
1115 struct evsel *evsel;
1116 bool have_tsc = false;
1117 u64 config;
1118
1119 if (!pt->tsc_bit)
1120 return false;
1121
1122 evlist__for_each_entry(pt->session->evlist, evsel) {
1123 if (intel_pt_get_config(pt, &evsel->core.attr, &config)) {
1124 if (config & pt->tsc_bit)
1125 have_tsc = true;
1126 else
1127 return false;
1128 }
1129 }
1130 return have_tsc;
1131}
1132
1133static bool intel_pt_have_mtc(struct intel_pt *pt)
1134{
1135 struct evsel *evsel;
1136 u64 config;
1137
1138 evlist__for_each_entry(pt->session->evlist, evsel) {
1139 if (intel_pt_get_config(pt, &evsel->core.attr, &config) &&
1140 (config & pt->mtc_bit))
1141 return true;
1142 }
1143 return false;
1144}
1145
1146static bool intel_pt_sampling_mode(struct intel_pt *pt)
1147{
1148 struct evsel *evsel;
1149
1150 evlist__for_each_entry(pt->session->evlist, evsel) {
1151 if ((evsel->core.attr.sample_type & PERF_SAMPLE_AUX) &&
1152 evsel->core.attr.aux_sample_size)
1153 return true;
1154 }
1155 return false;
1156}
1157
1158static u64 intel_pt_ctl(struct intel_pt *pt)
1159{
1160 struct evsel *evsel;
1161 u64 config;
1162
1163 evlist__for_each_entry(pt->session->evlist, evsel) {
1164 if (intel_pt_get_config(pt, &evsel->core.attr, &config))
1165 return config;
1166 }
1167 return 0;
1168}
1169
1170static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns)
1171{
1172 u64 quot, rem;
1173
1174 quot = ns / pt->tc.time_mult;
1175 rem = ns % pt->tc.time_mult;
1176 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) /
1177 pt->tc.time_mult;
1178}
1179
1180static struct ip_callchain *intel_pt_alloc_chain(struct intel_pt *pt)
1181{
1182 size_t sz = sizeof(struct ip_callchain);
1183
1184 /* Add 1 to callchain_sz for callchain context */
1185 sz += (pt->synth_opts.callchain_sz + 1) * sizeof(u64);
1186 return zalloc(sz);
1187}
1188
1189static int intel_pt_callchain_init(struct intel_pt *pt)
1190{
1191 struct evsel *evsel;
1192
1193 evlist__for_each_entry(pt->session->evlist, evsel) {
1194 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_CALLCHAIN))
1195 evsel->synth_sample_type |= PERF_SAMPLE_CALLCHAIN;
1196 }
1197
1198 pt->chain = intel_pt_alloc_chain(pt);
1199 if (!pt->chain)
1200 return -ENOMEM;
1201
1202 return 0;
1203}
1204
1205static void intel_pt_add_callchain(struct intel_pt *pt,
1206 struct perf_sample *sample)
1207{
1208 struct thread *thread = machine__findnew_thread(pt->machine,
1209 sample->pid,
1210 sample->tid);
1211
1212 thread_stack__sample_late(thread, sample->cpu, pt->chain,
1213 pt->synth_opts.callchain_sz + 1, sample->ip,
1214 pt->kernel_start);
1215
1216 sample->callchain = pt->chain;
1217}
1218
1219static struct branch_stack *intel_pt_alloc_br_stack(unsigned int entry_cnt)
1220{
1221 size_t sz = sizeof(struct branch_stack);
1222
1223 sz += entry_cnt * sizeof(struct branch_entry);
1224 return zalloc(sz);
1225}
1226
1227static int intel_pt_br_stack_init(struct intel_pt *pt)
1228{
1229 struct evsel *evsel;
1230
1231 evlist__for_each_entry(pt->session->evlist, evsel) {
1232 if (!(evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK))
1233 evsel->synth_sample_type |= PERF_SAMPLE_BRANCH_STACK;
1234 }
1235
1236 pt->br_stack = intel_pt_alloc_br_stack(pt->br_stack_sz);
1237 if (!pt->br_stack)
1238 return -ENOMEM;
1239
1240 return 0;
1241}
1242
1243static void intel_pt_add_br_stack(struct intel_pt *pt,
1244 struct perf_sample *sample)
1245{
1246 struct thread *thread = machine__findnew_thread(pt->machine,
1247 sample->pid,
1248 sample->tid);
1249
1250 thread_stack__br_sample_late(thread, sample->cpu, pt->br_stack,
1251 pt->br_stack_sz, sample->ip,
1252 pt->kernel_start);
1253
1254 sample->branch_stack = pt->br_stack;
1255}
1256
1257/* INTEL_PT_LBR_0, INTEL_PT_LBR_1 and INTEL_PT_LBR_2 */
1258#define LBRS_MAX (INTEL_PT_BLK_ITEM_ID_CNT * 3U)
1259
1260static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt,
1261 unsigned int queue_nr)
1262{
1263 struct intel_pt_params params = { .get_trace = 0, };
1264 struct perf_env *env = pt->machine->env;
1265 struct intel_pt_queue *ptq;
1266
1267 ptq = zalloc(sizeof(struct intel_pt_queue));
1268 if (!ptq)
1269 return NULL;
1270
1271 if (pt->synth_opts.callchain) {
1272 ptq->chain = intel_pt_alloc_chain(pt);
1273 if (!ptq->chain)
1274 goto out_free;
1275 }
1276
1277 if (pt->synth_opts.last_branch || pt->synth_opts.other_events) {
1278 unsigned int entry_cnt = max(LBRS_MAX, pt->br_stack_sz);
1279
1280 ptq->last_branch = intel_pt_alloc_br_stack(entry_cnt);
1281 if (!ptq->last_branch)
1282 goto out_free;
1283 }
1284
1285 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE);
1286 if (!ptq->event_buf)
1287 goto out_free;
1288
1289 ptq->pt = pt;
1290 ptq->queue_nr = queue_nr;
1291 ptq->exclude_kernel = intel_pt_exclude_kernel(pt);
1292 ptq->pid = -1;
1293 ptq->tid = -1;
1294 ptq->cpu = -1;
1295 ptq->next_tid = -1;
1296
1297 params.get_trace = intel_pt_get_trace;
1298 params.walk_insn = intel_pt_walk_next_insn;
1299 params.lookahead = intel_pt_lookahead;
1300 params.findnew_vmcs_info = intel_pt_findnew_vmcs_info;
1301 params.data = ptq;
1302 params.return_compression = intel_pt_return_compression(pt);
1303 params.branch_enable = intel_pt_branch_enable(pt);
1304 params.ctl = intel_pt_ctl(pt);
1305 params.max_non_turbo_ratio = pt->max_non_turbo_ratio;
1306 params.mtc_period = intel_pt_mtc_period(pt);
1307 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n;
1308 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d;
1309 params.quick = pt->synth_opts.quick;
1310 params.vm_time_correlation = pt->synth_opts.vm_time_correlation;
1311 params.vm_tm_corr_dry_run = pt->synth_opts.vm_tm_corr_dry_run;
1312 params.first_timestamp = pt->first_timestamp;
1313 params.max_loops = pt->max_loops;
1314
1315 /* Cannot walk code without TNT, so force 'quick' mode */
1316 if (params.branch_enable && intel_pt_disabled_tnt(pt) && !params.quick)
1317 params.quick = 1;
1318
1319 if (pt->filts.cnt > 0)
1320 params.pgd_ip = intel_pt_pgd_ip;
1321
1322 if (pt->synth_opts.instructions) {
1323 if (pt->synth_opts.period) {
1324 switch (pt->synth_opts.period_type) {
1325 case PERF_ITRACE_PERIOD_INSTRUCTIONS:
1326 params.period_type =
1327 INTEL_PT_PERIOD_INSTRUCTIONS;
1328 params.period = pt->synth_opts.period;
1329 break;
1330 case PERF_ITRACE_PERIOD_TICKS:
1331 params.period_type = INTEL_PT_PERIOD_TICKS;
1332 params.period = pt->synth_opts.period;
1333 break;
1334 case PERF_ITRACE_PERIOD_NANOSECS:
1335 params.period_type = INTEL_PT_PERIOD_TICKS;
1336 params.period = intel_pt_ns_to_ticks(pt,
1337 pt->synth_opts.period);
1338 break;
1339 default:
1340 break;
1341 }
1342 }
1343
1344 if (!params.period) {
1345 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS;
1346 params.period = 1;
1347 }
1348 }
1349
1350 if (env->cpuid && !strncmp(env->cpuid, "GenuineIntel,6,92,", 18))
1351 params.flags |= INTEL_PT_FUP_WITH_NLIP;
1352
1353 ptq->decoder = intel_pt_decoder_new(¶ms);
1354 if (!ptq->decoder)
1355 goto out_free;
1356
1357 return ptq;
1358
1359out_free:
1360 zfree(&ptq->event_buf);
1361 zfree(&ptq->last_branch);
1362 zfree(&ptq->chain);
1363 free(ptq);
1364 return NULL;
1365}
1366
1367static void intel_pt_free_queue(void *priv)
1368{
1369 struct intel_pt_queue *ptq = priv;
1370
1371 if (!ptq)
1372 return;
1373 thread__zput(ptq->thread);
1374 thread__zput(ptq->guest_thread);
1375 thread__zput(ptq->unknown_guest_thread);
1376 intel_pt_decoder_free(ptq->decoder);
1377 zfree(&ptq->event_buf);
1378 zfree(&ptq->last_branch);
1379 zfree(&ptq->chain);
1380 free(ptq);
1381}
1382
1383static void intel_pt_first_timestamp(struct intel_pt *pt, u64 timestamp)
1384{
1385 unsigned int i;
1386
1387 pt->first_timestamp = timestamp;
1388
1389 for (i = 0; i < pt->queues.nr_queues; i++) {
1390 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
1391 struct intel_pt_queue *ptq = queue->priv;
1392
1393 if (ptq && ptq->decoder)
1394 intel_pt_set_first_timestamp(ptq->decoder, timestamp);
1395 }
1396}
1397
1398static int intel_pt_get_guest_from_sideband(struct intel_pt_queue *ptq)
1399{
1400 struct machines *machines = &ptq->pt->session->machines;
1401 struct machine *machine;
1402 pid_t machine_pid = ptq->pid;
1403 pid_t tid;
1404 int vcpu;
1405
1406 if (machine_pid <= 0)
1407 return 0; /* Not a guest machine */
1408
1409 machine = machines__find(machines, machine_pid);
1410 if (!machine)
1411 return 0; /* Not a guest machine */
1412
1413 if (ptq->guest_machine != machine) {
1414 ptq->guest_machine = NULL;
1415 thread__zput(ptq->guest_thread);
1416 thread__zput(ptq->unknown_guest_thread);
1417
1418 ptq->unknown_guest_thread = machine__find_thread(machine, 0, 0);
1419 if (!ptq->unknown_guest_thread)
1420 return -1;
1421 ptq->guest_machine = machine;
1422 }
1423
1424 vcpu = ptq->thread ? ptq->thread->guest_cpu : -1;
1425 if (vcpu < 0)
1426 return -1;
1427
1428 tid = machine__get_current_tid(machine, vcpu);
1429
1430 if (ptq->guest_thread && ptq->guest_thread->tid != tid)
1431 thread__zput(ptq->guest_thread);
1432
1433 if (!ptq->guest_thread) {
1434 ptq->guest_thread = machine__find_thread(machine, -1, tid);
1435 if (!ptq->guest_thread)
1436 return -1;
1437 }
1438
1439 ptq->guest_machine_pid = machine_pid;
1440 ptq->guest_pid = ptq->guest_thread->pid_;
1441 ptq->guest_tid = tid;
1442 ptq->vcpu = vcpu;
1443
1444 return 0;
1445}
1446
1447static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt,
1448 struct auxtrace_queue *queue)
1449{
1450 struct intel_pt_queue *ptq = queue->priv;
1451
1452 if (queue->tid == -1 || pt->have_sched_switch) {
1453 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu);
1454 if (ptq->tid == -1)
1455 ptq->pid = -1;
1456 thread__zput(ptq->thread);
1457 }
1458
1459 if (!ptq->thread && ptq->tid != -1)
1460 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid);
1461
1462 if (ptq->thread) {
1463 ptq->pid = ptq->thread->pid_;
1464 if (queue->cpu == -1)
1465 ptq->cpu = ptq->thread->cpu;
1466 }
1467
1468 if (pt->have_guest_sideband && intel_pt_get_guest_from_sideband(ptq)) {
1469 ptq->guest_machine_pid = 0;
1470 ptq->guest_pid = -1;
1471 ptq->guest_tid = -1;
1472 ptq->vcpu = -1;
1473 }
1474}
1475
1476static void intel_pt_sample_flags(struct intel_pt_queue *ptq)
1477{
1478 struct intel_pt *pt = ptq->pt;
1479
1480 ptq->insn_len = 0;
1481 if (ptq->state->flags & INTEL_PT_ABORT_TX) {
1482 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT;
1483 } else if (ptq->state->flags & INTEL_PT_ASYNC) {
1484 if (!ptq->state->to_ip)
1485 ptq->flags = PERF_IP_FLAG_BRANCH |
1486 PERF_IP_FLAG_TRACE_END;
1487 else if (ptq->state->from_nr && !ptq->state->to_nr)
1488 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
1489 PERF_IP_FLAG_VMEXIT;
1490 else
1491 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL |
1492 PERF_IP_FLAG_ASYNC |
1493 PERF_IP_FLAG_INTERRUPT;
1494 } else {
1495 if (ptq->state->from_ip)
1496 ptq->flags = intel_pt_insn_type(ptq->state->insn_op);
1497 else
1498 ptq->flags = PERF_IP_FLAG_BRANCH |
1499 PERF_IP_FLAG_TRACE_BEGIN;
1500 if (ptq->state->flags & INTEL_PT_IN_TX)
1501 ptq->flags |= PERF_IP_FLAG_IN_TX;
1502 ptq->insn_len = ptq->state->insn_len;
1503 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ);
1504 }
1505
1506 if (ptq->state->type & INTEL_PT_TRACE_BEGIN)
1507 ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN;
1508 if (ptq->state->type & INTEL_PT_TRACE_END)
1509 ptq->flags |= PERF_IP_FLAG_TRACE_END;
1510
1511 if (pt->cap_event_trace) {
1512 if (ptq->state->type & INTEL_PT_IFLAG_CHG) {
1513 if (!ptq->state->from_iflag)
1514 ptq->flags |= PERF_IP_FLAG_INTR_DISABLE;
1515 if (ptq->state->from_iflag != ptq->state->to_iflag)
1516 ptq->flags |= PERF_IP_FLAG_INTR_TOGGLE;
1517 } else if (!ptq->state->to_iflag) {
1518 ptq->flags |= PERF_IP_FLAG_INTR_DISABLE;
1519 }
1520 }
1521}
1522
1523static void intel_pt_setup_time_range(struct intel_pt *pt,
1524 struct intel_pt_queue *ptq)
1525{
1526 if (!pt->range_cnt)
1527 return;
1528
1529 ptq->sel_timestamp = pt->time_ranges[0].start;
1530 ptq->sel_idx = 0;
1531
1532 if (ptq->sel_timestamp) {
1533 ptq->sel_start = true;
1534 } else {
1535 ptq->sel_timestamp = pt->time_ranges[0].end;
1536 ptq->sel_start = false;
1537 }
1538}
1539
1540static int intel_pt_setup_queue(struct intel_pt *pt,
1541 struct auxtrace_queue *queue,
1542 unsigned int queue_nr)
1543{
1544 struct intel_pt_queue *ptq = queue->priv;
1545
1546 if (list_empty(&queue->head))
1547 return 0;
1548
1549 if (!ptq) {
1550 ptq = intel_pt_alloc_queue(pt, queue_nr);
1551 if (!ptq)
1552 return -ENOMEM;
1553 queue->priv = ptq;
1554
1555 if (queue->cpu != -1)
1556 ptq->cpu = queue->cpu;
1557 ptq->tid = queue->tid;
1558
1559 ptq->cbr_seen = UINT_MAX;
1560
1561 if (pt->sampling_mode && !pt->snapshot_mode &&
1562 pt->timeless_decoding)
1563 ptq->step_through_buffers = true;
1564
1565 ptq->sync_switch = pt->sync_switch;
1566
1567 intel_pt_setup_time_range(pt, ptq);
1568 }
1569
1570 if (!ptq->on_heap &&
1571 (!ptq->sync_switch ||
1572 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) {
1573 const struct intel_pt_state *state;
1574 int ret;
1575
1576 if (pt->timeless_decoding)
1577 return 0;
1578
1579 intel_pt_log("queue %u getting timestamp\n", queue_nr);
1580 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
1581 queue_nr, ptq->cpu, ptq->pid, ptq->tid);
1582
1583 if (ptq->sel_start && ptq->sel_timestamp) {
1584 ret = intel_pt_fast_forward(ptq->decoder,
1585 ptq->sel_timestamp);
1586 if (ret)
1587 return ret;
1588 }
1589
1590 while (1) {
1591 state = intel_pt_decode(ptq->decoder);
1592 if (state->err) {
1593 if (state->err == INTEL_PT_ERR_NODATA) {
1594 intel_pt_log("queue %u has no timestamp\n",
1595 queue_nr);
1596 return 0;
1597 }
1598 continue;
1599 }
1600 if (state->timestamp)
1601 break;
1602 }
1603
1604 ptq->timestamp = state->timestamp;
1605 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n",
1606 queue_nr, ptq->timestamp);
1607 ptq->state = state;
1608 ptq->have_sample = true;
1609 if (ptq->sel_start && ptq->sel_timestamp &&
1610 ptq->timestamp < ptq->sel_timestamp)
1611 ptq->have_sample = false;
1612 intel_pt_sample_flags(ptq);
1613 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp);
1614 if (ret)
1615 return ret;
1616 ptq->on_heap = true;
1617 }
1618
1619 return 0;
1620}
1621
1622static int intel_pt_setup_queues(struct intel_pt *pt)
1623{
1624 unsigned int i;
1625 int ret;
1626
1627 for (i = 0; i < pt->queues.nr_queues; i++) {
1628 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i);
1629 if (ret)
1630 return ret;
1631 }
1632 return 0;
1633}
1634
1635static inline bool intel_pt_skip_event(struct intel_pt *pt)
1636{
1637 return pt->synth_opts.initial_skip &&
1638 pt->num_events++ < pt->synth_opts.initial_skip;
1639}
1640
1641/*
1642 * Cannot count CBR as skipped because it won't go away until cbr == cbr_seen.
1643 * Also ensure CBR is first non-skipped event by allowing for 4 more samples
1644 * from this decoder state.
1645 */
1646static inline bool intel_pt_skip_cbr_event(struct intel_pt *pt)
1647{
1648 return pt->synth_opts.initial_skip &&
1649 pt->num_events + 4 < pt->synth_opts.initial_skip;
1650}
1651
1652static void intel_pt_prep_a_sample(struct intel_pt_queue *ptq,
1653 union perf_event *event,
1654 struct perf_sample *sample)
1655{
1656 event->sample.header.type = PERF_RECORD_SAMPLE;
1657 event->sample.header.size = sizeof(struct perf_event_header);
1658
1659 sample->pid = ptq->pid;
1660 sample->tid = ptq->tid;
1661
1662 if (ptq->pt->have_guest_sideband) {
1663 if ((ptq->state->from_ip && ptq->state->from_nr) ||
1664 (ptq->state->to_ip && ptq->state->to_nr)) {
1665 sample->pid = ptq->guest_pid;
1666 sample->tid = ptq->guest_tid;
1667 sample->machine_pid = ptq->guest_machine_pid;
1668 sample->vcpu = ptq->vcpu;
1669 }
1670 }
1671
1672 sample->cpu = ptq->cpu;
1673 sample->insn_len = ptq->insn_len;
1674 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ);
1675}
1676
1677static void intel_pt_prep_b_sample(struct intel_pt *pt,
1678 struct intel_pt_queue *ptq,
1679 union perf_event *event,
1680 struct perf_sample *sample)
1681{
1682 intel_pt_prep_a_sample(ptq, event, sample);
1683
1684 if (!pt->timeless_decoding)
1685 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc);
1686
1687 sample->ip = ptq->state->from_ip;
1688 sample->addr = ptq->state->to_ip;
1689 sample->cpumode = intel_pt_cpumode(ptq, sample->ip, sample->addr);
1690 sample->period = 1;
1691 sample->flags = ptq->flags;
1692
1693 event->sample.header.misc = sample->cpumode;
1694}
1695
1696static int intel_pt_inject_event(union perf_event *event,
1697 struct perf_sample *sample, u64 type)
1698{
1699 event->header.size = perf_event__sample_event_size(sample, type, 0);
1700 return perf_event__synthesize_sample(event, type, 0, sample);
1701}
1702
1703static inline int intel_pt_opt_inject(struct intel_pt *pt,
1704 union perf_event *event,
1705 struct perf_sample *sample, u64 type)
1706{
1707 if (!pt->synth_opts.inject)
1708 return 0;
1709
1710 return intel_pt_inject_event(event, sample, type);
1711}
1712
1713static int intel_pt_deliver_synth_event(struct intel_pt *pt,
1714 union perf_event *event,
1715 struct perf_sample *sample, u64 type)
1716{
1717 int ret;
1718
1719 ret = intel_pt_opt_inject(pt, event, sample, type);
1720 if (ret)
1721 return ret;
1722
1723 ret = perf_session__deliver_synth_event(pt->session, event, sample);
1724 if (ret)
1725 pr_err("Intel PT: failed to deliver event, error %d\n", ret);
1726
1727 return ret;
1728}
1729
1730static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq)
1731{
1732 struct intel_pt *pt = ptq->pt;
1733 union perf_event *event = ptq->event_buf;
1734 struct perf_sample sample = { .ip = 0, };
1735 struct dummy_branch_stack {
1736 u64 nr;
1737 u64 hw_idx;
1738 struct branch_entry entries;
1739 } dummy_bs;
1740
1741 if (pt->branches_filter && !(pt->branches_filter & ptq->flags))
1742 return 0;
1743
1744 if (intel_pt_skip_event(pt))
1745 return 0;
1746
1747 intel_pt_prep_b_sample(pt, ptq, event, &sample);
1748
1749 sample.id = ptq->pt->branches_id;
1750 sample.stream_id = ptq->pt->branches_id;
1751
1752 /*
1753 * perf report cannot handle events without a branch stack when using
1754 * SORT_MODE__BRANCH so make a dummy one.
1755 */
1756 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) {
1757 dummy_bs = (struct dummy_branch_stack){
1758 .nr = 1,
1759 .hw_idx = -1ULL,
1760 .entries = {
1761 .from = sample.ip,
1762 .to = sample.addr,
1763 },
1764 };
1765 sample.branch_stack = (struct branch_stack *)&dummy_bs;
1766 }
1767
1768 if (ptq->sample_ipc)
1769 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_br_cyc_cnt;
1770 if (sample.cyc_cnt) {
1771 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_br_insn_cnt;
1772 ptq->last_br_insn_cnt = ptq->ipc_insn_cnt;
1773 ptq->last_br_cyc_cnt = ptq->ipc_cyc_cnt;
1774 }
1775
1776 return intel_pt_deliver_synth_event(pt, event, &sample,
1777 pt->branches_sample_type);
1778}
1779
1780static void intel_pt_prep_sample(struct intel_pt *pt,
1781 struct intel_pt_queue *ptq,
1782 union perf_event *event,
1783 struct perf_sample *sample)
1784{
1785 intel_pt_prep_b_sample(pt, ptq, event, sample);
1786
1787 if (pt->synth_opts.callchain) {
1788 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
1789 pt->synth_opts.callchain_sz + 1,
1790 sample->ip, pt->kernel_start);
1791 sample->callchain = ptq->chain;
1792 }
1793
1794 if (pt->synth_opts.last_branch) {
1795 thread_stack__br_sample(ptq->thread, ptq->cpu, ptq->last_branch,
1796 pt->br_stack_sz);
1797 sample->branch_stack = ptq->last_branch;
1798 }
1799}
1800
1801static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq)
1802{
1803 struct intel_pt *pt = ptq->pt;
1804 union perf_event *event = ptq->event_buf;
1805 struct perf_sample sample = { .ip = 0, };
1806
1807 if (intel_pt_skip_event(pt))
1808 return 0;
1809
1810 intel_pt_prep_sample(pt, ptq, event, &sample);
1811
1812 sample.id = ptq->pt->instructions_id;
1813 sample.stream_id = ptq->pt->instructions_id;
1814 if (pt->synth_opts.quick)
1815 sample.period = 1;
1816 else
1817 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt;
1818
1819 if (ptq->sample_ipc)
1820 sample.cyc_cnt = ptq->ipc_cyc_cnt - ptq->last_in_cyc_cnt;
1821 if (sample.cyc_cnt) {
1822 sample.insn_cnt = ptq->ipc_insn_cnt - ptq->last_in_insn_cnt;
1823 ptq->last_in_insn_cnt = ptq->ipc_insn_cnt;
1824 ptq->last_in_cyc_cnt = ptq->ipc_cyc_cnt;
1825 }
1826
1827 ptq->last_insn_cnt = ptq->state->tot_insn_cnt;
1828
1829 return intel_pt_deliver_synth_event(pt, event, &sample,
1830 pt->instructions_sample_type);
1831}
1832
1833static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq)
1834{
1835 struct intel_pt *pt = ptq->pt;
1836 union perf_event *event = ptq->event_buf;
1837 struct perf_sample sample = { .ip = 0, };
1838
1839 if (intel_pt_skip_event(pt))
1840 return 0;
1841
1842 intel_pt_prep_sample(pt, ptq, event, &sample);
1843
1844 sample.id = ptq->pt->transactions_id;
1845 sample.stream_id = ptq->pt->transactions_id;
1846
1847 return intel_pt_deliver_synth_event(pt, event, &sample,
1848 pt->transactions_sample_type);
1849}
1850
1851static void intel_pt_prep_p_sample(struct intel_pt *pt,
1852 struct intel_pt_queue *ptq,
1853 union perf_event *event,
1854 struct perf_sample *sample)
1855{
1856 intel_pt_prep_sample(pt, ptq, event, sample);
1857
1858 /*
1859 * Zero IP is used to mean "trace start" but that is not the case for
1860 * power or PTWRITE events with no IP, so clear the flags.
1861 */
1862 if (!sample->ip)
1863 sample->flags = 0;
1864}
1865
1866static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq)
1867{
1868 struct intel_pt *pt = ptq->pt;
1869 union perf_event *event = ptq->event_buf;
1870 struct perf_sample sample = { .ip = 0, };
1871 struct perf_synth_intel_ptwrite raw;
1872
1873 if (intel_pt_skip_event(pt))
1874 return 0;
1875
1876 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1877
1878 sample.id = ptq->pt->ptwrites_id;
1879 sample.stream_id = ptq->pt->ptwrites_id;
1880
1881 raw.flags = 0;
1882 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
1883 raw.payload = cpu_to_le64(ptq->state->ptw_payload);
1884
1885 sample.raw_size = perf_synth__raw_size(raw);
1886 sample.raw_data = perf_synth__raw_data(&raw);
1887
1888 return intel_pt_deliver_synth_event(pt, event, &sample,
1889 pt->ptwrites_sample_type);
1890}
1891
1892static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq)
1893{
1894 struct intel_pt *pt = ptq->pt;
1895 union perf_event *event = ptq->event_buf;
1896 struct perf_sample sample = { .ip = 0, };
1897 struct perf_synth_intel_cbr raw;
1898 u32 flags;
1899
1900 if (intel_pt_skip_cbr_event(pt))
1901 return 0;
1902
1903 ptq->cbr_seen = ptq->state->cbr;
1904
1905 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1906
1907 sample.id = ptq->pt->cbr_id;
1908 sample.stream_id = ptq->pt->cbr_id;
1909
1910 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16);
1911 raw.flags = cpu_to_le32(flags);
1912 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz);
1913 raw.reserved3 = 0;
1914
1915 sample.raw_size = perf_synth__raw_size(raw);
1916 sample.raw_data = perf_synth__raw_data(&raw);
1917
1918 return intel_pt_deliver_synth_event(pt, event, &sample,
1919 pt->pwr_events_sample_type);
1920}
1921
1922static int intel_pt_synth_psb_sample(struct intel_pt_queue *ptq)
1923{
1924 struct intel_pt *pt = ptq->pt;
1925 union perf_event *event = ptq->event_buf;
1926 struct perf_sample sample = { .ip = 0, };
1927 struct perf_synth_intel_psb raw;
1928
1929 if (intel_pt_skip_event(pt))
1930 return 0;
1931
1932 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1933
1934 sample.id = ptq->pt->psb_id;
1935 sample.stream_id = ptq->pt->psb_id;
1936 sample.flags = 0;
1937
1938 raw.reserved = 0;
1939 raw.offset = ptq->state->psb_offset;
1940
1941 sample.raw_size = perf_synth__raw_size(raw);
1942 sample.raw_data = perf_synth__raw_data(&raw);
1943
1944 return intel_pt_deliver_synth_event(pt, event, &sample,
1945 pt->pwr_events_sample_type);
1946}
1947
1948static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq)
1949{
1950 struct intel_pt *pt = ptq->pt;
1951 union perf_event *event = ptq->event_buf;
1952 struct perf_sample sample = { .ip = 0, };
1953 struct perf_synth_intel_mwait raw;
1954
1955 if (intel_pt_skip_event(pt))
1956 return 0;
1957
1958 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1959
1960 sample.id = ptq->pt->mwait_id;
1961 sample.stream_id = ptq->pt->mwait_id;
1962
1963 raw.reserved = 0;
1964 raw.payload = cpu_to_le64(ptq->state->mwait_payload);
1965
1966 sample.raw_size = perf_synth__raw_size(raw);
1967 sample.raw_data = perf_synth__raw_data(&raw);
1968
1969 return intel_pt_deliver_synth_event(pt, event, &sample,
1970 pt->pwr_events_sample_type);
1971}
1972
1973static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq)
1974{
1975 struct intel_pt *pt = ptq->pt;
1976 union perf_event *event = ptq->event_buf;
1977 struct perf_sample sample = { .ip = 0, };
1978 struct perf_synth_intel_pwre raw;
1979
1980 if (intel_pt_skip_event(pt))
1981 return 0;
1982
1983 intel_pt_prep_p_sample(pt, ptq, event, &sample);
1984
1985 sample.id = ptq->pt->pwre_id;
1986 sample.stream_id = ptq->pt->pwre_id;
1987
1988 raw.reserved = 0;
1989 raw.payload = cpu_to_le64(ptq->state->pwre_payload);
1990
1991 sample.raw_size = perf_synth__raw_size(raw);
1992 sample.raw_data = perf_synth__raw_data(&raw);
1993
1994 return intel_pt_deliver_synth_event(pt, event, &sample,
1995 pt->pwr_events_sample_type);
1996}
1997
1998static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq)
1999{
2000 struct intel_pt *pt = ptq->pt;
2001 union perf_event *event = ptq->event_buf;
2002 struct perf_sample sample = { .ip = 0, };
2003 struct perf_synth_intel_exstop raw;
2004
2005 if (intel_pt_skip_event(pt))
2006 return 0;
2007
2008 intel_pt_prep_p_sample(pt, ptq, event, &sample);
2009
2010 sample.id = ptq->pt->exstop_id;
2011 sample.stream_id = ptq->pt->exstop_id;
2012
2013 raw.flags = 0;
2014 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
2015
2016 sample.raw_size = perf_synth__raw_size(raw);
2017 sample.raw_data = perf_synth__raw_data(&raw);
2018
2019 return intel_pt_deliver_synth_event(pt, event, &sample,
2020 pt->pwr_events_sample_type);
2021}
2022
2023static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
2024{
2025 struct intel_pt *pt = ptq->pt;
2026 union perf_event *event = ptq->event_buf;
2027 struct perf_sample sample = { .ip = 0, };
2028 struct perf_synth_intel_pwrx raw;
2029
2030 if (intel_pt_skip_event(pt))
2031 return 0;
2032
2033 intel_pt_prep_p_sample(pt, ptq, event, &sample);
2034
2035 sample.id = ptq->pt->pwrx_id;
2036 sample.stream_id = ptq->pt->pwrx_id;
2037
2038 raw.reserved = 0;
2039 raw.payload = cpu_to_le64(ptq->state->pwrx_payload);
2040
2041 sample.raw_size = perf_synth__raw_size(raw);
2042 sample.raw_data = perf_synth__raw_data(&raw);
2043
2044 return intel_pt_deliver_synth_event(pt, event, &sample,
2045 pt->pwr_events_sample_type);
2046}
2047
2048/*
2049 * PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer
2050 * intel_pt_add_gp_regs().
2051 */
2052static const int pebs_gp_regs[] = {
2053 [PERF_REG_X86_FLAGS] = 1,
2054 [PERF_REG_X86_IP] = 2,
2055 [PERF_REG_X86_AX] = 3,
2056 [PERF_REG_X86_CX] = 4,
2057 [PERF_REG_X86_DX] = 5,
2058 [PERF_REG_X86_BX] = 6,
2059 [PERF_REG_X86_SP] = 7,
2060 [PERF_REG_X86_BP] = 8,
2061 [PERF_REG_X86_SI] = 9,
2062 [PERF_REG_X86_DI] = 10,
2063 [PERF_REG_X86_R8] = 11,
2064 [PERF_REG_X86_R9] = 12,
2065 [PERF_REG_X86_R10] = 13,
2066 [PERF_REG_X86_R11] = 14,
2067 [PERF_REG_X86_R12] = 15,
2068 [PERF_REG_X86_R13] = 16,
2069 [PERF_REG_X86_R14] = 17,
2070 [PERF_REG_X86_R15] = 18,
2071};
2072
2073static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
2074 const struct intel_pt_blk_items *items,
2075 u64 regs_mask)
2076{
2077 const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
2078 u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
2079 u32 bit;
2080 int i;
2081
2082 for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
2083 /* Get the PEBS gp_regs array index */
2084 int n = pebs_gp_regs[i] - 1;
2085
2086 if (n < 0)
2087 continue;
2088 /*
2089 * Add only registers that were requested (i.e. 'regs_mask') and
2090 * that were provided (i.e. 'mask'), and update the resulting
2091 * mask (i.e. 'intr_regs->mask') accordingly.
2092 */
2093 if (mask & 1 << n && regs_mask & bit) {
2094 intr_regs->mask |= bit;
2095 *pos++ = gp_regs[n];
2096 }
2097 }
2098
2099 return pos;
2100}
2101
2102#ifndef PERF_REG_X86_XMM0
2103#define PERF_REG_X86_XMM0 32
2104#endif
2105
2106static void intel_pt_add_xmm(struct regs_dump *intr_regs, u64 *pos,
2107 const struct intel_pt_blk_items *items,
2108 u64 regs_mask)
2109{
2110 u32 mask = items->has_xmm & (regs_mask >> PERF_REG_X86_XMM0);
2111 const u64 *xmm = items->xmm;
2112
2113 /*
2114 * If there are any XMM registers, then there should be all of them.
2115 * Nevertheless, follow the logic to add only registers that were
2116 * requested (i.e. 'regs_mask') and that were provided (i.e. 'mask'),
2117 * and update the resulting mask (i.e. 'intr_regs->mask') accordingly.
2118 */
2119 intr_regs->mask |= (u64)mask << PERF_REG_X86_XMM0;
2120
2121 for (; mask; mask >>= 1, xmm++) {
2122 if (mask & 1)
2123 *pos++ = *xmm;
2124 }
2125}
2126
2127#define LBR_INFO_MISPRED (1ULL << 63)
2128#define LBR_INFO_IN_TX (1ULL << 62)
2129#define LBR_INFO_ABORT (1ULL << 61)
2130#define LBR_INFO_CYCLES 0xffff
2131
2132/* Refer kernel's intel_pmu_store_pebs_lbrs() */
2133static u64 intel_pt_lbr_flags(u64 info)
2134{
2135 union {
2136 struct branch_flags flags;
2137 u64 result;
2138 } u;
2139
2140 u.result = 0;
2141 u.flags.mispred = !!(info & LBR_INFO_MISPRED);
2142 u.flags.predicted = !(info & LBR_INFO_MISPRED);
2143 u.flags.in_tx = !!(info & LBR_INFO_IN_TX);
2144 u.flags.abort = !!(info & LBR_INFO_ABORT);
2145 u.flags.cycles = info & LBR_INFO_CYCLES;
2146
2147 return u.result;
2148}
2149
2150static void intel_pt_add_lbrs(struct branch_stack *br_stack,
2151 const struct intel_pt_blk_items *items)
2152{
2153 u64 *to;
2154 int i;
2155
2156 br_stack->nr = 0;
2157
2158 to = &br_stack->entries[0].from;
2159
2160 for (i = INTEL_PT_LBR_0_POS; i <= INTEL_PT_LBR_2_POS; i++) {
2161 u32 mask = items->mask[i];
2162 const u64 *from = items->val[i];
2163
2164 for (; mask; mask >>= 3, from += 3) {
2165 if ((mask & 7) == 7) {
2166 *to++ = from[0];
2167 *to++ = from[1];
2168 *to++ = intel_pt_lbr_flags(from[2]);
2169 br_stack->nr += 1;
2170 }
2171 }
2172 }
2173}
2174
2175static int intel_pt_do_synth_pebs_sample(struct intel_pt_queue *ptq, struct evsel *evsel, u64 id)
2176{
2177 const struct intel_pt_blk_items *items = &ptq->state->items;
2178 struct perf_sample sample = { .ip = 0, };
2179 union perf_event *event = ptq->event_buf;
2180 struct intel_pt *pt = ptq->pt;
2181 u64 sample_type = evsel->core.attr.sample_type;
2182 u8 cpumode;
2183 u64 regs[8 * sizeof(sample.intr_regs.mask)];
2184
2185 if (intel_pt_skip_event(pt))
2186 return 0;
2187
2188 intel_pt_prep_a_sample(ptq, event, &sample);
2189
2190 sample.id = id;
2191 sample.stream_id = id;
2192
2193 if (!evsel->core.attr.freq)
2194 sample.period = evsel->core.attr.sample_period;
2195
2196 /* No support for non-zero CS base */
2197 if (items->has_ip)
2198 sample.ip = items->ip;
2199 else if (items->has_rip)
2200 sample.ip = items->rip;
2201 else
2202 sample.ip = ptq->state->from_ip;
2203
2204 cpumode = intel_pt_cpumode(ptq, sample.ip, 0);
2205
2206 event->sample.header.misc = cpumode | PERF_RECORD_MISC_EXACT_IP;
2207
2208 sample.cpumode = cpumode;
2209
2210 if (sample_type & PERF_SAMPLE_TIME) {
2211 u64 timestamp = 0;
2212
2213 if (items->has_timestamp)
2214 timestamp = items->timestamp;
2215 else if (!pt->timeless_decoding)
2216 timestamp = ptq->timestamp;
2217 if (timestamp)
2218 sample.time = tsc_to_perf_time(timestamp, &pt->tc);
2219 }
2220
2221 if (sample_type & PERF_SAMPLE_CALLCHAIN &&
2222 pt->synth_opts.callchain) {
2223 thread_stack__sample(ptq->thread, ptq->cpu, ptq->chain,
2224 pt->synth_opts.callchain_sz, sample.ip,
2225 pt->kernel_start);
2226 sample.callchain = ptq->chain;
2227 }
2228
2229 if (sample_type & PERF_SAMPLE_REGS_INTR &&
2230 (items->mask[INTEL_PT_GP_REGS_POS] ||
2231 items->mask[INTEL_PT_XMM_POS])) {
2232 u64 regs_mask = evsel->core.attr.sample_regs_intr;
2233 u64 *pos;
2234
2235 sample.intr_regs.abi = items->is_32_bit ?
2236 PERF_SAMPLE_REGS_ABI_32 :
2237 PERF_SAMPLE_REGS_ABI_64;
2238 sample.intr_regs.regs = regs;
2239
2240 pos = intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
2241
2242 intel_pt_add_xmm(&sample.intr_regs, pos, items, regs_mask);
2243 }
2244
2245 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
2246 if (items->mask[INTEL_PT_LBR_0_POS] ||
2247 items->mask[INTEL_PT_LBR_1_POS] ||
2248 items->mask[INTEL_PT_LBR_2_POS]) {
2249 intel_pt_add_lbrs(ptq->last_branch, items);
2250 } else if (pt->synth_opts.last_branch) {
2251 thread_stack__br_sample(ptq->thread, ptq->cpu,
2252 ptq->last_branch,
2253 pt->br_stack_sz);
2254 } else {
2255 ptq->last_branch->nr = 0;
2256 }
2257 sample.branch_stack = ptq->last_branch;
2258 }
2259
2260 if (sample_type & PERF_SAMPLE_ADDR && items->has_mem_access_address)
2261 sample.addr = items->mem_access_address;
2262
2263 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
2264 /*
2265 * Refer kernel's setup_pebs_adaptive_sample_data() and
2266 * intel_hsw_weight().
2267 */
2268 if (items->has_mem_access_latency) {
2269 u64 weight = items->mem_access_latency >> 32;
2270
2271 /*
2272 * Starts from SPR, the mem access latency field
2273 * contains both cache latency [47:32] and instruction
2274 * latency [15:0]. The cache latency is the same as the
2275 * mem access latency on previous platforms.
2276 *
2277 * In practice, no memory access could last than 4G
2278 * cycles. Use latency >> 32 to distinguish the
2279 * different format of the mem access latency field.
2280 */
2281 if (weight > 0) {
2282 sample.weight = weight & 0xffff;
2283 sample.ins_lat = items->mem_access_latency & 0xffff;
2284 } else
2285 sample.weight = items->mem_access_latency;
2286 }
2287 if (!sample.weight && items->has_tsx_aux_info) {
2288 /* Cycles last block */
2289 sample.weight = (u32)items->tsx_aux_info;
2290 }
2291 }
2292
2293 if (sample_type & PERF_SAMPLE_TRANSACTION && items->has_tsx_aux_info) {
2294 u64 ax = items->has_rax ? items->rax : 0;
2295 /* Refer kernel's intel_hsw_transaction() */
2296 u64 txn = (u8)(items->tsx_aux_info >> 32);
2297
2298 /* For RTM XABORTs also log the abort code from AX */
2299 if (txn & PERF_TXN_TRANSACTION && ax & 1)
2300 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
2301 sample.transaction = txn;
2302 }
2303
2304 return intel_pt_deliver_synth_event(pt, event, &sample, sample_type);
2305}
2306
2307static int intel_pt_synth_single_pebs_sample(struct intel_pt_queue *ptq)
2308{
2309 struct intel_pt *pt = ptq->pt;
2310 struct evsel *evsel = pt->pebs_evsel;
2311 u64 id = evsel->core.id[0];
2312
2313 return intel_pt_do_synth_pebs_sample(ptq, evsel, id);
2314}
2315
2316static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
2317{
2318 const struct intel_pt_blk_items *items = &ptq->state->items;
2319 struct intel_pt_pebs_event *pe;
2320 struct intel_pt *pt = ptq->pt;
2321 int err = -EINVAL;
2322 int hw_id;
2323
2324 if (!items->has_applicable_counters || !items->applicable_counters) {
2325 if (!pt->single_pebs)
2326 pr_err("PEBS-via-PT record with no applicable_counters\n");
2327 return intel_pt_synth_single_pebs_sample(ptq);
2328 }
2329
2330 for_each_set_bit(hw_id, (unsigned long *)&items->applicable_counters, INTEL_PT_MAX_PEBS) {
2331 pe = &ptq->pebs[hw_id];
2332 if (!pe->evsel) {
2333 if (!pt->single_pebs)
2334 pr_err("PEBS-via-PT record with no matching event, hw_id %d\n",
2335 hw_id);
2336 return intel_pt_synth_single_pebs_sample(ptq);
2337 }
2338 err = intel_pt_do_synth_pebs_sample(ptq, pe->evsel, pe->id);
2339 if (err)
2340 return err;
2341 }
2342
2343 return err;
2344}
2345
2346static int intel_pt_synth_events_sample(struct intel_pt_queue *ptq)
2347{
2348 struct intel_pt *pt = ptq->pt;
2349 union perf_event *event = ptq->event_buf;
2350 struct perf_sample sample = { .ip = 0, };
2351 struct {
2352 struct perf_synth_intel_evt cfe;
2353 struct perf_synth_intel_evd evd[INTEL_PT_MAX_EVDS];
2354 } raw;
2355 int i;
2356
2357 if (intel_pt_skip_event(pt))
2358 return 0;
2359
2360 intel_pt_prep_p_sample(pt, ptq, event, &sample);
2361
2362 sample.id = ptq->pt->evt_id;
2363 sample.stream_id = ptq->pt->evt_id;
2364
2365 raw.cfe.type = ptq->state->cfe_type;
2366 raw.cfe.reserved = 0;
2367 raw.cfe.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP);
2368 raw.cfe.vector = ptq->state->cfe_vector;
2369 raw.cfe.evd_cnt = ptq->state->evd_cnt;
2370
2371 for (i = 0; i < ptq->state->evd_cnt; i++) {
2372 raw.evd[i].et = 0;
2373 raw.evd[i].evd_type = ptq->state->evd[i].type;
2374 raw.evd[i].payload = ptq->state->evd[i].payload;
2375 }
2376
2377 sample.raw_size = perf_synth__raw_size(raw) +
2378 ptq->state->evd_cnt * sizeof(struct perf_synth_intel_evd);
2379 sample.raw_data = perf_synth__raw_data(&raw);
2380
2381 return intel_pt_deliver_synth_event(pt, event, &sample,
2382 pt->evt_sample_type);
2383}
2384
2385static int intel_pt_synth_iflag_chg_sample(struct intel_pt_queue *ptq)
2386{
2387 struct intel_pt *pt = ptq->pt;
2388 union perf_event *event = ptq->event_buf;
2389 struct perf_sample sample = { .ip = 0, };
2390 struct perf_synth_intel_iflag_chg raw;
2391
2392 if (intel_pt_skip_event(pt))
2393 return 0;
2394
2395 intel_pt_prep_p_sample(pt, ptq, event, &sample);
2396
2397 sample.id = ptq->pt->iflag_chg_id;
2398 sample.stream_id = ptq->pt->iflag_chg_id;
2399
2400 raw.flags = 0;
2401 raw.iflag = ptq->state->to_iflag;
2402
2403 if (ptq->state->type & INTEL_PT_BRANCH) {
2404 raw.via_branch = 1;
2405 raw.branch_ip = ptq->state->to_ip;
2406 } else {
2407 sample.addr = 0;
2408 }
2409 sample.flags = ptq->flags;
2410
2411 sample.raw_size = perf_synth__raw_size(raw);
2412 sample.raw_data = perf_synth__raw_data(&raw);
2413
2414 return intel_pt_deliver_synth_event(pt, event, &sample,
2415 pt->iflag_chg_sample_type);
2416}
2417
2418static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu,
2419 pid_t pid, pid_t tid, u64 ip, u64 timestamp,
2420 pid_t machine_pid, int vcpu)
2421{
2422 bool dump_log_on_error = pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ON_ERROR;
2423 bool log_on_stdout = pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_USE_STDOUT;
2424 union perf_event event;
2425 char msg[MAX_AUXTRACE_ERROR_MSG];
2426 int err;
2427
2428 if (pt->synth_opts.error_minus_flags) {
2429 if (code == INTEL_PT_ERR_OVR &&
2430 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_OVERFLOW)
2431 return 0;
2432 if (code == INTEL_PT_ERR_LOST &&
2433 pt->synth_opts.error_minus_flags & AUXTRACE_ERR_FLG_DATA_LOST)
2434 return 0;
2435 }
2436
2437 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG);
2438
2439 auxtrace_synth_guest_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE,
2440 code, cpu, pid, tid, ip, msg, timestamp,
2441 machine_pid, vcpu);
2442
2443 if (intel_pt_enable_logging && !log_on_stdout) {
2444 FILE *fp = intel_pt_log_fp();
2445
2446 if (fp)
2447 perf_event__fprintf_auxtrace_error(&event, fp);
2448 }
2449
2450 if (code != INTEL_PT_ERR_LOST && dump_log_on_error)
2451 intel_pt_log_dump_buf();
2452
2453 err = perf_session__deliver_synth_event(pt->session, &event, NULL);
2454 if (err)
2455 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n",
2456 err);
2457
2458 return err;
2459}
2460
2461static int intel_ptq_synth_error(struct intel_pt_queue *ptq,
2462 const struct intel_pt_state *state)
2463{
2464 struct intel_pt *pt = ptq->pt;
2465 u64 tm = ptq->timestamp;
2466 pid_t machine_pid = 0;
2467 pid_t pid = ptq->pid;
2468 pid_t tid = ptq->tid;
2469 int vcpu = -1;
2470
2471 tm = pt->timeless_decoding ? 0 : tsc_to_perf_time(tm, &pt->tc);
2472
2473 if (pt->have_guest_sideband && state->from_nr) {
2474 machine_pid = ptq->guest_machine_pid;
2475 vcpu = ptq->vcpu;
2476 pid = ptq->guest_pid;
2477 tid = ptq->guest_tid;
2478 }
2479
2480 return intel_pt_synth_error(pt, state->err, ptq->cpu, pid, tid,
2481 state->from_ip, tm, machine_pid, vcpu);
2482}
2483
2484static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq)
2485{
2486 struct auxtrace_queue *queue;
2487 pid_t tid = ptq->next_tid;
2488 int err;
2489
2490 if (tid == -1)
2491 return 0;
2492
2493 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid);
2494
2495 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid);
2496
2497 queue = &pt->queues.queue_array[ptq->queue_nr];
2498 intel_pt_set_pid_tid_cpu(pt, queue);
2499
2500 ptq->next_tid = -1;
2501
2502 return err;
2503}
2504
2505static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip)
2506{
2507 struct intel_pt *pt = ptq->pt;
2508
2509 return ip == pt->switch_ip &&
2510 (ptq->flags & PERF_IP_FLAG_BRANCH) &&
2511 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC |
2512 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT));
2513}
2514
2515#define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \
2516 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT)
2517
2518static int intel_pt_sample(struct intel_pt_queue *ptq)
2519{
2520 const struct intel_pt_state *state = ptq->state;
2521 struct intel_pt *pt = ptq->pt;
2522 int err;
2523
2524 if (!ptq->have_sample)
2525 return 0;
2526
2527 ptq->have_sample = false;
2528
2529 if (pt->synth_opts.approx_ipc) {
2530 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt;
2531 ptq->ipc_cyc_cnt = ptq->state->cycles;
2532 ptq->sample_ipc = true;
2533 } else {
2534 ptq->ipc_insn_cnt = ptq->state->tot_insn_cnt;
2535 ptq->ipc_cyc_cnt = ptq->state->tot_cyc_cnt;
2536 ptq->sample_ipc = ptq->state->flags & INTEL_PT_SAMPLE_IPC;
2537 }
2538
2539 /* Ensure guest code maps are set up */
2540 if (symbol_conf.guest_code && (state->from_nr || state->to_nr))
2541 intel_pt_get_guest(ptq);
2542
2543 /*
2544 * Do PEBS first to allow for the possibility that the PEBS timestamp
2545 * precedes the current timestamp.
2546 */
2547 if (pt->sample_pebs && state->type & INTEL_PT_BLK_ITEMS) {
2548 err = intel_pt_synth_pebs_sample(ptq);
2549 if (err)
2550 return err;
2551 }
2552
2553 if (pt->synth_opts.intr_events) {
2554 if (state->type & INTEL_PT_EVT) {
2555 err = intel_pt_synth_events_sample(ptq);
2556 if (err)
2557 return err;
2558 }
2559 if (state->type & INTEL_PT_IFLAG_CHG) {
2560 err = intel_pt_synth_iflag_chg_sample(ptq);
2561 if (err)
2562 return err;
2563 }
2564 }
2565
2566 if (pt->sample_pwr_events) {
2567 if (state->type & INTEL_PT_PSB_EVT) {
2568 err = intel_pt_synth_psb_sample(ptq);
2569 if (err)
2570 return err;
2571 }
2572 if (ptq->state->cbr != ptq->cbr_seen) {
2573 err = intel_pt_synth_cbr_sample(ptq);
2574 if (err)
2575 return err;
2576 }
2577 if (state->type & INTEL_PT_PWR_EVT) {
2578 if (state->type & INTEL_PT_MWAIT_OP) {
2579 err = intel_pt_synth_mwait_sample(ptq);
2580 if (err)
2581 return err;
2582 }
2583 if (state->type & INTEL_PT_PWR_ENTRY) {
2584 err = intel_pt_synth_pwre_sample(ptq);
2585 if (err)
2586 return err;
2587 }
2588 if (state->type & INTEL_PT_EX_STOP) {
2589 err = intel_pt_synth_exstop_sample(ptq);
2590 if (err)
2591 return err;
2592 }
2593 if (state->type & INTEL_PT_PWR_EXIT) {
2594 err = intel_pt_synth_pwrx_sample(ptq);
2595 if (err)
2596 return err;
2597 }
2598 }
2599 }
2600
2601 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) {
2602 err = intel_pt_synth_instruction_sample(ptq);
2603 if (err)
2604 return err;
2605 }
2606
2607 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) {
2608 err = intel_pt_synth_transaction_sample(ptq);
2609 if (err)
2610 return err;
2611 }
2612
2613 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) {
2614 err = intel_pt_synth_ptwrite_sample(ptq);
2615 if (err)
2616 return err;
2617 }
2618
2619 if (!(state->type & INTEL_PT_BRANCH))
2620 return 0;
2621
2622 if (pt->use_thread_stack) {
2623 thread_stack__event(ptq->thread, ptq->cpu, ptq->flags,
2624 state->from_ip, state->to_ip, ptq->insn_len,
2625 state->trace_nr, pt->callstack,
2626 pt->br_stack_sz_plus,
2627 pt->mispred_all);
2628 } else {
2629 thread_stack__set_trace_nr(ptq->thread, ptq->cpu, state->trace_nr);
2630 }
2631
2632 if (pt->sample_branches) {
2633 if (state->from_nr != state->to_nr &&
2634 state->from_ip && state->to_ip) {
2635 struct intel_pt_state *st = (struct intel_pt_state *)state;
2636 u64 to_ip = st->to_ip;
2637 u64 from_ip = st->from_ip;
2638
2639 /*
2640 * perf cannot handle having different machines for ip
2641 * and addr, so create 2 branches.
2642 */
2643 st->to_ip = 0;
2644 err = intel_pt_synth_branch_sample(ptq);
2645 if (err)
2646 return err;
2647 st->from_ip = 0;
2648 st->to_ip = to_ip;
2649 err = intel_pt_synth_branch_sample(ptq);
2650 st->from_ip = from_ip;
2651 } else {
2652 err = intel_pt_synth_branch_sample(ptq);
2653 }
2654 if (err)
2655 return err;
2656 }
2657
2658 if (!ptq->sync_switch)
2659 return 0;
2660
2661 if (intel_pt_is_switch_ip(ptq, state->to_ip)) {
2662 switch (ptq->switch_state) {
2663 case INTEL_PT_SS_NOT_TRACING:
2664 case INTEL_PT_SS_UNKNOWN:
2665 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
2666 err = intel_pt_next_tid(pt, ptq);
2667 if (err)
2668 return err;
2669 ptq->switch_state = INTEL_PT_SS_TRACING;
2670 break;
2671 default:
2672 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT;
2673 return 1;
2674 }
2675 } else if (!state->to_ip) {
2676 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2677 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) {
2678 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2679 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2680 state->to_ip == pt->ptss_ip &&
2681 (ptq->flags & PERF_IP_FLAG_CALL)) {
2682 ptq->switch_state = INTEL_PT_SS_TRACING;
2683 }
2684
2685 return 0;
2686}
2687
2688static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip)
2689{
2690 struct machine *machine = pt->machine;
2691 struct map *map;
2692 struct symbol *sym, *start;
2693 u64 ip, switch_ip = 0;
2694 const char *ptss;
2695
2696 if (ptss_ip)
2697 *ptss_ip = 0;
2698
2699 map = machine__kernel_map(machine);
2700 if (!map)
2701 return 0;
2702
2703 if (map__load(map))
2704 return 0;
2705
2706 start = dso__first_symbol(map->dso);
2707
2708 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2709 if (sym->binding == STB_GLOBAL &&
2710 !strcmp(sym->name, "__switch_to")) {
2711 ip = map->unmap_ip(map, sym->start);
2712 if (ip >= map->start && ip < map->end) {
2713 switch_ip = ip;
2714 break;
2715 }
2716 }
2717 }
2718
2719 if (!switch_ip || !ptss_ip)
2720 return 0;
2721
2722 if (pt->have_sched_switch == 1)
2723 ptss = "perf_trace_sched_switch";
2724 else
2725 ptss = "__perf_event_task_sched_out";
2726
2727 for (sym = start; sym; sym = dso__next_symbol(sym)) {
2728 if (!strcmp(sym->name, ptss)) {
2729 ip = map->unmap_ip(map, sym->start);
2730 if (ip >= map->start && ip < map->end) {
2731 *ptss_ip = ip;
2732 break;
2733 }
2734 }
2735 }
2736
2737 return switch_ip;
2738}
2739
2740static void intel_pt_enable_sync_switch(struct intel_pt *pt)
2741{
2742 unsigned int i;
2743
2744 if (pt->sync_switch_not_supported)
2745 return;
2746
2747 pt->sync_switch = true;
2748
2749 for (i = 0; i < pt->queues.nr_queues; i++) {
2750 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2751 struct intel_pt_queue *ptq = queue->priv;
2752
2753 if (ptq)
2754 ptq->sync_switch = true;
2755 }
2756}
2757
2758static void intel_pt_disable_sync_switch(struct intel_pt *pt)
2759{
2760 unsigned int i;
2761
2762 pt->sync_switch = false;
2763
2764 for (i = 0; i < pt->queues.nr_queues; i++) {
2765 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
2766 struct intel_pt_queue *ptq = queue->priv;
2767
2768 if (ptq) {
2769 ptq->sync_switch = false;
2770 intel_pt_next_tid(pt, ptq);
2771 }
2772 }
2773}
2774
2775/*
2776 * To filter against time ranges, it is only necessary to look at the next start
2777 * or end time.
2778 */
2779static bool intel_pt_next_time(struct intel_pt_queue *ptq)
2780{
2781 struct intel_pt *pt = ptq->pt;
2782
2783 if (ptq->sel_start) {
2784 /* Next time is an end time */
2785 ptq->sel_start = false;
2786 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].end;
2787 return true;
2788 } else if (ptq->sel_idx + 1 < pt->range_cnt) {
2789 /* Next time is a start time */
2790 ptq->sel_start = true;
2791 ptq->sel_idx += 1;
2792 ptq->sel_timestamp = pt->time_ranges[ptq->sel_idx].start;
2793 return true;
2794 }
2795
2796 /* No next time */
2797 return false;
2798}
2799
2800static int intel_pt_time_filter(struct intel_pt_queue *ptq, u64 *ff_timestamp)
2801{
2802 int err;
2803
2804 while (1) {
2805 if (ptq->sel_start) {
2806 if (ptq->timestamp >= ptq->sel_timestamp) {
2807 /* After start time, so consider next time */
2808 intel_pt_next_time(ptq);
2809 if (!ptq->sel_timestamp) {
2810 /* No end time */
2811 return 0;
2812 }
2813 /* Check against end time */
2814 continue;
2815 }
2816 /* Before start time, so fast forward */
2817 ptq->have_sample = false;
2818 if (ptq->sel_timestamp > *ff_timestamp) {
2819 if (ptq->sync_switch) {
2820 intel_pt_next_tid(ptq->pt, ptq);
2821 ptq->switch_state = INTEL_PT_SS_UNKNOWN;
2822 }
2823 *ff_timestamp = ptq->sel_timestamp;
2824 err = intel_pt_fast_forward(ptq->decoder,
2825 ptq->sel_timestamp);
2826 if (err)
2827 return err;
2828 }
2829 return 0;
2830 } else if (ptq->timestamp > ptq->sel_timestamp) {
2831 /* After end time, so consider next time */
2832 if (!intel_pt_next_time(ptq)) {
2833 /* No next time range, so stop decoding */
2834 ptq->have_sample = false;
2835 ptq->switch_state = INTEL_PT_SS_NOT_TRACING;
2836 return 1;
2837 }
2838 /* Check against next start time */
2839 continue;
2840 } else {
2841 /* Before end time */
2842 return 0;
2843 }
2844 }
2845}
2846
2847static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp)
2848{
2849 const struct intel_pt_state *state = ptq->state;
2850 struct intel_pt *pt = ptq->pt;
2851 u64 ff_timestamp = 0;
2852 int err;
2853
2854 if (!pt->kernel_start) {
2855 pt->kernel_start = machine__kernel_start(pt->machine);
2856 if (pt->per_cpu_mmaps &&
2857 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) &&
2858 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) &&
2859 !pt->sampling_mode && !pt->synth_opts.vm_time_correlation) {
2860 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip);
2861 if (pt->switch_ip) {
2862 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n",
2863 pt->switch_ip, pt->ptss_ip);
2864 intel_pt_enable_sync_switch(pt);
2865 }
2866 }
2867 }
2868
2869 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n",
2870 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
2871 while (1) {
2872 err = intel_pt_sample(ptq);
2873 if (err)
2874 return err;
2875
2876 state = intel_pt_decode(ptq->decoder);
2877 if (state->err) {
2878 if (state->err == INTEL_PT_ERR_NODATA)
2879 return 1;
2880 if (ptq->sync_switch &&
2881 state->from_ip >= pt->kernel_start) {
2882 ptq->sync_switch = false;
2883 intel_pt_next_tid(pt, ptq);
2884 }
2885 ptq->timestamp = state->est_timestamp;
2886 if (pt->synth_opts.errors) {
2887 err = intel_ptq_synth_error(ptq, state);
2888 if (err)
2889 return err;
2890 }
2891 continue;
2892 }
2893
2894 ptq->state = state;
2895 ptq->have_sample = true;
2896 intel_pt_sample_flags(ptq);
2897
2898 /* Use estimated TSC upon return to user space */
2899 if (pt->est_tsc &&
2900 (state->from_ip >= pt->kernel_start || !state->from_ip) &&
2901 state->to_ip && state->to_ip < pt->kernel_start) {
2902 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2903 state->timestamp, state->est_timestamp);
2904 ptq->timestamp = state->est_timestamp;
2905 /* Use estimated TSC in unknown switch state */
2906 } else if (ptq->sync_switch &&
2907 ptq->switch_state == INTEL_PT_SS_UNKNOWN &&
2908 intel_pt_is_switch_ip(ptq, state->to_ip) &&
2909 ptq->next_tid == -1) {
2910 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n",
2911 state->timestamp, state->est_timestamp);
2912 ptq->timestamp = state->est_timestamp;
2913 } else if (state->timestamp > ptq->timestamp) {
2914 ptq->timestamp = state->timestamp;
2915 }
2916
2917 if (ptq->sel_timestamp) {
2918 err = intel_pt_time_filter(ptq, &ff_timestamp);
2919 if (err)
2920 return err;
2921 }
2922
2923 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) {
2924 *timestamp = ptq->timestamp;
2925 return 0;
2926 }
2927 }
2928 return 0;
2929}
2930
2931static inline int intel_pt_update_queues(struct intel_pt *pt)
2932{
2933 if (pt->queues.new_data) {
2934 pt->queues.new_data = false;
2935 return intel_pt_setup_queues(pt);
2936 }
2937 return 0;
2938}
2939
2940static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp)
2941{
2942 unsigned int queue_nr;
2943 u64 ts;
2944 int ret;
2945
2946 while (1) {
2947 struct auxtrace_queue *queue;
2948 struct intel_pt_queue *ptq;
2949
2950 if (!pt->heap.heap_cnt)
2951 return 0;
2952
2953 if (pt->heap.heap_array[0].ordinal >= timestamp)
2954 return 0;
2955
2956 queue_nr = pt->heap.heap_array[0].queue_nr;
2957 queue = &pt->queues.queue_array[queue_nr];
2958 ptq = queue->priv;
2959
2960 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n",
2961 queue_nr, pt->heap.heap_array[0].ordinal,
2962 timestamp);
2963
2964 auxtrace_heap__pop(&pt->heap);
2965
2966 if (pt->heap.heap_cnt) {
2967 ts = pt->heap.heap_array[0].ordinal + 1;
2968 if (ts > timestamp)
2969 ts = timestamp;
2970 } else {
2971 ts = timestamp;
2972 }
2973
2974 intel_pt_set_pid_tid_cpu(pt, queue);
2975
2976 ret = intel_pt_run_decoder(ptq, &ts);
2977
2978 if (ret < 0) {
2979 auxtrace_heap__add(&pt->heap, queue_nr, ts);
2980 return ret;
2981 }
2982
2983 if (!ret) {
2984 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts);
2985 if (ret < 0)
2986 return ret;
2987 } else {
2988 ptq->on_heap = false;
2989 }
2990 }
2991
2992 return 0;
2993}
2994
2995static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid,
2996 u64 time_)
2997{
2998 struct auxtrace_queues *queues = &pt->queues;
2999 unsigned int i;
3000 u64 ts = 0;
3001
3002 for (i = 0; i < queues->nr_queues; i++) {
3003 struct auxtrace_queue *queue = &pt->queues.queue_array[i];
3004 struct intel_pt_queue *ptq = queue->priv;
3005
3006 if (ptq && (tid == -1 || ptq->tid == tid)) {
3007 ptq->time = time_;
3008 intel_pt_set_pid_tid_cpu(pt, queue);
3009 intel_pt_run_decoder(ptq, &ts);
3010 }
3011 }
3012 return 0;
3013}
3014
3015static void intel_pt_sample_set_pid_tid_cpu(struct intel_pt_queue *ptq,
3016 struct auxtrace_queue *queue,
3017 struct perf_sample *sample)
3018{
3019 struct machine *m = ptq->pt->machine;
3020
3021 ptq->pid = sample->pid;
3022 ptq->tid = sample->tid;
3023 ptq->cpu = queue->cpu;
3024
3025 intel_pt_log("queue %u cpu %d pid %d tid %d\n",
3026 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid);
3027
3028 thread__zput(ptq->thread);
3029
3030 if (ptq->tid == -1)
3031 return;
3032
3033 if (ptq->pid == -1) {
3034 ptq->thread = machine__find_thread(m, -1, ptq->tid);
3035 if (ptq->thread)
3036 ptq->pid = ptq->thread->pid_;
3037 return;
3038 }
3039
3040 ptq->thread = machine__findnew_thread(m, ptq->pid, ptq->tid);
3041}
3042
3043static int intel_pt_process_timeless_sample(struct intel_pt *pt,
3044 struct perf_sample *sample)
3045{
3046 struct auxtrace_queue *queue;
3047 struct intel_pt_queue *ptq;
3048 u64 ts = 0;
3049
3050 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session);
3051 if (!queue)
3052 return -EINVAL;
3053
3054 ptq = queue->priv;
3055 if (!ptq)
3056 return 0;
3057
3058 ptq->stop = false;
3059 ptq->time = sample->time;
3060 intel_pt_sample_set_pid_tid_cpu(ptq, queue, sample);
3061 intel_pt_run_decoder(ptq, &ts);
3062 return 0;
3063}
3064
3065static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample)
3066{
3067 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu,
3068 sample->pid, sample->tid, 0, sample->time,
3069 sample->machine_pid, sample->vcpu);
3070}
3071
3072static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu)
3073{
3074 unsigned i, j;
3075
3076 if (cpu < 0 || !pt->queues.nr_queues)
3077 return NULL;
3078
3079 if ((unsigned)cpu >= pt->queues.nr_queues)
3080 i = pt->queues.nr_queues - 1;
3081 else
3082 i = cpu;
3083
3084 if (pt->queues.queue_array[i].cpu == cpu)
3085 return pt->queues.queue_array[i].priv;
3086
3087 for (j = 0; i > 0; j++) {
3088 if (pt->queues.queue_array[--i].cpu == cpu)
3089 return pt->queues.queue_array[i].priv;
3090 }
3091
3092 for (; j < pt->queues.nr_queues; j++) {
3093 if (pt->queues.queue_array[j].cpu == cpu)
3094 return pt->queues.queue_array[j].priv;
3095 }
3096
3097 return NULL;
3098}
3099
3100static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid,
3101 u64 timestamp)
3102{
3103 struct intel_pt_queue *ptq;
3104 int err;
3105
3106 if (!pt->sync_switch)
3107 return 1;
3108
3109 ptq = intel_pt_cpu_to_ptq(pt, cpu);
3110 if (!ptq || !ptq->sync_switch)
3111 return 1;
3112
3113 switch (ptq->switch_state) {
3114 case INTEL_PT_SS_NOT_TRACING:
3115 break;
3116 case INTEL_PT_SS_UNKNOWN:
3117 case INTEL_PT_SS_TRACING:
3118 ptq->next_tid = tid;
3119 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP;
3120 return 0;
3121 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
3122 if (!ptq->on_heap) {
3123 ptq->timestamp = perf_time_to_tsc(timestamp,
3124 &pt->tc);
3125 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr,
3126 ptq->timestamp);
3127 if (err)
3128 return err;
3129 ptq->on_heap = true;
3130 }
3131 ptq->switch_state = INTEL_PT_SS_TRACING;
3132 break;
3133 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
3134 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu);
3135 break;
3136 default:
3137 break;
3138 }
3139
3140 ptq->next_tid = -1;
3141
3142 return 1;
3143}
3144
3145#ifdef HAVE_LIBTRACEEVENT
3146static int intel_pt_process_switch(struct intel_pt *pt,
3147 struct perf_sample *sample)
3148{
3149 pid_t tid;
3150 int cpu, ret;
3151 struct evsel *evsel = evlist__id2evsel(pt->session->evlist, sample->id);
3152
3153 if (evsel != pt->switch_evsel)
3154 return 0;
3155
3156 tid = evsel__intval(evsel, sample, "next_pid");
3157 cpu = sample->cpu;
3158
3159 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
3160 cpu, tid, sample->time, perf_time_to_tsc(sample->time,
3161 &pt->tc));
3162
3163 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
3164 if (ret <= 0)
3165 return ret;
3166
3167 return machine__set_current_tid(pt->machine, cpu, -1, tid);
3168}
3169#endif /* HAVE_LIBTRACEEVENT */
3170
3171static int intel_pt_context_switch_in(struct intel_pt *pt,
3172 struct perf_sample *sample)
3173{
3174 pid_t pid = sample->pid;
3175 pid_t tid = sample->tid;
3176 int cpu = sample->cpu;
3177
3178 if (pt->sync_switch) {
3179 struct intel_pt_queue *ptq;
3180
3181 ptq = intel_pt_cpu_to_ptq(pt, cpu);
3182 if (ptq && ptq->sync_switch) {
3183 ptq->next_tid = -1;
3184 switch (ptq->switch_state) {
3185 case INTEL_PT_SS_NOT_TRACING:
3186 case INTEL_PT_SS_UNKNOWN:
3187 case INTEL_PT_SS_TRACING:
3188 break;
3189 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT:
3190 case INTEL_PT_SS_EXPECTING_SWITCH_IP:
3191 ptq->switch_state = INTEL_PT_SS_TRACING;
3192 break;
3193 default:
3194 break;
3195 }
3196 }
3197 }
3198
3199 /*
3200 * If the current tid has not been updated yet, ensure it is now that
3201 * a "switch in" event has occurred.
3202 */
3203 if (machine__get_current_tid(pt->machine, cpu) == tid)
3204 return 0;
3205
3206 return machine__set_current_tid(pt->machine, cpu, pid, tid);
3207}
3208
3209static int intel_pt_guest_context_switch(struct intel_pt *pt,
3210 union perf_event *event,
3211 struct perf_sample *sample)
3212{
3213 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
3214 struct machines *machines = &pt->session->machines;
3215 struct machine *machine = machines__find(machines, sample->machine_pid);
3216
3217 pt->have_guest_sideband = true;
3218
3219 /*
3220 * sync_switch cannot handle guest machines at present, so just disable
3221 * it.
3222 */
3223 pt->sync_switch_not_supported = true;
3224 if (pt->sync_switch)
3225 intel_pt_disable_sync_switch(pt);
3226
3227 if (out)
3228 return 0;
3229
3230 if (!machine)
3231 return -EINVAL;
3232
3233 return machine__set_current_tid(machine, sample->vcpu, sample->pid, sample->tid);
3234}
3235
3236static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event,
3237 struct perf_sample *sample)
3238{
3239 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT;
3240 pid_t pid, tid;
3241 int cpu, ret;
3242
3243 if (perf_event__is_guest(event))
3244 return intel_pt_guest_context_switch(pt, event, sample);
3245
3246 cpu = sample->cpu;
3247
3248 if (pt->have_sched_switch == 3) {
3249 if (!out)
3250 return intel_pt_context_switch_in(pt, sample);
3251 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) {
3252 pr_err("Expecting CPU-wide context switch event\n");
3253 return -EINVAL;
3254 }
3255 pid = event->context_switch.next_prev_pid;
3256 tid = event->context_switch.next_prev_tid;
3257 } else {
3258 if (out)
3259 return 0;
3260 pid = sample->pid;
3261 tid = sample->tid;
3262 }
3263
3264 if (tid == -1)
3265 intel_pt_log("context_switch event has no tid\n");
3266
3267 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time);
3268 if (ret <= 0)
3269 return ret;
3270
3271 return machine__set_current_tid(pt->machine, cpu, pid, tid);
3272}
3273
3274static int intel_pt_process_itrace_start(struct intel_pt *pt,
3275 union perf_event *event,
3276 struct perf_sample *sample)
3277{
3278 if (!pt->per_cpu_mmaps)
3279 return 0;
3280
3281 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n",
3282 sample->cpu, event->itrace_start.pid,
3283 event->itrace_start.tid, sample->time,
3284 perf_time_to_tsc(sample->time, &pt->tc));
3285
3286 return machine__set_current_tid(pt->machine, sample->cpu,
3287 event->itrace_start.pid,
3288 event->itrace_start.tid);
3289}
3290
3291static int intel_pt_process_aux_output_hw_id(struct intel_pt *pt,
3292 union perf_event *event,
3293 struct perf_sample *sample)
3294{
3295 u64 hw_id = event->aux_output_hw_id.hw_id;
3296 struct auxtrace_queue *queue;
3297 struct intel_pt_queue *ptq;
3298 struct evsel *evsel;
3299
3300 queue = auxtrace_queues__sample_queue(&pt->queues, sample, pt->session);
3301 evsel = evlist__id2evsel_strict(pt->session->evlist, sample->id);
3302 if (!queue || !queue->priv || !evsel || hw_id > INTEL_PT_MAX_PEBS) {
3303 pr_err("Bad AUX output hardware ID\n");
3304 return -EINVAL;
3305 }
3306
3307 ptq = queue->priv;
3308
3309 ptq->pebs[hw_id].evsel = evsel;
3310 ptq->pebs[hw_id].id = sample->id;
3311
3312 return 0;
3313}
3314
3315static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr,
3316 struct addr_location *al)
3317{
3318 if (!al->map || addr < al->map->start || addr >= al->map->end) {
3319 if (!thread__find_map(thread, cpumode, addr, al))
3320 return -1;
3321 }
3322
3323 return 0;
3324}
3325
3326/* Invalidate all instruction cache entries that overlap the text poke */
3327static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event)
3328{
3329 u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK;
3330 u64 addr = event->text_poke.addr + event->text_poke.new_len - 1;
3331 /* Assume text poke begins in a basic block no more than 4096 bytes */
3332 int cnt = 4096 + event->text_poke.new_len;
3333 struct thread *thread = pt->unknown_thread;
3334 struct addr_location al = { .map = NULL };
3335 struct machine *machine = pt->machine;
3336 struct intel_pt_cache_entry *e;
3337 u64 offset;
3338
3339 if (!event->text_poke.new_len)
3340 return 0;
3341
3342 for (; cnt; cnt--, addr--) {
3343 if (intel_pt_find_map(thread, cpumode, addr, &al)) {
3344 if (addr < event->text_poke.addr)
3345 return 0;
3346 continue;
3347 }
3348
3349 if (!al.map->dso || !al.map->dso->auxtrace_cache)
3350 continue;
3351
3352 offset = al.map->map_ip(al.map, addr);
3353
3354 e = intel_pt_cache_lookup(al.map->dso, machine, offset);
3355 if (!e)
3356 continue;
3357
3358 if (addr + e->byte_cnt + e->length <= event->text_poke.addr) {
3359 /*
3360 * No overlap. Working backwards there cannot be another
3361 * basic block that overlaps the text poke if there is a
3362 * branch instruction before the text poke address.
3363 */
3364 if (e->branch != INTEL_PT_BR_NO_BRANCH)
3365 return 0;
3366 } else {
3367 intel_pt_cache_invalidate(al.map->dso, machine, offset);
3368 intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n",
3369 al.map->dso->long_name, addr);
3370 }
3371 }
3372
3373 return 0;
3374}
3375
3376static int intel_pt_process_event(struct perf_session *session,
3377 union perf_event *event,
3378 struct perf_sample *sample,
3379 struct perf_tool *tool)
3380{
3381 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3382 auxtrace);
3383 u64 timestamp;
3384 int err = 0;
3385
3386 if (dump_trace)
3387 return 0;
3388
3389 if (!tool->ordered_events) {
3390 pr_err("Intel Processor Trace requires ordered events\n");
3391 return -EINVAL;
3392 }
3393
3394 if (sample->time && sample->time != (u64)-1)
3395 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
3396 else
3397 timestamp = 0;
3398
3399 if (timestamp || pt->timeless_decoding) {
3400 err = intel_pt_update_queues(pt);
3401 if (err)
3402 return err;
3403 }
3404
3405 if (pt->timeless_decoding) {
3406 if (pt->sampling_mode) {
3407 if (sample->aux_sample.size)
3408 err = intel_pt_process_timeless_sample(pt,
3409 sample);
3410 } else if (event->header.type == PERF_RECORD_EXIT) {
3411 err = intel_pt_process_timeless_queues(pt,
3412 event->fork.tid,
3413 sample->time);
3414 }
3415 } else if (timestamp) {
3416 if (!pt->first_timestamp)
3417 intel_pt_first_timestamp(pt, timestamp);
3418 err = intel_pt_process_queues(pt, timestamp);
3419 }
3420 if (err)
3421 return err;
3422
3423 if (event->header.type == PERF_RECORD_SAMPLE) {
3424 if (pt->synth_opts.add_callchain && !sample->callchain)
3425 intel_pt_add_callchain(pt, sample);
3426 if (pt->synth_opts.add_last_branch && !sample->branch_stack)
3427 intel_pt_add_br_stack(pt, sample);
3428 }
3429
3430 if (event->header.type == PERF_RECORD_AUX &&
3431 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) &&
3432 pt->synth_opts.errors) {
3433 err = intel_pt_lost(pt, sample);
3434 if (err)
3435 return err;
3436 }
3437
3438#ifdef HAVE_LIBTRACEEVENT
3439 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE)
3440 err = intel_pt_process_switch(pt, sample);
3441 else
3442#endif
3443 if (event->header.type == PERF_RECORD_ITRACE_START)
3444 err = intel_pt_process_itrace_start(pt, event, sample);
3445 else if (event->header.type == PERF_RECORD_AUX_OUTPUT_HW_ID)
3446 err = intel_pt_process_aux_output_hw_id(pt, event, sample);
3447 else if (event->header.type == PERF_RECORD_SWITCH ||
3448 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE)
3449 err = intel_pt_context_switch(pt, event, sample);
3450
3451 if (!err && event->header.type == PERF_RECORD_TEXT_POKE)
3452 err = intel_pt_text_poke(pt, event);
3453
3454 if (intel_pt_enable_logging && intel_pt_log_events(pt, sample->time)) {
3455 intel_pt_log("event %u: cpu %d time %"PRIu64" tsc %#"PRIx64" ",
3456 event->header.type, sample->cpu, sample->time, timestamp);
3457 intel_pt_log_event(event);
3458 }
3459
3460 return err;
3461}
3462
3463static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool)
3464{
3465 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3466 auxtrace);
3467 int ret;
3468
3469 if (dump_trace)
3470 return 0;
3471
3472 if (!tool->ordered_events)
3473 return -EINVAL;
3474
3475 ret = intel_pt_update_queues(pt);
3476 if (ret < 0)
3477 return ret;
3478
3479 if (pt->timeless_decoding)
3480 return intel_pt_process_timeless_queues(pt, -1,
3481 MAX_TIMESTAMP - 1);
3482
3483 return intel_pt_process_queues(pt, MAX_TIMESTAMP);
3484}
3485
3486static void intel_pt_free_events(struct perf_session *session)
3487{
3488 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3489 auxtrace);
3490 struct auxtrace_queues *queues = &pt->queues;
3491 unsigned int i;
3492
3493 for (i = 0; i < queues->nr_queues; i++) {
3494 intel_pt_free_queue(queues->queue_array[i].priv);
3495 queues->queue_array[i].priv = NULL;
3496 }
3497 intel_pt_log_disable();
3498 auxtrace_queues__free(queues);
3499}
3500
3501static void intel_pt_free(struct perf_session *session)
3502{
3503 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3504 auxtrace);
3505
3506 auxtrace_heap__free(&pt->heap);
3507 intel_pt_free_events(session);
3508 session->auxtrace = NULL;
3509 intel_pt_free_vmcs_info(pt);
3510 thread__put(pt->unknown_thread);
3511 addr_filters__exit(&pt->filts);
3512 zfree(&pt->chain);
3513 zfree(&pt->filter);
3514 zfree(&pt->time_ranges);
3515 free(pt);
3516}
3517
3518static bool intel_pt_evsel_is_auxtrace(struct perf_session *session,
3519 struct evsel *evsel)
3520{
3521 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3522 auxtrace);
3523
3524 return evsel->core.attr.type == pt->pmu_type;
3525}
3526
3527static int intel_pt_process_auxtrace_event(struct perf_session *session,
3528 union perf_event *event,
3529 struct perf_tool *tool __maybe_unused)
3530{
3531 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3532 auxtrace);
3533
3534 if (!pt->data_queued) {
3535 struct auxtrace_buffer *buffer;
3536 off_t data_offset;
3537 int fd = perf_data__fd(session->data);
3538 int err;
3539
3540 if (perf_data__is_pipe(session->data)) {
3541 data_offset = 0;
3542 } else {
3543 data_offset = lseek(fd, 0, SEEK_CUR);
3544 if (data_offset == -1)
3545 return -errno;
3546 }
3547
3548 err = auxtrace_queues__add_event(&pt->queues, session, event,
3549 data_offset, &buffer);
3550 if (err)
3551 return err;
3552
3553 /* Dump here now we have copied a piped trace out of the pipe */
3554 if (dump_trace) {
3555 if (auxtrace_buffer__get_data(buffer, fd)) {
3556 intel_pt_dump_event(pt, buffer->data,
3557 buffer->size);
3558 auxtrace_buffer__put_data(buffer);
3559 }
3560 }
3561 }
3562
3563 return 0;
3564}
3565
3566static int intel_pt_queue_data(struct perf_session *session,
3567 struct perf_sample *sample,
3568 union perf_event *event, u64 data_offset)
3569{
3570 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt,
3571 auxtrace);
3572 u64 timestamp;
3573
3574 if (event) {
3575 return auxtrace_queues__add_event(&pt->queues, session, event,
3576 data_offset, NULL);
3577 }
3578
3579 if (sample->time && sample->time != (u64)-1)
3580 timestamp = perf_time_to_tsc(sample->time, &pt->tc);
3581 else
3582 timestamp = 0;
3583
3584 return auxtrace_queues__add_sample(&pt->queues, session, sample,
3585 data_offset, timestamp);
3586}
3587
3588struct intel_pt_synth {
3589 struct perf_tool dummy_tool;
3590 struct perf_session *session;
3591};
3592
3593static int intel_pt_event_synth(struct perf_tool *tool,
3594 union perf_event *event,
3595 struct perf_sample *sample __maybe_unused,
3596 struct machine *machine __maybe_unused)
3597{
3598 struct intel_pt_synth *intel_pt_synth =
3599 container_of(tool, struct intel_pt_synth, dummy_tool);
3600
3601 return perf_session__deliver_synth_event(intel_pt_synth->session, event,
3602 NULL);
3603}
3604
3605static int intel_pt_synth_event(struct perf_session *session, const char *name,
3606 struct perf_event_attr *attr, u64 id)
3607{
3608 struct intel_pt_synth intel_pt_synth;
3609 int err;
3610
3611 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n",
3612 name, id, (u64)attr->sample_type);
3613
3614 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth));
3615 intel_pt_synth.session = session;
3616
3617 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1,
3618 &id, intel_pt_event_synth);
3619 if (err)
3620 pr_err("%s: failed to synthesize '%s' event type\n",
3621 __func__, name);
3622
3623 return err;
3624}
3625
3626static void intel_pt_set_event_name(struct evlist *evlist, u64 id,
3627 const char *name)
3628{
3629 struct evsel *evsel;
3630
3631 evlist__for_each_entry(evlist, evsel) {
3632 if (evsel->core.id && evsel->core.id[0] == id) {
3633 if (evsel->name)
3634 zfree(&evsel->name);
3635 evsel->name = strdup(name);
3636 break;
3637 }
3638 }
3639}
3640
3641static struct evsel *intel_pt_evsel(struct intel_pt *pt,
3642 struct evlist *evlist)
3643{
3644 struct evsel *evsel;
3645
3646 evlist__for_each_entry(evlist, evsel) {
3647 if (evsel->core.attr.type == pt->pmu_type && evsel->core.ids)
3648 return evsel;
3649 }
3650
3651 return NULL;
3652}
3653
3654static int intel_pt_synth_events(struct intel_pt *pt,
3655 struct perf_session *session)
3656{
3657 struct evlist *evlist = session->evlist;
3658 struct evsel *evsel = intel_pt_evsel(pt, evlist);
3659 struct perf_event_attr attr;
3660 u64 id;
3661 int err;
3662
3663 if (!evsel) {
3664 pr_debug("There are no selected events with Intel Processor Trace data\n");
3665 return 0;
3666 }
3667
3668 memset(&attr, 0, sizeof(struct perf_event_attr));
3669 attr.size = sizeof(struct perf_event_attr);
3670 attr.type = PERF_TYPE_HARDWARE;
3671 attr.sample_type = evsel->core.attr.sample_type & PERF_SAMPLE_MASK;
3672 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID |
3673 PERF_SAMPLE_PERIOD;
3674 if (pt->timeless_decoding)
3675 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME;
3676 else
3677 attr.sample_type |= PERF_SAMPLE_TIME;
3678 if (!pt->per_cpu_mmaps)
3679 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU;
3680 attr.exclude_user = evsel->core.attr.exclude_user;
3681 attr.exclude_kernel = evsel->core.attr.exclude_kernel;
3682 attr.exclude_hv = evsel->core.attr.exclude_hv;
3683 attr.exclude_host = evsel->core.attr.exclude_host;
3684 attr.exclude_guest = evsel->core.attr.exclude_guest;
3685 attr.sample_id_all = evsel->core.attr.sample_id_all;
3686 attr.read_format = evsel->core.attr.read_format;
3687
3688 id = evsel->core.id[0] + 1000000000;
3689 if (!id)
3690 id = 1;
3691
3692 if (pt->synth_opts.branches) {
3693 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS;
3694 attr.sample_period = 1;
3695 attr.sample_type |= PERF_SAMPLE_ADDR;
3696 err = intel_pt_synth_event(session, "branches", &attr, id);
3697 if (err)
3698 return err;
3699 pt->sample_branches = true;
3700 pt->branches_sample_type = attr.sample_type;
3701 pt->branches_id = id;
3702 id += 1;
3703 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR;
3704 }
3705
3706 if (pt->synth_opts.callchain)
3707 attr.sample_type |= PERF_SAMPLE_CALLCHAIN;
3708 if (pt->synth_opts.last_branch) {
3709 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK;
3710 /*
3711 * We don't use the hardware index, but the sample generation
3712 * code uses the new format branch_stack with this field,
3713 * so the event attributes must indicate that it's present.
3714 */
3715 attr.branch_sample_type |= PERF_SAMPLE_BRANCH_HW_INDEX;
3716 }
3717
3718 if (pt->synth_opts.instructions) {
3719 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
3720 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS)
3721 attr.sample_period =
3722 intel_pt_ns_to_ticks(pt, pt->synth_opts.period);
3723 else
3724 attr.sample_period = pt->synth_opts.period;
3725 err = intel_pt_synth_event(session, "instructions", &attr, id);
3726 if (err)
3727 return err;
3728 pt->sample_instructions = true;
3729 pt->instructions_sample_type = attr.sample_type;
3730 pt->instructions_id = id;
3731 id += 1;
3732 }
3733
3734 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD;
3735 attr.sample_period = 1;
3736
3737 if (pt->synth_opts.transactions) {
3738 attr.config = PERF_COUNT_HW_INSTRUCTIONS;
3739 err = intel_pt_synth_event(session, "transactions", &attr, id);
3740 if (err)
3741 return err;
3742 pt->sample_transactions = true;
3743 pt->transactions_sample_type = attr.sample_type;
3744 pt->transactions_id = id;
3745 intel_pt_set_event_name(evlist, id, "transactions");
3746 id += 1;
3747 }
3748
3749 attr.type = PERF_TYPE_SYNTH;
3750 attr.sample_type |= PERF_SAMPLE_RAW;
3751
3752 if (pt->synth_opts.ptwrites) {
3753 attr.config = PERF_SYNTH_INTEL_PTWRITE;
3754 err = intel_pt_synth_event(session, "ptwrite", &attr, id);
3755 if (err)
3756 return err;
3757 pt->sample_ptwrites = true;
3758 pt->ptwrites_sample_type = attr.sample_type;
3759 pt->ptwrites_id = id;
3760 intel_pt_set_event_name(evlist, id, "ptwrite");
3761 id += 1;
3762 }
3763
3764 if (pt->synth_opts.pwr_events) {
3765 pt->sample_pwr_events = true;
3766 pt->pwr_events_sample_type = attr.sample_type;
3767
3768 attr.config = PERF_SYNTH_INTEL_CBR;
3769 err = intel_pt_synth_event(session, "cbr", &attr, id);
3770 if (err)
3771 return err;
3772 pt->cbr_id = id;
3773 intel_pt_set_event_name(evlist, id, "cbr");
3774 id += 1;
3775
3776 attr.config = PERF_SYNTH_INTEL_PSB;
3777 err = intel_pt_synth_event(session, "psb", &attr, id);
3778 if (err)
3779 return err;
3780 pt->psb_id = id;
3781 intel_pt_set_event_name(evlist, id, "psb");
3782 id += 1;
3783 }
3784
3785 if (pt->synth_opts.pwr_events && (evsel->core.attr.config & INTEL_PT_CFG_PWR_EVT_EN)) {
3786 attr.config = PERF_SYNTH_INTEL_MWAIT;
3787 err = intel_pt_synth_event(session, "mwait", &attr, id);
3788 if (err)
3789 return err;
3790 pt->mwait_id = id;
3791 intel_pt_set_event_name(evlist, id, "mwait");
3792 id += 1;
3793
3794 attr.config = PERF_SYNTH_INTEL_PWRE;
3795 err = intel_pt_synth_event(session, "pwre", &attr, id);
3796 if (err)
3797 return err;
3798 pt->pwre_id = id;
3799 intel_pt_set_event_name(evlist, id, "pwre");
3800 id += 1;
3801
3802 attr.config = PERF_SYNTH_INTEL_EXSTOP;
3803 err = intel_pt_synth_event(session, "exstop", &attr, id);
3804 if (err)
3805 return err;
3806 pt->exstop_id = id;
3807 intel_pt_set_event_name(evlist, id, "exstop");
3808 id += 1;
3809
3810 attr.config = PERF_SYNTH_INTEL_PWRX;
3811 err = intel_pt_synth_event(session, "pwrx", &attr, id);
3812 if (err)
3813 return err;
3814 pt->pwrx_id = id;
3815 intel_pt_set_event_name(evlist, id, "pwrx");
3816 id += 1;
3817 }
3818
3819 if (pt->synth_opts.intr_events && (evsel->core.attr.config & INTEL_PT_CFG_EVT_EN)) {
3820 attr.config = PERF_SYNTH_INTEL_EVT;
3821 err = intel_pt_synth_event(session, "evt", &attr, id);
3822 if (err)
3823 return err;
3824 pt->evt_sample_type = attr.sample_type;
3825 pt->evt_id = id;
3826 intel_pt_set_event_name(evlist, id, "evt");
3827 id += 1;
3828 }
3829
3830 if (pt->synth_opts.intr_events && pt->cap_event_trace) {
3831 attr.config = PERF_SYNTH_INTEL_IFLAG_CHG;
3832 err = intel_pt_synth_event(session, "iflag", &attr, id);
3833 if (err)
3834 return err;
3835 pt->iflag_chg_sample_type = attr.sample_type;
3836 pt->iflag_chg_id = id;
3837 intel_pt_set_event_name(evlist, id, "iflag");
3838 id += 1;
3839 }
3840
3841 return 0;
3842}
3843
3844static void intel_pt_setup_pebs_events(struct intel_pt *pt)
3845{
3846 struct evsel *evsel;
3847
3848 if (!pt->synth_opts.other_events)
3849 return;
3850
3851 evlist__for_each_entry(pt->session->evlist, evsel) {
3852 if (evsel->core.attr.aux_output && evsel->core.id) {
3853 if (pt->single_pebs) {
3854 pt->single_pebs = false;
3855 return;
3856 }
3857 pt->single_pebs = true;
3858 pt->sample_pebs = true;
3859 pt->pebs_evsel = evsel;
3860 }
3861 }
3862}
3863
3864static struct evsel *intel_pt_find_sched_switch(struct evlist *evlist)
3865{
3866 struct evsel *evsel;
3867
3868 evlist__for_each_entry_reverse(evlist, evsel) {
3869 const char *name = evsel__name(evsel);
3870
3871 if (!strcmp(name, "sched:sched_switch"))
3872 return evsel;
3873 }
3874
3875 return NULL;
3876}
3877
3878static bool intel_pt_find_switch(struct evlist *evlist)
3879{
3880 struct evsel *evsel;
3881
3882 evlist__for_each_entry(evlist, evsel) {
3883 if (evsel->core.attr.context_switch)
3884 return true;
3885 }
3886
3887 return false;
3888}
3889
3890static int intel_pt_perf_config(const char *var, const char *value, void *data)
3891{
3892 struct intel_pt *pt = data;
3893
3894 if (!strcmp(var, "intel-pt.mispred-all"))
3895 pt->mispred_all = perf_config_bool(var, value);
3896
3897 if (!strcmp(var, "intel-pt.max-loops"))
3898 perf_config_int(&pt->max_loops, var, value);
3899
3900 return 0;
3901}
3902
3903/* Find least TSC which converts to ns or later */
3904static u64 intel_pt_tsc_start(u64 ns, struct intel_pt *pt)
3905{
3906 u64 tsc, tm;
3907
3908 tsc = perf_time_to_tsc(ns, &pt->tc);
3909
3910 while (1) {
3911 tm = tsc_to_perf_time(tsc, &pt->tc);
3912 if (tm < ns)
3913 break;
3914 tsc -= 1;
3915 }
3916
3917 while (tm < ns)
3918 tm = tsc_to_perf_time(++tsc, &pt->tc);
3919
3920 return tsc;
3921}
3922
3923/* Find greatest TSC which converts to ns or earlier */
3924static u64 intel_pt_tsc_end(u64 ns, struct intel_pt *pt)
3925{
3926 u64 tsc, tm;
3927
3928 tsc = perf_time_to_tsc(ns, &pt->tc);
3929
3930 while (1) {
3931 tm = tsc_to_perf_time(tsc, &pt->tc);
3932 if (tm > ns)
3933 break;
3934 tsc += 1;
3935 }
3936
3937 while (tm > ns)
3938 tm = tsc_to_perf_time(--tsc, &pt->tc);
3939
3940 return tsc;
3941}
3942
3943static int intel_pt_setup_time_ranges(struct intel_pt *pt,
3944 struct itrace_synth_opts *opts)
3945{
3946 struct perf_time_interval *p = opts->ptime_range;
3947 int n = opts->range_num;
3948 int i;
3949
3950 if (!n || !p || pt->timeless_decoding)
3951 return 0;
3952
3953 pt->time_ranges = calloc(n, sizeof(struct range));
3954 if (!pt->time_ranges)
3955 return -ENOMEM;
3956
3957 pt->range_cnt = n;
3958
3959 intel_pt_log("%s: %u range(s)\n", __func__, n);
3960
3961 for (i = 0; i < n; i++) {
3962 struct range *r = &pt->time_ranges[i];
3963 u64 ts = p[i].start;
3964 u64 te = p[i].end;
3965
3966 /*
3967 * Take care to ensure the TSC range matches the perf-time range
3968 * when converted back to perf-time.
3969 */
3970 r->start = ts ? intel_pt_tsc_start(ts, pt) : 0;
3971 r->end = te ? intel_pt_tsc_end(te, pt) : 0;
3972
3973 intel_pt_log("range %d: perf time interval: %"PRIu64" to %"PRIu64"\n",
3974 i, ts, te);
3975 intel_pt_log("range %d: TSC time interval: %#"PRIx64" to %#"PRIx64"\n",
3976 i, r->start, r->end);
3977 }
3978
3979 return 0;
3980}
3981
3982static int intel_pt_parse_vm_tm_corr_arg(struct intel_pt *pt, char **args)
3983{
3984 struct intel_pt_vmcs_info *vmcs_info;
3985 u64 tsc_offset, vmcs;
3986 char *p = *args;
3987
3988 errno = 0;
3989
3990 p = skip_spaces(p);
3991 if (!*p)
3992 return 1;
3993
3994 tsc_offset = strtoull(p, &p, 0);
3995 if (errno)
3996 return -errno;
3997 p = skip_spaces(p);
3998 if (*p != ':') {
3999 pt->dflt_tsc_offset = tsc_offset;
4000 *args = p;
4001 return 0;
4002 }
4003 p += 1;
4004 while (1) {
4005 vmcs = strtoull(p, &p, 0);
4006 if (errno)
4007 return -errno;
4008 if (!vmcs)
4009 return -EINVAL;
4010 vmcs_info = intel_pt_findnew_vmcs(&pt->vmcs_info, vmcs, tsc_offset);
4011 if (!vmcs_info)
4012 return -ENOMEM;
4013 p = skip_spaces(p);
4014 if (*p != ',')
4015 break;
4016 p += 1;
4017 }
4018 *args = p;
4019 return 0;
4020}
4021
4022static int intel_pt_parse_vm_tm_corr_args(struct intel_pt *pt)
4023{
4024 char *args = pt->synth_opts.vm_tm_corr_args;
4025 int ret;
4026
4027 if (!args)
4028 return 0;
4029
4030 do {
4031 ret = intel_pt_parse_vm_tm_corr_arg(pt, &args);
4032 } while (!ret);
4033
4034 if (ret < 0) {
4035 pr_err("Failed to parse VM Time Correlation options\n");
4036 return ret;
4037 }
4038
4039 return 0;
4040}
4041
4042static const char * const intel_pt_info_fmts[] = {
4043 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n",
4044 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n",
4045 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n",
4046 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n",
4047 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n",
4048 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n",
4049 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n",
4050 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n",
4051 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n",
4052 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n",
4053 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n",
4054 [INTEL_PT_MTC_FREQ_BITS] = " MTC freq bits %#"PRIx64"\n",
4055 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n",
4056 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n",
4057 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n",
4058 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n",
4059 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n",
4060};
4061
4062static void intel_pt_print_info(__u64 *arr, int start, int finish)
4063{
4064 int i;
4065
4066 if (!dump_trace)
4067 return;
4068
4069 for (i = start; i <= finish; i++) {
4070 const char *fmt = intel_pt_info_fmts[i];
4071
4072 if (fmt)
4073 fprintf(stdout, fmt, arr[i]);
4074 }
4075}
4076
4077static void intel_pt_print_info_str(const char *name, const char *str)
4078{
4079 if (!dump_trace)
4080 return;
4081
4082 fprintf(stdout, " %-20s%s\n", name, str ? str : "");
4083}
4084
4085static bool intel_pt_has(struct perf_record_auxtrace_info *auxtrace_info, int pos)
4086{
4087 return auxtrace_info->header.size >=
4088 sizeof(struct perf_record_auxtrace_info) + (sizeof(u64) * (pos + 1));
4089}
4090
4091int intel_pt_process_auxtrace_info(union perf_event *event,
4092 struct perf_session *session)
4093{
4094 struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info;
4095 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS;
4096 struct intel_pt *pt;
4097 void *info_end;
4098 __u64 *info;
4099 int err;
4100
4101 if (auxtrace_info->header.size < sizeof(struct perf_record_auxtrace_info) +
4102 min_sz)
4103 return -EINVAL;
4104
4105 pt = zalloc(sizeof(struct intel_pt));
4106 if (!pt)
4107 return -ENOMEM;
4108
4109 pt->vmcs_info = RB_ROOT;
4110
4111 addr_filters__init(&pt->filts);
4112
4113 err = perf_config(intel_pt_perf_config, pt);
4114 if (err)
4115 goto err_free;
4116
4117 err = auxtrace_queues__init(&pt->queues);
4118 if (err)
4119 goto err_free;
4120
4121 if (session->itrace_synth_opts->set) {
4122 pt->synth_opts = *session->itrace_synth_opts;
4123 } else {
4124 struct itrace_synth_opts *opts = session->itrace_synth_opts;
4125
4126 itrace_synth_opts__set_default(&pt->synth_opts, opts->default_no_sample);
4127 if (!opts->default_no_sample && !opts->inject) {
4128 pt->synth_opts.branches = false;
4129 pt->synth_opts.callchain = true;
4130 pt->synth_opts.add_callchain = true;
4131 }
4132 pt->synth_opts.thread_stack = opts->thread_stack;
4133 }
4134
4135 if (!(pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_USE_STDOUT))
4136 intel_pt_log_set_name(INTEL_PT_PMU_NAME);
4137
4138 pt->session = session;
4139 pt->machine = &session->machines.host; /* No kvm support */
4140 pt->auxtrace_type = auxtrace_info->type;
4141 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE];
4142 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT];
4143 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT];
4144 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO];
4145 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO];
4146 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT];
4147 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT];
4148 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH];
4149 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE];
4150 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS];
4151 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE,
4152 INTEL_PT_PER_CPU_MMAPS);
4153
4154 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) {
4155 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT];
4156 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS];
4157 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N];
4158 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D];
4159 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT];
4160 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT,
4161 INTEL_PT_CYC_BIT);
4162 }
4163
4164 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) {
4165 pt->max_non_turbo_ratio =
4166 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO];
4167 intel_pt_print_info(&auxtrace_info->priv[0],
4168 INTEL_PT_MAX_NONTURBO_RATIO,
4169 INTEL_PT_MAX_NONTURBO_RATIO);
4170 }
4171
4172 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1;
4173 info_end = (void *)auxtrace_info + auxtrace_info->header.size;
4174
4175 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) {
4176 size_t len;
4177
4178 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN];
4179 intel_pt_print_info(&auxtrace_info->priv[0],
4180 INTEL_PT_FILTER_STR_LEN,
4181 INTEL_PT_FILTER_STR_LEN);
4182 if (len) {
4183 const char *filter = (const char *)info;
4184
4185 len = roundup(len + 1, 8);
4186 info += len >> 3;
4187 if ((void *)info > info_end) {
4188 pr_err("%s: bad filter string length\n", __func__);
4189 err = -EINVAL;
4190 goto err_free_queues;
4191 }
4192 pt->filter = memdup(filter, len);
4193 if (!pt->filter) {
4194 err = -ENOMEM;
4195 goto err_free_queues;
4196 }
4197 if (session->header.needs_swap)
4198 mem_bswap_64(pt->filter, len);
4199 if (pt->filter[len - 1]) {
4200 pr_err("%s: filter string not null terminated\n", __func__);
4201 err = -EINVAL;
4202 goto err_free_queues;
4203 }
4204 err = addr_filters__parse_bare_filter(&pt->filts,
4205 filter);
4206 if (err)
4207 goto err_free_queues;
4208 }
4209 intel_pt_print_info_str("Filter string", pt->filter);
4210 }
4211
4212 if ((void *)info < info_end) {
4213 pt->cap_event_trace = *info++;
4214 if (dump_trace)
4215 fprintf(stdout, " Cap Event Trace %d\n",
4216 pt->cap_event_trace);
4217 }
4218
4219 pt->timeless_decoding = intel_pt_timeless_decoding(pt);
4220 if (pt->timeless_decoding && !pt->tc.time_mult)
4221 pt->tc.time_mult = 1;
4222 pt->have_tsc = intel_pt_have_tsc(pt);
4223 pt->sampling_mode = intel_pt_sampling_mode(pt);
4224 pt->est_tsc = !pt->timeless_decoding;
4225
4226 if (pt->synth_opts.vm_time_correlation) {
4227 if (pt->timeless_decoding) {
4228 pr_err("Intel PT has no time information for VM Time Correlation\n");
4229 err = -EINVAL;
4230 goto err_free_queues;
4231 }
4232 if (session->itrace_synth_opts->ptime_range) {
4233 pr_err("Time ranges cannot be specified with VM Time Correlation\n");
4234 err = -EINVAL;
4235 goto err_free_queues;
4236 }
4237 /* Currently TSC Offset is calculated using MTC packets */
4238 if (!intel_pt_have_mtc(pt)) {
4239 pr_err("MTC packets must have been enabled for VM Time Correlation\n");
4240 err = -EINVAL;
4241 goto err_free_queues;
4242 }
4243 err = intel_pt_parse_vm_tm_corr_args(pt);
4244 if (err)
4245 goto err_free_queues;
4246 }
4247
4248 pt->unknown_thread = thread__new(999999999, 999999999);
4249 if (!pt->unknown_thread) {
4250 err = -ENOMEM;
4251 goto err_free_queues;
4252 }
4253
4254 /*
4255 * Since this thread will not be kept in any rbtree not in a
4256 * list, initialize its list node so that at thread__put() the
4257 * current thread lifetime assumption is kept and we don't segfault
4258 * at list_del_init().
4259 */
4260 INIT_LIST_HEAD(&pt->unknown_thread->node);
4261
4262 err = thread__set_comm(pt->unknown_thread, "unknown", 0);
4263 if (err)
4264 goto err_delete_thread;
4265 if (thread__init_maps(pt->unknown_thread, pt->machine)) {
4266 err = -ENOMEM;
4267 goto err_delete_thread;
4268 }
4269
4270 pt->auxtrace.process_event = intel_pt_process_event;
4271 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event;
4272 pt->auxtrace.queue_data = intel_pt_queue_data;
4273 pt->auxtrace.dump_auxtrace_sample = intel_pt_dump_sample;
4274 pt->auxtrace.flush_events = intel_pt_flush;
4275 pt->auxtrace.free_events = intel_pt_free_events;
4276 pt->auxtrace.free = intel_pt_free;
4277 pt->auxtrace.evsel_is_auxtrace = intel_pt_evsel_is_auxtrace;
4278 session->auxtrace = &pt->auxtrace;
4279
4280 if (dump_trace)
4281 return 0;
4282
4283 if (pt->have_sched_switch == 1) {
4284 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist);
4285 if (!pt->switch_evsel) {
4286 pr_err("%s: missing sched_switch event\n", __func__);
4287 err = -EINVAL;
4288 goto err_delete_thread;
4289 }
4290 } else if (pt->have_sched_switch == 2 &&
4291 !intel_pt_find_switch(session->evlist)) {
4292 pr_err("%s: missing context_switch attribute flag\n", __func__);
4293 err = -EINVAL;
4294 goto err_delete_thread;
4295 }
4296
4297 if (pt->synth_opts.log) {
4298 bool log_on_error = pt->synth_opts.log_plus_flags & AUXTRACE_LOG_FLG_ON_ERROR;
4299 unsigned int log_on_error_size = pt->synth_opts.log_on_error_size;
4300
4301 intel_pt_log_enable(log_on_error, log_on_error_size);
4302 }
4303
4304 /* Maximum non-turbo ratio is TSC freq / 100 MHz */
4305 if (pt->tc.time_mult) {
4306 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000);
4307
4308 if (!pt->max_non_turbo_ratio)
4309 pt->max_non_turbo_ratio =
4310 (tsc_freq + 50000000) / 100000000;
4311 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq);
4312 intel_pt_log("Maximum non-turbo ratio %u\n",
4313 pt->max_non_turbo_ratio);
4314 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000;
4315 }
4316
4317 err = intel_pt_setup_time_ranges(pt, session->itrace_synth_opts);
4318 if (err)
4319 goto err_delete_thread;
4320
4321 if (pt->synth_opts.calls)
4322 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC |
4323 PERF_IP_FLAG_TRACE_END;
4324 if (pt->synth_opts.returns)
4325 pt->branches_filter |= PERF_IP_FLAG_RETURN |
4326 PERF_IP_FLAG_TRACE_BEGIN;
4327
4328 if ((pt->synth_opts.callchain || pt->synth_opts.add_callchain) &&
4329 !symbol_conf.use_callchain) {
4330 symbol_conf.use_callchain = true;
4331 if (callchain_register_param(&callchain_param) < 0) {
4332 symbol_conf.use_callchain = false;
4333 pt->synth_opts.callchain = false;
4334 pt->synth_opts.add_callchain = false;
4335 }
4336 }
4337
4338 if (pt->synth_opts.add_callchain) {
4339 err = intel_pt_callchain_init(pt);
4340 if (err)
4341 goto err_delete_thread;
4342 }
4343
4344 if (pt->synth_opts.last_branch || pt->synth_opts.add_last_branch) {
4345 pt->br_stack_sz = pt->synth_opts.last_branch_sz;
4346 pt->br_stack_sz_plus = pt->br_stack_sz;
4347 }
4348
4349 if (pt->synth_opts.add_last_branch) {
4350 err = intel_pt_br_stack_init(pt);
4351 if (err)
4352 goto err_delete_thread;
4353 /*
4354 * Additional branch stack size to cater for tracing from the
4355 * actual sample ip to where the sample time is recorded.
4356 * Measured at about 200 branches, but generously set to 1024.
4357 * If kernel space is not being traced, then add just 1 for the
4358 * branch to kernel space.
4359 */
4360 if (intel_pt_tracing_kernel(pt))
4361 pt->br_stack_sz_plus += 1024;
4362 else
4363 pt->br_stack_sz_plus += 1;
4364 }
4365
4366 pt->use_thread_stack = pt->synth_opts.callchain ||
4367 pt->synth_opts.add_callchain ||
4368 pt->synth_opts.thread_stack ||
4369 pt->synth_opts.last_branch ||
4370 pt->synth_opts.add_last_branch;
4371
4372 pt->callstack = pt->synth_opts.callchain ||
4373 pt->synth_opts.add_callchain ||
4374 pt->synth_opts.thread_stack;
4375
4376 err = intel_pt_synth_events(pt, session);
4377 if (err)
4378 goto err_delete_thread;
4379
4380 intel_pt_setup_pebs_events(pt);
4381
4382 if (pt->sampling_mode || list_empty(&session->auxtrace_index))
4383 err = auxtrace_queue_data(session, true, true);
4384 else
4385 err = auxtrace_queues__process_index(&pt->queues, session);
4386 if (err)
4387 goto err_delete_thread;
4388
4389 if (pt->queues.populated)
4390 pt->data_queued = true;
4391
4392 if (pt->timeless_decoding)
4393 pr_debug2("Intel PT decoding without timestamps\n");
4394
4395 return 0;
4396
4397err_delete_thread:
4398 zfree(&pt->chain);
4399 thread__zput(pt->unknown_thread);
4400err_free_queues:
4401 intel_pt_log_disable();
4402 auxtrace_queues__free(&pt->queues);
4403 session->auxtrace = NULL;
4404err_free:
4405 addr_filters__exit(&pt->filts);
4406 zfree(&pt->filter);
4407 zfree(&pt->time_ranges);
4408 free(pt);
4409 return err;
4410}