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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/uaccess.h>
11#include <uapi/linux/sched/types.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_irq.h>
17#include <drm/drm_prime.h>
18#include <drm/drm_of.h>
19#include <drm/drm_vblank.h>
20
21#include "msm_drv.h"
22#include "msm_debugfs.h"
23#include "msm_fence.h"
24#include "msm_gem.h"
25#include "msm_gpu.h"
26#include "msm_kms.h"
27#include "adreno/adreno_gpu.h"
28
29/*
30 * MSM driver version:
31 * - 1.0.0 - initial interface
32 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
33 * - 1.2.0 - adds explicit fence support for submit ioctl
34 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
35 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
36 * MSM_GEM_INFO ioctl.
37 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
38 * GEM object's debug name
39 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
40 */
41#define MSM_VERSION_MAJOR 1
42#define MSM_VERSION_MINOR 5
43#define MSM_VERSION_PATCHLEVEL 0
44
45static const struct drm_mode_config_funcs mode_config_funcs = {
46 .fb_create = msm_framebuffer_create,
47 .output_poll_changed = drm_fb_helper_output_poll_changed,
48 .atomic_check = drm_atomic_helper_check,
49 .atomic_commit = drm_atomic_helper_commit,
50};
51
52static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
53 .atomic_commit_tail = msm_atomic_commit_tail,
54};
55
56#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
57static bool reglog = false;
58MODULE_PARM_DESC(reglog, "Enable register read/write logging");
59module_param(reglog, bool, 0600);
60#else
61#define reglog 0
62#endif
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate = false;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82/*
83 * Util/helpers:
84 */
85
86struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
87 const char *name)
88{
89 int i;
90 char n[32];
91
92 snprintf(n, sizeof(n), "%s_clk", name);
93
94 for (i = 0; bulk && i < count; i++) {
95 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
96 return bulk[i].clk;
97 }
98
99
100 return NULL;
101}
102
103struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
104{
105 struct clk *clk;
106 char name2[32];
107
108 clk = devm_clk_get(&pdev->dev, name);
109 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
110 return clk;
111
112 snprintf(name2, sizeof(name2), "%s_clk", name);
113
114 clk = devm_clk_get(&pdev->dev, name2);
115 if (!IS_ERR(clk))
116 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
117 "\"%s\" instead of \"%s\"\n", name, name2);
118
119 return clk;
120}
121
122void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
123 const char *dbgname)
124{
125 struct resource *res;
126 unsigned long size;
127 void __iomem *ptr;
128
129 if (name)
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
131 else
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133
134 if (!res) {
135 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
136 return ERR_PTR(-EINVAL);
137 }
138
139 size = resource_size(res);
140
141 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
142 if (!ptr) {
143 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
144 return ERR_PTR(-ENOMEM);
145 }
146
147 if (reglog)
148 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
149
150 return ptr;
151}
152
153void msm_writel(u32 data, void __iomem *addr)
154{
155 if (reglog)
156 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
157 writel(data, addr);
158}
159
160u32 msm_readl(const void __iomem *addr)
161{
162 u32 val = readl(addr);
163 if (reglog)
164 pr_err("IO:R %p %08x\n", addr, val);
165 return val;
166}
167
168struct msm_vblank_work {
169 struct work_struct work;
170 int crtc_id;
171 bool enable;
172 struct msm_drm_private *priv;
173};
174
175static void vblank_ctrl_worker(struct work_struct *work)
176{
177 struct msm_vblank_work *vbl_work = container_of(work,
178 struct msm_vblank_work, work);
179 struct msm_drm_private *priv = vbl_work->priv;
180 struct msm_kms *kms = priv->kms;
181
182 if (vbl_work->enable)
183 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
184 else
185 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
186
187 kfree(vbl_work);
188}
189
190static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
191 int crtc_id, bool enable)
192{
193 struct msm_vblank_work *vbl_work;
194
195 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
196 if (!vbl_work)
197 return -ENOMEM;
198
199 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
200
201 vbl_work->crtc_id = crtc_id;
202 vbl_work->enable = enable;
203 vbl_work->priv = priv;
204
205 queue_work(priv->wq, &vbl_work->work);
206
207 return 0;
208}
209
210static int msm_drm_uninit(struct device *dev)
211{
212 struct platform_device *pdev = to_platform_device(dev);
213 struct drm_device *ddev = platform_get_drvdata(pdev);
214 struct msm_drm_private *priv = ddev->dev_private;
215 struct msm_kms *kms = priv->kms;
216 struct msm_mdss *mdss = priv->mdss;
217 int i;
218
219 /*
220 * Shutdown the hw if we're far enough along where things might be on.
221 * If we run this too early, we'll end up panicking in any variety of
222 * places. Since we don't register the drm device until late in
223 * msm_drm_init, drm_dev->registered is used as an indicator that the
224 * shutdown will be successful.
225 */
226 if (ddev->registered) {
227 drm_dev_unregister(ddev);
228 drm_atomic_helper_shutdown(ddev);
229 }
230
231 /* We must cancel and cleanup any pending vblank enable/disable
232 * work before drm_irq_uninstall() to avoid work re-enabling an
233 * irq after uninstall has disabled it.
234 */
235
236 flush_workqueue(priv->wq);
237
238 /* clean up event worker threads */
239 for (i = 0; i < priv->num_crtcs; i++) {
240 if (priv->event_thread[i].thread) {
241 kthread_destroy_worker(&priv->event_thread[i].worker);
242 priv->event_thread[i].thread = NULL;
243 }
244 }
245
246 msm_gem_shrinker_cleanup(ddev);
247
248 drm_kms_helper_poll_fini(ddev);
249
250 msm_perf_debugfs_cleanup(priv);
251 msm_rd_debugfs_cleanup(priv);
252
253#ifdef CONFIG_DRM_FBDEV_EMULATION
254 if (fbdev && priv->fbdev)
255 msm_fbdev_free(ddev);
256#endif
257
258 drm_mode_config_cleanup(ddev);
259
260 pm_runtime_get_sync(dev);
261 drm_irq_uninstall(ddev);
262 pm_runtime_put_sync(dev);
263
264 if (kms && kms->funcs)
265 kms->funcs->destroy(kms);
266
267 if (priv->vram.paddr) {
268 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
269 drm_mm_takedown(&priv->vram.mm);
270 dma_free_attrs(dev, priv->vram.size, NULL,
271 priv->vram.paddr, attrs);
272 }
273
274 component_unbind_all(dev, ddev);
275
276 if (mdss && mdss->funcs)
277 mdss->funcs->destroy(ddev);
278
279 ddev->dev_private = NULL;
280 drm_dev_put(ddev);
281
282 destroy_workqueue(priv->wq);
283 kfree(priv);
284
285 return 0;
286}
287
288#define KMS_MDP4 4
289#define KMS_MDP5 5
290#define KMS_DPU 3
291
292static int get_mdp_ver(struct platform_device *pdev)
293{
294 struct device *dev = &pdev->dev;
295
296 return (int) (unsigned long) of_device_get_match_data(dev);
297}
298
299#include <linux/of_address.h>
300
301bool msm_use_mmu(struct drm_device *dev)
302{
303 struct msm_drm_private *priv = dev->dev_private;
304
305 /* a2xx comes with its own MMU */
306 return priv->is_a2xx || iommu_present(&platform_bus_type);
307}
308
309static int msm_init_vram(struct drm_device *dev)
310{
311 struct msm_drm_private *priv = dev->dev_private;
312 struct device_node *node;
313 unsigned long size = 0;
314 int ret = 0;
315
316 /* In the device-tree world, we could have a 'memory-region'
317 * phandle, which gives us a link to our "vram". Allocating
318 * is all nicely abstracted behind the dma api, but we need
319 * to know the entire size to allocate it all in one go. There
320 * are two cases:
321 * 1) device with no IOMMU, in which case we need exclusive
322 * access to a VRAM carveout big enough for all gpu
323 * buffers
324 * 2) device with IOMMU, but where the bootloader puts up
325 * a splash screen. In this case, the VRAM carveout
326 * need only be large enough for fbdev fb. But we need
327 * exclusive access to the buffer to avoid the kernel
328 * using those pages for other purposes (which appears
329 * as corruption on screen before we have a chance to
330 * load and do initial modeset)
331 */
332
333 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
334 if (node) {
335 struct resource r;
336 ret = of_address_to_resource(node, 0, &r);
337 of_node_put(node);
338 if (ret)
339 return ret;
340 size = r.end - r.start;
341 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
342
343 /* if we have no IOMMU, then we need to use carveout allocator.
344 * Grab the entire CMA chunk carved out in early startup in
345 * mach-msm:
346 */
347 } else if (!msm_use_mmu(dev)) {
348 DRM_INFO("using %s VRAM carveout\n", vram);
349 size = memparse(vram, NULL);
350 }
351
352 if (size) {
353 unsigned long attrs = 0;
354 void *p;
355
356 priv->vram.size = size;
357
358 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
359 spin_lock_init(&priv->vram.lock);
360
361 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
362 attrs |= DMA_ATTR_WRITE_COMBINE;
363
364 /* note that for no-kernel-mapping, the vaddr returned
365 * is bogus, but non-null if allocation succeeded:
366 */
367 p = dma_alloc_attrs(dev->dev, size,
368 &priv->vram.paddr, GFP_KERNEL, attrs);
369 if (!p) {
370 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
371 priv->vram.paddr = 0;
372 return -ENOMEM;
373 }
374
375 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
376 (uint32_t)priv->vram.paddr,
377 (uint32_t)(priv->vram.paddr + size));
378 }
379
380 return ret;
381}
382
383static int msm_drm_init(struct device *dev, struct drm_driver *drv)
384{
385 struct platform_device *pdev = to_platform_device(dev);
386 struct drm_device *ddev;
387 struct msm_drm_private *priv;
388 struct msm_kms *kms;
389 struct msm_mdss *mdss;
390 int ret, i;
391 struct sched_param param;
392
393 ddev = drm_dev_alloc(drv, dev);
394 if (IS_ERR(ddev)) {
395 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
396 return PTR_ERR(ddev);
397 }
398
399 platform_set_drvdata(pdev, ddev);
400
401 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
402 if (!priv) {
403 ret = -ENOMEM;
404 goto err_put_drm_dev;
405 }
406
407 ddev->dev_private = priv;
408 priv->dev = ddev;
409
410 switch (get_mdp_ver(pdev)) {
411 case KMS_MDP5:
412 ret = mdp5_mdss_init(ddev);
413 break;
414 case KMS_DPU:
415 ret = dpu_mdss_init(ddev);
416 break;
417 default:
418 ret = 0;
419 break;
420 }
421 if (ret)
422 goto err_free_priv;
423
424 mdss = priv->mdss;
425
426 priv->wq = alloc_ordered_workqueue("msm", 0);
427
428 INIT_WORK(&priv->free_work, msm_gem_free_work);
429 init_llist_head(&priv->free_list);
430
431 INIT_LIST_HEAD(&priv->inactive_list);
432
433 drm_mode_config_init(ddev);
434
435 /* Bind all our sub-components: */
436 ret = component_bind_all(dev, ddev);
437 if (ret)
438 goto err_destroy_mdss;
439
440 ret = msm_init_vram(ddev);
441 if (ret)
442 goto err_msm_uninit;
443
444 msm_gem_shrinker_init(ddev);
445
446 switch (get_mdp_ver(pdev)) {
447 case KMS_MDP4:
448 kms = mdp4_kms_init(ddev);
449 priv->kms = kms;
450 break;
451 case KMS_MDP5:
452 kms = mdp5_kms_init(ddev);
453 break;
454 case KMS_DPU:
455 kms = dpu_kms_init(ddev);
456 priv->kms = kms;
457 break;
458 default:
459 /* valid only for the dummy headless case, where of_node=NULL */
460 WARN_ON(dev->of_node);
461 kms = NULL;
462 break;
463 }
464
465 if (IS_ERR(kms)) {
466 DRM_DEV_ERROR(dev, "failed to load kms\n");
467 ret = PTR_ERR(kms);
468 priv->kms = NULL;
469 goto err_msm_uninit;
470 }
471
472 /* Enable normalization of plane zpos */
473 ddev->mode_config.normalize_zpos = true;
474
475 if (kms) {
476 kms->dev = ddev;
477 ret = kms->funcs->hw_init(kms);
478 if (ret) {
479 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
480 goto err_msm_uninit;
481 }
482 }
483
484 ddev->mode_config.funcs = &mode_config_funcs;
485 ddev->mode_config.helper_private = &mode_config_helper_funcs;
486
487 /**
488 * this priority was found during empiric testing to have appropriate
489 * realtime scheduling to process display updates and interact with
490 * other real time and normal priority task
491 */
492 param.sched_priority = 16;
493 for (i = 0; i < priv->num_crtcs; i++) {
494 /* initialize event thread */
495 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
496 kthread_init_worker(&priv->event_thread[i].worker);
497 priv->event_thread[i].dev = ddev;
498 priv->event_thread[i].thread =
499 kthread_run(kthread_worker_fn,
500 &priv->event_thread[i].worker,
501 "crtc_event:%d", priv->event_thread[i].crtc_id);
502 if (IS_ERR(priv->event_thread[i].thread)) {
503 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
504 priv->event_thread[i].thread = NULL;
505 goto err_msm_uninit;
506 }
507
508 ret = sched_setscheduler(priv->event_thread[i].thread,
509 SCHED_FIFO, ¶m);
510 if (ret)
511 dev_warn(dev, "event_thread set priority failed:%d\n",
512 ret);
513 }
514
515 ret = drm_vblank_init(ddev, priv->num_crtcs);
516 if (ret < 0) {
517 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
518 goto err_msm_uninit;
519 }
520
521 if (kms) {
522 pm_runtime_get_sync(dev);
523 ret = drm_irq_install(ddev, kms->irq);
524 pm_runtime_put_sync(dev);
525 if (ret < 0) {
526 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
527 goto err_msm_uninit;
528 }
529 }
530
531 ret = drm_dev_register(ddev, 0);
532 if (ret)
533 goto err_msm_uninit;
534
535 drm_mode_config_reset(ddev);
536
537#ifdef CONFIG_DRM_FBDEV_EMULATION
538 if (kms && fbdev)
539 priv->fbdev = msm_fbdev_init(ddev);
540#endif
541
542 ret = msm_debugfs_late_init(ddev);
543 if (ret)
544 goto err_msm_uninit;
545
546 drm_kms_helper_poll_init(ddev);
547
548 return 0;
549
550err_msm_uninit:
551 msm_drm_uninit(dev);
552 return ret;
553err_destroy_mdss:
554 if (mdss && mdss->funcs)
555 mdss->funcs->destroy(ddev);
556err_free_priv:
557 kfree(priv);
558err_put_drm_dev:
559 drm_dev_put(ddev);
560 return ret;
561}
562
563/*
564 * DRM operations:
565 */
566
567static void load_gpu(struct drm_device *dev)
568{
569 static DEFINE_MUTEX(init_lock);
570 struct msm_drm_private *priv = dev->dev_private;
571
572 mutex_lock(&init_lock);
573
574 if (!priv->gpu)
575 priv->gpu = adreno_load_gpu(dev);
576
577 mutex_unlock(&init_lock);
578}
579
580static int context_init(struct drm_device *dev, struct drm_file *file)
581{
582 struct msm_drm_private *priv = dev->dev_private;
583 struct msm_file_private *ctx;
584
585 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
586 if (!ctx)
587 return -ENOMEM;
588
589 msm_submitqueue_init(dev, ctx);
590
591 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
592 file->driver_priv = ctx;
593
594 return 0;
595}
596
597static int msm_open(struct drm_device *dev, struct drm_file *file)
598{
599 /* For now, load gpu on open.. to avoid the requirement of having
600 * firmware in the initrd.
601 */
602 load_gpu(dev);
603
604 return context_init(dev, file);
605}
606
607static void context_close(struct msm_file_private *ctx)
608{
609 msm_submitqueue_close(ctx);
610 kfree(ctx);
611}
612
613static void msm_postclose(struct drm_device *dev, struct drm_file *file)
614{
615 struct msm_drm_private *priv = dev->dev_private;
616 struct msm_file_private *ctx = file->driver_priv;
617
618 mutex_lock(&dev->struct_mutex);
619 if (ctx == priv->lastctx)
620 priv->lastctx = NULL;
621 mutex_unlock(&dev->struct_mutex);
622
623 context_close(ctx);
624}
625
626static irqreturn_t msm_irq(int irq, void *arg)
627{
628 struct drm_device *dev = arg;
629 struct msm_drm_private *priv = dev->dev_private;
630 struct msm_kms *kms = priv->kms;
631 BUG_ON(!kms);
632 return kms->funcs->irq(kms);
633}
634
635static void msm_irq_preinstall(struct drm_device *dev)
636{
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
639 BUG_ON(!kms);
640 kms->funcs->irq_preinstall(kms);
641}
642
643static int msm_irq_postinstall(struct drm_device *dev)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_kms *kms = priv->kms;
647 BUG_ON(!kms);
648
649 if (kms->funcs->irq_postinstall)
650 return kms->funcs->irq_postinstall(kms);
651
652 return 0;
653}
654
655static void msm_irq_uninstall(struct drm_device *dev)
656{
657 struct msm_drm_private *priv = dev->dev_private;
658 struct msm_kms *kms = priv->kms;
659 BUG_ON(!kms);
660 kms->funcs->irq_uninstall(kms);
661}
662
663static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
664{
665 struct msm_drm_private *priv = dev->dev_private;
666 struct msm_kms *kms = priv->kms;
667 if (!kms)
668 return -ENXIO;
669 DBG("dev=%p, crtc=%u", dev, pipe);
670 return vblank_ctrl_queue_work(priv, pipe, true);
671}
672
673static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
674{
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
677 if (!kms)
678 return;
679 DBG("dev=%p, crtc=%u", dev, pipe);
680 vblank_ctrl_queue_work(priv, pipe, false);
681}
682
683/*
684 * DRM ioctls:
685 */
686
687static int msm_ioctl_get_param(struct drm_device *dev, void *data,
688 struct drm_file *file)
689{
690 struct msm_drm_private *priv = dev->dev_private;
691 struct drm_msm_param *args = data;
692 struct msm_gpu *gpu;
693
694 /* for now, we just have 3d pipe.. eventually this would need to
695 * be more clever to dispatch to appropriate gpu module:
696 */
697 if (args->pipe != MSM_PIPE_3D0)
698 return -EINVAL;
699
700 gpu = priv->gpu;
701
702 if (!gpu)
703 return -ENXIO;
704
705 return gpu->funcs->get_param(gpu, args->param, &args->value);
706}
707
708static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
709 struct drm_file *file)
710{
711 struct drm_msm_gem_new *args = data;
712
713 if (args->flags & ~MSM_BO_FLAGS) {
714 DRM_ERROR("invalid flags: %08x\n", args->flags);
715 return -EINVAL;
716 }
717
718 return msm_gem_new_handle(dev, file, args->size,
719 args->flags, &args->handle, NULL);
720}
721
722static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
723{
724 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
725}
726
727static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
728 struct drm_file *file)
729{
730 struct drm_msm_gem_cpu_prep *args = data;
731 struct drm_gem_object *obj;
732 ktime_t timeout = to_ktime(args->timeout);
733 int ret;
734
735 if (args->op & ~MSM_PREP_FLAGS) {
736 DRM_ERROR("invalid op: %08x\n", args->op);
737 return -EINVAL;
738 }
739
740 obj = drm_gem_object_lookup(file, args->handle);
741 if (!obj)
742 return -ENOENT;
743
744 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
745
746 drm_gem_object_put_unlocked(obj);
747
748 return ret;
749}
750
751static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
752 struct drm_file *file)
753{
754 struct drm_msm_gem_cpu_fini *args = data;
755 struct drm_gem_object *obj;
756 int ret;
757
758 obj = drm_gem_object_lookup(file, args->handle);
759 if (!obj)
760 return -ENOENT;
761
762 ret = msm_gem_cpu_fini(obj);
763
764 drm_gem_object_put_unlocked(obj);
765
766 return ret;
767}
768
769static int msm_ioctl_gem_info_iova(struct drm_device *dev,
770 struct drm_gem_object *obj, uint64_t *iova)
771{
772 struct msm_drm_private *priv = dev->dev_private;
773
774 if (!priv->gpu)
775 return -EINVAL;
776
777 /*
778 * Don't pin the memory here - just get an address so that userspace can
779 * be productive
780 */
781 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
782}
783
784static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
785 struct drm_file *file)
786{
787 struct drm_msm_gem_info *args = data;
788 struct drm_gem_object *obj;
789 struct msm_gem_object *msm_obj;
790 int i, ret = 0;
791
792 if (args->pad)
793 return -EINVAL;
794
795 switch (args->info) {
796 case MSM_INFO_GET_OFFSET:
797 case MSM_INFO_GET_IOVA:
798 /* value returned as immediate, not pointer, so len==0: */
799 if (args->len)
800 return -EINVAL;
801 break;
802 case MSM_INFO_SET_NAME:
803 case MSM_INFO_GET_NAME:
804 break;
805 default:
806 return -EINVAL;
807 }
808
809 obj = drm_gem_object_lookup(file, args->handle);
810 if (!obj)
811 return -ENOENT;
812
813 msm_obj = to_msm_bo(obj);
814
815 switch (args->info) {
816 case MSM_INFO_GET_OFFSET:
817 args->value = msm_gem_mmap_offset(obj);
818 break;
819 case MSM_INFO_GET_IOVA:
820 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
821 break;
822 case MSM_INFO_SET_NAME:
823 /* length check should leave room for terminating null: */
824 if (args->len >= sizeof(msm_obj->name)) {
825 ret = -EINVAL;
826 break;
827 }
828 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
829 args->len)) {
830 msm_obj->name[0] = '\0';
831 ret = -EFAULT;
832 break;
833 }
834 msm_obj->name[args->len] = '\0';
835 for (i = 0; i < args->len; i++) {
836 if (!isprint(msm_obj->name[i])) {
837 msm_obj->name[i] = '\0';
838 break;
839 }
840 }
841 break;
842 case MSM_INFO_GET_NAME:
843 if (args->value && (args->len < strlen(msm_obj->name))) {
844 ret = -EINVAL;
845 break;
846 }
847 args->len = strlen(msm_obj->name);
848 if (args->value) {
849 if (copy_to_user(u64_to_user_ptr(args->value),
850 msm_obj->name, args->len))
851 ret = -EFAULT;
852 }
853 break;
854 }
855
856 drm_gem_object_put_unlocked(obj);
857
858 return ret;
859}
860
861static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
862 struct drm_file *file)
863{
864 struct msm_drm_private *priv = dev->dev_private;
865 struct drm_msm_wait_fence *args = data;
866 ktime_t timeout = to_ktime(args->timeout);
867 struct msm_gpu_submitqueue *queue;
868 struct msm_gpu *gpu = priv->gpu;
869 int ret;
870
871 if (args->pad) {
872 DRM_ERROR("invalid pad: %08x\n", args->pad);
873 return -EINVAL;
874 }
875
876 if (!gpu)
877 return 0;
878
879 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
880 if (!queue)
881 return -ENOENT;
882
883 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
884 true);
885
886 msm_submitqueue_put(queue);
887 return ret;
888}
889
890static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
891 struct drm_file *file)
892{
893 struct drm_msm_gem_madvise *args = data;
894 struct drm_gem_object *obj;
895 int ret;
896
897 switch (args->madv) {
898 case MSM_MADV_DONTNEED:
899 case MSM_MADV_WILLNEED:
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 ret = mutex_lock_interruptible(&dev->struct_mutex);
906 if (ret)
907 return ret;
908
909 obj = drm_gem_object_lookup(file, args->handle);
910 if (!obj) {
911 ret = -ENOENT;
912 goto unlock;
913 }
914
915 ret = msm_gem_madvise(obj, args->madv);
916 if (ret >= 0) {
917 args->retained = ret;
918 ret = 0;
919 }
920
921 drm_gem_object_put(obj);
922
923unlock:
924 mutex_unlock(&dev->struct_mutex);
925 return ret;
926}
927
928
929static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
930 struct drm_file *file)
931{
932 struct drm_msm_submitqueue *args = data;
933
934 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
935 return -EINVAL;
936
937 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
938 args->flags, &args->id);
939}
940
941static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
942 struct drm_file *file)
943{
944 return msm_submitqueue_query(dev, file->driver_priv, data);
945}
946
947static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
948 struct drm_file *file)
949{
950 u32 id = *(u32 *) data;
951
952 return msm_submitqueue_remove(file->driver_priv, id);
953}
954
955static const struct drm_ioctl_desc msm_ioctls[] = {
956 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
957 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
959 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
963 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
965 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
967};
968
969static const struct vm_operations_struct vm_ops = {
970 .fault = msm_gem_fault,
971 .open = drm_gem_vm_open,
972 .close = drm_gem_vm_close,
973};
974
975static const struct file_operations fops = {
976 .owner = THIS_MODULE,
977 .open = drm_open,
978 .release = drm_release,
979 .unlocked_ioctl = drm_ioctl,
980 .compat_ioctl = drm_compat_ioctl,
981 .poll = drm_poll,
982 .read = drm_read,
983 .llseek = no_llseek,
984 .mmap = msm_gem_mmap,
985};
986
987static struct drm_driver msm_driver = {
988 .driver_features = DRIVER_GEM |
989 DRIVER_RENDER |
990 DRIVER_ATOMIC |
991 DRIVER_MODESET,
992 .open = msm_open,
993 .postclose = msm_postclose,
994 .lastclose = drm_fb_helper_lastclose,
995 .irq_handler = msm_irq,
996 .irq_preinstall = msm_irq_preinstall,
997 .irq_postinstall = msm_irq_postinstall,
998 .irq_uninstall = msm_irq_uninstall,
999 .enable_vblank = msm_enable_vblank,
1000 .disable_vblank = msm_disable_vblank,
1001 .gem_free_object_unlocked = msm_gem_free_object,
1002 .gem_vm_ops = &vm_ops,
1003 .dumb_create = msm_gem_dumb_create,
1004 .dumb_map_offset = msm_gem_dumb_map_offset,
1005 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1006 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1007 .gem_prime_pin = msm_gem_prime_pin,
1008 .gem_prime_unpin = msm_gem_prime_unpin,
1009 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1010 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1011 .gem_prime_vmap = msm_gem_prime_vmap,
1012 .gem_prime_vunmap = msm_gem_prime_vunmap,
1013 .gem_prime_mmap = msm_gem_prime_mmap,
1014#ifdef CONFIG_DEBUG_FS
1015 .debugfs_init = msm_debugfs_init,
1016#endif
1017 .ioctls = msm_ioctls,
1018 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1019 .fops = &fops,
1020 .name = "msm",
1021 .desc = "MSM Snapdragon DRM",
1022 .date = "20130625",
1023 .major = MSM_VERSION_MAJOR,
1024 .minor = MSM_VERSION_MINOR,
1025 .patchlevel = MSM_VERSION_PATCHLEVEL,
1026};
1027
1028#ifdef CONFIG_PM_SLEEP
1029static int msm_pm_suspend(struct device *dev)
1030{
1031 struct drm_device *ddev = dev_get_drvdata(dev);
1032 struct msm_drm_private *priv = ddev->dev_private;
1033
1034 if (WARN_ON(priv->pm_state))
1035 drm_atomic_state_put(priv->pm_state);
1036
1037 priv->pm_state = drm_atomic_helper_suspend(ddev);
1038 if (IS_ERR(priv->pm_state)) {
1039 int ret = PTR_ERR(priv->pm_state);
1040 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1041 return ret;
1042 }
1043
1044 return 0;
1045}
1046
1047static int msm_pm_resume(struct device *dev)
1048{
1049 struct drm_device *ddev = dev_get_drvdata(dev);
1050 struct msm_drm_private *priv = ddev->dev_private;
1051 int ret;
1052
1053 if (WARN_ON(!priv->pm_state))
1054 return -ENOENT;
1055
1056 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1057 if (!ret)
1058 priv->pm_state = NULL;
1059
1060 return ret;
1061}
1062#endif
1063
1064#ifdef CONFIG_PM
1065static int msm_runtime_suspend(struct device *dev)
1066{
1067 struct drm_device *ddev = dev_get_drvdata(dev);
1068 struct msm_drm_private *priv = ddev->dev_private;
1069 struct msm_mdss *mdss = priv->mdss;
1070
1071 DBG("");
1072
1073 if (mdss && mdss->funcs)
1074 return mdss->funcs->disable(mdss);
1075
1076 return 0;
1077}
1078
1079static int msm_runtime_resume(struct device *dev)
1080{
1081 struct drm_device *ddev = dev_get_drvdata(dev);
1082 struct msm_drm_private *priv = ddev->dev_private;
1083 struct msm_mdss *mdss = priv->mdss;
1084
1085 DBG("");
1086
1087 if (mdss && mdss->funcs)
1088 return mdss->funcs->enable(mdss);
1089
1090 return 0;
1091}
1092#endif
1093
1094static const struct dev_pm_ops msm_pm_ops = {
1095 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1096 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1097};
1098
1099/*
1100 * Componentized driver support:
1101 */
1102
1103/*
1104 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1105 * so probably some room for some helpers
1106 */
1107static int compare_of(struct device *dev, void *data)
1108{
1109 return dev->of_node == data;
1110}
1111
1112/*
1113 * Identify what components need to be added by parsing what remote-endpoints
1114 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1115 * is no external component that we need to add since LVDS is within MDP4
1116 * itself.
1117 */
1118static int add_components_mdp(struct device *mdp_dev,
1119 struct component_match **matchptr)
1120{
1121 struct device_node *np = mdp_dev->of_node;
1122 struct device_node *ep_node;
1123 struct device *master_dev;
1124
1125 /*
1126 * on MDP4 based platforms, the MDP platform device is the component
1127 * master that adds other display interface components to itself.
1128 *
1129 * on MDP5 based platforms, the MDSS platform device is the component
1130 * master that adds MDP5 and other display interface components to
1131 * itself.
1132 */
1133 if (of_device_is_compatible(np, "qcom,mdp4"))
1134 master_dev = mdp_dev;
1135 else
1136 master_dev = mdp_dev->parent;
1137
1138 for_each_endpoint_of_node(np, ep_node) {
1139 struct device_node *intf;
1140 struct of_endpoint ep;
1141 int ret;
1142
1143 ret = of_graph_parse_endpoint(ep_node, &ep);
1144 if (ret) {
1145 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1146 of_node_put(ep_node);
1147 return ret;
1148 }
1149
1150 /*
1151 * The LCDC/LVDS port on MDP4 is a speacial case where the
1152 * remote-endpoint isn't a component that we need to add
1153 */
1154 if (of_device_is_compatible(np, "qcom,mdp4") &&
1155 ep.port == 0)
1156 continue;
1157
1158 /*
1159 * It's okay if some of the ports don't have a remote endpoint
1160 * specified. It just means that the port isn't connected to
1161 * any external interface.
1162 */
1163 intf = of_graph_get_remote_port_parent(ep_node);
1164 if (!intf)
1165 continue;
1166
1167 if (of_device_is_available(intf))
1168 drm_of_component_match_add(master_dev, matchptr,
1169 compare_of, intf);
1170
1171 of_node_put(intf);
1172 }
1173
1174 return 0;
1175}
1176
1177static int compare_name_mdp(struct device *dev, void *data)
1178{
1179 return (strstr(dev_name(dev), "mdp") != NULL);
1180}
1181
1182static int add_display_components(struct device *dev,
1183 struct component_match **matchptr)
1184{
1185 struct device *mdp_dev;
1186 int ret;
1187
1188 /*
1189 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1190 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1191 * Populate the children devices, find the MDP5/DPU node, and then add
1192 * the interfaces to our components list.
1193 */
1194 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1195 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1196 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1197 if (ret) {
1198 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1199 return ret;
1200 }
1201
1202 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1203 if (!mdp_dev) {
1204 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1205 of_platform_depopulate(dev);
1206 return -ENODEV;
1207 }
1208
1209 put_device(mdp_dev);
1210
1211 /* add the MDP component itself */
1212 drm_of_component_match_add(dev, matchptr, compare_of,
1213 mdp_dev->of_node);
1214 } else {
1215 /* MDP4 */
1216 mdp_dev = dev;
1217 }
1218
1219 ret = add_components_mdp(mdp_dev, matchptr);
1220 if (ret)
1221 of_platform_depopulate(dev);
1222
1223 return ret;
1224}
1225
1226/*
1227 * We don't know what's the best binding to link the gpu with the drm device.
1228 * Fow now, we just hunt for all the possible gpus that we support, and add them
1229 * as components.
1230 */
1231static const struct of_device_id msm_gpu_match[] = {
1232 { .compatible = "qcom,adreno" },
1233 { .compatible = "qcom,adreno-3xx" },
1234 { .compatible = "amd,imageon" },
1235 { .compatible = "qcom,kgsl-3d0" },
1236 { },
1237};
1238
1239static int add_gpu_components(struct device *dev,
1240 struct component_match **matchptr)
1241{
1242 struct device_node *np;
1243
1244 np = of_find_matching_node(NULL, msm_gpu_match);
1245 if (!np)
1246 return 0;
1247
1248 if (of_device_is_available(np))
1249 drm_of_component_match_add(dev, matchptr, compare_of, np);
1250
1251 of_node_put(np);
1252
1253 return 0;
1254}
1255
1256static int msm_drm_bind(struct device *dev)
1257{
1258 return msm_drm_init(dev, &msm_driver);
1259}
1260
1261static void msm_drm_unbind(struct device *dev)
1262{
1263 msm_drm_uninit(dev);
1264}
1265
1266static const struct component_master_ops msm_drm_ops = {
1267 .bind = msm_drm_bind,
1268 .unbind = msm_drm_unbind,
1269};
1270
1271/*
1272 * Platform driver:
1273 */
1274
1275static int msm_pdev_probe(struct platform_device *pdev)
1276{
1277 struct component_match *match = NULL;
1278 int ret;
1279
1280 if (get_mdp_ver(pdev)) {
1281 ret = add_display_components(&pdev->dev, &match);
1282 if (ret)
1283 return ret;
1284 }
1285
1286 ret = add_gpu_components(&pdev->dev, &match);
1287 if (ret)
1288 goto fail;
1289
1290 /* on all devices that I am aware of, iommu's which can map
1291 * any address the cpu can see are used:
1292 */
1293 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1294 if (ret)
1295 goto fail;
1296
1297 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1298 if (ret)
1299 goto fail;
1300
1301 return 0;
1302
1303fail:
1304 of_platform_depopulate(&pdev->dev);
1305 return ret;
1306}
1307
1308static int msm_pdev_remove(struct platform_device *pdev)
1309{
1310 component_master_del(&pdev->dev, &msm_drm_ops);
1311 of_platform_depopulate(&pdev->dev);
1312
1313 return 0;
1314}
1315
1316static const struct of_device_id dt_match[] = {
1317 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1318 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1319 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1320 {}
1321};
1322MODULE_DEVICE_TABLE(of, dt_match);
1323
1324static struct platform_driver msm_platform_driver = {
1325 .probe = msm_pdev_probe,
1326 .remove = msm_pdev_remove,
1327 .driver = {
1328 .name = "msm",
1329 .of_match_table = dt_match,
1330 .pm = &msm_pm_ops,
1331 },
1332};
1333
1334static int __init msm_drm_register(void)
1335{
1336 if (!modeset)
1337 return -EINVAL;
1338
1339 DBG("init");
1340 msm_mdp_register();
1341 msm_dpu_register();
1342 msm_dsi_register();
1343 msm_edp_register();
1344 msm_hdmi_register();
1345 adreno_register();
1346 return platform_driver_register(&msm_platform_driver);
1347}
1348
1349static void __exit msm_drm_unregister(void)
1350{
1351 DBG("fini");
1352 platform_driver_unregister(&msm_platform_driver);
1353 msm_hdmi_unregister();
1354 adreno_unregister();
1355 msm_edp_unregister();
1356 msm_dsi_unregister();
1357 msm_mdp_unregister();
1358 msm_dpu_unregister();
1359}
1360
1361module_init(msm_drm_register);
1362module_exit(msm_drm_unregister);
1363
1364MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1365MODULE_DESCRIPTION("MSM DRM Driver");
1366MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/fault-inject.h>
10#include <linux/kthread.h>
11#include <linux/sched/mm.h>
12#include <linux/uaccess.h>
13#include <uapi/linux/sched/types.h>
14
15#include <drm/drm_bridge.h>
16#include <drm/drm_drv.h>
17#include <drm/drm_file.h>
18#include <drm/drm_ioctl.h>
19#include <drm/drm_prime.h>
20#include <drm/drm_of.h>
21#include <drm/drm_vblank.h>
22
23#include "disp/msm_disp_snapshot.h"
24#include "msm_drv.h"
25#include "msm_debugfs.h"
26#include "msm_fence.h"
27#include "msm_gem.h"
28#include "msm_gpu.h"
29#include "msm_kms.h"
30#include "msm_mmu.h"
31#include "adreno/adreno_gpu.h"
32
33/*
34 * MSM driver version:
35 * - 1.0.0 - initial interface
36 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
37 * - 1.2.0 - adds explicit fence support for submit ioctl
38 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
39 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
40 * MSM_GEM_INFO ioctl.
41 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
42 * GEM object's debug name
43 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
44 * - 1.6.0 - Syncobj support
45 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
46 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
47 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
48 */
49#define MSM_VERSION_MAJOR 1
50#define MSM_VERSION_MINOR 9
51#define MSM_VERSION_PATCHLEVEL 0
52
53static const struct drm_mode_config_funcs mode_config_funcs = {
54 .fb_create = msm_framebuffer_create,
55 .output_poll_changed = drm_fb_helper_output_poll_changed,
56 .atomic_check = drm_atomic_helper_check,
57 .atomic_commit = drm_atomic_helper_commit,
58};
59
60static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
61 .atomic_commit_tail = msm_atomic_commit_tail,
62};
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82#ifdef CONFIG_FAULT_INJECTION
83DECLARE_FAULT_ATTR(fail_gem_alloc);
84DECLARE_FAULT_ATTR(fail_gem_iova);
85#endif
86
87static irqreturn_t msm_irq(int irq, void *arg)
88{
89 struct drm_device *dev = arg;
90 struct msm_drm_private *priv = dev->dev_private;
91 struct msm_kms *kms = priv->kms;
92
93 BUG_ON(!kms);
94
95 return kms->funcs->irq(kms);
96}
97
98static void msm_irq_preinstall(struct drm_device *dev)
99{
100 struct msm_drm_private *priv = dev->dev_private;
101 struct msm_kms *kms = priv->kms;
102
103 BUG_ON(!kms);
104
105 kms->funcs->irq_preinstall(kms);
106}
107
108static int msm_irq_postinstall(struct drm_device *dev)
109{
110 struct msm_drm_private *priv = dev->dev_private;
111 struct msm_kms *kms = priv->kms;
112
113 BUG_ON(!kms);
114
115 if (kms->funcs->irq_postinstall)
116 return kms->funcs->irq_postinstall(kms);
117
118 return 0;
119}
120
121static int msm_irq_install(struct drm_device *dev, unsigned int irq)
122{
123 struct msm_drm_private *priv = dev->dev_private;
124 struct msm_kms *kms = priv->kms;
125 int ret;
126
127 if (irq == IRQ_NOTCONNECTED)
128 return -ENOTCONN;
129
130 msm_irq_preinstall(dev);
131
132 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
133 if (ret)
134 return ret;
135
136 kms->irq_requested = true;
137
138 ret = msm_irq_postinstall(dev);
139 if (ret) {
140 free_irq(irq, dev);
141 return ret;
142 }
143
144 return 0;
145}
146
147static void msm_irq_uninstall(struct drm_device *dev)
148{
149 struct msm_drm_private *priv = dev->dev_private;
150 struct msm_kms *kms = priv->kms;
151
152 kms->funcs->irq_uninstall(kms);
153 if (kms->irq_requested)
154 free_irq(kms->irq, dev);
155}
156
157struct msm_vblank_work {
158 struct work_struct work;
159 int crtc_id;
160 bool enable;
161 struct msm_drm_private *priv;
162};
163
164static void vblank_ctrl_worker(struct work_struct *work)
165{
166 struct msm_vblank_work *vbl_work = container_of(work,
167 struct msm_vblank_work, work);
168 struct msm_drm_private *priv = vbl_work->priv;
169 struct msm_kms *kms = priv->kms;
170
171 if (vbl_work->enable)
172 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
173 else
174 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
175
176 kfree(vbl_work);
177}
178
179static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
180 int crtc_id, bool enable)
181{
182 struct msm_vblank_work *vbl_work;
183
184 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
185 if (!vbl_work)
186 return -ENOMEM;
187
188 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
189
190 vbl_work->crtc_id = crtc_id;
191 vbl_work->enable = enable;
192 vbl_work->priv = priv;
193
194 queue_work(priv->wq, &vbl_work->work);
195
196 return 0;
197}
198
199static int msm_drm_uninit(struct device *dev)
200{
201 struct platform_device *pdev = to_platform_device(dev);
202 struct msm_drm_private *priv = platform_get_drvdata(pdev);
203 struct drm_device *ddev = priv->dev;
204 struct msm_kms *kms = priv->kms;
205 int i;
206
207 /*
208 * Shutdown the hw if we're far enough along where things might be on.
209 * If we run this too early, we'll end up panicking in any variety of
210 * places. Since we don't register the drm device until late in
211 * msm_drm_init, drm_dev->registered is used as an indicator that the
212 * shutdown will be successful.
213 */
214 if (ddev->registered) {
215 drm_dev_unregister(ddev);
216 drm_atomic_helper_shutdown(ddev);
217 }
218
219 /* We must cancel and cleanup any pending vblank enable/disable
220 * work before msm_irq_uninstall() to avoid work re-enabling an
221 * irq after uninstall has disabled it.
222 */
223
224 flush_workqueue(priv->wq);
225
226 /* clean up event worker threads */
227 for (i = 0; i < priv->num_crtcs; i++) {
228 if (priv->event_thread[i].worker)
229 kthread_destroy_worker(priv->event_thread[i].worker);
230 }
231
232 msm_gem_shrinker_cleanup(ddev);
233
234 drm_kms_helper_poll_fini(ddev);
235
236 msm_perf_debugfs_cleanup(priv);
237 msm_rd_debugfs_cleanup(priv);
238
239#ifdef CONFIG_DRM_FBDEV_EMULATION
240 if (fbdev && priv->fbdev)
241 msm_fbdev_free(ddev);
242#endif
243
244 msm_disp_snapshot_destroy(ddev);
245
246 drm_mode_config_cleanup(ddev);
247
248 for (i = 0; i < priv->num_bridges; i++)
249 drm_bridge_remove(priv->bridges[i]);
250 priv->num_bridges = 0;
251
252 pm_runtime_get_sync(dev);
253 msm_irq_uninstall(ddev);
254 pm_runtime_put_sync(dev);
255
256 if (kms && kms->funcs)
257 kms->funcs->destroy(kms);
258
259 if (priv->vram.paddr) {
260 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
261 drm_mm_takedown(&priv->vram.mm);
262 dma_free_attrs(dev, priv->vram.size, NULL,
263 priv->vram.paddr, attrs);
264 }
265
266 component_unbind_all(dev, ddev);
267
268 ddev->dev_private = NULL;
269 drm_dev_put(ddev);
270
271 destroy_workqueue(priv->wq);
272
273 return 0;
274}
275
276#include <linux/of_address.h>
277
278struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
279{
280 struct msm_gem_address_space *aspace;
281 struct msm_mmu *mmu;
282 struct device *mdp_dev = dev->dev;
283 struct device *mdss_dev = mdp_dev->parent;
284 struct device *iommu_dev;
285
286 /*
287 * IOMMUs can be a part of MDSS device tree binding, or the
288 * MDP/DPU device.
289 */
290 if (device_iommu_mapped(mdp_dev))
291 iommu_dev = mdp_dev;
292 else
293 iommu_dev = mdss_dev;
294
295 mmu = msm_iommu_new(iommu_dev, 0);
296 if (IS_ERR(mmu))
297 return ERR_CAST(mmu);
298
299 if (!mmu) {
300 drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
301 return NULL;
302 }
303
304 aspace = msm_gem_address_space_create(mmu, "mdp_kms",
305 0x1000, 0x100000000 - 0x1000);
306 if (IS_ERR(aspace)) {
307 dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
308 mmu->funcs->destroy(mmu);
309 }
310
311 return aspace;
312}
313
314bool msm_use_mmu(struct drm_device *dev)
315{
316 struct msm_drm_private *priv = dev->dev_private;
317
318 /*
319 * a2xx comes with its own MMU
320 * On other platforms IOMMU can be declared specified either for the
321 * MDP/DPU device or for its parent, MDSS device.
322 */
323 return priv->is_a2xx ||
324 device_iommu_mapped(dev->dev) ||
325 device_iommu_mapped(dev->dev->parent);
326}
327
328static int msm_init_vram(struct drm_device *dev)
329{
330 struct msm_drm_private *priv = dev->dev_private;
331 struct device_node *node;
332 unsigned long size = 0;
333 int ret = 0;
334
335 /* In the device-tree world, we could have a 'memory-region'
336 * phandle, which gives us a link to our "vram". Allocating
337 * is all nicely abstracted behind the dma api, but we need
338 * to know the entire size to allocate it all in one go. There
339 * are two cases:
340 * 1) device with no IOMMU, in which case we need exclusive
341 * access to a VRAM carveout big enough for all gpu
342 * buffers
343 * 2) device with IOMMU, but where the bootloader puts up
344 * a splash screen. In this case, the VRAM carveout
345 * need only be large enough for fbdev fb. But we need
346 * exclusive access to the buffer to avoid the kernel
347 * using those pages for other purposes (which appears
348 * as corruption on screen before we have a chance to
349 * load and do initial modeset)
350 */
351
352 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
353 if (node) {
354 struct resource r;
355 ret = of_address_to_resource(node, 0, &r);
356 of_node_put(node);
357 if (ret)
358 return ret;
359 size = r.end - r.start + 1;
360 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
361
362 /* if we have no IOMMU, then we need to use carveout allocator.
363 * Grab the entire DMA chunk carved out in early startup in
364 * mach-msm:
365 */
366 } else if (!msm_use_mmu(dev)) {
367 DRM_INFO("using %s VRAM carveout\n", vram);
368 size = memparse(vram, NULL);
369 }
370
371 if (size) {
372 unsigned long attrs = 0;
373 void *p;
374
375 priv->vram.size = size;
376
377 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
378 spin_lock_init(&priv->vram.lock);
379
380 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
381 attrs |= DMA_ATTR_WRITE_COMBINE;
382
383 /* note that for no-kernel-mapping, the vaddr returned
384 * is bogus, but non-null if allocation succeeded:
385 */
386 p = dma_alloc_attrs(dev->dev, size,
387 &priv->vram.paddr, GFP_KERNEL, attrs);
388 if (!p) {
389 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
390 priv->vram.paddr = 0;
391 return -ENOMEM;
392 }
393
394 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
395 (uint32_t)priv->vram.paddr,
396 (uint32_t)(priv->vram.paddr + size));
397 }
398
399 return ret;
400}
401
402static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
403{
404 struct msm_drm_private *priv = dev_get_drvdata(dev);
405 struct drm_device *ddev;
406 struct msm_kms *kms;
407 int ret, i;
408
409 if (drm_firmware_drivers_only())
410 return -ENODEV;
411
412 ddev = drm_dev_alloc(drv, dev);
413 if (IS_ERR(ddev)) {
414 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
415 return PTR_ERR(ddev);
416 }
417 ddev->dev_private = priv;
418 priv->dev = ddev;
419
420 priv->wq = alloc_ordered_workqueue("msm", 0);
421
422 INIT_LIST_HEAD(&priv->objects);
423 mutex_init(&priv->obj_lock);
424
425 /*
426 * Initialize the LRUs:
427 */
428 mutex_init(&priv->lru.lock);
429 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
430 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
431 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
432 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
433
434 /* Teach lockdep about lock ordering wrt. shrinker: */
435 fs_reclaim_acquire(GFP_KERNEL);
436 might_lock(&priv->lru.lock);
437 fs_reclaim_release(GFP_KERNEL);
438
439 drm_mode_config_init(ddev);
440
441 ret = msm_init_vram(ddev);
442 if (ret)
443 return ret;
444
445 /* Bind all our sub-components: */
446 ret = component_bind_all(dev, ddev);
447 if (ret)
448 return ret;
449
450 dma_set_max_seg_size(dev, UINT_MAX);
451
452 msm_gem_shrinker_init(ddev);
453
454 if (priv->kms_init) {
455 ret = priv->kms_init(ddev);
456 if (ret) {
457 DRM_DEV_ERROR(dev, "failed to load kms\n");
458 priv->kms = NULL;
459 goto err_msm_uninit;
460 }
461 kms = priv->kms;
462 } else {
463 /* valid only for the dummy headless case, where of_node=NULL */
464 WARN_ON(dev->of_node);
465 kms = NULL;
466 }
467
468 /* Enable normalization of plane zpos */
469 ddev->mode_config.normalize_zpos = true;
470
471 if (kms) {
472 kms->dev = ddev;
473 ret = kms->funcs->hw_init(kms);
474 if (ret) {
475 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
476 goto err_msm_uninit;
477 }
478 }
479
480 drm_helper_move_panel_connectors_to_head(ddev);
481
482 ddev->mode_config.funcs = &mode_config_funcs;
483 ddev->mode_config.helper_private = &mode_config_helper_funcs;
484
485 for (i = 0; i < priv->num_crtcs; i++) {
486 /* initialize event thread */
487 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
488 priv->event_thread[i].dev = ddev;
489 priv->event_thread[i].worker = kthread_create_worker(0,
490 "crtc_event:%d", priv->event_thread[i].crtc_id);
491 if (IS_ERR(priv->event_thread[i].worker)) {
492 ret = PTR_ERR(priv->event_thread[i].worker);
493 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
494 ret = PTR_ERR(priv->event_thread[i].worker);
495 goto err_msm_uninit;
496 }
497
498 sched_set_fifo(priv->event_thread[i].worker->task);
499 }
500
501 ret = drm_vblank_init(ddev, priv->num_crtcs);
502 if (ret < 0) {
503 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
504 goto err_msm_uninit;
505 }
506
507 if (kms) {
508 pm_runtime_get_sync(dev);
509 ret = msm_irq_install(ddev, kms->irq);
510 pm_runtime_put_sync(dev);
511 if (ret < 0) {
512 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
513 goto err_msm_uninit;
514 }
515 }
516
517 ret = drm_dev_register(ddev, 0);
518 if (ret)
519 goto err_msm_uninit;
520
521 if (kms) {
522 ret = msm_disp_snapshot_init(ddev);
523 if (ret)
524 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
525 }
526 drm_mode_config_reset(ddev);
527
528#ifdef CONFIG_DRM_FBDEV_EMULATION
529 if (kms && fbdev)
530 priv->fbdev = msm_fbdev_init(ddev);
531#endif
532
533 ret = msm_debugfs_late_init(ddev);
534 if (ret)
535 goto err_msm_uninit;
536
537 drm_kms_helper_poll_init(ddev);
538
539 return 0;
540
541err_msm_uninit:
542 msm_drm_uninit(dev);
543 return ret;
544}
545
546/*
547 * DRM operations:
548 */
549
550static void load_gpu(struct drm_device *dev)
551{
552 static DEFINE_MUTEX(init_lock);
553 struct msm_drm_private *priv = dev->dev_private;
554
555 mutex_lock(&init_lock);
556
557 if (!priv->gpu)
558 priv->gpu = adreno_load_gpu(dev);
559
560 mutex_unlock(&init_lock);
561}
562
563static int context_init(struct drm_device *dev, struct drm_file *file)
564{
565 static atomic_t ident = ATOMIC_INIT(0);
566 struct msm_drm_private *priv = dev->dev_private;
567 struct msm_file_private *ctx;
568
569 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
570 if (!ctx)
571 return -ENOMEM;
572
573 INIT_LIST_HEAD(&ctx->submitqueues);
574 rwlock_init(&ctx->queuelock);
575
576 kref_init(&ctx->ref);
577 msm_submitqueue_init(dev, ctx);
578
579 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
580 file->driver_priv = ctx;
581
582 ctx->seqno = atomic_inc_return(&ident);
583
584 return 0;
585}
586
587static int msm_open(struct drm_device *dev, struct drm_file *file)
588{
589 /* For now, load gpu on open.. to avoid the requirement of having
590 * firmware in the initrd.
591 */
592 load_gpu(dev);
593
594 return context_init(dev, file);
595}
596
597static void context_close(struct msm_file_private *ctx)
598{
599 msm_submitqueue_close(ctx);
600 msm_file_private_put(ctx);
601}
602
603static void msm_postclose(struct drm_device *dev, struct drm_file *file)
604{
605 struct msm_drm_private *priv = dev->dev_private;
606 struct msm_file_private *ctx = file->driver_priv;
607
608 /*
609 * It is not possible to set sysprof param to non-zero if gpu
610 * is not initialized:
611 */
612 if (priv->gpu)
613 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
614
615 context_close(ctx);
616}
617
618int msm_crtc_enable_vblank(struct drm_crtc *crtc)
619{
620 struct drm_device *dev = crtc->dev;
621 unsigned int pipe = crtc->index;
622 struct msm_drm_private *priv = dev->dev_private;
623 struct msm_kms *kms = priv->kms;
624 if (!kms)
625 return -ENXIO;
626 drm_dbg_vbl(dev, "crtc=%u", pipe);
627 return vblank_ctrl_queue_work(priv, pipe, true);
628}
629
630void msm_crtc_disable_vblank(struct drm_crtc *crtc)
631{
632 struct drm_device *dev = crtc->dev;
633 unsigned int pipe = crtc->index;
634 struct msm_drm_private *priv = dev->dev_private;
635 struct msm_kms *kms = priv->kms;
636 if (!kms)
637 return;
638 drm_dbg_vbl(dev, "crtc=%u", pipe);
639 vblank_ctrl_queue_work(priv, pipe, false);
640}
641
642/*
643 * DRM ioctls:
644 */
645
646static int msm_ioctl_get_param(struct drm_device *dev, void *data,
647 struct drm_file *file)
648{
649 struct msm_drm_private *priv = dev->dev_private;
650 struct drm_msm_param *args = data;
651 struct msm_gpu *gpu;
652
653 /* for now, we just have 3d pipe.. eventually this would need to
654 * be more clever to dispatch to appropriate gpu module:
655 */
656 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
657 return -EINVAL;
658
659 gpu = priv->gpu;
660
661 if (!gpu)
662 return -ENXIO;
663
664 return gpu->funcs->get_param(gpu, file->driver_priv,
665 args->param, &args->value, &args->len);
666}
667
668static int msm_ioctl_set_param(struct drm_device *dev, void *data,
669 struct drm_file *file)
670{
671 struct msm_drm_private *priv = dev->dev_private;
672 struct drm_msm_param *args = data;
673 struct msm_gpu *gpu;
674
675 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
676 return -EINVAL;
677
678 gpu = priv->gpu;
679
680 if (!gpu)
681 return -ENXIO;
682
683 return gpu->funcs->set_param(gpu, file->driver_priv,
684 args->param, args->value, args->len);
685}
686
687static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
688 struct drm_file *file)
689{
690 struct drm_msm_gem_new *args = data;
691 uint32_t flags = args->flags;
692
693 if (args->flags & ~MSM_BO_FLAGS) {
694 DRM_ERROR("invalid flags: %08x\n", args->flags);
695 return -EINVAL;
696 }
697
698 /*
699 * Uncached CPU mappings are deprecated, as of:
700 *
701 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
702 *
703 * So promote them to WC.
704 */
705 if (flags & MSM_BO_UNCACHED) {
706 flags &= ~MSM_BO_CACHED;
707 flags |= MSM_BO_WC;
708 }
709
710 if (should_fail(&fail_gem_alloc, args->size))
711 return -ENOMEM;
712
713 return msm_gem_new_handle(dev, file, args->size,
714 args->flags, &args->handle, NULL);
715}
716
717static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
718{
719 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
720}
721
722static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
723 struct drm_file *file)
724{
725 struct drm_msm_gem_cpu_prep *args = data;
726 struct drm_gem_object *obj;
727 ktime_t timeout = to_ktime(args->timeout);
728 int ret;
729
730 if (args->op & ~MSM_PREP_FLAGS) {
731 DRM_ERROR("invalid op: %08x\n", args->op);
732 return -EINVAL;
733 }
734
735 obj = drm_gem_object_lookup(file, args->handle);
736 if (!obj)
737 return -ENOENT;
738
739 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
740
741 drm_gem_object_put(obj);
742
743 return ret;
744}
745
746static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
747 struct drm_file *file)
748{
749 struct drm_msm_gem_cpu_fini *args = data;
750 struct drm_gem_object *obj;
751 int ret;
752
753 obj = drm_gem_object_lookup(file, args->handle);
754 if (!obj)
755 return -ENOENT;
756
757 ret = msm_gem_cpu_fini(obj);
758
759 drm_gem_object_put(obj);
760
761 return ret;
762}
763
764static int msm_ioctl_gem_info_iova(struct drm_device *dev,
765 struct drm_file *file, struct drm_gem_object *obj,
766 uint64_t *iova)
767{
768 struct msm_drm_private *priv = dev->dev_private;
769 struct msm_file_private *ctx = file->driver_priv;
770
771 if (!priv->gpu)
772 return -EINVAL;
773
774 if (should_fail(&fail_gem_iova, obj->size))
775 return -ENOMEM;
776
777 /*
778 * Don't pin the memory here - just get an address so that userspace can
779 * be productive
780 */
781 return msm_gem_get_iova(obj, ctx->aspace, iova);
782}
783
784static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
785 struct drm_file *file, struct drm_gem_object *obj,
786 uint64_t iova)
787{
788 struct msm_drm_private *priv = dev->dev_private;
789 struct msm_file_private *ctx = file->driver_priv;
790
791 if (!priv->gpu)
792 return -EINVAL;
793
794 /* Only supported if per-process address space is supported: */
795 if (priv->gpu->aspace == ctx->aspace)
796 return -EOPNOTSUPP;
797
798 if (should_fail(&fail_gem_iova, obj->size))
799 return -ENOMEM;
800
801 return msm_gem_set_iova(obj, ctx->aspace, iova);
802}
803
804static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
805 struct drm_file *file)
806{
807 struct drm_msm_gem_info *args = data;
808 struct drm_gem_object *obj;
809 struct msm_gem_object *msm_obj;
810 int i, ret = 0;
811
812 if (args->pad)
813 return -EINVAL;
814
815 switch (args->info) {
816 case MSM_INFO_GET_OFFSET:
817 case MSM_INFO_GET_IOVA:
818 case MSM_INFO_SET_IOVA:
819 case MSM_INFO_GET_FLAGS:
820 /* value returned as immediate, not pointer, so len==0: */
821 if (args->len)
822 return -EINVAL;
823 break;
824 case MSM_INFO_SET_NAME:
825 case MSM_INFO_GET_NAME:
826 break;
827 default:
828 return -EINVAL;
829 }
830
831 obj = drm_gem_object_lookup(file, args->handle);
832 if (!obj)
833 return -ENOENT;
834
835 msm_obj = to_msm_bo(obj);
836
837 switch (args->info) {
838 case MSM_INFO_GET_OFFSET:
839 args->value = msm_gem_mmap_offset(obj);
840 break;
841 case MSM_INFO_GET_IOVA:
842 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
843 break;
844 case MSM_INFO_SET_IOVA:
845 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
846 break;
847 case MSM_INFO_GET_FLAGS:
848 if (obj->import_attach) {
849 ret = -EINVAL;
850 break;
851 }
852 /* Hide internal kernel-only flags: */
853 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
854 ret = 0;
855 break;
856 case MSM_INFO_SET_NAME:
857 /* length check should leave room for terminating null: */
858 if (args->len >= sizeof(msm_obj->name)) {
859 ret = -EINVAL;
860 break;
861 }
862 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
863 args->len)) {
864 msm_obj->name[0] = '\0';
865 ret = -EFAULT;
866 break;
867 }
868 msm_obj->name[args->len] = '\0';
869 for (i = 0; i < args->len; i++) {
870 if (!isprint(msm_obj->name[i])) {
871 msm_obj->name[i] = '\0';
872 break;
873 }
874 }
875 break;
876 case MSM_INFO_GET_NAME:
877 if (args->value && (args->len < strlen(msm_obj->name))) {
878 ret = -EINVAL;
879 break;
880 }
881 args->len = strlen(msm_obj->name);
882 if (args->value) {
883 if (copy_to_user(u64_to_user_ptr(args->value),
884 msm_obj->name, args->len))
885 ret = -EFAULT;
886 }
887 break;
888 }
889
890 drm_gem_object_put(obj);
891
892 return ret;
893}
894
895static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
896 ktime_t timeout)
897{
898 struct dma_fence *fence;
899 int ret;
900
901 if (fence_after(fence_id, queue->last_fence)) {
902 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
903 fence_id, queue->last_fence);
904 return -EINVAL;
905 }
906
907 /*
908 * Map submitqueue scoped "seqno" (which is actually an idr key)
909 * back to underlying dma-fence
910 *
911 * The fence is removed from the fence_idr when the submit is
912 * retired, so if the fence is not found it means there is nothing
913 * to wait for
914 */
915 ret = mutex_lock_interruptible(&queue->idr_lock);
916 if (ret)
917 return ret;
918 fence = idr_find(&queue->fence_idr, fence_id);
919 if (fence)
920 fence = dma_fence_get_rcu(fence);
921 mutex_unlock(&queue->idr_lock);
922
923 if (!fence)
924 return 0;
925
926 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
927 if (ret == 0) {
928 ret = -ETIMEDOUT;
929 } else if (ret != -ERESTARTSYS) {
930 ret = 0;
931 }
932
933 dma_fence_put(fence);
934
935 return ret;
936}
937
938static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
939 struct drm_file *file)
940{
941 struct msm_drm_private *priv = dev->dev_private;
942 struct drm_msm_wait_fence *args = data;
943 struct msm_gpu_submitqueue *queue;
944 int ret;
945
946 if (args->pad) {
947 DRM_ERROR("invalid pad: %08x\n", args->pad);
948 return -EINVAL;
949 }
950
951 if (!priv->gpu)
952 return 0;
953
954 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
955 if (!queue)
956 return -ENOENT;
957
958 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
959
960 msm_submitqueue_put(queue);
961
962 return ret;
963}
964
965static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
966 struct drm_file *file)
967{
968 struct drm_msm_gem_madvise *args = data;
969 struct drm_gem_object *obj;
970 int ret;
971
972 switch (args->madv) {
973 case MSM_MADV_DONTNEED:
974 case MSM_MADV_WILLNEED:
975 break;
976 default:
977 return -EINVAL;
978 }
979
980 obj = drm_gem_object_lookup(file, args->handle);
981 if (!obj) {
982 return -ENOENT;
983 }
984
985 ret = msm_gem_madvise(obj, args->madv);
986 if (ret >= 0) {
987 args->retained = ret;
988 ret = 0;
989 }
990
991 drm_gem_object_put(obj);
992
993 return ret;
994}
995
996
997static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
998 struct drm_file *file)
999{
1000 struct drm_msm_submitqueue *args = data;
1001
1002 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1003 return -EINVAL;
1004
1005 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1006 args->flags, &args->id);
1007}
1008
1009static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1010 struct drm_file *file)
1011{
1012 return msm_submitqueue_query(dev, file->driver_priv, data);
1013}
1014
1015static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1016 struct drm_file *file)
1017{
1018 u32 id = *(u32 *) data;
1019
1020 return msm_submitqueue_remove(file->driver_priv, id);
1021}
1022
1023static const struct drm_ioctl_desc msm_ioctls[] = {
1024 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1025 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
1026 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1027 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1028 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1029 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1030 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1031 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1032 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1033 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1034 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1035 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1036};
1037
1038static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f)
1039{
1040 struct drm_file *file = f->private_data;
1041 struct drm_device *dev = file->minor->dev;
1042 struct msm_drm_private *priv = dev->dev_private;
1043 struct drm_printer p = drm_seq_file_printer(m);
1044
1045 if (!priv->gpu)
1046 return;
1047
1048 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p);
1049}
1050
1051static const struct file_operations fops = {
1052 .owner = THIS_MODULE,
1053 DRM_GEM_FOPS,
1054 .show_fdinfo = msm_fop_show_fdinfo,
1055};
1056
1057static const struct drm_driver msm_driver = {
1058 .driver_features = DRIVER_GEM |
1059 DRIVER_RENDER |
1060 DRIVER_ATOMIC |
1061 DRIVER_MODESET |
1062 DRIVER_SYNCOBJ,
1063 .open = msm_open,
1064 .postclose = msm_postclose,
1065 .lastclose = drm_fb_helper_lastclose,
1066 .dumb_create = msm_gem_dumb_create,
1067 .dumb_map_offset = msm_gem_dumb_map_offset,
1068 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1069 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1070 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1071 .gem_prime_mmap = msm_gem_prime_mmap,
1072#ifdef CONFIG_DEBUG_FS
1073 .debugfs_init = msm_debugfs_init,
1074#endif
1075 .ioctls = msm_ioctls,
1076 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1077 .fops = &fops,
1078 .name = "msm",
1079 .desc = "MSM Snapdragon DRM",
1080 .date = "20130625",
1081 .major = MSM_VERSION_MAJOR,
1082 .minor = MSM_VERSION_MINOR,
1083 .patchlevel = MSM_VERSION_PATCHLEVEL,
1084};
1085
1086int msm_pm_prepare(struct device *dev)
1087{
1088 struct msm_drm_private *priv = dev_get_drvdata(dev);
1089 struct drm_device *ddev = priv ? priv->dev : NULL;
1090
1091 if (!priv || !priv->kms)
1092 return 0;
1093
1094 return drm_mode_config_helper_suspend(ddev);
1095}
1096
1097void msm_pm_complete(struct device *dev)
1098{
1099 struct msm_drm_private *priv = dev_get_drvdata(dev);
1100 struct drm_device *ddev = priv ? priv->dev : NULL;
1101
1102 if (!priv || !priv->kms)
1103 return;
1104
1105 drm_mode_config_helper_resume(ddev);
1106}
1107
1108static const struct dev_pm_ops msm_pm_ops = {
1109 .prepare = msm_pm_prepare,
1110 .complete = msm_pm_complete,
1111};
1112
1113/*
1114 * Componentized driver support:
1115 */
1116
1117/*
1118 * Identify what components need to be added by parsing what remote-endpoints
1119 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1120 * is no external component that we need to add since LVDS is within MDP4
1121 * itself.
1122 */
1123static int add_components_mdp(struct device *master_dev,
1124 struct component_match **matchptr)
1125{
1126 struct device_node *np = master_dev->of_node;
1127 struct device_node *ep_node;
1128
1129 for_each_endpoint_of_node(np, ep_node) {
1130 struct device_node *intf;
1131 struct of_endpoint ep;
1132 int ret;
1133
1134 ret = of_graph_parse_endpoint(ep_node, &ep);
1135 if (ret) {
1136 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
1137 of_node_put(ep_node);
1138 return ret;
1139 }
1140
1141 /*
1142 * The LCDC/LVDS port on MDP4 is a speacial case where the
1143 * remote-endpoint isn't a component that we need to add
1144 */
1145 if (of_device_is_compatible(np, "qcom,mdp4") &&
1146 ep.port == 0)
1147 continue;
1148
1149 /*
1150 * It's okay if some of the ports don't have a remote endpoint
1151 * specified. It just means that the port isn't connected to
1152 * any external interface.
1153 */
1154 intf = of_graph_get_remote_port_parent(ep_node);
1155 if (!intf)
1156 continue;
1157
1158 if (of_device_is_available(intf))
1159 drm_of_component_match_add(master_dev, matchptr,
1160 component_compare_of, intf);
1161
1162 of_node_put(intf);
1163 }
1164
1165 return 0;
1166}
1167
1168/*
1169 * We don't know what's the best binding to link the gpu with the drm device.
1170 * Fow now, we just hunt for all the possible gpus that we support, and add them
1171 * as components.
1172 */
1173static const struct of_device_id msm_gpu_match[] = {
1174 { .compatible = "qcom,adreno" },
1175 { .compatible = "qcom,adreno-3xx" },
1176 { .compatible = "amd,imageon" },
1177 { .compatible = "qcom,kgsl-3d0" },
1178 { },
1179};
1180
1181static int add_gpu_components(struct device *dev,
1182 struct component_match **matchptr)
1183{
1184 struct device_node *np;
1185
1186 np = of_find_matching_node(NULL, msm_gpu_match);
1187 if (!np)
1188 return 0;
1189
1190 if (of_device_is_available(np))
1191 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1192
1193 of_node_put(np);
1194
1195 return 0;
1196}
1197
1198static int msm_drm_bind(struct device *dev)
1199{
1200 return msm_drm_init(dev, &msm_driver);
1201}
1202
1203static void msm_drm_unbind(struct device *dev)
1204{
1205 msm_drm_uninit(dev);
1206}
1207
1208const struct component_master_ops msm_drm_ops = {
1209 .bind = msm_drm_bind,
1210 .unbind = msm_drm_unbind,
1211};
1212
1213int msm_drv_probe(struct device *master_dev,
1214 int (*kms_init)(struct drm_device *dev))
1215{
1216 struct msm_drm_private *priv;
1217 struct component_match *match = NULL;
1218 int ret;
1219
1220 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1221 if (!priv)
1222 return -ENOMEM;
1223
1224 priv->kms_init = kms_init;
1225 dev_set_drvdata(master_dev, priv);
1226
1227 /* Add mdp components if we have KMS. */
1228 if (kms_init) {
1229 ret = add_components_mdp(master_dev, &match);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 ret = add_gpu_components(master_dev, &match);
1235 if (ret)
1236 return ret;
1237
1238 /* on all devices that I am aware of, iommu's which can map
1239 * any address the cpu can see are used:
1240 */
1241 ret = dma_set_mask_and_coherent(master_dev, ~0);
1242 if (ret)
1243 return ret;
1244
1245 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1246 if (ret)
1247 return ret;
1248
1249 return 0;
1250}
1251
1252/*
1253 * Platform driver:
1254 * Used only for headlesss GPU instances
1255 */
1256
1257static int msm_pdev_probe(struct platform_device *pdev)
1258{
1259 return msm_drv_probe(&pdev->dev, NULL);
1260}
1261
1262static int msm_pdev_remove(struct platform_device *pdev)
1263{
1264 component_master_del(&pdev->dev, &msm_drm_ops);
1265
1266 return 0;
1267}
1268
1269void msm_drv_shutdown(struct platform_device *pdev)
1270{
1271 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1272 struct drm_device *drm = priv ? priv->dev : NULL;
1273
1274 /*
1275 * Shutdown the hw if we're far enough along where things might be on.
1276 * If we run this too early, we'll end up panicking in any variety of
1277 * places. Since we don't register the drm device until late in
1278 * msm_drm_init, drm_dev->registered is used as an indicator that the
1279 * shutdown will be successful.
1280 */
1281 if (drm && drm->registered && priv->kms)
1282 drm_atomic_helper_shutdown(drm);
1283}
1284
1285static struct platform_driver msm_platform_driver = {
1286 .probe = msm_pdev_probe,
1287 .remove = msm_pdev_remove,
1288 .shutdown = msm_drv_shutdown,
1289 .driver = {
1290 .name = "msm",
1291 .pm = &msm_pm_ops,
1292 },
1293};
1294
1295static int __init msm_drm_register(void)
1296{
1297 if (!modeset)
1298 return -EINVAL;
1299
1300 DBG("init");
1301 msm_mdp_register();
1302 msm_dpu_register();
1303 msm_dsi_register();
1304 msm_hdmi_register();
1305 msm_dp_register();
1306 adreno_register();
1307 msm_mdp4_register();
1308 msm_mdss_register();
1309 return platform_driver_register(&msm_platform_driver);
1310}
1311
1312static void __exit msm_drm_unregister(void)
1313{
1314 DBG("fini");
1315 platform_driver_unregister(&msm_platform_driver);
1316 msm_mdss_unregister();
1317 msm_mdp4_unregister();
1318 msm_dp_unregister();
1319 msm_hdmi_unregister();
1320 adreno_unregister();
1321 msm_dsi_unregister();
1322 msm_mdp_unregister();
1323 msm_dpu_unregister();
1324}
1325
1326module_init(msm_drm_register);
1327module_exit(msm_drm_unregister);
1328
1329MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1330MODULE_DESCRIPTION("MSM DRM Driver");
1331MODULE_LICENSE("GPL");