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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/kthread.h>
10#include <linux/uaccess.h>
11#include <uapi/linux/sched/types.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_irq.h>
17#include <drm/drm_prime.h>
18#include <drm/drm_of.h>
19#include <drm/drm_vblank.h>
20
21#include "msm_drv.h"
22#include "msm_debugfs.h"
23#include "msm_fence.h"
24#include "msm_gem.h"
25#include "msm_gpu.h"
26#include "msm_kms.h"
27#include "adreno/adreno_gpu.h"
28
29/*
30 * MSM driver version:
31 * - 1.0.0 - initial interface
32 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
33 * - 1.2.0 - adds explicit fence support for submit ioctl
34 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
35 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
36 * MSM_GEM_INFO ioctl.
37 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
38 * GEM object's debug name
39 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
40 */
41#define MSM_VERSION_MAJOR 1
42#define MSM_VERSION_MINOR 5
43#define MSM_VERSION_PATCHLEVEL 0
44
45static const struct drm_mode_config_funcs mode_config_funcs = {
46 .fb_create = msm_framebuffer_create,
47 .output_poll_changed = drm_fb_helper_output_poll_changed,
48 .atomic_check = drm_atomic_helper_check,
49 .atomic_commit = drm_atomic_helper_commit,
50};
51
52static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
53 .atomic_commit_tail = msm_atomic_commit_tail,
54};
55
56#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
57static bool reglog = false;
58MODULE_PARM_DESC(reglog, "Enable register read/write logging");
59module_param(reglog, bool, 0600);
60#else
61#define reglog 0
62#endif
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate = false;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82/*
83 * Util/helpers:
84 */
85
86struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
87 const char *name)
88{
89 int i;
90 char n[32];
91
92 snprintf(n, sizeof(n), "%s_clk", name);
93
94 for (i = 0; bulk && i < count; i++) {
95 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
96 return bulk[i].clk;
97 }
98
99
100 return NULL;
101}
102
103struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
104{
105 struct clk *clk;
106 char name2[32];
107
108 clk = devm_clk_get(&pdev->dev, name);
109 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
110 return clk;
111
112 snprintf(name2, sizeof(name2), "%s_clk", name);
113
114 clk = devm_clk_get(&pdev->dev, name2);
115 if (!IS_ERR(clk))
116 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
117 "\"%s\" instead of \"%s\"\n", name, name2);
118
119 return clk;
120}
121
122void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
123 const char *dbgname)
124{
125 struct resource *res;
126 unsigned long size;
127 void __iomem *ptr;
128
129 if (name)
130 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
131 else
132 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
133
134 if (!res) {
135 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
136 return ERR_PTR(-EINVAL);
137 }
138
139 size = resource_size(res);
140
141 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
142 if (!ptr) {
143 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
144 return ERR_PTR(-ENOMEM);
145 }
146
147 if (reglog)
148 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
149
150 return ptr;
151}
152
153void msm_writel(u32 data, void __iomem *addr)
154{
155 if (reglog)
156 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
157 writel(data, addr);
158}
159
160u32 msm_readl(const void __iomem *addr)
161{
162 u32 val = readl(addr);
163 if (reglog)
164 pr_err("IO:R %p %08x\n", addr, val);
165 return val;
166}
167
168struct msm_vblank_work {
169 struct work_struct work;
170 int crtc_id;
171 bool enable;
172 struct msm_drm_private *priv;
173};
174
175static void vblank_ctrl_worker(struct work_struct *work)
176{
177 struct msm_vblank_work *vbl_work = container_of(work,
178 struct msm_vblank_work, work);
179 struct msm_drm_private *priv = vbl_work->priv;
180 struct msm_kms *kms = priv->kms;
181
182 if (vbl_work->enable)
183 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
184 else
185 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
186
187 kfree(vbl_work);
188}
189
190static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
191 int crtc_id, bool enable)
192{
193 struct msm_vblank_work *vbl_work;
194
195 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
196 if (!vbl_work)
197 return -ENOMEM;
198
199 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
200
201 vbl_work->crtc_id = crtc_id;
202 vbl_work->enable = enable;
203 vbl_work->priv = priv;
204
205 queue_work(priv->wq, &vbl_work->work);
206
207 return 0;
208}
209
210static int msm_drm_uninit(struct device *dev)
211{
212 struct platform_device *pdev = to_platform_device(dev);
213 struct drm_device *ddev = platform_get_drvdata(pdev);
214 struct msm_drm_private *priv = ddev->dev_private;
215 struct msm_kms *kms = priv->kms;
216 struct msm_mdss *mdss = priv->mdss;
217 int i;
218
219 /*
220 * Shutdown the hw if we're far enough along where things might be on.
221 * If we run this too early, we'll end up panicking in any variety of
222 * places. Since we don't register the drm device until late in
223 * msm_drm_init, drm_dev->registered is used as an indicator that the
224 * shutdown will be successful.
225 */
226 if (ddev->registered) {
227 drm_dev_unregister(ddev);
228 drm_atomic_helper_shutdown(ddev);
229 }
230
231 /* We must cancel and cleanup any pending vblank enable/disable
232 * work before drm_irq_uninstall() to avoid work re-enabling an
233 * irq after uninstall has disabled it.
234 */
235
236 flush_workqueue(priv->wq);
237
238 /* clean up event worker threads */
239 for (i = 0; i < priv->num_crtcs; i++) {
240 if (priv->event_thread[i].thread) {
241 kthread_destroy_worker(&priv->event_thread[i].worker);
242 priv->event_thread[i].thread = NULL;
243 }
244 }
245
246 msm_gem_shrinker_cleanup(ddev);
247
248 drm_kms_helper_poll_fini(ddev);
249
250 msm_perf_debugfs_cleanup(priv);
251 msm_rd_debugfs_cleanup(priv);
252
253#ifdef CONFIG_DRM_FBDEV_EMULATION
254 if (fbdev && priv->fbdev)
255 msm_fbdev_free(ddev);
256#endif
257
258 drm_mode_config_cleanup(ddev);
259
260 pm_runtime_get_sync(dev);
261 drm_irq_uninstall(ddev);
262 pm_runtime_put_sync(dev);
263
264 if (kms && kms->funcs)
265 kms->funcs->destroy(kms);
266
267 if (priv->vram.paddr) {
268 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
269 drm_mm_takedown(&priv->vram.mm);
270 dma_free_attrs(dev, priv->vram.size, NULL,
271 priv->vram.paddr, attrs);
272 }
273
274 component_unbind_all(dev, ddev);
275
276 if (mdss && mdss->funcs)
277 mdss->funcs->destroy(ddev);
278
279 ddev->dev_private = NULL;
280 drm_dev_put(ddev);
281
282 destroy_workqueue(priv->wq);
283 kfree(priv);
284
285 return 0;
286}
287
288#define KMS_MDP4 4
289#define KMS_MDP5 5
290#define KMS_DPU 3
291
292static int get_mdp_ver(struct platform_device *pdev)
293{
294 struct device *dev = &pdev->dev;
295
296 return (int) (unsigned long) of_device_get_match_data(dev);
297}
298
299#include <linux/of_address.h>
300
301bool msm_use_mmu(struct drm_device *dev)
302{
303 struct msm_drm_private *priv = dev->dev_private;
304
305 /* a2xx comes with its own MMU */
306 return priv->is_a2xx || iommu_present(&platform_bus_type);
307}
308
309static int msm_init_vram(struct drm_device *dev)
310{
311 struct msm_drm_private *priv = dev->dev_private;
312 struct device_node *node;
313 unsigned long size = 0;
314 int ret = 0;
315
316 /* In the device-tree world, we could have a 'memory-region'
317 * phandle, which gives us a link to our "vram". Allocating
318 * is all nicely abstracted behind the dma api, but we need
319 * to know the entire size to allocate it all in one go. There
320 * are two cases:
321 * 1) device with no IOMMU, in which case we need exclusive
322 * access to a VRAM carveout big enough for all gpu
323 * buffers
324 * 2) device with IOMMU, but where the bootloader puts up
325 * a splash screen. In this case, the VRAM carveout
326 * need only be large enough for fbdev fb. But we need
327 * exclusive access to the buffer to avoid the kernel
328 * using those pages for other purposes (which appears
329 * as corruption on screen before we have a chance to
330 * load and do initial modeset)
331 */
332
333 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
334 if (node) {
335 struct resource r;
336 ret = of_address_to_resource(node, 0, &r);
337 of_node_put(node);
338 if (ret)
339 return ret;
340 size = r.end - r.start;
341 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
342
343 /* if we have no IOMMU, then we need to use carveout allocator.
344 * Grab the entire CMA chunk carved out in early startup in
345 * mach-msm:
346 */
347 } else if (!msm_use_mmu(dev)) {
348 DRM_INFO("using %s VRAM carveout\n", vram);
349 size = memparse(vram, NULL);
350 }
351
352 if (size) {
353 unsigned long attrs = 0;
354 void *p;
355
356 priv->vram.size = size;
357
358 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
359 spin_lock_init(&priv->vram.lock);
360
361 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
362 attrs |= DMA_ATTR_WRITE_COMBINE;
363
364 /* note that for no-kernel-mapping, the vaddr returned
365 * is bogus, but non-null if allocation succeeded:
366 */
367 p = dma_alloc_attrs(dev->dev, size,
368 &priv->vram.paddr, GFP_KERNEL, attrs);
369 if (!p) {
370 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
371 priv->vram.paddr = 0;
372 return -ENOMEM;
373 }
374
375 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
376 (uint32_t)priv->vram.paddr,
377 (uint32_t)(priv->vram.paddr + size));
378 }
379
380 return ret;
381}
382
383static int msm_drm_init(struct device *dev, struct drm_driver *drv)
384{
385 struct platform_device *pdev = to_platform_device(dev);
386 struct drm_device *ddev;
387 struct msm_drm_private *priv;
388 struct msm_kms *kms;
389 struct msm_mdss *mdss;
390 int ret, i;
391 struct sched_param param;
392
393 ddev = drm_dev_alloc(drv, dev);
394 if (IS_ERR(ddev)) {
395 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
396 return PTR_ERR(ddev);
397 }
398
399 platform_set_drvdata(pdev, ddev);
400
401 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
402 if (!priv) {
403 ret = -ENOMEM;
404 goto err_put_drm_dev;
405 }
406
407 ddev->dev_private = priv;
408 priv->dev = ddev;
409
410 switch (get_mdp_ver(pdev)) {
411 case KMS_MDP5:
412 ret = mdp5_mdss_init(ddev);
413 break;
414 case KMS_DPU:
415 ret = dpu_mdss_init(ddev);
416 break;
417 default:
418 ret = 0;
419 break;
420 }
421 if (ret)
422 goto err_free_priv;
423
424 mdss = priv->mdss;
425
426 priv->wq = alloc_ordered_workqueue("msm", 0);
427
428 INIT_WORK(&priv->free_work, msm_gem_free_work);
429 init_llist_head(&priv->free_list);
430
431 INIT_LIST_HEAD(&priv->inactive_list);
432
433 drm_mode_config_init(ddev);
434
435 /* Bind all our sub-components: */
436 ret = component_bind_all(dev, ddev);
437 if (ret)
438 goto err_destroy_mdss;
439
440 ret = msm_init_vram(ddev);
441 if (ret)
442 goto err_msm_uninit;
443
444 msm_gem_shrinker_init(ddev);
445
446 switch (get_mdp_ver(pdev)) {
447 case KMS_MDP4:
448 kms = mdp4_kms_init(ddev);
449 priv->kms = kms;
450 break;
451 case KMS_MDP5:
452 kms = mdp5_kms_init(ddev);
453 break;
454 case KMS_DPU:
455 kms = dpu_kms_init(ddev);
456 priv->kms = kms;
457 break;
458 default:
459 /* valid only for the dummy headless case, where of_node=NULL */
460 WARN_ON(dev->of_node);
461 kms = NULL;
462 break;
463 }
464
465 if (IS_ERR(kms)) {
466 DRM_DEV_ERROR(dev, "failed to load kms\n");
467 ret = PTR_ERR(kms);
468 priv->kms = NULL;
469 goto err_msm_uninit;
470 }
471
472 /* Enable normalization of plane zpos */
473 ddev->mode_config.normalize_zpos = true;
474
475 if (kms) {
476 kms->dev = ddev;
477 ret = kms->funcs->hw_init(kms);
478 if (ret) {
479 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
480 goto err_msm_uninit;
481 }
482 }
483
484 ddev->mode_config.funcs = &mode_config_funcs;
485 ddev->mode_config.helper_private = &mode_config_helper_funcs;
486
487 /**
488 * this priority was found during empiric testing to have appropriate
489 * realtime scheduling to process display updates and interact with
490 * other real time and normal priority task
491 */
492 param.sched_priority = 16;
493 for (i = 0; i < priv->num_crtcs; i++) {
494 /* initialize event thread */
495 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
496 kthread_init_worker(&priv->event_thread[i].worker);
497 priv->event_thread[i].dev = ddev;
498 priv->event_thread[i].thread =
499 kthread_run(kthread_worker_fn,
500 &priv->event_thread[i].worker,
501 "crtc_event:%d", priv->event_thread[i].crtc_id);
502 if (IS_ERR(priv->event_thread[i].thread)) {
503 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
504 priv->event_thread[i].thread = NULL;
505 goto err_msm_uninit;
506 }
507
508 ret = sched_setscheduler(priv->event_thread[i].thread,
509 SCHED_FIFO, ¶m);
510 if (ret)
511 dev_warn(dev, "event_thread set priority failed:%d\n",
512 ret);
513 }
514
515 ret = drm_vblank_init(ddev, priv->num_crtcs);
516 if (ret < 0) {
517 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
518 goto err_msm_uninit;
519 }
520
521 if (kms) {
522 pm_runtime_get_sync(dev);
523 ret = drm_irq_install(ddev, kms->irq);
524 pm_runtime_put_sync(dev);
525 if (ret < 0) {
526 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
527 goto err_msm_uninit;
528 }
529 }
530
531 ret = drm_dev_register(ddev, 0);
532 if (ret)
533 goto err_msm_uninit;
534
535 drm_mode_config_reset(ddev);
536
537#ifdef CONFIG_DRM_FBDEV_EMULATION
538 if (kms && fbdev)
539 priv->fbdev = msm_fbdev_init(ddev);
540#endif
541
542 ret = msm_debugfs_late_init(ddev);
543 if (ret)
544 goto err_msm_uninit;
545
546 drm_kms_helper_poll_init(ddev);
547
548 return 0;
549
550err_msm_uninit:
551 msm_drm_uninit(dev);
552 return ret;
553err_destroy_mdss:
554 if (mdss && mdss->funcs)
555 mdss->funcs->destroy(ddev);
556err_free_priv:
557 kfree(priv);
558err_put_drm_dev:
559 drm_dev_put(ddev);
560 return ret;
561}
562
563/*
564 * DRM operations:
565 */
566
567static void load_gpu(struct drm_device *dev)
568{
569 static DEFINE_MUTEX(init_lock);
570 struct msm_drm_private *priv = dev->dev_private;
571
572 mutex_lock(&init_lock);
573
574 if (!priv->gpu)
575 priv->gpu = adreno_load_gpu(dev);
576
577 mutex_unlock(&init_lock);
578}
579
580static int context_init(struct drm_device *dev, struct drm_file *file)
581{
582 struct msm_drm_private *priv = dev->dev_private;
583 struct msm_file_private *ctx;
584
585 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
586 if (!ctx)
587 return -ENOMEM;
588
589 msm_submitqueue_init(dev, ctx);
590
591 ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
592 file->driver_priv = ctx;
593
594 return 0;
595}
596
597static int msm_open(struct drm_device *dev, struct drm_file *file)
598{
599 /* For now, load gpu on open.. to avoid the requirement of having
600 * firmware in the initrd.
601 */
602 load_gpu(dev);
603
604 return context_init(dev, file);
605}
606
607static void context_close(struct msm_file_private *ctx)
608{
609 msm_submitqueue_close(ctx);
610 kfree(ctx);
611}
612
613static void msm_postclose(struct drm_device *dev, struct drm_file *file)
614{
615 struct msm_drm_private *priv = dev->dev_private;
616 struct msm_file_private *ctx = file->driver_priv;
617
618 mutex_lock(&dev->struct_mutex);
619 if (ctx == priv->lastctx)
620 priv->lastctx = NULL;
621 mutex_unlock(&dev->struct_mutex);
622
623 context_close(ctx);
624}
625
626static irqreturn_t msm_irq(int irq, void *arg)
627{
628 struct drm_device *dev = arg;
629 struct msm_drm_private *priv = dev->dev_private;
630 struct msm_kms *kms = priv->kms;
631 BUG_ON(!kms);
632 return kms->funcs->irq(kms);
633}
634
635static void msm_irq_preinstall(struct drm_device *dev)
636{
637 struct msm_drm_private *priv = dev->dev_private;
638 struct msm_kms *kms = priv->kms;
639 BUG_ON(!kms);
640 kms->funcs->irq_preinstall(kms);
641}
642
643static int msm_irq_postinstall(struct drm_device *dev)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct msm_kms *kms = priv->kms;
647 BUG_ON(!kms);
648
649 if (kms->funcs->irq_postinstall)
650 return kms->funcs->irq_postinstall(kms);
651
652 return 0;
653}
654
655static void msm_irq_uninstall(struct drm_device *dev)
656{
657 struct msm_drm_private *priv = dev->dev_private;
658 struct msm_kms *kms = priv->kms;
659 BUG_ON(!kms);
660 kms->funcs->irq_uninstall(kms);
661}
662
663static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
664{
665 struct msm_drm_private *priv = dev->dev_private;
666 struct msm_kms *kms = priv->kms;
667 if (!kms)
668 return -ENXIO;
669 DBG("dev=%p, crtc=%u", dev, pipe);
670 return vblank_ctrl_queue_work(priv, pipe, true);
671}
672
673static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
674{
675 struct msm_drm_private *priv = dev->dev_private;
676 struct msm_kms *kms = priv->kms;
677 if (!kms)
678 return;
679 DBG("dev=%p, crtc=%u", dev, pipe);
680 vblank_ctrl_queue_work(priv, pipe, false);
681}
682
683/*
684 * DRM ioctls:
685 */
686
687static int msm_ioctl_get_param(struct drm_device *dev, void *data,
688 struct drm_file *file)
689{
690 struct msm_drm_private *priv = dev->dev_private;
691 struct drm_msm_param *args = data;
692 struct msm_gpu *gpu;
693
694 /* for now, we just have 3d pipe.. eventually this would need to
695 * be more clever to dispatch to appropriate gpu module:
696 */
697 if (args->pipe != MSM_PIPE_3D0)
698 return -EINVAL;
699
700 gpu = priv->gpu;
701
702 if (!gpu)
703 return -ENXIO;
704
705 return gpu->funcs->get_param(gpu, args->param, &args->value);
706}
707
708static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
709 struct drm_file *file)
710{
711 struct drm_msm_gem_new *args = data;
712
713 if (args->flags & ~MSM_BO_FLAGS) {
714 DRM_ERROR("invalid flags: %08x\n", args->flags);
715 return -EINVAL;
716 }
717
718 return msm_gem_new_handle(dev, file, args->size,
719 args->flags, &args->handle, NULL);
720}
721
722static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
723{
724 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
725}
726
727static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
728 struct drm_file *file)
729{
730 struct drm_msm_gem_cpu_prep *args = data;
731 struct drm_gem_object *obj;
732 ktime_t timeout = to_ktime(args->timeout);
733 int ret;
734
735 if (args->op & ~MSM_PREP_FLAGS) {
736 DRM_ERROR("invalid op: %08x\n", args->op);
737 return -EINVAL;
738 }
739
740 obj = drm_gem_object_lookup(file, args->handle);
741 if (!obj)
742 return -ENOENT;
743
744 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
745
746 drm_gem_object_put_unlocked(obj);
747
748 return ret;
749}
750
751static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
752 struct drm_file *file)
753{
754 struct drm_msm_gem_cpu_fini *args = data;
755 struct drm_gem_object *obj;
756 int ret;
757
758 obj = drm_gem_object_lookup(file, args->handle);
759 if (!obj)
760 return -ENOENT;
761
762 ret = msm_gem_cpu_fini(obj);
763
764 drm_gem_object_put_unlocked(obj);
765
766 return ret;
767}
768
769static int msm_ioctl_gem_info_iova(struct drm_device *dev,
770 struct drm_gem_object *obj, uint64_t *iova)
771{
772 struct msm_drm_private *priv = dev->dev_private;
773
774 if (!priv->gpu)
775 return -EINVAL;
776
777 /*
778 * Don't pin the memory here - just get an address so that userspace can
779 * be productive
780 */
781 return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
782}
783
784static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
785 struct drm_file *file)
786{
787 struct drm_msm_gem_info *args = data;
788 struct drm_gem_object *obj;
789 struct msm_gem_object *msm_obj;
790 int i, ret = 0;
791
792 if (args->pad)
793 return -EINVAL;
794
795 switch (args->info) {
796 case MSM_INFO_GET_OFFSET:
797 case MSM_INFO_GET_IOVA:
798 /* value returned as immediate, not pointer, so len==0: */
799 if (args->len)
800 return -EINVAL;
801 break;
802 case MSM_INFO_SET_NAME:
803 case MSM_INFO_GET_NAME:
804 break;
805 default:
806 return -EINVAL;
807 }
808
809 obj = drm_gem_object_lookup(file, args->handle);
810 if (!obj)
811 return -ENOENT;
812
813 msm_obj = to_msm_bo(obj);
814
815 switch (args->info) {
816 case MSM_INFO_GET_OFFSET:
817 args->value = msm_gem_mmap_offset(obj);
818 break;
819 case MSM_INFO_GET_IOVA:
820 ret = msm_ioctl_gem_info_iova(dev, obj, &args->value);
821 break;
822 case MSM_INFO_SET_NAME:
823 /* length check should leave room for terminating null: */
824 if (args->len >= sizeof(msm_obj->name)) {
825 ret = -EINVAL;
826 break;
827 }
828 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
829 args->len)) {
830 msm_obj->name[0] = '\0';
831 ret = -EFAULT;
832 break;
833 }
834 msm_obj->name[args->len] = '\0';
835 for (i = 0; i < args->len; i++) {
836 if (!isprint(msm_obj->name[i])) {
837 msm_obj->name[i] = '\0';
838 break;
839 }
840 }
841 break;
842 case MSM_INFO_GET_NAME:
843 if (args->value && (args->len < strlen(msm_obj->name))) {
844 ret = -EINVAL;
845 break;
846 }
847 args->len = strlen(msm_obj->name);
848 if (args->value) {
849 if (copy_to_user(u64_to_user_ptr(args->value),
850 msm_obj->name, args->len))
851 ret = -EFAULT;
852 }
853 break;
854 }
855
856 drm_gem_object_put_unlocked(obj);
857
858 return ret;
859}
860
861static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
862 struct drm_file *file)
863{
864 struct msm_drm_private *priv = dev->dev_private;
865 struct drm_msm_wait_fence *args = data;
866 ktime_t timeout = to_ktime(args->timeout);
867 struct msm_gpu_submitqueue *queue;
868 struct msm_gpu *gpu = priv->gpu;
869 int ret;
870
871 if (args->pad) {
872 DRM_ERROR("invalid pad: %08x\n", args->pad);
873 return -EINVAL;
874 }
875
876 if (!gpu)
877 return 0;
878
879 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
880 if (!queue)
881 return -ENOENT;
882
883 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
884 true);
885
886 msm_submitqueue_put(queue);
887 return ret;
888}
889
890static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
891 struct drm_file *file)
892{
893 struct drm_msm_gem_madvise *args = data;
894 struct drm_gem_object *obj;
895 int ret;
896
897 switch (args->madv) {
898 case MSM_MADV_DONTNEED:
899 case MSM_MADV_WILLNEED:
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 ret = mutex_lock_interruptible(&dev->struct_mutex);
906 if (ret)
907 return ret;
908
909 obj = drm_gem_object_lookup(file, args->handle);
910 if (!obj) {
911 ret = -ENOENT;
912 goto unlock;
913 }
914
915 ret = msm_gem_madvise(obj, args->madv);
916 if (ret >= 0) {
917 args->retained = ret;
918 ret = 0;
919 }
920
921 drm_gem_object_put(obj);
922
923unlock:
924 mutex_unlock(&dev->struct_mutex);
925 return ret;
926}
927
928
929static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
930 struct drm_file *file)
931{
932 struct drm_msm_submitqueue *args = data;
933
934 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
935 return -EINVAL;
936
937 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
938 args->flags, &args->id);
939}
940
941static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
942 struct drm_file *file)
943{
944 return msm_submitqueue_query(dev, file->driver_priv, data);
945}
946
947static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
948 struct drm_file *file)
949{
950 u32 id = *(u32 *) data;
951
952 return msm_submitqueue_remove(file->driver_priv, id);
953}
954
955static const struct drm_ioctl_desc msm_ioctls[] = {
956 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
957 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
958 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
959 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
960 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
961 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
962 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
963 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
964 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
965 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
966 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
967};
968
969static const struct vm_operations_struct vm_ops = {
970 .fault = msm_gem_fault,
971 .open = drm_gem_vm_open,
972 .close = drm_gem_vm_close,
973};
974
975static const struct file_operations fops = {
976 .owner = THIS_MODULE,
977 .open = drm_open,
978 .release = drm_release,
979 .unlocked_ioctl = drm_ioctl,
980 .compat_ioctl = drm_compat_ioctl,
981 .poll = drm_poll,
982 .read = drm_read,
983 .llseek = no_llseek,
984 .mmap = msm_gem_mmap,
985};
986
987static struct drm_driver msm_driver = {
988 .driver_features = DRIVER_GEM |
989 DRIVER_RENDER |
990 DRIVER_ATOMIC |
991 DRIVER_MODESET,
992 .open = msm_open,
993 .postclose = msm_postclose,
994 .lastclose = drm_fb_helper_lastclose,
995 .irq_handler = msm_irq,
996 .irq_preinstall = msm_irq_preinstall,
997 .irq_postinstall = msm_irq_postinstall,
998 .irq_uninstall = msm_irq_uninstall,
999 .enable_vblank = msm_enable_vblank,
1000 .disable_vblank = msm_disable_vblank,
1001 .gem_free_object_unlocked = msm_gem_free_object,
1002 .gem_vm_ops = &vm_ops,
1003 .dumb_create = msm_gem_dumb_create,
1004 .dumb_map_offset = msm_gem_dumb_map_offset,
1005 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1006 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1007 .gem_prime_pin = msm_gem_prime_pin,
1008 .gem_prime_unpin = msm_gem_prime_unpin,
1009 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
1010 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1011 .gem_prime_vmap = msm_gem_prime_vmap,
1012 .gem_prime_vunmap = msm_gem_prime_vunmap,
1013 .gem_prime_mmap = msm_gem_prime_mmap,
1014#ifdef CONFIG_DEBUG_FS
1015 .debugfs_init = msm_debugfs_init,
1016#endif
1017 .ioctls = msm_ioctls,
1018 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1019 .fops = &fops,
1020 .name = "msm",
1021 .desc = "MSM Snapdragon DRM",
1022 .date = "20130625",
1023 .major = MSM_VERSION_MAJOR,
1024 .minor = MSM_VERSION_MINOR,
1025 .patchlevel = MSM_VERSION_PATCHLEVEL,
1026};
1027
1028#ifdef CONFIG_PM_SLEEP
1029static int msm_pm_suspend(struct device *dev)
1030{
1031 struct drm_device *ddev = dev_get_drvdata(dev);
1032 struct msm_drm_private *priv = ddev->dev_private;
1033
1034 if (WARN_ON(priv->pm_state))
1035 drm_atomic_state_put(priv->pm_state);
1036
1037 priv->pm_state = drm_atomic_helper_suspend(ddev);
1038 if (IS_ERR(priv->pm_state)) {
1039 int ret = PTR_ERR(priv->pm_state);
1040 DRM_ERROR("Failed to suspend dpu, %d\n", ret);
1041 return ret;
1042 }
1043
1044 return 0;
1045}
1046
1047static int msm_pm_resume(struct device *dev)
1048{
1049 struct drm_device *ddev = dev_get_drvdata(dev);
1050 struct msm_drm_private *priv = ddev->dev_private;
1051 int ret;
1052
1053 if (WARN_ON(!priv->pm_state))
1054 return -ENOENT;
1055
1056 ret = drm_atomic_helper_resume(ddev, priv->pm_state);
1057 if (!ret)
1058 priv->pm_state = NULL;
1059
1060 return ret;
1061}
1062#endif
1063
1064#ifdef CONFIG_PM
1065static int msm_runtime_suspend(struct device *dev)
1066{
1067 struct drm_device *ddev = dev_get_drvdata(dev);
1068 struct msm_drm_private *priv = ddev->dev_private;
1069 struct msm_mdss *mdss = priv->mdss;
1070
1071 DBG("");
1072
1073 if (mdss && mdss->funcs)
1074 return mdss->funcs->disable(mdss);
1075
1076 return 0;
1077}
1078
1079static int msm_runtime_resume(struct device *dev)
1080{
1081 struct drm_device *ddev = dev_get_drvdata(dev);
1082 struct msm_drm_private *priv = ddev->dev_private;
1083 struct msm_mdss *mdss = priv->mdss;
1084
1085 DBG("");
1086
1087 if (mdss && mdss->funcs)
1088 return mdss->funcs->enable(mdss);
1089
1090 return 0;
1091}
1092#endif
1093
1094static const struct dev_pm_ops msm_pm_ops = {
1095 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1096 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1097};
1098
1099/*
1100 * Componentized driver support:
1101 */
1102
1103/*
1104 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1105 * so probably some room for some helpers
1106 */
1107static int compare_of(struct device *dev, void *data)
1108{
1109 return dev->of_node == data;
1110}
1111
1112/*
1113 * Identify what components need to be added by parsing what remote-endpoints
1114 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1115 * is no external component that we need to add since LVDS is within MDP4
1116 * itself.
1117 */
1118static int add_components_mdp(struct device *mdp_dev,
1119 struct component_match **matchptr)
1120{
1121 struct device_node *np = mdp_dev->of_node;
1122 struct device_node *ep_node;
1123 struct device *master_dev;
1124
1125 /*
1126 * on MDP4 based platforms, the MDP platform device is the component
1127 * master that adds other display interface components to itself.
1128 *
1129 * on MDP5 based platforms, the MDSS platform device is the component
1130 * master that adds MDP5 and other display interface components to
1131 * itself.
1132 */
1133 if (of_device_is_compatible(np, "qcom,mdp4"))
1134 master_dev = mdp_dev;
1135 else
1136 master_dev = mdp_dev->parent;
1137
1138 for_each_endpoint_of_node(np, ep_node) {
1139 struct device_node *intf;
1140 struct of_endpoint ep;
1141 int ret;
1142
1143 ret = of_graph_parse_endpoint(ep_node, &ep);
1144 if (ret) {
1145 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1146 of_node_put(ep_node);
1147 return ret;
1148 }
1149
1150 /*
1151 * The LCDC/LVDS port on MDP4 is a speacial case where the
1152 * remote-endpoint isn't a component that we need to add
1153 */
1154 if (of_device_is_compatible(np, "qcom,mdp4") &&
1155 ep.port == 0)
1156 continue;
1157
1158 /*
1159 * It's okay if some of the ports don't have a remote endpoint
1160 * specified. It just means that the port isn't connected to
1161 * any external interface.
1162 */
1163 intf = of_graph_get_remote_port_parent(ep_node);
1164 if (!intf)
1165 continue;
1166
1167 if (of_device_is_available(intf))
1168 drm_of_component_match_add(master_dev, matchptr,
1169 compare_of, intf);
1170
1171 of_node_put(intf);
1172 }
1173
1174 return 0;
1175}
1176
1177static int compare_name_mdp(struct device *dev, void *data)
1178{
1179 return (strstr(dev_name(dev), "mdp") != NULL);
1180}
1181
1182static int add_display_components(struct device *dev,
1183 struct component_match **matchptr)
1184{
1185 struct device *mdp_dev;
1186 int ret;
1187
1188 /*
1189 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1190 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1191 * Populate the children devices, find the MDP5/DPU node, and then add
1192 * the interfaces to our components list.
1193 */
1194 if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
1195 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) {
1196 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1197 if (ret) {
1198 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1199 return ret;
1200 }
1201
1202 mdp_dev = device_find_child(dev, NULL, compare_name_mdp);
1203 if (!mdp_dev) {
1204 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1205 of_platform_depopulate(dev);
1206 return -ENODEV;
1207 }
1208
1209 put_device(mdp_dev);
1210
1211 /* add the MDP component itself */
1212 drm_of_component_match_add(dev, matchptr, compare_of,
1213 mdp_dev->of_node);
1214 } else {
1215 /* MDP4 */
1216 mdp_dev = dev;
1217 }
1218
1219 ret = add_components_mdp(mdp_dev, matchptr);
1220 if (ret)
1221 of_platform_depopulate(dev);
1222
1223 return ret;
1224}
1225
1226/*
1227 * We don't know what's the best binding to link the gpu with the drm device.
1228 * Fow now, we just hunt for all the possible gpus that we support, and add them
1229 * as components.
1230 */
1231static const struct of_device_id msm_gpu_match[] = {
1232 { .compatible = "qcom,adreno" },
1233 { .compatible = "qcom,adreno-3xx" },
1234 { .compatible = "amd,imageon" },
1235 { .compatible = "qcom,kgsl-3d0" },
1236 { },
1237};
1238
1239static int add_gpu_components(struct device *dev,
1240 struct component_match **matchptr)
1241{
1242 struct device_node *np;
1243
1244 np = of_find_matching_node(NULL, msm_gpu_match);
1245 if (!np)
1246 return 0;
1247
1248 if (of_device_is_available(np))
1249 drm_of_component_match_add(dev, matchptr, compare_of, np);
1250
1251 of_node_put(np);
1252
1253 return 0;
1254}
1255
1256static int msm_drm_bind(struct device *dev)
1257{
1258 return msm_drm_init(dev, &msm_driver);
1259}
1260
1261static void msm_drm_unbind(struct device *dev)
1262{
1263 msm_drm_uninit(dev);
1264}
1265
1266static const struct component_master_ops msm_drm_ops = {
1267 .bind = msm_drm_bind,
1268 .unbind = msm_drm_unbind,
1269};
1270
1271/*
1272 * Platform driver:
1273 */
1274
1275static int msm_pdev_probe(struct platform_device *pdev)
1276{
1277 struct component_match *match = NULL;
1278 int ret;
1279
1280 if (get_mdp_ver(pdev)) {
1281 ret = add_display_components(&pdev->dev, &match);
1282 if (ret)
1283 return ret;
1284 }
1285
1286 ret = add_gpu_components(&pdev->dev, &match);
1287 if (ret)
1288 goto fail;
1289
1290 /* on all devices that I am aware of, iommu's which can map
1291 * any address the cpu can see are used:
1292 */
1293 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1294 if (ret)
1295 goto fail;
1296
1297 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1298 if (ret)
1299 goto fail;
1300
1301 return 0;
1302
1303fail:
1304 of_platform_depopulate(&pdev->dev);
1305 return ret;
1306}
1307
1308static int msm_pdev_remove(struct platform_device *pdev)
1309{
1310 component_master_del(&pdev->dev, &msm_drm_ops);
1311 of_platform_depopulate(&pdev->dev);
1312
1313 return 0;
1314}
1315
1316static const struct of_device_id dt_match[] = {
1317 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1318 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1319 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1320 {}
1321};
1322MODULE_DEVICE_TABLE(of, dt_match);
1323
1324static struct platform_driver msm_platform_driver = {
1325 .probe = msm_pdev_probe,
1326 .remove = msm_pdev_remove,
1327 .driver = {
1328 .name = "msm",
1329 .of_match_table = dt_match,
1330 .pm = &msm_pm_ops,
1331 },
1332};
1333
1334static int __init msm_drm_register(void)
1335{
1336 if (!modeset)
1337 return -EINVAL;
1338
1339 DBG("init");
1340 msm_mdp_register();
1341 msm_dpu_register();
1342 msm_dsi_register();
1343 msm_edp_register();
1344 msm_hdmi_register();
1345 adreno_register();
1346 return platform_driver_register(&msm_platform_driver);
1347}
1348
1349static void __exit msm_drm_unregister(void)
1350{
1351 DBG("fini");
1352 platform_driver_unregister(&msm_platform_driver);
1353 msm_hdmi_unregister();
1354 adreno_unregister();
1355 msm_edp_unregister();
1356 msm_dsi_unregister();
1357 msm_mdp_unregister();
1358 msm_dpu_unregister();
1359}
1360
1361module_init(msm_drm_register);
1362module_exit(msm_drm_unregister);
1363
1364MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1365MODULE_DESCRIPTION("MSM DRM Driver");
1366MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_drv.h"
19#include "msm_gpu.h"
20#include "msm_kms.h"
21
22static void msm_fb_output_poll_changed(struct drm_device *dev)
23{
24 struct msm_drm_private *priv = dev->dev_private;
25 if (priv->fbdev)
26 drm_fb_helper_hotplug_event(priv->fbdev);
27}
28
29static const struct drm_mode_config_funcs mode_config_funcs = {
30 .fb_create = msm_framebuffer_create,
31 .output_poll_changed = msm_fb_output_poll_changed,
32};
33
34int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
35{
36 struct msm_drm_private *priv = dev->dev_private;
37 int idx = priv->num_mmus++;
38
39 if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
40 return -EINVAL;
41
42 priv->mmus[idx] = mmu;
43
44 return idx;
45}
46
47#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
48static bool reglog = false;
49MODULE_PARM_DESC(reglog, "Enable register read/write logging");
50module_param(reglog, bool, 0600);
51#else
52#define reglog 0
53#endif
54
55static char *vram;
56MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
57module_param(vram, charp, 0);
58
59/*
60 * Util/helpers:
61 */
62
63void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
64 const char *dbgname)
65{
66 struct resource *res;
67 unsigned long size;
68 void __iomem *ptr;
69
70 if (name)
71 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
72 else
73 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
74
75 if (!res) {
76 dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
77 return ERR_PTR(-EINVAL);
78 }
79
80 size = resource_size(res);
81
82 ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
83 if (!ptr) {
84 dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
85 return ERR_PTR(-ENOMEM);
86 }
87
88 if (reglog)
89 printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
90
91 return ptr;
92}
93
94void msm_writel(u32 data, void __iomem *addr)
95{
96 if (reglog)
97 printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
98 writel(data, addr);
99}
100
101u32 msm_readl(const void __iomem *addr)
102{
103 u32 val = readl(addr);
104 if (reglog)
105 printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
106 return val;
107}
108
109/*
110 * DRM operations:
111 */
112
113static int msm_unload(struct drm_device *dev)
114{
115 struct msm_drm_private *priv = dev->dev_private;
116 struct msm_kms *kms = priv->kms;
117 struct msm_gpu *gpu = priv->gpu;
118
119 drm_kms_helper_poll_fini(dev);
120 drm_mode_config_cleanup(dev);
121 drm_vblank_cleanup(dev);
122
123 pm_runtime_get_sync(dev->dev);
124 drm_irq_uninstall(dev);
125 pm_runtime_put_sync(dev->dev);
126
127 flush_workqueue(priv->wq);
128 destroy_workqueue(priv->wq);
129
130 if (kms) {
131 pm_runtime_disable(dev->dev);
132 kms->funcs->destroy(kms);
133 }
134
135 if (gpu) {
136 mutex_lock(&dev->struct_mutex);
137 gpu->funcs->pm_suspend(gpu);
138 gpu->funcs->destroy(gpu);
139 mutex_unlock(&dev->struct_mutex);
140 }
141
142 if (priv->vram.paddr) {
143 DEFINE_DMA_ATTRS(attrs);
144 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
145 drm_mm_takedown(&priv->vram.mm);
146 dma_free_attrs(dev->dev, priv->vram.size, NULL,
147 priv->vram.paddr, &attrs);
148 }
149
150 component_unbind_all(dev->dev, dev);
151
152 dev->dev_private = NULL;
153
154 kfree(priv);
155
156 return 0;
157}
158
159static int get_mdp_ver(struct platform_device *pdev)
160{
161#ifdef CONFIG_OF
162 const static struct of_device_id match_types[] = { {
163 .compatible = "qcom,mdss_mdp",
164 .data = (void *)5,
165 }, {
166 /* end node */
167 } };
168 struct device *dev = &pdev->dev;
169 const struct of_device_id *match;
170 match = of_match_node(match_types, dev->of_node);
171 if (match)
172 return (int)match->data;
173#endif
174 return 4;
175}
176
177static int msm_load(struct drm_device *dev, unsigned long flags)
178{
179 struct platform_device *pdev = dev->platformdev;
180 struct msm_drm_private *priv;
181 struct msm_kms *kms;
182 int ret;
183
184
185 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
186 if (!priv) {
187 dev_err(dev->dev, "failed to allocate private data\n");
188 return -ENOMEM;
189 }
190
191 dev->dev_private = priv;
192
193 priv->wq = alloc_ordered_workqueue("msm", 0);
194 init_waitqueue_head(&priv->fence_event);
195
196 INIT_LIST_HEAD(&priv->inactive_list);
197 INIT_LIST_HEAD(&priv->fence_cbs);
198
199 drm_mode_config_init(dev);
200
201 /* if we have no IOMMU, then we need to use carveout allocator.
202 * Grab the entire CMA chunk carved out in early startup in
203 * mach-msm:
204 */
205 if (!iommu_present(&platform_bus_type)) {
206 DEFINE_DMA_ATTRS(attrs);
207 unsigned long size;
208 void *p;
209
210 DBG("using %s VRAM carveout", vram);
211 size = memparse(vram, NULL);
212 priv->vram.size = size;
213
214 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
215
216 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
217 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
218
219 /* note that for no-kernel-mapping, the vaddr returned
220 * is bogus, but non-null if allocation succeeded:
221 */
222 p = dma_alloc_attrs(dev->dev, size,
223 &priv->vram.paddr, 0, &attrs);
224 if (!p) {
225 dev_err(dev->dev, "failed to allocate VRAM\n");
226 priv->vram.paddr = 0;
227 ret = -ENOMEM;
228 goto fail;
229 }
230
231 dev_info(dev->dev, "VRAM: %08x->%08x\n",
232 (uint32_t)priv->vram.paddr,
233 (uint32_t)(priv->vram.paddr + size));
234 }
235
236 platform_set_drvdata(pdev, dev);
237
238 /* Bind all our sub-components: */
239 ret = component_bind_all(dev->dev, dev);
240 if (ret)
241 return ret;
242
243 switch (get_mdp_ver(pdev)) {
244 case 4:
245 kms = mdp4_kms_init(dev);
246 break;
247 case 5:
248 kms = mdp5_kms_init(dev);
249 break;
250 default:
251 kms = ERR_PTR(-ENODEV);
252 break;
253 }
254
255 if (IS_ERR(kms)) {
256 /*
257 * NOTE: once we have GPU support, having no kms should not
258 * be considered fatal.. ideally we would still support gpu
259 * and (for example) use dmabuf/prime to share buffers with
260 * imx drm driver on iMX5
261 */
262 dev_err(dev->dev, "failed to load kms\n");
263 ret = PTR_ERR(kms);
264 goto fail;
265 }
266
267 priv->kms = kms;
268
269 if (kms) {
270 pm_runtime_enable(dev->dev);
271 ret = kms->funcs->hw_init(kms);
272 if (ret) {
273 dev_err(dev->dev, "kms hw init failed: %d\n", ret);
274 goto fail;
275 }
276 }
277
278 dev->mode_config.min_width = 0;
279 dev->mode_config.min_height = 0;
280 dev->mode_config.max_width = 2048;
281 dev->mode_config.max_height = 2048;
282 dev->mode_config.funcs = &mode_config_funcs;
283
284 ret = drm_vblank_init(dev, 1);
285 if (ret < 0) {
286 dev_err(dev->dev, "failed to initialize vblank\n");
287 goto fail;
288 }
289
290 pm_runtime_get_sync(dev->dev);
291 ret = drm_irq_install(dev);
292 pm_runtime_put_sync(dev->dev);
293 if (ret < 0) {
294 dev_err(dev->dev, "failed to install IRQ handler\n");
295 goto fail;
296 }
297
298#ifdef CONFIG_DRM_MSM_FBDEV
299 priv->fbdev = msm_fbdev_init(dev);
300#endif
301
302 drm_kms_helper_poll_init(dev);
303
304 return 0;
305
306fail:
307 msm_unload(dev);
308 return ret;
309}
310
311static void load_gpu(struct drm_device *dev)
312{
313 struct msm_drm_private *priv = dev->dev_private;
314 struct msm_gpu *gpu;
315
316 if (priv->gpu)
317 return;
318
319 mutex_lock(&dev->struct_mutex);
320 gpu = a3xx_gpu_init(dev);
321 if (IS_ERR(gpu)) {
322 dev_warn(dev->dev, "failed to load a3xx gpu\n");
323 gpu = NULL;
324 /* not fatal */
325 }
326
327 if (gpu) {
328 int ret;
329 gpu->funcs->pm_resume(gpu);
330 ret = gpu->funcs->hw_init(gpu);
331 if (ret) {
332 dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
333 gpu->funcs->destroy(gpu);
334 gpu = NULL;
335 } else {
336 /* give inactive pm a chance to kick in: */
337 msm_gpu_retire(gpu);
338 }
339
340 }
341
342 priv->gpu = gpu;
343
344 mutex_unlock(&dev->struct_mutex);
345}
346
347static int msm_open(struct drm_device *dev, struct drm_file *file)
348{
349 struct msm_file_private *ctx;
350
351 /* For now, load gpu on open.. to avoid the requirement of having
352 * firmware in the initrd.
353 */
354 load_gpu(dev);
355
356 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
357 if (!ctx)
358 return -ENOMEM;
359
360 file->driver_priv = ctx;
361
362 return 0;
363}
364
365static void msm_preclose(struct drm_device *dev, struct drm_file *file)
366{
367 struct msm_drm_private *priv = dev->dev_private;
368 struct msm_file_private *ctx = file->driver_priv;
369 struct msm_kms *kms = priv->kms;
370
371 if (kms)
372 kms->funcs->preclose(kms, file);
373
374 mutex_lock(&dev->struct_mutex);
375 if (ctx == priv->lastctx)
376 priv->lastctx = NULL;
377 mutex_unlock(&dev->struct_mutex);
378
379 kfree(ctx);
380}
381
382static void msm_lastclose(struct drm_device *dev)
383{
384 struct msm_drm_private *priv = dev->dev_private;
385 if (priv->fbdev) {
386 drm_modeset_lock_all(dev);
387 drm_fb_helper_restore_fbdev_mode(priv->fbdev);
388 drm_modeset_unlock_all(dev);
389 }
390}
391
392static irqreturn_t msm_irq(int irq, void *arg)
393{
394 struct drm_device *dev = arg;
395 struct msm_drm_private *priv = dev->dev_private;
396 struct msm_kms *kms = priv->kms;
397 BUG_ON(!kms);
398 return kms->funcs->irq(kms);
399}
400
401static void msm_irq_preinstall(struct drm_device *dev)
402{
403 struct msm_drm_private *priv = dev->dev_private;
404 struct msm_kms *kms = priv->kms;
405 BUG_ON(!kms);
406 kms->funcs->irq_preinstall(kms);
407}
408
409static int msm_irq_postinstall(struct drm_device *dev)
410{
411 struct msm_drm_private *priv = dev->dev_private;
412 struct msm_kms *kms = priv->kms;
413 BUG_ON(!kms);
414 return kms->funcs->irq_postinstall(kms);
415}
416
417static void msm_irq_uninstall(struct drm_device *dev)
418{
419 struct msm_drm_private *priv = dev->dev_private;
420 struct msm_kms *kms = priv->kms;
421 BUG_ON(!kms);
422 kms->funcs->irq_uninstall(kms);
423}
424
425static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
426{
427 struct msm_drm_private *priv = dev->dev_private;
428 struct msm_kms *kms = priv->kms;
429 if (!kms)
430 return -ENXIO;
431 DBG("dev=%p, crtc=%d", dev, crtc_id);
432 return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
433}
434
435static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
436{
437 struct msm_drm_private *priv = dev->dev_private;
438 struct msm_kms *kms = priv->kms;
439 if (!kms)
440 return;
441 DBG("dev=%p, crtc=%d", dev, crtc_id);
442 kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
443}
444
445/*
446 * DRM debugfs:
447 */
448
449#ifdef CONFIG_DEBUG_FS
450static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
451{
452 struct msm_drm_private *priv = dev->dev_private;
453 struct msm_gpu *gpu = priv->gpu;
454
455 if (gpu) {
456 seq_printf(m, "%s Status:\n", gpu->name);
457 gpu->funcs->show(gpu, m);
458 }
459
460 return 0;
461}
462
463static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
464{
465 struct msm_drm_private *priv = dev->dev_private;
466 struct msm_gpu *gpu = priv->gpu;
467
468 if (gpu) {
469 seq_printf(m, "Active Objects (%s):\n", gpu->name);
470 msm_gem_describe_objects(&gpu->active_list, m);
471 }
472
473 seq_printf(m, "Inactive Objects:\n");
474 msm_gem_describe_objects(&priv->inactive_list, m);
475
476 return 0;
477}
478
479static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
480{
481 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
482}
483
484static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
485{
486 struct msm_drm_private *priv = dev->dev_private;
487 struct drm_framebuffer *fb, *fbdev_fb = NULL;
488
489 if (priv->fbdev) {
490 seq_printf(m, "fbcon ");
491 fbdev_fb = priv->fbdev->fb;
492 msm_framebuffer_describe(fbdev_fb, m);
493 }
494
495 mutex_lock(&dev->mode_config.fb_lock);
496 list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
497 if (fb == fbdev_fb)
498 continue;
499
500 seq_printf(m, "user ");
501 msm_framebuffer_describe(fb, m);
502 }
503 mutex_unlock(&dev->mode_config.fb_lock);
504
505 return 0;
506}
507
508static int show_locked(struct seq_file *m, void *arg)
509{
510 struct drm_info_node *node = (struct drm_info_node *) m->private;
511 struct drm_device *dev = node->minor->dev;
512 int (*show)(struct drm_device *dev, struct seq_file *m) =
513 node->info_ent->data;
514 int ret;
515
516 ret = mutex_lock_interruptible(&dev->struct_mutex);
517 if (ret)
518 return ret;
519
520 ret = show(dev, m);
521
522 mutex_unlock(&dev->struct_mutex);
523
524 return ret;
525}
526
527static struct drm_info_list msm_debugfs_list[] = {
528 {"gpu", show_locked, 0, msm_gpu_show},
529 {"gem", show_locked, 0, msm_gem_show},
530 { "mm", show_locked, 0, msm_mm_show },
531 { "fb", show_locked, 0, msm_fb_show },
532};
533
534static int msm_debugfs_init(struct drm_minor *minor)
535{
536 struct drm_device *dev = minor->dev;
537 int ret;
538
539 ret = drm_debugfs_create_files(msm_debugfs_list,
540 ARRAY_SIZE(msm_debugfs_list),
541 minor->debugfs_root, minor);
542
543 if (ret) {
544 dev_err(dev->dev, "could not install msm_debugfs_list\n");
545 return ret;
546 }
547
548 return ret;
549}
550
551static void msm_debugfs_cleanup(struct drm_minor *minor)
552{
553 drm_debugfs_remove_files(msm_debugfs_list,
554 ARRAY_SIZE(msm_debugfs_list), minor);
555}
556#endif
557
558/*
559 * Fences:
560 */
561
562int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
563 struct timespec *timeout)
564{
565 struct msm_drm_private *priv = dev->dev_private;
566 int ret;
567
568 if (!priv->gpu)
569 return 0;
570
571 if (fence > priv->gpu->submitted_fence) {
572 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
573 fence, priv->gpu->submitted_fence);
574 return -EINVAL;
575 }
576
577 if (!timeout) {
578 /* no-wait: */
579 ret = fence_completed(dev, fence) ? 0 : -EBUSY;
580 } else {
581 unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
582 unsigned long start_jiffies = jiffies;
583 unsigned long remaining_jiffies;
584
585 if (time_after(start_jiffies, timeout_jiffies))
586 remaining_jiffies = 0;
587 else
588 remaining_jiffies = timeout_jiffies - start_jiffies;
589
590 ret = wait_event_interruptible_timeout(priv->fence_event,
591 fence_completed(dev, fence),
592 remaining_jiffies);
593
594 if (ret == 0) {
595 DBG("timeout waiting for fence: %u (completed: %u)",
596 fence, priv->completed_fence);
597 ret = -ETIMEDOUT;
598 } else if (ret != -ERESTARTSYS) {
599 ret = 0;
600 }
601 }
602
603 return ret;
604}
605
606/* called from workqueue */
607void msm_update_fence(struct drm_device *dev, uint32_t fence)
608{
609 struct msm_drm_private *priv = dev->dev_private;
610
611 mutex_lock(&dev->struct_mutex);
612 priv->completed_fence = max(fence, priv->completed_fence);
613
614 while (!list_empty(&priv->fence_cbs)) {
615 struct msm_fence_cb *cb;
616
617 cb = list_first_entry(&priv->fence_cbs,
618 struct msm_fence_cb, work.entry);
619
620 if (cb->fence > priv->completed_fence)
621 break;
622
623 list_del_init(&cb->work.entry);
624 queue_work(priv->wq, &cb->work);
625 }
626
627 mutex_unlock(&dev->struct_mutex);
628
629 wake_up_all(&priv->fence_event);
630}
631
632void __msm_fence_worker(struct work_struct *work)
633{
634 struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
635 cb->func(cb);
636}
637
638/*
639 * DRM ioctls:
640 */
641
642static int msm_ioctl_get_param(struct drm_device *dev, void *data,
643 struct drm_file *file)
644{
645 struct msm_drm_private *priv = dev->dev_private;
646 struct drm_msm_param *args = data;
647 struct msm_gpu *gpu;
648
649 /* for now, we just have 3d pipe.. eventually this would need to
650 * be more clever to dispatch to appropriate gpu module:
651 */
652 if (args->pipe != MSM_PIPE_3D0)
653 return -EINVAL;
654
655 gpu = priv->gpu;
656
657 if (!gpu)
658 return -ENXIO;
659
660 return gpu->funcs->get_param(gpu, args->param, &args->value);
661}
662
663static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
664 struct drm_file *file)
665{
666 struct drm_msm_gem_new *args = data;
667
668 if (args->flags & ~MSM_BO_FLAGS) {
669 DRM_ERROR("invalid flags: %08x\n", args->flags);
670 return -EINVAL;
671 }
672
673 return msm_gem_new_handle(dev, file, args->size,
674 args->flags, &args->handle);
675}
676
677#define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
678
679static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
680 struct drm_file *file)
681{
682 struct drm_msm_gem_cpu_prep *args = data;
683 struct drm_gem_object *obj;
684 int ret;
685
686 if (args->op & ~MSM_PREP_FLAGS) {
687 DRM_ERROR("invalid op: %08x\n", args->op);
688 return -EINVAL;
689 }
690
691 obj = drm_gem_object_lookup(dev, file, args->handle);
692 if (!obj)
693 return -ENOENT;
694
695 ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
696
697 drm_gem_object_unreference_unlocked(obj);
698
699 return ret;
700}
701
702static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
703 struct drm_file *file)
704{
705 struct drm_msm_gem_cpu_fini *args = data;
706 struct drm_gem_object *obj;
707 int ret;
708
709 obj = drm_gem_object_lookup(dev, file, args->handle);
710 if (!obj)
711 return -ENOENT;
712
713 ret = msm_gem_cpu_fini(obj);
714
715 drm_gem_object_unreference_unlocked(obj);
716
717 return ret;
718}
719
720static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
721 struct drm_file *file)
722{
723 struct drm_msm_gem_info *args = data;
724 struct drm_gem_object *obj;
725 int ret = 0;
726
727 if (args->pad)
728 return -EINVAL;
729
730 obj = drm_gem_object_lookup(dev, file, args->handle);
731 if (!obj)
732 return -ENOENT;
733
734 args->offset = msm_gem_mmap_offset(obj);
735
736 drm_gem_object_unreference_unlocked(obj);
737
738 return ret;
739}
740
741static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
742 struct drm_file *file)
743{
744 struct drm_msm_wait_fence *args = data;
745
746 if (args->pad) {
747 DRM_ERROR("invalid pad: %08x\n", args->pad);
748 return -EINVAL;
749 }
750
751 return msm_wait_fence_interruptable(dev, args->fence,
752 &TS(args->timeout));
753}
754
755static const struct drm_ioctl_desc msm_ioctls[] = {
756 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
757 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
758 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
759 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
760 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
761 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
762 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
763};
764
765static const struct vm_operations_struct vm_ops = {
766 .fault = msm_gem_fault,
767 .open = drm_gem_vm_open,
768 .close = drm_gem_vm_close,
769};
770
771static const struct file_operations fops = {
772 .owner = THIS_MODULE,
773 .open = drm_open,
774 .release = drm_release,
775 .unlocked_ioctl = drm_ioctl,
776#ifdef CONFIG_COMPAT
777 .compat_ioctl = drm_compat_ioctl,
778#endif
779 .poll = drm_poll,
780 .read = drm_read,
781 .llseek = no_llseek,
782 .mmap = msm_gem_mmap,
783};
784
785static struct drm_driver msm_driver = {
786 .driver_features = DRIVER_HAVE_IRQ |
787 DRIVER_GEM |
788 DRIVER_PRIME |
789 DRIVER_RENDER |
790 DRIVER_MODESET,
791 .load = msm_load,
792 .unload = msm_unload,
793 .open = msm_open,
794 .preclose = msm_preclose,
795 .lastclose = msm_lastclose,
796 .irq_handler = msm_irq,
797 .irq_preinstall = msm_irq_preinstall,
798 .irq_postinstall = msm_irq_postinstall,
799 .irq_uninstall = msm_irq_uninstall,
800 .get_vblank_counter = drm_vblank_count,
801 .enable_vblank = msm_enable_vblank,
802 .disable_vblank = msm_disable_vblank,
803 .gem_free_object = msm_gem_free_object,
804 .gem_vm_ops = &vm_ops,
805 .dumb_create = msm_gem_dumb_create,
806 .dumb_map_offset = msm_gem_dumb_map_offset,
807 .dumb_destroy = drm_gem_dumb_destroy,
808 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
809 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
810 .gem_prime_export = drm_gem_prime_export,
811 .gem_prime_import = drm_gem_prime_import,
812 .gem_prime_pin = msm_gem_prime_pin,
813 .gem_prime_unpin = msm_gem_prime_unpin,
814 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
815 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
816 .gem_prime_vmap = msm_gem_prime_vmap,
817 .gem_prime_vunmap = msm_gem_prime_vunmap,
818#ifdef CONFIG_DEBUG_FS
819 .debugfs_init = msm_debugfs_init,
820 .debugfs_cleanup = msm_debugfs_cleanup,
821#endif
822 .ioctls = msm_ioctls,
823 .num_ioctls = DRM_MSM_NUM_IOCTLS,
824 .fops = &fops,
825 .name = "msm",
826 .desc = "MSM Snapdragon DRM",
827 .date = "20130625",
828 .major = 1,
829 .minor = 0,
830};
831
832#ifdef CONFIG_PM_SLEEP
833static int msm_pm_suspend(struct device *dev)
834{
835 struct drm_device *ddev = dev_get_drvdata(dev);
836
837 drm_kms_helper_poll_disable(ddev);
838
839 return 0;
840}
841
842static int msm_pm_resume(struct device *dev)
843{
844 struct drm_device *ddev = dev_get_drvdata(dev);
845
846 drm_kms_helper_poll_enable(ddev);
847
848 return 0;
849}
850#endif
851
852static const struct dev_pm_ops msm_pm_ops = {
853 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
854};
855
856/*
857 * Componentized driver support:
858 */
859
860#ifdef CONFIG_OF
861/* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx
862 * (or probably any other).. so probably some room for some helpers
863 */
864static int compare_of(struct device *dev, void *data)
865{
866 return dev->of_node == data;
867}
868
869static int msm_drm_add_components(struct device *master, struct master *m)
870{
871 struct device_node *np = master->of_node;
872 unsigned i;
873 int ret;
874
875 for (i = 0; ; i++) {
876 struct device_node *node;
877
878 node = of_parse_phandle(np, "connectors", i);
879 if (!node)
880 break;
881
882 ret = component_master_add_child(m, compare_of, node);
883 of_node_put(node);
884
885 if (ret)
886 return ret;
887 }
888 return 0;
889}
890#else
891static int compare_dev(struct device *dev, void *data)
892{
893 return dev == data;
894}
895
896static int msm_drm_add_components(struct device *master, struct master *m)
897{
898 /* For non-DT case, it kinda sucks. We don't actually have a way
899 * to know whether or not we are waiting for certain devices (or if
900 * they are simply not present). But for non-DT we only need to
901 * care about apq8064/apq8060/etc (all mdp4/a3xx):
902 */
903 static const char *devnames[] = {
904 "hdmi_msm.0", "kgsl-3d0.0",
905 };
906 int i;
907
908 DBG("Adding components..");
909
910 for (i = 0; i < ARRAY_SIZE(devnames); i++) {
911 struct device *dev;
912 int ret;
913
914 dev = bus_find_device_by_name(&platform_bus_type,
915 NULL, devnames[i]);
916 if (!dev) {
917 dev_info(master, "still waiting for %s\n", devnames[i]);
918 return -EPROBE_DEFER;
919 }
920
921 ret = component_master_add_child(m, compare_dev, dev);
922 if (ret) {
923 DBG("could not add child: %d", ret);
924 return ret;
925 }
926 }
927
928 return 0;
929}
930#endif
931
932static int msm_drm_bind(struct device *dev)
933{
934 return drm_platform_init(&msm_driver, to_platform_device(dev));
935}
936
937static void msm_drm_unbind(struct device *dev)
938{
939 drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
940}
941
942static const struct component_master_ops msm_drm_ops = {
943 .add_components = msm_drm_add_components,
944 .bind = msm_drm_bind,
945 .unbind = msm_drm_unbind,
946};
947
948/*
949 * Platform driver:
950 */
951
952static int msm_pdev_probe(struct platform_device *pdev)
953{
954 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
955 return component_master_add(&pdev->dev, &msm_drm_ops);
956}
957
958static int msm_pdev_remove(struct platform_device *pdev)
959{
960 component_master_del(&pdev->dev, &msm_drm_ops);
961
962 return 0;
963}
964
965static const struct platform_device_id msm_id[] = {
966 { "mdp", 0 },
967 { }
968};
969
970static const struct of_device_id dt_match[] = {
971 { .compatible = "qcom,mdss_mdp" },
972 {}
973};
974MODULE_DEVICE_TABLE(of, dt_match);
975
976static struct platform_driver msm_platform_driver = {
977 .probe = msm_pdev_probe,
978 .remove = msm_pdev_remove,
979 .driver = {
980 .owner = THIS_MODULE,
981 .name = "msm",
982 .of_match_table = dt_match,
983 .pm = &msm_pm_ops,
984 },
985 .id_table = msm_id,
986};
987
988static int __init msm_drm_register(void)
989{
990 DBG("init");
991 hdmi_register();
992 a3xx_register();
993 return platform_driver_register(&msm_platform_driver);
994}
995
996static void __exit msm_drm_unregister(void)
997{
998 DBG("fini");
999 platform_driver_unregister(&msm_platform_driver);
1000 hdmi_unregister();
1001 a3xx_unregister();
1002}
1003
1004module_init(msm_drm_register);
1005module_exit(msm_drm_unregister);
1006
1007MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1008MODULE_DESCRIPTION("MSM DRM Driver");
1009MODULE_LICENSE("GPL");