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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Enable PCIe link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/jiffies.h>
20#include <linux/delay.h>
21#include "../pci.h"
22
23#ifdef MODULE_PARAM_PREFIX
24#undef MODULE_PARAM_PREFIX
25#endif
26#define MODULE_PARAM_PREFIX "pcie_aspm."
27
28/* Note: those are not register definitions */
29#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
31#define ASPM_STATE_L1 (4) /* L1 state */
32#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
36#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
37#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
38#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
39 ASPM_STATE_L1_2_MASK)
40#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
41#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
42 ASPM_STATE_L1SS)
43
44struct aspm_latency {
45 u32 l0s; /* L0s latency (nsec) */
46 u32 l1; /* L1 latency (nsec) */
47};
48
49struct pcie_link_state {
50 struct pci_dev *pdev; /* Upstream component of the Link */
51 struct pci_dev *downstream; /* Downstream component, function 0 */
52 struct pcie_link_state *root; /* pointer to the root port link */
53 struct pcie_link_state *parent; /* pointer to the parent Link state */
54 struct list_head sibling; /* node in link_list */
55
56 /* ASPM state */
57 u32 aspm_support:7; /* Supported ASPM state */
58 u32 aspm_enabled:7; /* Enabled ASPM state */
59 u32 aspm_capable:7; /* Capable ASPM state with latency */
60 u32 aspm_default:7; /* Default ASPM state by BIOS */
61 u32 aspm_disable:7; /* Disabled ASPM state */
62
63 /* Clock PM state */
64 u32 clkpm_capable:1; /* Clock PM capable? */
65 u32 clkpm_enabled:1; /* Current Clock PM state */
66 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
67
68 /* Exit latencies */
69 struct aspm_latency latency_up; /* Upstream direction exit latency */
70 struct aspm_latency latency_dw; /* Downstream direction exit latency */
71 /*
72 * Endpoint acceptable latencies. A pcie downstream port only
73 * has one slot under it, so at most there are 8 functions.
74 */
75 struct aspm_latency acceptable[8];
76
77 /* L1 PM Substate info */
78 struct {
79 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
80 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
81 u32 ctl1; /* value to be programmed in ctl1 */
82 u32 ctl2; /* value to be programmed in ctl2 */
83 } l1ss;
84};
85
86static int aspm_disabled, aspm_force;
87static bool aspm_support_enabled = true;
88static DEFINE_MUTEX(aspm_lock);
89static LIST_HEAD(link_list);
90
91#define POLICY_DEFAULT 0 /* BIOS default setting */
92#define POLICY_PERFORMANCE 1 /* high performance */
93#define POLICY_POWERSAVE 2 /* high power saving */
94#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
95
96#ifdef CONFIG_PCIEASPM_PERFORMANCE
97static int aspm_policy = POLICY_PERFORMANCE;
98#elif defined CONFIG_PCIEASPM_POWERSAVE
99static int aspm_policy = POLICY_POWERSAVE;
100#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
101static int aspm_policy = POLICY_POWER_SUPERSAVE;
102#else
103static int aspm_policy;
104#endif
105
106static const char *policy_str[] = {
107 [POLICY_DEFAULT] = "default",
108 [POLICY_PERFORMANCE] = "performance",
109 [POLICY_POWERSAVE] = "powersave",
110 [POLICY_POWER_SUPERSAVE] = "powersupersave"
111};
112
113#define LINK_RETRAIN_TIMEOUT HZ
114
115static int policy_to_aspm_state(struct pcie_link_state *link)
116{
117 switch (aspm_policy) {
118 case POLICY_PERFORMANCE:
119 /* Disable ASPM and Clock PM */
120 return 0;
121 case POLICY_POWERSAVE:
122 /* Enable ASPM L0s/L1 */
123 return (ASPM_STATE_L0S | ASPM_STATE_L1);
124 case POLICY_POWER_SUPERSAVE:
125 /* Enable Everything */
126 return ASPM_STATE_ALL;
127 case POLICY_DEFAULT:
128 return link->aspm_default;
129 }
130 return 0;
131}
132
133static int policy_to_clkpm_state(struct pcie_link_state *link)
134{
135 switch (aspm_policy) {
136 case POLICY_PERFORMANCE:
137 /* Disable ASPM and Clock PM */
138 return 0;
139 case POLICY_POWERSAVE:
140 case POLICY_POWER_SUPERSAVE:
141 /* Enable Clock PM */
142 return 1;
143 case POLICY_DEFAULT:
144 return link->clkpm_default;
145 }
146 return 0;
147}
148
149static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
150{
151 struct pci_dev *child;
152 struct pci_bus *linkbus = link->pdev->subordinate;
153 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
154
155 list_for_each_entry(child, &linkbus->devices, bus_list)
156 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
157 PCI_EXP_LNKCTL_CLKREQ_EN,
158 val);
159 link->clkpm_enabled = !!enable;
160}
161
162static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
163{
164 /* Don't enable Clock PM if the link is not Clock PM capable */
165 if (!link->clkpm_capable)
166 enable = 0;
167 /* Need nothing if the specified equals to current state */
168 if (link->clkpm_enabled == enable)
169 return;
170 pcie_set_clkpm_nocheck(link, enable);
171}
172
173static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
174{
175 int capable = 1, enabled = 1;
176 u32 reg32;
177 u16 reg16;
178 struct pci_dev *child;
179 struct pci_bus *linkbus = link->pdev->subordinate;
180
181 /* All functions should have the same cap and state, take the worst */
182 list_for_each_entry(child, &linkbus->devices, bus_list) {
183 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
184 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
185 capable = 0;
186 enabled = 0;
187 break;
188 }
189 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
190 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
191 enabled = 0;
192 }
193 link->clkpm_enabled = enabled;
194 link->clkpm_default = enabled;
195 link->clkpm_capable = (blacklist) ? 0 : capable;
196}
197
198static bool pcie_retrain_link(struct pcie_link_state *link)
199{
200 struct pci_dev *parent = link->pdev;
201 unsigned long end_jiffies;
202 u16 reg16;
203
204 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
205 reg16 |= PCI_EXP_LNKCTL_RL;
206 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
207 if (parent->clear_retrain_link) {
208 /*
209 * Due to an erratum in some devices the Retrain Link bit
210 * needs to be cleared again manually to allow the link
211 * training to succeed.
212 */
213 reg16 &= ~PCI_EXP_LNKCTL_RL;
214 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
215 }
216
217 /* Wait for link training end. Break out after waiting for timeout */
218 end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
219 do {
220 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
221 if (!(reg16 & PCI_EXP_LNKSTA_LT))
222 break;
223 msleep(1);
224 } while (time_before(jiffies, end_jiffies));
225 return !(reg16 & PCI_EXP_LNKSTA_LT);
226}
227
228/*
229 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
230 * could use common clock. If they are, configure them to use the
231 * common clock. That will reduce the ASPM state exit latency.
232 */
233static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
234{
235 int same_clock = 1;
236 u16 reg16, parent_reg, child_reg[8];
237 struct pci_dev *child, *parent = link->pdev;
238 struct pci_bus *linkbus = parent->subordinate;
239 /*
240 * All functions of a slot should have the same Slot Clock
241 * Configuration, so just check one function
242 */
243 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
244 BUG_ON(!pci_is_pcie(child));
245
246 /* Check downstream component if bit Slot Clock Configuration is 1 */
247 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
248 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
249 same_clock = 0;
250
251 /* Check upstream component if bit Slot Clock Configuration is 1 */
252 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
253 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
254 same_clock = 0;
255
256 /* Port might be already in common clock mode */
257 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
258 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
259 bool consistent = true;
260
261 list_for_each_entry(child, &linkbus->devices, bus_list) {
262 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
263 ®16);
264 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
265 consistent = false;
266 break;
267 }
268 }
269 if (consistent)
270 return;
271 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
272 }
273
274 /* Configure downstream component, all functions */
275 list_for_each_entry(child, &linkbus->devices, bus_list) {
276 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
277 child_reg[PCI_FUNC(child->devfn)] = reg16;
278 if (same_clock)
279 reg16 |= PCI_EXP_LNKCTL_CCC;
280 else
281 reg16 &= ~PCI_EXP_LNKCTL_CCC;
282 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
283 }
284
285 /* Configure upstream component */
286 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
287 parent_reg = reg16;
288 if (same_clock)
289 reg16 |= PCI_EXP_LNKCTL_CCC;
290 else
291 reg16 &= ~PCI_EXP_LNKCTL_CCC;
292 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
293
294 if (pcie_retrain_link(link))
295 return;
296
297 /* Training failed. Restore common clock configurations */
298 pci_err(parent, "ASPM: Could not configure common clock\n");
299 list_for_each_entry(child, &linkbus->devices, bus_list)
300 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
301 child_reg[PCI_FUNC(child->devfn)]);
302 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
303}
304
305/* Convert L0s latency encoding to ns */
306static u32 calc_l0s_latency(u32 encoding)
307{
308 if (encoding == 0x7)
309 return (5 * 1000); /* > 4us */
310 return (64 << encoding);
311}
312
313/* Convert L0s acceptable latency encoding to ns */
314static u32 calc_l0s_acceptable(u32 encoding)
315{
316 if (encoding == 0x7)
317 return -1U;
318 return (64 << encoding);
319}
320
321/* Convert L1 latency encoding to ns */
322static u32 calc_l1_latency(u32 encoding)
323{
324 if (encoding == 0x7)
325 return (65 * 1000); /* > 64us */
326 return (1000 << encoding);
327}
328
329/* Convert L1 acceptable latency encoding to ns */
330static u32 calc_l1_acceptable(u32 encoding)
331{
332 if (encoding == 0x7)
333 return -1U;
334 return (1000 << encoding);
335}
336
337/* Convert L1SS T_pwr encoding to usec */
338static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
339{
340 switch (scale) {
341 case 0:
342 return val * 2;
343 case 1:
344 return val * 10;
345 case 2:
346 return val * 100;
347 }
348 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
349 return 0;
350}
351
352static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
353{
354 u32 threshold_ns = threshold_us * 1000;
355
356 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
357 if (threshold_ns < 32) {
358 *scale = 0;
359 *value = threshold_ns;
360 } else if (threshold_ns < 1024) {
361 *scale = 1;
362 *value = threshold_ns >> 5;
363 } else if (threshold_ns < 32768) {
364 *scale = 2;
365 *value = threshold_ns >> 10;
366 } else if (threshold_ns < 1048576) {
367 *scale = 3;
368 *value = threshold_ns >> 15;
369 } else if (threshold_ns < 33554432) {
370 *scale = 4;
371 *value = threshold_ns >> 20;
372 } else {
373 *scale = 5;
374 *value = threshold_ns >> 25;
375 }
376}
377
378struct aspm_register_info {
379 u32 support:2;
380 u32 enabled:2;
381 u32 latency_encoding_l0s;
382 u32 latency_encoding_l1;
383
384 /* L1 substates */
385 u32 l1ss_cap_ptr;
386 u32 l1ss_cap;
387 u32 l1ss_ctl1;
388 u32 l1ss_ctl2;
389};
390
391static void pcie_get_aspm_reg(struct pci_dev *pdev,
392 struct aspm_register_info *info)
393{
394 u16 reg16;
395 u32 reg32;
396
397 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
398 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
399 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
400 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
401 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
402 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
403
404 /* Read L1 PM substate capabilities */
405 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
406 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
407 if (!info->l1ss_cap_ptr)
408 return;
409 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
410 &info->l1ss_cap);
411 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
412 info->l1ss_cap = 0;
413 return;
414 }
415
416 /*
417 * If we don't have LTR for the entire path from the Root Complex
418 * to this device, we can't use ASPM L1.2 because it relies on the
419 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
420 */
421 if (!pdev->ltr_path)
422 info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
423
424 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
425 &info->l1ss_ctl1);
426 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
427 &info->l1ss_ctl2);
428}
429
430static void pcie_aspm_check_latency(struct pci_dev *endpoint)
431{
432 u32 latency, l1_switch_latency = 0;
433 struct aspm_latency *acceptable;
434 struct pcie_link_state *link;
435
436 /* Device not in D0 doesn't need latency check */
437 if ((endpoint->current_state != PCI_D0) &&
438 (endpoint->current_state != PCI_UNKNOWN))
439 return;
440
441 link = endpoint->bus->self->link_state;
442 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
443
444 while (link) {
445 /* Check upstream direction L0s latency */
446 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
447 (link->latency_up.l0s > acceptable->l0s))
448 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
449
450 /* Check downstream direction L0s latency */
451 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
452 (link->latency_dw.l0s > acceptable->l0s))
453 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
454 /*
455 * Check L1 latency.
456 * Every switch on the path to root complex need 1
457 * more microsecond for L1. Spec doesn't mention L0s.
458 *
459 * The exit latencies for L1 substates are not advertised
460 * by a device. Since the spec also doesn't mention a way
461 * to determine max latencies introduced by enabling L1
462 * substates on the components, it is not clear how to do
463 * a L1 substate exit latency check. We assume that the
464 * L1 exit latencies advertised by a device include L1
465 * substate latencies (and hence do not do any check).
466 */
467 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
468 if ((link->aspm_capable & ASPM_STATE_L1) &&
469 (latency + l1_switch_latency > acceptable->l1))
470 link->aspm_capable &= ~ASPM_STATE_L1;
471 l1_switch_latency += 1000;
472
473 link = link->parent;
474 }
475}
476
477/*
478 * The L1 PM substate capability is only implemented in function 0 in a
479 * multi function device.
480 */
481static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
482{
483 struct pci_dev *child;
484
485 list_for_each_entry(child, &linkbus->devices, bus_list)
486 if (PCI_FUNC(child->devfn) == 0)
487 return child;
488 return NULL;
489}
490
491/* Calculate L1.2 PM substate timing parameters */
492static void aspm_calc_l1ss_info(struct pcie_link_state *link,
493 struct aspm_register_info *upreg,
494 struct aspm_register_info *dwreg)
495{
496 u32 val1, val2, scale1, scale2;
497 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
498
499 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
500 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
501 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
502
503 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
504 return;
505
506 /* Choose the greater of the two Port Common_Mode_Restore_Times */
507 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
508 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
509 t_common_mode = max(val1, val2);
510
511 /* Choose the greater of the two Port T_POWER_ON times */
512 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
513 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
514 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
515 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
516
517 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
518 calc_l1ss_pwron(link->downstream, scale2, val2)) {
519 link->l1ss.ctl2 |= scale1 | (val1 << 3);
520 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
521 } else {
522 link->l1ss.ctl2 |= scale2 | (val2 << 3);
523 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
524 }
525
526 /*
527 * Set LTR_L1.2_THRESHOLD to the time required to transition the
528 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
529 * downstream devices report (via LTR) that they can tolerate at
530 * least that much latency.
531 *
532 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
533 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
534 * least 4us.
535 */
536 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
537 encode_l12_threshold(l1_2_threshold, &scale, &value);
538 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
539}
540
541static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
542{
543 struct pci_dev *child = link->downstream, *parent = link->pdev;
544 struct pci_bus *linkbus = parent->subordinate;
545 struct aspm_register_info upreg, dwreg;
546
547 if (blacklist) {
548 /* Set enabled/disable so that we will disable ASPM later */
549 link->aspm_enabled = ASPM_STATE_ALL;
550 link->aspm_disable = ASPM_STATE_ALL;
551 return;
552 }
553
554 /* Get upstream/downstream components' register state */
555 pcie_get_aspm_reg(parent, &upreg);
556 pcie_get_aspm_reg(child, &dwreg);
557
558 /*
559 * If ASPM not supported, don't mess with the clocks and link,
560 * bail out now.
561 */
562 if (!(upreg.support & dwreg.support))
563 return;
564
565 /* Configure common clock before checking latencies */
566 pcie_aspm_configure_common_clock(link);
567
568 /*
569 * Re-read upstream/downstream components' register state
570 * after clock configuration
571 */
572 pcie_get_aspm_reg(parent, &upreg);
573 pcie_get_aspm_reg(child, &dwreg);
574
575 /*
576 * Setup L0s state
577 *
578 * Note that we must not enable L0s in either direction on a
579 * given link unless components on both sides of the link each
580 * support L0s.
581 */
582 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
583 link->aspm_support |= ASPM_STATE_L0S;
584 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
585 link->aspm_enabled |= ASPM_STATE_L0S_UP;
586 if (upreg.enabled & PCIE_LINK_STATE_L0S)
587 link->aspm_enabled |= ASPM_STATE_L0S_DW;
588 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
589 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
590
591 /* Setup L1 state */
592 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
593 link->aspm_support |= ASPM_STATE_L1;
594 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
595 link->aspm_enabled |= ASPM_STATE_L1;
596 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
597 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
598
599 /* Setup L1 substate */
600 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
601 link->aspm_support |= ASPM_STATE_L1_1;
602 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
603 link->aspm_support |= ASPM_STATE_L1_2;
604 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
605 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
606 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
607 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
608
609 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
610 link->aspm_enabled |= ASPM_STATE_L1_1;
611 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
612 link->aspm_enabled |= ASPM_STATE_L1_2;
613 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
614 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
615 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
616 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
617
618 if (link->aspm_support & ASPM_STATE_L1SS)
619 aspm_calc_l1ss_info(link, &upreg, &dwreg);
620
621 /* Save default state */
622 link->aspm_default = link->aspm_enabled;
623
624 /* Setup initial capable state. Will be updated later */
625 link->aspm_capable = link->aspm_support;
626 /*
627 * If the downstream component has pci bridge function, don't
628 * do ASPM for now.
629 */
630 list_for_each_entry(child, &linkbus->devices, bus_list) {
631 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
632 link->aspm_disable = ASPM_STATE_ALL;
633 break;
634 }
635 }
636
637 /* Get and check endpoint acceptable latencies */
638 list_for_each_entry(child, &linkbus->devices, bus_list) {
639 u32 reg32, encoding;
640 struct aspm_latency *acceptable =
641 &link->acceptable[PCI_FUNC(child->devfn)];
642
643 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
644 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
645 continue;
646
647 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
648 /* Calculate endpoint L0s acceptable latency */
649 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
650 acceptable->l0s = calc_l0s_acceptable(encoding);
651 /* Calculate endpoint L1 acceptable latency */
652 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
653 acceptable->l1 = calc_l1_acceptable(encoding);
654
655 pcie_aspm_check_latency(child);
656 }
657}
658
659static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
660 u32 clear, u32 set)
661{
662 u32 val;
663
664 pci_read_config_dword(pdev, pos, &val);
665 val &= ~clear;
666 val |= set;
667 pci_write_config_dword(pdev, pos, val);
668}
669
670/* Configure the ASPM L1 substates */
671static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
672{
673 u32 val, enable_req;
674 struct pci_dev *child = link->downstream, *parent = link->pdev;
675 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
676 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
677
678 enable_req = (link->aspm_enabled ^ state) & state;
679
680 /*
681 * Here are the rules specified in the PCIe spec for enabling L1SS:
682 * - When enabling L1.x, enable bit at parent first, then at child
683 * - When disabling L1.x, disable bit at child first, then at parent
684 * - When enabling ASPM L1.x, need to disable L1
685 * (at child followed by parent).
686 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
687 * parameters
688 *
689 * To keep it simple, disable all L1SS bits first, and later enable
690 * what is needed.
691 */
692
693 /* Disable all L1 substates */
694 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
695 PCI_L1SS_CTL1_L1SS_MASK, 0);
696 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
697 PCI_L1SS_CTL1_L1SS_MASK, 0);
698 /*
699 * If needed, disable L1, and it gets enabled later
700 * in pcie_config_aspm_link().
701 */
702 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
703 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
704 PCI_EXP_LNKCTL_ASPM_L1, 0);
705 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
706 PCI_EXP_LNKCTL_ASPM_L1, 0);
707 }
708
709 if (enable_req & ASPM_STATE_L1_2_MASK) {
710
711 /* Program T_POWER_ON times in both ports */
712 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
713 link->l1ss.ctl2);
714 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
715 link->l1ss.ctl2);
716
717 /* Program Common_Mode_Restore_Time in upstream device */
718 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
719 PCI_L1SS_CTL1_CM_RESTORE_TIME,
720 link->l1ss.ctl1);
721
722 /* Program LTR_L1.2_THRESHOLD time in both ports */
723 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
724 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
725 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
726 link->l1ss.ctl1);
727 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
728 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
729 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
730 link->l1ss.ctl1);
731 }
732
733 val = 0;
734 if (state & ASPM_STATE_L1_1)
735 val |= PCI_L1SS_CTL1_ASPM_L1_1;
736 if (state & ASPM_STATE_L1_2)
737 val |= PCI_L1SS_CTL1_ASPM_L1_2;
738 if (state & ASPM_STATE_L1_1_PCIPM)
739 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
740 if (state & ASPM_STATE_L1_2_PCIPM)
741 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
742
743 /* Enable what we need to enable */
744 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
745 PCI_L1SS_CAP_L1_PM_SS, val);
746 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
747 PCI_L1SS_CAP_L1_PM_SS, val);
748}
749
750static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
751{
752 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
753 PCI_EXP_LNKCTL_ASPMC, val);
754}
755
756static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
757{
758 u32 upstream = 0, dwstream = 0;
759 struct pci_dev *child = link->downstream, *parent = link->pdev;
760 struct pci_bus *linkbus = parent->subordinate;
761
762 /* Enable only the states that were not explicitly disabled */
763 state &= (link->aspm_capable & ~link->aspm_disable);
764
765 /* Can't enable any substates if L1 is not enabled */
766 if (!(state & ASPM_STATE_L1))
767 state &= ~ASPM_STATE_L1SS;
768
769 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
770 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
771 state &= ~ASPM_STATE_L1_SS_PCIPM;
772 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
773 }
774
775 /* Nothing to do if the link is already in the requested state */
776 if (link->aspm_enabled == state)
777 return;
778 /* Convert ASPM state to upstream/downstream ASPM register state */
779 if (state & ASPM_STATE_L0S_UP)
780 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
781 if (state & ASPM_STATE_L0S_DW)
782 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
783 if (state & ASPM_STATE_L1) {
784 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
785 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
786 }
787
788 if (link->aspm_capable & ASPM_STATE_L1SS)
789 pcie_config_aspm_l1ss(link, state);
790
791 /*
792 * Spec 2.0 suggests all functions should be configured the
793 * same setting for ASPM. Enabling ASPM L1 should be done in
794 * upstream component first and then downstream, and vice
795 * versa for disabling ASPM L1. Spec doesn't mention L0S.
796 */
797 if (state & ASPM_STATE_L1)
798 pcie_config_aspm_dev(parent, upstream);
799 list_for_each_entry(child, &linkbus->devices, bus_list)
800 pcie_config_aspm_dev(child, dwstream);
801 if (!(state & ASPM_STATE_L1))
802 pcie_config_aspm_dev(parent, upstream);
803
804 link->aspm_enabled = state;
805}
806
807static void pcie_config_aspm_path(struct pcie_link_state *link)
808{
809 while (link) {
810 pcie_config_aspm_link(link, policy_to_aspm_state(link));
811 link = link->parent;
812 }
813}
814
815static void free_link_state(struct pcie_link_state *link)
816{
817 link->pdev->link_state = NULL;
818 kfree(link);
819}
820
821static int pcie_aspm_sanity_check(struct pci_dev *pdev)
822{
823 struct pci_dev *child;
824 u32 reg32;
825
826 /*
827 * Some functions in a slot might not all be PCIe functions,
828 * very strange. Disable ASPM for the whole slot
829 */
830 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
831 if (!pci_is_pcie(child))
832 return -EINVAL;
833
834 /*
835 * If ASPM is disabled then we're not going to change
836 * the BIOS state. It's safe to continue even if it's a
837 * pre-1.1 device
838 */
839
840 if (aspm_disabled)
841 continue;
842
843 /*
844 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
845 * RBER bit to determine if a function is 1.1 version device
846 */
847 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
848 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
849 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
850 return -EINVAL;
851 }
852 }
853 return 0;
854}
855
856static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
857{
858 struct pcie_link_state *link;
859
860 link = kzalloc(sizeof(*link), GFP_KERNEL);
861 if (!link)
862 return NULL;
863
864 INIT_LIST_HEAD(&link->sibling);
865 link->pdev = pdev;
866 link->downstream = pci_function_0(pdev->subordinate);
867
868 /*
869 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
870 * hierarchies. Note that some PCIe host implementations omit
871 * the root ports entirely, in which case a downstream port on
872 * a switch may become the root of the link state chain for all
873 * its subordinate endpoints.
874 */
875 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
876 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
877 !pdev->bus->parent->self) {
878 link->root = link;
879 } else {
880 struct pcie_link_state *parent;
881
882 parent = pdev->bus->parent->self->link_state;
883 if (!parent) {
884 kfree(link);
885 return NULL;
886 }
887
888 link->parent = parent;
889 link->root = link->parent->root;
890 }
891
892 list_add(&link->sibling, &link_list);
893 pdev->link_state = link;
894 return link;
895}
896
897/*
898 * pcie_aspm_init_link_state: Initiate PCI express link state.
899 * It is called after the pcie and its children devices are scanned.
900 * @pdev: the root port or switch downstream port
901 */
902void pcie_aspm_init_link_state(struct pci_dev *pdev)
903{
904 struct pcie_link_state *link;
905 int blacklist = !!pcie_aspm_sanity_check(pdev);
906
907 if (!aspm_support_enabled)
908 return;
909
910 if (pdev->link_state)
911 return;
912
913 /*
914 * We allocate pcie_link_state for the component on the upstream
915 * end of a Link, so there's nothing to do unless this device is
916 * downstream port.
917 */
918 if (!pcie_downstream_port(pdev))
919 return;
920
921 /* VIA has a strange chipset, root port is under a bridge */
922 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
923 pdev->bus->self)
924 return;
925
926 down_read(&pci_bus_sem);
927 if (list_empty(&pdev->subordinate->devices))
928 goto out;
929
930 mutex_lock(&aspm_lock);
931 link = alloc_pcie_link_state(pdev);
932 if (!link)
933 goto unlock;
934 /*
935 * Setup initial ASPM state. Note that we need to configure
936 * upstream links also because capable state of them can be
937 * update through pcie_aspm_cap_init().
938 */
939 pcie_aspm_cap_init(link, blacklist);
940
941 /* Setup initial Clock PM state */
942 pcie_clkpm_cap_init(link, blacklist);
943
944 /*
945 * At this stage drivers haven't had an opportunity to change the
946 * link policy setting. Enabling ASPM on broken hardware can cripple
947 * it even before the driver has had a chance to disable ASPM, so
948 * default to a safe level right now. If we're enabling ASPM beyond
949 * the BIOS's expectation, we'll do so once pci_enable_device() is
950 * called.
951 */
952 if (aspm_policy != POLICY_POWERSAVE &&
953 aspm_policy != POLICY_POWER_SUPERSAVE) {
954 pcie_config_aspm_path(link);
955 pcie_set_clkpm(link, policy_to_clkpm_state(link));
956 }
957
958unlock:
959 mutex_unlock(&aspm_lock);
960out:
961 up_read(&pci_bus_sem);
962}
963
964/* Recheck latencies and update aspm_capable for links under the root */
965static void pcie_update_aspm_capable(struct pcie_link_state *root)
966{
967 struct pcie_link_state *link;
968 BUG_ON(root->parent);
969 list_for_each_entry(link, &link_list, sibling) {
970 if (link->root != root)
971 continue;
972 link->aspm_capable = link->aspm_support;
973 }
974 list_for_each_entry(link, &link_list, sibling) {
975 struct pci_dev *child;
976 struct pci_bus *linkbus = link->pdev->subordinate;
977 if (link->root != root)
978 continue;
979 list_for_each_entry(child, &linkbus->devices, bus_list) {
980 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
981 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
982 continue;
983 pcie_aspm_check_latency(child);
984 }
985 }
986}
987
988/* @pdev: the endpoint device */
989void pcie_aspm_exit_link_state(struct pci_dev *pdev)
990{
991 struct pci_dev *parent = pdev->bus->self;
992 struct pcie_link_state *link, *root, *parent_link;
993
994 if (!parent || !parent->link_state)
995 return;
996
997 down_read(&pci_bus_sem);
998 mutex_lock(&aspm_lock);
999 /*
1000 * All PCIe functions are in one slot, remove one function will remove
1001 * the whole slot, so just wait until we are the last function left.
1002 */
1003 if (!list_empty(&parent->subordinate->devices))
1004 goto out;
1005
1006 link = parent->link_state;
1007 root = link->root;
1008 parent_link = link->parent;
1009
1010 /* All functions are removed, so just disable ASPM for the link */
1011 pcie_config_aspm_link(link, 0);
1012 list_del(&link->sibling);
1013 /* Clock PM is for endpoint device */
1014 free_link_state(link);
1015
1016 /* Recheck latencies and configure upstream links */
1017 if (parent_link) {
1018 pcie_update_aspm_capable(root);
1019 pcie_config_aspm_path(parent_link);
1020 }
1021out:
1022 mutex_unlock(&aspm_lock);
1023 up_read(&pci_bus_sem);
1024}
1025
1026/* @pdev: the root port or switch downstream port */
1027void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1028{
1029 struct pcie_link_state *link = pdev->link_state;
1030
1031 if (aspm_disabled || !link)
1032 return;
1033 /*
1034 * Devices changed PM state, we should recheck if latency
1035 * meets all functions' requirement
1036 */
1037 down_read(&pci_bus_sem);
1038 mutex_lock(&aspm_lock);
1039 pcie_update_aspm_capable(link->root);
1040 pcie_config_aspm_path(link);
1041 mutex_unlock(&aspm_lock);
1042 up_read(&pci_bus_sem);
1043}
1044
1045void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1046{
1047 struct pcie_link_state *link = pdev->link_state;
1048
1049 if (aspm_disabled || !link)
1050 return;
1051
1052 if (aspm_policy != POLICY_POWERSAVE &&
1053 aspm_policy != POLICY_POWER_SUPERSAVE)
1054 return;
1055
1056 down_read(&pci_bus_sem);
1057 mutex_lock(&aspm_lock);
1058 pcie_config_aspm_path(link);
1059 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1060 mutex_unlock(&aspm_lock);
1061 up_read(&pci_bus_sem);
1062}
1063
1064static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1065{
1066 struct pci_dev *parent = pdev->bus->self;
1067 struct pcie_link_state *link;
1068
1069 if (!pci_is_pcie(pdev))
1070 return 0;
1071
1072 if (pcie_downstream_port(pdev))
1073 parent = pdev;
1074 if (!parent || !parent->link_state)
1075 return -EINVAL;
1076
1077 /*
1078 * A driver requested that ASPM be disabled on this device, but
1079 * if we don't have permission to manage ASPM (e.g., on ACPI
1080 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1081 * the _OSC method), we can't honor that request. Windows has
1082 * a similar mechanism using "PciASPMOptOut", which is also
1083 * ignored in this situation.
1084 */
1085 if (aspm_disabled) {
1086 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1087 return -EPERM;
1088 }
1089
1090 if (sem)
1091 down_read(&pci_bus_sem);
1092 mutex_lock(&aspm_lock);
1093 link = parent->link_state;
1094 if (state & PCIE_LINK_STATE_L0S)
1095 link->aspm_disable |= ASPM_STATE_L0S;
1096 if (state & PCIE_LINK_STATE_L1)
1097 link->aspm_disable |= ASPM_STATE_L1;
1098 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1099
1100 if (state & PCIE_LINK_STATE_CLKPM) {
1101 link->clkpm_capable = 0;
1102 pcie_set_clkpm(link, 0);
1103 }
1104 mutex_unlock(&aspm_lock);
1105 if (sem)
1106 up_read(&pci_bus_sem);
1107
1108 return 0;
1109}
1110
1111int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1112{
1113 return __pci_disable_link_state(pdev, state, false);
1114}
1115EXPORT_SYMBOL(pci_disable_link_state_locked);
1116
1117/**
1118 * pci_disable_link_state - Disable device's link state, so the link will
1119 * never enter specific states. Note that if the BIOS didn't grant ASPM
1120 * control to the OS, this does nothing because we can't touch the LNKCTL
1121 * register. Returns 0 or a negative errno.
1122 *
1123 * @pdev: PCI device
1124 * @state: ASPM link state to disable
1125 */
1126int pci_disable_link_state(struct pci_dev *pdev, int state)
1127{
1128 return __pci_disable_link_state(pdev, state, true);
1129}
1130EXPORT_SYMBOL(pci_disable_link_state);
1131
1132static int pcie_aspm_set_policy(const char *val,
1133 const struct kernel_param *kp)
1134{
1135 int i;
1136 struct pcie_link_state *link;
1137
1138 if (aspm_disabled)
1139 return -EPERM;
1140 i = sysfs_match_string(policy_str, val);
1141 if (i < 0)
1142 return i;
1143 if (i == aspm_policy)
1144 return 0;
1145
1146 down_read(&pci_bus_sem);
1147 mutex_lock(&aspm_lock);
1148 aspm_policy = i;
1149 list_for_each_entry(link, &link_list, sibling) {
1150 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1151 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1152 }
1153 mutex_unlock(&aspm_lock);
1154 up_read(&pci_bus_sem);
1155 return 0;
1156}
1157
1158static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1159{
1160 int i, cnt = 0;
1161 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1162 if (i == aspm_policy)
1163 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1164 else
1165 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1166 return cnt;
1167}
1168
1169module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1170 NULL, 0644);
1171
1172/**
1173 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1174 * @pdev: Target device.
1175 */
1176bool pcie_aspm_enabled(struct pci_dev *pdev)
1177{
1178 struct pci_dev *bridge = pci_upstream_bridge(pdev);
1179 bool ret;
1180
1181 if (!bridge)
1182 return false;
1183
1184 mutex_lock(&aspm_lock);
1185 ret = bridge->link_state ? !!bridge->link_state->aspm_enabled : false;
1186 mutex_unlock(&aspm_lock);
1187
1188 return ret;
1189}
1190EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1191
1192#ifdef CONFIG_PCIEASPM_DEBUG
1193static ssize_t link_state_show(struct device *dev,
1194 struct device_attribute *attr,
1195 char *buf)
1196{
1197 struct pci_dev *pci_device = to_pci_dev(dev);
1198 struct pcie_link_state *link_state = pci_device->link_state;
1199
1200 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1201}
1202
1203static ssize_t link_state_store(struct device *dev,
1204 struct device_attribute *attr,
1205 const char *buf,
1206 size_t n)
1207{
1208 struct pci_dev *pdev = to_pci_dev(dev);
1209 struct pcie_link_state *link, *root = pdev->link_state->root;
1210 u32 state;
1211
1212 if (aspm_disabled)
1213 return -EPERM;
1214
1215 if (kstrtouint(buf, 10, &state))
1216 return -EINVAL;
1217 if ((state & ~ASPM_STATE_ALL) != 0)
1218 return -EINVAL;
1219
1220 down_read(&pci_bus_sem);
1221 mutex_lock(&aspm_lock);
1222 list_for_each_entry(link, &link_list, sibling) {
1223 if (link->root != root)
1224 continue;
1225 pcie_config_aspm_link(link, state);
1226 }
1227 mutex_unlock(&aspm_lock);
1228 up_read(&pci_bus_sem);
1229 return n;
1230}
1231
1232static ssize_t clk_ctl_show(struct device *dev,
1233 struct device_attribute *attr,
1234 char *buf)
1235{
1236 struct pci_dev *pci_device = to_pci_dev(dev);
1237 struct pcie_link_state *link_state = pci_device->link_state;
1238
1239 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1240}
1241
1242static ssize_t clk_ctl_store(struct device *dev,
1243 struct device_attribute *attr,
1244 const char *buf,
1245 size_t n)
1246{
1247 struct pci_dev *pdev = to_pci_dev(dev);
1248 bool state;
1249
1250 if (strtobool(buf, &state))
1251 return -EINVAL;
1252
1253 down_read(&pci_bus_sem);
1254 mutex_lock(&aspm_lock);
1255 pcie_set_clkpm_nocheck(pdev->link_state, state);
1256 mutex_unlock(&aspm_lock);
1257 up_read(&pci_bus_sem);
1258
1259 return n;
1260}
1261
1262static DEVICE_ATTR_RW(link_state);
1263static DEVICE_ATTR_RW(clk_ctl);
1264
1265static char power_group[] = "power";
1266void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1267{
1268 struct pcie_link_state *link_state = pdev->link_state;
1269
1270 if (!link_state)
1271 return;
1272
1273 if (link_state->aspm_support)
1274 sysfs_add_file_to_group(&pdev->dev.kobj,
1275 &dev_attr_link_state.attr, power_group);
1276 if (link_state->clkpm_capable)
1277 sysfs_add_file_to_group(&pdev->dev.kobj,
1278 &dev_attr_clk_ctl.attr, power_group);
1279}
1280
1281void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1282{
1283 struct pcie_link_state *link_state = pdev->link_state;
1284
1285 if (!link_state)
1286 return;
1287
1288 if (link_state->aspm_support)
1289 sysfs_remove_file_from_group(&pdev->dev.kobj,
1290 &dev_attr_link_state.attr, power_group);
1291 if (link_state->clkpm_capable)
1292 sysfs_remove_file_from_group(&pdev->dev.kobj,
1293 &dev_attr_clk_ctl.attr, power_group);
1294}
1295#endif
1296
1297static int __init pcie_aspm_disable(char *str)
1298{
1299 if (!strcmp(str, "off")) {
1300 aspm_policy = POLICY_DEFAULT;
1301 aspm_disabled = 1;
1302 aspm_support_enabled = false;
1303 printk(KERN_INFO "PCIe ASPM is disabled\n");
1304 } else if (!strcmp(str, "force")) {
1305 aspm_force = 1;
1306 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1307 }
1308 return 1;
1309}
1310
1311__setup("pcie_aspm=", pcie_aspm_disable);
1312
1313void pcie_no_aspm(void)
1314{
1315 /*
1316 * Disabling ASPM is intended to prevent the kernel from modifying
1317 * existing hardware state, not to clear existing state. To that end:
1318 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1319 * (b) prevent userspace from changing policy
1320 */
1321 if (!aspm_force) {
1322 aspm_policy = POLICY_DEFAULT;
1323 aspm_disabled = 1;
1324 }
1325}
1326
1327bool pcie_aspm_support_enabled(void)
1328{
1329 return aspm_support_enabled;
1330}
1331EXPORT_SYMBOL(pcie_aspm_support_enabled);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Enable PCIe link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/bitfield.h>
11#include <linux/bits.h>
12#include <linux/build_bug.h>
13#include <linux/kernel.h>
14#include <linux/limits.h>
15#include <linux/math.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/pci.h>
19#include <linux/pci_regs.h>
20#include <linux/errno.h>
21#include <linux/pm.h>
22#include <linux/init.h>
23#include <linux/printk.h>
24#include <linux/slab.h>
25#include <linux/time.h>
26
27#include "../pci.h"
28
29void pci_save_ltr_state(struct pci_dev *dev)
30{
31 int ltr;
32 struct pci_cap_saved_state *save_state;
33 u32 *cap;
34
35 if (!pci_is_pcie(dev))
36 return;
37
38 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
39 if (!ltr)
40 return;
41
42 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
43 if (!save_state) {
44 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
45 return;
46 }
47
48 /* Some broken devices only support dword access to LTR */
49 cap = &save_state->cap.data[0];
50 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
51}
52
53void pci_restore_ltr_state(struct pci_dev *dev)
54{
55 struct pci_cap_saved_state *save_state;
56 int ltr;
57 u32 *cap;
58
59 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
60 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
61 if (!save_state || !ltr)
62 return;
63
64 /* Some broken devices only support dword access to LTR */
65 cap = &save_state->cap.data[0];
66 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
67}
68
69void pci_configure_aspm_l1ss(struct pci_dev *pdev)
70{
71 int rc;
72
73 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
74
75 rc = pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_L1SS,
76 2 * sizeof(u32));
77 if (rc)
78 pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n",
79 ERR_PTR(rc));
80}
81
82void pci_save_aspm_l1ss_state(struct pci_dev *pdev)
83{
84 struct pci_cap_saved_state *save_state;
85 u16 l1ss = pdev->l1ss;
86 u32 *cap;
87
88 /*
89 * Save L1 substate configuration. The ASPM L0s/L1 configuration
90 * in PCI_EXP_LNKCTL_ASPMC is saved by pci_save_pcie_state().
91 */
92 if (!l1ss)
93 return;
94
95 save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
96 if (!save_state)
97 return;
98
99 cap = &save_state->cap.data[0];
100 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++);
101 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++);
102}
103
104void pci_restore_aspm_l1ss_state(struct pci_dev *pdev)
105{
106 struct pci_cap_saved_state *pl_save_state, *cl_save_state;
107 struct pci_dev *parent = pdev->bus->self;
108 u32 *cap, pl_ctl1, pl_ctl2, pl_l1_2_enable;
109 u32 cl_ctl1, cl_ctl2, cl_l1_2_enable;
110 u16 clnkctl, plnkctl;
111
112 /*
113 * In case BIOS enabled L1.2 when resuming, we need to disable it first
114 * on the downstream component before the upstream. So, don't attempt to
115 * restore either until we are at the downstream component.
116 */
117 if (pcie_downstream_port(pdev) || !parent)
118 return;
119
120 if (!pdev->l1ss || !parent->l1ss)
121 return;
122
123 cl_save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
124 pl_save_state = pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS);
125 if (!cl_save_state || !pl_save_state)
126 return;
127
128 cap = &cl_save_state->cap.data[0];
129 cl_ctl2 = *cap++;
130 cl_ctl1 = *cap;
131 cap = &pl_save_state->cap.data[0];
132 pl_ctl2 = *cap++;
133 pl_ctl1 = *cap;
134
135 /* Make sure L0s/L1 are disabled before updating L1SS config */
136 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &clnkctl);
137 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &plnkctl);
138 if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, clnkctl) ||
139 FIELD_GET(PCI_EXP_LNKCTL_ASPMC, plnkctl)) {
140 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
141 clnkctl & ~PCI_EXP_LNKCTL_ASPMC);
142 pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
143 plnkctl & ~PCI_EXP_LNKCTL_ASPMC);
144 }
145
146 /*
147 * Disable L1.2 on this downstream endpoint device first, followed
148 * by the upstream
149 */
150 pci_clear_and_set_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
151 PCI_L1SS_CTL1_L1_2_MASK, 0);
152 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
153 PCI_L1SS_CTL1_L1_2_MASK, 0);
154
155 /*
156 * In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD
157 * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
158 * enable bits, even though they're all in PCI_L1SS_CTL1.
159 */
160 pl_l1_2_enable = pl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
161 pl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
162 cl_l1_2_enable = cl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
163 cl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
164
165 /* Write back without enables first (above we cleared them in ctl1) */
166 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2);
167 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2);
168 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1);
169 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1);
170
171 /* Then write back the enables */
172 if (pl_l1_2_enable || cl_l1_2_enable) {
173 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
174 pl_ctl1 | pl_l1_2_enable);
175 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
176 cl_ctl1 | cl_l1_2_enable);
177 }
178
179 /* Restore L0s/L1 if they were enabled */
180 if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, clnkctl) ||
181 FIELD_GET(PCI_EXP_LNKCTL_ASPMC, plnkctl)) {
182 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, plnkctl);
183 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, clnkctl);
184 }
185}
186
187#ifdef CONFIG_PCIEASPM
188
189#ifdef MODULE_PARAM_PREFIX
190#undef MODULE_PARAM_PREFIX
191#endif
192#define MODULE_PARAM_PREFIX "pcie_aspm."
193
194/* Note: these are not register definitions */
195#define PCIE_LINK_STATE_L0S_UP BIT(0) /* Upstream direction L0s state */
196#define PCIE_LINK_STATE_L0S_DW BIT(1) /* Downstream direction L0s state */
197static_assert(PCIE_LINK_STATE_L0S == (PCIE_LINK_STATE_L0S_UP | PCIE_LINK_STATE_L0S_DW));
198
199#define PCIE_LINK_STATE_L1_SS_PCIPM (PCIE_LINK_STATE_L1_1_PCIPM |\
200 PCIE_LINK_STATE_L1_2_PCIPM)
201#define PCIE_LINK_STATE_L1_2_MASK (PCIE_LINK_STATE_L1_2 |\
202 PCIE_LINK_STATE_L1_2_PCIPM)
203#define PCIE_LINK_STATE_L1SS (PCIE_LINK_STATE_L1_1 |\
204 PCIE_LINK_STATE_L1_1_PCIPM |\
205 PCIE_LINK_STATE_L1_2_MASK)
206
207struct pcie_link_state {
208 struct pci_dev *pdev; /* Upstream component of the Link */
209 struct pci_dev *downstream; /* Downstream component, function 0 */
210 struct pcie_link_state *root; /* pointer to the root port link */
211 struct pcie_link_state *parent; /* pointer to the parent Link state */
212 struct list_head sibling; /* node in link_list */
213
214 /* ASPM state */
215 u32 aspm_support:7; /* Supported ASPM state */
216 u32 aspm_enabled:7; /* Enabled ASPM state */
217 u32 aspm_capable:7; /* Capable ASPM state with latency */
218 u32 aspm_default:7; /* Default ASPM state by BIOS */
219 u32 aspm_disable:7; /* Disabled ASPM state */
220
221 /* Clock PM state */
222 u32 clkpm_capable:1; /* Clock PM capable? */
223 u32 clkpm_enabled:1; /* Current Clock PM state */
224 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
225 u32 clkpm_disable:1; /* Clock PM disabled */
226};
227
228static int aspm_disabled, aspm_force;
229static bool aspm_support_enabled = true;
230static DEFINE_MUTEX(aspm_lock);
231static LIST_HEAD(link_list);
232
233#define POLICY_DEFAULT 0 /* BIOS default setting */
234#define POLICY_PERFORMANCE 1 /* high performance */
235#define POLICY_POWERSAVE 2 /* high power saving */
236#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
237
238#ifdef CONFIG_PCIEASPM_PERFORMANCE
239static int aspm_policy = POLICY_PERFORMANCE;
240#elif defined CONFIG_PCIEASPM_POWERSAVE
241static int aspm_policy = POLICY_POWERSAVE;
242#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
243static int aspm_policy = POLICY_POWER_SUPERSAVE;
244#else
245static int aspm_policy;
246#endif
247
248static const char *policy_str[] = {
249 [POLICY_DEFAULT] = "default",
250 [POLICY_PERFORMANCE] = "performance",
251 [POLICY_POWERSAVE] = "powersave",
252 [POLICY_POWER_SUPERSAVE] = "powersupersave"
253};
254
255/*
256 * The L1 PM substate capability is only implemented in function 0 in a
257 * multi function device.
258 */
259static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
260{
261 struct pci_dev *child;
262
263 list_for_each_entry(child, &linkbus->devices, bus_list)
264 if (PCI_FUNC(child->devfn) == 0)
265 return child;
266 return NULL;
267}
268
269static int policy_to_aspm_state(struct pcie_link_state *link)
270{
271 switch (aspm_policy) {
272 case POLICY_PERFORMANCE:
273 /* Disable ASPM and Clock PM */
274 return 0;
275 case POLICY_POWERSAVE:
276 /* Enable ASPM L0s/L1 */
277 return PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1;
278 case POLICY_POWER_SUPERSAVE:
279 /* Enable Everything */
280 return PCIE_LINK_STATE_ASPM_ALL;
281 case POLICY_DEFAULT:
282 return link->aspm_default;
283 }
284 return 0;
285}
286
287static int policy_to_clkpm_state(struct pcie_link_state *link)
288{
289 switch (aspm_policy) {
290 case POLICY_PERFORMANCE:
291 /* Disable ASPM and Clock PM */
292 return 0;
293 case POLICY_POWERSAVE:
294 case POLICY_POWER_SUPERSAVE:
295 /* Enable Clock PM */
296 return 1;
297 case POLICY_DEFAULT:
298 return link->clkpm_default;
299 }
300 return 0;
301}
302
303static void pci_update_aspm_saved_state(struct pci_dev *dev)
304{
305 struct pci_cap_saved_state *save_state;
306 u16 *cap, lnkctl, aspm_ctl;
307
308 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
309 if (!save_state)
310 return;
311
312 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl);
313
314 /*
315 * Update ASPM and CLKREQ bits of LNKCTL in save_state. We only
316 * write PCI_EXP_LNKCTL_CCC during enumeration, so it shouldn't
317 * change after being captured in save_state.
318 */
319 aspm_ctl = lnkctl & (PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN);
320 lnkctl &= ~(PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN);
321
322 /* Depends on pci_save_pcie_state(): cap[1] is LNKCTL */
323 cap = (u16 *)&save_state->cap.data[0];
324 cap[1] = lnkctl | aspm_ctl;
325}
326
327static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
328{
329 struct pci_dev *child;
330 struct pci_bus *linkbus = link->pdev->subordinate;
331 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
332
333 list_for_each_entry(child, &linkbus->devices, bus_list) {
334 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
335 PCI_EXP_LNKCTL_CLKREQ_EN,
336 val);
337 pci_update_aspm_saved_state(child);
338 }
339 link->clkpm_enabled = !!enable;
340}
341
342static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
343{
344 /*
345 * Don't enable Clock PM if the link is not Clock PM capable
346 * or Clock PM is disabled
347 */
348 if (!link->clkpm_capable || link->clkpm_disable)
349 enable = 0;
350 /* Need nothing if the specified equals to current state */
351 if (link->clkpm_enabled == enable)
352 return;
353 pcie_set_clkpm_nocheck(link, enable);
354}
355
356static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
357{
358 int capable = 1, enabled = 1;
359 u32 reg32;
360 u16 reg16;
361 struct pci_dev *child;
362 struct pci_bus *linkbus = link->pdev->subordinate;
363
364 /* All functions should have the same cap and state, take the worst */
365 list_for_each_entry(child, &linkbus->devices, bus_list) {
366 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
367 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
368 capable = 0;
369 enabled = 0;
370 break;
371 }
372 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
373 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
374 enabled = 0;
375 }
376 link->clkpm_enabled = enabled;
377 link->clkpm_default = enabled;
378 link->clkpm_capable = capable;
379 link->clkpm_disable = blacklist ? 1 : 0;
380}
381
382/*
383 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
384 * could use common clock. If they are, configure them to use the
385 * common clock. That will reduce the ASPM state exit latency.
386 */
387static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
388{
389 int same_clock = 1;
390 u16 reg16, ccc, parent_old_ccc, child_old_ccc[8];
391 struct pci_dev *child, *parent = link->pdev;
392 struct pci_bus *linkbus = parent->subordinate;
393 /*
394 * All functions of a slot should have the same Slot Clock
395 * Configuration, so just check one function
396 */
397 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
398 BUG_ON(!pci_is_pcie(child));
399
400 /* Check downstream component if bit Slot Clock Configuration is 1 */
401 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
402 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
403 same_clock = 0;
404
405 /* Check upstream component if bit Slot Clock Configuration is 1 */
406 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
407 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
408 same_clock = 0;
409
410 /* Port might be already in common clock mode */
411 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
412 parent_old_ccc = reg16 & PCI_EXP_LNKCTL_CCC;
413 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
414 bool consistent = true;
415
416 list_for_each_entry(child, &linkbus->devices, bus_list) {
417 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
418 ®16);
419 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
420 consistent = false;
421 break;
422 }
423 }
424 if (consistent)
425 return;
426 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
427 }
428
429 ccc = same_clock ? PCI_EXP_LNKCTL_CCC : 0;
430 /* Configure downstream component, all functions */
431 list_for_each_entry(child, &linkbus->devices, bus_list) {
432 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
433 child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC;
434 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
435 PCI_EXP_LNKCTL_CCC, ccc);
436 }
437
438 /* Configure upstream component */
439 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
440 PCI_EXP_LNKCTL_CCC, ccc);
441
442 if (pcie_retrain_link(link->pdev, true)) {
443
444 /* Training failed. Restore common clock configurations */
445 pci_err(parent, "ASPM: Could not configure common clock\n");
446 list_for_each_entry(child, &linkbus->devices, bus_list)
447 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
448 PCI_EXP_LNKCTL_CCC,
449 child_old_ccc[PCI_FUNC(child->devfn)]);
450 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
451 PCI_EXP_LNKCTL_CCC, parent_old_ccc);
452 }
453}
454
455/* Convert L0s latency encoding to ns */
456static u32 calc_l0s_latency(u32 lnkcap)
457{
458 u32 encoding = FIELD_GET(PCI_EXP_LNKCAP_L0SEL, lnkcap);
459
460 if (encoding == 0x7)
461 return 5 * NSEC_PER_USEC; /* > 4us */
462 return (64 << encoding);
463}
464
465/* Convert L0s acceptable latency encoding to ns */
466static u32 calc_l0s_acceptable(u32 encoding)
467{
468 if (encoding == 0x7)
469 return U32_MAX;
470 return (64 << encoding);
471}
472
473/* Convert L1 latency encoding to ns */
474static u32 calc_l1_latency(u32 lnkcap)
475{
476 u32 encoding = FIELD_GET(PCI_EXP_LNKCAP_L1EL, lnkcap);
477
478 if (encoding == 0x7)
479 return 65 * NSEC_PER_USEC; /* > 64us */
480 return NSEC_PER_USEC << encoding;
481}
482
483/* Convert L1 acceptable latency encoding to ns */
484static u32 calc_l1_acceptable(u32 encoding)
485{
486 if (encoding == 0x7)
487 return U32_MAX;
488 return NSEC_PER_USEC << encoding;
489}
490
491/* Convert L1SS T_pwr encoding to usec */
492static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
493{
494 switch (scale) {
495 case 0:
496 return val * 2;
497 case 1:
498 return val * 10;
499 case 2:
500 return val * 100;
501 }
502 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
503 return 0;
504}
505
506/*
507 * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
508 * register. Ports enter L1.2 when the most recent LTR value is greater
509 * than or equal to LTR_L1.2_THRESHOLD, so we round up to make sure we
510 * don't enter L1.2 too aggressively.
511 *
512 * See PCIe r6.0, sec 5.5.1, 6.18, 7.8.3.3.
513 */
514static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
515{
516 u64 threshold_ns = (u64)threshold_us * NSEC_PER_USEC;
517
518 /*
519 * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max
520 * value of 0x3ff.
521 */
522 if (threshold_ns <= 1 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
523 *scale = 0; /* Value times 1ns */
524 *value = threshold_ns;
525 } else if (threshold_ns <= 32 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
526 *scale = 1; /* Value times 32ns */
527 *value = roundup(threshold_ns, 32) / 32;
528 } else if (threshold_ns <= 1024 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
529 *scale = 2; /* Value times 1024ns */
530 *value = roundup(threshold_ns, 1024) / 1024;
531 } else if (threshold_ns <= 32768 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
532 *scale = 3; /* Value times 32768ns */
533 *value = roundup(threshold_ns, 32768) / 32768;
534 } else if (threshold_ns <= 1048576 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
535 *scale = 4; /* Value times 1048576ns */
536 *value = roundup(threshold_ns, 1048576) / 1048576;
537 } else if (threshold_ns <= (u64)33554432 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
538 *scale = 5; /* Value times 33554432ns */
539 *value = roundup(threshold_ns, 33554432) / 33554432;
540 } else {
541 *scale = 5;
542 *value = FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE);
543 }
544}
545
546static void pcie_aspm_check_latency(struct pci_dev *endpoint)
547{
548 u32 latency, encoding, lnkcap_up, lnkcap_dw;
549 u32 l1_switch_latency = 0, latency_up_l0s;
550 u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
551 u32 acceptable_l0s, acceptable_l1;
552 struct pcie_link_state *link;
553
554 /* Device not in D0 doesn't need latency check */
555 if ((endpoint->current_state != PCI_D0) &&
556 (endpoint->current_state != PCI_UNKNOWN))
557 return;
558
559 link = endpoint->bus->self->link_state;
560
561 /* Calculate endpoint L0s acceptable latency */
562 encoding = FIELD_GET(PCI_EXP_DEVCAP_L0S, endpoint->devcap);
563 acceptable_l0s = calc_l0s_acceptable(encoding);
564
565 /* Calculate endpoint L1 acceptable latency */
566 encoding = FIELD_GET(PCI_EXP_DEVCAP_L1, endpoint->devcap);
567 acceptable_l1 = calc_l1_acceptable(encoding);
568
569 while (link) {
570 struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
571
572 /* Read direction exit latencies */
573 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
574 &lnkcap_up);
575 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
576 &lnkcap_dw);
577 latency_up_l0s = calc_l0s_latency(lnkcap_up);
578 latency_up_l1 = calc_l1_latency(lnkcap_up);
579 latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
580 latency_dw_l1 = calc_l1_latency(lnkcap_dw);
581
582 /* Check upstream direction L0s latency */
583 if ((link->aspm_capable & PCIE_LINK_STATE_L0S_UP) &&
584 (latency_up_l0s > acceptable_l0s))
585 link->aspm_capable &= ~PCIE_LINK_STATE_L0S_UP;
586
587 /* Check downstream direction L0s latency */
588 if ((link->aspm_capable & PCIE_LINK_STATE_L0S_DW) &&
589 (latency_dw_l0s > acceptable_l0s))
590 link->aspm_capable &= ~PCIE_LINK_STATE_L0S_DW;
591 /*
592 * Check L1 latency.
593 * Every switch on the path to root complex need 1
594 * more microsecond for L1. Spec doesn't mention L0s.
595 *
596 * The exit latencies for L1 substates are not advertised
597 * by a device. Since the spec also doesn't mention a way
598 * to determine max latencies introduced by enabling L1
599 * substates on the components, it is not clear how to do
600 * a L1 substate exit latency check. We assume that the
601 * L1 exit latencies advertised by a device include L1
602 * substate latencies (and hence do not do any check).
603 */
604 latency = max_t(u32, latency_up_l1, latency_dw_l1);
605 if ((link->aspm_capable & PCIE_LINK_STATE_L1) &&
606 (latency + l1_switch_latency > acceptable_l1))
607 link->aspm_capable &= ~PCIE_LINK_STATE_L1;
608 l1_switch_latency += NSEC_PER_USEC;
609
610 link = link->parent;
611 }
612}
613
614/* Calculate L1.2 PM substate timing parameters */
615static void aspm_calc_l12_info(struct pcie_link_state *link,
616 u32 parent_l1ss_cap, u32 child_l1ss_cap)
617{
618 struct pci_dev *child = link->downstream, *parent = link->pdev;
619 u32 val1, val2, scale1, scale2;
620 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
621 u32 ctl1 = 0, ctl2 = 0;
622 u32 pctl1, pctl2, cctl1, cctl2;
623 u32 pl1_2_enables, cl1_2_enables;
624
625 /* Choose the greater of the two Port Common_Mode_Restore_Times */
626 val1 = FIELD_GET(PCI_L1SS_CAP_CM_RESTORE_TIME, parent_l1ss_cap);
627 val2 = FIELD_GET(PCI_L1SS_CAP_CM_RESTORE_TIME, child_l1ss_cap);
628 t_common_mode = max(val1, val2);
629
630 /* Choose the greater of the two Port T_POWER_ON times */
631 val1 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_VALUE, parent_l1ss_cap);
632 scale1 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_SCALE, parent_l1ss_cap);
633 val2 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_VALUE, child_l1ss_cap);
634 scale2 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_SCALE, child_l1ss_cap);
635
636 if (calc_l12_pwron(parent, scale1, val1) >
637 calc_l12_pwron(child, scale2, val2)) {
638 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale1) |
639 FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_VALUE, val1);
640 t_power_on = calc_l12_pwron(parent, scale1, val1);
641 } else {
642 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale2) |
643 FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_VALUE, val2);
644 t_power_on = calc_l12_pwron(child, scale2, val2);
645 }
646
647 /*
648 * Set LTR_L1.2_THRESHOLD to the time required to transition the
649 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
650 * downstream devices report (via LTR) that they can tolerate at
651 * least that much latency.
652 *
653 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
654 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
655 * least 4us.
656 */
657 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
658 encode_l12_threshold(l1_2_threshold, &scale, &value);
659 ctl1 |= FIELD_PREP(PCI_L1SS_CTL1_CM_RESTORE_TIME, t_common_mode) |
660 FIELD_PREP(PCI_L1SS_CTL1_LTR_L12_TH_VALUE, value) |
661 FIELD_PREP(PCI_L1SS_CTL1_LTR_L12_TH_SCALE, scale);
662
663 /* Some broken devices only support dword access to L1 SS */
664 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
665 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
666 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
667 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
668
669 if (ctl1 == pctl1 && ctl1 == cctl1 &&
670 ctl2 == pctl2 && ctl2 == cctl2)
671 return;
672
673 /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
674 pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
675 cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
676
677 if (pl1_2_enables || cl1_2_enables) {
678 pci_clear_and_set_config_dword(child,
679 child->l1ss + PCI_L1SS_CTL1,
680 PCI_L1SS_CTL1_L1_2_MASK, 0);
681 pci_clear_and_set_config_dword(parent,
682 parent->l1ss + PCI_L1SS_CTL1,
683 PCI_L1SS_CTL1_L1_2_MASK, 0);
684 }
685
686 /* Program T_POWER_ON times in both ports */
687 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
688 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
689
690 /* Program Common_Mode_Restore_Time in upstream device */
691 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
692 PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
693
694 /* Program LTR_L1.2_THRESHOLD time in both ports */
695 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
696 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
697 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
698 ctl1);
699 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
700 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
701 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
702 ctl1);
703
704 if (pl1_2_enables || cl1_2_enables) {
705 pci_clear_and_set_config_dword(parent,
706 parent->l1ss + PCI_L1SS_CTL1, 0,
707 pl1_2_enables);
708 pci_clear_and_set_config_dword(child,
709 child->l1ss + PCI_L1SS_CTL1, 0,
710 cl1_2_enables);
711 }
712}
713
714static void aspm_l1ss_init(struct pcie_link_state *link)
715{
716 struct pci_dev *child = link->downstream, *parent = link->pdev;
717 u32 parent_l1ss_cap, child_l1ss_cap;
718 u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
719
720 if (!parent->l1ss || !child->l1ss)
721 return;
722
723 /* Setup L1 substate */
724 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
725 &parent_l1ss_cap);
726 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
727 &child_l1ss_cap);
728
729 if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
730 parent_l1ss_cap = 0;
731 if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
732 child_l1ss_cap = 0;
733
734 /*
735 * If we don't have LTR for the entire path from the Root Complex
736 * to this device, we can't use ASPM L1.2 because it relies on the
737 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
738 */
739 if (!child->ltr_path)
740 child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
741
742 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
743 link->aspm_support |= PCIE_LINK_STATE_L1_1;
744 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
745 link->aspm_support |= PCIE_LINK_STATE_L1_2;
746 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
747 link->aspm_support |= PCIE_LINK_STATE_L1_1_PCIPM;
748 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
749 link->aspm_support |= PCIE_LINK_STATE_L1_2_PCIPM;
750
751 if (parent_l1ss_cap)
752 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
753 &parent_l1ss_ctl1);
754 if (child_l1ss_cap)
755 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
756 &child_l1ss_ctl1);
757
758 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
759 link->aspm_enabled |= PCIE_LINK_STATE_L1_1;
760 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
761 link->aspm_enabled |= PCIE_LINK_STATE_L1_2;
762 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
763 link->aspm_enabled |= PCIE_LINK_STATE_L1_1_PCIPM;
764 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
765 link->aspm_enabled |= PCIE_LINK_STATE_L1_2_PCIPM;
766
767 if (link->aspm_support & PCIE_LINK_STATE_L1_2_MASK)
768 aspm_calc_l12_info(link, parent_l1ss_cap, child_l1ss_cap);
769}
770
771static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
772{
773 struct pci_dev *child = link->downstream, *parent = link->pdev;
774 u32 parent_lnkcap, child_lnkcap;
775 u16 parent_lnkctl, child_lnkctl;
776 struct pci_bus *linkbus = parent->subordinate;
777
778 if (blacklist) {
779 /* Set enabled/disable so that we will disable ASPM later */
780 link->aspm_enabled = PCIE_LINK_STATE_ASPM_ALL;
781 link->aspm_disable = PCIE_LINK_STATE_ASPM_ALL;
782 return;
783 }
784
785 /*
786 * If ASPM not supported, don't mess with the clocks and link,
787 * bail out now.
788 */
789 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
790 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
791 if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
792 return;
793
794 /* Configure common clock before checking latencies */
795 pcie_aspm_configure_common_clock(link);
796
797 /*
798 * Re-read upstream/downstream components' register state after
799 * clock configuration. L0s & L1 exit latencies in the otherwise
800 * read-only Link Capabilities may change depending on common clock
801 * configuration (PCIe r5.0, sec 7.5.3.6).
802 */
803 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
804 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
805 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
806 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
807
808 /* Disable L0s/L1 before updating L1SS config */
809 if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
810 FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
811 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
812 child_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
813 pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
814 parent_lnkctl & ~PCI_EXP_LNKCTL_ASPMC);
815 }
816
817 /*
818 * Setup L0s state
819 *
820 * Note that we must not enable L0s in either direction on a
821 * given link unless components on both sides of the link each
822 * support L0s.
823 */
824 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
825 link->aspm_support |= PCIE_LINK_STATE_L0S;
826
827 if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
828 link->aspm_enabled |= PCIE_LINK_STATE_L0S_UP;
829 if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
830 link->aspm_enabled |= PCIE_LINK_STATE_L0S_DW;
831
832 /* Setup L1 state */
833 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
834 link->aspm_support |= PCIE_LINK_STATE_L1;
835
836 if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
837 link->aspm_enabled |= PCIE_LINK_STATE_L1;
838
839 aspm_l1ss_init(link);
840
841 /* Restore L0s/L1 if they were enabled */
842 if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, child_lnkctl) ||
843 FIELD_GET(PCI_EXP_LNKCTL_ASPMC, parent_lnkctl)) {
844 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_lnkctl);
845 pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_lnkctl);
846 }
847
848 /* Save default state */
849 link->aspm_default = link->aspm_enabled;
850
851 /* Setup initial capable state. Will be updated later */
852 link->aspm_capable = link->aspm_support;
853
854 /* Get and check endpoint acceptable latencies */
855 list_for_each_entry(child, &linkbus->devices, bus_list) {
856 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
857 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
858 continue;
859
860 pcie_aspm_check_latency(child);
861 }
862}
863
864/* Configure the ASPM L1 substates. Caller must disable L1 first. */
865static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
866{
867 u32 val;
868 struct pci_dev *child = link->downstream, *parent = link->pdev;
869
870 val = 0;
871 if (state & PCIE_LINK_STATE_L1_1)
872 val |= PCI_L1SS_CTL1_ASPM_L1_1;
873 if (state & PCIE_LINK_STATE_L1_2)
874 val |= PCI_L1SS_CTL1_ASPM_L1_2;
875 if (state & PCIE_LINK_STATE_L1_1_PCIPM)
876 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
877 if (state & PCIE_LINK_STATE_L1_2_PCIPM)
878 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
879
880 /*
881 * PCIe r6.2, sec 5.5.4, rules for enabling L1 PM Substates:
882 * - Clear L1.x enable bits at child first, then at parent
883 * - Set L1.x enable bits at parent first, then at child
884 * - ASPM/PCIPM L1.2 must be disabled while programming timing
885 * parameters
886 */
887
888 /* Disable all L1 substates */
889 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
890 PCI_L1SS_CTL1_L1SS_MASK, 0);
891 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
892 PCI_L1SS_CTL1_L1SS_MASK, 0);
893
894 /* Enable what we need to enable */
895 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
896 PCI_L1SS_CTL1_L1SS_MASK, val);
897 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
898 PCI_L1SS_CTL1_L1SS_MASK, val);
899}
900
901static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
902{
903 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
904 PCI_EXP_LNKCTL_ASPMC, val);
905}
906
907static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
908{
909 u32 upstream = 0, dwstream = 0;
910 struct pci_dev *child = link->downstream, *parent = link->pdev;
911 struct pci_bus *linkbus = parent->subordinate;
912
913 /* Enable only the states that were not explicitly disabled */
914 state &= (link->aspm_capable & ~link->aspm_disable);
915
916 /* Can't enable any substates if L1 is not enabled */
917 if (!(state & PCIE_LINK_STATE_L1))
918 state &= ~PCIE_LINK_STATE_L1SS;
919
920 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
921 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
922 state &= ~PCIE_LINK_STATE_L1_SS_PCIPM;
923 state |= (link->aspm_enabled & PCIE_LINK_STATE_L1_SS_PCIPM);
924 }
925
926 /* Nothing to do if the link is already in the requested state */
927 if (link->aspm_enabled == state)
928 return;
929 /* Convert ASPM state to upstream/downstream ASPM register state */
930 if (state & PCIE_LINK_STATE_L0S_UP)
931 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
932 if (state & PCIE_LINK_STATE_L0S_DW)
933 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
934 if (state & PCIE_LINK_STATE_L1) {
935 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
936 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
937 }
938
939 /*
940 * Per PCIe r6.2, sec 5.5.4, setting either or both of the enable
941 * bits for ASPM L1 PM Substates must be done while ASPM L1 is
942 * disabled. Disable L1 here and apply new configuration after L1SS
943 * configuration has been completed.
944 *
945 * Per sec 7.5.3.7, when disabling ASPM L1, software must disable
946 * it in the Downstream component prior to disabling it in the
947 * Upstream component, and ASPM L1 must be enabled in the Upstream
948 * component prior to enabling it in the Downstream component.
949 *
950 * Sec 7.5.3.7 also recommends programming the same ASPM Control
951 * value for all functions of a multi-function device.
952 */
953 list_for_each_entry(child, &linkbus->devices, bus_list)
954 pcie_config_aspm_dev(child, 0);
955 pcie_config_aspm_dev(parent, 0);
956
957 if (link->aspm_capable & PCIE_LINK_STATE_L1SS)
958 pcie_config_aspm_l1ss(link, state);
959
960 pcie_config_aspm_dev(parent, upstream);
961 list_for_each_entry(child, &linkbus->devices, bus_list)
962 pcie_config_aspm_dev(child, dwstream);
963
964 link->aspm_enabled = state;
965
966 /* Update latest ASPM configuration in saved context */
967 pci_save_aspm_l1ss_state(link->downstream);
968 pci_update_aspm_saved_state(link->downstream);
969 pci_save_aspm_l1ss_state(parent);
970 pci_update_aspm_saved_state(parent);
971}
972
973static void pcie_config_aspm_path(struct pcie_link_state *link)
974{
975 while (link) {
976 pcie_config_aspm_link(link, policy_to_aspm_state(link));
977 link = link->parent;
978 }
979}
980
981static void free_link_state(struct pcie_link_state *link)
982{
983 link->pdev->link_state = NULL;
984 kfree(link);
985}
986
987static int pcie_aspm_sanity_check(struct pci_dev *pdev)
988{
989 struct pci_dev *child;
990 u32 reg32;
991
992 /*
993 * Some functions in a slot might not all be PCIe functions,
994 * very strange. Disable ASPM for the whole slot
995 */
996 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
997 if (!pci_is_pcie(child))
998 return -EINVAL;
999
1000 /*
1001 * If ASPM is disabled then we're not going to change
1002 * the BIOS state. It's safe to continue even if it's a
1003 * pre-1.1 device
1004 */
1005
1006 if (aspm_disabled)
1007 continue;
1008
1009 /*
1010 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
1011 * RBER bit to determine if a function is 1.1 version device
1012 */
1013 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
1014 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
1015 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
1016 return -EINVAL;
1017 }
1018 }
1019 return 0;
1020}
1021
1022static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
1023{
1024 struct pcie_link_state *link;
1025
1026 link = kzalloc(sizeof(*link), GFP_KERNEL);
1027 if (!link)
1028 return NULL;
1029
1030 INIT_LIST_HEAD(&link->sibling);
1031 link->pdev = pdev;
1032 link->downstream = pci_function_0(pdev->subordinate);
1033
1034 /*
1035 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
1036 * hierarchies. Note that some PCIe host implementations omit
1037 * the root ports entirely, in which case a downstream port on
1038 * a switch may become the root of the link state chain for all
1039 * its subordinate endpoints.
1040 */
1041 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
1042 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
1043 !pdev->bus->parent->self) {
1044 link->root = link;
1045 } else {
1046 struct pcie_link_state *parent;
1047
1048 parent = pdev->bus->parent->self->link_state;
1049 if (!parent) {
1050 kfree(link);
1051 return NULL;
1052 }
1053
1054 link->parent = parent;
1055 link->root = link->parent->root;
1056 }
1057
1058 list_add(&link->sibling, &link_list);
1059 pdev->link_state = link;
1060 return link;
1061}
1062
1063static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
1064{
1065 struct pci_dev *child;
1066
1067 list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
1068 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
1069}
1070
1071/*
1072 * pcie_aspm_init_link_state: Initiate PCI express link state.
1073 * It is called after the pcie and its children devices are scanned.
1074 * @pdev: the root port or switch downstream port
1075 */
1076void pcie_aspm_init_link_state(struct pci_dev *pdev)
1077{
1078 struct pcie_link_state *link;
1079 int blacklist = !!pcie_aspm_sanity_check(pdev);
1080
1081 if (!aspm_support_enabled)
1082 return;
1083
1084 if (pdev->link_state)
1085 return;
1086
1087 /*
1088 * We allocate pcie_link_state for the component on the upstream
1089 * end of a Link, so there's nothing to do unless this device is
1090 * downstream port.
1091 */
1092 if (!pcie_downstream_port(pdev))
1093 return;
1094
1095 /* VIA has a strange chipset, root port is under a bridge */
1096 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
1097 pdev->bus->self)
1098 return;
1099
1100 down_read(&pci_bus_sem);
1101 if (list_empty(&pdev->subordinate->devices))
1102 goto out;
1103
1104 mutex_lock(&aspm_lock);
1105 link = alloc_pcie_link_state(pdev);
1106 if (!link)
1107 goto unlock;
1108 /*
1109 * Setup initial ASPM state. Note that we need to configure
1110 * upstream links also because capable state of them can be
1111 * update through pcie_aspm_cap_init().
1112 */
1113 pcie_aspm_cap_init(link, blacklist);
1114
1115 /* Setup initial Clock PM state */
1116 pcie_clkpm_cap_init(link, blacklist);
1117
1118 /*
1119 * At this stage drivers haven't had an opportunity to change the
1120 * link policy setting. Enabling ASPM on broken hardware can cripple
1121 * it even before the driver has had a chance to disable ASPM, so
1122 * default to a safe level right now. If we're enabling ASPM beyond
1123 * the BIOS's expectation, we'll do so once pci_enable_device() is
1124 * called.
1125 */
1126 if (aspm_policy != POLICY_POWERSAVE &&
1127 aspm_policy != POLICY_POWER_SUPERSAVE) {
1128 pcie_config_aspm_path(link);
1129 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1130 }
1131
1132 pcie_aspm_update_sysfs_visibility(pdev);
1133
1134unlock:
1135 mutex_unlock(&aspm_lock);
1136out:
1137 up_read(&pci_bus_sem);
1138}
1139
1140void pci_bridge_reconfigure_ltr(struct pci_dev *pdev)
1141{
1142 struct pci_dev *bridge;
1143 u32 ctl;
1144
1145 bridge = pci_upstream_bridge(pdev);
1146 if (bridge && bridge->ltr_path) {
1147 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1148 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1149 pci_dbg(bridge, "re-enabling LTR\n");
1150 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1151 PCI_EXP_DEVCTL2_LTR_EN);
1152 }
1153 }
1154}
1155
1156void pci_configure_ltr(struct pci_dev *pdev)
1157{
1158 struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
1159 struct pci_dev *bridge;
1160 u32 cap, ctl;
1161
1162 if (!pci_is_pcie(pdev))
1163 return;
1164
1165 pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap);
1166 if (!(cap & PCI_EXP_DEVCAP2_LTR))
1167 return;
1168
1169 pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL2, &ctl);
1170 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
1171 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
1172 pdev->ltr_path = 1;
1173 return;
1174 }
1175
1176 bridge = pci_upstream_bridge(pdev);
1177 if (bridge && bridge->ltr_path)
1178 pdev->ltr_path = 1;
1179
1180 return;
1181 }
1182
1183 if (!host->native_ltr)
1184 return;
1185
1186 /*
1187 * Software must not enable LTR in an Endpoint unless the Root
1188 * Complex and all intermediate Switches indicate support for LTR.
1189 * PCIe r4.0, sec 6.18.
1190 */
1191 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
1192 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
1193 PCI_EXP_DEVCTL2_LTR_EN);
1194 pdev->ltr_path = 1;
1195 return;
1196 }
1197
1198 /*
1199 * If we're configuring a hot-added device, LTR was likely
1200 * disabled in the upstream bridge, so re-enable it before enabling
1201 * it in the new device.
1202 */
1203 bridge = pci_upstream_bridge(pdev);
1204 if (bridge && bridge->ltr_path) {
1205 pci_bridge_reconfigure_ltr(pdev);
1206 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
1207 PCI_EXP_DEVCTL2_LTR_EN);
1208 pdev->ltr_path = 1;
1209 }
1210}
1211
1212/* Recheck latencies and update aspm_capable for links under the root */
1213static void pcie_update_aspm_capable(struct pcie_link_state *root)
1214{
1215 struct pcie_link_state *link;
1216 BUG_ON(root->parent);
1217 list_for_each_entry(link, &link_list, sibling) {
1218 if (link->root != root)
1219 continue;
1220 link->aspm_capable = link->aspm_support;
1221 }
1222 list_for_each_entry(link, &link_list, sibling) {
1223 struct pci_dev *child;
1224 struct pci_bus *linkbus = link->pdev->subordinate;
1225 if (link->root != root)
1226 continue;
1227 list_for_each_entry(child, &linkbus->devices, bus_list) {
1228 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
1229 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
1230 continue;
1231 pcie_aspm_check_latency(child);
1232 }
1233 }
1234}
1235
1236/* @pdev: the endpoint device */
1237void pcie_aspm_exit_link_state(struct pci_dev *pdev)
1238{
1239 struct pci_dev *parent = pdev->bus->self;
1240 struct pcie_link_state *link, *root, *parent_link;
1241
1242 if (!parent || !parent->link_state)
1243 return;
1244
1245 down_read(&pci_bus_sem);
1246 mutex_lock(&aspm_lock);
1247
1248 link = parent->link_state;
1249 root = link->root;
1250 parent_link = link->parent;
1251
1252 /*
1253 * link->downstream is a pointer to the pci_dev of function 0. If
1254 * we remove that function, the pci_dev is about to be deallocated,
1255 * so we can't use link->downstream again. Free the link state to
1256 * avoid this.
1257 *
1258 * If we're removing a non-0 function, it's possible we could
1259 * retain the link state, but PCIe r6.0, sec 7.5.3.7, recommends
1260 * programming the same ASPM Control value for all functions of
1261 * multi-function devices, so disable ASPM for all of them.
1262 */
1263 pcie_config_aspm_link(link, 0);
1264 list_del(&link->sibling);
1265 free_link_state(link);
1266
1267 /* Recheck latencies and configure upstream links */
1268 if (parent_link) {
1269 pcie_update_aspm_capable(root);
1270 pcie_config_aspm_path(parent_link);
1271 }
1272
1273 mutex_unlock(&aspm_lock);
1274 up_read(&pci_bus_sem);
1275}
1276
1277/*
1278 * @pdev: the root port or switch downstream port
1279 * @locked: whether pci_bus_sem is held
1280 */
1281void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)
1282{
1283 struct pcie_link_state *link = pdev->link_state;
1284
1285 if (aspm_disabled || !link)
1286 return;
1287 /*
1288 * Devices changed PM state, we should recheck if latency
1289 * meets all functions' requirement
1290 */
1291 if (!locked)
1292 down_read(&pci_bus_sem);
1293 mutex_lock(&aspm_lock);
1294 pcie_update_aspm_capable(link->root);
1295 pcie_config_aspm_path(link);
1296 mutex_unlock(&aspm_lock);
1297 if (!locked)
1298 up_read(&pci_bus_sem);
1299}
1300
1301void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1302{
1303 struct pcie_link_state *link = pdev->link_state;
1304
1305 if (aspm_disabled || !link)
1306 return;
1307
1308 if (aspm_policy != POLICY_POWERSAVE &&
1309 aspm_policy != POLICY_POWER_SUPERSAVE)
1310 return;
1311
1312 down_read(&pci_bus_sem);
1313 mutex_lock(&aspm_lock);
1314 pcie_config_aspm_path(link);
1315 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1316 mutex_unlock(&aspm_lock);
1317 up_read(&pci_bus_sem);
1318}
1319
1320static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1321{
1322 struct pci_dev *bridge;
1323
1324 if (!pci_is_pcie(pdev))
1325 return NULL;
1326
1327 bridge = pci_upstream_bridge(pdev);
1328 if (!bridge || !pci_is_pcie(bridge))
1329 return NULL;
1330
1331 return bridge->link_state;
1332}
1333
1334static u8 pci_calc_aspm_disable_mask(int state)
1335{
1336 state &= ~PCIE_LINK_STATE_CLKPM;
1337
1338 /* L1 PM substates require L1 */
1339 if (state & PCIE_LINK_STATE_L1)
1340 state |= PCIE_LINK_STATE_L1SS;
1341
1342 return state;
1343}
1344
1345static u8 pci_calc_aspm_enable_mask(int state)
1346{
1347 state &= ~PCIE_LINK_STATE_CLKPM;
1348
1349 /* L1 PM substates require L1 */
1350 if (state & PCIE_LINK_STATE_L1SS)
1351 state |= PCIE_LINK_STATE_L1;
1352
1353 return state;
1354}
1355
1356static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool locked)
1357{
1358 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1359
1360 if (!link)
1361 return -EINVAL;
1362 /*
1363 * A driver requested that ASPM be disabled on this device, but
1364 * if we don't have permission to manage ASPM (e.g., on ACPI
1365 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1366 * the _OSC method), we can't honor that request. Windows has
1367 * a similar mechanism using "PciASPMOptOut", which is also
1368 * ignored in this situation.
1369 */
1370 if (aspm_disabled) {
1371 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1372 return -EPERM;
1373 }
1374
1375 if (!locked)
1376 down_read(&pci_bus_sem);
1377 mutex_lock(&aspm_lock);
1378 link->aspm_disable |= pci_calc_aspm_disable_mask(state);
1379 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1380
1381 if (state & PCIE_LINK_STATE_CLKPM)
1382 link->clkpm_disable = 1;
1383 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1384 mutex_unlock(&aspm_lock);
1385 if (!locked)
1386 up_read(&pci_bus_sem);
1387
1388 return 0;
1389}
1390
1391int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1392{
1393 lockdep_assert_held_read(&pci_bus_sem);
1394
1395 return __pci_disable_link_state(pdev, state, true);
1396}
1397EXPORT_SYMBOL(pci_disable_link_state_locked);
1398
1399/**
1400 * pci_disable_link_state - Disable device's link state, so the link will
1401 * never enter specific states. Note that if the BIOS didn't grant ASPM
1402 * control to the OS, this does nothing because we can't touch the LNKCTL
1403 * register. Returns 0 or a negative errno.
1404 *
1405 * @pdev: PCI device
1406 * @state: ASPM link state to disable
1407 */
1408int pci_disable_link_state(struct pci_dev *pdev, int state)
1409{
1410 return __pci_disable_link_state(pdev, state, false);
1411}
1412EXPORT_SYMBOL(pci_disable_link_state);
1413
1414static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked)
1415{
1416 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1417
1418 if (!link)
1419 return -EINVAL;
1420 /*
1421 * A driver requested that ASPM be enabled on this device, but
1422 * if we don't have permission to manage ASPM (e.g., on ACPI
1423 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1424 * the _OSC method), we can't honor that request.
1425 */
1426 if (aspm_disabled) {
1427 pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n");
1428 return -EPERM;
1429 }
1430
1431 if (!locked)
1432 down_read(&pci_bus_sem);
1433 mutex_lock(&aspm_lock);
1434 link->aspm_default = pci_calc_aspm_enable_mask(state);
1435 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1436
1437 link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0;
1438 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1439 mutex_unlock(&aspm_lock);
1440 if (!locked)
1441 up_read(&pci_bus_sem);
1442
1443 return 0;
1444}
1445
1446/**
1447 * pci_enable_link_state - Clear and set the default device link state so that
1448 * the link may be allowed to enter the specified states. Note that if the
1449 * BIOS didn't grant ASPM control to the OS, this does nothing because we can't
1450 * touch the LNKCTL register. Also note that this does not enable states
1451 * disabled by pci_disable_link_state(). Return 0 or a negative errno.
1452 *
1453 * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1454 * PCIe r6.0, sec 5.5.4.
1455 *
1456 * @pdev: PCI device
1457 * @state: Mask of ASPM link states to enable
1458 */
1459int pci_enable_link_state(struct pci_dev *pdev, int state)
1460{
1461 return __pci_enable_link_state(pdev, state, false);
1462}
1463EXPORT_SYMBOL(pci_enable_link_state);
1464
1465/**
1466 * pci_enable_link_state_locked - Clear and set the default device link state
1467 * so that the link may be allowed to enter the specified states. Note that if
1468 * the BIOS didn't grant ASPM control to the OS, this does nothing because we
1469 * can't touch the LNKCTL register. Also note that this does not enable states
1470 * disabled by pci_disable_link_state(). Return 0 or a negative errno.
1471 *
1472 * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
1473 * PCIe r6.0, sec 5.5.4.
1474 *
1475 * @pdev: PCI device
1476 * @state: Mask of ASPM link states to enable
1477 *
1478 * Context: Caller holds pci_bus_sem read lock.
1479 */
1480int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1481{
1482 lockdep_assert_held_read(&pci_bus_sem);
1483
1484 return __pci_enable_link_state(pdev, state, true);
1485}
1486EXPORT_SYMBOL(pci_enable_link_state_locked);
1487
1488static int pcie_aspm_set_policy(const char *val,
1489 const struct kernel_param *kp)
1490{
1491 int i;
1492 struct pcie_link_state *link;
1493
1494 if (aspm_disabled)
1495 return -EPERM;
1496 i = sysfs_match_string(policy_str, val);
1497 if (i < 0)
1498 return i;
1499 if (i == aspm_policy)
1500 return 0;
1501
1502 down_read(&pci_bus_sem);
1503 mutex_lock(&aspm_lock);
1504 aspm_policy = i;
1505 list_for_each_entry(link, &link_list, sibling) {
1506 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1507 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1508 }
1509 mutex_unlock(&aspm_lock);
1510 up_read(&pci_bus_sem);
1511 return 0;
1512}
1513
1514static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1515{
1516 int i, cnt = 0;
1517 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1518 if (i == aspm_policy)
1519 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1520 else
1521 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1522 cnt += sprintf(buffer + cnt, "\n");
1523 return cnt;
1524}
1525
1526module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1527 NULL, 0644);
1528
1529/**
1530 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1531 * @pdev: Target device.
1532 *
1533 * Relies on the upstream bridge's link_state being valid. The link_state
1534 * is deallocated only when the last child of the bridge (i.e., @pdev or a
1535 * sibling) is removed, and the caller should be holding a reference to
1536 * @pdev, so this should be safe.
1537 */
1538bool pcie_aspm_enabled(struct pci_dev *pdev)
1539{
1540 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1541
1542 if (!link)
1543 return false;
1544
1545 return link->aspm_enabled;
1546}
1547EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1548
1549static ssize_t aspm_attr_show_common(struct device *dev,
1550 struct device_attribute *attr,
1551 char *buf, u8 state)
1552{
1553 struct pci_dev *pdev = to_pci_dev(dev);
1554 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1555
1556 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1557}
1558
1559static ssize_t aspm_attr_store_common(struct device *dev,
1560 struct device_attribute *attr,
1561 const char *buf, size_t len, u8 state)
1562{
1563 struct pci_dev *pdev = to_pci_dev(dev);
1564 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1565 bool state_enable;
1566
1567 if (kstrtobool(buf, &state_enable) < 0)
1568 return -EINVAL;
1569
1570 down_read(&pci_bus_sem);
1571 mutex_lock(&aspm_lock);
1572
1573 if (state_enable) {
1574 link->aspm_disable &= ~state;
1575 /* need to enable L1 for substates */
1576 if (state & PCIE_LINK_STATE_L1SS)
1577 link->aspm_disable &= ~PCIE_LINK_STATE_L1;
1578 } else {
1579 link->aspm_disable |= state;
1580 if (state & PCIE_LINK_STATE_L1)
1581 link->aspm_disable |= PCIE_LINK_STATE_L1SS;
1582 }
1583
1584 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1585
1586 mutex_unlock(&aspm_lock);
1587 up_read(&pci_bus_sem);
1588
1589 return len;
1590}
1591
1592#define ASPM_ATTR(_f, _s) \
1593static ssize_t _f##_show(struct device *dev, \
1594 struct device_attribute *attr, char *buf) \
1595{ return aspm_attr_show_common(dev, attr, buf, PCIE_LINK_STATE_##_s); } \
1596 \
1597static ssize_t _f##_store(struct device *dev, \
1598 struct device_attribute *attr, \
1599 const char *buf, size_t len) \
1600{ return aspm_attr_store_common(dev, attr, buf, len, PCIE_LINK_STATE_##_s); }
1601
1602ASPM_ATTR(l0s_aspm, L0S)
1603ASPM_ATTR(l1_aspm, L1)
1604ASPM_ATTR(l1_1_aspm, L1_1)
1605ASPM_ATTR(l1_2_aspm, L1_2)
1606ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1607ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1608
1609static ssize_t clkpm_show(struct device *dev,
1610 struct device_attribute *attr, char *buf)
1611{
1612 struct pci_dev *pdev = to_pci_dev(dev);
1613 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1614
1615 return sysfs_emit(buf, "%d\n", link->clkpm_enabled);
1616}
1617
1618static ssize_t clkpm_store(struct device *dev,
1619 struct device_attribute *attr,
1620 const char *buf, size_t len)
1621{
1622 struct pci_dev *pdev = to_pci_dev(dev);
1623 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1624 bool state_enable;
1625
1626 if (kstrtobool(buf, &state_enable) < 0)
1627 return -EINVAL;
1628
1629 down_read(&pci_bus_sem);
1630 mutex_lock(&aspm_lock);
1631
1632 link->clkpm_disable = !state_enable;
1633 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1634
1635 mutex_unlock(&aspm_lock);
1636 up_read(&pci_bus_sem);
1637
1638 return len;
1639}
1640
1641static DEVICE_ATTR_RW(clkpm);
1642static DEVICE_ATTR_RW(l0s_aspm);
1643static DEVICE_ATTR_RW(l1_aspm);
1644static DEVICE_ATTR_RW(l1_1_aspm);
1645static DEVICE_ATTR_RW(l1_2_aspm);
1646static DEVICE_ATTR_RW(l1_1_pcipm);
1647static DEVICE_ATTR_RW(l1_2_pcipm);
1648
1649static struct attribute *aspm_ctrl_attrs[] = {
1650 &dev_attr_clkpm.attr,
1651 &dev_attr_l0s_aspm.attr,
1652 &dev_attr_l1_aspm.attr,
1653 &dev_attr_l1_1_aspm.attr,
1654 &dev_attr_l1_2_aspm.attr,
1655 &dev_attr_l1_1_pcipm.attr,
1656 &dev_attr_l1_2_pcipm.attr,
1657 NULL
1658};
1659
1660static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1661 struct attribute *a, int n)
1662{
1663 struct device *dev = kobj_to_dev(kobj);
1664 struct pci_dev *pdev = to_pci_dev(dev);
1665 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1666 static const u8 aspm_state_map[] = {
1667 PCIE_LINK_STATE_L0S,
1668 PCIE_LINK_STATE_L1,
1669 PCIE_LINK_STATE_L1_1,
1670 PCIE_LINK_STATE_L1_2,
1671 PCIE_LINK_STATE_L1_1_PCIPM,
1672 PCIE_LINK_STATE_L1_2_PCIPM,
1673 };
1674
1675 if (aspm_disabled || !link)
1676 return 0;
1677
1678 if (n == 0)
1679 return link->clkpm_capable ? a->mode : 0;
1680
1681 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1682}
1683
1684const struct attribute_group aspm_ctrl_attr_group = {
1685 .name = "link",
1686 .attrs = aspm_ctrl_attrs,
1687 .is_visible = aspm_ctrl_attrs_are_visible,
1688};
1689
1690static int __init pcie_aspm_disable(char *str)
1691{
1692 if (!strcmp(str, "off")) {
1693 aspm_policy = POLICY_DEFAULT;
1694 aspm_disabled = 1;
1695 aspm_support_enabled = false;
1696 pr_info("PCIe ASPM is disabled\n");
1697 } else if (!strcmp(str, "force")) {
1698 aspm_force = 1;
1699 pr_info("PCIe ASPM is forcibly enabled\n");
1700 }
1701 return 1;
1702}
1703
1704__setup("pcie_aspm=", pcie_aspm_disable);
1705
1706void pcie_no_aspm(void)
1707{
1708 /*
1709 * Disabling ASPM is intended to prevent the kernel from modifying
1710 * existing hardware state, not to clear existing state. To that end:
1711 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1712 * (b) prevent userspace from changing policy
1713 */
1714 if (!aspm_force) {
1715 aspm_policy = POLICY_DEFAULT;
1716 aspm_disabled = 1;
1717 }
1718}
1719
1720bool pcie_aspm_support_enabled(void)
1721{
1722 return aspm_support_enabled;
1723}
1724
1725#endif /* CONFIG_PCIEASPM */