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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Enable PCIe link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/jiffies.h>
20#include <linux/delay.h>
21#include "../pci.h"
22
23#ifdef MODULE_PARAM_PREFIX
24#undef MODULE_PARAM_PREFIX
25#endif
26#define MODULE_PARAM_PREFIX "pcie_aspm."
27
28/* Note: those are not register definitions */
29#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
31#define ASPM_STATE_L1 (4) /* L1 state */
32#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
36#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
37#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
38#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
39 ASPM_STATE_L1_2_MASK)
40#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
41#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
42 ASPM_STATE_L1SS)
43
44struct aspm_latency {
45 u32 l0s; /* L0s latency (nsec) */
46 u32 l1; /* L1 latency (nsec) */
47};
48
49struct pcie_link_state {
50 struct pci_dev *pdev; /* Upstream component of the Link */
51 struct pci_dev *downstream; /* Downstream component, function 0 */
52 struct pcie_link_state *root; /* pointer to the root port link */
53 struct pcie_link_state *parent; /* pointer to the parent Link state */
54 struct list_head sibling; /* node in link_list */
55
56 /* ASPM state */
57 u32 aspm_support:7; /* Supported ASPM state */
58 u32 aspm_enabled:7; /* Enabled ASPM state */
59 u32 aspm_capable:7; /* Capable ASPM state with latency */
60 u32 aspm_default:7; /* Default ASPM state by BIOS */
61 u32 aspm_disable:7; /* Disabled ASPM state */
62
63 /* Clock PM state */
64 u32 clkpm_capable:1; /* Clock PM capable? */
65 u32 clkpm_enabled:1; /* Current Clock PM state */
66 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
67
68 /* Exit latencies */
69 struct aspm_latency latency_up; /* Upstream direction exit latency */
70 struct aspm_latency latency_dw; /* Downstream direction exit latency */
71 /*
72 * Endpoint acceptable latencies. A pcie downstream port only
73 * has one slot under it, so at most there are 8 functions.
74 */
75 struct aspm_latency acceptable[8];
76
77 /* L1 PM Substate info */
78 struct {
79 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
80 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
81 u32 ctl1; /* value to be programmed in ctl1 */
82 u32 ctl2; /* value to be programmed in ctl2 */
83 } l1ss;
84};
85
86static int aspm_disabled, aspm_force;
87static bool aspm_support_enabled = true;
88static DEFINE_MUTEX(aspm_lock);
89static LIST_HEAD(link_list);
90
91#define POLICY_DEFAULT 0 /* BIOS default setting */
92#define POLICY_PERFORMANCE 1 /* high performance */
93#define POLICY_POWERSAVE 2 /* high power saving */
94#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
95
96#ifdef CONFIG_PCIEASPM_PERFORMANCE
97static int aspm_policy = POLICY_PERFORMANCE;
98#elif defined CONFIG_PCIEASPM_POWERSAVE
99static int aspm_policy = POLICY_POWERSAVE;
100#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
101static int aspm_policy = POLICY_POWER_SUPERSAVE;
102#else
103static int aspm_policy;
104#endif
105
106static const char *policy_str[] = {
107 [POLICY_DEFAULT] = "default",
108 [POLICY_PERFORMANCE] = "performance",
109 [POLICY_POWERSAVE] = "powersave",
110 [POLICY_POWER_SUPERSAVE] = "powersupersave"
111};
112
113#define LINK_RETRAIN_TIMEOUT HZ
114
115static int policy_to_aspm_state(struct pcie_link_state *link)
116{
117 switch (aspm_policy) {
118 case POLICY_PERFORMANCE:
119 /* Disable ASPM and Clock PM */
120 return 0;
121 case POLICY_POWERSAVE:
122 /* Enable ASPM L0s/L1 */
123 return (ASPM_STATE_L0S | ASPM_STATE_L1);
124 case POLICY_POWER_SUPERSAVE:
125 /* Enable Everything */
126 return ASPM_STATE_ALL;
127 case POLICY_DEFAULT:
128 return link->aspm_default;
129 }
130 return 0;
131}
132
133static int policy_to_clkpm_state(struct pcie_link_state *link)
134{
135 switch (aspm_policy) {
136 case POLICY_PERFORMANCE:
137 /* Disable ASPM and Clock PM */
138 return 0;
139 case POLICY_POWERSAVE:
140 case POLICY_POWER_SUPERSAVE:
141 /* Enable Clock PM */
142 return 1;
143 case POLICY_DEFAULT:
144 return link->clkpm_default;
145 }
146 return 0;
147}
148
149static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
150{
151 struct pci_dev *child;
152 struct pci_bus *linkbus = link->pdev->subordinate;
153 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
154
155 list_for_each_entry(child, &linkbus->devices, bus_list)
156 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
157 PCI_EXP_LNKCTL_CLKREQ_EN,
158 val);
159 link->clkpm_enabled = !!enable;
160}
161
162static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
163{
164 /* Don't enable Clock PM if the link is not Clock PM capable */
165 if (!link->clkpm_capable)
166 enable = 0;
167 /* Need nothing if the specified equals to current state */
168 if (link->clkpm_enabled == enable)
169 return;
170 pcie_set_clkpm_nocheck(link, enable);
171}
172
173static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
174{
175 int capable = 1, enabled = 1;
176 u32 reg32;
177 u16 reg16;
178 struct pci_dev *child;
179 struct pci_bus *linkbus = link->pdev->subordinate;
180
181 /* All functions should have the same cap and state, take the worst */
182 list_for_each_entry(child, &linkbus->devices, bus_list) {
183 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
184 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
185 capable = 0;
186 enabled = 0;
187 break;
188 }
189 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
190 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
191 enabled = 0;
192 }
193 link->clkpm_enabled = enabled;
194 link->clkpm_default = enabled;
195 link->clkpm_capable = (blacklist) ? 0 : capable;
196}
197
198static bool pcie_retrain_link(struct pcie_link_state *link)
199{
200 struct pci_dev *parent = link->pdev;
201 unsigned long end_jiffies;
202 u16 reg16;
203
204 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
205 reg16 |= PCI_EXP_LNKCTL_RL;
206 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
207 if (parent->clear_retrain_link) {
208 /*
209 * Due to an erratum in some devices the Retrain Link bit
210 * needs to be cleared again manually to allow the link
211 * training to succeed.
212 */
213 reg16 &= ~PCI_EXP_LNKCTL_RL;
214 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
215 }
216
217 /* Wait for link training end. Break out after waiting for timeout */
218 end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
219 do {
220 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
221 if (!(reg16 & PCI_EXP_LNKSTA_LT))
222 break;
223 msleep(1);
224 } while (time_before(jiffies, end_jiffies));
225 return !(reg16 & PCI_EXP_LNKSTA_LT);
226}
227
228/*
229 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
230 * could use common clock. If they are, configure them to use the
231 * common clock. That will reduce the ASPM state exit latency.
232 */
233static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
234{
235 int same_clock = 1;
236 u16 reg16, parent_reg, child_reg[8];
237 struct pci_dev *child, *parent = link->pdev;
238 struct pci_bus *linkbus = parent->subordinate;
239 /*
240 * All functions of a slot should have the same Slot Clock
241 * Configuration, so just check one function
242 */
243 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
244 BUG_ON(!pci_is_pcie(child));
245
246 /* Check downstream component if bit Slot Clock Configuration is 1 */
247 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
248 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
249 same_clock = 0;
250
251 /* Check upstream component if bit Slot Clock Configuration is 1 */
252 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
253 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
254 same_clock = 0;
255
256 /* Port might be already in common clock mode */
257 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
258 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
259 bool consistent = true;
260
261 list_for_each_entry(child, &linkbus->devices, bus_list) {
262 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
263 ®16);
264 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
265 consistent = false;
266 break;
267 }
268 }
269 if (consistent)
270 return;
271 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
272 }
273
274 /* Configure downstream component, all functions */
275 list_for_each_entry(child, &linkbus->devices, bus_list) {
276 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
277 child_reg[PCI_FUNC(child->devfn)] = reg16;
278 if (same_clock)
279 reg16 |= PCI_EXP_LNKCTL_CCC;
280 else
281 reg16 &= ~PCI_EXP_LNKCTL_CCC;
282 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
283 }
284
285 /* Configure upstream component */
286 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
287 parent_reg = reg16;
288 if (same_clock)
289 reg16 |= PCI_EXP_LNKCTL_CCC;
290 else
291 reg16 &= ~PCI_EXP_LNKCTL_CCC;
292 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
293
294 if (pcie_retrain_link(link))
295 return;
296
297 /* Training failed. Restore common clock configurations */
298 pci_err(parent, "ASPM: Could not configure common clock\n");
299 list_for_each_entry(child, &linkbus->devices, bus_list)
300 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
301 child_reg[PCI_FUNC(child->devfn)]);
302 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
303}
304
305/* Convert L0s latency encoding to ns */
306static u32 calc_l0s_latency(u32 encoding)
307{
308 if (encoding == 0x7)
309 return (5 * 1000); /* > 4us */
310 return (64 << encoding);
311}
312
313/* Convert L0s acceptable latency encoding to ns */
314static u32 calc_l0s_acceptable(u32 encoding)
315{
316 if (encoding == 0x7)
317 return -1U;
318 return (64 << encoding);
319}
320
321/* Convert L1 latency encoding to ns */
322static u32 calc_l1_latency(u32 encoding)
323{
324 if (encoding == 0x7)
325 return (65 * 1000); /* > 64us */
326 return (1000 << encoding);
327}
328
329/* Convert L1 acceptable latency encoding to ns */
330static u32 calc_l1_acceptable(u32 encoding)
331{
332 if (encoding == 0x7)
333 return -1U;
334 return (1000 << encoding);
335}
336
337/* Convert L1SS T_pwr encoding to usec */
338static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
339{
340 switch (scale) {
341 case 0:
342 return val * 2;
343 case 1:
344 return val * 10;
345 case 2:
346 return val * 100;
347 }
348 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
349 return 0;
350}
351
352static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
353{
354 u32 threshold_ns = threshold_us * 1000;
355
356 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
357 if (threshold_ns < 32) {
358 *scale = 0;
359 *value = threshold_ns;
360 } else if (threshold_ns < 1024) {
361 *scale = 1;
362 *value = threshold_ns >> 5;
363 } else if (threshold_ns < 32768) {
364 *scale = 2;
365 *value = threshold_ns >> 10;
366 } else if (threshold_ns < 1048576) {
367 *scale = 3;
368 *value = threshold_ns >> 15;
369 } else if (threshold_ns < 33554432) {
370 *scale = 4;
371 *value = threshold_ns >> 20;
372 } else {
373 *scale = 5;
374 *value = threshold_ns >> 25;
375 }
376}
377
378struct aspm_register_info {
379 u32 support:2;
380 u32 enabled:2;
381 u32 latency_encoding_l0s;
382 u32 latency_encoding_l1;
383
384 /* L1 substates */
385 u32 l1ss_cap_ptr;
386 u32 l1ss_cap;
387 u32 l1ss_ctl1;
388 u32 l1ss_ctl2;
389};
390
391static void pcie_get_aspm_reg(struct pci_dev *pdev,
392 struct aspm_register_info *info)
393{
394 u16 reg16;
395 u32 reg32;
396
397 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
398 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
399 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
400 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
401 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
402 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
403
404 /* Read L1 PM substate capabilities */
405 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
406 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
407 if (!info->l1ss_cap_ptr)
408 return;
409 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
410 &info->l1ss_cap);
411 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
412 info->l1ss_cap = 0;
413 return;
414 }
415
416 /*
417 * If we don't have LTR for the entire path from the Root Complex
418 * to this device, we can't use ASPM L1.2 because it relies on the
419 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
420 */
421 if (!pdev->ltr_path)
422 info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
423
424 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
425 &info->l1ss_ctl1);
426 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
427 &info->l1ss_ctl2);
428}
429
430static void pcie_aspm_check_latency(struct pci_dev *endpoint)
431{
432 u32 latency, l1_switch_latency = 0;
433 struct aspm_latency *acceptable;
434 struct pcie_link_state *link;
435
436 /* Device not in D0 doesn't need latency check */
437 if ((endpoint->current_state != PCI_D0) &&
438 (endpoint->current_state != PCI_UNKNOWN))
439 return;
440
441 link = endpoint->bus->self->link_state;
442 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
443
444 while (link) {
445 /* Check upstream direction L0s latency */
446 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
447 (link->latency_up.l0s > acceptable->l0s))
448 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
449
450 /* Check downstream direction L0s latency */
451 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
452 (link->latency_dw.l0s > acceptable->l0s))
453 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
454 /*
455 * Check L1 latency.
456 * Every switch on the path to root complex need 1
457 * more microsecond for L1. Spec doesn't mention L0s.
458 *
459 * The exit latencies for L1 substates are not advertised
460 * by a device. Since the spec also doesn't mention a way
461 * to determine max latencies introduced by enabling L1
462 * substates on the components, it is not clear how to do
463 * a L1 substate exit latency check. We assume that the
464 * L1 exit latencies advertised by a device include L1
465 * substate latencies (and hence do not do any check).
466 */
467 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
468 if ((link->aspm_capable & ASPM_STATE_L1) &&
469 (latency + l1_switch_latency > acceptable->l1))
470 link->aspm_capable &= ~ASPM_STATE_L1;
471 l1_switch_latency += 1000;
472
473 link = link->parent;
474 }
475}
476
477/*
478 * The L1 PM substate capability is only implemented in function 0 in a
479 * multi function device.
480 */
481static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
482{
483 struct pci_dev *child;
484
485 list_for_each_entry(child, &linkbus->devices, bus_list)
486 if (PCI_FUNC(child->devfn) == 0)
487 return child;
488 return NULL;
489}
490
491/* Calculate L1.2 PM substate timing parameters */
492static void aspm_calc_l1ss_info(struct pcie_link_state *link,
493 struct aspm_register_info *upreg,
494 struct aspm_register_info *dwreg)
495{
496 u32 val1, val2, scale1, scale2;
497 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
498
499 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
500 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
501 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
502
503 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
504 return;
505
506 /* Choose the greater of the two Port Common_Mode_Restore_Times */
507 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
508 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
509 t_common_mode = max(val1, val2);
510
511 /* Choose the greater of the two Port T_POWER_ON times */
512 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
513 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
514 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
515 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
516
517 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
518 calc_l1ss_pwron(link->downstream, scale2, val2)) {
519 link->l1ss.ctl2 |= scale1 | (val1 << 3);
520 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
521 } else {
522 link->l1ss.ctl2 |= scale2 | (val2 << 3);
523 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
524 }
525
526 /*
527 * Set LTR_L1.2_THRESHOLD to the time required to transition the
528 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
529 * downstream devices report (via LTR) that they can tolerate at
530 * least that much latency.
531 *
532 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
533 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
534 * least 4us.
535 */
536 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
537 encode_l12_threshold(l1_2_threshold, &scale, &value);
538 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
539}
540
541static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
542{
543 struct pci_dev *child = link->downstream, *parent = link->pdev;
544 struct pci_bus *linkbus = parent->subordinate;
545 struct aspm_register_info upreg, dwreg;
546
547 if (blacklist) {
548 /* Set enabled/disable so that we will disable ASPM later */
549 link->aspm_enabled = ASPM_STATE_ALL;
550 link->aspm_disable = ASPM_STATE_ALL;
551 return;
552 }
553
554 /* Get upstream/downstream components' register state */
555 pcie_get_aspm_reg(parent, &upreg);
556 pcie_get_aspm_reg(child, &dwreg);
557
558 /*
559 * If ASPM not supported, don't mess with the clocks and link,
560 * bail out now.
561 */
562 if (!(upreg.support & dwreg.support))
563 return;
564
565 /* Configure common clock before checking latencies */
566 pcie_aspm_configure_common_clock(link);
567
568 /*
569 * Re-read upstream/downstream components' register state
570 * after clock configuration
571 */
572 pcie_get_aspm_reg(parent, &upreg);
573 pcie_get_aspm_reg(child, &dwreg);
574
575 /*
576 * Setup L0s state
577 *
578 * Note that we must not enable L0s in either direction on a
579 * given link unless components on both sides of the link each
580 * support L0s.
581 */
582 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
583 link->aspm_support |= ASPM_STATE_L0S;
584 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
585 link->aspm_enabled |= ASPM_STATE_L0S_UP;
586 if (upreg.enabled & PCIE_LINK_STATE_L0S)
587 link->aspm_enabled |= ASPM_STATE_L0S_DW;
588 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
589 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
590
591 /* Setup L1 state */
592 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
593 link->aspm_support |= ASPM_STATE_L1;
594 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
595 link->aspm_enabled |= ASPM_STATE_L1;
596 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
597 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
598
599 /* Setup L1 substate */
600 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
601 link->aspm_support |= ASPM_STATE_L1_1;
602 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
603 link->aspm_support |= ASPM_STATE_L1_2;
604 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
605 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
606 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
607 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
608
609 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
610 link->aspm_enabled |= ASPM_STATE_L1_1;
611 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
612 link->aspm_enabled |= ASPM_STATE_L1_2;
613 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
614 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
615 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
616 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
617
618 if (link->aspm_support & ASPM_STATE_L1SS)
619 aspm_calc_l1ss_info(link, &upreg, &dwreg);
620
621 /* Save default state */
622 link->aspm_default = link->aspm_enabled;
623
624 /* Setup initial capable state. Will be updated later */
625 link->aspm_capable = link->aspm_support;
626 /*
627 * If the downstream component has pci bridge function, don't
628 * do ASPM for now.
629 */
630 list_for_each_entry(child, &linkbus->devices, bus_list) {
631 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
632 link->aspm_disable = ASPM_STATE_ALL;
633 break;
634 }
635 }
636
637 /* Get and check endpoint acceptable latencies */
638 list_for_each_entry(child, &linkbus->devices, bus_list) {
639 u32 reg32, encoding;
640 struct aspm_latency *acceptable =
641 &link->acceptable[PCI_FUNC(child->devfn)];
642
643 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
644 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
645 continue;
646
647 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
648 /* Calculate endpoint L0s acceptable latency */
649 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
650 acceptable->l0s = calc_l0s_acceptable(encoding);
651 /* Calculate endpoint L1 acceptable latency */
652 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
653 acceptable->l1 = calc_l1_acceptable(encoding);
654
655 pcie_aspm_check_latency(child);
656 }
657}
658
659static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
660 u32 clear, u32 set)
661{
662 u32 val;
663
664 pci_read_config_dword(pdev, pos, &val);
665 val &= ~clear;
666 val |= set;
667 pci_write_config_dword(pdev, pos, val);
668}
669
670/* Configure the ASPM L1 substates */
671static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
672{
673 u32 val, enable_req;
674 struct pci_dev *child = link->downstream, *parent = link->pdev;
675 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
676 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
677
678 enable_req = (link->aspm_enabled ^ state) & state;
679
680 /*
681 * Here are the rules specified in the PCIe spec for enabling L1SS:
682 * - When enabling L1.x, enable bit at parent first, then at child
683 * - When disabling L1.x, disable bit at child first, then at parent
684 * - When enabling ASPM L1.x, need to disable L1
685 * (at child followed by parent).
686 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
687 * parameters
688 *
689 * To keep it simple, disable all L1SS bits first, and later enable
690 * what is needed.
691 */
692
693 /* Disable all L1 substates */
694 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
695 PCI_L1SS_CTL1_L1SS_MASK, 0);
696 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
697 PCI_L1SS_CTL1_L1SS_MASK, 0);
698 /*
699 * If needed, disable L1, and it gets enabled later
700 * in pcie_config_aspm_link().
701 */
702 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
703 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
704 PCI_EXP_LNKCTL_ASPM_L1, 0);
705 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
706 PCI_EXP_LNKCTL_ASPM_L1, 0);
707 }
708
709 if (enable_req & ASPM_STATE_L1_2_MASK) {
710
711 /* Program T_POWER_ON times in both ports */
712 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
713 link->l1ss.ctl2);
714 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
715 link->l1ss.ctl2);
716
717 /* Program Common_Mode_Restore_Time in upstream device */
718 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
719 PCI_L1SS_CTL1_CM_RESTORE_TIME,
720 link->l1ss.ctl1);
721
722 /* Program LTR_L1.2_THRESHOLD time in both ports */
723 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
724 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
725 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
726 link->l1ss.ctl1);
727 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
728 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
729 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
730 link->l1ss.ctl1);
731 }
732
733 val = 0;
734 if (state & ASPM_STATE_L1_1)
735 val |= PCI_L1SS_CTL1_ASPM_L1_1;
736 if (state & ASPM_STATE_L1_2)
737 val |= PCI_L1SS_CTL1_ASPM_L1_2;
738 if (state & ASPM_STATE_L1_1_PCIPM)
739 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
740 if (state & ASPM_STATE_L1_2_PCIPM)
741 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
742
743 /* Enable what we need to enable */
744 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
745 PCI_L1SS_CAP_L1_PM_SS, val);
746 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
747 PCI_L1SS_CAP_L1_PM_SS, val);
748}
749
750static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
751{
752 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
753 PCI_EXP_LNKCTL_ASPMC, val);
754}
755
756static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
757{
758 u32 upstream = 0, dwstream = 0;
759 struct pci_dev *child = link->downstream, *parent = link->pdev;
760 struct pci_bus *linkbus = parent->subordinate;
761
762 /* Enable only the states that were not explicitly disabled */
763 state &= (link->aspm_capable & ~link->aspm_disable);
764
765 /* Can't enable any substates if L1 is not enabled */
766 if (!(state & ASPM_STATE_L1))
767 state &= ~ASPM_STATE_L1SS;
768
769 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
770 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
771 state &= ~ASPM_STATE_L1_SS_PCIPM;
772 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
773 }
774
775 /* Nothing to do if the link is already in the requested state */
776 if (link->aspm_enabled == state)
777 return;
778 /* Convert ASPM state to upstream/downstream ASPM register state */
779 if (state & ASPM_STATE_L0S_UP)
780 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
781 if (state & ASPM_STATE_L0S_DW)
782 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
783 if (state & ASPM_STATE_L1) {
784 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
785 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
786 }
787
788 if (link->aspm_capable & ASPM_STATE_L1SS)
789 pcie_config_aspm_l1ss(link, state);
790
791 /*
792 * Spec 2.0 suggests all functions should be configured the
793 * same setting for ASPM. Enabling ASPM L1 should be done in
794 * upstream component first and then downstream, and vice
795 * versa for disabling ASPM L1. Spec doesn't mention L0S.
796 */
797 if (state & ASPM_STATE_L1)
798 pcie_config_aspm_dev(parent, upstream);
799 list_for_each_entry(child, &linkbus->devices, bus_list)
800 pcie_config_aspm_dev(child, dwstream);
801 if (!(state & ASPM_STATE_L1))
802 pcie_config_aspm_dev(parent, upstream);
803
804 link->aspm_enabled = state;
805}
806
807static void pcie_config_aspm_path(struct pcie_link_state *link)
808{
809 while (link) {
810 pcie_config_aspm_link(link, policy_to_aspm_state(link));
811 link = link->parent;
812 }
813}
814
815static void free_link_state(struct pcie_link_state *link)
816{
817 link->pdev->link_state = NULL;
818 kfree(link);
819}
820
821static int pcie_aspm_sanity_check(struct pci_dev *pdev)
822{
823 struct pci_dev *child;
824 u32 reg32;
825
826 /*
827 * Some functions in a slot might not all be PCIe functions,
828 * very strange. Disable ASPM for the whole slot
829 */
830 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
831 if (!pci_is_pcie(child))
832 return -EINVAL;
833
834 /*
835 * If ASPM is disabled then we're not going to change
836 * the BIOS state. It's safe to continue even if it's a
837 * pre-1.1 device
838 */
839
840 if (aspm_disabled)
841 continue;
842
843 /*
844 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
845 * RBER bit to determine if a function is 1.1 version device
846 */
847 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
848 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
849 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
850 return -EINVAL;
851 }
852 }
853 return 0;
854}
855
856static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
857{
858 struct pcie_link_state *link;
859
860 link = kzalloc(sizeof(*link), GFP_KERNEL);
861 if (!link)
862 return NULL;
863
864 INIT_LIST_HEAD(&link->sibling);
865 link->pdev = pdev;
866 link->downstream = pci_function_0(pdev->subordinate);
867
868 /*
869 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
870 * hierarchies. Note that some PCIe host implementations omit
871 * the root ports entirely, in which case a downstream port on
872 * a switch may become the root of the link state chain for all
873 * its subordinate endpoints.
874 */
875 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
876 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
877 !pdev->bus->parent->self) {
878 link->root = link;
879 } else {
880 struct pcie_link_state *parent;
881
882 parent = pdev->bus->parent->self->link_state;
883 if (!parent) {
884 kfree(link);
885 return NULL;
886 }
887
888 link->parent = parent;
889 link->root = link->parent->root;
890 }
891
892 list_add(&link->sibling, &link_list);
893 pdev->link_state = link;
894 return link;
895}
896
897/*
898 * pcie_aspm_init_link_state: Initiate PCI express link state.
899 * It is called after the pcie and its children devices are scanned.
900 * @pdev: the root port or switch downstream port
901 */
902void pcie_aspm_init_link_state(struct pci_dev *pdev)
903{
904 struct pcie_link_state *link;
905 int blacklist = !!pcie_aspm_sanity_check(pdev);
906
907 if (!aspm_support_enabled)
908 return;
909
910 if (pdev->link_state)
911 return;
912
913 /*
914 * We allocate pcie_link_state for the component on the upstream
915 * end of a Link, so there's nothing to do unless this device is
916 * downstream port.
917 */
918 if (!pcie_downstream_port(pdev))
919 return;
920
921 /* VIA has a strange chipset, root port is under a bridge */
922 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
923 pdev->bus->self)
924 return;
925
926 down_read(&pci_bus_sem);
927 if (list_empty(&pdev->subordinate->devices))
928 goto out;
929
930 mutex_lock(&aspm_lock);
931 link = alloc_pcie_link_state(pdev);
932 if (!link)
933 goto unlock;
934 /*
935 * Setup initial ASPM state. Note that we need to configure
936 * upstream links also because capable state of them can be
937 * update through pcie_aspm_cap_init().
938 */
939 pcie_aspm_cap_init(link, blacklist);
940
941 /* Setup initial Clock PM state */
942 pcie_clkpm_cap_init(link, blacklist);
943
944 /*
945 * At this stage drivers haven't had an opportunity to change the
946 * link policy setting. Enabling ASPM on broken hardware can cripple
947 * it even before the driver has had a chance to disable ASPM, so
948 * default to a safe level right now. If we're enabling ASPM beyond
949 * the BIOS's expectation, we'll do so once pci_enable_device() is
950 * called.
951 */
952 if (aspm_policy != POLICY_POWERSAVE &&
953 aspm_policy != POLICY_POWER_SUPERSAVE) {
954 pcie_config_aspm_path(link);
955 pcie_set_clkpm(link, policy_to_clkpm_state(link));
956 }
957
958unlock:
959 mutex_unlock(&aspm_lock);
960out:
961 up_read(&pci_bus_sem);
962}
963
964/* Recheck latencies and update aspm_capable for links under the root */
965static void pcie_update_aspm_capable(struct pcie_link_state *root)
966{
967 struct pcie_link_state *link;
968 BUG_ON(root->parent);
969 list_for_each_entry(link, &link_list, sibling) {
970 if (link->root != root)
971 continue;
972 link->aspm_capable = link->aspm_support;
973 }
974 list_for_each_entry(link, &link_list, sibling) {
975 struct pci_dev *child;
976 struct pci_bus *linkbus = link->pdev->subordinate;
977 if (link->root != root)
978 continue;
979 list_for_each_entry(child, &linkbus->devices, bus_list) {
980 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
981 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
982 continue;
983 pcie_aspm_check_latency(child);
984 }
985 }
986}
987
988/* @pdev: the endpoint device */
989void pcie_aspm_exit_link_state(struct pci_dev *pdev)
990{
991 struct pci_dev *parent = pdev->bus->self;
992 struct pcie_link_state *link, *root, *parent_link;
993
994 if (!parent || !parent->link_state)
995 return;
996
997 down_read(&pci_bus_sem);
998 mutex_lock(&aspm_lock);
999 /*
1000 * All PCIe functions are in one slot, remove one function will remove
1001 * the whole slot, so just wait until we are the last function left.
1002 */
1003 if (!list_empty(&parent->subordinate->devices))
1004 goto out;
1005
1006 link = parent->link_state;
1007 root = link->root;
1008 parent_link = link->parent;
1009
1010 /* All functions are removed, so just disable ASPM for the link */
1011 pcie_config_aspm_link(link, 0);
1012 list_del(&link->sibling);
1013 /* Clock PM is for endpoint device */
1014 free_link_state(link);
1015
1016 /* Recheck latencies and configure upstream links */
1017 if (parent_link) {
1018 pcie_update_aspm_capable(root);
1019 pcie_config_aspm_path(parent_link);
1020 }
1021out:
1022 mutex_unlock(&aspm_lock);
1023 up_read(&pci_bus_sem);
1024}
1025
1026/* @pdev: the root port or switch downstream port */
1027void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1028{
1029 struct pcie_link_state *link = pdev->link_state;
1030
1031 if (aspm_disabled || !link)
1032 return;
1033 /*
1034 * Devices changed PM state, we should recheck if latency
1035 * meets all functions' requirement
1036 */
1037 down_read(&pci_bus_sem);
1038 mutex_lock(&aspm_lock);
1039 pcie_update_aspm_capable(link->root);
1040 pcie_config_aspm_path(link);
1041 mutex_unlock(&aspm_lock);
1042 up_read(&pci_bus_sem);
1043}
1044
1045void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1046{
1047 struct pcie_link_state *link = pdev->link_state;
1048
1049 if (aspm_disabled || !link)
1050 return;
1051
1052 if (aspm_policy != POLICY_POWERSAVE &&
1053 aspm_policy != POLICY_POWER_SUPERSAVE)
1054 return;
1055
1056 down_read(&pci_bus_sem);
1057 mutex_lock(&aspm_lock);
1058 pcie_config_aspm_path(link);
1059 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1060 mutex_unlock(&aspm_lock);
1061 up_read(&pci_bus_sem);
1062}
1063
1064static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1065{
1066 struct pci_dev *parent = pdev->bus->self;
1067 struct pcie_link_state *link;
1068
1069 if (!pci_is_pcie(pdev))
1070 return 0;
1071
1072 if (pcie_downstream_port(pdev))
1073 parent = pdev;
1074 if (!parent || !parent->link_state)
1075 return -EINVAL;
1076
1077 /*
1078 * A driver requested that ASPM be disabled on this device, but
1079 * if we don't have permission to manage ASPM (e.g., on ACPI
1080 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1081 * the _OSC method), we can't honor that request. Windows has
1082 * a similar mechanism using "PciASPMOptOut", which is also
1083 * ignored in this situation.
1084 */
1085 if (aspm_disabled) {
1086 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1087 return -EPERM;
1088 }
1089
1090 if (sem)
1091 down_read(&pci_bus_sem);
1092 mutex_lock(&aspm_lock);
1093 link = parent->link_state;
1094 if (state & PCIE_LINK_STATE_L0S)
1095 link->aspm_disable |= ASPM_STATE_L0S;
1096 if (state & PCIE_LINK_STATE_L1)
1097 link->aspm_disable |= ASPM_STATE_L1;
1098 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1099
1100 if (state & PCIE_LINK_STATE_CLKPM) {
1101 link->clkpm_capable = 0;
1102 pcie_set_clkpm(link, 0);
1103 }
1104 mutex_unlock(&aspm_lock);
1105 if (sem)
1106 up_read(&pci_bus_sem);
1107
1108 return 0;
1109}
1110
1111int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1112{
1113 return __pci_disable_link_state(pdev, state, false);
1114}
1115EXPORT_SYMBOL(pci_disable_link_state_locked);
1116
1117/**
1118 * pci_disable_link_state - Disable device's link state, so the link will
1119 * never enter specific states. Note that if the BIOS didn't grant ASPM
1120 * control to the OS, this does nothing because we can't touch the LNKCTL
1121 * register. Returns 0 or a negative errno.
1122 *
1123 * @pdev: PCI device
1124 * @state: ASPM link state to disable
1125 */
1126int pci_disable_link_state(struct pci_dev *pdev, int state)
1127{
1128 return __pci_disable_link_state(pdev, state, true);
1129}
1130EXPORT_SYMBOL(pci_disable_link_state);
1131
1132static int pcie_aspm_set_policy(const char *val,
1133 const struct kernel_param *kp)
1134{
1135 int i;
1136 struct pcie_link_state *link;
1137
1138 if (aspm_disabled)
1139 return -EPERM;
1140 i = sysfs_match_string(policy_str, val);
1141 if (i < 0)
1142 return i;
1143 if (i == aspm_policy)
1144 return 0;
1145
1146 down_read(&pci_bus_sem);
1147 mutex_lock(&aspm_lock);
1148 aspm_policy = i;
1149 list_for_each_entry(link, &link_list, sibling) {
1150 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1151 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1152 }
1153 mutex_unlock(&aspm_lock);
1154 up_read(&pci_bus_sem);
1155 return 0;
1156}
1157
1158static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1159{
1160 int i, cnt = 0;
1161 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1162 if (i == aspm_policy)
1163 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1164 else
1165 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1166 return cnt;
1167}
1168
1169module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1170 NULL, 0644);
1171
1172/**
1173 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1174 * @pdev: Target device.
1175 */
1176bool pcie_aspm_enabled(struct pci_dev *pdev)
1177{
1178 struct pci_dev *bridge = pci_upstream_bridge(pdev);
1179 bool ret;
1180
1181 if (!bridge)
1182 return false;
1183
1184 mutex_lock(&aspm_lock);
1185 ret = bridge->link_state ? !!bridge->link_state->aspm_enabled : false;
1186 mutex_unlock(&aspm_lock);
1187
1188 return ret;
1189}
1190EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1191
1192#ifdef CONFIG_PCIEASPM_DEBUG
1193static ssize_t link_state_show(struct device *dev,
1194 struct device_attribute *attr,
1195 char *buf)
1196{
1197 struct pci_dev *pci_device = to_pci_dev(dev);
1198 struct pcie_link_state *link_state = pci_device->link_state;
1199
1200 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1201}
1202
1203static ssize_t link_state_store(struct device *dev,
1204 struct device_attribute *attr,
1205 const char *buf,
1206 size_t n)
1207{
1208 struct pci_dev *pdev = to_pci_dev(dev);
1209 struct pcie_link_state *link, *root = pdev->link_state->root;
1210 u32 state;
1211
1212 if (aspm_disabled)
1213 return -EPERM;
1214
1215 if (kstrtouint(buf, 10, &state))
1216 return -EINVAL;
1217 if ((state & ~ASPM_STATE_ALL) != 0)
1218 return -EINVAL;
1219
1220 down_read(&pci_bus_sem);
1221 mutex_lock(&aspm_lock);
1222 list_for_each_entry(link, &link_list, sibling) {
1223 if (link->root != root)
1224 continue;
1225 pcie_config_aspm_link(link, state);
1226 }
1227 mutex_unlock(&aspm_lock);
1228 up_read(&pci_bus_sem);
1229 return n;
1230}
1231
1232static ssize_t clk_ctl_show(struct device *dev,
1233 struct device_attribute *attr,
1234 char *buf)
1235{
1236 struct pci_dev *pci_device = to_pci_dev(dev);
1237 struct pcie_link_state *link_state = pci_device->link_state;
1238
1239 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1240}
1241
1242static ssize_t clk_ctl_store(struct device *dev,
1243 struct device_attribute *attr,
1244 const char *buf,
1245 size_t n)
1246{
1247 struct pci_dev *pdev = to_pci_dev(dev);
1248 bool state;
1249
1250 if (strtobool(buf, &state))
1251 return -EINVAL;
1252
1253 down_read(&pci_bus_sem);
1254 mutex_lock(&aspm_lock);
1255 pcie_set_clkpm_nocheck(pdev->link_state, state);
1256 mutex_unlock(&aspm_lock);
1257 up_read(&pci_bus_sem);
1258
1259 return n;
1260}
1261
1262static DEVICE_ATTR_RW(link_state);
1263static DEVICE_ATTR_RW(clk_ctl);
1264
1265static char power_group[] = "power";
1266void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1267{
1268 struct pcie_link_state *link_state = pdev->link_state;
1269
1270 if (!link_state)
1271 return;
1272
1273 if (link_state->aspm_support)
1274 sysfs_add_file_to_group(&pdev->dev.kobj,
1275 &dev_attr_link_state.attr, power_group);
1276 if (link_state->clkpm_capable)
1277 sysfs_add_file_to_group(&pdev->dev.kobj,
1278 &dev_attr_clk_ctl.attr, power_group);
1279}
1280
1281void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1282{
1283 struct pcie_link_state *link_state = pdev->link_state;
1284
1285 if (!link_state)
1286 return;
1287
1288 if (link_state->aspm_support)
1289 sysfs_remove_file_from_group(&pdev->dev.kobj,
1290 &dev_attr_link_state.attr, power_group);
1291 if (link_state->clkpm_capable)
1292 sysfs_remove_file_from_group(&pdev->dev.kobj,
1293 &dev_attr_clk_ctl.attr, power_group);
1294}
1295#endif
1296
1297static int __init pcie_aspm_disable(char *str)
1298{
1299 if (!strcmp(str, "off")) {
1300 aspm_policy = POLICY_DEFAULT;
1301 aspm_disabled = 1;
1302 aspm_support_enabled = false;
1303 printk(KERN_INFO "PCIe ASPM is disabled\n");
1304 } else if (!strcmp(str, "force")) {
1305 aspm_force = 1;
1306 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1307 }
1308 return 1;
1309}
1310
1311__setup("pcie_aspm=", pcie_aspm_disable);
1312
1313void pcie_no_aspm(void)
1314{
1315 /*
1316 * Disabling ASPM is intended to prevent the kernel from modifying
1317 * existing hardware state, not to clear existing state. To that end:
1318 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1319 * (b) prevent userspace from changing policy
1320 */
1321 if (!aspm_force) {
1322 aspm_policy = POLICY_DEFAULT;
1323 aspm_disabled = 1;
1324 }
1325}
1326
1327bool pcie_aspm_support_enabled(void)
1328{
1329 return aspm_support_enabled;
1330}
1331EXPORT_SYMBOL(pcie_aspm_support_enabled);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Enable PCIe link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/bitfield.h>
11#include <linux/kernel.h>
12#include <linux/limits.h>
13#include <linux/math.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/pci.h>
17#include <linux/pci_regs.h>
18#include <linux/errno.h>
19#include <linux/pm.h>
20#include <linux/init.h>
21#include <linux/printk.h>
22#include <linux/slab.h>
23#include <linux/time.h>
24
25#include "../pci.h"
26
27void pci_save_ltr_state(struct pci_dev *dev)
28{
29 int ltr;
30 struct pci_cap_saved_state *save_state;
31 u32 *cap;
32
33 if (!pci_is_pcie(dev))
34 return;
35
36 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
37 if (!ltr)
38 return;
39
40 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
41 if (!save_state) {
42 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
43 return;
44 }
45
46 /* Some broken devices only support dword access to LTR */
47 cap = &save_state->cap.data[0];
48 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
49}
50
51void pci_restore_ltr_state(struct pci_dev *dev)
52{
53 struct pci_cap_saved_state *save_state;
54 int ltr;
55 u32 *cap;
56
57 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
58 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
59 if (!save_state || !ltr)
60 return;
61
62 /* Some broken devices only support dword access to LTR */
63 cap = &save_state->cap.data[0];
64 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
65}
66
67void pci_configure_aspm_l1ss(struct pci_dev *pdev)
68{
69 int rc;
70
71 pdev->l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
72
73 rc = pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_L1SS,
74 2 * sizeof(u32));
75 if (rc)
76 pci_err(pdev, "unable to allocate ASPM L1SS save buffer (%pe)\n",
77 ERR_PTR(rc));
78}
79
80void pci_save_aspm_l1ss_state(struct pci_dev *pdev)
81{
82 struct pci_cap_saved_state *save_state;
83 u16 l1ss = pdev->l1ss;
84 u32 *cap;
85
86 /*
87 * Save L1 substate configuration. The ASPM L0s/L1 configuration
88 * in PCI_EXP_LNKCTL_ASPMC is saved by pci_save_pcie_state().
89 */
90 if (!l1ss)
91 return;
92
93 save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
94 if (!save_state)
95 return;
96
97 cap = &save_state->cap.data[0];
98 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL2, cap++);
99 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, cap++);
100}
101
102void pci_restore_aspm_l1ss_state(struct pci_dev *pdev)
103{
104 struct pci_cap_saved_state *pl_save_state, *cl_save_state;
105 struct pci_dev *parent = pdev->bus->self;
106 u32 *cap, pl_ctl1, pl_ctl2, pl_l1_2_enable;
107 u32 cl_ctl1, cl_ctl2, cl_l1_2_enable;
108 u16 clnkctl, plnkctl;
109
110 /*
111 * In case BIOS enabled L1.2 when resuming, we need to disable it first
112 * on the downstream component before the upstream. So, don't attempt to
113 * restore either until we are at the downstream component.
114 */
115 if (pcie_downstream_port(pdev) || !parent)
116 return;
117
118 if (!pdev->l1ss || !parent->l1ss)
119 return;
120
121 cl_save_state = pci_find_saved_ext_cap(pdev, PCI_EXT_CAP_ID_L1SS);
122 pl_save_state = pci_find_saved_ext_cap(parent, PCI_EXT_CAP_ID_L1SS);
123 if (!cl_save_state || !pl_save_state)
124 return;
125
126 cap = &cl_save_state->cap.data[0];
127 cl_ctl2 = *cap++;
128 cl_ctl1 = *cap;
129 cap = &pl_save_state->cap.data[0];
130 pl_ctl2 = *cap++;
131 pl_ctl1 = *cap;
132
133 /* Make sure L0s/L1 are disabled before updating L1SS config */
134 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &clnkctl);
135 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &plnkctl);
136 if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, clnkctl) ||
137 FIELD_GET(PCI_EXP_LNKCTL_ASPMC, plnkctl)) {
138 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL,
139 clnkctl & ~PCI_EXP_LNKCTL_ASPMC);
140 pcie_capability_write_word(parent, PCI_EXP_LNKCTL,
141 plnkctl & ~PCI_EXP_LNKCTL_ASPMC);
142 }
143
144 /*
145 * Disable L1.2 on this downstream endpoint device first, followed
146 * by the upstream
147 */
148 pci_clear_and_set_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
149 PCI_L1SS_CTL1_L1_2_MASK, 0);
150 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
151 PCI_L1SS_CTL1_L1_2_MASK, 0);
152
153 /*
154 * In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD
155 * in PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
156 * enable bits, even though they're all in PCI_L1SS_CTL1.
157 */
158 pl_l1_2_enable = pl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
159 pl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
160 cl_l1_2_enable = cl_ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
161 cl_ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
162
163 /* Write back without enables first (above we cleared them in ctl1) */
164 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, pl_ctl2);
165 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL2, cl_ctl2);
166 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, pl_ctl1);
167 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1, cl_ctl1);
168
169 /* Then write back the enables */
170 if (pl_l1_2_enable || cl_l1_2_enable) {
171 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
172 pl_ctl1 | pl_l1_2_enable);
173 pci_write_config_dword(pdev, pdev->l1ss + PCI_L1SS_CTL1,
174 cl_ctl1 | cl_l1_2_enable);
175 }
176
177 /* Restore L0s/L1 if they were enabled */
178 if (FIELD_GET(PCI_EXP_LNKCTL_ASPMC, clnkctl) ||
179 FIELD_GET(PCI_EXP_LNKCTL_ASPMC, plnkctl)) {
180 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, plnkctl);
181 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, clnkctl);
182 }
183}
184
185#ifdef CONFIG_PCIEASPM
186
187#ifdef MODULE_PARAM_PREFIX
188#undef MODULE_PARAM_PREFIX
189#endif
190#define MODULE_PARAM_PREFIX "pcie_aspm."
191
192/* Note: those are not register definitions */
193#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
194#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
195#define ASPM_STATE_L1 (4) /* L1 state */
196#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
197#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
198#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
199#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
200#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
201#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
202#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
203 ASPM_STATE_L1_2_MASK)
204#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
205#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
206 ASPM_STATE_L1SS)
207
208struct pcie_link_state {
209 struct pci_dev *pdev; /* Upstream component of the Link */
210 struct pci_dev *downstream; /* Downstream component, function 0 */
211 struct pcie_link_state *root; /* pointer to the root port link */
212 struct pcie_link_state *parent; /* pointer to the parent Link state */
213 struct list_head sibling; /* node in link_list */
214
215 /* ASPM state */
216 u32 aspm_support:7; /* Supported ASPM state */
217 u32 aspm_enabled:7; /* Enabled ASPM state */
218 u32 aspm_capable:7; /* Capable ASPM state with latency */
219 u32 aspm_default:7; /* Default ASPM state by BIOS */
220 u32 aspm_disable:7; /* Disabled ASPM state */
221
222 /* Clock PM state */
223 u32 clkpm_capable:1; /* Clock PM capable? */
224 u32 clkpm_enabled:1; /* Current Clock PM state */
225 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
226 u32 clkpm_disable:1; /* Clock PM disabled */
227};
228
229static int aspm_disabled, aspm_force;
230static bool aspm_support_enabled = true;
231static DEFINE_MUTEX(aspm_lock);
232static LIST_HEAD(link_list);
233
234#define POLICY_DEFAULT 0 /* BIOS default setting */
235#define POLICY_PERFORMANCE 1 /* high performance */
236#define POLICY_POWERSAVE 2 /* high power saving */
237#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
238
239#ifdef CONFIG_PCIEASPM_PERFORMANCE
240static int aspm_policy = POLICY_PERFORMANCE;
241#elif defined CONFIG_PCIEASPM_POWERSAVE
242static int aspm_policy = POLICY_POWERSAVE;
243#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
244static int aspm_policy = POLICY_POWER_SUPERSAVE;
245#else
246static int aspm_policy;
247#endif
248
249static const char *policy_str[] = {
250 [POLICY_DEFAULT] = "default",
251 [POLICY_PERFORMANCE] = "performance",
252 [POLICY_POWERSAVE] = "powersave",
253 [POLICY_POWER_SUPERSAVE] = "powersupersave"
254};
255
256/*
257 * The L1 PM substate capability is only implemented in function 0 in a
258 * multi function device.
259 */
260static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
261{
262 struct pci_dev *child;
263
264 list_for_each_entry(child, &linkbus->devices, bus_list)
265 if (PCI_FUNC(child->devfn) == 0)
266 return child;
267 return NULL;
268}
269
270static int policy_to_aspm_state(struct pcie_link_state *link)
271{
272 switch (aspm_policy) {
273 case POLICY_PERFORMANCE:
274 /* Disable ASPM and Clock PM */
275 return 0;
276 case POLICY_POWERSAVE:
277 /* Enable ASPM L0s/L1 */
278 return (ASPM_STATE_L0S | ASPM_STATE_L1);
279 case POLICY_POWER_SUPERSAVE:
280 /* Enable Everything */
281 return ASPM_STATE_ALL;
282 case POLICY_DEFAULT:
283 return link->aspm_default;
284 }
285 return 0;
286}
287
288static int policy_to_clkpm_state(struct pcie_link_state *link)
289{
290 switch (aspm_policy) {
291 case POLICY_PERFORMANCE:
292 /* Disable ASPM and Clock PM */
293 return 0;
294 case POLICY_POWERSAVE:
295 case POLICY_POWER_SUPERSAVE:
296 /* Enable Clock PM */
297 return 1;
298 case POLICY_DEFAULT:
299 return link->clkpm_default;
300 }
301 return 0;
302}
303
304static void pci_update_aspm_saved_state(struct pci_dev *dev)
305{
306 struct pci_cap_saved_state *save_state;
307 u16 *cap, lnkctl, aspm_ctl;
308
309 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
310 if (!save_state)
311 return;
312
313 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl);
314
315 /*
316 * Update ASPM and CLKREQ bits of LNKCTL in save_state. We only
317 * write PCI_EXP_LNKCTL_CCC during enumeration, so it shouldn't
318 * change after being captured in save_state.
319 */
320 aspm_ctl = lnkctl & (PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN);
321 lnkctl &= ~(PCI_EXP_LNKCTL_ASPMC | PCI_EXP_LNKCTL_CLKREQ_EN);
322
323 /* Depends on pci_save_pcie_state(): cap[1] is LNKCTL */
324 cap = (u16 *)&save_state->cap.data[0];
325 cap[1] = lnkctl | aspm_ctl;
326}
327
328static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
329{
330 struct pci_dev *child;
331 struct pci_bus *linkbus = link->pdev->subordinate;
332 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
333
334 list_for_each_entry(child, &linkbus->devices, bus_list) {
335 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
336 PCI_EXP_LNKCTL_CLKREQ_EN,
337 val);
338 pci_update_aspm_saved_state(child);
339 }
340 link->clkpm_enabled = !!enable;
341}
342
343static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
344{
345 /*
346 * Don't enable Clock PM if the link is not Clock PM capable
347 * or Clock PM is disabled
348 */
349 if (!link->clkpm_capable || link->clkpm_disable)
350 enable = 0;
351 /* Need nothing if the specified equals to current state */
352 if (link->clkpm_enabled == enable)
353 return;
354 pcie_set_clkpm_nocheck(link, enable);
355}
356
357static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
358{
359 int capable = 1, enabled = 1;
360 u32 reg32;
361 u16 reg16;
362 struct pci_dev *child;
363 struct pci_bus *linkbus = link->pdev->subordinate;
364
365 /* All functions should have the same cap and state, take the worst */
366 list_for_each_entry(child, &linkbus->devices, bus_list) {
367 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
368 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
369 capable = 0;
370 enabled = 0;
371 break;
372 }
373 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
374 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
375 enabled = 0;
376 }
377 link->clkpm_enabled = enabled;
378 link->clkpm_default = enabled;
379 link->clkpm_capable = capable;
380 link->clkpm_disable = blacklist ? 1 : 0;
381}
382
383/*
384 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
385 * could use common clock. If they are, configure them to use the
386 * common clock. That will reduce the ASPM state exit latency.
387 */
388static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
389{
390 int same_clock = 1;
391 u16 reg16, ccc, parent_old_ccc, child_old_ccc[8];
392 struct pci_dev *child, *parent = link->pdev;
393 struct pci_bus *linkbus = parent->subordinate;
394 /*
395 * All functions of a slot should have the same Slot Clock
396 * Configuration, so just check one function
397 */
398 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
399 BUG_ON(!pci_is_pcie(child));
400
401 /* Check downstream component if bit Slot Clock Configuration is 1 */
402 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
403 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
404 same_clock = 0;
405
406 /* Check upstream component if bit Slot Clock Configuration is 1 */
407 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
408 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
409 same_clock = 0;
410
411 /* Port might be already in common clock mode */
412 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
413 parent_old_ccc = reg16 & PCI_EXP_LNKCTL_CCC;
414 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
415 bool consistent = true;
416
417 list_for_each_entry(child, &linkbus->devices, bus_list) {
418 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
419 ®16);
420 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
421 consistent = false;
422 break;
423 }
424 }
425 if (consistent)
426 return;
427 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
428 }
429
430 ccc = same_clock ? PCI_EXP_LNKCTL_CCC : 0;
431 /* Configure downstream component, all functions */
432 list_for_each_entry(child, &linkbus->devices, bus_list) {
433 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
434 child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC;
435 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
436 PCI_EXP_LNKCTL_CCC, ccc);
437 }
438
439 /* Configure upstream component */
440 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
441 PCI_EXP_LNKCTL_CCC, ccc);
442
443 if (pcie_retrain_link(link->pdev, true)) {
444
445 /* Training failed. Restore common clock configurations */
446 pci_err(parent, "ASPM: Could not configure common clock\n");
447 list_for_each_entry(child, &linkbus->devices, bus_list)
448 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
449 PCI_EXP_LNKCTL_CCC,
450 child_old_ccc[PCI_FUNC(child->devfn)]);
451 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
452 PCI_EXP_LNKCTL_CCC, parent_old_ccc);
453 }
454}
455
456/* Convert L0s latency encoding to ns */
457static u32 calc_l0s_latency(u32 lnkcap)
458{
459 u32 encoding = FIELD_GET(PCI_EXP_LNKCAP_L0SEL, lnkcap);
460
461 if (encoding == 0x7)
462 return 5 * NSEC_PER_USEC; /* > 4us */
463 return (64 << encoding);
464}
465
466/* Convert L0s acceptable latency encoding to ns */
467static u32 calc_l0s_acceptable(u32 encoding)
468{
469 if (encoding == 0x7)
470 return U32_MAX;
471 return (64 << encoding);
472}
473
474/* Convert L1 latency encoding to ns */
475static u32 calc_l1_latency(u32 lnkcap)
476{
477 u32 encoding = FIELD_GET(PCI_EXP_LNKCAP_L1EL, lnkcap);
478
479 if (encoding == 0x7)
480 return 65 * NSEC_PER_USEC; /* > 64us */
481 return NSEC_PER_USEC << encoding;
482}
483
484/* Convert L1 acceptable latency encoding to ns */
485static u32 calc_l1_acceptable(u32 encoding)
486{
487 if (encoding == 0x7)
488 return U32_MAX;
489 return NSEC_PER_USEC << encoding;
490}
491
492/* Convert L1SS T_pwr encoding to usec */
493static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val)
494{
495 switch (scale) {
496 case 0:
497 return val * 2;
498 case 1:
499 return val * 10;
500 case 2:
501 return val * 100;
502 }
503 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
504 return 0;
505}
506
507/*
508 * Encode an LTR_L1.2_THRESHOLD value for the L1 PM Substates Control 1
509 * register. Ports enter L1.2 when the most recent LTR value is greater
510 * than or equal to LTR_L1.2_THRESHOLD, so we round up to make sure we
511 * don't enter L1.2 too aggressively.
512 *
513 * See PCIe r6.0, sec 5.5.1, 6.18, 7.8.3.3.
514 */
515static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
516{
517 u64 threshold_ns = (u64)threshold_us * NSEC_PER_USEC;
518
519 /*
520 * LTR_L1.2_THRESHOLD_Value ("value") is a 10-bit field with max
521 * value of 0x3ff.
522 */
523 if (threshold_ns <= 1 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
524 *scale = 0; /* Value times 1ns */
525 *value = threshold_ns;
526 } else if (threshold_ns <= 32 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
527 *scale = 1; /* Value times 32ns */
528 *value = roundup(threshold_ns, 32) / 32;
529 } else if (threshold_ns <= 1024 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
530 *scale = 2; /* Value times 1024ns */
531 *value = roundup(threshold_ns, 1024) / 1024;
532 } else if (threshold_ns <= 32768 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
533 *scale = 3; /* Value times 32768ns */
534 *value = roundup(threshold_ns, 32768) / 32768;
535 } else if (threshold_ns <= 1048576 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
536 *scale = 4; /* Value times 1048576ns */
537 *value = roundup(threshold_ns, 1048576) / 1048576;
538 } else if (threshold_ns <= (u64)33554432 * FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE)) {
539 *scale = 5; /* Value times 33554432ns */
540 *value = roundup(threshold_ns, 33554432) / 33554432;
541 } else {
542 *scale = 5;
543 *value = FIELD_MAX(PCI_L1SS_CTL1_LTR_L12_TH_VALUE);
544 }
545}
546
547static void pcie_aspm_check_latency(struct pci_dev *endpoint)
548{
549 u32 latency, encoding, lnkcap_up, lnkcap_dw;
550 u32 l1_switch_latency = 0, latency_up_l0s;
551 u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
552 u32 acceptable_l0s, acceptable_l1;
553 struct pcie_link_state *link;
554
555 /* Device not in D0 doesn't need latency check */
556 if ((endpoint->current_state != PCI_D0) &&
557 (endpoint->current_state != PCI_UNKNOWN))
558 return;
559
560 link = endpoint->bus->self->link_state;
561
562 /* Calculate endpoint L0s acceptable latency */
563 encoding = FIELD_GET(PCI_EXP_DEVCAP_L0S, endpoint->devcap);
564 acceptable_l0s = calc_l0s_acceptable(encoding);
565
566 /* Calculate endpoint L1 acceptable latency */
567 encoding = FIELD_GET(PCI_EXP_DEVCAP_L1, endpoint->devcap);
568 acceptable_l1 = calc_l1_acceptable(encoding);
569
570 while (link) {
571 struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
572
573 /* Read direction exit latencies */
574 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
575 &lnkcap_up);
576 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
577 &lnkcap_dw);
578 latency_up_l0s = calc_l0s_latency(lnkcap_up);
579 latency_up_l1 = calc_l1_latency(lnkcap_up);
580 latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
581 latency_dw_l1 = calc_l1_latency(lnkcap_dw);
582
583 /* Check upstream direction L0s latency */
584 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
585 (latency_up_l0s > acceptable_l0s))
586 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
587
588 /* Check downstream direction L0s latency */
589 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
590 (latency_dw_l0s > acceptable_l0s))
591 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
592 /*
593 * Check L1 latency.
594 * Every switch on the path to root complex need 1
595 * more microsecond for L1. Spec doesn't mention L0s.
596 *
597 * The exit latencies for L1 substates are not advertised
598 * by a device. Since the spec also doesn't mention a way
599 * to determine max latencies introduced by enabling L1
600 * substates on the components, it is not clear how to do
601 * a L1 substate exit latency check. We assume that the
602 * L1 exit latencies advertised by a device include L1
603 * substate latencies (and hence do not do any check).
604 */
605 latency = max_t(u32, latency_up_l1, latency_dw_l1);
606 if ((link->aspm_capable & ASPM_STATE_L1) &&
607 (latency + l1_switch_latency > acceptable_l1))
608 link->aspm_capable &= ~ASPM_STATE_L1;
609 l1_switch_latency += NSEC_PER_USEC;
610
611 link = link->parent;
612 }
613}
614
615/* Calculate L1.2 PM substate timing parameters */
616static void aspm_calc_l12_info(struct pcie_link_state *link,
617 u32 parent_l1ss_cap, u32 child_l1ss_cap)
618{
619 struct pci_dev *child = link->downstream, *parent = link->pdev;
620 u32 val1, val2, scale1, scale2;
621 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
622 u32 ctl1 = 0, ctl2 = 0;
623 u32 pctl1, pctl2, cctl1, cctl2;
624 u32 pl1_2_enables, cl1_2_enables;
625
626 /* Choose the greater of the two Port Common_Mode_Restore_Times */
627 val1 = FIELD_GET(PCI_L1SS_CAP_CM_RESTORE_TIME, parent_l1ss_cap);
628 val2 = FIELD_GET(PCI_L1SS_CAP_CM_RESTORE_TIME, child_l1ss_cap);
629 t_common_mode = max(val1, val2);
630
631 /* Choose the greater of the two Port T_POWER_ON times */
632 val1 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_VALUE, parent_l1ss_cap);
633 scale1 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_SCALE, parent_l1ss_cap);
634 val2 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_VALUE, child_l1ss_cap);
635 scale2 = FIELD_GET(PCI_L1SS_CAP_P_PWR_ON_SCALE, child_l1ss_cap);
636
637 if (calc_l12_pwron(parent, scale1, val1) >
638 calc_l12_pwron(child, scale2, val2)) {
639 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale1) |
640 FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_VALUE, val1);
641 t_power_on = calc_l12_pwron(parent, scale1, val1);
642 } else {
643 ctl2 |= FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_SCALE, scale2) |
644 FIELD_PREP(PCI_L1SS_CTL2_T_PWR_ON_VALUE, val2);
645 t_power_on = calc_l12_pwron(child, scale2, val2);
646 }
647
648 /*
649 * Set LTR_L1.2_THRESHOLD to the time required to transition the
650 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
651 * downstream devices report (via LTR) that they can tolerate at
652 * least that much latency.
653 *
654 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
655 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
656 * least 4us.
657 */
658 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
659 encode_l12_threshold(l1_2_threshold, &scale, &value);
660 ctl1 |= FIELD_PREP(PCI_L1SS_CTL1_CM_RESTORE_TIME, t_common_mode) |
661 FIELD_PREP(PCI_L1SS_CTL1_LTR_L12_TH_VALUE, value) |
662 FIELD_PREP(PCI_L1SS_CTL1_LTR_L12_TH_SCALE, scale);
663
664 /* Some broken devices only support dword access to L1 SS */
665 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
666 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
667 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
668 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
669
670 if (ctl1 == pctl1 && ctl1 == cctl1 &&
671 ctl2 == pctl2 && ctl2 == cctl2)
672 return;
673
674 /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
675 pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
676 cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
677
678 if (pl1_2_enables || cl1_2_enables) {
679 pci_clear_and_set_config_dword(child,
680 child->l1ss + PCI_L1SS_CTL1,
681 PCI_L1SS_CTL1_L1_2_MASK, 0);
682 pci_clear_and_set_config_dword(parent,
683 parent->l1ss + PCI_L1SS_CTL1,
684 PCI_L1SS_CTL1_L1_2_MASK, 0);
685 }
686
687 /* Program T_POWER_ON times in both ports */
688 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
689 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
690
691 /* Program Common_Mode_Restore_Time in upstream device */
692 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
693 PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
694
695 /* Program LTR_L1.2_THRESHOLD time in both ports */
696 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
697 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
698 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
699 ctl1);
700 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
701 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
702 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
703 ctl1);
704
705 if (pl1_2_enables || cl1_2_enables) {
706 pci_clear_and_set_config_dword(parent,
707 parent->l1ss + PCI_L1SS_CTL1, 0,
708 pl1_2_enables);
709 pci_clear_and_set_config_dword(child,
710 child->l1ss + PCI_L1SS_CTL1, 0,
711 cl1_2_enables);
712 }
713}
714
715static void aspm_l1ss_init(struct pcie_link_state *link)
716{
717 struct pci_dev *child = link->downstream, *parent = link->pdev;
718 u32 parent_l1ss_cap, child_l1ss_cap;
719 u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
720
721 if (!parent->l1ss || !child->l1ss)
722 return;
723
724 /* Setup L1 substate */
725 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
726 &parent_l1ss_cap);
727 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
728 &child_l1ss_cap);
729
730 if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
731 parent_l1ss_cap = 0;
732 if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
733 child_l1ss_cap = 0;
734
735 /*
736 * If we don't have LTR for the entire path from the Root Complex
737 * to this device, we can't use ASPM L1.2 because it relies on the
738 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
739 */
740 if (!child->ltr_path)
741 child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
742
743 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
744 link->aspm_support |= ASPM_STATE_L1_1;
745 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
746 link->aspm_support |= ASPM_STATE_L1_2;
747 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
748 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
749 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
750 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
751
752 if (parent_l1ss_cap)
753 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
754 &parent_l1ss_ctl1);
755 if (child_l1ss_cap)
756 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
757 &child_l1ss_ctl1);
758
759 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
760 link->aspm_enabled |= ASPM_STATE_L1_1;
761 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
762 link->aspm_enabled |= ASPM_STATE_L1_2;
763 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
764 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
765 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
766 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
767
768 if (link->aspm_support & ASPM_STATE_L1_2_MASK)
769 aspm_calc_l12_info(link, parent_l1ss_cap, child_l1ss_cap);
770}
771
772static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
773{
774 struct pci_dev *child = link->downstream, *parent = link->pdev;
775 u32 parent_lnkcap, child_lnkcap;
776 u16 parent_lnkctl, child_lnkctl;
777 struct pci_bus *linkbus = parent->subordinate;
778
779 if (blacklist) {
780 /* Set enabled/disable so that we will disable ASPM later */
781 link->aspm_enabled = ASPM_STATE_ALL;
782 link->aspm_disable = ASPM_STATE_ALL;
783 return;
784 }
785
786 /*
787 * If ASPM not supported, don't mess with the clocks and link,
788 * bail out now.
789 */
790 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
791 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
792 if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
793 return;
794
795 /* Configure common clock before checking latencies */
796 pcie_aspm_configure_common_clock(link);
797
798 /*
799 * Re-read upstream/downstream components' register state after
800 * clock configuration. L0s & L1 exit latencies in the otherwise
801 * read-only Link Capabilities may change depending on common clock
802 * configuration (PCIe r5.0, sec 7.5.3.6).
803 */
804 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
805 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
806 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
807 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
808
809 /*
810 * Setup L0s state
811 *
812 * Note that we must not enable L0s in either direction on a
813 * given link unless components on both sides of the link each
814 * support L0s.
815 */
816 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
817 link->aspm_support |= ASPM_STATE_L0S;
818
819 if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
820 link->aspm_enabled |= ASPM_STATE_L0S_UP;
821 if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
822 link->aspm_enabled |= ASPM_STATE_L0S_DW;
823
824 /* Setup L1 state */
825 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
826 link->aspm_support |= ASPM_STATE_L1;
827
828 if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
829 link->aspm_enabled |= ASPM_STATE_L1;
830
831 aspm_l1ss_init(link);
832
833 /* Save default state */
834 link->aspm_default = link->aspm_enabled;
835
836 /* Setup initial capable state. Will be updated later */
837 link->aspm_capable = link->aspm_support;
838
839 /* Get and check endpoint acceptable latencies */
840 list_for_each_entry(child, &linkbus->devices, bus_list) {
841 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
842 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
843 continue;
844
845 pcie_aspm_check_latency(child);
846 }
847}
848
849/* Configure the ASPM L1 substates */
850static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
851{
852 u32 val, enable_req;
853 struct pci_dev *child = link->downstream, *parent = link->pdev;
854
855 enable_req = (link->aspm_enabled ^ state) & state;
856
857 /*
858 * Here are the rules specified in the PCIe spec for enabling L1SS:
859 * - When enabling L1.x, enable bit at parent first, then at child
860 * - When disabling L1.x, disable bit at child first, then at parent
861 * - When enabling ASPM L1.x, need to disable L1
862 * (at child followed by parent).
863 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
864 * parameters
865 *
866 * To keep it simple, disable all L1SS bits first, and later enable
867 * what is needed.
868 */
869
870 /* Disable all L1 substates */
871 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
872 PCI_L1SS_CTL1_L1SS_MASK, 0);
873 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
874 PCI_L1SS_CTL1_L1SS_MASK, 0);
875 /*
876 * If needed, disable L1, and it gets enabled later
877 * in pcie_config_aspm_link().
878 */
879 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
880 pcie_capability_clear_word(child, PCI_EXP_LNKCTL,
881 PCI_EXP_LNKCTL_ASPM_L1);
882 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
883 PCI_EXP_LNKCTL_ASPM_L1);
884 }
885
886 val = 0;
887 if (state & ASPM_STATE_L1_1)
888 val |= PCI_L1SS_CTL1_ASPM_L1_1;
889 if (state & ASPM_STATE_L1_2)
890 val |= PCI_L1SS_CTL1_ASPM_L1_2;
891 if (state & ASPM_STATE_L1_1_PCIPM)
892 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
893 if (state & ASPM_STATE_L1_2_PCIPM)
894 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
895
896 /* Enable what we need to enable */
897 pci_clear_and_set_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
898 PCI_L1SS_CTL1_L1SS_MASK, val);
899 pci_clear_and_set_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
900 PCI_L1SS_CTL1_L1SS_MASK, val);
901}
902
903static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
904{
905 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
906 PCI_EXP_LNKCTL_ASPMC, val);
907}
908
909static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
910{
911 u32 upstream = 0, dwstream = 0;
912 struct pci_dev *child = link->downstream, *parent = link->pdev;
913 struct pci_bus *linkbus = parent->subordinate;
914
915 /* Enable only the states that were not explicitly disabled */
916 state &= (link->aspm_capable & ~link->aspm_disable);
917
918 /* Can't enable any substates if L1 is not enabled */
919 if (!(state & ASPM_STATE_L1))
920 state &= ~ASPM_STATE_L1SS;
921
922 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
923 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
924 state &= ~ASPM_STATE_L1_SS_PCIPM;
925 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
926 }
927
928 /* Nothing to do if the link is already in the requested state */
929 if (link->aspm_enabled == state)
930 return;
931 /* Convert ASPM state to upstream/downstream ASPM register state */
932 if (state & ASPM_STATE_L0S_UP)
933 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
934 if (state & ASPM_STATE_L0S_DW)
935 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
936 if (state & ASPM_STATE_L1) {
937 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
938 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
939 }
940
941 if (link->aspm_capable & ASPM_STATE_L1SS)
942 pcie_config_aspm_l1ss(link, state);
943
944 /*
945 * Spec 2.0 suggests all functions should be configured the
946 * same setting for ASPM. Enabling ASPM L1 should be done in
947 * upstream component first and then downstream, and vice
948 * versa for disabling ASPM L1. Spec doesn't mention L0S.
949 */
950 if (state & ASPM_STATE_L1)
951 pcie_config_aspm_dev(parent, upstream);
952 list_for_each_entry(child, &linkbus->devices, bus_list)
953 pcie_config_aspm_dev(child, dwstream);
954 if (!(state & ASPM_STATE_L1))
955 pcie_config_aspm_dev(parent, upstream);
956
957 link->aspm_enabled = state;
958
959 /* Update latest ASPM configuration in saved context */
960 pci_save_aspm_l1ss_state(link->downstream);
961 pci_update_aspm_saved_state(link->downstream);
962 pci_save_aspm_l1ss_state(parent);
963 pci_update_aspm_saved_state(parent);
964}
965
966static void pcie_config_aspm_path(struct pcie_link_state *link)
967{
968 while (link) {
969 pcie_config_aspm_link(link, policy_to_aspm_state(link));
970 link = link->parent;
971 }
972}
973
974static void free_link_state(struct pcie_link_state *link)
975{
976 link->pdev->link_state = NULL;
977 kfree(link);
978}
979
980static int pcie_aspm_sanity_check(struct pci_dev *pdev)
981{
982 struct pci_dev *child;
983 u32 reg32;
984
985 /*
986 * Some functions in a slot might not all be PCIe functions,
987 * very strange. Disable ASPM for the whole slot
988 */
989 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
990 if (!pci_is_pcie(child))
991 return -EINVAL;
992
993 /*
994 * If ASPM is disabled then we're not going to change
995 * the BIOS state. It's safe to continue even if it's a
996 * pre-1.1 device
997 */
998
999 if (aspm_disabled)
1000 continue;
1001
1002 /*
1003 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
1004 * RBER bit to determine if a function is 1.1 version device
1005 */
1006 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
1007 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
1008 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
1009 return -EINVAL;
1010 }
1011 }
1012 return 0;
1013}
1014
1015static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
1016{
1017 struct pcie_link_state *link;
1018
1019 link = kzalloc(sizeof(*link), GFP_KERNEL);
1020 if (!link)
1021 return NULL;
1022
1023 INIT_LIST_HEAD(&link->sibling);
1024 link->pdev = pdev;
1025 link->downstream = pci_function_0(pdev->subordinate);
1026
1027 /*
1028 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
1029 * hierarchies. Note that some PCIe host implementations omit
1030 * the root ports entirely, in which case a downstream port on
1031 * a switch may become the root of the link state chain for all
1032 * its subordinate endpoints.
1033 */
1034 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
1035 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
1036 !pdev->bus->parent->self) {
1037 link->root = link;
1038 } else {
1039 struct pcie_link_state *parent;
1040
1041 parent = pdev->bus->parent->self->link_state;
1042 if (!parent) {
1043 kfree(link);
1044 return NULL;
1045 }
1046
1047 link->parent = parent;
1048 link->root = link->parent->root;
1049 }
1050
1051 list_add(&link->sibling, &link_list);
1052 pdev->link_state = link;
1053 return link;
1054}
1055
1056static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
1057{
1058 struct pci_dev *child;
1059
1060 list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
1061 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
1062}
1063
1064/*
1065 * pcie_aspm_init_link_state: Initiate PCI express link state.
1066 * It is called after the pcie and its children devices are scanned.
1067 * @pdev: the root port or switch downstream port
1068 */
1069void pcie_aspm_init_link_state(struct pci_dev *pdev)
1070{
1071 struct pcie_link_state *link;
1072 int blacklist = !!pcie_aspm_sanity_check(pdev);
1073
1074 if (!aspm_support_enabled)
1075 return;
1076
1077 if (pdev->link_state)
1078 return;
1079
1080 /*
1081 * We allocate pcie_link_state for the component on the upstream
1082 * end of a Link, so there's nothing to do unless this device is
1083 * downstream port.
1084 */
1085 if (!pcie_downstream_port(pdev))
1086 return;
1087
1088 /* VIA has a strange chipset, root port is under a bridge */
1089 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
1090 pdev->bus->self)
1091 return;
1092
1093 down_read(&pci_bus_sem);
1094 if (list_empty(&pdev->subordinate->devices))
1095 goto out;
1096
1097 mutex_lock(&aspm_lock);
1098 link = alloc_pcie_link_state(pdev);
1099 if (!link)
1100 goto unlock;
1101 /*
1102 * Setup initial ASPM state. Note that we need to configure
1103 * upstream links also because capable state of them can be
1104 * update through pcie_aspm_cap_init().
1105 */
1106 pcie_aspm_cap_init(link, blacklist);
1107
1108 /* Setup initial Clock PM state */
1109 pcie_clkpm_cap_init(link, blacklist);
1110
1111 /*
1112 * At this stage drivers haven't had an opportunity to change the
1113 * link policy setting. Enabling ASPM on broken hardware can cripple
1114 * it even before the driver has had a chance to disable ASPM, so
1115 * default to a safe level right now. If we're enabling ASPM beyond
1116 * the BIOS's expectation, we'll do so once pci_enable_device() is
1117 * called.
1118 */
1119 if (aspm_policy != POLICY_POWERSAVE &&
1120 aspm_policy != POLICY_POWER_SUPERSAVE) {
1121 pcie_config_aspm_path(link);
1122 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1123 }
1124
1125 pcie_aspm_update_sysfs_visibility(pdev);
1126
1127unlock:
1128 mutex_unlock(&aspm_lock);
1129out:
1130 up_read(&pci_bus_sem);
1131}
1132
1133void pci_bridge_reconfigure_ltr(struct pci_dev *pdev)
1134{
1135 struct pci_dev *bridge;
1136 u32 ctl;
1137
1138 bridge = pci_upstream_bridge(pdev);
1139 if (bridge && bridge->ltr_path) {
1140 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1141 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1142 pci_dbg(bridge, "re-enabling LTR\n");
1143 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1144 PCI_EXP_DEVCTL2_LTR_EN);
1145 }
1146 }
1147}
1148
1149void pci_configure_ltr(struct pci_dev *pdev)
1150{
1151 struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
1152 struct pci_dev *bridge;
1153 u32 cap, ctl;
1154
1155 if (!pci_is_pcie(pdev))
1156 return;
1157
1158 pcie_capability_read_dword(pdev, PCI_EXP_DEVCAP2, &cap);
1159 if (!(cap & PCI_EXP_DEVCAP2_LTR))
1160 return;
1161
1162 pcie_capability_read_dword(pdev, PCI_EXP_DEVCTL2, &ctl);
1163 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
1164 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
1165 pdev->ltr_path = 1;
1166 return;
1167 }
1168
1169 bridge = pci_upstream_bridge(pdev);
1170 if (bridge && bridge->ltr_path)
1171 pdev->ltr_path = 1;
1172
1173 return;
1174 }
1175
1176 if (!host->native_ltr)
1177 return;
1178
1179 /*
1180 * Software must not enable LTR in an Endpoint unless the Root
1181 * Complex and all intermediate Switches indicate support for LTR.
1182 * PCIe r4.0, sec 6.18.
1183 */
1184 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) {
1185 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
1186 PCI_EXP_DEVCTL2_LTR_EN);
1187 pdev->ltr_path = 1;
1188 return;
1189 }
1190
1191 /*
1192 * If we're configuring a hot-added device, LTR was likely
1193 * disabled in the upstream bridge, so re-enable it before enabling
1194 * it in the new device.
1195 */
1196 bridge = pci_upstream_bridge(pdev);
1197 if (bridge && bridge->ltr_path) {
1198 pci_bridge_reconfigure_ltr(pdev);
1199 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
1200 PCI_EXP_DEVCTL2_LTR_EN);
1201 pdev->ltr_path = 1;
1202 }
1203}
1204
1205/* Recheck latencies and update aspm_capable for links under the root */
1206static void pcie_update_aspm_capable(struct pcie_link_state *root)
1207{
1208 struct pcie_link_state *link;
1209 BUG_ON(root->parent);
1210 list_for_each_entry(link, &link_list, sibling) {
1211 if (link->root != root)
1212 continue;
1213 link->aspm_capable = link->aspm_support;
1214 }
1215 list_for_each_entry(link, &link_list, sibling) {
1216 struct pci_dev *child;
1217 struct pci_bus *linkbus = link->pdev->subordinate;
1218 if (link->root != root)
1219 continue;
1220 list_for_each_entry(child, &linkbus->devices, bus_list) {
1221 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
1222 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
1223 continue;
1224 pcie_aspm_check_latency(child);
1225 }
1226 }
1227}
1228
1229/* @pdev: the endpoint device */
1230void pcie_aspm_exit_link_state(struct pci_dev *pdev)
1231{
1232 struct pci_dev *parent = pdev->bus->self;
1233 struct pcie_link_state *link, *root, *parent_link;
1234
1235 if (!parent || !parent->link_state)
1236 return;
1237
1238 down_read(&pci_bus_sem);
1239 mutex_lock(&aspm_lock);
1240
1241 link = parent->link_state;
1242 root = link->root;
1243 parent_link = link->parent;
1244
1245 /*
1246 * link->downstream is a pointer to the pci_dev of function 0. If
1247 * we remove that function, the pci_dev is about to be deallocated,
1248 * so we can't use link->downstream again. Free the link state to
1249 * avoid this.
1250 *
1251 * If we're removing a non-0 function, it's possible we could
1252 * retain the link state, but PCIe r6.0, sec 7.5.3.7, recommends
1253 * programming the same ASPM Control value for all functions of
1254 * multi-function devices, so disable ASPM for all of them.
1255 */
1256 pcie_config_aspm_link(link, 0);
1257 list_del(&link->sibling);
1258 free_link_state(link);
1259
1260 /* Recheck latencies and configure upstream links */
1261 if (parent_link) {
1262 pcie_update_aspm_capable(root);
1263 pcie_config_aspm_path(parent_link);
1264 }
1265
1266 mutex_unlock(&aspm_lock);
1267 up_read(&pci_bus_sem);
1268}
1269
1270/*
1271 * @pdev: the root port or switch downstream port
1272 * @locked: whether pci_bus_sem is held
1273 */
1274void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked)
1275{
1276 struct pcie_link_state *link = pdev->link_state;
1277
1278 if (aspm_disabled || !link)
1279 return;
1280 /*
1281 * Devices changed PM state, we should recheck if latency
1282 * meets all functions' requirement
1283 */
1284 if (!locked)
1285 down_read(&pci_bus_sem);
1286 mutex_lock(&aspm_lock);
1287 pcie_update_aspm_capable(link->root);
1288 pcie_config_aspm_path(link);
1289 mutex_unlock(&aspm_lock);
1290 if (!locked)
1291 up_read(&pci_bus_sem);
1292}
1293
1294void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1295{
1296 struct pcie_link_state *link = pdev->link_state;
1297
1298 if (aspm_disabled || !link)
1299 return;
1300
1301 if (aspm_policy != POLICY_POWERSAVE &&
1302 aspm_policy != POLICY_POWER_SUPERSAVE)
1303 return;
1304
1305 down_read(&pci_bus_sem);
1306 mutex_lock(&aspm_lock);
1307 pcie_config_aspm_path(link);
1308 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1309 mutex_unlock(&aspm_lock);
1310 up_read(&pci_bus_sem);
1311}
1312
1313static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1314{
1315 struct pci_dev *bridge;
1316
1317 if (!pci_is_pcie(pdev))
1318 return NULL;
1319
1320 bridge = pci_upstream_bridge(pdev);
1321 if (!bridge || !pci_is_pcie(bridge))
1322 return NULL;
1323
1324 return bridge->link_state;
1325}
1326
1327static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool locked)
1328{
1329 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1330
1331 if (!link)
1332 return -EINVAL;
1333 /*
1334 * A driver requested that ASPM be disabled on this device, but
1335 * if we don't have permission to manage ASPM (e.g., on ACPI
1336 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1337 * the _OSC method), we can't honor that request. Windows has
1338 * a similar mechanism using "PciASPMOptOut", which is also
1339 * ignored in this situation.
1340 */
1341 if (aspm_disabled) {
1342 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1343 return -EPERM;
1344 }
1345
1346 if (!locked)
1347 down_read(&pci_bus_sem);
1348 mutex_lock(&aspm_lock);
1349 if (state & PCIE_LINK_STATE_L0S)
1350 link->aspm_disable |= ASPM_STATE_L0S;
1351 if (state & PCIE_LINK_STATE_L1)
1352 /* L1 PM substates require L1 */
1353 link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
1354 if (state & PCIE_LINK_STATE_L1_1)
1355 link->aspm_disable |= ASPM_STATE_L1_1;
1356 if (state & PCIE_LINK_STATE_L1_2)
1357 link->aspm_disable |= ASPM_STATE_L1_2;
1358 if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1359 link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
1360 if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1361 link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
1362 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1363
1364 if (state & PCIE_LINK_STATE_CLKPM)
1365 link->clkpm_disable = 1;
1366 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1367 mutex_unlock(&aspm_lock);
1368 if (!locked)
1369 up_read(&pci_bus_sem);
1370
1371 return 0;
1372}
1373
1374int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1375{
1376 lockdep_assert_held_read(&pci_bus_sem);
1377
1378 return __pci_disable_link_state(pdev, state, true);
1379}
1380EXPORT_SYMBOL(pci_disable_link_state_locked);
1381
1382/**
1383 * pci_disable_link_state - Disable device's link state, so the link will
1384 * never enter specific states. Note that if the BIOS didn't grant ASPM
1385 * control to the OS, this does nothing because we can't touch the LNKCTL
1386 * register. Returns 0 or a negative errno.
1387 *
1388 * @pdev: PCI device
1389 * @state: ASPM link state to disable
1390 */
1391int pci_disable_link_state(struct pci_dev *pdev, int state)
1392{
1393 return __pci_disable_link_state(pdev, state, false);
1394}
1395EXPORT_SYMBOL(pci_disable_link_state);
1396
1397static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked)
1398{
1399 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1400
1401 if (!link)
1402 return -EINVAL;
1403 /*
1404 * A driver requested that ASPM be enabled on this device, but
1405 * if we don't have permission to manage ASPM (e.g., on ACPI
1406 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1407 * the _OSC method), we can't honor that request.
1408 */
1409 if (aspm_disabled) {
1410 pci_warn(pdev, "can't override BIOS ASPM; OS doesn't have ASPM control\n");
1411 return -EPERM;
1412 }
1413
1414 if (!locked)
1415 down_read(&pci_bus_sem);
1416 mutex_lock(&aspm_lock);
1417 link->aspm_default = 0;
1418 if (state & PCIE_LINK_STATE_L0S)
1419 link->aspm_default |= ASPM_STATE_L0S;
1420 if (state & PCIE_LINK_STATE_L1)
1421 link->aspm_default |= ASPM_STATE_L1;
1422 /* L1 PM substates require L1 */
1423 if (state & PCIE_LINK_STATE_L1_1)
1424 link->aspm_default |= ASPM_STATE_L1_1 | ASPM_STATE_L1;
1425 if (state & PCIE_LINK_STATE_L1_2)
1426 link->aspm_default |= ASPM_STATE_L1_2 | ASPM_STATE_L1;
1427 if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1428 link->aspm_default |= ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1;
1429 if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1430 link->aspm_default |= ASPM_STATE_L1_2_PCIPM | ASPM_STATE_L1;
1431 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1432
1433 link->clkpm_default = (state & PCIE_LINK_STATE_CLKPM) ? 1 : 0;
1434 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1435 mutex_unlock(&aspm_lock);
1436 if (!locked)
1437 up_read(&pci_bus_sem);
1438
1439 return 0;
1440}
1441
1442/**
1443 * pci_enable_link_state - Clear and set the default device link state so that
1444 * the link may be allowed to enter the specified states. Note that if the
1445 * BIOS didn't grant ASPM control to the OS, this does nothing because we can't
1446 * touch the LNKCTL register. Also note that this does not enable states
1447 * disabled by pci_disable_link_state(). Return 0 or a negative errno.
1448 *
1449 * @pdev: PCI device
1450 * @state: Mask of ASPM link states to enable
1451 */
1452int pci_enable_link_state(struct pci_dev *pdev, int state)
1453{
1454 return __pci_enable_link_state(pdev, state, false);
1455}
1456EXPORT_SYMBOL(pci_enable_link_state);
1457
1458/**
1459 * pci_enable_link_state_locked - Clear and set the default device link state
1460 * so that the link may be allowed to enter the specified states. Note that if
1461 * the BIOS didn't grant ASPM control to the OS, this does nothing because we
1462 * can't touch the LNKCTL register. Also note that this does not enable states
1463 * disabled by pci_disable_link_state(). Return 0 or a negative errno.
1464 *
1465 * @pdev: PCI device
1466 * @state: Mask of ASPM link states to enable
1467 *
1468 * Context: Caller holds pci_bus_sem read lock.
1469 */
1470int pci_enable_link_state_locked(struct pci_dev *pdev, int state)
1471{
1472 lockdep_assert_held_read(&pci_bus_sem);
1473
1474 return __pci_enable_link_state(pdev, state, true);
1475}
1476EXPORT_SYMBOL(pci_enable_link_state_locked);
1477
1478static int pcie_aspm_set_policy(const char *val,
1479 const struct kernel_param *kp)
1480{
1481 int i;
1482 struct pcie_link_state *link;
1483
1484 if (aspm_disabled)
1485 return -EPERM;
1486 i = sysfs_match_string(policy_str, val);
1487 if (i < 0)
1488 return i;
1489 if (i == aspm_policy)
1490 return 0;
1491
1492 down_read(&pci_bus_sem);
1493 mutex_lock(&aspm_lock);
1494 aspm_policy = i;
1495 list_for_each_entry(link, &link_list, sibling) {
1496 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1497 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1498 }
1499 mutex_unlock(&aspm_lock);
1500 up_read(&pci_bus_sem);
1501 return 0;
1502}
1503
1504static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1505{
1506 int i, cnt = 0;
1507 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1508 if (i == aspm_policy)
1509 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1510 else
1511 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1512 cnt += sprintf(buffer + cnt, "\n");
1513 return cnt;
1514}
1515
1516module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1517 NULL, 0644);
1518
1519/**
1520 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1521 * @pdev: Target device.
1522 *
1523 * Relies on the upstream bridge's link_state being valid. The link_state
1524 * is deallocated only when the last child of the bridge (i.e., @pdev or a
1525 * sibling) is removed, and the caller should be holding a reference to
1526 * @pdev, so this should be safe.
1527 */
1528bool pcie_aspm_enabled(struct pci_dev *pdev)
1529{
1530 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1531
1532 if (!link)
1533 return false;
1534
1535 return link->aspm_enabled;
1536}
1537EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1538
1539static ssize_t aspm_attr_show_common(struct device *dev,
1540 struct device_attribute *attr,
1541 char *buf, u8 state)
1542{
1543 struct pci_dev *pdev = to_pci_dev(dev);
1544 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1545
1546 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1547}
1548
1549static ssize_t aspm_attr_store_common(struct device *dev,
1550 struct device_attribute *attr,
1551 const char *buf, size_t len, u8 state)
1552{
1553 struct pci_dev *pdev = to_pci_dev(dev);
1554 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1555 bool state_enable;
1556
1557 if (kstrtobool(buf, &state_enable) < 0)
1558 return -EINVAL;
1559
1560 down_read(&pci_bus_sem);
1561 mutex_lock(&aspm_lock);
1562
1563 if (state_enable) {
1564 link->aspm_disable &= ~state;
1565 /* need to enable L1 for substates */
1566 if (state & ASPM_STATE_L1SS)
1567 link->aspm_disable &= ~ASPM_STATE_L1;
1568 } else {
1569 link->aspm_disable |= state;
1570 if (state & ASPM_STATE_L1)
1571 link->aspm_disable |= ASPM_STATE_L1SS;
1572 }
1573
1574 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1575
1576 mutex_unlock(&aspm_lock);
1577 up_read(&pci_bus_sem);
1578
1579 return len;
1580}
1581
1582#define ASPM_ATTR(_f, _s) \
1583static ssize_t _f##_show(struct device *dev, \
1584 struct device_attribute *attr, char *buf) \
1585{ return aspm_attr_show_common(dev, attr, buf, ASPM_STATE_##_s); } \
1586 \
1587static ssize_t _f##_store(struct device *dev, \
1588 struct device_attribute *attr, \
1589 const char *buf, size_t len) \
1590{ return aspm_attr_store_common(dev, attr, buf, len, ASPM_STATE_##_s); }
1591
1592ASPM_ATTR(l0s_aspm, L0S)
1593ASPM_ATTR(l1_aspm, L1)
1594ASPM_ATTR(l1_1_aspm, L1_1)
1595ASPM_ATTR(l1_2_aspm, L1_2)
1596ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1597ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1598
1599static ssize_t clkpm_show(struct device *dev,
1600 struct device_attribute *attr, char *buf)
1601{
1602 struct pci_dev *pdev = to_pci_dev(dev);
1603 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1604
1605 return sysfs_emit(buf, "%d\n", link->clkpm_enabled);
1606}
1607
1608static ssize_t clkpm_store(struct device *dev,
1609 struct device_attribute *attr,
1610 const char *buf, size_t len)
1611{
1612 struct pci_dev *pdev = to_pci_dev(dev);
1613 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1614 bool state_enable;
1615
1616 if (kstrtobool(buf, &state_enable) < 0)
1617 return -EINVAL;
1618
1619 down_read(&pci_bus_sem);
1620 mutex_lock(&aspm_lock);
1621
1622 link->clkpm_disable = !state_enable;
1623 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1624
1625 mutex_unlock(&aspm_lock);
1626 up_read(&pci_bus_sem);
1627
1628 return len;
1629}
1630
1631static DEVICE_ATTR_RW(clkpm);
1632static DEVICE_ATTR_RW(l0s_aspm);
1633static DEVICE_ATTR_RW(l1_aspm);
1634static DEVICE_ATTR_RW(l1_1_aspm);
1635static DEVICE_ATTR_RW(l1_2_aspm);
1636static DEVICE_ATTR_RW(l1_1_pcipm);
1637static DEVICE_ATTR_RW(l1_2_pcipm);
1638
1639static struct attribute *aspm_ctrl_attrs[] = {
1640 &dev_attr_clkpm.attr,
1641 &dev_attr_l0s_aspm.attr,
1642 &dev_attr_l1_aspm.attr,
1643 &dev_attr_l1_1_aspm.attr,
1644 &dev_attr_l1_2_aspm.attr,
1645 &dev_attr_l1_1_pcipm.attr,
1646 &dev_attr_l1_2_pcipm.attr,
1647 NULL
1648};
1649
1650static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1651 struct attribute *a, int n)
1652{
1653 struct device *dev = kobj_to_dev(kobj);
1654 struct pci_dev *pdev = to_pci_dev(dev);
1655 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1656 static const u8 aspm_state_map[] = {
1657 ASPM_STATE_L0S,
1658 ASPM_STATE_L1,
1659 ASPM_STATE_L1_1,
1660 ASPM_STATE_L1_2,
1661 ASPM_STATE_L1_1_PCIPM,
1662 ASPM_STATE_L1_2_PCIPM,
1663 };
1664
1665 if (aspm_disabled || !link)
1666 return 0;
1667
1668 if (n == 0)
1669 return link->clkpm_capable ? a->mode : 0;
1670
1671 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1672}
1673
1674const struct attribute_group aspm_ctrl_attr_group = {
1675 .name = "link",
1676 .attrs = aspm_ctrl_attrs,
1677 .is_visible = aspm_ctrl_attrs_are_visible,
1678};
1679
1680static int __init pcie_aspm_disable(char *str)
1681{
1682 if (!strcmp(str, "off")) {
1683 aspm_policy = POLICY_DEFAULT;
1684 aspm_disabled = 1;
1685 aspm_support_enabled = false;
1686 pr_info("PCIe ASPM is disabled\n");
1687 } else if (!strcmp(str, "force")) {
1688 aspm_force = 1;
1689 pr_info("PCIe ASPM is forcibly enabled\n");
1690 }
1691 return 1;
1692}
1693
1694__setup("pcie_aspm=", pcie_aspm_disable);
1695
1696void pcie_no_aspm(void)
1697{
1698 /*
1699 * Disabling ASPM is intended to prevent the kernel from modifying
1700 * existing hardware state, not to clear existing state. To that end:
1701 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1702 * (b) prevent userspace from changing policy
1703 */
1704 if (!aspm_force) {
1705 aspm_policy = POLICY_DEFAULT;
1706 aspm_disabled = 1;
1707 }
1708}
1709
1710bool pcie_aspm_support_enabled(void)
1711{
1712 return aspm_support_enabled;
1713}
1714
1715#endif /* CONFIG_PCIEASPM */