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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include "amdgpu_ctx.h"
32
33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
37#include <linux/rbtree.h>
38#include <linux/hashtable.h>
39#include <linux/dma-fence.h>
40
41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
46
47#include <drm/amdgpu_drm.h>
48#include <drm/drm_gem.h>
49#include <drm/drm_ioctl.h>
50#include <drm/gpu_scheduler.h>
51
52#include <kgd_kfd_interface.h>
53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
55
56#include "amd_shared.h"
57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
61#include "amdgpu_ttm.h"
62#include "amdgpu_psp.h"
63#include "amdgpu_gds.h"
64#include "amdgpu_sync.h"
65#include "amdgpu_ring.h"
66#include "amdgpu_vm.h"
67#include "amdgpu_dpm.h"
68#include "amdgpu_acp.h"
69#include "amdgpu_uvd.h"
70#include "amdgpu_vce.h"
71#include "amdgpu_vcn.h"
72#include "amdgpu_mn.h"
73#include "amdgpu_gmc.h"
74#include "amdgpu_gfx.h"
75#include "amdgpu_sdma.h"
76#include "amdgpu_dm.h"
77#include "amdgpu_virt.h"
78#include "amdgpu_csa.h"
79#include "amdgpu_gart.h"
80#include "amdgpu_debugfs.h"
81#include "amdgpu_job.h"
82#include "amdgpu_bo_list.h"
83#include "amdgpu_gem.h"
84#include "amdgpu_doorbell.h"
85#include "amdgpu_amdkfd.h"
86#include "amdgpu_smu.h"
87#include "amdgpu_discovery.h"
88#include "amdgpu_mes.h"
89#include "amdgpu_umc.h"
90#include "amdgpu_mmhub.h"
91
92#define MAX_GPU_INSTANCE 16
93
94struct amdgpu_gpu_instance
95{
96 struct amdgpu_device *adev;
97 int mgpu_fan_enabled;
98};
99
100struct amdgpu_mgpu_info
101{
102 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
103 struct mutex mutex;
104 uint32_t num_gpu;
105 uint32_t num_dgpu;
106 uint32_t num_apu;
107};
108
109/*
110 * Modules parameters.
111 */
112extern int amdgpu_modeset;
113extern int amdgpu_vram_limit;
114extern int amdgpu_vis_vram_limit;
115extern int amdgpu_gart_size;
116extern int amdgpu_gtt_size;
117extern int amdgpu_moverate;
118extern int amdgpu_benchmarking;
119extern int amdgpu_testing;
120extern int amdgpu_audio;
121extern int amdgpu_disp_priority;
122extern int amdgpu_hw_i2c;
123extern int amdgpu_pcie_gen2;
124extern int amdgpu_msi;
125extern int amdgpu_dpm;
126extern int amdgpu_fw_load_type;
127extern int amdgpu_aspm;
128extern int amdgpu_runtime_pm;
129extern uint amdgpu_ip_block_mask;
130extern int amdgpu_bapm;
131extern int amdgpu_deep_color;
132extern int amdgpu_vm_size;
133extern int amdgpu_vm_block_size;
134extern int amdgpu_vm_fragment_size;
135extern int amdgpu_vm_fault_stop;
136extern int amdgpu_vm_debug;
137extern int amdgpu_vm_update_mode;
138extern int amdgpu_dc;
139extern int amdgpu_sched_jobs;
140extern int amdgpu_sched_hw_submission;
141extern uint amdgpu_pcie_gen_cap;
142extern uint amdgpu_pcie_lane_cap;
143extern uint amdgpu_cg_mask;
144extern uint amdgpu_pg_mask;
145extern uint amdgpu_sdma_phase_quantum;
146extern char *amdgpu_disable_cu;
147extern char *amdgpu_virtual_display;
148extern uint amdgpu_pp_feature_mask;
149extern int amdgpu_ngg;
150extern int amdgpu_prim_buf_per_se;
151extern int amdgpu_pos_buf_per_se;
152extern int amdgpu_cntl_sb_buf_per_se;
153extern int amdgpu_param_buf_per_se;
154extern int amdgpu_job_hang_limit;
155extern int amdgpu_lbpw;
156extern int amdgpu_compute_multipipe;
157extern int amdgpu_gpu_recovery;
158extern int amdgpu_emu_mode;
159extern uint amdgpu_smu_memory_pool_size;
160extern uint amdgpu_dc_feature_mask;
161extern uint amdgpu_dm_abm_level;
162extern struct amdgpu_mgpu_info mgpu_info;
163extern int amdgpu_ras_enable;
164extern uint amdgpu_ras_mask;
165extern int amdgpu_async_gfx_ring;
166extern int amdgpu_mcbp;
167extern int amdgpu_discovery;
168extern int amdgpu_mes;
169extern int amdgpu_noretry;
170
171#ifdef CONFIG_DRM_AMDGPU_SI
172extern int amdgpu_si_support;
173#endif
174#ifdef CONFIG_DRM_AMDGPU_CIK
175extern int amdgpu_cik_support;
176#endif
177
178#define AMDGPU_VM_MAX_NUM_CTX 4096
179#define AMDGPU_SG_THRESHOLD (256*1024*1024)
180#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
181#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
182#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
183#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
184/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
185#define AMDGPU_IB_POOL_SIZE 16
186#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
187#define AMDGPUFB_CONN_LIMIT 4
188#define AMDGPU_BIOS_NUM_SCRATCH 16
189
190/* hard reset data */
191#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
192
193/* reset flags */
194#define AMDGPU_RESET_GFX (1 << 0)
195#define AMDGPU_RESET_COMPUTE (1 << 1)
196#define AMDGPU_RESET_DMA (1 << 2)
197#define AMDGPU_RESET_CP (1 << 3)
198#define AMDGPU_RESET_GRBM (1 << 4)
199#define AMDGPU_RESET_DMA1 (1 << 5)
200#define AMDGPU_RESET_RLC (1 << 6)
201#define AMDGPU_RESET_SEM (1 << 7)
202#define AMDGPU_RESET_IH (1 << 8)
203#define AMDGPU_RESET_VMC (1 << 9)
204#define AMDGPU_RESET_MC (1 << 10)
205#define AMDGPU_RESET_DISPLAY (1 << 11)
206#define AMDGPU_RESET_UVD (1 << 12)
207#define AMDGPU_RESET_VCE (1 << 13)
208#define AMDGPU_RESET_VCE1 (1 << 14)
209
210/* max cursor sizes (in pixels) */
211#define CIK_CURSOR_WIDTH 128
212#define CIK_CURSOR_HEIGHT 128
213
214struct amdgpu_device;
215struct amdgpu_ib;
216struct amdgpu_cs_parser;
217struct amdgpu_job;
218struct amdgpu_irq_src;
219struct amdgpu_fpriv;
220struct amdgpu_bo_va_mapping;
221struct amdgpu_atif;
222struct kfd_vm_fault_info;
223
224enum amdgpu_cp_irq {
225 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
226 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
227 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
228 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
229 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
230 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
231 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
232 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
233 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
234 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
235
236 AMDGPU_CP_IRQ_LAST
237};
238
239enum amdgpu_thermal_irq {
240 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
241 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
242
243 AMDGPU_THERMAL_IRQ_LAST
244};
245
246enum amdgpu_kiq_irq {
247 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
248 AMDGPU_CP_KIQ_IRQ_LAST
249};
250
251#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
252#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
253#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
254
255int amdgpu_device_ip_set_clockgating_state(void *dev,
256 enum amd_ip_block_type block_type,
257 enum amd_clockgating_state state);
258int amdgpu_device_ip_set_powergating_state(void *dev,
259 enum amd_ip_block_type block_type,
260 enum amd_powergating_state state);
261void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
262 u32 *flags);
263int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
264 enum amd_ip_block_type block_type);
265bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
266 enum amd_ip_block_type block_type);
267
268#define AMDGPU_MAX_IP_NUM 16
269
270struct amdgpu_ip_block_status {
271 bool valid;
272 bool sw;
273 bool hw;
274 bool late_initialized;
275 bool hang;
276};
277
278struct amdgpu_ip_block_version {
279 const enum amd_ip_block_type type;
280 const u32 major;
281 const u32 minor;
282 const u32 rev;
283 const struct amd_ip_funcs *funcs;
284};
285
286struct amdgpu_ip_block {
287 struct amdgpu_ip_block_status status;
288 const struct amdgpu_ip_block_version *version;
289};
290
291int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
292 enum amd_ip_block_type type,
293 u32 major, u32 minor);
294
295struct amdgpu_ip_block *
296amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
297 enum amd_ip_block_type type);
298
299int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
300 const struct amdgpu_ip_block_version *ip_block_version);
301
302/*
303 * BIOS.
304 */
305bool amdgpu_get_bios(struct amdgpu_device *adev);
306bool amdgpu_read_bios(struct amdgpu_device *adev);
307
308/*
309 * Clocks
310 */
311
312#define AMDGPU_MAX_PPLL 3
313
314struct amdgpu_clock {
315 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
316 struct amdgpu_pll spll;
317 struct amdgpu_pll mpll;
318 /* 10 Khz units */
319 uint32_t default_mclk;
320 uint32_t default_sclk;
321 uint32_t default_dispclk;
322 uint32_t current_dispclk;
323 uint32_t dp_extclk;
324 uint32_t max_pixel_clock;
325};
326
327/* sub-allocation manager, it has to be protected by another lock.
328 * By conception this is an helper for other part of the driver
329 * like the indirect buffer or semaphore, which both have their
330 * locking.
331 *
332 * Principe is simple, we keep a list of sub allocation in offset
333 * order (first entry has offset == 0, last entry has the highest
334 * offset).
335 *
336 * When allocating new object we first check if there is room at
337 * the end total_size - (last_object_offset + last_object_size) >=
338 * alloc_size. If so we allocate new object there.
339 *
340 * When there is not enough room at the end, we start waiting for
341 * each sub object until we reach object_offset+object_size >=
342 * alloc_size, this object then become the sub object we return.
343 *
344 * Alignment can't be bigger than page size.
345 *
346 * Hole are not considered for allocation to keep things simple.
347 * Assumption is that there won't be hole (all object on same
348 * alignment).
349 */
350
351#define AMDGPU_SA_NUM_FENCE_LISTS 32
352
353struct amdgpu_sa_manager {
354 wait_queue_head_t wq;
355 struct amdgpu_bo *bo;
356 struct list_head *hole;
357 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
358 struct list_head olist;
359 unsigned size;
360 uint64_t gpu_addr;
361 void *cpu_ptr;
362 uint32_t domain;
363 uint32_t align;
364};
365
366/* sub-allocation buffer */
367struct amdgpu_sa_bo {
368 struct list_head olist;
369 struct list_head flist;
370 struct amdgpu_sa_manager *manager;
371 unsigned soffset;
372 unsigned eoffset;
373 struct dma_fence *fence;
374};
375
376int amdgpu_fence_slab_init(void);
377void amdgpu_fence_slab_fini(void);
378
379/*
380 * IRQS.
381 */
382
383struct amdgpu_flip_work {
384 struct delayed_work flip_work;
385 struct work_struct unpin_work;
386 struct amdgpu_device *adev;
387 int crtc_id;
388 u32 target_vblank;
389 uint64_t base;
390 struct drm_pending_vblank_event *event;
391 struct amdgpu_bo *old_abo;
392 struct dma_fence *excl;
393 unsigned shared_count;
394 struct dma_fence **shared;
395 struct dma_fence_cb cb;
396 bool async;
397};
398
399
400/*
401 * CP & rings.
402 */
403
404struct amdgpu_ib {
405 struct amdgpu_sa_bo *sa_bo;
406 uint32_t length_dw;
407 uint64_t gpu_addr;
408 uint32_t *ptr;
409 uint32_t flags;
410};
411
412extern const struct drm_sched_backend_ops amdgpu_sched_ops;
413
414/*
415 * file private structure
416 */
417
418struct amdgpu_fpriv {
419 struct amdgpu_vm vm;
420 struct amdgpu_bo_va *prt_va;
421 struct amdgpu_bo_va *csa_va;
422 struct mutex bo_list_lock;
423 struct idr bo_list_handles;
424 struct amdgpu_ctx_mgr ctx_mgr;
425};
426
427int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
428int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
429
430int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
431 unsigned size, struct amdgpu_ib *ib);
432void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
433 struct dma_fence *f);
434int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
435 struct amdgpu_ib *ibs, struct amdgpu_job *job,
436 struct dma_fence **f);
437int amdgpu_ib_pool_init(struct amdgpu_device *adev);
438void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
439int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
440
441/*
442 * CS.
443 */
444struct amdgpu_cs_chunk {
445 uint32_t chunk_id;
446 uint32_t length_dw;
447 void *kdata;
448};
449
450struct amdgpu_cs_post_dep {
451 struct drm_syncobj *syncobj;
452 struct dma_fence_chain *chain;
453 u64 point;
454};
455
456struct amdgpu_cs_parser {
457 struct amdgpu_device *adev;
458 struct drm_file *filp;
459 struct amdgpu_ctx *ctx;
460
461 /* chunks */
462 unsigned nchunks;
463 struct amdgpu_cs_chunk *chunks;
464
465 /* scheduler job object */
466 struct amdgpu_job *job;
467 struct drm_sched_entity *entity;
468
469 /* buffer objects */
470 struct ww_acquire_ctx ticket;
471 struct amdgpu_bo_list *bo_list;
472 struct amdgpu_mn *mn;
473 struct amdgpu_bo_list_entry vm_pd;
474 struct list_head validated;
475 struct dma_fence *fence;
476 uint64_t bytes_moved_threshold;
477 uint64_t bytes_moved_vis_threshold;
478 uint64_t bytes_moved;
479 uint64_t bytes_moved_vis;
480 struct amdgpu_bo_list_entry *evictable;
481
482 /* user fence */
483 struct amdgpu_bo_list_entry uf_entry;
484
485 unsigned num_post_deps;
486 struct amdgpu_cs_post_dep *post_deps;
487};
488
489static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
490 uint32_t ib_idx, int idx)
491{
492 return p->job->ibs[ib_idx].ptr[idx];
493}
494
495static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
496 uint32_t ib_idx, int idx,
497 uint32_t value)
498{
499 p->job->ibs[ib_idx].ptr[idx] = value;
500}
501
502/*
503 * Writeback
504 */
505#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
506
507struct amdgpu_wb {
508 struct amdgpu_bo *wb_obj;
509 volatile uint32_t *wb;
510 uint64_t gpu_addr;
511 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
512 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
513};
514
515int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
516void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
517
518/*
519 * Benchmarking
520 */
521void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
522
523
524/*
525 * Testing
526 */
527void amdgpu_test_moves(struct amdgpu_device *adev);
528
529/*
530 * ASIC specific register table accessible by UMD
531 */
532struct amdgpu_allowed_register_entry {
533 uint32_t reg_offset;
534 bool grbm_indexed;
535};
536
537enum amd_reset_method {
538 AMD_RESET_METHOD_LEGACY = 0,
539 AMD_RESET_METHOD_MODE0,
540 AMD_RESET_METHOD_MODE1,
541 AMD_RESET_METHOD_MODE2,
542 AMD_RESET_METHOD_BACO
543};
544
545/*
546 * ASIC specific functions.
547 */
548struct amdgpu_asic_funcs {
549 bool (*read_disabled_bios)(struct amdgpu_device *adev);
550 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
551 u8 *bios, u32 length_bytes);
552 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
553 u32 sh_num, u32 reg_offset, u32 *value);
554 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
555 int (*reset)(struct amdgpu_device *adev);
556 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
557 /* get the reference clock */
558 u32 (*get_xclk)(struct amdgpu_device *adev);
559 /* MM block clocks */
560 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
561 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
562 /* static power management */
563 int (*get_pcie_lanes)(struct amdgpu_device *adev);
564 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
565 /* get config memsize register */
566 u32 (*get_config_memsize)(struct amdgpu_device *adev);
567 /* flush hdp write queue */
568 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
569 /* invalidate hdp read cache */
570 void (*invalidate_hdp)(struct amdgpu_device *adev,
571 struct amdgpu_ring *ring);
572 /* check if the asic needs a full reset of if soft reset will work */
573 bool (*need_full_reset)(struct amdgpu_device *adev);
574 /* initialize doorbell layout for specific asic*/
575 void (*init_doorbell_index)(struct amdgpu_device *adev);
576 /* PCIe bandwidth usage */
577 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
578 uint64_t *count1);
579 /* do we need to reset the asic at init time (e.g., kexec) */
580 bool (*need_reset_on_init)(struct amdgpu_device *adev);
581 /* PCIe replay counter */
582 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
583};
584
585/*
586 * IOCTL.
587 */
588int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
589 struct drm_file *filp);
590
591int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
592int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
593 struct drm_file *filp);
594int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
595int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
596 struct drm_file *filp);
597
598/* VRAM scratch page for HDP bug, default vram page */
599struct amdgpu_vram_scratch {
600 struct amdgpu_bo *robj;
601 volatile uint32_t *ptr;
602 u64 gpu_addr;
603};
604
605/*
606 * ACPI
607 */
608struct amdgpu_atcs_functions {
609 bool get_ext_state;
610 bool pcie_perf_req;
611 bool pcie_dev_rdy;
612 bool pcie_bus_width;
613};
614
615struct amdgpu_atcs {
616 struct amdgpu_atcs_functions functions;
617};
618
619/*
620 * Firmware VRAM reservation
621 */
622struct amdgpu_fw_vram_usage {
623 u64 start_offset;
624 u64 size;
625 struct amdgpu_bo *reserved_bo;
626 void *va;
627};
628
629/*
630 * CGS
631 */
632struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
633void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
634
635/*
636 * Core structure, functions and helpers.
637 */
638typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
639typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
640
641typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
642typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
643
644typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
645typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
646
647
648/*
649 * amdgpu nbio functions
650 *
651 */
652struct nbio_hdp_flush_reg {
653 u32 ref_and_mask_cp0;
654 u32 ref_and_mask_cp1;
655 u32 ref_and_mask_cp2;
656 u32 ref_and_mask_cp3;
657 u32 ref_and_mask_cp4;
658 u32 ref_and_mask_cp5;
659 u32 ref_and_mask_cp6;
660 u32 ref_and_mask_cp7;
661 u32 ref_and_mask_cp8;
662 u32 ref_and_mask_cp9;
663 u32 ref_and_mask_sdma0;
664 u32 ref_and_mask_sdma1;
665 u32 ref_and_mask_sdma2;
666 u32 ref_and_mask_sdma3;
667 u32 ref_and_mask_sdma4;
668 u32 ref_and_mask_sdma5;
669 u32 ref_and_mask_sdma6;
670 u32 ref_and_mask_sdma7;
671};
672
673struct amdgpu_mmio_remap {
674 u32 reg_offset;
675 resource_size_t bus_addr;
676};
677
678struct amdgpu_nbio_funcs {
679 const struct nbio_hdp_flush_reg *hdp_flush_reg;
680 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
681 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
682 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
683 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
684 u32 (*get_rev_id)(struct amdgpu_device *adev);
685 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
686 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
687 u32 (*get_memsize)(struct amdgpu_device *adev);
688 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
689 bool use_doorbell, int doorbell_index, int doorbell_size);
690 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
691 int doorbell_index, int instance);
692 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
693 bool enable);
694 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
695 bool enable);
696 void (*ih_doorbell_range)(struct amdgpu_device *adev,
697 bool use_doorbell, int doorbell_index);
698 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
699 bool enable);
700 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
701 bool enable);
702 void (*get_clockgating_state)(struct amdgpu_device *adev,
703 u32 *flags);
704 void (*ih_control)(struct amdgpu_device *adev);
705 void (*init_registers)(struct amdgpu_device *adev);
706 void (*detect_hw_virt)(struct amdgpu_device *adev);
707 void (*remap_hdp_registers)(struct amdgpu_device *adev);
708};
709
710struct amdgpu_df_funcs {
711 void (*sw_init)(struct amdgpu_device *adev);
712 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
713 bool enable);
714 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
715 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
716 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
717 bool enable);
718 void (*get_clockgating_state)(struct amdgpu_device *adev,
719 u32 *flags);
720 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
721 bool enable);
722 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
723 int is_enable);
724 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
725 int is_disable);
726 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
727 uint64_t *count);
728 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
729 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
730 uint32_t ficadl_val, uint32_t ficadh_val);
731};
732/* Define the HW IP blocks will be used in driver , add more if necessary */
733enum amd_hw_ip_block_type {
734 GC_HWIP = 1,
735 HDP_HWIP,
736 SDMA0_HWIP,
737 SDMA1_HWIP,
738 SDMA2_HWIP,
739 SDMA3_HWIP,
740 SDMA4_HWIP,
741 SDMA5_HWIP,
742 SDMA6_HWIP,
743 SDMA7_HWIP,
744 MMHUB_HWIP,
745 ATHUB_HWIP,
746 NBIO_HWIP,
747 MP0_HWIP,
748 MP1_HWIP,
749 UVD_HWIP,
750 VCN_HWIP = UVD_HWIP,
751 VCE_HWIP,
752 DF_HWIP,
753 DCE_HWIP,
754 OSSSYS_HWIP,
755 SMUIO_HWIP,
756 PWR_HWIP,
757 NBIF_HWIP,
758 THM_HWIP,
759 CLK_HWIP,
760 UMC_HWIP,
761 RSMU_HWIP,
762 MAX_HWIP
763};
764
765#define HWIP_MAX_INSTANCE 8
766
767struct amd_powerplay {
768 void *pp_handle;
769 const struct amd_pm_funcs *pp_funcs;
770};
771
772#define AMDGPU_RESET_MAGIC_NUM 64
773#define AMDGPU_MAX_DF_PERFMONS 4
774struct amdgpu_device {
775 struct device *dev;
776 struct drm_device *ddev;
777 struct pci_dev *pdev;
778
779#ifdef CONFIG_DRM_AMD_ACP
780 struct amdgpu_acp acp;
781#endif
782
783 /* ASIC */
784 enum amd_asic_type asic_type;
785 uint32_t family;
786 uint32_t rev_id;
787 uint32_t external_rev_id;
788 unsigned long flags;
789 int usec_timeout;
790 const struct amdgpu_asic_funcs *asic_funcs;
791 bool shutdown;
792 bool need_swiotlb;
793 bool accel_working;
794 struct notifier_block acpi_nb;
795 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
796 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
797 unsigned debugfs_count;
798#if defined(CONFIG_DEBUG_FS)
799 struct dentry *debugfs_preempt;
800 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
801#endif
802 struct amdgpu_atif *atif;
803 struct amdgpu_atcs atcs;
804 struct mutex srbm_mutex;
805 /* GRBM index mutex. Protects concurrent access to GRBM index */
806 struct mutex grbm_idx_mutex;
807 struct dev_pm_domain vga_pm_domain;
808 bool have_disp_power_ref;
809 bool have_atomics_support;
810
811 /* BIOS */
812 bool is_atom_fw;
813 uint8_t *bios;
814 uint32_t bios_size;
815 struct amdgpu_bo *stolen_vga_memory;
816 uint32_t bios_scratch_reg_offset;
817 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
818
819 /* Register/doorbell mmio */
820 resource_size_t rmmio_base;
821 resource_size_t rmmio_size;
822 void __iomem *rmmio;
823 /* protects concurrent MM_INDEX/DATA based register access */
824 spinlock_t mmio_idx_lock;
825 struct amdgpu_mmio_remap rmmio_remap;
826 /* protects concurrent SMC based register access */
827 spinlock_t smc_idx_lock;
828 amdgpu_rreg_t smc_rreg;
829 amdgpu_wreg_t smc_wreg;
830 /* protects concurrent PCIE register access */
831 spinlock_t pcie_idx_lock;
832 amdgpu_rreg_t pcie_rreg;
833 amdgpu_wreg_t pcie_wreg;
834 amdgpu_rreg_t pciep_rreg;
835 amdgpu_wreg_t pciep_wreg;
836 amdgpu_rreg64_t pcie_rreg64;
837 amdgpu_wreg64_t pcie_wreg64;
838 /* protects concurrent UVD register access */
839 spinlock_t uvd_ctx_idx_lock;
840 amdgpu_rreg_t uvd_ctx_rreg;
841 amdgpu_wreg_t uvd_ctx_wreg;
842 /* protects concurrent DIDT register access */
843 spinlock_t didt_idx_lock;
844 amdgpu_rreg_t didt_rreg;
845 amdgpu_wreg_t didt_wreg;
846 /* protects concurrent gc_cac register access */
847 spinlock_t gc_cac_idx_lock;
848 amdgpu_rreg_t gc_cac_rreg;
849 amdgpu_wreg_t gc_cac_wreg;
850 /* protects concurrent se_cac register access */
851 spinlock_t se_cac_idx_lock;
852 amdgpu_rreg_t se_cac_rreg;
853 amdgpu_wreg_t se_cac_wreg;
854 /* protects concurrent ENDPOINT (audio) register access */
855 spinlock_t audio_endpt_idx_lock;
856 amdgpu_block_rreg_t audio_endpt_rreg;
857 amdgpu_block_wreg_t audio_endpt_wreg;
858 void __iomem *rio_mem;
859 resource_size_t rio_mem_size;
860 struct amdgpu_doorbell doorbell;
861
862 /* clock/pll info */
863 struct amdgpu_clock clock;
864
865 /* MC */
866 struct amdgpu_gmc gmc;
867 struct amdgpu_gart gart;
868 dma_addr_t dummy_page_addr;
869 struct amdgpu_vm_manager vm_manager;
870 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
871 unsigned num_vmhubs;
872
873 /* memory management */
874 struct amdgpu_mman mman;
875 struct amdgpu_vram_scratch vram_scratch;
876 struct amdgpu_wb wb;
877 atomic64_t num_bytes_moved;
878 atomic64_t num_evictions;
879 atomic64_t num_vram_cpu_page_faults;
880 atomic_t gpu_reset_counter;
881 atomic_t vram_lost_counter;
882
883 /* data for buffer migration throttling */
884 struct {
885 spinlock_t lock;
886 s64 last_update_us;
887 s64 accum_us; /* accumulated microseconds */
888 s64 accum_us_vis; /* for visible VRAM */
889 u32 log2_max_MBps;
890 } mm_stats;
891
892 /* display */
893 bool enable_virtual_display;
894 struct amdgpu_mode_info mode_info;
895 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
896 struct work_struct hotplug_work;
897 struct amdgpu_irq_src crtc_irq;
898 struct amdgpu_irq_src vupdate_irq;
899 struct amdgpu_irq_src pageflip_irq;
900 struct amdgpu_irq_src hpd_irq;
901
902 /* rings */
903 u64 fence_context;
904 unsigned num_rings;
905 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
906 bool ib_pool_ready;
907 struct amdgpu_sa_manager ring_tmp_bo;
908
909 /* interrupts */
910 struct amdgpu_irq irq;
911
912 /* powerplay */
913 struct amd_powerplay powerplay;
914 bool pp_force_state_enabled;
915
916 /* smu */
917 struct smu_context smu;
918
919 /* dpm */
920 struct amdgpu_pm pm;
921 u32 cg_flags;
922 u32 pg_flags;
923
924 /* gfx */
925 struct amdgpu_gfx gfx;
926
927 /* sdma */
928 struct amdgpu_sdma sdma;
929
930 /* uvd */
931 struct amdgpu_uvd uvd;
932
933 /* vce */
934 struct amdgpu_vce vce;
935
936 /* vcn */
937 struct amdgpu_vcn vcn;
938
939 /* firmwares */
940 struct amdgpu_firmware firmware;
941
942 /* PSP */
943 struct psp_context psp;
944
945 /* GDS */
946 struct amdgpu_gds gds;
947
948 /* KFD */
949 struct amdgpu_kfd_dev kfd;
950
951 /* UMC */
952 struct amdgpu_umc umc;
953
954 /* display related functionality */
955 struct amdgpu_display_manager dm;
956
957 /* discovery */
958 uint8_t *discovery;
959
960 /* mes */
961 bool enable_mes;
962 struct amdgpu_mes mes;
963
964 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
965 int num_ip_blocks;
966 struct mutex mn_lock;
967 DECLARE_HASHTABLE(mn_hash, 7);
968
969 /* tracking pinned memory */
970 atomic64_t vram_pin_size;
971 atomic64_t visible_pin_size;
972 atomic64_t gart_pin_size;
973
974 /* soc15 register offset based on ip, instance and segment */
975 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
976
977 const struct amdgpu_nbio_funcs *nbio_funcs;
978 const struct amdgpu_df_funcs *df_funcs;
979 const struct amdgpu_mmhub_funcs *mmhub_funcs;
980
981 /* delayed work_func for deferring clockgating during resume */
982 struct delayed_work delayed_init_work;
983
984 struct amdgpu_virt virt;
985 /* firmware VRAM reservation */
986 struct amdgpu_fw_vram_usage fw_vram_usage;
987
988 /* link all shadow bo */
989 struct list_head shadow_list;
990 struct mutex shadow_list_lock;
991 /* keep an lru list of rings by HW IP */
992 struct list_head ring_lru_list;
993 spinlock_t ring_lru_list_lock;
994
995 /* record hw reset is performed */
996 bool has_hw_reset;
997 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
998
999 /* s3/s4 mask */
1000 bool in_suspend;
1001
1002 /* record last mm index being written through WREG32*/
1003 unsigned long last_mm_index;
1004 bool in_gpu_reset;
1005 enum pp_mp1_state mp1_state;
1006 struct mutex lock_reset;
1007 struct amdgpu_doorbell_index doorbell_index;
1008
1009 int asic_reset_res;
1010 struct work_struct xgmi_reset_work;
1011
1012 bool in_baco_reset;
1013
1014 long gfx_timeout;
1015 long sdma_timeout;
1016 long video_timeout;
1017 long compute_timeout;
1018
1019 uint64_t unique_id;
1020 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1021};
1022
1023static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1024{
1025 return container_of(bdev, struct amdgpu_device, mman.bdev);
1026}
1027
1028int amdgpu_device_init(struct amdgpu_device *adev,
1029 struct drm_device *ddev,
1030 struct pci_dev *pdev,
1031 uint32_t flags);
1032void amdgpu_device_fini(struct amdgpu_device *adev);
1033int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1034
1035uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1036 uint32_t acc_flags);
1037void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1038 uint32_t acc_flags);
1039void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1040uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1041
1042u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1043void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1044
1045bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1046bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1047
1048int emu_soc_asic_init(struct amdgpu_device *adev);
1049
1050/*
1051 * Registers read & write functions.
1052 */
1053
1054#define AMDGPU_REGS_IDX (1<<0)
1055#define AMDGPU_REGS_NO_KIQ (1<<1)
1056
1057#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1058#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1059
1060#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1061#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1062
1063#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1064#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1065#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1066#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1067#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1068#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1069#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1070#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1071#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1072#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1073#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1074#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1075#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1076#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1077#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1078#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1079#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1080#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1081#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1082#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1083#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1084#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1085#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1086#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1087#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1088#define WREG32_P(reg, val, mask) \
1089 do { \
1090 uint32_t tmp_ = RREG32(reg); \
1091 tmp_ &= (mask); \
1092 tmp_ |= ((val) & ~(mask)); \
1093 WREG32(reg, tmp_); \
1094 } while (0)
1095#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1096#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1097#define WREG32_PLL_P(reg, val, mask) \
1098 do { \
1099 uint32_t tmp_ = RREG32_PLL(reg); \
1100 tmp_ &= (mask); \
1101 tmp_ |= ((val) & ~(mask)); \
1102 WREG32_PLL(reg, tmp_); \
1103 } while (0)
1104#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1105#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1106#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1107
1108#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1109#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1110
1111#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1112 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1113 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1114
1115#define REG_GET_FIELD(value, reg, field) \
1116 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1117
1118#define WREG32_FIELD(reg, field, val) \
1119 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1120
1121#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1122 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1123
1124/*
1125 * BIOS helpers.
1126 */
1127#define RBIOS8(i) (adev->bios[i])
1128#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1129#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1130
1131/*
1132 * ASICs macro.
1133 */
1134#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1135#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1136#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1137#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1138#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1139#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1140#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1141#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1142#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1143#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1144#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1145#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1146#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1147#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1148#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1149#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1150#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1151#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1152#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1153#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1154#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1155
1156/* Common functions */
1157bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1158int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1159 struct amdgpu_job* job);
1160void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1161bool amdgpu_device_need_post(struct amdgpu_device *adev);
1162
1163void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1164 u64 num_vis_bytes);
1165int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1166void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1167 const u32 *registers,
1168 const u32 array_size);
1169
1170bool amdgpu_device_is_px(struct drm_device *dev);
1171bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1172 struct amdgpu_device *peer_adev);
1173
1174/* atpx handler */
1175#if defined(CONFIG_VGA_SWITCHEROO)
1176void amdgpu_register_atpx_handler(void);
1177void amdgpu_unregister_atpx_handler(void);
1178bool amdgpu_has_atpx_dgpu_power_cntl(void);
1179bool amdgpu_is_atpx_hybrid(void);
1180bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1181bool amdgpu_has_atpx(void);
1182#else
1183static inline void amdgpu_register_atpx_handler(void) {}
1184static inline void amdgpu_unregister_atpx_handler(void) {}
1185static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1186static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1187static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1188static inline bool amdgpu_has_atpx(void) { return false; }
1189#endif
1190
1191#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1192void *amdgpu_atpx_get_dhandle(void);
1193#else
1194static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1195#endif
1196
1197/*
1198 * KMS
1199 */
1200extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1201extern const int amdgpu_max_kms_ioctl;
1202
1203int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1204void amdgpu_driver_unload_kms(struct drm_device *dev);
1205void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1206int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1207void amdgpu_driver_postclose_kms(struct drm_device *dev,
1208 struct drm_file *file_priv);
1209int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1210int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1211int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1212u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1213int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1214void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1215long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1216 unsigned long arg);
1217
1218/*
1219 * functions used by amdgpu_encoder.c
1220 */
1221struct amdgpu_afmt_acr {
1222 u32 clock;
1223
1224 int n_32khz;
1225 int cts_32khz;
1226
1227 int n_44_1khz;
1228 int cts_44_1khz;
1229
1230 int n_48khz;
1231 int cts_48khz;
1232
1233};
1234
1235struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1236
1237/* amdgpu_acpi.c */
1238#if defined(CONFIG_ACPI)
1239int amdgpu_acpi_init(struct amdgpu_device *adev);
1240void amdgpu_acpi_fini(struct amdgpu_device *adev);
1241bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1242int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1243 u8 perf_req, bool advertise);
1244int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1245
1246void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1247 struct amdgpu_dm_backlight_caps *caps);
1248#else
1249static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1250static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1251#endif
1252
1253int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1254 uint64_t addr, struct amdgpu_bo **bo,
1255 struct amdgpu_bo_va_mapping **mapping);
1256
1257#if defined(CONFIG_DRM_AMD_DC)
1258int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1259#else
1260static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1261#endif
1262
1263
1264void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1265void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1266
1267#include "amdgpu_object.h"
1268
1269/* used by df_v3_6.c and amdgpu_pmu.c */
1270#define AMDGPU_PMU_ATTR(_name, _object) \
1271static ssize_t \
1272_name##_show(struct device *dev, \
1273 struct device_attribute *attr, \
1274 char *page) \
1275{ \
1276 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1277 return sprintf(page, _object "\n"); \
1278} \
1279 \
1280static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1281
1282#endif
1283
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53
54#include <drm/ttm/ttm_bo.h>
55#include <drm/ttm/ttm_placement.h>
56
57#include <drm/amdgpu_drm.h>
58#include <drm/drm_gem.h>
59#include <drm/drm_ioctl.h>
60
61#include <kgd_kfd_interface.h>
62#include "dm_pp_interface.h"
63#include "kgd_pp_interface.h"
64
65#include "amd_shared.h"
66#include "amdgpu_mode.h"
67#include "amdgpu_ih.h"
68#include "amdgpu_irq.h"
69#include "amdgpu_ucode.h"
70#include "amdgpu_ttm.h"
71#include "amdgpu_psp.h"
72#include "amdgpu_gds.h"
73#include "amdgpu_sync.h"
74#include "amdgpu_ring.h"
75#include "amdgpu_vm.h"
76#include "amdgpu_dpm.h"
77#include "amdgpu_acp.h"
78#include "amdgpu_uvd.h"
79#include "amdgpu_vce.h"
80#include "amdgpu_vcn.h"
81#include "amdgpu_jpeg.h"
82#include "amdgpu_vpe.h"
83#include "amdgpu_umsch_mm.h"
84#include "amdgpu_gmc.h"
85#include "amdgpu_gfx.h"
86#include "amdgpu_sdma.h"
87#include "amdgpu_lsdma.h"
88#include "amdgpu_nbio.h"
89#include "amdgpu_hdp.h"
90#include "amdgpu_dm.h"
91#include "amdgpu_virt.h"
92#include "amdgpu_csa.h"
93#include "amdgpu_mes_ctx.h"
94#include "amdgpu_gart.h"
95#include "amdgpu_debugfs.h"
96#include "amdgpu_job.h"
97#include "amdgpu_bo_list.h"
98#include "amdgpu_gem.h"
99#include "amdgpu_doorbell.h"
100#include "amdgpu_amdkfd.h"
101#include "amdgpu_discovery.h"
102#include "amdgpu_mes.h"
103#include "amdgpu_umc.h"
104#include "amdgpu_mmhub.h"
105#include "amdgpu_gfxhub.h"
106#include "amdgpu_df.h"
107#include "amdgpu_smuio.h"
108#include "amdgpu_fdinfo.h"
109#include "amdgpu_mca.h"
110#include "amdgpu_aca.h"
111#include "amdgpu_ras.h"
112#include "amdgpu_xcp.h"
113#include "amdgpu_seq64.h"
114#include "amdgpu_reg_state.h"
115#if defined(CONFIG_DRM_AMD_ISP)
116#include "amdgpu_isp.h"
117#endif
118
119#define MAX_GPU_INSTANCE 64
120
121#define GFX_SLICE_PERIOD_MS 250
122
123struct amdgpu_gpu_instance {
124 struct amdgpu_device *adev;
125 int mgpu_fan_enabled;
126};
127
128struct amdgpu_mgpu_info {
129 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
130 struct mutex mutex;
131 uint32_t num_gpu;
132 uint32_t num_dgpu;
133 uint32_t num_apu;
134};
135
136enum amdgpu_ss {
137 AMDGPU_SS_DRV_LOAD,
138 AMDGPU_SS_DEV_D0,
139 AMDGPU_SS_DEV_D3,
140 AMDGPU_SS_DRV_UNLOAD
141};
142
143struct amdgpu_hwip_reg_entry {
144 u32 hwip;
145 u32 inst;
146 u32 seg;
147 u32 reg_offset;
148 const char *reg_name;
149};
150
151struct amdgpu_watchdog_timer {
152 bool timeout_fatal_disable;
153 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
154};
155
156#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
157
158/*
159 * Modules parameters.
160 */
161extern int amdgpu_modeset;
162extern unsigned int amdgpu_vram_limit;
163extern int amdgpu_vis_vram_limit;
164extern int amdgpu_gart_size;
165extern int amdgpu_gtt_size;
166extern int amdgpu_moverate;
167extern int amdgpu_audio;
168extern int amdgpu_disp_priority;
169extern int amdgpu_hw_i2c;
170extern int amdgpu_pcie_gen2;
171extern int amdgpu_msi;
172extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
173extern int amdgpu_dpm;
174extern int amdgpu_fw_load_type;
175extern int amdgpu_aspm;
176extern int amdgpu_runtime_pm;
177extern uint amdgpu_ip_block_mask;
178extern int amdgpu_bapm;
179extern int amdgpu_deep_color;
180extern int amdgpu_vm_size;
181extern int amdgpu_vm_block_size;
182extern int amdgpu_vm_fragment_size;
183extern int amdgpu_vm_fault_stop;
184extern int amdgpu_vm_debug;
185extern int amdgpu_vm_update_mode;
186extern int amdgpu_exp_hw_support;
187extern int amdgpu_dc;
188extern int amdgpu_sched_jobs;
189extern int amdgpu_sched_hw_submission;
190extern uint amdgpu_pcie_gen_cap;
191extern uint amdgpu_pcie_lane_cap;
192extern u64 amdgpu_cg_mask;
193extern uint amdgpu_pg_mask;
194extern uint amdgpu_sdma_phase_quantum;
195extern char *amdgpu_disable_cu;
196extern char *amdgpu_virtual_display;
197extern uint amdgpu_pp_feature_mask;
198extern uint amdgpu_force_long_training;
199extern int amdgpu_lbpw;
200extern int amdgpu_compute_multipipe;
201extern int amdgpu_gpu_recovery;
202extern int amdgpu_emu_mode;
203extern uint amdgpu_smu_memory_pool_size;
204extern int amdgpu_smu_pptable_id;
205extern uint amdgpu_dc_feature_mask;
206extern uint amdgpu_freesync_vid_mode;
207extern uint amdgpu_dc_debug_mask;
208extern uint amdgpu_dc_visual_confirm;
209extern int amdgpu_dm_abm_level;
210extern int amdgpu_backlight;
211extern int amdgpu_damage_clips;
212extern struct amdgpu_mgpu_info mgpu_info;
213extern int amdgpu_ras_enable;
214extern uint amdgpu_ras_mask;
215extern int amdgpu_bad_page_threshold;
216extern bool amdgpu_ignore_bad_page_threshold;
217extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
218extern int amdgpu_async_gfx_ring;
219extern int amdgpu_mcbp;
220extern int amdgpu_discovery;
221extern int amdgpu_mes;
222extern int amdgpu_mes_log_enable;
223extern int amdgpu_mes_kiq;
224extern int amdgpu_uni_mes;
225extern int amdgpu_noretry;
226extern int amdgpu_force_asic_type;
227extern int amdgpu_smartshift_bias;
228extern int amdgpu_use_xgmi_p2p;
229extern int amdgpu_mtype_local;
230extern bool enforce_isolation;
231#ifdef CONFIG_HSA_AMD
232extern int sched_policy;
233extern bool debug_evictions;
234extern bool no_system_mem_limit;
235extern int halt_if_hws_hang;
236extern uint amdgpu_svm_default_granularity;
237#else
238static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
239static const bool __maybe_unused debug_evictions; /* = false */
240static const bool __maybe_unused no_system_mem_limit;
241static const int __maybe_unused halt_if_hws_hang;
242#endif
243#ifdef CONFIG_HSA_AMD_P2P
244extern bool pcie_p2p;
245#endif
246
247extern int amdgpu_tmz;
248extern int amdgpu_reset_method;
249
250#ifdef CONFIG_DRM_AMDGPU_SI
251extern int amdgpu_si_support;
252#endif
253#ifdef CONFIG_DRM_AMDGPU_CIK
254extern int amdgpu_cik_support;
255#endif
256extern int amdgpu_num_kcq;
257
258#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
259#define AMDGPU_UMSCHFW_LOG_SIZE (32 * 1024)
260extern int amdgpu_vcnfw_log;
261extern int amdgpu_sg_display;
262extern int amdgpu_umsch_mm;
263extern int amdgpu_seamless;
264extern int amdgpu_umsch_mm_fwlog;
265
266extern int amdgpu_user_partt_mode;
267extern int amdgpu_agp;
268
269extern int amdgpu_wbrf;
270
271#define AMDGPU_VM_MAX_NUM_CTX 4096
272#define AMDGPU_SG_THRESHOLD (256*1024*1024)
273#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
274#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
275#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
276#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
277#define AMDGPUFB_CONN_LIMIT 4
278#define AMDGPU_BIOS_NUM_SCRATCH 16
279
280#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
281
282/* hard reset data */
283#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
284
285/* reset flags */
286#define AMDGPU_RESET_GFX (1 << 0)
287#define AMDGPU_RESET_COMPUTE (1 << 1)
288#define AMDGPU_RESET_DMA (1 << 2)
289#define AMDGPU_RESET_CP (1 << 3)
290#define AMDGPU_RESET_GRBM (1 << 4)
291#define AMDGPU_RESET_DMA1 (1 << 5)
292#define AMDGPU_RESET_RLC (1 << 6)
293#define AMDGPU_RESET_SEM (1 << 7)
294#define AMDGPU_RESET_IH (1 << 8)
295#define AMDGPU_RESET_VMC (1 << 9)
296#define AMDGPU_RESET_MC (1 << 10)
297#define AMDGPU_RESET_DISPLAY (1 << 11)
298#define AMDGPU_RESET_UVD (1 << 12)
299#define AMDGPU_RESET_VCE (1 << 13)
300#define AMDGPU_RESET_VCE1 (1 << 14)
301
302/* reset mask */
303#define AMDGPU_RESET_TYPE_FULL (1 << 0) /* full adapter reset, mode1/mode2/BACO/etc. */
304#define AMDGPU_RESET_TYPE_SOFT_RESET (1 << 1) /* IP level soft reset */
305#define AMDGPU_RESET_TYPE_PER_QUEUE (1 << 2) /* per queue */
306#define AMDGPU_RESET_TYPE_PER_PIPE (1 << 3) /* per pipe */
307
308/* max cursor sizes (in pixels) */
309#define CIK_CURSOR_WIDTH 128
310#define CIK_CURSOR_HEIGHT 128
311
312/* smart shift bias level limits */
313#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
314#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
315
316/* Extra time delay(in ms) to eliminate the influence of temperature momentary fluctuation */
317#define AMDGPU_SWCTF_EXTRA_DELAY 50
318
319struct amdgpu_xcp_mgr;
320struct amdgpu_device;
321struct amdgpu_irq_src;
322struct amdgpu_fpriv;
323struct amdgpu_bo_va_mapping;
324struct kfd_vm_fault_info;
325struct amdgpu_hive_info;
326struct amdgpu_reset_context;
327struct amdgpu_reset_control;
328
329enum amdgpu_cp_irq {
330 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
331 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
332 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
333 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
334 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
335 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
336 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
337 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
338 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
339 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
340
341 AMDGPU_CP_IRQ_LAST
342};
343
344enum amdgpu_thermal_irq {
345 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
346 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
347
348 AMDGPU_THERMAL_IRQ_LAST
349};
350
351enum amdgpu_kiq_irq {
352 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
353 AMDGPU_CP_KIQ_IRQ_LAST
354};
355#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
356#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
357#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
358#define MAX_KIQ_REG_TRY 1000
359
360int amdgpu_device_ip_set_clockgating_state(void *dev,
361 enum amd_ip_block_type block_type,
362 enum amd_clockgating_state state);
363int amdgpu_device_ip_set_powergating_state(void *dev,
364 enum amd_ip_block_type block_type,
365 enum amd_powergating_state state);
366void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
367 u64 *flags);
368int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
369 enum amd_ip_block_type block_type);
370bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev,
371 enum amd_ip_block_type block_type);
372int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block);
373
374int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block);
375
376#define AMDGPU_MAX_IP_NUM 16
377
378struct amdgpu_ip_block_status {
379 bool valid;
380 bool sw;
381 bool hw;
382 bool late_initialized;
383 bool hang;
384};
385
386struct amdgpu_ip_block_version {
387 const enum amd_ip_block_type type;
388 const u32 major;
389 const u32 minor;
390 const u32 rev;
391 const struct amd_ip_funcs *funcs;
392};
393
394struct amdgpu_ip_block {
395 struct amdgpu_ip_block_status status;
396 const struct amdgpu_ip_block_version *version;
397 struct amdgpu_device *adev;
398};
399
400int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
401 enum amd_ip_block_type type,
402 u32 major, u32 minor);
403
404struct amdgpu_ip_block *
405amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
406 enum amd_ip_block_type type);
407
408int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
409 const struct amdgpu_ip_block_version *ip_block_version);
410
411/*
412 * BIOS.
413 */
414bool amdgpu_get_bios(struct amdgpu_device *adev);
415bool amdgpu_read_bios(struct amdgpu_device *adev);
416bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
417 u8 *bios, u32 length_bytes);
418/*
419 * Clocks
420 */
421
422#define AMDGPU_MAX_PPLL 3
423
424struct amdgpu_clock {
425 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
426 struct amdgpu_pll spll;
427 struct amdgpu_pll mpll;
428 /* 10 Khz units */
429 uint32_t default_mclk;
430 uint32_t default_sclk;
431 uint32_t default_dispclk;
432 uint32_t current_dispclk;
433 uint32_t dp_extclk;
434 uint32_t max_pixel_clock;
435};
436
437/* sub-allocation manager, it has to be protected by another lock.
438 * By conception this is an helper for other part of the driver
439 * like the indirect buffer or semaphore, which both have their
440 * locking.
441 *
442 * Principe is simple, we keep a list of sub allocation in offset
443 * order (first entry has offset == 0, last entry has the highest
444 * offset).
445 *
446 * When allocating new object we first check if there is room at
447 * the end total_size - (last_object_offset + last_object_size) >=
448 * alloc_size. If so we allocate new object there.
449 *
450 * When there is not enough room at the end, we start waiting for
451 * each sub object until we reach object_offset+object_size >=
452 * alloc_size, this object then become the sub object we return.
453 *
454 * Alignment can't be bigger than page size.
455 *
456 * Hole are not considered for allocation to keep things simple.
457 * Assumption is that there won't be hole (all object on same
458 * alignment).
459 */
460
461struct amdgpu_sa_manager {
462 struct drm_suballoc_manager base;
463 struct amdgpu_bo *bo;
464 uint64_t gpu_addr;
465 void *cpu_ptr;
466};
467
468int amdgpu_fence_slab_init(void);
469void amdgpu_fence_slab_fini(void);
470
471/*
472 * IRQS.
473 */
474
475struct amdgpu_flip_work {
476 struct delayed_work flip_work;
477 struct work_struct unpin_work;
478 struct amdgpu_device *adev;
479 int crtc_id;
480 u32 target_vblank;
481 uint64_t base;
482 struct drm_pending_vblank_event *event;
483 struct amdgpu_bo *old_abo;
484 unsigned shared_count;
485 struct dma_fence **shared;
486 struct dma_fence_cb cb;
487 bool async;
488};
489
490
491/*
492 * file private structure
493 */
494
495struct amdgpu_fpriv {
496 struct amdgpu_vm vm;
497 struct amdgpu_bo_va *prt_va;
498 struct amdgpu_bo_va *csa_va;
499 struct amdgpu_bo_va *seq64_va;
500 struct mutex bo_list_lock;
501 struct idr bo_list_handles;
502 struct amdgpu_ctx_mgr ctx_mgr;
503 /** GPU partition selection */
504 uint32_t xcp_id;
505};
506
507int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
508
509/*
510 * Writeback
511 */
512#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
513
514struct amdgpu_wb {
515 struct amdgpu_bo *wb_obj;
516 volatile uint32_t *wb;
517 uint64_t gpu_addr;
518 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
519 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
520 spinlock_t lock;
521};
522
523int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
524void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
525
526/*
527 * Benchmarking
528 */
529int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
530
531/*
532 * ASIC specific register table accessible by UMD
533 */
534struct amdgpu_allowed_register_entry {
535 uint32_t reg_offset;
536 bool grbm_indexed;
537};
538
539/**
540 * enum amd_reset_method - Methods for resetting AMD GPU devices
541 *
542 * @AMD_RESET_METHOD_NONE: The device will not be reset.
543 * @AMD_RESET_LEGACY: Method reserved for SI, CIK and VI ASICs.
544 * @AMD_RESET_MODE0: Reset the entire ASIC. Not currently available for the
545 * any device.
546 * @AMD_RESET_MODE1: Resets all IP blocks on the ASIC (SDMA, GFX, VCN, etc.)
547 * individually. Suitable only for some discrete GPU, not
548 * available for all ASICs.
549 * @AMD_RESET_MODE2: Resets a lesser level of IPs compared to MODE1. Which IPs
550 * are reset depends on the ASIC. Notably doesn't reset IPs
551 * shared with the CPU on APUs or the memory controllers (so
552 * VRAM is not lost). Not available on all ASICs.
553 * @AMD_RESET_BACO: BACO (Bus Alive, Chip Off) method powers off and on the card
554 * but without powering off the PCI bus. Suitable only for
555 * discrete GPUs.
556 * @AMD_RESET_PCI: Does a full bus reset using core Linux subsystem PCI reset
557 * and does a secondary bus reset or FLR, depending on what the
558 * underlying hardware supports.
559 *
560 * Methods available for AMD GPU driver for resetting the device. Not all
561 * methods are suitable for every device. User can override the method using
562 * module parameter `reset_method`.
563 */
564enum amd_reset_method {
565 AMD_RESET_METHOD_NONE = -1,
566 AMD_RESET_METHOD_LEGACY = 0,
567 AMD_RESET_METHOD_MODE0,
568 AMD_RESET_METHOD_MODE1,
569 AMD_RESET_METHOD_MODE2,
570 AMD_RESET_METHOD_BACO,
571 AMD_RESET_METHOD_PCI,
572 AMD_RESET_METHOD_ON_INIT,
573};
574
575struct amdgpu_video_codec_info {
576 u32 codec_type;
577 u32 max_width;
578 u32 max_height;
579 u32 max_pixels_per_frame;
580 u32 max_level;
581};
582
583#define codec_info_build(type, width, height, level) \
584 .codec_type = type,\
585 .max_width = width,\
586 .max_height = height,\
587 .max_pixels_per_frame = height * width,\
588 .max_level = level,
589
590struct amdgpu_video_codecs {
591 const u32 codec_count;
592 const struct amdgpu_video_codec_info *codec_array;
593};
594
595/*
596 * ASIC specific functions.
597 */
598struct amdgpu_asic_funcs {
599 bool (*read_disabled_bios)(struct amdgpu_device *adev);
600 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
601 u8 *bios, u32 length_bytes);
602 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
603 u32 sh_num, u32 reg_offset, u32 *value);
604 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
605 int (*reset)(struct amdgpu_device *adev);
606 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
607 /* get the reference clock */
608 u32 (*get_xclk)(struct amdgpu_device *adev);
609 /* MM block clocks */
610 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
611 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
612 /* static power management */
613 int (*get_pcie_lanes)(struct amdgpu_device *adev);
614 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
615 /* get config memsize register */
616 u32 (*get_config_memsize)(struct amdgpu_device *adev);
617 /* flush hdp write queue */
618 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
619 /* invalidate hdp read cache */
620 void (*invalidate_hdp)(struct amdgpu_device *adev,
621 struct amdgpu_ring *ring);
622 /* check if the asic needs a full reset of if soft reset will work */
623 bool (*need_full_reset)(struct amdgpu_device *adev);
624 /* initialize doorbell layout for specific asic*/
625 void (*init_doorbell_index)(struct amdgpu_device *adev);
626 /* PCIe bandwidth usage */
627 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
628 uint64_t *count1);
629 /* do we need to reset the asic at init time (e.g., kexec) */
630 bool (*need_reset_on_init)(struct amdgpu_device *adev);
631 /* PCIe replay counter */
632 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
633 /* device supports BACO */
634 int (*supports_baco)(struct amdgpu_device *adev);
635 /* pre asic_init quirks */
636 void (*pre_asic_init)(struct amdgpu_device *adev);
637 /* enter/exit umd stable pstate */
638 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
639 /* query video codecs */
640 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
641 const struct amdgpu_video_codecs **codecs);
642 /* encode "> 32bits" smn addressing */
643 u64 (*encode_ext_smn_addressing)(int ext_id);
644
645 ssize_t (*get_reg_state)(struct amdgpu_device *adev,
646 enum amdgpu_reg_state reg_state, void *buf,
647 size_t max_size);
648};
649
650/*
651 * IOCTL.
652 */
653int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
654 struct drm_file *filp);
655
656int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
657int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
658 struct drm_file *filp);
659int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
660int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
661 struct drm_file *filp);
662
663/* VRAM scratch page for HDP bug, default vram page */
664struct amdgpu_mem_scratch {
665 struct amdgpu_bo *robj;
666 volatile uint32_t *ptr;
667 u64 gpu_addr;
668};
669
670/*
671 * CGS
672 */
673struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
674void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
675
676/*
677 * Core structure, functions and helpers.
678 */
679typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
680typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
681
682typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t);
683typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t);
684
685typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
686typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
687
688typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t);
689typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t);
690
691typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
692typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
693
694struct amdgpu_mmio_remap {
695 u32 reg_offset;
696 resource_size_t bus_addr;
697};
698
699/* Define the HW IP blocks will be used in driver , add more if necessary */
700enum amd_hw_ip_block_type {
701 GC_HWIP = 1,
702 HDP_HWIP,
703 SDMA0_HWIP,
704 SDMA1_HWIP,
705 SDMA2_HWIP,
706 SDMA3_HWIP,
707 SDMA4_HWIP,
708 SDMA5_HWIP,
709 SDMA6_HWIP,
710 SDMA7_HWIP,
711 LSDMA_HWIP,
712 MMHUB_HWIP,
713 ATHUB_HWIP,
714 NBIO_HWIP,
715 MP0_HWIP,
716 MP1_HWIP,
717 UVD_HWIP,
718 VCN_HWIP = UVD_HWIP,
719 JPEG_HWIP = VCN_HWIP,
720 VCN1_HWIP,
721 VCE_HWIP,
722 VPE_HWIP,
723 DF_HWIP,
724 DCE_HWIP,
725 OSSSYS_HWIP,
726 SMUIO_HWIP,
727 PWR_HWIP,
728 NBIF_HWIP,
729 THM_HWIP,
730 CLK_HWIP,
731 UMC_HWIP,
732 RSMU_HWIP,
733 XGMI_HWIP,
734 DCI_HWIP,
735 PCIE_HWIP,
736 ISP_HWIP,
737 MAX_HWIP
738};
739
740#define HWIP_MAX_INSTANCE 44
741
742#define HW_ID_MAX 300
743#define IP_VERSION_FULL(mj, mn, rv, var, srev) \
744 (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev))
745#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0)
746#define IP_VERSION_MAJ(ver) ((ver) >> 24)
747#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF)
748#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF)
749#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF)
750#define IP_VERSION_SUBREV(ver) ((ver) & 0xF)
751#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8)
752
753struct amdgpu_ip_map_info {
754 /* Map of logical to actual dev instances/mask */
755 uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE];
756 int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev,
757 enum amd_hw_ip_block_type block,
758 int8_t inst);
759 uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev,
760 enum amd_hw_ip_block_type block,
761 uint32_t mask);
762};
763
764struct amd_powerplay {
765 void *pp_handle;
766 const struct amd_pm_funcs *pp_funcs;
767};
768
769struct ip_discovery_top;
770
771/* polaris10 kickers */
772#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
773 ((rid == 0xE3) || \
774 (rid == 0xE4) || \
775 (rid == 0xE5) || \
776 (rid == 0xE7) || \
777 (rid == 0xEF))) || \
778 ((did == 0x6FDF) && \
779 ((rid == 0xE7) || \
780 (rid == 0xEF) || \
781 (rid == 0xFF))))
782
783#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
784 ((rid == 0xE1) || \
785 (rid == 0xF7)))
786
787/* polaris11 kickers */
788#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
789 ((rid == 0xE0) || \
790 (rid == 0xE5))) || \
791 ((did == 0x67FF) && \
792 ((rid == 0xCF) || \
793 (rid == 0xEF) || \
794 (rid == 0xFF))))
795
796#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
797 ((rid == 0xE2)))
798
799/* polaris12 kickers */
800#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
801 ((rid == 0xC0) || \
802 (rid == 0xC1) || \
803 (rid == 0xC3) || \
804 (rid == 0xC7))) || \
805 ((did == 0x6981) && \
806 ((rid == 0x00) || \
807 (rid == 0x01) || \
808 (rid == 0x10))))
809
810struct amdgpu_mqd_prop {
811 uint64_t mqd_gpu_addr;
812 uint64_t hqd_base_gpu_addr;
813 uint64_t rptr_gpu_addr;
814 uint64_t wptr_gpu_addr;
815 uint32_t queue_size;
816 bool use_doorbell;
817 uint32_t doorbell_index;
818 uint64_t eop_gpu_addr;
819 uint32_t hqd_pipe_priority;
820 uint32_t hqd_queue_priority;
821 bool allow_tunneling;
822 bool hqd_active;
823};
824
825struct amdgpu_mqd {
826 unsigned mqd_size;
827 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
828 struct amdgpu_mqd_prop *p);
829};
830
831/*
832 * Custom Init levels could be defined for different situations where a full
833 * initialization of all hardware blocks are not expected. Sample cases are
834 * custom init sequences after resume after S0i3/S3, reset on initialization,
835 * partial reset of blocks etc. Presently, this defines only two levels. Levels
836 * are described in corresponding struct definitions - amdgpu_init_default,
837 * amdgpu_init_minimal_xgmi.
838 */
839enum amdgpu_init_lvl_id {
840 AMDGPU_INIT_LEVEL_DEFAULT,
841 AMDGPU_INIT_LEVEL_MINIMAL_XGMI,
842 AMDGPU_INIT_LEVEL_RESET_RECOVERY,
843};
844
845struct amdgpu_init_level {
846 enum amdgpu_init_lvl_id level;
847 uint32_t hwini_ip_block_mask;
848};
849
850#define AMDGPU_RESET_MAGIC_NUM 64
851#define AMDGPU_MAX_DF_PERFMONS 4
852struct amdgpu_reset_domain;
853struct amdgpu_fru_info;
854
855/*
856 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
857 */
858#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
859
860struct amdgpu_device {
861 struct device *dev;
862 struct pci_dev *pdev;
863 struct drm_device ddev;
864
865#ifdef CONFIG_DRM_AMD_ACP
866 struct amdgpu_acp acp;
867#endif
868 struct amdgpu_hive_info *hive;
869 struct amdgpu_xcp_mgr *xcp_mgr;
870 /* ASIC */
871 enum amd_asic_type asic_type;
872 uint32_t family;
873 uint32_t rev_id;
874 uint32_t external_rev_id;
875 unsigned long flags;
876 unsigned long apu_flags;
877 int usec_timeout;
878 const struct amdgpu_asic_funcs *asic_funcs;
879 bool shutdown;
880 bool need_swiotlb;
881 bool accel_working;
882 struct notifier_block acpi_nb;
883 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
884 struct debugfs_blob_wrapper debugfs_vbios_blob;
885 struct debugfs_blob_wrapper debugfs_discovery_blob;
886 struct mutex srbm_mutex;
887 /* GRBM index mutex. Protects concurrent access to GRBM index */
888 struct mutex grbm_idx_mutex;
889 struct dev_pm_domain vga_pm_domain;
890 bool have_disp_power_ref;
891 bool have_atomics_support;
892
893 /* BIOS */
894 bool is_atom_fw;
895 uint8_t *bios;
896 uint32_t bios_size;
897 uint32_t bios_scratch_reg_offset;
898 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
899
900 /* Register/doorbell mmio */
901 resource_size_t rmmio_base;
902 resource_size_t rmmio_size;
903 void __iomem *rmmio;
904 /* protects concurrent MM_INDEX/DATA based register access */
905 spinlock_t mmio_idx_lock;
906 struct amdgpu_mmio_remap rmmio_remap;
907 /* protects concurrent SMC based register access */
908 spinlock_t smc_idx_lock;
909 amdgpu_rreg_t smc_rreg;
910 amdgpu_wreg_t smc_wreg;
911 /* protects concurrent PCIE register access */
912 spinlock_t pcie_idx_lock;
913 amdgpu_rreg_t pcie_rreg;
914 amdgpu_wreg_t pcie_wreg;
915 amdgpu_rreg_t pciep_rreg;
916 amdgpu_wreg_t pciep_wreg;
917 amdgpu_rreg_ext_t pcie_rreg_ext;
918 amdgpu_wreg_ext_t pcie_wreg_ext;
919 amdgpu_rreg64_t pcie_rreg64;
920 amdgpu_wreg64_t pcie_wreg64;
921 amdgpu_rreg64_ext_t pcie_rreg64_ext;
922 amdgpu_wreg64_ext_t pcie_wreg64_ext;
923 /* protects concurrent UVD register access */
924 spinlock_t uvd_ctx_idx_lock;
925 amdgpu_rreg_t uvd_ctx_rreg;
926 amdgpu_wreg_t uvd_ctx_wreg;
927 /* protects concurrent DIDT register access */
928 spinlock_t didt_idx_lock;
929 amdgpu_rreg_t didt_rreg;
930 amdgpu_wreg_t didt_wreg;
931 /* protects concurrent gc_cac register access */
932 spinlock_t gc_cac_idx_lock;
933 amdgpu_rreg_t gc_cac_rreg;
934 amdgpu_wreg_t gc_cac_wreg;
935 /* protects concurrent se_cac register access */
936 spinlock_t se_cac_idx_lock;
937 amdgpu_rreg_t se_cac_rreg;
938 amdgpu_wreg_t se_cac_wreg;
939 /* protects concurrent ENDPOINT (audio) register access */
940 spinlock_t audio_endpt_idx_lock;
941 amdgpu_block_rreg_t audio_endpt_rreg;
942 amdgpu_block_wreg_t audio_endpt_wreg;
943 struct amdgpu_doorbell doorbell;
944
945 /* clock/pll info */
946 struct amdgpu_clock clock;
947
948 /* MC */
949 struct amdgpu_gmc gmc;
950 struct amdgpu_gart gart;
951 dma_addr_t dummy_page_addr;
952 struct amdgpu_vm_manager vm_manager;
953 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
954 DECLARE_BITMAP(vmhubs_mask, AMDGPU_MAX_VMHUBS);
955
956 /* memory management */
957 struct amdgpu_mman mman;
958 struct amdgpu_mem_scratch mem_scratch;
959 struct amdgpu_wb wb;
960 atomic64_t num_bytes_moved;
961 atomic64_t num_evictions;
962 atomic64_t num_vram_cpu_page_faults;
963 atomic_t gpu_reset_counter;
964 atomic_t vram_lost_counter;
965
966 /* data for buffer migration throttling */
967 struct {
968 spinlock_t lock;
969 s64 last_update_us;
970 s64 accum_us; /* accumulated microseconds */
971 s64 accum_us_vis; /* for visible VRAM */
972 u32 log2_max_MBps;
973 } mm_stats;
974
975 /* display */
976 bool enable_virtual_display;
977 struct amdgpu_vkms_output *amdgpu_vkms_output;
978 struct amdgpu_mode_info mode_info;
979 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
980 struct delayed_work hotplug_work;
981 struct amdgpu_irq_src crtc_irq;
982 struct amdgpu_irq_src vline0_irq;
983 struct amdgpu_irq_src vupdate_irq;
984 struct amdgpu_irq_src pageflip_irq;
985 struct amdgpu_irq_src hpd_irq;
986 struct amdgpu_irq_src dmub_trace_irq;
987 struct amdgpu_irq_src dmub_outbox_irq;
988
989 /* rings */
990 u64 fence_context;
991 unsigned num_rings;
992 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
993 struct dma_fence __rcu *gang_submit;
994 bool ib_pool_ready;
995 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
996 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
997
998 /* interrupts */
999 struct amdgpu_irq irq;
1000
1001 /* powerplay */
1002 struct amd_powerplay powerplay;
1003 struct amdgpu_pm pm;
1004 u64 cg_flags;
1005 u32 pg_flags;
1006
1007 /* nbio */
1008 struct amdgpu_nbio nbio;
1009
1010 /* hdp */
1011 struct amdgpu_hdp hdp;
1012
1013 /* smuio */
1014 struct amdgpu_smuio smuio;
1015
1016 /* mmhub */
1017 struct amdgpu_mmhub mmhub;
1018
1019 /* gfxhub */
1020 struct amdgpu_gfxhub gfxhub;
1021
1022 /* gfx */
1023 struct amdgpu_gfx gfx;
1024
1025 /* sdma */
1026 struct amdgpu_sdma sdma;
1027
1028 /* lsdma */
1029 struct amdgpu_lsdma lsdma;
1030
1031 /* uvd */
1032 struct amdgpu_uvd uvd;
1033
1034 /* vce */
1035 struct amdgpu_vce vce;
1036
1037 /* vcn */
1038 struct amdgpu_vcn vcn;
1039
1040 /* jpeg */
1041 struct amdgpu_jpeg jpeg;
1042
1043 /* vpe */
1044 struct amdgpu_vpe vpe;
1045
1046 /* umsch */
1047 struct amdgpu_umsch_mm umsch_mm;
1048 bool enable_umsch_mm;
1049
1050 /* firmwares */
1051 struct amdgpu_firmware firmware;
1052
1053 /* PSP */
1054 struct psp_context psp;
1055
1056 /* GDS */
1057 struct amdgpu_gds gds;
1058
1059 /* for userq and VM fences */
1060 struct amdgpu_seq64 seq64;
1061
1062 /* KFD */
1063 struct amdgpu_kfd_dev kfd;
1064
1065 /* UMC */
1066 struct amdgpu_umc umc;
1067
1068 /* display related functionality */
1069 struct amdgpu_display_manager dm;
1070
1071#if defined(CONFIG_DRM_AMD_ISP)
1072 /* isp */
1073 struct amdgpu_isp isp;
1074#endif
1075
1076 /* mes */
1077 bool enable_mes;
1078 bool enable_mes_kiq;
1079 bool enable_uni_mes;
1080 struct amdgpu_mes mes;
1081 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
1082
1083 /* df */
1084 struct amdgpu_df df;
1085
1086 /* MCA */
1087 struct amdgpu_mca mca;
1088
1089 /* ACA */
1090 struct amdgpu_aca aca;
1091
1092 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1093 uint32_t harvest_ip_mask;
1094 int num_ip_blocks;
1095 struct mutex mn_lock;
1096 DECLARE_HASHTABLE(mn_hash, 7);
1097
1098 /* tracking pinned memory */
1099 atomic64_t vram_pin_size;
1100 atomic64_t visible_pin_size;
1101 atomic64_t gart_pin_size;
1102
1103 /* soc15 register offset based on ip, instance and segment */
1104 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
1105 struct amdgpu_ip_map_info ip_map;
1106
1107 /* delayed work_func for deferring clockgating during resume */
1108 struct delayed_work delayed_init_work;
1109
1110 struct amdgpu_virt virt;
1111
1112 /* record hw reset is performed */
1113 bool has_hw_reset;
1114 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1115
1116 /* s3/s4 mask */
1117 bool in_suspend;
1118 bool in_s3;
1119 bool in_s4;
1120 bool in_s0ix;
1121
1122 enum pp_mp1_state mp1_state;
1123 struct amdgpu_doorbell_index doorbell_index;
1124
1125 struct mutex notifier_lock;
1126
1127 int asic_reset_res;
1128 struct work_struct xgmi_reset_work;
1129 struct list_head reset_list;
1130
1131 long gfx_timeout;
1132 long sdma_timeout;
1133 long video_timeout;
1134 long compute_timeout;
1135 long psp_timeout;
1136
1137 uint64_t unique_id;
1138 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1139
1140 /* enable runtime pm on the device */
1141 bool in_runpm;
1142 bool has_pr3;
1143
1144 bool ucode_sysfs_en;
1145
1146 struct amdgpu_fru_info *fru_info;
1147 atomic_t throttling_logging_enabled;
1148 struct ratelimit_state throttling_logging_rs;
1149 uint32_t ras_hw_enabled;
1150 uint32_t ras_enabled;
1151
1152 bool no_hw_access;
1153 struct pci_saved_state *pci_state;
1154 pci_channel_state_t pci_channel_state;
1155
1156 /* Track auto wait count on s_barrier settings */
1157 bool barrier_has_auto_waitcnt;
1158
1159 struct amdgpu_reset_control *reset_cntl;
1160 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1161
1162 bool ram_is_direct_mapped;
1163
1164 struct list_head ras_list;
1165
1166 struct ip_discovery_top *ip_top;
1167
1168 struct amdgpu_reset_domain *reset_domain;
1169
1170 struct mutex benchmark_mutex;
1171
1172 bool scpm_enabled;
1173 uint32_t scpm_status;
1174
1175 struct work_struct reset_work;
1176
1177 bool job_hang;
1178 bool dc_enabled;
1179 /* Mask of active clusters */
1180 uint32_t aid_mask;
1181
1182 /* Debug */
1183 bool debug_vm;
1184 bool debug_largebar;
1185 bool debug_disable_soft_recovery;
1186 bool debug_use_vram_fw_buf;
1187 bool debug_enable_ras_aca;
1188 bool debug_exp_resets;
1189
1190 bool enforce_isolation[MAX_XCP];
1191 /* Added this mutex for cleaner shader isolation between GFX and compute processes */
1192 struct mutex enforce_isolation_mutex;
1193
1194 struct amdgpu_init_level *init_lvl;
1195};
1196
1197static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev,
1198 uint8_t ip, uint8_t inst)
1199{
1200 /* This considers only major/minor/rev and ignores
1201 * subrevision/variant fields.
1202 */
1203 return adev->ip_versions[ip][inst] & ~0xFFU;
1204}
1205
1206static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev,
1207 uint8_t ip, uint8_t inst)
1208{
1209 /* This returns full version - major/minor/rev/variant/subrevision */
1210 return adev->ip_versions[ip][inst];
1211}
1212
1213static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1214{
1215 return container_of(ddev, struct amdgpu_device, ddev);
1216}
1217
1218static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1219{
1220 return &adev->ddev;
1221}
1222
1223static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1224{
1225 return container_of(bdev, struct amdgpu_device, mman.bdev);
1226}
1227
1228int amdgpu_device_init(struct amdgpu_device *adev,
1229 uint32_t flags);
1230void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1231void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1232
1233int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1234
1235void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1236 void *buf, size_t size, bool write);
1237size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1238 void *buf, size_t size, bool write);
1239
1240void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1241 void *buf, size_t size, bool write);
1242uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev,
1243 uint32_t inst, uint32_t reg_addr, char reg_name[],
1244 uint32_t expected_value, uint32_t mask);
1245uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1246 uint32_t reg, uint32_t acc_flags);
1247u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev,
1248 u64 reg_addr);
1249uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev,
1250 uint32_t reg, uint32_t acc_flags,
1251 uint32_t xcc_id);
1252void amdgpu_device_wreg(struct amdgpu_device *adev,
1253 uint32_t reg, uint32_t v,
1254 uint32_t acc_flags);
1255void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev,
1256 u64 reg_addr, u32 reg_data);
1257void amdgpu_device_xcc_wreg(struct amdgpu_device *adev,
1258 uint32_t reg, uint32_t v,
1259 uint32_t acc_flags,
1260 uint32_t xcc_id);
1261void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1262 uint32_t reg, uint32_t v, uint32_t xcc_id);
1263void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1264uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1265
1266u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1267 u32 reg_addr);
1268u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1269 u32 reg_addr);
1270u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev,
1271 u64 reg_addr);
1272void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1273 u32 reg_addr, u32 reg_data);
1274void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1275 u32 reg_addr, u64 reg_data);
1276void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev,
1277 u64 reg_addr, u64 reg_data);
1278u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev);
1279bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1280bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1281
1282void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1283
1284int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1285 struct amdgpu_reset_context *reset_context);
1286
1287int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1288 struct amdgpu_reset_context *reset_context);
1289
1290int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context);
1291
1292int emu_soc_asic_init(struct amdgpu_device *adev);
1293
1294/*
1295 * Registers read & write functions.
1296 */
1297#define AMDGPU_REGS_NO_KIQ (1<<1)
1298#define AMDGPU_REGS_RLC (1<<2)
1299
1300#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1301#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1302
1303#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg), 0)
1304#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v), 0)
1305
1306#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1307#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1308
1309#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1310#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1311#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1312#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1313#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1314#define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst)
1315#define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst)
1316#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1317#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1318#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1319#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1320#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1321#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1322#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1323#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1324#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg))
1325#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v))
1326#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1327#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1328#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1329#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1330#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1331#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1332#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1333#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1334#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1335#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1336#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1337#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1338#define WREG32_P(reg, val, mask) \
1339 do { \
1340 uint32_t tmp_ = RREG32(reg); \
1341 tmp_ &= (mask); \
1342 tmp_ |= ((val) & ~(mask)); \
1343 WREG32(reg, tmp_); \
1344 } while (0)
1345#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1346#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1347#define WREG32_PLL_P(reg, val, mask) \
1348 do { \
1349 uint32_t tmp_ = RREG32_PLL(reg); \
1350 tmp_ &= (mask); \
1351 tmp_ |= ((val) & ~(mask)); \
1352 WREG32_PLL(reg, tmp_); \
1353 } while (0)
1354
1355#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1356 do { \
1357 u32 tmp = RREG32_SMC(_Reg); \
1358 tmp &= (_Mask); \
1359 tmp |= ((_Val) & ~(_Mask)); \
1360 WREG32_SMC(_Reg, tmp); \
1361 } while (0)
1362
1363#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1364
1365#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1366#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1367
1368#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1369 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1370 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1371
1372#define REG_GET_FIELD(value, reg, field) \
1373 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1374
1375#define WREG32_FIELD(reg, field, val) \
1376 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1377
1378#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1379 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1380
1381#define AMDGPU_GET_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> (l))
1382/*
1383 * BIOS helpers.
1384 */
1385#define RBIOS8(i) (adev->bios[i])
1386#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1387#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1388
1389/*
1390 * ASICs macro.
1391 */
1392#define amdgpu_asic_set_vga_state(adev, state) \
1393 ((adev)->asic_funcs->set_vga_state ? (adev)->asic_funcs->set_vga_state((adev), (state)) : 0)
1394#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1395#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1396#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1397#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1398#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1399#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1400#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1401#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1402#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1403#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1404#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1405#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1406#define amdgpu_asic_flush_hdp(adev, r) \
1407 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1408#define amdgpu_asic_invalidate_hdp(adev, r) \
1409 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1410 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : (void)0))
1411#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1412#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1413#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1414#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1415#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1416#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1417#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1418#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1419 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1420#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1421
1422#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter))
1423
1424#define BIT_MASK_UPPER(i) ((i) >= BITS_PER_LONG ? 0 : ~0UL << (i))
1425#define for_each_inst(i, inst_mask) \
1426 for (i = ffs(inst_mask); i-- != 0; \
1427 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
1428
1429/* Common functions */
1430bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1431bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1432int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1433 struct amdgpu_job *job,
1434 struct amdgpu_reset_context *reset_context);
1435void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1436int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1437bool amdgpu_device_need_post(struct amdgpu_device *adev);
1438bool amdgpu_device_seamless_boot_supported(struct amdgpu_device *adev);
1439bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1440
1441void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1442 u64 num_vis_bytes);
1443int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1444void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1445 const u32 *registers,
1446 const u32 array_size);
1447
1448int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1449bool amdgpu_device_supports_atpx(struct drm_device *dev);
1450bool amdgpu_device_supports_px(struct drm_device *dev);
1451bool amdgpu_device_supports_boco(struct drm_device *dev);
1452bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1453int amdgpu_device_supports_baco(struct drm_device *dev);
1454void amdgpu_device_detect_runtime_pm_mode(struct amdgpu_device *adev);
1455bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1456 struct amdgpu_device *peer_adev);
1457int amdgpu_device_baco_enter(struct drm_device *dev);
1458int amdgpu_device_baco_exit(struct drm_device *dev);
1459
1460void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1461 struct amdgpu_ring *ring);
1462void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1463 struct amdgpu_ring *ring);
1464
1465void amdgpu_device_halt(struct amdgpu_device *adev);
1466u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1467 u32 reg);
1468void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1469 u32 reg, u32 v);
1470struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev);
1471struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1472 struct dma_fence *gang);
1473bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1474ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
1475ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
1476
1477/* atpx handler */
1478#if defined(CONFIG_VGA_SWITCHEROO)
1479void amdgpu_register_atpx_handler(void);
1480void amdgpu_unregister_atpx_handler(void);
1481bool amdgpu_has_atpx_dgpu_power_cntl(void);
1482bool amdgpu_is_atpx_hybrid(void);
1483bool amdgpu_has_atpx(void);
1484#else
1485static inline void amdgpu_register_atpx_handler(void) {}
1486static inline void amdgpu_unregister_atpx_handler(void) {}
1487static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1488static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1489static inline bool amdgpu_has_atpx(void) { return false; }
1490#endif
1491
1492/*
1493 * KMS
1494 */
1495extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1496extern const int amdgpu_max_kms_ioctl;
1497
1498int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1499void amdgpu_driver_unload_kms(struct drm_device *dev);
1500int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1501void amdgpu_driver_postclose_kms(struct drm_device *dev,
1502 struct drm_file *file_priv);
1503void amdgpu_driver_release_kms(struct drm_device *dev);
1504
1505int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1506int amdgpu_device_prepare(struct drm_device *dev);
1507int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1508int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1509u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1510int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1511void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1512int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1513 struct drm_file *filp);
1514
1515/*
1516 * functions used by amdgpu_encoder.c
1517 */
1518struct amdgpu_afmt_acr {
1519 u32 clock;
1520
1521 int n_32khz;
1522 int cts_32khz;
1523
1524 int n_44_1khz;
1525 int cts_44_1khz;
1526
1527 int n_48khz;
1528 int cts_48khz;
1529
1530};
1531
1532struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1533
1534/* amdgpu_acpi.c */
1535
1536struct amdgpu_numa_info {
1537 uint64_t size;
1538 int pxm;
1539 int nid;
1540};
1541
1542/* ATCS Device/Driver State */
1543#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1544#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1545#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1546#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1547
1548#if defined(CONFIG_ACPI)
1549int amdgpu_acpi_init(struct amdgpu_device *adev);
1550void amdgpu_acpi_fini(struct amdgpu_device *adev);
1551bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1552bool amdgpu_acpi_is_power_shift_control_supported(void);
1553int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1554 u8 perf_req, bool advertise);
1555int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1556 u8 dev_state, bool drv_state);
1557int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1558int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1559int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
1560 u64 *tmr_size);
1561int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id,
1562 struct amdgpu_numa_info *numa_info);
1563
1564void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1565bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1566void amdgpu_acpi_detect(void);
1567void amdgpu_acpi_release(void);
1568#else
1569static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1570static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev,
1571 u64 *tmr_offset, u64 *tmr_size)
1572{
1573 return -EINVAL;
1574}
1575static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev,
1576 int xcc_id,
1577 struct amdgpu_numa_info *numa_info)
1578{
1579 return -EINVAL;
1580}
1581static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1582static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1583static inline void amdgpu_acpi_detect(void) { }
1584static inline void amdgpu_acpi_release(void) { }
1585static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1586static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1587 u8 dev_state, bool drv_state) { return 0; }
1588static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1589 enum amdgpu_ss ss_state) { return 0; }
1590static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { }
1591#endif
1592
1593#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1594bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1595bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1596void amdgpu_choose_low_power_state(struct amdgpu_device *adev);
1597#else
1598static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1599static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1600static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { }
1601#endif
1602
1603void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1604void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1605
1606pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1607 pci_channel_state_t state);
1608pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1609pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1610void amdgpu_pci_resume(struct pci_dev *pdev);
1611
1612bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1613bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1614
1615bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1616
1617int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1618 enum amd_clockgating_state state);
1619int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1620 enum amd_powergating_state state);
1621
1622static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1623{
1624 return amdgpu_gpu_recovery != 0 &&
1625 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1626 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1627 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1628 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1629}
1630
1631#include "amdgpu_object.h"
1632
1633static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1634{
1635 return adev->gmc.tmz_enabled;
1636}
1637
1638int amdgpu_in_reset(struct amdgpu_device *adev);
1639
1640extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1641extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1642extern const struct attribute_group amdgpu_flash_attr_group;
1643
1644void amdgpu_set_init_level(struct amdgpu_device *adev,
1645 enum amdgpu_init_lvl_id lvl);
1646#endif