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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#include "amdgpu_ctx.h"
32
33#include <linux/atomic.h>
34#include <linux/wait.h>
35#include <linux/list.h>
36#include <linux/kref.h>
37#include <linux/rbtree.h>
38#include <linux/hashtable.h>
39#include <linux/dma-fence.h>
40
41#include <drm/ttm/ttm_bo_api.h>
42#include <drm/ttm/ttm_bo_driver.h>
43#include <drm/ttm/ttm_placement.h>
44#include <drm/ttm/ttm_module.h>
45#include <drm/ttm/ttm_execbuf_util.h>
46
47#include <drm/amdgpu_drm.h>
48#include <drm/drm_gem.h>
49#include <drm/drm_ioctl.h>
50#include <drm/gpu_scheduler.h>
51
52#include <kgd_kfd_interface.h>
53#include "dm_pp_interface.h"
54#include "kgd_pp_interface.h"
55
56#include "amd_shared.h"
57#include "amdgpu_mode.h"
58#include "amdgpu_ih.h"
59#include "amdgpu_irq.h"
60#include "amdgpu_ucode.h"
61#include "amdgpu_ttm.h"
62#include "amdgpu_psp.h"
63#include "amdgpu_gds.h"
64#include "amdgpu_sync.h"
65#include "amdgpu_ring.h"
66#include "amdgpu_vm.h"
67#include "amdgpu_dpm.h"
68#include "amdgpu_acp.h"
69#include "amdgpu_uvd.h"
70#include "amdgpu_vce.h"
71#include "amdgpu_vcn.h"
72#include "amdgpu_mn.h"
73#include "amdgpu_gmc.h"
74#include "amdgpu_gfx.h"
75#include "amdgpu_sdma.h"
76#include "amdgpu_dm.h"
77#include "amdgpu_virt.h"
78#include "amdgpu_csa.h"
79#include "amdgpu_gart.h"
80#include "amdgpu_debugfs.h"
81#include "amdgpu_job.h"
82#include "amdgpu_bo_list.h"
83#include "amdgpu_gem.h"
84#include "amdgpu_doorbell.h"
85#include "amdgpu_amdkfd.h"
86#include "amdgpu_smu.h"
87#include "amdgpu_discovery.h"
88#include "amdgpu_mes.h"
89#include "amdgpu_umc.h"
90#include "amdgpu_mmhub.h"
91
92#define MAX_GPU_INSTANCE 16
93
94struct amdgpu_gpu_instance
95{
96 struct amdgpu_device *adev;
97 int mgpu_fan_enabled;
98};
99
100struct amdgpu_mgpu_info
101{
102 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
103 struct mutex mutex;
104 uint32_t num_gpu;
105 uint32_t num_dgpu;
106 uint32_t num_apu;
107};
108
109/*
110 * Modules parameters.
111 */
112extern int amdgpu_modeset;
113extern int amdgpu_vram_limit;
114extern int amdgpu_vis_vram_limit;
115extern int amdgpu_gart_size;
116extern int amdgpu_gtt_size;
117extern int amdgpu_moverate;
118extern int amdgpu_benchmarking;
119extern int amdgpu_testing;
120extern int amdgpu_audio;
121extern int amdgpu_disp_priority;
122extern int amdgpu_hw_i2c;
123extern int amdgpu_pcie_gen2;
124extern int amdgpu_msi;
125extern int amdgpu_dpm;
126extern int amdgpu_fw_load_type;
127extern int amdgpu_aspm;
128extern int amdgpu_runtime_pm;
129extern uint amdgpu_ip_block_mask;
130extern int amdgpu_bapm;
131extern int amdgpu_deep_color;
132extern int amdgpu_vm_size;
133extern int amdgpu_vm_block_size;
134extern int amdgpu_vm_fragment_size;
135extern int amdgpu_vm_fault_stop;
136extern int amdgpu_vm_debug;
137extern int amdgpu_vm_update_mode;
138extern int amdgpu_dc;
139extern int amdgpu_sched_jobs;
140extern int amdgpu_sched_hw_submission;
141extern uint amdgpu_pcie_gen_cap;
142extern uint amdgpu_pcie_lane_cap;
143extern uint amdgpu_cg_mask;
144extern uint amdgpu_pg_mask;
145extern uint amdgpu_sdma_phase_quantum;
146extern char *amdgpu_disable_cu;
147extern char *amdgpu_virtual_display;
148extern uint amdgpu_pp_feature_mask;
149extern int amdgpu_ngg;
150extern int amdgpu_prim_buf_per_se;
151extern int amdgpu_pos_buf_per_se;
152extern int amdgpu_cntl_sb_buf_per_se;
153extern int amdgpu_param_buf_per_se;
154extern int amdgpu_job_hang_limit;
155extern int amdgpu_lbpw;
156extern int amdgpu_compute_multipipe;
157extern int amdgpu_gpu_recovery;
158extern int amdgpu_emu_mode;
159extern uint amdgpu_smu_memory_pool_size;
160extern uint amdgpu_dc_feature_mask;
161extern uint amdgpu_dm_abm_level;
162extern struct amdgpu_mgpu_info mgpu_info;
163extern int amdgpu_ras_enable;
164extern uint amdgpu_ras_mask;
165extern int amdgpu_async_gfx_ring;
166extern int amdgpu_mcbp;
167extern int amdgpu_discovery;
168extern int amdgpu_mes;
169extern int amdgpu_noretry;
170
171#ifdef CONFIG_DRM_AMDGPU_SI
172extern int amdgpu_si_support;
173#endif
174#ifdef CONFIG_DRM_AMDGPU_CIK
175extern int amdgpu_cik_support;
176#endif
177
178#define AMDGPU_VM_MAX_NUM_CTX 4096
179#define AMDGPU_SG_THRESHOLD (256*1024*1024)
180#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
181#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
182#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
183#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
184/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
185#define AMDGPU_IB_POOL_SIZE 16
186#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
187#define AMDGPUFB_CONN_LIMIT 4
188#define AMDGPU_BIOS_NUM_SCRATCH 16
189
190/* hard reset data */
191#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
192
193/* reset flags */
194#define AMDGPU_RESET_GFX (1 << 0)
195#define AMDGPU_RESET_COMPUTE (1 << 1)
196#define AMDGPU_RESET_DMA (1 << 2)
197#define AMDGPU_RESET_CP (1 << 3)
198#define AMDGPU_RESET_GRBM (1 << 4)
199#define AMDGPU_RESET_DMA1 (1 << 5)
200#define AMDGPU_RESET_RLC (1 << 6)
201#define AMDGPU_RESET_SEM (1 << 7)
202#define AMDGPU_RESET_IH (1 << 8)
203#define AMDGPU_RESET_VMC (1 << 9)
204#define AMDGPU_RESET_MC (1 << 10)
205#define AMDGPU_RESET_DISPLAY (1 << 11)
206#define AMDGPU_RESET_UVD (1 << 12)
207#define AMDGPU_RESET_VCE (1 << 13)
208#define AMDGPU_RESET_VCE1 (1 << 14)
209
210/* max cursor sizes (in pixels) */
211#define CIK_CURSOR_WIDTH 128
212#define CIK_CURSOR_HEIGHT 128
213
214struct amdgpu_device;
215struct amdgpu_ib;
216struct amdgpu_cs_parser;
217struct amdgpu_job;
218struct amdgpu_irq_src;
219struct amdgpu_fpriv;
220struct amdgpu_bo_va_mapping;
221struct amdgpu_atif;
222struct kfd_vm_fault_info;
223
224enum amdgpu_cp_irq {
225 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
226 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
227 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
228 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
229 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
230 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
231 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
232 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
233 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
234 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
235
236 AMDGPU_CP_IRQ_LAST
237};
238
239enum amdgpu_thermal_irq {
240 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
241 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
242
243 AMDGPU_THERMAL_IRQ_LAST
244};
245
246enum amdgpu_kiq_irq {
247 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
248 AMDGPU_CP_KIQ_IRQ_LAST
249};
250
251#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
252#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
253#define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */
254
255int amdgpu_device_ip_set_clockgating_state(void *dev,
256 enum amd_ip_block_type block_type,
257 enum amd_clockgating_state state);
258int amdgpu_device_ip_set_powergating_state(void *dev,
259 enum amd_ip_block_type block_type,
260 enum amd_powergating_state state);
261void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
262 u32 *flags);
263int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
264 enum amd_ip_block_type block_type);
265bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
266 enum amd_ip_block_type block_type);
267
268#define AMDGPU_MAX_IP_NUM 16
269
270struct amdgpu_ip_block_status {
271 bool valid;
272 bool sw;
273 bool hw;
274 bool late_initialized;
275 bool hang;
276};
277
278struct amdgpu_ip_block_version {
279 const enum amd_ip_block_type type;
280 const u32 major;
281 const u32 minor;
282 const u32 rev;
283 const struct amd_ip_funcs *funcs;
284};
285
286struct amdgpu_ip_block {
287 struct amdgpu_ip_block_status status;
288 const struct amdgpu_ip_block_version *version;
289};
290
291int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
292 enum amd_ip_block_type type,
293 u32 major, u32 minor);
294
295struct amdgpu_ip_block *
296amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
297 enum amd_ip_block_type type);
298
299int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
300 const struct amdgpu_ip_block_version *ip_block_version);
301
302/*
303 * BIOS.
304 */
305bool amdgpu_get_bios(struct amdgpu_device *adev);
306bool amdgpu_read_bios(struct amdgpu_device *adev);
307
308/*
309 * Clocks
310 */
311
312#define AMDGPU_MAX_PPLL 3
313
314struct amdgpu_clock {
315 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
316 struct amdgpu_pll spll;
317 struct amdgpu_pll mpll;
318 /* 10 Khz units */
319 uint32_t default_mclk;
320 uint32_t default_sclk;
321 uint32_t default_dispclk;
322 uint32_t current_dispclk;
323 uint32_t dp_extclk;
324 uint32_t max_pixel_clock;
325};
326
327/* sub-allocation manager, it has to be protected by another lock.
328 * By conception this is an helper for other part of the driver
329 * like the indirect buffer or semaphore, which both have their
330 * locking.
331 *
332 * Principe is simple, we keep a list of sub allocation in offset
333 * order (first entry has offset == 0, last entry has the highest
334 * offset).
335 *
336 * When allocating new object we first check if there is room at
337 * the end total_size - (last_object_offset + last_object_size) >=
338 * alloc_size. If so we allocate new object there.
339 *
340 * When there is not enough room at the end, we start waiting for
341 * each sub object until we reach object_offset+object_size >=
342 * alloc_size, this object then become the sub object we return.
343 *
344 * Alignment can't be bigger than page size.
345 *
346 * Hole are not considered for allocation to keep things simple.
347 * Assumption is that there won't be hole (all object on same
348 * alignment).
349 */
350
351#define AMDGPU_SA_NUM_FENCE_LISTS 32
352
353struct amdgpu_sa_manager {
354 wait_queue_head_t wq;
355 struct amdgpu_bo *bo;
356 struct list_head *hole;
357 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
358 struct list_head olist;
359 unsigned size;
360 uint64_t gpu_addr;
361 void *cpu_ptr;
362 uint32_t domain;
363 uint32_t align;
364};
365
366/* sub-allocation buffer */
367struct amdgpu_sa_bo {
368 struct list_head olist;
369 struct list_head flist;
370 struct amdgpu_sa_manager *manager;
371 unsigned soffset;
372 unsigned eoffset;
373 struct dma_fence *fence;
374};
375
376int amdgpu_fence_slab_init(void);
377void amdgpu_fence_slab_fini(void);
378
379/*
380 * IRQS.
381 */
382
383struct amdgpu_flip_work {
384 struct delayed_work flip_work;
385 struct work_struct unpin_work;
386 struct amdgpu_device *adev;
387 int crtc_id;
388 u32 target_vblank;
389 uint64_t base;
390 struct drm_pending_vblank_event *event;
391 struct amdgpu_bo *old_abo;
392 struct dma_fence *excl;
393 unsigned shared_count;
394 struct dma_fence **shared;
395 struct dma_fence_cb cb;
396 bool async;
397};
398
399
400/*
401 * CP & rings.
402 */
403
404struct amdgpu_ib {
405 struct amdgpu_sa_bo *sa_bo;
406 uint32_t length_dw;
407 uint64_t gpu_addr;
408 uint32_t *ptr;
409 uint32_t flags;
410};
411
412extern const struct drm_sched_backend_ops amdgpu_sched_ops;
413
414/*
415 * file private structure
416 */
417
418struct amdgpu_fpriv {
419 struct amdgpu_vm vm;
420 struct amdgpu_bo_va *prt_va;
421 struct amdgpu_bo_va *csa_va;
422 struct mutex bo_list_lock;
423 struct idr bo_list_handles;
424 struct amdgpu_ctx_mgr ctx_mgr;
425};
426
427int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
428int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
429
430int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
431 unsigned size, struct amdgpu_ib *ib);
432void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
433 struct dma_fence *f);
434int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
435 struct amdgpu_ib *ibs, struct amdgpu_job *job,
436 struct dma_fence **f);
437int amdgpu_ib_pool_init(struct amdgpu_device *adev);
438void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
439int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
440
441/*
442 * CS.
443 */
444struct amdgpu_cs_chunk {
445 uint32_t chunk_id;
446 uint32_t length_dw;
447 void *kdata;
448};
449
450struct amdgpu_cs_post_dep {
451 struct drm_syncobj *syncobj;
452 struct dma_fence_chain *chain;
453 u64 point;
454};
455
456struct amdgpu_cs_parser {
457 struct amdgpu_device *adev;
458 struct drm_file *filp;
459 struct amdgpu_ctx *ctx;
460
461 /* chunks */
462 unsigned nchunks;
463 struct amdgpu_cs_chunk *chunks;
464
465 /* scheduler job object */
466 struct amdgpu_job *job;
467 struct drm_sched_entity *entity;
468
469 /* buffer objects */
470 struct ww_acquire_ctx ticket;
471 struct amdgpu_bo_list *bo_list;
472 struct amdgpu_mn *mn;
473 struct amdgpu_bo_list_entry vm_pd;
474 struct list_head validated;
475 struct dma_fence *fence;
476 uint64_t bytes_moved_threshold;
477 uint64_t bytes_moved_vis_threshold;
478 uint64_t bytes_moved;
479 uint64_t bytes_moved_vis;
480 struct amdgpu_bo_list_entry *evictable;
481
482 /* user fence */
483 struct amdgpu_bo_list_entry uf_entry;
484
485 unsigned num_post_deps;
486 struct amdgpu_cs_post_dep *post_deps;
487};
488
489static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
490 uint32_t ib_idx, int idx)
491{
492 return p->job->ibs[ib_idx].ptr[idx];
493}
494
495static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
496 uint32_t ib_idx, int idx,
497 uint32_t value)
498{
499 p->job->ibs[ib_idx].ptr[idx] = value;
500}
501
502/*
503 * Writeback
504 */
505#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */
506
507struct amdgpu_wb {
508 struct amdgpu_bo *wb_obj;
509 volatile uint32_t *wb;
510 uint64_t gpu_addr;
511 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
512 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
513};
514
515int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
516void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
517
518/*
519 * Benchmarking
520 */
521void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
522
523
524/*
525 * Testing
526 */
527void amdgpu_test_moves(struct amdgpu_device *adev);
528
529/*
530 * ASIC specific register table accessible by UMD
531 */
532struct amdgpu_allowed_register_entry {
533 uint32_t reg_offset;
534 bool grbm_indexed;
535};
536
537enum amd_reset_method {
538 AMD_RESET_METHOD_LEGACY = 0,
539 AMD_RESET_METHOD_MODE0,
540 AMD_RESET_METHOD_MODE1,
541 AMD_RESET_METHOD_MODE2,
542 AMD_RESET_METHOD_BACO
543};
544
545/*
546 * ASIC specific functions.
547 */
548struct amdgpu_asic_funcs {
549 bool (*read_disabled_bios)(struct amdgpu_device *adev);
550 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
551 u8 *bios, u32 length_bytes);
552 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
553 u32 sh_num, u32 reg_offset, u32 *value);
554 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
555 int (*reset)(struct amdgpu_device *adev);
556 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
557 /* get the reference clock */
558 u32 (*get_xclk)(struct amdgpu_device *adev);
559 /* MM block clocks */
560 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
561 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
562 /* static power management */
563 int (*get_pcie_lanes)(struct amdgpu_device *adev);
564 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
565 /* get config memsize register */
566 u32 (*get_config_memsize)(struct amdgpu_device *adev);
567 /* flush hdp write queue */
568 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
569 /* invalidate hdp read cache */
570 void (*invalidate_hdp)(struct amdgpu_device *adev,
571 struct amdgpu_ring *ring);
572 /* check if the asic needs a full reset of if soft reset will work */
573 bool (*need_full_reset)(struct amdgpu_device *adev);
574 /* initialize doorbell layout for specific asic*/
575 void (*init_doorbell_index)(struct amdgpu_device *adev);
576 /* PCIe bandwidth usage */
577 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
578 uint64_t *count1);
579 /* do we need to reset the asic at init time (e.g., kexec) */
580 bool (*need_reset_on_init)(struct amdgpu_device *adev);
581 /* PCIe replay counter */
582 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
583};
584
585/*
586 * IOCTL.
587 */
588int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
589 struct drm_file *filp);
590
591int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
592int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
593 struct drm_file *filp);
594int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
595int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
596 struct drm_file *filp);
597
598/* VRAM scratch page for HDP bug, default vram page */
599struct amdgpu_vram_scratch {
600 struct amdgpu_bo *robj;
601 volatile uint32_t *ptr;
602 u64 gpu_addr;
603};
604
605/*
606 * ACPI
607 */
608struct amdgpu_atcs_functions {
609 bool get_ext_state;
610 bool pcie_perf_req;
611 bool pcie_dev_rdy;
612 bool pcie_bus_width;
613};
614
615struct amdgpu_atcs {
616 struct amdgpu_atcs_functions functions;
617};
618
619/*
620 * Firmware VRAM reservation
621 */
622struct amdgpu_fw_vram_usage {
623 u64 start_offset;
624 u64 size;
625 struct amdgpu_bo *reserved_bo;
626 void *va;
627};
628
629/*
630 * CGS
631 */
632struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
633void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
634
635/*
636 * Core structure, functions and helpers.
637 */
638typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
639typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
640
641typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
642typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
643
644typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
645typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
646
647
648/*
649 * amdgpu nbio functions
650 *
651 */
652struct nbio_hdp_flush_reg {
653 u32 ref_and_mask_cp0;
654 u32 ref_and_mask_cp1;
655 u32 ref_and_mask_cp2;
656 u32 ref_and_mask_cp3;
657 u32 ref_and_mask_cp4;
658 u32 ref_and_mask_cp5;
659 u32 ref_and_mask_cp6;
660 u32 ref_and_mask_cp7;
661 u32 ref_and_mask_cp8;
662 u32 ref_and_mask_cp9;
663 u32 ref_and_mask_sdma0;
664 u32 ref_and_mask_sdma1;
665 u32 ref_and_mask_sdma2;
666 u32 ref_and_mask_sdma3;
667 u32 ref_and_mask_sdma4;
668 u32 ref_and_mask_sdma5;
669 u32 ref_and_mask_sdma6;
670 u32 ref_and_mask_sdma7;
671};
672
673struct amdgpu_mmio_remap {
674 u32 reg_offset;
675 resource_size_t bus_addr;
676};
677
678struct amdgpu_nbio_funcs {
679 const struct nbio_hdp_flush_reg *hdp_flush_reg;
680 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
681 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
682 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
683 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
684 u32 (*get_rev_id)(struct amdgpu_device *adev);
685 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
686 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
687 u32 (*get_memsize)(struct amdgpu_device *adev);
688 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
689 bool use_doorbell, int doorbell_index, int doorbell_size);
690 void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
691 int doorbell_index, int instance);
692 void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
693 bool enable);
694 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
695 bool enable);
696 void (*ih_doorbell_range)(struct amdgpu_device *adev,
697 bool use_doorbell, int doorbell_index);
698 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
699 bool enable);
700 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
701 bool enable);
702 void (*get_clockgating_state)(struct amdgpu_device *adev,
703 u32 *flags);
704 void (*ih_control)(struct amdgpu_device *adev);
705 void (*init_registers)(struct amdgpu_device *adev);
706 void (*detect_hw_virt)(struct amdgpu_device *adev);
707 void (*remap_hdp_registers)(struct amdgpu_device *adev);
708};
709
710struct amdgpu_df_funcs {
711 void (*sw_init)(struct amdgpu_device *adev);
712 void (*enable_broadcast_mode)(struct amdgpu_device *adev,
713 bool enable);
714 u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
715 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
716 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
717 bool enable);
718 void (*get_clockgating_state)(struct amdgpu_device *adev,
719 u32 *flags);
720 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
721 bool enable);
722 int (*pmc_start)(struct amdgpu_device *adev, uint64_t config,
723 int is_enable);
724 int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config,
725 int is_disable);
726 void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config,
727 uint64_t *count);
728 uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val);
729 void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val,
730 uint32_t ficadl_val, uint32_t ficadh_val);
731};
732/* Define the HW IP blocks will be used in driver , add more if necessary */
733enum amd_hw_ip_block_type {
734 GC_HWIP = 1,
735 HDP_HWIP,
736 SDMA0_HWIP,
737 SDMA1_HWIP,
738 SDMA2_HWIP,
739 SDMA3_HWIP,
740 SDMA4_HWIP,
741 SDMA5_HWIP,
742 SDMA6_HWIP,
743 SDMA7_HWIP,
744 MMHUB_HWIP,
745 ATHUB_HWIP,
746 NBIO_HWIP,
747 MP0_HWIP,
748 MP1_HWIP,
749 UVD_HWIP,
750 VCN_HWIP = UVD_HWIP,
751 VCE_HWIP,
752 DF_HWIP,
753 DCE_HWIP,
754 OSSSYS_HWIP,
755 SMUIO_HWIP,
756 PWR_HWIP,
757 NBIF_HWIP,
758 THM_HWIP,
759 CLK_HWIP,
760 UMC_HWIP,
761 RSMU_HWIP,
762 MAX_HWIP
763};
764
765#define HWIP_MAX_INSTANCE 8
766
767struct amd_powerplay {
768 void *pp_handle;
769 const struct amd_pm_funcs *pp_funcs;
770};
771
772#define AMDGPU_RESET_MAGIC_NUM 64
773#define AMDGPU_MAX_DF_PERFMONS 4
774struct amdgpu_device {
775 struct device *dev;
776 struct drm_device *ddev;
777 struct pci_dev *pdev;
778
779#ifdef CONFIG_DRM_AMD_ACP
780 struct amdgpu_acp acp;
781#endif
782
783 /* ASIC */
784 enum amd_asic_type asic_type;
785 uint32_t family;
786 uint32_t rev_id;
787 uint32_t external_rev_id;
788 unsigned long flags;
789 int usec_timeout;
790 const struct amdgpu_asic_funcs *asic_funcs;
791 bool shutdown;
792 bool need_swiotlb;
793 bool accel_working;
794 struct notifier_block acpi_nb;
795 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
796 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
797 unsigned debugfs_count;
798#if defined(CONFIG_DEBUG_FS)
799 struct dentry *debugfs_preempt;
800 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
801#endif
802 struct amdgpu_atif *atif;
803 struct amdgpu_atcs atcs;
804 struct mutex srbm_mutex;
805 /* GRBM index mutex. Protects concurrent access to GRBM index */
806 struct mutex grbm_idx_mutex;
807 struct dev_pm_domain vga_pm_domain;
808 bool have_disp_power_ref;
809 bool have_atomics_support;
810
811 /* BIOS */
812 bool is_atom_fw;
813 uint8_t *bios;
814 uint32_t bios_size;
815 struct amdgpu_bo *stolen_vga_memory;
816 uint32_t bios_scratch_reg_offset;
817 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
818
819 /* Register/doorbell mmio */
820 resource_size_t rmmio_base;
821 resource_size_t rmmio_size;
822 void __iomem *rmmio;
823 /* protects concurrent MM_INDEX/DATA based register access */
824 spinlock_t mmio_idx_lock;
825 struct amdgpu_mmio_remap rmmio_remap;
826 /* protects concurrent SMC based register access */
827 spinlock_t smc_idx_lock;
828 amdgpu_rreg_t smc_rreg;
829 amdgpu_wreg_t smc_wreg;
830 /* protects concurrent PCIE register access */
831 spinlock_t pcie_idx_lock;
832 amdgpu_rreg_t pcie_rreg;
833 amdgpu_wreg_t pcie_wreg;
834 amdgpu_rreg_t pciep_rreg;
835 amdgpu_wreg_t pciep_wreg;
836 amdgpu_rreg64_t pcie_rreg64;
837 amdgpu_wreg64_t pcie_wreg64;
838 /* protects concurrent UVD register access */
839 spinlock_t uvd_ctx_idx_lock;
840 amdgpu_rreg_t uvd_ctx_rreg;
841 amdgpu_wreg_t uvd_ctx_wreg;
842 /* protects concurrent DIDT register access */
843 spinlock_t didt_idx_lock;
844 amdgpu_rreg_t didt_rreg;
845 amdgpu_wreg_t didt_wreg;
846 /* protects concurrent gc_cac register access */
847 spinlock_t gc_cac_idx_lock;
848 amdgpu_rreg_t gc_cac_rreg;
849 amdgpu_wreg_t gc_cac_wreg;
850 /* protects concurrent se_cac register access */
851 spinlock_t se_cac_idx_lock;
852 amdgpu_rreg_t se_cac_rreg;
853 amdgpu_wreg_t se_cac_wreg;
854 /* protects concurrent ENDPOINT (audio) register access */
855 spinlock_t audio_endpt_idx_lock;
856 amdgpu_block_rreg_t audio_endpt_rreg;
857 amdgpu_block_wreg_t audio_endpt_wreg;
858 void __iomem *rio_mem;
859 resource_size_t rio_mem_size;
860 struct amdgpu_doorbell doorbell;
861
862 /* clock/pll info */
863 struct amdgpu_clock clock;
864
865 /* MC */
866 struct amdgpu_gmc gmc;
867 struct amdgpu_gart gart;
868 dma_addr_t dummy_page_addr;
869 struct amdgpu_vm_manager vm_manager;
870 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
871 unsigned num_vmhubs;
872
873 /* memory management */
874 struct amdgpu_mman mman;
875 struct amdgpu_vram_scratch vram_scratch;
876 struct amdgpu_wb wb;
877 atomic64_t num_bytes_moved;
878 atomic64_t num_evictions;
879 atomic64_t num_vram_cpu_page_faults;
880 atomic_t gpu_reset_counter;
881 atomic_t vram_lost_counter;
882
883 /* data for buffer migration throttling */
884 struct {
885 spinlock_t lock;
886 s64 last_update_us;
887 s64 accum_us; /* accumulated microseconds */
888 s64 accum_us_vis; /* for visible VRAM */
889 u32 log2_max_MBps;
890 } mm_stats;
891
892 /* display */
893 bool enable_virtual_display;
894 struct amdgpu_mode_info mode_info;
895 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
896 struct work_struct hotplug_work;
897 struct amdgpu_irq_src crtc_irq;
898 struct amdgpu_irq_src vupdate_irq;
899 struct amdgpu_irq_src pageflip_irq;
900 struct amdgpu_irq_src hpd_irq;
901
902 /* rings */
903 u64 fence_context;
904 unsigned num_rings;
905 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
906 bool ib_pool_ready;
907 struct amdgpu_sa_manager ring_tmp_bo;
908
909 /* interrupts */
910 struct amdgpu_irq irq;
911
912 /* powerplay */
913 struct amd_powerplay powerplay;
914 bool pp_force_state_enabled;
915
916 /* smu */
917 struct smu_context smu;
918
919 /* dpm */
920 struct amdgpu_pm pm;
921 u32 cg_flags;
922 u32 pg_flags;
923
924 /* gfx */
925 struct amdgpu_gfx gfx;
926
927 /* sdma */
928 struct amdgpu_sdma sdma;
929
930 /* uvd */
931 struct amdgpu_uvd uvd;
932
933 /* vce */
934 struct amdgpu_vce vce;
935
936 /* vcn */
937 struct amdgpu_vcn vcn;
938
939 /* firmwares */
940 struct amdgpu_firmware firmware;
941
942 /* PSP */
943 struct psp_context psp;
944
945 /* GDS */
946 struct amdgpu_gds gds;
947
948 /* KFD */
949 struct amdgpu_kfd_dev kfd;
950
951 /* UMC */
952 struct amdgpu_umc umc;
953
954 /* display related functionality */
955 struct amdgpu_display_manager dm;
956
957 /* discovery */
958 uint8_t *discovery;
959
960 /* mes */
961 bool enable_mes;
962 struct amdgpu_mes mes;
963
964 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
965 int num_ip_blocks;
966 struct mutex mn_lock;
967 DECLARE_HASHTABLE(mn_hash, 7);
968
969 /* tracking pinned memory */
970 atomic64_t vram_pin_size;
971 atomic64_t visible_pin_size;
972 atomic64_t gart_pin_size;
973
974 /* soc15 register offset based on ip, instance and segment */
975 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
976
977 const struct amdgpu_nbio_funcs *nbio_funcs;
978 const struct amdgpu_df_funcs *df_funcs;
979 const struct amdgpu_mmhub_funcs *mmhub_funcs;
980
981 /* delayed work_func for deferring clockgating during resume */
982 struct delayed_work delayed_init_work;
983
984 struct amdgpu_virt virt;
985 /* firmware VRAM reservation */
986 struct amdgpu_fw_vram_usage fw_vram_usage;
987
988 /* link all shadow bo */
989 struct list_head shadow_list;
990 struct mutex shadow_list_lock;
991 /* keep an lru list of rings by HW IP */
992 struct list_head ring_lru_list;
993 spinlock_t ring_lru_list_lock;
994
995 /* record hw reset is performed */
996 bool has_hw_reset;
997 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
998
999 /* s3/s4 mask */
1000 bool in_suspend;
1001
1002 /* record last mm index being written through WREG32*/
1003 unsigned long last_mm_index;
1004 bool in_gpu_reset;
1005 enum pp_mp1_state mp1_state;
1006 struct mutex lock_reset;
1007 struct amdgpu_doorbell_index doorbell_index;
1008
1009 int asic_reset_res;
1010 struct work_struct xgmi_reset_work;
1011
1012 bool in_baco_reset;
1013
1014 long gfx_timeout;
1015 long sdma_timeout;
1016 long video_timeout;
1017 long compute_timeout;
1018
1019 uint64_t unique_id;
1020 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1021};
1022
1023static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1024{
1025 return container_of(bdev, struct amdgpu_device, mman.bdev);
1026}
1027
1028int amdgpu_device_init(struct amdgpu_device *adev,
1029 struct drm_device *ddev,
1030 struct pci_dev *pdev,
1031 uint32_t flags);
1032void amdgpu_device_fini(struct amdgpu_device *adev);
1033int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1034
1035uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1036 uint32_t acc_flags);
1037void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1038 uint32_t acc_flags);
1039void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1040uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1041
1042u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1043void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1044
1045bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1046bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1047
1048int emu_soc_asic_init(struct amdgpu_device *adev);
1049
1050/*
1051 * Registers read & write functions.
1052 */
1053
1054#define AMDGPU_REGS_IDX (1<<0)
1055#define AMDGPU_REGS_NO_KIQ (1<<1)
1056
1057#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1058#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1059
1060#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1061#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1062
1063#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1064#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1065#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1066#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1067#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1068#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1069#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1070#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1071#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1072#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1073#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1074#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1075#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1076#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1077#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1078#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1079#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1080#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1081#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1082#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1083#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1084#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1085#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1086#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1087#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1088#define WREG32_P(reg, val, mask) \
1089 do { \
1090 uint32_t tmp_ = RREG32(reg); \
1091 tmp_ &= (mask); \
1092 tmp_ |= ((val) & ~(mask)); \
1093 WREG32(reg, tmp_); \
1094 } while (0)
1095#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1096#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1097#define WREG32_PLL_P(reg, val, mask) \
1098 do { \
1099 uint32_t tmp_ = RREG32_PLL(reg); \
1100 tmp_ &= (mask); \
1101 tmp_ |= ((val) & ~(mask)); \
1102 WREG32_PLL(reg, tmp_); \
1103 } while (0)
1104#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1105#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1106#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1107
1108#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1109#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1110
1111#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1112 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1113 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1114
1115#define REG_GET_FIELD(value, reg, field) \
1116 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1117
1118#define WREG32_FIELD(reg, field, val) \
1119 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1120
1121#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1122 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1123
1124/*
1125 * BIOS helpers.
1126 */
1127#define RBIOS8(i) (adev->bios[i])
1128#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1129#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1130
1131/*
1132 * ASICs macro.
1133 */
1134#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1135#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1136#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1137#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1138#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1139#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1140#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1141#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1142#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1143#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1144#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1145#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1146#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1147#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
1148#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
1149#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1150#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1151#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1152#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1153#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1154#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1155
1156/* Common functions */
1157bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1158int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1159 struct amdgpu_job* job);
1160void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1161bool amdgpu_device_need_post(struct amdgpu_device *adev);
1162
1163void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1164 u64 num_vis_bytes);
1165int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1166void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1167 const u32 *registers,
1168 const u32 array_size);
1169
1170bool amdgpu_device_is_px(struct drm_device *dev);
1171bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1172 struct amdgpu_device *peer_adev);
1173
1174/* atpx handler */
1175#if defined(CONFIG_VGA_SWITCHEROO)
1176void amdgpu_register_atpx_handler(void);
1177void amdgpu_unregister_atpx_handler(void);
1178bool amdgpu_has_atpx_dgpu_power_cntl(void);
1179bool amdgpu_is_atpx_hybrid(void);
1180bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1181bool amdgpu_has_atpx(void);
1182#else
1183static inline void amdgpu_register_atpx_handler(void) {}
1184static inline void amdgpu_unregister_atpx_handler(void) {}
1185static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1186static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1187static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1188static inline bool amdgpu_has_atpx(void) { return false; }
1189#endif
1190
1191#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1192void *amdgpu_atpx_get_dhandle(void);
1193#else
1194static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1195#endif
1196
1197/*
1198 * KMS
1199 */
1200extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1201extern const int amdgpu_max_kms_ioctl;
1202
1203int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1204void amdgpu_driver_unload_kms(struct drm_device *dev);
1205void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1206int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1207void amdgpu_driver_postclose_kms(struct drm_device *dev,
1208 struct drm_file *file_priv);
1209int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1210int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1211int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1212u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1213int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1214void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1215long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1216 unsigned long arg);
1217
1218/*
1219 * functions used by amdgpu_encoder.c
1220 */
1221struct amdgpu_afmt_acr {
1222 u32 clock;
1223
1224 int n_32khz;
1225 int cts_32khz;
1226
1227 int n_44_1khz;
1228 int cts_44_1khz;
1229
1230 int n_48khz;
1231 int cts_48khz;
1232
1233};
1234
1235struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1236
1237/* amdgpu_acpi.c */
1238#if defined(CONFIG_ACPI)
1239int amdgpu_acpi_init(struct amdgpu_device *adev);
1240void amdgpu_acpi_fini(struct amdgpu_device *adev);
1241bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1242int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1243 u8 perf_req, bool advertise);
1244int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1245
1246void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev,
1247 struct amdgpu_dm_backlight_caps *caps);
1248#else
1249static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1250static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1251#endif
1252
1253int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1254 uint64_t addr, struct amdgpu_bo **bo,
1255 struct amdgpu_bo_va_mapping **mapping);
1256
1257#if defined(CONFIG_DRM_AMD_DC)
1258int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1259#else
1260static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1261#endif
1262
1263
1264void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1265void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1266
1267#include "amdgpu_object.h"
1268
1269/* used by df_v3_6.c and amdgpu_pmu.c */
1270#define AMDGPU_PMU_ATTR(_name, _object) \
1271static ssize_t \
1272_name##_show(struct device *dev, \
1273 struct device_attribute *attr, \
1274 char *page) \
1275{ \
1276 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \
1277 return sprintf(page, _object "\n"); \
1278} \
1279 \
1280static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name)
1281
1282#endif
1283
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54
55#include <drm/ttm/ttm_bo_api.h>
56#include <drm/ttm/ttm_bo_driver.h>
57#include <drm/ttm/ttm_placement.h>
58#include <drm/ttm/ttm_execbuf_util.h>
59
60#include <drm/amdgpu_drm.h>
61#include <drm/drm_gem.h>
62#include <drm/drm_ioctl.h>
63
64#include <kgd_kfd_interface.h>
65#include "dm_pp_interface.h"
66#include "kgd_pp_interface.h"
67
68#include "amd_shared.h"
69#include "amdgpu_mode.h"
70#include "amdgpu_ih.h"
71#include "amdgpu_irq.h"
72#include "amdgpu_ucode.h"
73#include "amdgpu_ttm.h"
74#include "amdgpu_psp.h"
75#include "amdgpu_gds.h"
76#include "amdgpu_sync.h"
77#include "amdgpu_ring.h"
78#include "amdgpu_vm.h"
79#include "amdgpu_dpm.h"
80#include "amdgpu_acp.h"
81#include "amdgpu_uvd.h"
82#include "amdgpu_vce.h"
83#include "amdgpu_vcn.h"
84#include "amdgpu_jpeg.h"
85#include "amdgpu_gmc.h"
86#include "amdgpu_gfx.h"
87#include "amdgpu_sdma.h"
88#include "amdgpu_lsdma.h"
89#include "amdgpu_nbio.h"
90#include "amdgpu_hdp.h"
91#include "amdgpu_dm.h"
92#include "amdgpu_virt.h"
93#include "amdgpu_csa.h"
94#include "amdgpu_mes_ctx.h"
95#include "amdgpu_gart.h"
96#include "amdgpu_debugfs.h"
97#include "amdgpu_job.h"
98#include "amdgpu_bo_list.h"
99#include "amdgpu_gem.h"
100#include "amdgpu_doorbell.h"
101#include "amdgpu_amdkfd.h"
102#include "amdgpu_discovery.h"
103#include "amdgpu_mes.h"
104#include "amdgpu_umc.h"
105#include "amdgpu_mmhub.h"
106#include "amdgpu_gfxhub.h"
107#include "amdgpu_df.h"
108#include "amdgpu_smuio.h"
109#include "amdgpu_fdinfo.h"
110#include "amdgpu_mca.h"
111#include "amdgpu_ras.h"
112
113#define MAX_GPU_INSTANCE 16
114
115struct amdgpu_gpu_instance
116{
117 struct amdgpu_device *adev;
118 int mgpu_fan_enabled;
119};
120
121struct amdgpu_mgpu_info
122{
123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
124 struct mutex mutex;
125 uint32_t num_gpu;
126 uint32_t num_dgpu;
127 uint32_t num_apu;
128
129 /* delayed reset_func for XGMI configuration if necessary */
130 struct delayed_work delayed_reset_work;
131 bool pending_reset;
132};
133
134enum amdgpu_ss {
135 AMDGPU_SS_DRV_LOAD,
136 AMDGPU_SS_DEV_D0,
137 AMDGPU_SS_DEV_D3,
138 AMDGPU_SS_DRV_UNLOAD
139};
140
141struct amdgpu_watchdog_timer
142{
143 bool timeout_fatal_disable;
144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
145};
146
147#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
148
149/*
150 * Modules parameters.
151 */
152extern int amdgpu_modeset;
153extern int amdgpu_vram_limit;
154extern int amdgpu_vis_vram_limit;
155extern int amdgpu_gart_size;
156extern int amdgpu_gtt_size;
157extern int amdgpu_moverate;
158extern int amdgpu_audio;
159extern int amdgpu_disp_priority;
160extern int amdgpu_hw_i2c;
161extern int amdgpu_pcie_gen2;
162extern int amdgpu_msi;
163extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
164extern int amdgpu_dpm;
165extern int amdgpu_fw_load_type;
166extern int amdgpu_aspm;
167extern int amdgpu_runtime_pm;
168extern uint amdgpu_ip_block_mask;
169extern int amdgpu_bapm;
170extern int amdgpu_deep_color;
171extern int amdgpu_vm_size;
172extern int amdgpu_vm_block_size;
173extern int amdgpu_vm_fragment_size;
174extern int amdgpu_vm_fault_stop;
175extern int amdgpu_vm_debug;
176extern int amdgpu_vm_update_mode;
177extern int amdgpu_exp_hw_support;
178extern int amdgpu_dc;
179extern int amdgpu_sched_jobs;
180extern int amdgpu_sched_hw_submission;
181extern uint amdgpu_pcie_gen_cap;
182extern uint amdgpu_pcie_lane_cap;
183extern u64 amdgpu_cg_mask;
184extern uint amdgpu_pg_mask;
185extern uint amdgpu_sdma_phase_quantum;
186extern char *amdgpu_disable_cu;
187extern char *amdgpu_virtual_display;
188extern uint amdgpu_pp_feature_mask;
189extern uint amdgpu_force_long_training;
190extern int amdgpu_job_hang_limit;
191extern int amdgpu_lbpw;
192extern int amdgpu_compute_multipipe;
193extern int amdgpu_gpu_recovery;
194extern int amdgpu_emu_mode;
195extern uint amdgpu_smu_memory_pool_size;
196extern int amdgpu_smu_pptable_id;
197extern uint amdgpu_dc_feature_mask;
198extern uint amdgpu_freesync_vid_mode;
199extern uint amdgpu_dc_debug_mask;
200extern uint amdgpu_dc_visual_confirm;
201extern uint amdgpu_dm_abm_level;
202extern int amdgpu_backlight;
203extern struct amdgpu_mgpu_info mgpu_info;
204extern int amdgpu_ras_enable;
205extern uint amdgpu_ras_mask;
206extern int amdgpu_bad_page_threshold;
207extern bool amdgpu_ignore_bad_page_threshold;
208extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
209extern int amdgpu_async_gfx_ring;
210extern int amdgpu_mcbp;
211extern int amdgpu_discovery;
212extern int amdgpu_mes;
213extern int amdgpu_mes_kiq;
214extern int amdgpu_noretry;
215extern int amdgpu_force_asic_type;
216extern int amdgpu_smartshift_bias;
217extern int amdgpu_use_xgmi_p2p;
218#ifdef CONFIG_HSA_AMD
219extern int sched_policy;
220extern bool debug_evictions;
221extern bool no_system_mem_limit;
222extern int halt_if_hws_hang;
223#else
224static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
225static const bool __maybe_unused debug_evictions; /* = false */
226static const bool __maybe_unused no_system_mem_limit;
227static const int __maybe_unused halt_if_hws_hang;
228#endif
229#ifdef CONFIG_HSA_AMD_P2P
230extern bool pcie_p2p;
231#endif
232
233extern int amdgpu_tmz;
234extern int amdgpu_reset_method;
235
236#ifdef CONFIG_DRM_AMDGPU_SI
237extern int amdgpu_si_support;
238#endif
239#ifdef CONFIG_DRM_AMDGPU_CIK
240extern int amdgpu_cik_support;
241#endif
242extern int amdgpu_num_kcq;
243
244#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
245extern int amdgpu_vcnfw_log;
246extern int amdgpu_sg_display;
247
248#define AMDGPU_VM_MAX_NUM_CTX 4096
249#define AMDGPU_SG_THRESHOLD (256*1024*1024)
250#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
251#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
252#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
253#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
254#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
255#define AMDGPUFB_CONN_LIMIT 4
256#define AMDGPU_BIOS_NUM_SCRATCH 16
257
258#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
259
260/* hard reset data */
261#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
262
263/* reset flags */
264#define AMDGPU_RESET_GFX (1 << 0)
265#define AMDGPU_RESET_COMPUTE (1 << 1)
266#define AMDGPU_RESET_DMA (1 << 2)
267#define AMDGPU_RESET_CP (1 << 3)
268#define AMDGPU_RESET_GRBM (1 << 4)
269#define AMDGPU_RESET_DMA1 (1 << 5)
270#define AMDGPU_RESET_RLC (1 << 6)
271#define AMDGPU_RESET_SEM (1 << 7)
272#define AMDGPU_RESET_IH (1 << 8)
273#define AMDGPU_RESET_VMC (1 << 9)
274#define AMDGPU_RESET_MC (1 << 10)
275#define AMDGPU_RESET_DISPLAY (1 << 11)
276#define AMDGPU_RESET_UVD (1 << 12)
277#define AMDGPU_RESET_VCE (1 << 13)
278#define AMDGPU_RESET_VCE1 (1 << 14)
279
280/* max cursor sizes (in pixels) */
281#define CIK_CURSOR_WIDTH 128
282#define CIK_CURSOR_HEIGHT 128
283
284/* smart shift bias level limits */
285#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
286#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
287
288struct amdgpu_device;
289struct amdgpu_irq_src;
290struct amdgpu_fpriv;
291struct amdgpu_bo_va_mapping;
292struct kfd_vm_fault_info;
293struct amdgpu_hive_info;
294struct amdgpu_reset_context;
295struct amdgpu_reset_control;
296
297enum amdgpu_cp_irq {
298 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
299 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
300 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
301 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
302 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
303 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
304 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
305 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
306 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
307 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
308
309 AMDGPU_CP_IRQ_LAST
310};
311
312enum amdgpu_thermal_irq {
313 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
314 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
315
316 AMDGPU_THERMAL_IRQ_LAST
317};
318
319enum amdgpu_kiq_irq {
320 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
321 AMDGPU_CP_KIQ_IRQ_LAST
322};
323#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
324#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
325#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
326#define MAX_KIQ_REG_TRY 1000
327
328int amdgpu_device_ip_set_clockgating_state(void *dev,
329 enum amd_ip_block_type block_type,
330 enum amd_clockgating_state state);
331int amdgpu_device_ip_set_powergating_state(void *dev,
332 enum amd_ip_block_type block_type,
333 enum amd_powergating_state state);
334void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
335 u64 *flags);
336int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
337 enum amd_ip_block_type block_type);
338bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
339 enum amd_ip_block_type block_type);
340
341#define AMDGPU_MAX_IP_NUM 16
342
343struct amdgpu_ip_block_status {
344 bool valid;
345 bool sw;
346 bool hw;
347 bool late_initialized;
348 bool hang;
349};
350
351struct amdgpu_ip_block_version {
352 const enum amd_ip_block_type type;
353 const u32 major;
354 const u32 minor;
355 const u32 rev;
356 const struct amd_ip_funcs *funcs;
357};
358
359#define HW_REV(_Major, _Minor, _Rev) \
360 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
361
362struct amdgpu_ip_block {
363 struct amdgpu_ip_block_status status;
364 const struct amdgpu_ip_block_version *version;
365};
366
367int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
368 enum amd_ip_block_type type,
369 u32 major, u32 minor);
370
371struct amdgpu_ip_block *
372amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
373 enum amd_ip_block_type type);
374
375int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
376 const struct amdgpu_ip_block_version *ip_block_version);
377
378/*
379 * BIOS.
380 */
381bool amdgpu_get_bios(struct amdgpu_device *adev);
382bool amdgpu_read_bios(struct amdgpu_device *adev);
383bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
384 u8 *bios, u32 length_bytes);
385/*
386 * Clocks
387 */
388
389#define AMDGPU_MAX_PPLL 3
390
391struct amdgpu_clock {
392 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
393 struct amdgpu_pll spll;
394 struct amdgpu_pll mpll;
395 /* 10 Khz units */
396 uint32_t default_mclk;
397 uint32_t default_sclk;
398 uint32_t default_dispclk;
399 uint32_t current_dispclk;
400 uint32_t dp_extclk;
401 uint32_t max_pixel_clock;
402};
403
404/* sub-allocation manager, it has to be protected by another lock.
405 * By conception this is an helper for other part of the driver
406 * like the indirect buffer or semaphore, which both have their
407 * locking.
408 *
409 * Principe is simple, we keep a list of sub allocation in offset
410 * order (first entry has offset == 0, last entry has the highest
411 * offset).
412 *
413 * When allocating new object we first check if there is room at
414 * the end total_size - (last_object_offset + last_object_size) >=
415 * alloc_size. If so we allocate new object there.
416 *
417 * When there is not enough room at the end, we start waiting for
418 * each sub object until we reach object_offset+object_size >=
419 * alloc_size, this object then become the sub object we return.
420 *
421 * Alignment can't be bigger than page size.
422 *
423 * Hole are not considered for allocation to keep things simple.
424 * Assumption is that there won't be hole (all object on same
425 * alignment).
426 */
427
428#define AMDGPU_SA_NUM_FENCE_LISTS 32
429
430struct amdgpu_sa_manager {
431 wait_queue_head_t wq;
432 struct amdgpu_bo *bo;
433 struct list_head *hole;
434 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
435 struct list_head olist;
436 unsigned size;
437 uint64_t gpu_addr;
438 void *cpu_ptr;
439 uint32_t domain;
440 uint32_t align;
441};
442
443/* sub-allocation buffer */
444struct amdgpu_sa_bo {
445 struct list_head olist;
446 struct list_head flist;
447 struct amdgpu_sa_manager *manager;
448 unsigned soffset;
449 unsigned eoffset;
450 struct dma_fence *fence;
451};
452
453int amdgpu_fence_slab_init(void);
454void amdgpu_fence_slab_fini(void);
455
456/*
457 * IRQS.
458 */
459
460struct amdgpu_flip_work {
461 struct delayed_work flip_work;
462 struct work_struct unpin_work;
463 struct amdgpu_device *adev;
464 int crtc_id;
465 u32 target_vblank;
466 uint64_t base;
467 struct drm_pending_vblank_event *event;
468 struct amdgpu_bo *old_abo;
469 unsigned shared_count;
470 struct dma_fence **shared;
471 struct dma_fence_cb cb;
472 bool async;
473};
474
475
476/*
477 * file private structure
478 */
479
480struct amdgpu_fpriv {
481 struct amdgpu_vm vm;
482 struct amdgpu_bo_va *prt_va;
483 struct amdgpu_bo_va *csa_va;
484 struct mutex bo_list_lock;
485 struct idr bo_list_handles;
486 struct amdgpu_ctx_mgr ctx_mgr;
487};
488
489int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
490
491/*
492 * Writeback
493 */
494#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
495
496struct amdgpu_wb {
497 struct amdgpu_bo *wb_obj;
498 volatile uint32_t *wb;
499 uint64_t gpu_addr;
500 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
501 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
502};
503
504int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
505void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
506
507/*
508 * Benchmarking
509 */
510int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
511
512/*
513 * ASIC specific register table accessible by UMD
514 */
515struct amdgpu_allowed_register_entry {
516 uint32_t reg_offset;
517 bool grbm_indexed;
518};
519
520enum amd_reset_method {
521 AMD_RESET_METHOD_NONE = -1,
522 AMD_RESET_METHOD_LEGACY = 0,
523 AMD_RESET_METHOD_MODE0,
524 AMD_RESET_METHOD_MODE1,
525 AMD_RESET_METHOD_MODE2,
526 AMD_RESET_METHOD_BACO,
527 AMD_RESET_METHOD_PCI,
528};
529
530struct amdgpu_video_codec_info {
531 u32 codec_type;
532 u32 max_width;
533 u32 max_height;
534 u32 max_pixels_per_frame;
535 u32 max_level;
536};
537
538#define codec_info_build(type, width, height, level) \
539 .codec_type = type,\
540 .max_width = width,\
541 .max_height = height,\
542 .max_pixels_per_frame = height * width,\
543 .max_level = level,
544
545struct amdgpu_video_codecs {
546 const u32 codec_count;
547 const struct amdgpu_video_codec_info *codec_array;
548};
549
550/*
551 * ASIC specific functions.
552 */
553struct amdgpu_asic_funcs {
554 bool (*read_disabled_bios)(struct amdgpu_device *adev);
555 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
556 u8 *bios, u32 length_bytes);
557 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
558 u32 sh_num, u32 reg_offset, u32 *value);
559 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
560 int (*reset)(struct amdgpu_device *adev);
561 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
562 /* get the reference clock */
563 u32 (*get_xclk)(struct amdgpu_device *adev);
564 /* MM block clocks */
565 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
566 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
567 /* static power management */
568 int (*get_pcie_lanes)(struct amdgpu_device *adev);
569 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
570 /* get config memsize register */
571 u32 (*get_config_memsize)(struct amdgpu_device *adev);
572 /* flush hdp write queue */
573 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
574 /* invalidate hdp read cache */
575 void (*invalidate_hdp)(struct amdgpu_device *adev,
576 struct amdgpu_ring *ring);
577 /* check if the asic needs a full reset of if soft reset will work */
578 bool (*need_full_reset)(struct amdgpu_device *adev);
579 /* initialize doorbell layout for specific asic*/
580 void (*init_doorbell_index)(struct amdgpu_device *adev);
581 /* PCIe bandwidth usage */
582 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
583 uint64_t *count1);
584 /* do we need to reset the asic at init time (e.g., kexec) */
585 bool (*need_reset_on_init)(struct amdgpu_device *adev);
586 /* PCIe replay counter */
587 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
588 /* device supports BACO */
589 bool (*supports_baco)(struct amdgpu_device *adev);
590 /* pre asic_init quirks */
591 void (*pre_asic_init)(struct amdgpu_device *adev);
592 /* enter/exit umd stable pstate */
593 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
594 /* query video codecs */
595 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
596 const struct amdgpu_video_codecs **codecs);
597};
598
599/*
600 * IOCTL.
601 */
602int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
603 struct drm_file *filp);
604
605int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
606int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
607 struct drm_file *filp);
608int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
609int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
610 struct drm_file *filp);
611
612/* VRAM scratch page for HDP bug, default vram page */
613struct amdgpu_vram_scratch {
614 struct amdgpu_bo *robj;
615 volatile uint32_t *ptr;
616 u64 gpu_addr;
617};
618
619/*
620 * CGS
621 */
622struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
623void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
624
625/*
626 * Core structure, functions and helpers.
627 */
628typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
629typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
630
631typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
632typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
633
634typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
635typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
636
637struct amdgpu_mmio_remap {
638 u32 reg_offset;
639 resource_size_t bus_addr;
640};
641
642/* Define the HW IP blocks will be used in driver , add more if necessary */
643enum amd_hw_ip_block_type {
644 GC_HWIP = 1,
645 HDP_HWIP,
646 SDMA0_HWIP,
647 SDMA1_HWIP,
648 SDMA2_HWIP,
649 SDMA3_HWIP,
650 SDMA4_HWIP,
651 SDMA5_HWIP,
652 SDMA6_HWIP,
653 SDMA7_HWIP,
654 LSDMA_HWIP,
655 MMHUB_HWIP,
656 ATHUB_HWIP,
657 NBIO_HWIP,
658 MP0_HWIP,
659 MP1_HWIP,
660 UVD_HWIP,
661 VCN_HWIP = UVD_HWIP,
662 JPEG_HWIP = VCN_HWIP,
663 VCN1_HWIP,
664 VCE_HWIP,
665 DF_HWIP,
666 DCE_HWIP,
667 OSSSYS_HWIP,
668 SMUIO_HWIP,
669 PWR_HWIP,
670 NBIF_HWIP,
671 THM_HWIP,
672 CLK_HWIP,
673 UMC_HWIP,
674 RSMU_HWIP,
675 XGMI_HWIP,
676 DCI_HWIP,
677 PCIE_HWIP,
678 MAX_HWIP
679};
680
681#define HWIP_MAX_INSTANCE 28
682
683#define HW_ID_MAX 300
684#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
685#define IP_VERSION_MAJ(ver) ((ver) >> 16)
686#define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
687#define IP_VERSION_REV(ver) ((ver) & 0xFF)
688
689struct amd_powerplay {
690 void *pp_handle;
691 const struct amd_pm_funcs *pp_funcs;
692};
693
694struct ip_discovery_top;
695
696/* polaris10 kickers */
697#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
698 ((rid == 0xE3) || \
699 (rid == 0xE4) || \
700 (rid == 0xE5) || \
701 (rid == 0xE7) || \
702 (rid == 0xEF))) || \
703 ((did == 0x6FDF) && \
704 ((rid == 0xE7) || \
705 (rid == 0xEF) || \
706 (rid == 0xFF))))
707
708#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
709 ((rid == 0xE1) || \
710 (rid == 0xF7)))
711
712/* polaris11 kickers */
713#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
714 ((rid == 0xE0) || \
715 (rid == 0xE5))) || \
716 ((did == 0x67FF) && \
717 ((rid == 0xCF) || \
718 (rid == 0xEF) || \
719 (rid == 0xFF))))
720
721#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
722 ((rid == 0xE2)))
723
724/* polaris12 kickers */
725#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
726 ((rid == 0xC0) || \
727 (rid == 0xC1) || \
728 (rid == 0xC3) || \
729 (rid == 0xC7))) || \
730 ((did == 0x6981) && \
731 ((rid == 0x00) || \
732 (rid == 0x01) || \
733 (rid == 0x10))))
734
735struct amdgpu_mqd_prop {
736 uint64_t mqd_gpu_addr;
737 uint64_t hqd_base_gpu_addr;
738 uint64_t rptr_gpu_addr;
739 uint64_t wptr_gpu_addr;
740 uint32_t queue_size;
741 bool use_doorbell;
742 uint32_t doorbell_index;
743 uint64_t eop_gpu_addr;
744 uint32_t hqd_pipe_priority;
745 uint32_t hqd_queue_priority;
746 bool hqd_active;
747};
748
749struct amdgpu_mqd {
750 unsigned mqd_size;
751 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
752 struct amdgpu_mqd_prop *p);
753};
754
755#define AMDGPU_RESET_MAGIC_NUM 64
756#define AMDGPU_MAX_DF_PERFMONS 4
757#define AMDGPU_PRODUCT_NAME_LEN 64
758struct amdgpu_reset_domain;
759
760struct amdgpu_device {
761 struct device *dev;
762 struct pci_dev *pdev;
763 struct drm_device ddev;
764
765#ifdef CONFIG_DRM_AMD_ACP
766 struct amdgpu_acp acp;
767#endif
768 struct amdgpu_hive_info *hive;
769 /* ASIC */
770 enum amd_asic_type asic_type;
771 uint32_t family;
772 uint32_t rev_id;
773 uint32_t external_rev_id;
774 unsigned long flags;
775 unsigned long apu_flags;
776 int usec_timeout;
777 const struct amdgpu_asic_funcs *asic_funcs;
778 bool shutdown;
779 bool need_swiotlb;
780 bool accel_working;
781 struct notifier_block acpi_nb;
782 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
783 struct debugfs_blob_wrapper debugfs_vbios_blob;
784 struct debugfs_blob_wrapper debugfs_discovery_blob;
785 struct mutex srbm_mutex;
786 /* GRBM index mutex. Protects concurrent access to GRBM index */
787 struct mutex grbm_idx_mutex;
788 struct dev_pm_domain vga_pm_domain;
789 bool have_disp_power_ref;
790 bool have_atomics_support;
791
792 /* BIOS */
793 bool is_atom_fw;
794 uint8_t *bios;
795 uint32_t bios_size;
796 uint32_t bios_scratch_reg_offset;
797 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
798
799 /* Register/doorbell mmio */
800 resource_size_t rmmio_base;
801 resource_size_t rmmio_size;
802 void __iomem *rmmio;
803 /* protects concurrent MM_INDEX/DATA based register access */
804 spinlock_t mmio_idx_lock;
805 struct amdgpu_mmio_remap rmmio_remap;
806 /* protects concurrent SMC based register access */
807 spinlock_t smc_idx_lock;
808 amdgpu_rreg_t smc_rreg;
809 amdgpu_wreg_t smc_wreg;
810 /* protects concurrent PCIE register access */
811 spinlock_t pcie_idx_lock;
812 amdgpu_rreg_t pcie_rreg;
813 amdgpu_wreg_t pcie_wreg;
814 amdgpu_rreg_t pciep_rreg;
815 amdgpu_wreg_t pciep_wreg;
816 amdgpu_rreg64_t pcie_rreg64;
817 amdgpu_wreg64_t pcie_wreg64;
818 /* protects concurrent UVD register access */
819 spinlock_t uvd_ctx_idx_lock;
820 amdgpu_rreg_t uvd_ctx_rreg;
821 amdgpu_wreg_t uvd_ctx_wreg;
822 /* protects concurrent DIDT register access */
823 spinlock_t didt_idx_lock;
824 amdgpu_rreg_t didt_rreg;
825 amdgpu_wreg_t didt_wreg;
826 /* protects concurrent gc_cac register access */
827 spinlock_t gc_cac_idx_lock;
828 amdgpu_rreg_t gc_cac_rreg;
829 amdgpu_wreg_t gc_cac_wreg;
830 /* protects concurrent se_cac register access */
831 spinlock_t se_cac_idx_lock;
832 amdgpu_rreg_t se_cac_rreg;
833 amdgpu_wreg_t se_cac_wreg;
834 /* protects concurrent ENDPOINT (audio) register access */
835 spinlock_t audio_endpt_idx_lock;
836 amdgpu_block_rreg_t audio_endpt_rreg;
837 amdgpu_block_wreg_t audio_endpt_wreg;
838 struct amdgpu_doorbell doorbell;
839
840 /* clock/pll info */
841 struct amdgpu_clock clock;
842
843 /* MC */
844 struct amdgpu_gmc gmc;
845 struct amdgpu_gart gart;
846 dma_addr_t dummy_page_addr;
847 struct amdgpu_vm_manager vm_manager;
848 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
849 unsigned num_vmhubs;
850
851 /* memory management */
852 struct amdgpu_mman mman;
853 struct amdgpu_vram_scratch vram_scratch;
854 struct amdgpu_wb wb;
855 atomic64_t num_bytes_moved;
856 atomic64_t num_evictions;
857 atomic64_t num_vram_cpu_page_faults;
858 atomic_t gpu_reset_counter;
859 atomic_t vram_lost_counter;
860
861 /* data for buffer migration throttling */
862 struct {
863 spinlock_t lock;
864 s64 last_update_us;
865 s64 accum_us; /* accumulated microseconds */
866 s64 accum_us_vis; /* for visible VRAM */
867 u32 log2_max_MBps;
868 } mm_stats;
869
870 /* display */
871 bool enable_virtual_display;
872 struct amdgpu_vkms_output *amdgpu_vkms_output;
873 struct amdgpu_mode_info mode_info;
874 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
875 struct work_struct hotplug_work;
876 struct amdgpu_irq_src crtc_irq;
877 struct amdgpu_irq_src vline0_irq;
878 struct amdgpu_irq_src vupdate_irq;
879 struct amdgpu_irq_src pageflip_irq;
880 struct amdgpu_irq_src hpd_irq;
881 struct amdgpu_irq_src dmub_trace_irq;
882 struct amdgpu_irq_src dmub_outbox_irq;
883
884 /* rings */
885 u64 fence_context;
886 unsigned num_rings;
887 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
888 struct dma_fence __rcu *gang_submit;
889 bool ib_pool_ready;
890 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
891 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
892
893 /* interrupts */
894 struct amdgpu_irq irq;
895
896 /* powerplay */
897 struct amd_powerplay powerplay;
898 struct amdgpu_pm pm;
899 u64 cg_flags;
900 u32 pg_flags;
901
902 /* nbio */
903 struct amdgpu_nbio nbio;
904
905 /* hdp */
906 struct amdgpu_hdp hdp;
907
908 /* smuio */
909 struct amdgpu_smuio smuio;
910
911 /* mmhub */
912 struct amdgpu_mmhub mmhub;
913
914 /* gfxhub */
915 struct amdgpu_gfxhub gfxhub;
916
917 /* gfx */
918 struct amdgpu_gfx gfx;
919
920 /* sdma */
921 struct amdgpu_sdma sdma;
922
923 /* lsdma */
924 struct amdgpu_lsdma lsdma;
925
926 /* uvd */
927 struct amdgpu_uvd uvd;
928
929 /* vce */
930 struct amdgpu_vce vce;
931
932 /* vcn */
933 struct amdgpu_vcn vcn;
934
935 /* jpeg */
936 struct amdgpu_jpeg jpeg;
937
938 /* firmwares */
939 struct amdgpu_firmware firmware;
940
941 /* PSP */
942 struct psp_context psp;
943
944 /* GDS */
945 struct amdgpu_gds gds;
946
947 /* KFD */
948 struct amdgpu_kfd_dev kfd;
949
950 /* UMC */
951 struct amdgpu_umc umc;
952
953 /* display related functionality */
954 struct amdgpu_display_manager dm;
955
956 /* mes */
957 bool enable_mes;
958 bool enable_mes_kiq;
959 struct amdgpu_mes mes;
960 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
961
962 /* df */
963 struct amdgpu_df df;
964
965 /* MCA */
966 struct amdgpu_mca mca;
967
968 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
969 uint32_t harvest_ip_mask;
970 int num_ip_blocks;
971 struct mutex mn_lock;
972 DECLARE_HASHTABLE(mn_hash, 7);
973
974 /* tracking pinned memory */
975 atomic64_t vram_pin_size;
976 atomic64_t visible_pin_size;
977 atomic64_t gart_pin_size;
978
979 /* soc15 register offset based on ip, instance and segment */
980 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
981
982 /* delayed work_func for deferring clockgating during resume */
983 struct delayed_work delayed_init_work;
984
985 struct amdgpu_virt virt;
986
987 /* link all shadow bo */
988 struct list_head shadow_list;
989 struct mutex shadow_list_lock;
990
991 /* record hw reset is performed */
992 bool has_hw_reset;
993 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
994
995 /* s3/s4 mask */
996 bool in_suspend;
997 bool in_s3;
998 bool in_s4;
999 bool in_s0ix;
1000
1001 enum pp_mp1_state mp1_state;
1002 struct amdgpu_doorbell_index doorbell_index;
1003
1004 struct mutex notifier_lock;
1005
1006 int asic_reset_res;
1007 struct work_struct xgmi_reset_work;
1008 struct list_head reset_list;
1009
1010 long gfx_timeout;
1011 long sdma_timeout;
1012 long video_timeout;
1013 long compute_timeout;
1014
1015 uint64_t unique_id;
1016 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1017
1018 /* enable runtime pm on the device */
1019 bool in_runpm;
1020 bool has_pr3;
1021
1022 bool pm_sysfs_en;
1023 bool ucode_sysfs_en;
1024 bool psp_sysfs_en;
1025
1026 /* Chip product information */
1027 char product_number[20];
1028 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1029 char serial[20];
1030
1031 atomic_t throttling_logging_enabled;
1032 struct ratelimit_state throttling_logging_rs;
1033 uint32_t ras_hw_enabled;
1034 uint32_t ras_enabled;
1035
1036 bool no_hw_access;
1037 struct pci_saved_state *pci_state;
1038 pci_channel_state_t pci_channel_state;
1039
1040 struct amdgpu_reset_control *reset_cntl;
1041 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1042
1043 bool ram_is_direct_mapped;
1044
1045 struct list_head ras_list;
1046
1047 struct ip_discovery_top *ip_top;
1048
1049 struct amdgpu_reset_domain *reset_domain;
1050
1051 struct mutex benchmark_mutex;
1052
1053 /* reset dump register */
1054 uint32_t *reset_dump_reg_list;
1055 uint32_t *reset_dump_reg_value;
1056 int num_regs;
1057#ifdef CONFIG_DEV_COREDUMP
1058 struct amdgpu_task_info reset_task_info;
1059 bool reset_vram_lost;
1060 struct timespec64 reset_time;
1061#endif
1062
1063 bool scpm_enabled;
1064 uint32_t scpm_status;
1065
1066 struct work_struct reset_work;
1067
1068 bool job_hang;
1069 bool dc_enabled;
1070};
1071
1072static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1073{
1074 return container_of(ddev, struct amdgpu_device, ddev);
1075}
1076
1077static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1078{
1079 return &adev->ddev;
1080}
1081
1082static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1083{
1084 return container_of(bdev, struct amdgpu_device, mman.bdev);
1085}
1086
1087int amdgpu_device_init(struct amdgpu_device *adev,
1088 uint32_t flags);
1089void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1090void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1091
1092int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1093
1094void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1095 void *buf, size_t size, bool write);
1096size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1097 void *buf, size_t size, bool write);
1098
1099void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1100 void *buf, size_t size, bool write);
1101uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1102 uint32_t reg, uint32_t acc_flags);
1103void amdgpu_device_wreg(struct amdgpu_device *adev,
1104 uint32_t reg, uint32_t v,
1105 uint32_t acc_flags);
1106void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1107 uint32_t reg, uint32_t v);
1108void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1109uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1110
1111u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1112 u32 pcie_index, u32 pcie_data,
1113 u32 reg_addr);
1114u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1115 u32 pcie_index, u32 pcie_data,
1116 u32 reg_addr);
1117void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1118 u32 pcie_index, u32 pcie_data,
1119 u32 reg_addr, u32 reg_data);
1120void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1121 u32 pcie_index, u32 pcie_data,
1122 u32 reg_addr, u64 reg_data);
1123
1124bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1125bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1126
1127void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1128
1129int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1130 struct amdgpu_reset_context *reset_context);
1131
1132int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1133 struct amdgpu_reset_context *reset_context);
1134
1135int emu_soc_asic_init(struct amdgpu_device *adev);
1136
1137/*
1138 * Registers read & write functions.
1139 */
1140#define AMDGPU_REGS_NO_KIQ (1<<1)
1141#define AMDGPU_REGS_RLC (1<<2)
1142
1143#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1144#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1145
1146#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1147#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1148
1149#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1150#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1151
1152#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1153#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1154#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1155#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1156#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1157#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1158#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1159#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1160#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1161#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1162#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1163#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1164#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1165#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1166#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1167#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1168#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1169#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1170#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1171#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1172#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1173#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1174#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1175#define WREG32_P(reg, val, mask) \
1176 do { \
1177 uint32_t tmp_ = RREG32(reg); \
1178 tmp_ &= (mask); \
1179 tmp_ |= ((val) & ~(mask)); \
1180 WREG32(reg, tmp_); \
1181 } while (0)
1182#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1183#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1184#define WREG32_PLL_P(reg, val, mask) \
1185 do { \
1186 uint32_t tmp_ = RREG32_PLL(reg); \
1187 tmp_ &= (mask); \
1188 tmp_ |= ((val) & ~(mask)); \
1189 WREG32_PLL(reg, tmp_); \
1190 } while (0)
1191
1192#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1193 do { \
1194 u32 tmp = RREG32_SMC(_Reg); \
1195 tmp &= (_Mask); \
1196 tmp |= ((_Val) & ~(_Mask)); \
1197 WREG32_SMC(_Reg, tmp); \
1198 } while (0)
1199
1200#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1201
1202#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1203#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1204
1205#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1206 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1207 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1208
1209#define REG_GET_FIELD(value, reg, field) \
1210 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1211
1212#define WREG32_FIELD(reg, field, val) \
1213 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1214
1215#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1216 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1217
1218/*
1219 * BIOS helpers.
1220 */
1221#define RBIOS8(i) (adev->bios[i])
1222#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1223#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1224
1225/*
1226 * ASICs macro.
1227 */
1228#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1229#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1230#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1231#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1232#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1233#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1234#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1235#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1236#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1237#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1238#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1239#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1240#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1241#define amdgpu_asic_flush_hdp(adev, r) \
1242 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1243#define amdgpu_asic_invalidate_hdp(adev, r) \
1244 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1245 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
1246#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1247#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1248#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1249#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1250#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1251#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1252#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1253#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1254 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1255#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1256
1257#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1258
1259#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1260
1261/* Common functions */
1262bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1263bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1264int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1265 struct amdgpu_job *job,
1266 struct amdgpu_reset_context *reset_context);
1267void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1268int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1269bool amdgpu_device_need_post(struct amdgpu_device *adev);
1270bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1271
1272void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1273 u64 num_vis_bytes);
1274int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1275void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1276 const u32 *registers,
1277 const u32 array_size);
1278
1279int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1280bool amdgpu_device_supports_atpx(struct drm_device *dev);
1281bool amdgpu_device_supports_px(struct drm_device *dev);
1282bool amdgpu_device_supports_boco(struct drm_device *dev);
1283bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1284bool amdgpu_device_supports_baco(struct drm_device *dev);
1285bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1286 struct amdgpu_device *peer_adev);
1287int amdgpu_device_baco_enter(struct drm_device *dev);
1288int amdgpu_device_baco_exit(struct drm_device *dev);
1289
1290void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1291 struct amdgpu_ring *ring);
1292void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1293 struct amdgpu_ring *ring);
1294
1295void amdgpu_device_halt(struct amdgpu_device *adev);
1296u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1297 u32 reg);
1298void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1299 u32 reg, u32 v);
1300struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1301 struct dma_fence *gang);
1302bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1303
1304/* atpx handler */
1305#if defined(CONFIG_VGA_SWITCHEROO)
1306void amdgpu_register_atpx_handler(void);
1307void amdgpu_unregister_atpx_handler(void);
1308bool amdgpu_has_atpx_dgpu_power_cntl(void);
1309bool amdgpu_is_atpx_hybrid(void);
1310bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1311bool amdgpu_has_atpx(void);
1312#else
1313static inline void amdgpu_register_atpx_handler(void) {}
1314static inline void amdgpu_unregister_atpx_handler(void) {}
1315static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1316static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1317static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1318static inline bool amdgpu_has_atpx(void) { return false; }
1319#endif
1320
1321#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1322void *amdgpu_atpx_get_dhandle(void);
1323#else
1324static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1325#endif
1326
1327/*
1328 * KMS
1329 */
1330extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1331extern const int amdgpu_max_kms_ioctl;
1332
1333int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1334void amdgpu_driver_unload_kms(struct drm_device *dev);
1335void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1336int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1337void amdgpu_driver_postclose_kms(struct drm_device *dev,
1338 struct drm_file *file_priv);
1339void amdgpu_driver_release_kms(struct drm_device *dev);
1340
1341int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1342int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1343int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1344u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1345int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1346void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1347int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1348 struct drm_file *filp);
1349
1350/*
1351 * functions used by amdgpu_encoder.c
1352 */
1353struct amdgpu_afmt_acr {
1354 u32 clock;
1355
1356 int n_32khz;
1357 int cts_32khz;
1358
1359 int n_44_1khz;
1360 int cts_44_1khz;
1361
1362 int n_48khz;
1363 int cts_48khz;
1364
1365};
1366
1367struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1368
1369/* amdgpu_acpi.c */
1370
1371/* ATCS Device/Driver State */
1372#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1373#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1374#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1375#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1376
1377#if defined(CONFIG_ACPI)
1378int amdgpu_acpi_init(struct amdgpu_device *adev);
1379void amdgpu_acpi_fini(struct amdgpu_device *adev);
1380bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1381bool amdgpu_acpi_is_power_shift_control_supported(void);
1382int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1383 u8 perf_req, bool advertise);
1384int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1385 u8 dev_state, bool drv_state);
1386int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1387int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1388
1389void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1390void amdgpu_acpi_detect(void);
1391#else
1392static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1393static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1394static inline void amdgpu_acpi_detect(void) { }
1395static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1396static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1397 u8 dev_state, bool drv_state) { return 0; }
1398static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1399 enum amdgpu_ss ss_state) { return 0; }
1400#endif
1401
1402#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1403bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1404bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1405bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1406#else
1407static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1408static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1409static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1410#endif
1411
1412#if defined(CONFIG_DRM_AMD_DC)
1413int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1414#else
1415static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1416#endif
1417
1418
1419void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1420void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1421
1422pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1423 pci_channel_state_t state);
1424pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1425pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1426void amdgpu_pci_resume(struct pci_dev *pdev);
1427
1428bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1429bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1430
1431bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1432
1433int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1434 enum amd_clockgating_state state);
1435int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1436 enum amd_powergating_state state);
1437
1438static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1439{
1440 return amdgpu_gpu_recovery != 0 &&
1441 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1442 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1443 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1444 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1445}
1446
1447#include "amdgpu_object.h"
1448
1449static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1450{
1451 return adev->gmc.tmz_enabled;
1452}
1453
1454int amdgpu_in_reset(struct amdgpu_device *adev);
1455
1456#endif