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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1500000 1250000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
56 /* cooling options */
57 #cooling-cells = <2>; /* min followed by max */
58 };
59 cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x1>;
63
64 operating-points = <
65 /* kHz uV */
66 1000000 1060000
67 1500000 1250000
68 >;
69
70 clocks = <&dpll_mpu_ck>;
71 clock-names = "cpu";
72
73 clock-latency = <300000>; /* From omap-cpufreq driver */
74
75 /* cooling options */
76 #cooling-cells = <2>; /* min followed by max */
77 };
78 };
79
80 thermal-zones {
81 #include "omap4-cpu-thermal.dtsi"
82 #include "omap5-gpu-thermal.dtsi"
83 #include "omap5-core-thermal.dtsi"
84 };
85
86 timer {
87 compatible = "arm,armv7-timer";
88 /* PPI secure/nonsecure IRQ */
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
93 interrupt-parent = <&gic>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu";
98 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 gic: interrupt-controller@48211000 {
103 compatible = "arm,cortex-a15-gic";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0 0x48211000 0 0x1000>,
107 <0 0x48212000 0 0x2000>,
108 <0 0x48214000 0 0x2000>,
109 <0 0x48216000 0 0x2000>;
110 interrupt-parent = <&gic>;
111 };
112
113 wakeupgen: interrupt-controller@48281000 {
114 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 reg = <0 0x48281000 0 0x1000>;
118 interrupt-parent = <&gic>;
119 };
120
121 /*
122 * The soc node represents the soc top level view. It is used for IPs
123 * that are not memory mapped in the MPU view or for the MPU itself.
124 */
125 soc {
126 compatible = "ti,omap-infra";
127 mpu {
128 compatible = "ti,omap4-mpu";
129 ti,hwmods = "mpu";
130 sram = <&ocmcram>;
131 };
132 };
133
134 /*
135 * XXX: Use a flat representation of the OMAP3 interconnect.
136 * The real OMAP interconnect network is quite complex.
137 * Since it will not bring real advantage to represent that in DT for
138 * the moment, just use a fake OCP bus entry to represent the whole bus
139 * hierarchy.
140 */
141 ocp {
142 compatible = "ti,omap5-l3-noc", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0 0 0xc0000000>;
146 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
147 reg = <0 0x44000000 0 0x2000>,
148 <0 0x44800000 0 0x3000>,
149 <0 0x45000000 0 0x4000>;
150 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
152
153 l4_wkup: interconnect@4ae00000 {
154 };
155
156 l4_cfg: interconnect@4a000000 {
157 };
158
159 l4_per: interconnect@48000000 {
160 };
161
162 l4_abe: interconnect@40100000 {
163 };
164
165 ocmcram: ocmcram@40300000 {
166 compatible = "mmio-sram";
167 reg = <0x40300000 0x20000>; /* 128k */
168 };
169
170 gpmc: gpmc@50000000 {
171 compatible = "ti,omap4430-gpmc";
172 reg = <0x50000000 0x1000>;
173 #address-cells = <2>;
174 #size-cells = <1>;
175 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
176 dmas = <&sdma 4>;
177 dma-names = "rxtx";
178 gpmc,num-cs = <8>;
179 gpmc,num-waitpins = <4>;
180 ti,hwmods = "gpmc";
181 clocks = <&l3_iclk_div>;
182 clock-names = "fck";
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 };
188
189 mmu_dsp: mmu@4a066000 {
190 compatible = "ti,omap4-iommu";
191 reg = <0x4a066000 0x100>;
192 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "mmu_dsp";
194 #iommu-cells = <0>;
195 };
196
197 mmu_ipu: mmu@55082000 {
198 compatible = "ti,omap4-iommu";
199 reg = <0x55082000 0x100>;
200 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
201 ti,hwmods = "mmu_ipu";
202 #iommu-cells = <0>;
203 ti,iommu-bus-err-back;
204 };
205
206 dmm@4e000000 {
207 compatible = "ti,omap5-dmm";
208 reg = <0x4e000000 0x800>;
209 interrupts = <0 113 0x4>;
210 ti,hwmods = "dmm";
211 };
212
213 emif1: emif@4c000000 {
214 compatible = "ti,emif-4d5";
215 ti,hwmods = "emif1";
216 ti,no-idle-on-init;
217 phy-type = <2>; /* DDR PHY type: Intelli PHY */
218 reg = <0x4c000000 0x400>;
219 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
220 hw-caps-read-idle-ctrl;
221 hw-caps-ll-interface;
222 hw-caps-temp-alert;
223 };
224
225 emif2: emif@4d000000 {
226 compatible = "ti,emif-4d5";
227 ti,hwmods = "emif2";
228 ti,no-idle-on-init;
229 phy-type = <2>; /* DDR PHY type: Intelli PHY */
230 reg = <0x4d000000 0x400>;
231 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
232 hw-caps-read-idle-ctrl;
233 hw-caps-ll-interface;
234 hw-caps-temp-alert;
235 };
236
237 bandgap: bandgap@4a0021e0 {
238 reg = <0x4a0021e0 0xc
239 0x4a00232c 0xc
240 0x4a002380 0x2c
241 0x4a0023C0 0x3c>;
242 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
243 compatible = "ti,omap5430-bandgap";
244
245 #thermal-sensor-cells = <1>;
246 };
247
248 /* OCP2SCP3 */
249 sata: sata@4a141100 {
250 compatible = "snps,dwc-ahci";
251 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
252 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
253 phys = <&sata_phy>;
254 phy-names = "sata-phy";
255 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
256 ti,hwmods = "sata";
257 ports-implemented = <0x1>;
258 };
259
260 target-module@56000000 {
261 compatible = "ti,sysc-omap4", "ti,sysc";
262 reg = <0x5600fe00 0x4>,
263 <0x5600fe10 0x4>;
264 reg-names = "rev", "sysc";
265 ti,sysc-midle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_NO>,
267 <SYSC_IDLE_SMART>;
268 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
269 <SYSC_IDLE_NO>,
270 <SYSC_IDLE_SMART>;
271 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
272 clock-names = "fck";
273 #address-cells = <1>;
274 #size-cells = <1>;
275 ranges = <0 0x56000000 0x2000000>;
276
277 /*
278 * Closed source PowerVR driver, no child device
279 * binding or driver in mainline
280 */
281 };
282
283 dss: dss@58000000 {
284 compatible = "ti,omap5-dss";
285 reg = <0x58000000 0x80>;
286 status = "disabled";
287 ti,hwmods = "dss_core";
288 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
289 clock-names = "fck";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293
294 dispc@58001000 {
295 compatible = "ti,omap5-dispc";
296 reg = <0x58001000 0x1000>;
297 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
298 ti,hwmods = "dss_dispc";
299 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
300 clock-names = "fck";
301 };
302
303 rfbi: encoder@58002000 {
304 compatible = "ti,omap5-rfbi";
305 reg = <0x58002000 0x100>;
306 status = "disabled";
307 ti,hwmods = "dss_rfbi";
308 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
309 clock-names = "fck", "ick";
310 };
311
312 dsi1: encoder@58004000 {
313 compatible = "ti,omap5-dsi";
314 reg = <0x58004000 0x200>,
315 <0x58004200 0x40>,
316 <0x58004300 0x40>;
317 reg-names = "proto", "phy", "pll";
318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
319 status = "disabled";
320 ti,hwmods = "dss_dsi1";
321 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
322 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
323 clock-names = "fck", "sys_clk";
324 };
325
326 dsi2: encoder@58005000 {
327 compatible = "ti,omap5-dsi";
328 reg = <0x58009000 0x200>,
329 <0x58009200 0x40>,
330 <0x58009300 0x40>;
331 reg-names = "proto", "phy", "pll";
332 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
333 status = "disabled";
334 ti,hwmods = "dss_dsi2";
335 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
336 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
337 clock-names = "fck", "sys_clk";
338 };
339
340 hdmi: encoder@58060000 {
341 compatible = "ti,omap5-hdmi";
342 reg = <0x58040000 0x200>,
343 <0x58040200 0x80>,
344 <0x58040300 0x80>,
345 <0x58060000 0x19000>;
346 reg-names = "wp", "pll", "phy", "core";
347 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
348 status = "disabled";
349 ti,hwmods = "dss_hdmi";
350 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
351 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
352 clock-names = "fck", "sys_clk";
353 dmas = <&sdma 76>;
354 dma-names = "audio_tx";
355 };
356 };
357
358 abb_mpu: regulator-abb-mpu {
359 compatible = "ti,abb-v2";
360 regulator-name = "abb_mpu";
361 #address-cells = <0>;
362 #size-cells = <0>;
363 clocks = <&sys_clkin>;
364 ti,settling-time = <50>;
365 ti,clock-cycles = <16>;
366
367 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
368 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
369 reg-names = "base-address", "int-address",
370 "efuse-address", "ldo-address";
371 ti,tranxdone-status-mask = <0x80>;
372 /* LDOVBBMPU_MUX_CTRL */
373 ti,ldovbb-override-mask = <0x400>;
374 /* LDOVBBMPU_VSET_OUT */
375 ti,ldovbb-vset-mask = <0x1F>;
376
377 /*
378 * NOTE: only FBB mode used but actual vset will
379 * determine final biasing
380 */
381 ti,abb_info = <
382 /*uV ABB efuse rbb_m fbb_m vset_m*/
383 1060000 0 0x0 0 0x02000000 0x01F00000
384 1250000 0 0x4 0 0x02000000 0x01F00000
385 >;
386 };
387
388 abb_mm: regulator-abb-mm {
389 compatible = "ti,abb-v2";
390 regulator-name = "abb_mm";
391 #address-cells = <0>;
392 #size-cells = <0>;
393 clocks = <&sys_clkin>;
394 ti,settling-time = <50>;
395 ti,clock-cycles = <16>;
396
397 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
398 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
399 reg-names = "base-address", "int-address",
400 "efuse-address", "ldo-address";
401 ti,tranxdone-status-mask = <0x80000000>;
402 /* LDOVBBMM_MUX_CTRL */
403 ti,ldovbb-override-mask = <0x400>;
404 /* LDOVBBMM_VSET_OUT */
405 ti,ldovbb-vset-mask = <0x1F>;
406
407 /*
408 * NOTE: only FBB mode used but actual vset will
409 * determine final biasing
410 */
411 ti,abb_info = <
412 /*uV ABB efuse rbb_m fbb_m vset_m*/
413 1025000 0 0x0 0 0x02000000 0x01F00000
414 1120000 0 0x4 0 0x02000000 0x01F00000
415 >;
416 };
417 };
418};
419
420&cpu_thermal {
421 polling-delay = <500>; /* milliseconds */
422 coefficients = <65 (-1791)>;
423};
424
425#include "omap5-l4.dtsi"
426#include "omap54xx-clocks.dtsi"
427
428&gpu_thermal {
429 coefficients = <117 (-2992)>;
430};
431
432&core_thermal {
433 coefficients = <0 2000>;
434};
435
436#include "omap5-l4-abe.dtsi"
437#include "omap54xx-clocks.dtsi"