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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1500000 1250000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
56 /* cooling options */
57 #cooling-cells = <2>; /* min followed by max */
58 };
59 cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x1>;
63
64 operating-points = <
65 /* kHz uV */
66 1000000 1060000
67 1500000 1250000
68 >;
69
70 clocks = <&dpll_mpu_ck>;
71 clock-names = "cpu";
72
73 clock-latency = <300000>; /* From omap-cpufreq driver */
74
75 /* cooling options */
76 #cooling-cells = <2>; /* min followed by max */
77 };
78 };
79
80 thermal-zones {
81 #include "omap4-cpu-thermal.dtsi"
82 #include "omap5-gpu-thermal.dtsi"
83 #include "omap5-core-thermal.dtsi"
84 };
85
86 timer {
87 compatible = "arm,armv7-timer";
88 /* PPI secure/nonsecure IRQ */
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
93 interrupt-parent = <&gic>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu";
98 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 gic: interrupt-controller@48211000 {
103 compatible = "arm,cortex-a15-gic";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0 0x48211000 0 0x1000>,
107 <0 0x48212000 0 0x2000>,
108 <0 0x48214000 0 0x2000>,
109 <0 0x48216000 0 0x2000>;
110 interrupt-parent = <&gic>;
111 };
112
113 wakeupgen: interrupt-controller@48281000 {
114 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 reg = <0 0x48281000 0 0x1000>;
118 interrupt-parent = <&gic>;
119 };
120
121 /*
122 * The soc node represents the soc top level view. It is used for IPs
123 * that are not memory mapped in the MPU view or for the MPU itself.
124 */
125 soc {
126 compatible = "ti,omap-infra";
127 mpu {
128 compatible = "ti,omap4-mpu";
129 ti,hwmods = "mpu";
130 sram = <&ocmcram>;
131 };
132 };
133
134 /*
135 * XXX: Use a flat representation of the OMAP3 interconnect.
136 * The real OMAP interconnect network is quite complex.
137 * Since it will not bring real advantage to represent that in DT for
138 * the moment, just use a fake OCP bus entry to represent the whole bus
139 * hierarchy.
140 */
141 ocp {
142 compatible = "ti,omap5-l3-noc", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0 0 0xc0000000>;
146 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
147 reg = <0 0x44000000 0 0x2000>,
148 <0 0x44800000 0 0x3000>,
149 <0 0x45000000 0 0x4000>;
150 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
152
153 l4_wkup: interconnect@4ae00000 {
154 };
155
156 l4_cfg: interconnect@4a000000 {
157 };
158
159 l4_per: interconnect@48000000 {
160 };
161
162 l4_abe: interconnect@40100000 {
163 };
164
165 ocmcram: ocmcram@40300000 {
166 compatible = "mmio-sram";
167 reg = <0x40300000 0x20000>; /* 128k */
168 };
169
170 gpmc: gpmc@50000000 {
171 compatible = "ti,omap4430-gpmc";
172 reg = <0x50000000 0x1000>;
173 #address-cells = <2>;
174 #size-cells = <1>;
175 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
176 dmas = <&sdma 4>;
177 dma-names = "rxtx";
178 gpmc,num-cs = <8>;
179 gpmc,num-waitpins = <4>;
180 ti,hwmods = "gpmc";
181 clocks = <&l3_iclk_div>;
182 clock-names = "fck";
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 };
188
189 mmu_dsp: mmu@4a066000 {
190 compatible = "ti,omap4-iommu";
191 reg = <0x4a066000 0x100>;
192 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "mmu_dsp";
194 #iommu-cells = <0>;
195 };
196
197 mmu_ipu: mmu@55082000 {
198 compatible = "ti,omap4-iommu";
199 reg = <0x55082000 0x100>;
200 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
201 ti,hwmods = "mmu_ipu";
202 #iommu-cells = <0>;
203 ti,iommu-bus-err-back;
204 };
205
206 dmm@4e000000 {
207 compatible = "ti,omap5-dmm";
208 reg = <0x4e000000 0x800>;
209 interrupts = <0 113 0x4>;
210 ti,hwmods = "dmm";
211 };
212
213 emif1: emif@4c000000 {
214 compatible = "ti,emif-4d5";
215 ti,hwmods = "emif1";
216 ti,no-idle-on-init;
217 phy-type = <2>; /* DDR PHY type: Intelli PHY */
218 reg = <0x4c000000 0x400>;
219 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
220 hw-caps-read-idle-ctrl;
221 hw-caps-ll-interface;
222 hw-caps-temp-alert;
223 };
224
225 emif2: emif@4d000000 {
226 compatible = "ti,emif-4d5";
227 ti,hwmods = "emif2";
228 ti,no-idle-on-init;
229 phy-type = <2>; /* DDR PHY type: Intelli PHY */
230 reg = <0x4d000000 0x400>;
231 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
232 hw-caps-read-idle-ctrl;
233 hw-caps-ll-interface;
234 hw-caps-temp-alert;
235 };
236
237 bandgap: bandgap@4a0021e0 {
238 reg = <0x4a0021e0 0xc
239 0x4a00232c 0xc
240 0x4a002380 0x2c
241 0x4a0023C0 0x3c>;
242 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
243 compatible = "ti,omap5430-bandgap";
244
245 #thermal-sensor-cells = <1>;
246 };
247
248 /* OCP2SCP3 */
249 sata: sata@4a141100 {
250 compatible = "snps,dwc-ahci";
251 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
252 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
253 phys = <&sata_phy>;
254 phy-names = "sata-phy";
255 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
256 ti,hwmods = "sata";
257 ports-implemented = <0x1>;
258 };
259
260 target-module@56000000 {
261 compatible = "ti,sysc-omap4", "ti,sysc";
262 reg = <0x5600fe00 0x4>,
263 <0x5600fe10 0x4>;
264 reg-names = "rev", "sysc";
265 ti,sysc-midle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_NO>,
267 <SYSC_IDLE_SMART>;
268 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
269 <SYSC_IDLE_NO>,
270 <SYSC_IDLE_SMART>;
271 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
272 clock-names = "fck";
273 #address-cells = <1>;
274 #size-cells = <1>;
275 ranges = <0 0x56000000 0x2000000>;
276
277 /*
278 * Closed source PowerVR driver, no child device
279 * binding or driver in mainline
280 */
281 };
282
283 dss: dss@58000000 {
284 compatible = "ti,omap5-dss";
285 reg = <0x58000000 0x80>;
286 status = "disabled";
287 ti,hwmods = "dss_core";
288 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
289 clock-names = "fck";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293
294 dispc@58001000 {
295 compatible = "ti,omap5-dispc";
296 reg = <0x58001000 0x1000>;
297 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
298 ti,hwmods = "dss_dispc";
299 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
300 clock-names = "fck";
301 };
302
303 rfbi: encoder@58002000 {
304 compatible = "ti,omap5-rfbi";
305 reg = <0x58002000 0x100>;
306 status = "disabled";
307 ti,hwmods = "dss_rfbi";
308 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
309 clock-names = "fck", "ick";
310 };
311
312 dsi1: encoder@58004000 {
313 compatible = "ti,omap5-dsi";
314 reg = <0x58004000 0x200>,
315 <0x58004200 0x40>,
316 <0x58004300 0x40>;
317 reg-names = "proto", "phy", "pll";
318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
319 status = "disabled";
320 ti,hwmods = "dss_dsi1";
321 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
322 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
323 clock-names = "fck", "sys_clk";
324 };
325
326 dsi2: encoder@58005000 {
327 compatible = "ti,omap5-dsi";
328 reg = <0x58009000 0x200>,
329 <0x58009200 0x40>,
330 <0x58009300 0x40>;
331 reg-names = "proto", "phy", "pll";
332 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
333 status = "disabled";
334 ti,hwmods = "dss_dsi2";
335 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
336 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
337 clock-names = "fck", "sys_clk";
338 };
339
340 hdmi: encoder@58060000 {
341 compatible = "ti,omap5-hdmi";
342 reg = <0x58040000 0x200>,
343 <0x58040200 0x80>,
344 <0x58040300 0x80>,
345 <0x58060000 0x19000>;
346 reg-names = "wp", "pll", "phy", "core";
347 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
348 status = "disabled";
349 ti,hwmods = "dss_hdmi";
350 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
351 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
352 clock-names = "fck", "sys_clk";
353 dmas = <&sdma 76>;
354 dma-names = "audio_tx";
355 };
356 };
357
358 abb_mpu: regulator-abb-mpu {
359 compatible = "ti,abb-v2";
360 regulator-name = "abb_mpu";
361 #address-cells = <0>;
362 #size-cells = <0>;
363 clocks = <&sys_clkin>;
364 ti,settling-time = <50>;
365 ti,clock-cycles = <16>;
366
367 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
368 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
369 reg-names = "base-address", "int-address",
370 "efuse-address", "ldo-address";
371 ti,tranxdone-status-mask = <0x80>;
372 /* LDOVBBMPU_MUX_CTRL */
373 ti,ldovbb-override-mask = <0x400>;
374 /* LDOVBBMPU_VSET_OUT */
375 ti,ldovbb-vset-mask = <0x1F>;
376
377 /*
378 * NOTE: only FBB mode used but actual vset will
379 * determine final biasing
380 */
381 ti,abb_info = <
382 /*uV ABB efuse rbb_m fbb_m vset_m*/
383 1060000 0 0x0 0 0x02000000 0x01F00000
384 1250000 0 0x4 0 0x02000000 0x01F00000
385 >;
386 };
387
388 abb_mm: regulator-abb-mm {
389 compatible = "ti,abb-v2";
390 regulator-name = "abb_mm";
391 #address-cells = <0>;
392 #size-cells = <0>;
393 clocks = <&sys_clkin>;
394 ti,settling-time = <50>;
395 ti,clock-cycles = <16>;
396
397 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
398 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
399 reg-names = "base-address", "int-address",
400 "efuse-address", "ldo-address";
401 ti,tranxdone-status-mask = <0x80000000>;
402 /* LDOVBBMM_MUX_CTRL */
403 ti,ldovbb-override-mask = <0x400>;
404 /* LDOVBBMM_VSET_OUT */
405 ti,ldovbb-vset-mask = <0x1F>;
406
407 /*
408 * NOTE: only FBB mode used but actual vset will
409 * determine final biasing
410 */
411 ti,abb_info = <
412 /*uV ABB efuse rbb_m fbb_m vset_m*/
413 1025000 0 0x0 0 0x02000000 0x01F00000
414 1120000 0 0x4 0 0x02000000 0x01F00000
415 >;
416 };
417 };
418};
419
420&cpu_thermal {
421 polling-delay = <500>; /* milliseconds */
422 coefficients = <65 (-1791)>;
423};
424
425#include "omap5-l4.dtsi"
426#include "omap54xx-clocks.dtsi"
427
428&gpu_thermal {
429 coefficients = <117 (-2992)>;
430};
431
432&core_thermal {
433 coefficients = <0 2000>;
434};
435
436#include "omap5-l4-abe.dtsi"
437#include "omap54xx-clocks.dtsi"
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 rproc0 = &dsp;
35 rproc1 = &ipu;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 cpu0: cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <0x0>;
46
47 operating-points = <
48 /* kHz uV */
49 1000000 1060000
50 1500000 1250000
51 >;
52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
56 clock-latency = <300000>; /* From omap-cpufreq driver */
57
58 /* cooling options */
59 #cooling-cells = <2>; /* min followed by max */
60 };
61 cpu@1 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0x1>;
65
66 operating-points = <
67 /* kHz uV */
68 1000000 1060000
69 1500000 1250000
70 >;
71
72 clocks = <&dpll_mpu_ck>;
73 clock-names = "cpu";
74
75 clock-latency = <300000>; /* From omap-cpufreq driver */
76
77 /* cooling options */
78 #cooling-cells = <2>; /* min followed by max */
79 };
80 };
81
82 thermal-zones {
83 #include "omap4-cpu-thermal.dtsi"
84 #include "omap5-gpu-thermal.dtsi"
85 #include "omap5-core-thermal.dtsi"
86 };
87
88 timer {
89 compatible = "arm,armv7-timer";
90 /* PPI secure/nonsecure IRQ */
91 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
95 interrupt-parent = <&gic>;
96 };
97
98 pmu {
99 compatible = "arm,cortex-a15-pmu";
100 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
102 };
103
104 gic: interrupt-controller@48211000 {
105 compatible = "arm,cortex-a15-gic";
106 interrupt-controller;
107 #interrupt-cells = <3>;
108 reg = <0 0x48211000 0 0x1000>,
109 <0 0x48212000 0 0x2000>,
110 <0 0x48214000 0 0x2000>,
111 <0 0x48216000 0 0x2000>;
112 interrupt-parent = <&gic>;
113 };
114
115 wakeupgen: interrupt-controller@48281000 {
116 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
117 interrupt-controller;
118 #interrupt-cells = <3>;
119 reg = <0 0x48281000 0 0x1000>;
120 interrupt-parent = <&gic>;
121 };
122
123 /*
124 * The soc node represents the soc top level view. It is used for IPs
125 * that are not memory mapped in the MPU view or for the MPU itself.
126 */
127 soc {
128 compatible = "ti,omap-infra";
129 mpu {
130 compatible = "ti,omap4-mpu";
131 ti,hwmods = "mpu";
132 sram = <&ocmcram>;
133 };
134 };
135
136 /*
137 * XXX: Use a flat representation of the OMAP3 interconnect.
138 * The real OMAP interconnect network is quite complex.
139 * Since it will not bring real advantage to represent that in DT for
140 * the moment, just use a fake OCP bus entry to represent the whole bus
141 * hierarchy.
142 */
143 ocp {
144 compatible = "ti,omap5-l3-noc", "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0 0 0xc0000000>;
148 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
149 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
150 reg = <0 0x44000000 0 0x2000>,
151 <0 0x44800000 0 0x3000>,
152 <0 0x45000000 0 0x4000>;
153 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
155
156 l4_wkup: interconnect@4ae00000 {
157 };
158
159 l4_cfg: interconnect@4a000000 {
160 };
161
162 l4_per: interconnect@48000000 {
163 };
164
165 l4_abe: interconnect@40100000 {
166 };
167
168 ocmcram: sram@40300000 {
169 compatible = "mmio-sram";
170 reg = <0x40300000 0x20000>; /* 128k */
171 };
172
173 gpmc: gpmc@50000000 {
174 compatible = "ti,omap4430-gpmc";
175 reg = <0x50000000 0x1000>;
176 #address-cells = <2>;
177 #size-cells = <1>;
178 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
179 dmas = <&sdma 4>;
180 dma-names = "rxtx";
181 gpmc,num-cs = <8>;
182 gpmc,num-waitpins = <4>;
183 ti,hwmods = "gpmc";
184 clocks = <&l3_iclk_div>;
185 clock-names = "fck";
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 };
191
192 target-module@55082000 {
193 compatible = "ti,sysc-omap2", "ti,sysc";
194 reg = <0x55082000 0x4>,
195 <0x55082010 0x4>,
196 <0x55082014 0x4>;
197 reg-names = "rev", "sysc", "syss";
198 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_NO>,
200 <SYSC_IDLE_SMART>;
201 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
202 SYSC_OMAP2_SOFTRESET |
203 SYSC_OMAP2_AUTOIDLE)>;
204 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
205 clock-names = "fck";
206 resets = <&prm_core 2>;
207 reset-names = "rstctrl";
208 ranges = <0x0 0x55082000 0x100>;
209 #size-cells = <1>;
210 #address-cells = <1>;
211
212 mmu_ipu: mmu@0 {
213 compatible = "ti,omap4-iommu";
214 reg = <0x0 0x100>;
215 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
216 #iommu-cells = <0>;
217 ti,iommu-bus-err-back;
218 };
219 };
220
221 dsp: dsp {
222 compatible = "ti,omap5-dsp";
223 ti,bootreg = <&scm_conf 0x304 0>;
224 iommus = <&mmu_dsp>;
225 resets = <&prm_dsp 0>;
226 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
227 firmware-name = "omap5-dsp-fw.xe64T";
228 mboxes = <&mailbox &mbox_dsp>;
229 status = "disabled";
230 };
231
232 ipu: ipu@55020000 {
233 compatible = "ti,omap5-ipu";
234 reg = <0x55020000 0x10000>;
235 reg-names = "l2ram";
236 iommus = <&mmu_ipu>;
237 resets = <&prm_core 0>, <&prm_core 1>;
238 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
239 firmware-name = "omap5-ipu-fw.xem4";
240 mboxes = <&mailbox &mbox_ipu>;
241 status = "disabled";
242 };
243
244 dmm@4e000000 {
245 compatible = "ti,omap5-dmm";
246 reg = <0x4e000000 0x800>;
247 interrupts = <0 113 0x4>;
248 ti,hwmods = "dmm";
249 };
250
251 emif1: emif@4c000000 {
252 compatible = "ti,emif-4d5";
253 ti,hwmods = "emif1";
254 ti,no-idle-on-init;
255 phy-type = <2>; /* DDR PHY type: Intelli PHY */
256 reg = <0x4c000000 0x400>;
257 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
258 hw-caps-read-idle-ctrl;
259 hw-caps-ll-interface;
260 hw-caps-temp-alert;
261 };
262
263 emif2: emif@4d000000 {
264 compatible = "ti,emif-4d5";
265 ti,hwmods = "emif2";
266 ti,no-idle-on-init;
267 phy-type = <2>; /* DDR PHY type: Intelli PHY */
268 reg = <0x4d000000 0x400>;
269 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
270 hw-caps-read-idle-ctrl;
271 hw-caps-ll-interface;
272 hw-caps-temp-alert;
273 };
274
275 aes1_target: target-module@4b501000 {
276 compatible = "ti,sysc-omap2", "ti,sysc";
277 reg = <0x4b501080 0x4>,
278 <0x4b501084 0x4>,
279 <0x4b501088 0x4>;
280 reg-names = "rev", "sysc", "syss";
281 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
282 SYSC_OMAP2_AUTOIDLE)>;
283 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
284 <SYSC_IDLE_NO>,
285 <SYSC_IDLE_SMART>,
286 <SYSC_IDLE_SMART_WKUP>;
287 ti,syss-mask = <1>;
288 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
289 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
290 clock-names = "fck";
291 #address-cells = <1>;
292 #size-cells = <1>;
293 ranges = <0x0 0x4b501000 0x1000>;
294
295 aes1: aes@0 {
296 compatible = "ti,omap4-aes";
297 reg = <0 0xa0>;
298 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
299 dmas = <&sdma 111>, <&sdma 110>;
300 dma-names = "tx", "rx";
301 };
302 };
303
304 aes2_target: target-module@4b701000 {
305 compatible = "ti,sysc-omap2", "ti,sysc";
306 reg = <0x4b701080 0x4>,
307 <0x4b701084 0x4>,
308 <0x4b701088 0x4>;
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311 SYSC_OMAP2_AUTOIDLE)>;
312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313 <SYSC_IDLE_NO>,
314 <SYSC_IDLE_SMART>,
315 <SYSC_IDLE_SMART_WKUP>;
316 ti,syss-mask = <1>;
317 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
318 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
319 clock-names = "fck";
320 #address-cells = <1>;
321 #size-cells = <1>;
322 ranges = <0x0 0x4b701000 0x1000>;
323
324 aes2: aes@0 {
325 compatible = "ti,omap4-aes";
326 reg = <0 0xa0>;
327 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
328 dmas = <&sdma 114>, <&sdma 113>;
329 dma-names = "tx", "rx";
330 };
331 };
332
333 sham_target: target-module@4b100000 {
334 compatible = "ti,sysc-omap3-sham", "ti,sysc";
335 reg = <0x4b100100 0x4>,
336 <0x4b100110 0x4>,
337 <0x4b100114 0x4>;
338 reg-names = "rev", "sysc", "syss";
339 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
340 SYSC_OMAP2_AUTOIDLE)>;
341 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
342 <SYSC_IDLE_NO>,
343 <SYSC_IDLE_SMART>;
344 ti,syss-mask = <1>;
345 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
346 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
347 clock-names = "fck";
348 #address-cells = <1>;
349 #size-cells = <1>;
350 ranges = <0x0 0x4b100000 0x1000>;
351
352 sham: sham@0 {
353 compatible = "ti,omap4-sham";
354 reg = <0 0x300>;
355 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
356 dmas = <&sdma 119>;
357 dma-names = "rx";
358 };
359 };
360
361 bandgap: bandgap@4a0021e0 {
362 reg = <0x4a0021e0 0xc
363 0x4a00232c 0xc
364 0x4a002380 0x2c
365 0x4a0023C0 0x3c>;
366 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
367 compatible = "ti,omap5430-bandgap";
368
369 #thermal-sensor-cells = <1>;
370 };
371
372 /* OCP2SCP3 */
373 sata: sata@4a141100 {
374 compatible = "snps,dwc-ahci";
375 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
376 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
377 phys = <&sata_phy>;
378 phy-names = "sata-phy";
379 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
380 ti,hwmods = "sata";
381 ports-implemented = <0x1>;
382 };
383
384 target-module@56000000 {
385 compatible = "ti,sysc-omap4", "ti,sysc";
386 reg = <0x5600fe00 0x4>,
387 <0x5600fe10 0x4>;
388 reg-names = "rev", "sysc";
389 ti,sysc-midle = <SYSC_IDLE_FORCE>,
390 <SYSC_IDLE_NO>,
391 <SYSC_IDLE_SMART>;
392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
393 <SYSC_IDLE_NO>,
394 <SYSC_IDLE_SMART>;
395 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
396 clock-names = "fck";
397 #address-cells = <1>;
398 #size-cells = <1>;
399 ranges = <0 0x56000000 0x2000000>;
400
401 /*
402 * Closed source PowerVR driver, no child device
403 * binding or driver in mainline
404 */
405 };
406
407 target-module@58000000 {
408 compatible = "ti,sysc-omap2", "ti,sysc";
409 reg = <0x58000000 4>,
410 <0x58000014 4>;
411 reg-names = "rev", "syss";
412 ti,syss-mask = <1>;
413 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
414 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
415 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
416 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
417 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
418 #address-cells = <1>;
419 #size-cells = <1>;
420 ranges = <0 0x58000000 0x1000000>;
421
422 dss: dss@0 {
423 compatible = "ti,omap5-dss";
424 reg = <0 0x80>;
425 status = "disabled";
426 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
427 clock-names = "fck";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0 0 0x1000000>;
431
432 target-module@1000 {
433 compatible = "ti,sysc-omap2", "ti,sysc";
434 reg = <0x1000 0x4>,
435 <0x1010 0x4>,
436 <0x1014 0x4>;
437 reg-names = "rev", "sysc", "syss";
438 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
439 <SYSC_IDLE_NO>,
440 <SYSC_IDLE_SMART>;
441 ti,sysc-midle = <SYSC_IDLE_FORCE>,
442 <SYSC_IDLE_NO>,
443 <SYSC_IDLE_SMART>;
444 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
445 SYSC_OMAP2_ENAWAKEUP |
446 SYSC_OMAP2_SOFTRESET |
447 SYSC_OMAP2_AUTOIDLE)>;
448 ti,syss-mask = <1>;
449 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
450 clock-names = "fck";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ranges = <0 0x1000 0x1000>;
454
455 dispc@0 {
456 compatible = "ti,omap5-dispc";
457 reg = <0 0x1000>;
458 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
460 clock-names = "fck";
461 };
462 };
463
464 target-module@2000 {
465 compatible = "ti,sysc-omap2", "ti,sysc";
466 reg = <0x2000 0x4>,
467 <0x2010 0x4>,
468 <0x2014 0x4>;
469 reg-names = "rev", "sysc", "syss";
470 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
471 <SYSC_IDLE_NO>,
472 <SYSC_IDLE_SMART>;
473 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
474 SYSC_OMAP2_AUTOIDLE)>;
475 ti,syss-mask = <1>;
476 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
477 clock-names = "fck";
478 #address-cells = <1>;
479 #size-cells = <1>;
480 ranges = <0 0x2000 0x1000>;
481
482 rfbi: encoder@0 {
483 compatible = "ti,omap5-rfbi";
484 reg = <0 0x100>;
485 status = "disabled";
486 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
487 clock-names = "fck", "ick";
488 };
489 };
490
491 target-module@4000 {
492 compatible = "ti,sysc-omap2", "ti,sysc";
493 reg = <0x4000 0x4>,
494 <0x4010 0x4>,
495 <0x4014 0x4>;
496 reg-names = "rev", "sysc", "syss";
497 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
498 <SYSC_IDLE_NO>,
499 <SYSC_IDLE_SMART>;
500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
501 SYSC_OMAP2_ENAWAKEUP |
502 SYSC_OMAP2_SOFTRESET |
503 SYSC_OMAP2_AUTOIDLE)>;
504 ti,syss-mask = <1>;
505 #address-cells = <1>;
506 #size-cells = <1>;
507 ranges = <0 0x4000 0x1000>;
508
509 dsi1: encoder@0 {
510 compatible = "ti,omap5-dsi";
511 reg = <0 0x200>,
512 <0x200 0x40>,
513 <0x300 0x40>;
514 reg-names = "proto", "phy", "pll";
515 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
516 status = "disabled";
517 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
518 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
519 clock-names = "fck", "sys_clk";
520 };
521 };
522
523 target-module@9000 {
524 compatible = "ti,sysc-omap2", "ti,sysc";
525 reg = <0x9000 0x4>,
526 <0x9010 0x4>,
527 <0x9014 0x4>;
528 reg-names = "rev", "sysc", "syss";
529 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
530 <SYSC_IDLE_NO>,
531 <SYSC_IDLE_SMART>;
532 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
533 SYSC_OMAP2_ENAWAKEUP |
534 SYSC_OMAP2_SOFTRESET |
535 SYSC_OMAP2_AUTOIDLE)>;
536 ti,syss-mask = <1>;
537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges = <0 0x9000 0x1000>;
540
541 dsi2: encoder@0 {
542 compatible = "ti,omap5-dsi";
543 reg = <0 0x200>,
544 <0x200 0x40>,
545 <0x300 0x40>;
546 reg-names = "proto", "phy", "pll";
547 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
548 status = "disabled";
549 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
550 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
551 clock-names = "fck", "sys_clk";
552 };
553 };
554
555 target-module@40000 {
556 compatible = "ti,sysc-omap4", "ti,sysc";
557 reg = <0x40000 0x4>,
558 <0x40010 0x4>;
559 reg-names = "rev", "sysc";
560 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
561 <SYSC_IDLE_NO>,
562 <SYSC_IDLE_SMART>,
563 <SYSC_IDLE_SMART_WKUP>;
564 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
565 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
566 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
567 clock-names = "fck", "dss_clk";
568 #address-cells = <1>;
569 #size-cells = <1>;
570 ranges = <0 0x40000 0x40000>;
571
572 hdmi: encoder@0 {
573 compatible = "ti,omap5-hdmi";
574 reg = <0 0x200>,
575 <0x200 0x80>,
576 <0x300 0x80>,
577 <0x20000 0x19000>;
578 reg-names = "wp", "pll", "phy", "core";
579 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
580 status = "disabled";
581 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
582 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
583 clock-names = "fck", "sys_clk";
584 dmas = <&sdma 76>;
585 dma-names = "audio_tx";
586 };
587 };
588 };
589 };
590
591 abb_mpu: regulator-abb-mpu {
592 compatible = "ti,abb-v2";
593 regulator-name = "abb_mpu";
594 #address-cells = <0>;
595 #size-cells = <0>;
596 clocks = <&sys_clkin>;
597 ti,settling-time = <50>;
598 ti,clock-cycles = <16>;
599
600 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
601 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
602 reg-names = "base-address", "int-address",
603 "efuse-address", "ldo-address";
604 ti,tranxdone-status-mask = <0x80>;
605 /* LDOVBBMPU_MUX_CTRL */
606 ti,ldovbb-override-mask = <0x400>;
607 /* LDOVBBMPU_VSET_OUT */
608 ti,ldovbb-vset-mask = <0x1F>;
609
610 /*
611 * NOTE: only FBB mode used but actual vset will
612 * determine final biasing
613 */
614 ti,abb_info = <
615 /*uV ABB efuse rbb_m fbb_m vset_m*/
616 1060000 0 0x0 0 0x02000000 0x01F00000
617 1250000 0 0x4 0 0x02000000 0x01F00000
618 >;
619 };
620
621 abb_mm: regulator-abb-mm {
622 compatible = "ti,abb-v2";
623 regulator-name = "abb_mm";
624 #address-cells = <0>;
625 #size-cells = <0>;
626 clocks = <&sys_clkin>;
627 ti,settling-time = <50>;
628 ti,clock-cycles = <16>;
629
630 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
631 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
632 reg-names = "base-address", "int-address",
633 "efuse-address", "ldo-address";
634 ti,tranxdone-status-mask = <0x80000000>;
635 /* LDOVBBMM_MUX_CTRL */
636 ti,ldovbb-override-mask = <0x400>;
637 /* LDOVBBMM_VSET_OUT */
638 ti,ldovbb-vset-mask = <0x1F>;
639
640 /*
641 * NOTE: only FBB mode used but actual vset will
642 * determine final biasing
643 */
644 ti,abb_info = <
645 /*uV ABB efuse rbb_m fbb_m vset_m*/
646 1025000 0 0x0 0 0x02000000 0x01F00000
647 1120000 0 0x4 0 0x02000000 0x01F00000
648 >;
649 };
650 };
651};
652
653&cpu_thermal {
654 polling-delay = <500>; /* milliseconds */
655 coefficients = <65 (-1791)>;
656};
657
658#include "omap5-l4.dtsi"
659#include "omap54xx-clocks.dtsi"
660
661&gpu_thermal {
662 coefficients = <117 (-2992)>;
663};
664
665&core_thermal {
666 coefficients = <0 2000>;
667};
668
669#include "omap5-l4-abe.dtsi"
670#include "omap54xx-clocks.dtsi"
671
672&prm {
673 prm_dsp: prm@400 {
674 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
675 reg = <0x400 0x100>;
676 #reset-cells = <1>;
677 };
678
679 prm_core: prm@700 {
680 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
681 reg = <0x700 0x100>;
682 #reset-cells = <1>;
683 };
684
685 prm_iva: prm@1200 {
686 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
687 reg = <0x1200 0x100>;
688 #reset-cells = <1>;
689 };
690
691 prm_device: prm@1c00 {
692 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
693 reg = <0x1c00 0x100>;
694 #reset-cells = <1>;
695 };
696};
697
698/* Preferred always-on timer for clockevent */
699&timer1_target {
700 ti,no-reset-on-init;
701 ti,no-idle;
702 timer@0 {
703 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
704 assigned-clock-parents = <&sys_32k_ck>;
705 };
706};