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1/* Generic MTRR (Memory Type Range Register) driver.
2
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
5
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
10
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
15
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
23
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
26 section 11.11.7
27
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
29 on 6-7 March 2002.
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
32*/
33
34#define DEBUG
35
36#include <linux/types.h> /* FIXME: kvm_para.h needs this */
37
38#include <linux/stop_machine.h>
39#include <linux/kvm_para.h>
40#include <linux/uaccess.h>
41#include <linux/export.h>
42#include <linux/mutex.h>
43#include <linux/init.h>
44#include <linux/sort.h>
45#include <linux/cpu.h>
46#include <linux/pci.h>
47#include <linux/smp.h>
48#include <linux/syscore_ops.h>
49#include <linux/rcupdate.h>
50
51#include <asm/cpufeature.h>
52#include <asm/e820/api.h>
53#include <asm/mtrr.h>
54#include <asm/msr.h>
55#include <asm/pat.h>
56
57#include "mtrr.h"
58
59/* arch_phys_wc_add returns an MTRR register index plus this offset. */
60#define MTRR_TO_PHYS_WC_OFFSET 1000
61
62u32 num_var_ranges;
63static bool __mtrr_enabled;
64
65static bool mtrr_enabled(void)
66{
67 return __mtrr_enabled;
68}
69
70unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
71static DEFINE_MUTEX(mtrr_mutex);
72
73u64 size_or_mask, size_and_mask;
74static bool mtrr_aps_delayed_init;
75
76static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM] __ro_after_init;
77
78const struct mtrr_ops *mtrr_if;
79
80static void set_mtrr(unsigned int reg, unsigned long base,
81 unsigned long size, mtrr_type type);
82
83void __init set_mtrr_ops(const struct mtrr_ops *ops)
84{
85 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
86 mtrr_ops[ops->vendor] = ops;
87}
88
89/* Returns non-zero if we have the write-combining memory type */
90static int have_wrcomb(void)
91{
92 struct pci_dev *dev;
93
94 dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
95 if (dev != NULL) {
96 /*
97 * ServerWorks LE chipsets < rev 6 have problems with
98 * write-combining. Don't allow it and leave room for other
99 * chipsets to be tagged
100 */
101 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
102 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
103 dev->revision <= 5) {
104 pr_info("Serverworks LE rev < 6 detected. Write-combining disabled.\n");
105 pci_dev_put(dev);
106 return 0;
107 }
108 /*
109 * Intel 450NX errata # 23. Non ascending cacheline evictions to
110 * write combining memory may resulting in data corruption
111 */
112 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
113 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
114 pr_info("Intel 450NX MMC detected. Write-combining disabled.\n");
115 pci_dev_put(dev);
116 return 0;
117 }
118 pci_dev_put(dev);
119 }
120 return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
121}
122
123/* This function returns the number of variable MTRRs */
124static void __init set_num_var_ranges(void)
125{
126 unsigned long config = 0, dummy;
127
128 if (use_intel())
129 rdmsr(MSR_MTRRcap, config, dummy);
130 else if (is_cpu(AMD) || is_cpu(HYGON))
131 config = 2;
132 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
133 config = 8;
134
135 num_var_ranges = config & 0xff;
136}
137
138static void __init init_table(void)
139{
140 int i, max;
141
142 max = num_var_ranges;
143 for (i = 0; i < max; i++)
144 mtrr_usage_table[i] = 1;
145}
146
147struct set_mtrr_data {
148 unsigned long smp_base;
149 unsigned long smp_size;
150 unsigned int smp_reg;
151 mtrr_type smp_type;
152};
153
154/**
155 * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
156 * by all the CPUs.
157 * @info: pointer to mtrr configuration data
158 *
159 * Returns nothing.
160 */
161static int mtrr_rendezvous_handler(void *info)
162{
163 struct set_mtrr_data *data = info;
164
165 /*
166 * We use this same function to initialize the mtrrs during boot,
167 * resume, runtime cpu online and on an explicit request to set a
168 * specific MTRR.
169 *
170 * During boot or suspend, the state of the boot cpu's mtrrs has been
171 * saved, and we want to replicate that across all the cpus that come
172 * online (either at the end of boot or resume or during a runtime cpu
173 * online). If we're doing that, @reg is set to something special and on
174 * all the cpu's we do mtrr_if->set_all() (On the logical cpu that
175 * started the boot/resume sequence, this might be a duplicate
176 * set_all()).
177 */
178 if (data->smp_reg != ~0U) {
179 mtrr_if->set(data->smp_reg, data->smp_base,
180 data->smp_size, data->smp_type);
181 } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) {
182 mtrr_if->set_all();
183 }
184 return 0;
185}
186
187static inline int types_compatible(mtrr_type type1, mtrr_type type2)
188{
189 return type1 == MTRR_TYPE_UNCACHABLE ||
190 type2 == MTRR_TYPE_UNCACHABLE ||
191 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
192 (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
193}
194
195/**
196 * set_mtrr - update mtrrs on all processors
197 * @reg: mtrr in question
198 * @base: mtrr base
199 * @size: mtrr size
200 * @type: mtrr type
201 *
202 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
203 *
204 * 1. Queue work to do the following on all processors:
205 * 2. Disable Interrupts
206 * 3. Wait for all procs to do so
207 * 4. Enter no-fill cache mode
208 * 5. Flush caches
209 * 6. Clear PGE bit
210 * 7. Flush all TLBs
211 * 8. Disable all range registers
212 * 9. Update the MTRRs
213 * 10. Enable all range registers
214 * 11. Flush all TLBs and caches again
215 * 12. Enter normal cache mode and reenable caching
216 * 13. Set PGE
217 * 14. Wait for buddies to catch up
218 * 15. Enable interrupts.
219 *
220 * What does that mean for us? Well, stop_machine() will ensure that
221 * the rendezvous handler is started on each CPU. And in lockstep they
222 * do the state transition of disabling interrupts, updating MTRR's
223 * (the CPU vendors may each do it differently, so we call mtrr_if->set()
224 * callback and let them take care of it.) and enabling interrupts.
225 *
226 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
227 * becomes nops.
228 */
229static void
230set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
231{
232 struct set_mtrr_data data = { .smp_reg = reg,
233 .smp_base = base,
234 .smp_size = size,
235 .smp_type = type
236 };
237
238 stop_machine(mtrr_rendezvous_handler, &data, cpu_online_mask);
239}
240
241static void set_mtrr_cpuslocked(unsigned int reg, unsigned long base,
242 unsigned long size, mtrr_type type)
243{
244 struct set_mtrr_data data = { .smp_reg = reg,
245 .smp_base = base,
246 .smp_size = size,
247 .smp_type = type
248 };
249
250 stop_machine_cpuslocked(mtrr_rendezvous_handler, &data, cpu_online_mask);
251}
252
253static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base,
254 unsigned long size, mtrr_type type)
255{
256 struct set_mtrr_data data = { .smp_reg = reg,
257 .smp_base = base,
258 .smp_size = size,
259 .smp_type = type
260 };
261
262 stop_machine_from_inactive_cpu(mtrr_rendezvous_handler, &data,
263 cpu_callout_mask);
264}
265
266/**
267 * mtrr_add_page - Add a memory type region
268 * @base: Physical base address of region in pages (in units of 4 kB!)
269 * @size: Physical size of region in pages (4 kB)
270 * @type: Type of MTRR desired
271 * @increment: If this is true do usage counting on the region
272 *
273 * Memory type region registers control the caching on newer Intel and
274 * non Intel processors. This function allows drivers to request an
275 * MTRR is added. The details and hardware specifics of each processor's
276 * implementation are hidden from the caller, but nevertheless the
277 * caller should expect to need to provide a power of two size on an
278 * equivalent power of two boundary.
279 *
280 * If the region cannot be added either because all regions are in use
281 * or the CPU cannot support it a negative value is returned. On success
282 * the register number for this entry is returned, but should be treated
283 * as a cookie only.
284 *
285 * On a multiprocessor machine the changes are made to all processors.
286 * This is required on x86 by the Intel processors.
287 *
288 * The available types are
289 *
290 * %MTRR_TYPE_UNCACHABLE - No caching
291 *
292 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
293 *
294 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
295 *
296 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
297 *
298 * BUGS: Needs a quiet flag for the cases where drivers do not mind
299 * failures and do not wish system log messages to be sent.
300 */
301int mtrr_add_page(unsigned long base, unsigned long size,
302 unsigned int type, bool increment)
303{
304 unsigned long lbase, lsize;
305 int i, replace, error;
306 mtrr_type ltype;
307
308 if (!mtrr_enabled())
309 return -ENXIO;
310
311 error = mtrr_if->validate_add_page(base, size, type);
312 if (error)
313 return error;
314
315 if (type >= MTRR_NUM_TYPES) {
316 pr_warn("type: %u invalid\n", type);
317 return -EINVAL;
318 }
319
320 /* If the type is WC, check that this processor supports it */
321 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
322 pr_warn("your processor doesn't support write-combining\n");
323 return -ENOSYS;
324 }
325
326 if (!size) {
327 pr_warn("zero sized request\n");
328 return -EINVAL;
329 }
330
331 if ((base | (base + size - 1)) >>
332 (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
333 pr_warn("base or size exceeds the MTRR width\n");
334 return -EINVAL;
335 }
336
337 error = -EINVAL;
338 replace = -1;
339
340 /* No CPU hotplug when we change MTRR entries */
341 get_online_cpus();
342
343 /* Search for existing MTRR */
344 mutex_lock(&mtrr_mutex);
345 for (i = 0; i < num_var_ranges; ++i) {
346 mtrr_if->get(i, &lbase, &lsize, <ype);
347 if (!lsize || base > lbase + lsize - 1 ||
348 base + size - 1 < lbase)
349 continue;
350 /*
351 * At this point we know there is some kind of
352 * overlap/enclosure
353 */
354 if (base < lbase || base + size - 1 > lbase + lsize - 1) {
355 if (base <= lbase &&
356 base + size - 1 >= lbase + lsize - 1) {
357 /* New region encloses an existing region */
358 if (type == ltype) {
359 replace = replace == -1 ? i : -2;
360 continue;
361 } else if (types_compatible(type, ltype))
362 continue;
363 }
364 pr_warn("0x%lx000,0x%lx000 overlaps existing 0x%lx000,0x%lx000\n", base, size, lbase,
365 lsize);
366 goto out;
367 }
368 /* New region is enclosed by an existing region */
369 if (ltype != type) {
370 if (types_compatible(type, ltype))
371 continue;
372 pr_warn("type mismatch for %lx000,%lx000 old: %s new: %s\n",
373 base, size, mtrr_attrib_to_str(ltype),
374 mtrr_attrib_to_str(type));
375 goto out;
376 }
377 if (increment)
378 ++mtrr_usage_table[i];
379 error = i;
380 goto out;
381 }
382 /* Search for an empty MTRR */
383 i = mtrr_if->get_free_region(base, size, replace);
384 if (i >= 0) {
385 set_mtrr_cpuslocked(i, base, size, type);
386 if (likely(replace < 0)) {
387 mtrr_usage_table[i] = 1;
388 } else {
389 mtrr_usage_table[i] = mtrr_usage_table[replace];
390 if (increment)
391 mtrr_usage_table[i]++;
392 if (unlikely(replace != i)) {
393 set_mtrr_cpuslocked(replace, 0, 0, 0);
394 mtrr_usage_table[replace] = 0;
395 }
396 }
397 } else {
398 pr_info("no more MTRRs available\n");
399 }
400 error = i;
401 out:
402 mutex_unlock(&mtrr_mutex);
403 put_online_cpus();
404 return error;
405}
406
407static int mtrr_check(unsigned long base, unsigned long size)
408{
409 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
410 pr_warn("size and base must be multiples of 4 kiB\n");
411 pr_debug("size: 0x%lx base: 0x%lx\n", size, base);
412 dump_stack();
413 return -1;
414 }
415 return 0;
416}
417
418/**
419 * mtrr_add - Add a memory type region
420 * @base: Physical base address of region
421 * @size: Physical size of region
422 * @type: Type of MTRR desired
423 * @increment: If this is true do usage counting on the region
424 *
425 * Memory type region registers control the caching on newer Intel and
426 * non Intel processors. This function allows drivers to request an
427 * MTRR is added. The details and hardware specifics of each processor's
428 * implementation are hidden from the caller, but nevertheless the
429 * caller should expect to need to provide a power of two size on an
430 * equivalent power of two boundary.
431 *
432 * If the region cannot be added either because all regions are in use
433 * or the CPU cannot support it a negative value is returned. On success
434 * the register number for this entry is returned, but should be treated
435 * as a cookie only.
436 *
437 * On a multiprocessor machine the changes are made to all processors.
438 * This is required on x86 by the Intel processors.
439 *
440 * The available types are
441 *
442 * %MTRR_TYPE_UNCACHABLE - No caching
443 *
444 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
445 *
446 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
447 *
448 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
449 *
450 * BUGS: Needs a quiet flag for the cases where drivers do not mind
451 * failures and do not wish system log messages to be sent.
452 */
453int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
454 bool increment)
455{
456 if (!mtrr_enabled())
457 return -ENODEV;
458 if (mtrr_check(base, size))
459 return -EINVAL;
460 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
461 increment);
462}
463
464/**
465 * mtrr_del_page - delete a memory type region
466 * @reg: Register returned by mtrr_add
467 * @base: Physical base address
468 * @size: Size of region
469 *
470 * If register is supplied then base and size are ignored. This is
471 * how drivers should call it.
472 *
473 * Releases an MTRR region. If the usage count drops to zero the
474 * register is freed and the region returns to default state.
475 * On success the register is returned, on failure a negative error
476 * code.
477 */
478int mtrr_del_page(int reg, unsigned long base, unsigned long size)
479{
480 int i, max;
481 mtrr_type ltype;
482 unsigned long lbase, lsize;
483 int error = -EINVAL;
484
485 if (!mtrr_enabled())
486 return -ENODEV;
487
488 max = num_var_ranges;
489 /* No CPU hotplug when we change MTRR entries */
490 get_online_cpus();
491 mutex_lock(&mtrr_mutex);
492 if (reg < 0) {
493 /* Search for existing MTRR */
494 for (i = 0; i < max; ++i) {
495 mtrr_if->get(i, &lbase, &lsize, <ype);
496 if (lbase == base && lsize == size) {
497 reg = i;
498 break;
499 }
500 }
501 if (reg < 0) {
502 pr_debug("no MTRR for %lx000,%lx000 found\n",
503 base, size);
504 goto out;
505 }
506 }
507 if (reg >= max) {
508 pr_warn("register: %d too big\n", reg);
509 goto out;
510 }
511 mtrr_if->get(reg, &lbase, &lsize, <ype);
512 if (lsize < 1) {
513 pr_warn("MTRR %d not used\n", reg);
514 goto out;
515 }
516 if (mtrr_usage_table[reg] < 1) {
517 pr_warn("reg: %d has count=0\n", reg);
518 goto out;
519 }
520 if (--mtrr_usage_table[reg] < 1)
521 set_mtrr_cpuslocked(reg, 0, 0, 0);
522 error = reg;
523 out:
524 mutex_unlock(&mtrr_mutex);
525 put_online_cpus();
526 return error;
527}
528
529/**
530 * mtrr_del - delete a memory type region
531 * @reg: Register returned by mtrr_add
532 * @base: Physical base address
533 * @size: Size of region
534 *
535 * If register is supplied then base and size are ignored. This is
536 * how drivers should call it.
537 *
538 * Releases an MTRR region. If the usage count drops to zero the
539 * register is freed and the region returns to default state.
540 * On success the register is returned, on failure a negative error
541 * code.
542 */
543int mtrr_del(int reg, unsigned long base, unsigned long size)
544{
545 if (!mtrr_enabled())
546 return -ENODEV;
547 if (mtrr_check(base, size))
548 return -EINVAL;
549 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
550}
551
552/**
553 * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable
554 * @base: Physical base address
555 * @size: Size of region
556 *
557 * If PAT is available, this does nothing. If PAT is unavailable, it
558 * attempts to add a WC MTRR covering size bytes starting at base and
559 * logs an error if this fails.
560 *
561 * The called should provide a power of two size on an equivalent
562 * power of two boundary.
563 *
564 * Drivers must store the return value to pass to mtrr_del_wc_if_needed,
565 * but drivers should not try to interpret that return value.
566 */
567int arch_phys_wc_add(unsigned long base, unsigned long size)
568{
569 int ret;
570
571 if (pat_enabled() || !mtrr_enabled())
572 return 0; /* Success! (We don't need to do anything.) */
573
574 ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true);
575 if (ret < 0) {
576 pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.",
577 (void *)base, (void *)(base + size - 1));
578 return ret;
579 }
580 return ret + MTRR_TO_PHYS_WC_OFFSET;
581}
582EXPORT_SYMBOL(arch_phys_wc_add);
583
584/*
585 * arch_phys_wc_del - undoes arch_phys_wc_add
586 * @handle: Return value from arch_phys_wc_add
587 *
588 * This cleans up after mtrr_add_wc_if_needed.
589 *
590 * The API guarantees that mtrr_del_wc_if_needed(error code) and
591 * mtrr_del_wc_if_needed(0) do nothing.
592 */
593void arch_phys_wc_del(int handle)
594{
595 if (handle >= 1) {
596 WARN_ON(handle < MTRR_TO_PHYS_WC_OFFSET);
597 mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0);
598 }
599}
600EXPORT_SYMBOL(arch_phys_wc_del);
601
602/*
603 * arch_phys_wc_index - translates arch_phys_wc_add's return value
604 * @handle: Return value from arch_phys_wc_add
605 *
606 * This will turn the return value from arch_phys_wc_add into an mtrr
607 * index suitable for debugging.
608 *
609 * Note: There is no legitimate use for this function, except possibly
610 * in printk line. Alas there is an illegitimate use in some ancient
611 * drm ioctls.
612 */
613int arch_phys_wc_index(int handle)
614{
615 if (handle < MTRR_TO_PHYS_WC_OFFSET)
616 return -1;
617 else
618 return handle - MTRR_TO_PHYS_WC_OFFSET;
619}
620EXPORT_SYMBOL_GPL(arch_phys_wc_index);
621
622/*
623 * HACK ALERT!
624 * These should be called implicitly, but we can't yet until all the initcall
625 * stuff is done...
626 */
627static void __init init_ifs(void)
628{
629#ifndef CONFIG_X86_64
630 amd_init_mtrr();
631 cyrix_init_mtrr();
632 centaur_init_mtrr();
633#endif
634}
635
636/* The suspend/resume methods are only for CPU without MTRR. CPU using generic
637 * MTRR driver doesn't require this
638 */
639struct mtrr_value {
640 mtrr_type ltype;
641 unsigned long lbase;
642 unsigned long lsize;
643};
644
645static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
646
647static int mtrr_save(void)
648{
649 int i;
650
651 for (i = 0; i < num_var_ranges; i++) {
652 mtrr_if->get(i, &mtrr_value[i].lbase,
653 &mtrr_value[i].lsize,
654 &mtrr_value[i].ltype);
655 }
656 return 0;
657}
658
659static void mtrr_restore(void)
660{
661 int i;
662
663 for (i = 0; i < num_var_ranges; i++) {
664 if (mtrr_value[i].lsize) {
665 set_mtrr(i, mtrr_value[i].lbase,
666 mtrr_value[i].lsize,
667 mtrr_value[i].ltype);
668 }
669 }
670}
671
672
673
674static struct syscore_ops mtrr_syscore_ops = {
675 .suspend = mtrr_save,
676 .resume = mtrr_restore,
677};
678
679int __initdata changed_by_mtrr_cleanup;
680
681#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
682/**
683 * mtrr_bp_init - initialize mtrrs on the boot CPU
684 *
685 * This needs to be called early; before any of the other CPUs are
686 * initialized (i.e. before smp_init()).
687 *
688 */
689void __init mtrr_bp_init(void)
690{
691 u32 phys_addr;
692
693 init_ifs();
694
695 phys_addr = 32;
696
697 if (boot_cpu_has(X86_FEATURE_MTRR)) {
698 mtrr_if = &generic_mtrr_ops;
699 size_or_mask = SIZE_OR_MASK_BITS(36);
700 size_and_mask = 0x00f00000;
701 phys_addr = 36;
702
703 /*
704 * This is an AMD specific MSR, but we assume(hope?) that
705 * Intel will implement it too when they extend the address
706 * bus of the Xeon.
707 */
708 if (cpuid_eax(0x80000000) >= 0x80000008) {
709 phys_addr = cpuid_eax(0x80000008) & 0xff;
710 /* CPUID workaround for Intel 0F33/0F34 CPU */
711 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
712 boot_cpu_data.x86 == 0xF &&
713 boot_cpu_data.x86_model == 0x3 &&
714 (boot_cpu_data.x86_stepping == 0x3 ||
715 boot_cpu_data.x86_stepping == 0x4))
716 phys_addr = 36;
717
718 size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
719 size_and_mask = ~size_or_mask & 0xfffff00000ULL;
720 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
721 boot_cpu_data.x86 == 6) {
722 /*
723 * VIA C* family have Intel style MTRRs,
724 * but don't support PAE
725 */
726 size_or_mask = SIZE_OR_MASK_BITS(32);
727 size_and_mask = 0;
728 phys_addr = 32;
729 }
730 } else {
731 switch (boot_cpu_data.x86_vendor) {
732 case X86_VENDOR_AMD:
733 if (cpu_feature_enabled(X86_FEATURE_K6_MTRR)) {
734 /* Pre-Athlon (K6) AMD CPU MTRRs */
735 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
736 size_or_mask = SIZE_OR_MASK_BITS(32);
737 size_and_mask = 0;
738 }
739 break;
740 case X86_VENDOR_CENTAUR:
741 if (cpu_feature_enabled(X86_FEATURE_CENTAUR_MCR)) {
742 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
743 size_or_mask = SIZE_OR_MASK_BITS(32);
744 size_and_mask = 0;
745 }
746 break;
747 case X86_VENDOR_CYRIX:
748 if (cpu_feature_enabled(X86_FEATURE_CYRIX_ARR)) {
749 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
750 size_or_mask = SIZE_OR_MASK_BITS(32);
751 size_and_mask = 0;
752 }
753 break;
754 default:
755 break;
756 }
757 }
758
759 if (mtrr_if) {
760 __mtrr_enabled = true;
761 set_num_var_ranges();
762 init_table();
763 if (use_intel()) {
764 /* BIOS may override */
765 __mtrr_enabled = get_mtrr_state();
766
767 if (mtrr_enabled())
768 mtrr_bp_pat_init();
769
770 if (mtrr_cleanup(phys_addr)) {
771 changed_by_mtrr_cleanup = 1;
772 mtrr_if->set_all();
773 }
774 }
775 }
776
777 if (!mtrr_enabled()) {
778 pr_info("Disabled\n");
779
780 /*
781 * PAT initialization relies on MTRR's rendezvous handler.
782 * Skip PAT init until the handler can initialize both
783 * features independently.
784 */
785 pat_disable("MTRRs disabled, skipping PAT initialization too.");
786 }
787}
788
789void mtrr_ap_init(void)
790{
791 if (!mtrr_enabled())
792 return;
793
794 if (!use_intel() || mtrr_aps_delayed_init)
795 return;
796
797 rcu_cpu_starting(smp_processor_id());
798
799 /*
800 * Ideally we should hold mtrr_mutex here to avoid mtrr entries
801 * changed, but this routine will be called in cpu boot time,
802 * holding the lock breaks it.
803 *
804 * This routine is called in two cases:
805 *
806 * 1. very earily time of software resume, when there absolutely
807 * isn't mtrr entry changes;
808 *
809 * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
810 * lock to prevent mtrr entry changes
811 */
812 set_mtrr_from_inactive_cpu(~0U, 0, 0, 0);
813}
814
815/**
816 * Save current fixed-range MTRR state of the first cpu in cpu_online_mask.
817 */
818void mtrr_save_state(void)
819{
820 int first_cpu;
821
822 if (!mtrr_enabled())
823 return;
824
825 first_cpu = cpumask_first(cpu_online_mask);
826 smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1);
827}
828
829void set_mtrr_aps_delayed_init(void)
830{
831 if (!mtrr_enabled())
832 return;
833 if (!use_intel())
834 return;
835
836 mtrr_aps_delayed_init = true;
837}
838
839/*
840 * Delayed MTRR initialization for all AP's
841 */
842void mtrr_aps_init(void)
843{
844 if (!use_intel() || !mtrr_enabled())
845 return;
846
847 /*
848 * Check if someone has requested the delay of AP MTRR initialization,
849 * by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
850 * then we are done.
851 */
852 if (!mtrr_aps_delayed_init)
853 return;
854
855 set_mtrr(~0U, 0, 0, 0);
856 mtrr_aps_delayed_init = false;
857}
858
859void mtrr_bp_restore(void)
860{
861 if (!use_intel() || !mtrr_enabled())
862 return;
863
864 mtrr_if->set_all();
865}
866
867static int __init mtrr_init_finialize(void)
868{
869 if (!mtrr_enabled())
870 return 0;
871
872 if (use_intel()) {
873 if (!changed_by_mtrr_cleanup)
874 mtrr_state_warn();
875 return 0;
876 }
877
878 /*
879 * The CPU has no MTRR and seems to not support SMP. They have
880 * specific drivers, we use a tricky method to support
881 * suspend/resume for them.
882 *
883 * TBD: is there any system with such CPU which supports
884 * suspend/resume? If no, we should remove the code.
885 */
886 register_syscore_ops(&mtrr_syscore_ops);
887
888 return 0;
889}
890subsys_initcall(mtrr_init_finialize);
1/* Generic MTRR (Memory Type Range Register) driver.
2
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
5
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
10
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
15
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
23
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
26 section 11.11.7
27
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
29 on 6-7 March 2002.
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
32*/
33
34#include <linux/types.h> /* FIXME: kvm_para.h needs this */
35
36#include <linux/stop_machine.h>
37#include <linux/kvm_para.h>
38#include <linux/uaccess.h>
39#include <linux/export.h>
40#include <linux/mutex.h>
41#include <linux/init.h>
42#include <linux/sort.h>
43#include <linux/cpu.h>
44#include <linux/pci.h>
45#include <linux/smp.h>
46#include <linux/syscore_ops.h>
47#include <linux/rcupdate.h>
48
49#include <asm/cacheinfo.h>
50#include <asm/cpufeature.h>
51#include <asm/e820/api.h>
52#include <asm/mtrr.h>
53#include <asm/msr.h>
54#include <asm/memtype.h>
55
56#include "mtrr.h"
57
58static_assert(X86_MEMTYPE_UC == MTRR_TYPE_UNCACHABLE);
59static_assert(X86_MEMTYPE_WC == MTRR_TYPE_WRCOMB);
60static_assert(X86_MEMTYPE_WT == MTRR_TYPE_WRTHROUGH);
61static_assert(X86_MEMTYPE_WP == MTRR_TYPE_WRPROT);
62static_assert(X86_MEMTYPE_WB == MTRR_TYPE_WRBACK);
63
64/* arch_phys_wc_add returns an MTRR register index plus this offset. */
65#define MTRR_TO_PHYS_WC_OFFSET 1000
66
67u32 num_var_ranges;
68
69unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
70DEFINE_MUTEX(mtrr_mutex);
71
72const struct mtrr_ops *mtrr_if;
73
74/* Returns non-zero if we have the write-combining memory type */
75static int have_wrcomb(void)
76{
77 struct pci_dev *dev;
78
79 dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
80 if (dev != NULL) {
81 /*
82 * ServerWorks LE chipsets < rev 6 have problems with
83 * write-combining. Don't allow it and leave room for other
84 * chipsets to be tagged
85 */
86 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
87 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE &&
88 dev->revision <= 5) {
89 pr_info("Serverworks LE rev < 6 detected. Write-combining disabled.\n");
90 pci_dev_put(dev);
91 return 0;
92 }
93 /*
94 * Intel 450NX errata # 23. Non ascending cacheline evictions to
95 * write combining memory may resulting in data corruption
96 */
97 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
98 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
99 pr_info("Intel 450NX MMC detected. Write-combining disabled.\n");
100 pci_dev_put(dev);
101 return 0;
102 }
103 pci_dev_put(dev);
104 }
105 return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
106}
107
108static void __init init_table(void)
109{
110 int i, max;
111
112 max = num_var_ranges;
113 for (i = 0; i < max; i++)
114 mtrr_usage_table[i] = 1;
115}
116
117struct set_mtrr_data {
118 unsigned long smp_base;
119 unsigned long smp_size;
120 unsigned int smp_reg;
121 mtrr_type smp_type;
122};
123
124/**
125 * mtrr_rendezvous_handler - Work done in the synchronization handler. Executed
126 * by all the CPUs.
127 * @info: pointer to mtrr configuration data
128 *
129 * Returns nothing.
130 */
131static int mtrr_rendezvous_handler(void *info)
132{
133 struct set_mtrr_data *data = info;
134
135 mtrr_if->set(data->smp_reg, data->smp_base,
136 data->smp_size, data->smp_type);
137 return 0;
138}
139
140static inline int types_compatible(mtrr_type type1, mtrr_type type2)
141{
142 return type1 == MTRR_TYPE_UNCACHABLE ||
143 type2 == MTRR_TYPE_UNCACHABLE ||
144 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
145 (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
146}
147
148/**
149 * set_mtrr - update mtrrs on all processors
150 * @reg: mtrr in question
151 * @base: mtrr base
152 * @size: mtrr size
153 * @type: mtrr type
154 *
155 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
156 *
157 * 1. Queue work to do the following on all processors:
158 * 2. Disable Interrupts
159 * 3. Wait for all procs to do so
160 * 4. Enter no-fill cache mode
161 * 5. Flush caches
162 * 6. Clear PGE bit
163 * 7. Flush all TLBs
164 * 8. Disable all range registers
165 * 9. Update the MTRRs
166 * 10. Enable all range registers
167 * 11. Flush all TLBs and caches again
168 * 12. Enter normal cache mode and reenable caching
169 * 13. Set PGE
170 * 14. Wait for buddies to catch up
171 * 15. Enable interrupts.
172 *
173 * What does that mean for us? Well, stop_machine() will ensure that
174 * the rendezvous handler is started on each CPU. And in lockstep they
175 * do the state transition of disabling interrupts, updating MTRR's
176 * (the CPU vendors may each do it differently, so we call mtrr_if->set()
177 * callback and let them take care of it.) and enabling interrupts.
178 *
179 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
180 * becomes nops.
181 */
182static void set_mtrr(unsigned int reg, unsigned long base, unsigned long size,
183 mtrr_type type)
184{
185 struct set_mtrr_data data = { .smp_reg = reg,
186 .smp_base = base,
187 .smp_size = size,
188 .smp_type = type
189 };
190
191 stop_machine_cpuslocked(mtrr_rendezvous_handler, &data, cpu_online_mask);
192
193 generic_rebuild_map();
194}
195
196/**
197 * mtrr_add_page - Add a memory type region
198 * @base: Physical base address of region in pages (in units of 4 kB!)
199 * @size: Physical size of region in pages (4 kB)
200 * @type: Type of MTRR desired
201 * @increment: If this is true do usage counting on the region
202 *
203 * Memory type region registers control the caching on newer Intel and
204 * non Intel processors. This function allows drivers to request an
205 * MTRR is added. The details and hardware specifics of each processor's
206 * implementation are hidden from the caller, but nevertheless the
207 * caller should expect to need to provide a power of two size on an
208 * equivalent power of two boundary.
209 *
210 * If the region cannot be added either because all regions are in use
211 * or the CPU cannot support it a negative value is returned. On success
212 * the register number for this entry is returned, but should be treated
213 * as a cookie only.
214 *
215 * On a multiprocessor machine the changes are made to all processors.
216 * This is required on x86 by the Intel processors.
217 *
218 * The available types are
219 *
220 * %MTRR_TYPE_UNCACHABLE - No caching
221 *
222 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
223 *
224 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
225 *
226 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
227 *
228 * BUGS: Needs a quiet flag for the cases where drivers do not mind
229 * failures and do not wish system log messages to be sent.
230 */
231int mtrr_add_page(unsigned long base, unsigned long size,
232 unsigned int type, bool increment)
233{
234 unsigned long lbase, lsize;
235 int i, replace, error;
236 mtrr_type ltype;
237
238 if (!mtrr_enabled())
239 return -ENXIO;
240
241 error = mtrr_if->validate_add_page(base, size, type);
242 if (error)
243 return error;
244
245 if (type >= MTRR_NUM_TYPES) {
246 pr_warn("type: %u invalid\n", type);
247 return -EINVAL;
248 }
249
250 /* If the type is WC, check that this processor supports it */
251 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
252 pr_warn("your processor doesn't support write-combining\n");
253 return -ENOSYS;
254 }
255
256 if (!size) {
257 pr_warn("zero sized request\n");
258 return -EINVAL;
259 }
260
261 if ((base | (base + size - 1)) >>
262 (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
263 pr_warn("base or size exceeds the MTRR width\n");
264 return -EINVAL;
265 }
266
267 error = -EINVAL;
268 replace = -1;
269
270 /* No CPU hotplug when we change MTRR entries */
271 cpus_read_lock();
272
273 /* Search for existing MTRR */
274 mutex_lock(&mtrr_mutex);
275 for (i = 0; i < num_var_ranges; ++i) {
276 mtrr_if->get(i, &lbase, &lsize, <ype);
277 if (!lsize || base > lbase + lsize - 1 ||
278 base + size - 1 < lbase)
279 continue;
280 /*
281 * At this point we know there is some kind of
282 * overlap/enclosure
283 */
284 if (base < lbase || base + size - 1 > lbase + lsize - 1) {
285 if (base <= lbase &&
286 base + size - 1 >= lbase + lsize - 1) {
287 /* New region encloses an existing region */
288 if (type == ltype) {
289 replace = replace == -1 ? i : -2;
290 continue;
291 } else if (types_compatible(type, ltype))
292 continue;
293 }
294 pr_warn("0x%lx000,0x%lx000 overlaps existing 0x%lx000,0x%lx000\n", base, size, lbase,
295 lsize);
296 goto out;
297 }
298 /* New region is enclosed by an existing region */
299 if (ltype != type) {
300 if (types_compatible(type, ltype))
301 continue;
302 pr_warn("type mismatch for %lx000,%lx000 old: %s new: %s\n",
303 base, size, mtrr_attrib_to_str(ltype),
304 mtrr_attrib_to_str(type));
305 goto out;
306 }
307 if (increment)
308 ++mtrr_usage_table[i];
309 error = i;
310 goto out;
311 }
312 /* Search for an empty MTRR */
313 i = mtrr_if->get_free_region(base, size, replace);
314 if (i >= 0) {
315 set_mtrr(i, base, size, type);
316 if (likely(replace < 0)) {
317 mtrr_usage_table[i] = 1;
318 } else {
319 mtrr_usage_table[i] = mtrr_usage_table[replace];
320 if (increment)
321 mtrr_usage_table[i]++;
322 if (unlikely(replace != i)) {
323 set_mtrr(replace, 0, 0, 0);
324 mtrr_usage_table[replace] = 0;
325 }
326 }
327 } else {
328 pr_info("no more MTRRs available\n");
329 }
330 error = i;
331 out:
332 mutex_unlock(&mtrr_mutex);
333 cpus_read_unlock();
334 return error;
335}
336
337static int mtrr_check(unsigned long base, unsigned long size)
338{
339 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
340 pr_warn("size and base must be multiples of 4 kiB\n");
341 Dprintk("size: 0x%lx base: 0x%lx\n", size, base);
342 dump_stack();
343 return -1;
344 }
345 return 0;
346}
347
348/**
349 * mtrr_add - Add a memory type region
350 * @base: Physical base address of region
351 * @size: Physical size of region
352 * @type: Type of MTRR desired
353 * @increment: If this is true do usage counting on the region
354 *
355 * Memory type region registers control the caching on newer Intel and
356 * non Intel processors. This function allows drivers to request an
357 * MTRR is added. The details and hardware specifics of each processor's
358 * implementation are hidden from the caller, but nevertheless the
359 * caller should expect to need to provide a power of two size on an
360 * equivalent power of two boundary.
361 *
362 * If the region cannot be added either because all regions are in use
363 * or the CPU cannot support it a negative value is returned. On success
364 * the register number for this entry is returned, but should be treated
365 * as a cookie only.
366 *
367 * On a multiprocessor machine the changes are made to all processors.
368 * This is required on x86 by the Intel processors.
369 *
370 * The available types are
371 *
372 * %MTRR_TYPE_UNCACHABLE - No caching
373 *
374 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
375 *
376 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
377 *
378 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
379 *
380 * BUGS: Needs a quiet flag for the cases where drivers do not mind
381 * failures and do not wish system log messages to be sent.
382 */
383int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
384 bool increment)
385{
386 if (!mtrr_enabled())
387 return -ENODEV;
388 if (mtrr_check(base, size))
389 return -EINVAL;
390 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
391 increment);
392}
393
394/**
395 * mtrr_del_page - delete a memory type region
396 * @reg: Register returned by mtrr_add
397 * @base: Physical base address
398 * @size: Size of region
399 *
400 * If register is supplied then base and size are ignored. This is
401 * how drivers should call it.
402 *
403 * Releases an MTRR region. If the usage count drops to zero the
404 * register is freed and the region returns to default state.
405 * On success the register is returned, on failure a negative error
406 * code.
407 */
408int mtrr_del_page(int reg, unsigned long base, unsigned long size)
409{
410 int i, max;
411 mtrr_type ltype;
412 unsigned long lbase, lsize;
413 int error = -EINVAL;
414
415 if (!mtrr_enabled())
416 return -ENODEV;
417
418 max = num_var_ranges;
419 /* No CPU hotplug when we change MTRR entries */
420 cpus_read_lock();
421 mutex_lock(&mtrr_mutex);
422 if (reg < 0) {
423 /* Search for existing MTRR */
424 for (i = 0; i < max; ++i) {
425 mtrr_if->get(i, &lbase, &lsize, <ype);
426 if (lbase == base && lsize == size) {
427 reg = i;
428 break;
429 }
430 }
431 if (reg < 0) {
432 Dprintk("no MTRR for %lx000,%lx000 found\n", base, size);
433 goto out;
434 }
435 }
436 if (reg >= max) {
437 pr_warn("register: %d too big\n", reg);
438 goto out;
439 }
440 mtrr_if->get(reg, &lbase, &lsize, <ype);
441 if (lsize < 1) {
442 pr_warn("MTRR %d not used\n", reg);
443 goto out;
444 }
445 if (mtrr_usage_table[reg] < 1) {
446 pr_warn("reg: %d has count=0\n", reg);
447 goto out;
448 }
449 if (--mtrr_usage_table[reg] < 1)
450 set_mtrr(reg, 0, 0, 0);
451 error = reg;
452 out:
453 mutex_unlock(&mtrr_mutex);
454 cpus_read_unlock();
455 return error;
456}
457
458/**
459 * mtrr_del - delete a memory type region
460 * @reg: Register returned by mtrr_add
461 * @base: Physical base address
462 * @size: Size of region
463 *
464 * If register is supplied then base and size are ignored. This is
465 * how drivers should call it.
466 *
467 * Releases an MTRR region. If the usage count drops to zero the
468 * register is freed and the region returns to default state.
469 * On success the register is returned, on failure a negative error
470 * code.
471 */
472int mtrr_del(int reg, unsigned long base, unsigned long size)
473{
474 if (!mtrr_enabled())
475 return -ENODEV;
476 if (mtrr_check(base, size))
477 return -EINVAL;
478 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
479}
480
481/**
482 * arch_phys_wc_add - add a WC MTRR and handle errors if PAT is unavailable
483 * @base: Physical base address
484 * @size: Size of region
485 *
486 * If PAT is available, this does nothing. If PAT is unavailable, it
487 * attempts to add a WC MTRR covering size bytes starting at base and
488 * logs an error if this fails.
489 *
490 * The called should provide a power of two size on an equivalent
491 * power of two boundary.
492 *
493 * Drivers must store the return value to pass to mtrr_del_wc_if_needed,
494 * but drivers should not try to interpret that return value.
495 */
496int arch_phys_wc_add(unsigned long base, unsigned long size)
497{
498 int ret;
499
500 if (pat_enabled() || !mtrr_enabled())
501 return 0; /* Success! (We don't need to do anything.) */
502
503 ret = mtrr_add(base, size, MTRR_TYPE_WRCOMB, true);
504 if (ret < 0) {
505 pr_warn("Failed to add WC MTRR for [%p-%p]; performance may suffer.",
506 (void *)base, (void *)(base + size - 1));
507 return ret;
508 }
509 return ret + MTRR_TO_PHYS_WC_OFFSET;
510}
511EXPORT_SYMBOL(arch_phys_wc_add);
512
513/*
514 * arch_phys_wc_del - undoes arch_phys_wc_add
515 * @handle: Return value from arch_phys_wc_add
516 *
517 * This cleans up after mtrr_add_wc_if_needed.
518 *
519 * The API guarantees that mtrr_del_wc_if_needed(error code) and
520 * mtrr_del_wc_if_needed(0) do nothing.
521 */
522void arch_phys_wc_del(int handle)
523{
524 if (handle >= 1) {
525 WARN_ON(handle < MTRR_TO_PHYS_WC_OFFSET);
526 mtrr_del(handle - MTRR_TO_PHYS_WC_OFFSET, 0, 0);
527 }
528}
529EXPORT_SYMBOL(arch_phys_wc_del);
530
531/*
532 * arch_phys_wc_index - translates arch_phys_wc_add's return value
533 * @handle: Return value from arch_phys_wc_add
534 *
535 * This will turn the return value from arch_phys_wc_add into an mtrr
536 * index suitable for debugging.
537 *
538 * Note: There is no legitimate use for this function, except possibly
539 * in printk line. Alas there is an illegitimate use in some ancient
540 * drm ioctls.
541 */
542int arch_phys_wc_index(int handle)
543{
544 if (handle < MTRR_TO_PHYS_WC_OFFSET)
545 return -1;
546 else
547 return handle - MTRR_TO_PHYS_WC_OFFSET;
548}
549EXPORT_SYMBOL_GPL(arch_phys_wc_index);
550
551int __initdata changed_by_mtrr_cleanup;
552
553/**
554 * mtrr_bp_init - initialize MTRRs on the boot CPU
555 *
556 * This needs to be called early; before any of the other CPUs are
557 * initialized (i.e. before smp_init()).
558 */
559void __init mtrr_bp_init(void)
560{
561 bool generic_mtrrs = cpu_feature_enabled(X86_FEATURE_MTRR);
562 const char *why = "(not available)";
563 unsigned long config, dummy;
564
565 phys_hi_rsvd = GENMASK(31, boot_cpu_data.x86_phys_bits - 32);
566
567 if (!generic_mtrrs && mtrr_state.enabled) {
568 /*
569 * Software overwrite of MTRR state, only for generic case.
570 * Note that X86_FEATURE_MTRR has been reset in this case.
571 */
572 init_table();
573 mtrr_build_map();
574 pr_info("MTRRs set to read-only\n");
575
576 return;
577 }
578
579 if (generic_mtrrs)
580 mtrr_if = &generic_mtrr_ops;
581 else
582 mtrr_set_if();
583
584 if (mtrr_enabled()) {
585 /* Get the number of variable MTRR ranges. */
586 if (mtrr_if == &generic_mtrr_ops)
587 rdmsr(MSR_MTRRcap, config, dummy);
588 else
589 config = mtrr_if->var_regs;
590 num_var_ranges = config & MTRR_CAP_VCNT;
591
592 init_table();
593 if (mtrr_if == &generic_mtrr_ops) {
594 /* BIOS may override */
595 if (get_mtrr_state()) {
596 memory_caching_control |= CACHE_MTRR;
597 changed_by_mtrr_cleanup = mtrr_cleanup();
598 mtrr_build_map();
599 } else {
600 mtrr_if = NULL;
601 why = "by BIOS";
602 }
603 }
604 }
605
606 if (!mtrr_enabled())
607 pr_info("MTRRs disabled %s\n", why);
608}
609
610/**
611 * mtrr_save_state - Save current fixed-range MTRR state of the first
612 * cpu in cpu_online_mask.
613 */
614void mtrr_save_state(void)
615{
616 int first_cpu;
617
618 if (!mtrr_enabled() || !mtrr_state.have_fixed)
619 return;
620
621 first_cpu = cpumask_first(cpu_online_mask);
622 smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1);
623}
624
625static int __init mtrr_init_finalize(void)
626{
627 /*
628 * Map might exist if mtrr_overwrite_state() has been called or if
629 * mtrr_enabled() returns true.
630 */
631 mtrr_copy_map();
632
633 if (!mtrr_enabled())
634 return 0;
635
636 if (memory_caching_control & CACHE_MTRR) {
637 if (!changed_by_mtrr_cleanup)
638 mtrr_state_warn();
639 return 0;
640 }
641
642 mtrr_register_syscore();
643
644 return 0;
645}
646subsys_initcall(mtrr_init_finalize);