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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2007 Alan Stern
5 * Copyright (C) 2009 IBM Corporation
6 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
7 *
8 * Authors: Alan Stern <stern@rowland.harvard.edu>
9 * K.Prasad <prasad@linux.vnet.ibm.com>
10 * Frederic Weisbecker <fweisbec@gmail.com>
11 */
12
13/*
14 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
15 * using the CPU's debug registers.
16 */
17
18#include <linux/perf_event.h>
19#include <linux/hw_breakpoint.h>
20#include <linux/irqflags.h>
21#include <linux/notifier.h>
22#include <linux/kallsyms.h>
23#include <linux/kprobes.h>
24#include <linux/percpu.h>
25#include <linux/kdebug.h>
26#include <linux/kernel.h>
27#include <linux/export.h>
28#include <linux/sched.h>
29#include <linux/smp.h>
30
31#include <asm/hw_breakpoint.h>
32#include <asm/processor.h>
33#include <asm/debugreg.h>
34#include <asm/user.h>
35
36/* Per cpu debug control register value */
37DEFINE_PER_CPU(unsigned long, cpu_dr7);
38EXPORT_PER_CPU_SYMBOL(cpu_dr7);
39
40/* Per cpu debug address registers values */
41static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
42
43/*
44 * Stores the breakpoints currently in use on each breakpoint address
45 * register for each cpus
46 */
47static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
48
49
50static inline unsigned long
51__encode_dr7(int drnum, unsigned int len, unsigned int type)
52{
53 unsigned long bp_info;
54
55 bp_info = (len | type) & 0xf;
56 bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
57 bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
58
59 return bp_info;
60}
61
62/*
63 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
64 * as stored in debug register 7.
65 */
66unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
67{
68 return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
69}
70
71/*
72 * Decode the length and type bits for a particular breakpoint as
73 * stored in debug register 7. Return the "enabled" status.
74 */
75int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
76{
77 int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
78
79 *len = (bp_info & 0xc) | 0x40;
80 *type = (bp_info & 0x3) | 0x80;
81
82 return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
83}
84
85/*
86 * Install a perf counter breakpoint.
87 *
88 * We seek a free debug address register and use it for this
89 * breakpoint. Eventually we enable it in the debug control register.
90 *
91 * Atomic: we hold the counter->ctx->lock and we only handle variables
92 * and registers local to this cpu.
93 */
94int arch_install_hw_breakpoint(struct perf_event *bp)
95{
96 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
97 unsigned long *dr7;
98 int i;
99
100 for (i = 0; i < HBP_NUM; i++) {
101 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
102
103 if (!*slot) {
104 *slot = bp;
105 break;
106 }
107 }
108
109 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
110 return -EBUSY;
111
112 set_debugreg(info->address, i);
113 __this_cpu_write(cpu_debugreg[i], info->address);
114
115 dr7 = this_cpu_ptr(&cpu_dr7);
116 *dr7 |= encode_dr7(i, info->len, info->type);
117
118 set_debugreg(*dr7, 7);
119 if (info->mask)
120 set_dr_addr_mask(info->mask, i);
121
122 return 0;
123}
124
125/*
126 * Uninstall the breakpoint contained in the given counter.
127 *
128 * First we search the debug address register it uses and then we disable
129 * it.
130 *
131 * Atomic: we hold the counter->ctx->lock and we only handle variables
132 * and registers local to this cpu.
133 */
134void arch_uninstall_hw_breakpoint(struct perf_event *bp)
135{
136 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
137 unsigned long *dr7;
138 int i;
139
140 for (i = 0; i < HBP_NUM; i++) {
141 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
142
143 if (*slot == bp) {
144 *slot = NULL;
145 break;
146 }
147 }
148
149 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
150 return;
151
152 dr7 = this_cpu_ptr(&cpu_dr7);
153 *dr7 &= ~__encode_dr7(i, info->len, info->type);
154
155 set_debugreg(*dr7, 7);
156 if (info->mask)
157 set_dr_addr_mask(0, i);
158}
159
160static int arch_bp_generic_len(int x86_len)
161{
162 switch (x86_len) {
163 case X86_BREAKPOINT_LEN_1:
164 return HW_BREAKPOINT_LEN_1;
165 case X86_BREAKPOINT_LEN_2:
166 return HW_BREAKPOINT_LEN_2;
167 case X86_BREAKPOINT_LEN_4:
168 return HW_BREAKPOINT_LEN_4;
169#ifdef CONFIG_X86_64
170 case X86_BREAKPOINT_LEN_8:
171 return HW_BREAKPOINT_LEN_8;
172#endif
173 default:
174 return -EINVAL;
175 }
176}
177
178int arch_bp_generic_fields(int x86_len, int x86_type,
179 int *gen_len, int *gen_type)
180{
181 int len;
182
183 /* Type */
184 switch (x86_type) {
185 case X86_BREAKPOINT_EXECUTE:
186 if (x86_len != X86_BREAKPOINT_LEN_X)
187 return -EINVAL;
188
189 *gen_type = HW_BREAKPOINT_X;
190 *gen_len = sizeof(long);
191 return 0;
192 case X86_BREAKPOINT_WRITE:
193 *gen_type = HW_BREAKPOINT_W;
194 break;
195 case X86_BREAKPOINT_RW:
196 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
197 break;
198 default:
199 return -EINVAL;
200 }
201
202 /* Len */
203 len = arch_bp_generic_len(x86_len);
204 if (len < 0)
205 return -EINVAL;
206 *gen_len = len;
207
208 return 0;
209}
210
211/*
212 * Check for virtual address in kernel space.
213 */
214int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
215{
216 unsigned long va;
217 int len;
218
219 va = hw->address;
220 len = arch_bp_generic_len(hw->len);
221 WARN_ON_ONCE(len < 0);
222
223 /*
224 * We don't need to worry about va + len - 1 overflowing:
225 * we already require that va is aligned to a multiple of len.
226 */
227 return (va >= TASK_SIZE_MAX) || ((va + len - 1) >= TASK_SIZE_MAX);
228}
229
230static int arch_build_bp_info(struct perf_event *bp,
231 const struct perf_event_attr *attr,
232 struct arch_hw_breakpoint *hw)
233{
234 hw->address = attr->bp_addr;
235 hw->mask = 0;
236
237 /* Type */
238 switch (attr->bp_type) {
239 case HW_BREAKPOINT_W:
240 hw->type = X86_BREAKPOINT_WRITE;
241 break;
242 case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
243 hw->type = X86_BREAKPOINT_RW;
244 break;
245 case HW_BREAKPOINT_X:
246 /*
247 * We don't allow kernel breakpoints in places that are not
248 * acceptable for kprobes. On non-kprobes kernels, we don't
249 * allow kernel breakpoints at all.
250 */
251 if (attr->bp_addr >= TASK_SIZE_MAX) {
252 if (within_kprobe_blacklist(attr->bp_addr))
253 return -EINVAL;
254 }
255
256 hw->type = X86_BREAKPOINT_EXECUTE;
257 /*
258 * x86 inst breakpoints need to have a specific undefined len.
259 * But we still need to check userspace is not trying to setup
260 * an unsupported length, to get a range breakpoint for example.
261 */
262 if (attr->bp_len == sizeof(long)) {
263 hw->len = X86_BREAKPOINT_LEN_X;
264 return 0;
265 }
266 /* fall through */
267 default:
268 return -EINVAL;
269 }
270
271 /* Len */
272 switch (attr->bp_len) {
273 case HW_BREAKPOINT_LEN_1:
274 hw->len = X86_BREAKPOINT_LEN_1;
275 break;
276 case HW_BREAKPOINT_LEN_2:
277 hw->len = X86_BREAKPOINT_LEN_2;
278 break;
279 case HW_BREAKPOINT_LEN_4:
280 hw->len = X86_BREAKPOINT_LEN_4;
281 break;
282#ifdef CONFIG_X86_64
283 case HW_BREAKPOINT_LEN_8:
284 hw->len = X86_BREAKPOINT_LEN_8;
285 break;
286#endif
287 default:
288 /* AMD range breakpoint */
289 if (!is_power_of_2(attr->bp_len))
290 return -EINVAL;
291 if (attr->bp_addr & (attr->bp_len - 1))
292 return -EINVAL;
293
294 if (!boot_cpu_has(X86_FEATURE_BPEXT))
295 return -EOPNOTSUPP;
296
297 /*
298 * It's impossible to use a range breakpoint to fake out
299 * user vs kernel detection because bp_len - 1 can't
300 * have the high bit set. If we ever allow range instruction
301 * breakpoints, then we'll have to check for kprobe-blacklisted
302 * addresses anywhere in the range.
303 */
304 hw->mask = attr->bp_len - 1;
305 hw->len = X86_BREAKPOINT_LEN_1;
306 }
307
308 return 0;
309}
310
311/*
312 * Validate the arch-specific HW Breakpoint register settings
313 */
314int hw_breakpoint_arch_parse(struct perf_event *bp,
315 const struct perf_event_attr *attr,
316 struct arch_hw_breakpoint *hw)
317{
318 unsigned int align;
319 int ret;
320
321
322 ret = arch_build_bp_info(bp, attr, hw);
323 if (ret)
324 return ret;
325
326 switch (hw->len) {
327 case X86_BREAKPOINT_LEN_1:
328 align = 0;
329 if (hw->mask)
330 align = hw->mask;
331 break;
332 case X86_BREAKPOINT_LEN_2:
333 align = 1;
334 break;
335 case X86_BREAKPOINT_LEN_4:
336 align = 3;
337 break;
338#ifdef CONFIG_X86_64
339 case X86_BREAKPOINT_LEN_8:
340 align = 7;
341 break;
342#endif
343 default:
344 WARN_ON_ONCE(1);
345 return -EINVAL;
346 }
347
348 /*
349 * Check that the low-order bits of the address are appropriate
350 * for the alignment implied by len.
351 */
352 if (hw->address & align)
353 return -EINVAL;
354
355 return 0;
356}
357
358/*
359 * Dump the debug register contents to the user.
360 * We can't dump our per cpu values because it
361 * may contain cpu wide breakpoint, something that
362 * doesn't belong to the current task.
363 *
364 * TODO: include non-ptrace user breakpoints (perf)
365 */
366void aout_dump_debugregs(struct user *dump)
367{
368 int i;
369 int dr7 = 0;
370 struct perf_event *bp;
371 struct arch_hw_breakpoint *info;
372 struct thread_struct *thread = ¤t->thread;
373
374 for (i = 0; i < HBP_NUM; i++) {
375 bp = thread->ptrace_bps[i];
376
377 if (bp && !bp->attr.disabled) {
378 dump->u_debugreg[i] = bp->attr.bp_addr;
379 info = counter_arch_bp(bp);
380 dr7 |= encode_dr7(i, info->len, info->type);
381 } else {
382 dump->u_debugreg[i] = 0;
383 }
384 }
385
386 dump->u_debugreg[4] = 0;
387 dump->u_debugreg[5] = 0;
388 dump->u_debugreg[6] = current->thread.debugreg6;
389
390 dump->u_debugreg[7] = dr7;
391}
392EXPORT_SYMBOL_GPL(aout_dump_debugregs);
393
394/*
395 * Release the user breakpoints used by ptrace
396 */
397void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
398{
399 int i;
400 struct thread_struct *t = &tsk->thread;
401
402 for (i = 0; i < HBP_NUM; i++) {
403 unregister_hw_breakpoint(t->ptrace_bps[i]);
404 t->ptrace_bps[i] = NULL;
405 }
406
407 t->debugreg6 = 0;
408 t->ptrace_dr7 = 0;
409}
410
411void hw_breakpoint_restore(void)
412{
413 set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
414 set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
415 set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
416 set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
417 set_debugreg(current->thread.debugreg6, 6);
418 set_debugreg(__this_cpu_read(cpu_dr7), 7);
419}
420EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
421
422/*
423 * Handle debug exception notifications.
424 *
425 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
426 *
427 * NOTIFY_DONE returned if one of the following conditions is true.
428 * i) When the causative address is from user-space and the exception
429 * is a valid one, i.e. not triggered as a result of lazy debug register
430 * switching
431 * ii) When there are more bits than trap<n> set in DR6 register (such
432 * as BD, BS or BT) indicating that more than one debug condition is
433 * met and requires some more action in do_debug().
434 *
435 * NOTIFY_STOP returned for all other cases
436 *
437 */
438static int hw_breakpoint_handler(struct die_args *args)
439{
440 int i, cpu, rc = NOTIFY_STOP;
441 struct perf_event *bp;
442 unsigned long dr7, dr6;
443 unsigned long *dr6_p;
444
445 /* The DR6 value is pointed by args->err */
446 dr6_p = (unsigned long *)ERR_PTR(args->err);
447 dr6 = *dr6_p;
448
449 /* If it's a single step, TRAP bits are random */
450 if (dr6 & DR_STEP)
451 return NOTIFY_DONE;
452
453 /* Do an early return if no trap bits are set in DR6 */
454 if ((dr6 & DR_TRAP_BITS) == 0)
455 return NOTIFY_DONE;
456
457 get_debugreg(dr7, 7);
458 /* Disable breakpoints during exception handling */
459 set_debugreg(0UL, 7);
460 /*
461 * Assert that local interrupts are disabled
462 * Reset the DRn bits in the virtualized register value.
463 * The ptrace trigger routine will add in whatever is needed.
464 */
465 current->thread.debugreg6 &= ~DR_TRAP_BITS;
466 cpu = get_cpu();
467
468 /* Handle all the breakpoints that were triggered */
469 for (i = 0; i < HBP_NUM; ++i) {
470 if (likely(!(dr6 & (DR_TRAP0 << i))))
471 continue;
472
473 /*
474 * The counter may be concurrently released but that can only
475 * occur from a call_rcu() path. We can then safely fetch
476 * the breakpoint, use its callback, touch its counter
477 * while we are in an rcu_read_lock() path.
478 */
479 rcu_read_lock();
480
481 bp = per_cpu(bp_per_reg[i], cpu);
482 /*
483 * Reset the 'i'th TRAP bit in dr6 to denote completion of
484 * exception handling
485 */
486 (*dr6_p) &= ~(DR_TRAP0 << i);
487 /*
488 * bp can be NULL due to lazy debug register switching
489 * or due to concurrent perf counter removing.
490 */
491 if (!bp) {
492 rcu_read_unlock();
493 break;
494 }
495
496 perf_bp_event(bp, args->regs);
497
498 /*
499 * Set up resume flag to avoid breakpoint recursion when
500 * returning back to origin.
501 */
502 if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
503 args->regs->flags |= X86_EFLAGS_RF;
504
505 rcu_read_unlock();
506 }
507 /*
508 * Further processing in do_debug() is needed for a) user-space
509 * breakpoints (to generate signals) and b) when the system has
510 * taken exception due to multiple causes
511 */
512 if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
513 (dr6 & (~DR_TRAP_BITS)))
514 rc = NOTIFY_DONE;
515
516 set_debugreg(dr7, 7);
517 put_cpu();
518
519 return rc;
520}
521
522/*
523 * Handle debug exception notifications.
524 */
525int hw_breakpoint_exceptions_notify(
526 struct notifier_block *unused, unsigned long val, void *data)
527{
528 if (val != DIE_DEBUG)
529 return NOTIFY_DONE;
530
531 return hw_breakpoint_handler(data);
532}
533
534void hw_breakpoint_pmu_read(struct perf_event *bp)
535{
536 /* TODO */
537}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2007 Alan Stern
5 * Copyright (C) 2009 IBM Corporation
6 * Copyright (C) 2009 Frederic Weisbecker <fweisbec@gmail.com>
7 *
8 * Authors: Alan Stern <stern@rowland.harvard.edu>
9 * K.Prasad <prasad@linux.vnet.ibm.com>
10 * Frederic Weisbecker <fweisbec@gmail.com>
11 */
12
13/*
14 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
15 * using the CPU's debug registers.
16 */
17
18#include <linux/perf_event.h>
19#include <linux/hw_breakpoint.h>
20#include <linux/irqflags.h>
21#include <linux/notifier.h>
22#include <linux/kallsyms.h>
23#include <linux/kprobes.h>
24#include <linux/percpu.h>
25#include <linux/kdebug.h>
26#include <linux/kernel.h>
27#include <linux/export.h>
28#include <linux/sched.h>
29#include <linux/smp.h>
30
31#include <asm/hw_breakpoint.h>
32#include <asm/processor.h>
33#include <asm/debugreg.h>
34#include <asm/user.h>
35#include <asm/desc.h>
36#include <asm/tlbflush.h>
37
38/* Per cpu debug control register value */
39DEFINE_PER_CPU(unsigned long, cpu_dr7);
40EXPORT_PER_CPU_SYMBOL(cpu_dr7);
41
42/* Per cpu debug address registers values */
43static DEFINE_PER_CPU(unsigned long, cpu_debugreg[HBP_NUM]);
44
45/*
46 * Stores the breakpoints currently in use on each breakpoint address
47 * register for each cpus
48 */
49static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
50
51
52static inline unsigned long
53__encode_dr7(int drnum, unsigned int len, unsigned int type)
54{
55 unsigned long bp_info;
56
57 bp_info = (len | type) & 0xf;
58 bp_info <<= (DR_CONTROL_SHIFT + drnum * DR_CONTROL_SIZE);
59 bp_info |= (DR_GLOBAL_ENABLE << (drnum * DR_ENABLE_SIZE));
60
61 return bp_info;
62}
63
64/*
65 * Encode the length, type, Exact, and Enable bits for a particular breakpoint
66 * as stored in debug register 7.
67 */
68unsigned long encode_dr7(int drnum, unsigned int len, unsigned int type)
69{
70 return __encode_dr7(drnum, len, type) | DR_GLOBAL_SLOWDOWN;
71}
72
73/*
74 * Decode the length and type bits for a particular breakpoint as
75 * stored in debug register 7. Return the "enabled" status.
76 */
77int decode_dr7(unsigned long dr7, int bpnum, unsigned *len, unsigned *type)
78{
79 int bp_info = dr7 >> (DR_CONTROL_SHIFT + bpnum * DR_CONTROL_SIZE);
80
81 *len = (bp_info & 0xc) | 0x40;
82 *type = (bp_info & 0x3) | 0x80;
83
84 return (dr7 >> (bpnum * DR_ENABLE_SIZE)) & 0x3;
85}
86
87/*
88 * Install a perf counter breakpoint.
89 *
90 * We seek a free debug address register and use it for this
91 * breakpoint. Eventually we enable it in the debug control register.
92 *
93 * Atomic: we hold the counter->ctx->lock and we only handle variables
94 * and registers local to this cpu.
95 */
96int arch_install_hw_breakpoint(struct perf_event *bp)
97{
98 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
99 unsigned long *dr7;
100 int i;
101
102 lockdep_assert_irqs_disabled();
103
104 for (i = 0; i < HBP_NUM; i++) {
105 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
106
107 if (!*slot) {
108 *slot = bp;
109 break;
110 }
111 }
112
113 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
114 return -EBUSY;
115
116 set_debugreg(info->address, i);
117 __this_cpu_write(cpu_debugreg[i], info->address);
118
119 dr7 = this_cpu_ptr(&cpu_dr7);
120 *dr7 |= encode_dr7(i, info->len, info->type);
121
122 /*
123 * Ensure we first write cpu_dr7 before we set the DR7 register.
124 * This ensures an NMI never see cpu_dr7 0 when DR7 is not.
125 */
126 barrier();
127
128 set_debugreg(*dr7, 7);
129 if (info->mask)
130 set_dr_addr_mask(info->mask, i);
131
132 return 0;
133}
134
135/*
136 * Uninstall the breakpoint contained in the given counter.
137 *
138 * First we search the debug address register it uses and then we disable
139 * it.
140 *
141 * Atomic: we hold the counter->ctx->lock and we only handle variables
142 * and registers local to this cpu.
143 */
144void arch_uninstall_hw_breakpoint(struct perf_event *bp)
145{
146 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
147 unsigned long dr7;
148 int i;
149
150 lockdep_assert_irqs_disabled();
151
152 for (i = 0; i < HBP_NUM; i++) {
153 struct perf_event **slot = this_cpu_ptr(&bp_per_reg[i]);
154
155 if (*slot == bp) {
156 *slot = NULL;
157 break;
158 }
159 }
160
161 if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot"))
162 return;
163
164 dr7 = this_cpu_read(cpu_dr7);
165 dr7 &= ~__encode_dr7(i, info->len, info->type);
166
167 set_debugreg(dr7, 7);
168 if (info->mask)
169 set_dr_addr_mask(0, i);
170
171 /*
172 * Ensure the write to cpu_dr7 is after we've set the DR7 register.
173 * This ensures an NMI never see cpu_dr7 0 when DR7 is not.
174 */
175 barrier();
176
177 this_cpu_write(cpu_dr7, dr7);
178}
179
180static int arch_bp_generic_len(int x86_len)
181{
182 switch (x86_len) {
183 case X86_BREAKPOINT_LEN_1:
184 return HW_BREAKPOINT_LEN_1;
185 case X86_BREAKPOINT_LEN_2:
186 return HW_BREAKPOINT_LEN_2;
187 case X86_BREAKPOINT_LEN_4:
188 return HW_BREAKPOINT_LEN_4;
189#ifdef CONFIG_X86_64
190 case X86_BREAKPOINT_LEN_8:
191 return HW_BREAKPOINT_LEN_8;
192#endif
193 default:
194 return -EINVAL;
195 }
196}
197
198int arch_bp_generic_fields(int x86_len, int x86_type,
199 int *gen_len, int *gen_type)
200{
201 int len;
202
203 /* Type */
204 switch (x86_type) {
205 case X86_BREAKPOINT_EXECUTE:
206 if (x86_len != X86_BREAKPOINT_LEN_X)
207 return -EINVAL;
208
209 *gen_type = HW_BREAKPOINT_X;
210 *gen_len = sizeof(long);
211 return 0;
212 case X86_BREAKPOINT_WRITE:
213 *gen_type = HW_BREAKPOINT_W;
214 break;
215 case X86_BREAKPOINT_RW:
216 *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 /* Len */
223 len = arch_bp_generic_len(x86_len);
224 if (len < 0)
225 return -EINVAL;
226 *gen_len = len;
227
228 return 0;
229}
230
231/*
232 * Check for virtual address in kernel space.
233 */
234int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
235{
236 unsigned long va;
237 int len;
238
239 va = hw->address;
240 len = arch_bp_generic_len(hw->len);
241 WARN_ON_ONCE(len < 0);
242
243 /*
244 * We don't need to worry about va + len - 1 overflowing:
245 * we already require that va is aligned to a multiple of len.
246 */
247 return (va >= TASK_SIZE_MAX) || ((va + len - 1) >= TASK_SIZE_MAX);
248}
249
250/*
251 * Checks whether the range [addr, end], overlaps the area [base, base + size).
252 */
253static inline bool within_area(unsigned long addr, unsigned long end,
254 unsigned long base, unsigned long size)
255{
256 return end >= base && addr < (base + size);
257}
258
259/*
260 * Checks whether the range from addr to end, inclusive, overlaps the fixed
261 * mapped CPU entry area range or other ranges used for CPU entry.
262 */
263static inline bool within_cpu_entry(unsigned long addr, unsigned long end)
264{
265 int cpu;
266
267 /* CPU entry erea is always used for CPU entry */
268 if (within_area(addr, end, CPU_ENTRY_AREA_BASE,
269 CPU_ENTRY_AREA_TOTAL_SIZE))
270 return true;
271
272 for_each_possible_cpu(cpu) {
273 /* The original rw GDT is being used after load_direct_gdt() */
274 if (within_area(addr, end, (unsigned long)get_cpu_gdt_rw(cpu),
275 GDT_SIZE))
276 return true;
277
278 /*
279 * cpu_tss_rw is not directly referenced by hardware, but
280 * cpu_tss_rw is also used in CPU entry code,
281 */
282 if (within_area(addr, end,
283 (unsigned long)&per_cpu(cpu_tss_rw, cpu),
284 sizeof(struct tss_struct)))
285 return true;
286
287 /*
288 * cpu_tlbstate.user_pcid_flush_mask is used for CPU entry.
289 * If a data breakpoint on it, it will cause an unwanted #DB.
290 * Protect the full cpu_tlbstate structure to be sure.
291 */
292 if (within_area(addr, end,
293 (unsigned long)&per_cpu(cpu_tlbstate, cpu),
294 sizeof(struct tlb_state)))
295 return true;
296 }
297
298 return false;
299}
300
301static int arch_build_bp_info(struct perf_event *bp,
302 const struct perf_event_attr *attr,
303 struct arch_hw_breakpoint *hw)
304{
305 unsigned long bp_end;
306
307 bp_end = attr->bp_addr + attr->bp_len - 1;
308 if (bp_end < attr->bp_addr)
309 return -EINVAL;
310
311 /*
312 * Prevent any breakpoint of any type that overlaps the CPU
313 * entry area and data. This protects the IST stacks and also
314 * reduces the chance that we ever find out what happens if
315 * there's a data breakpoint on the GDT, IDT, or TSS.
316 */
317 if (within_cpu_entry(attr->bp_addr, bp_end))
318 return -EINVAL;
319
320 hw->address = attr->bp_addr;
321 hw->mask = 0;
322
323 /* Type */
324 switch (attr->bp_type) {
325 case HW_BREAKPOINT_W:
326 hw->type = X86_BREAKPOINT_WRITE;
327 break;
328 case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
329 hw->type = X86_BREAKPOINT_RW;
330 break;
331 case HW_BREAKPOINT_X:
332 /*
333 * We don't allow kernel breakpoints in places that are not
334 * acceptable for kprobes. On non-kprobes kernels, we don't
335 * allow kernel breakpoints at all.
336 */
337 if (attr->bp_addr >= TASK_SIZE_MAX) {
338 if (within_kprobe_blacklist(attr->bp_addr))
339 return -EINVAL;
340 }
341
342 hw->type = X86_BREAKPOINT_EXECUTE;
343 /*
344 * x86 inst breakpoints need to have a specific undefined len.
345 * But we still need to check userspace is not trying to setup
346 * an unsupported length, to get a range breakpoint for example.
347 */
348 if (attr->bp_len == sizeof(long)) {
349 hw->len = X86_BREAKPOINT_LEN_X;
350 return 0;
351 }
352 fallthrough;
353 default:
354 return -EINVAL;
355 }
356
357 /* Len */
358 switch (attr->bp_len) {
359 case HW_BREAKPOINT_LEN_1:
360 hw->len = X86_BREAKPOINT_LEN_1;
361 break;
362 case HW_BREAKPOINT_LEN_2:
363 hw->len = X86_BREAKPOINT_LEN_2;
364 break;
365 case HW_BREAKPOINT_LEN_4:
366 hw->len = X86_BREAKPOINT_LEN_4;
367 break;
368#ifdef CONFIG_X86_64
369 case HW_BREAKPOINT_LEN_8:
370 hw->len = X86_BREAKPOINT_LEN_8;
371 break;
372#endif
373 default:
374 /* AMD range breakpoint */
375 if (!is_power_of_2(attr->bp_len))
376 return -EINVAL;
377 if (attr->bp_addr & (attr->bp_len - 1))
378 return -EINVAL;
379
380 if (!boot_cpu_has(X86_FEATURE_BPEXT))
381 return -EOPNOTSUPP;
382
383 /*
384 * It's impossible to use a range breakpoint to fake out
385 * user vs kernel detection because bp_len - 1 can't
386 * have the high bit set. If we ever allow range instruction
387 * breakpoints, then we'll have to check for kprobe-blacklisted
388 * addresses anywhere in the range.
389 */
390 hw->mask = attr->bp_len - 1;
391 hw->len = X86_BREAKPOINT_LEN_1;
392 }
393
394 return 0;
395}
396
397/*
398 * Validate the arch-specific HW Breakpoint register settings
399 */
400int hw_breakpoint_arch_parse(struct perf_event *bp,
401 const struct perf_event_attr *attr,
402 struct arch_hw_breakpoint *hw)
403{
404 unsigned int align;
405 int ret;
406
407
408 ret = arch_build_bp_info(bp, attr, hw);
409 if (ret)
410 return ret;
411
412 switch (hw->len) {
413 case X86_BREAKPOINT_LEN_1:
414 align = 0;
415 if (hw->mask)
416 align = hw->mask;
417 break;
418 case X86_BREAKPOINT_LEN_2:
419 align = 1;
420 break;
421 case X86_BREAKPOINT_LEN_4:
422 align = 3;
423 break;
424#ifdef CONFIG_X86_64
425 case X86_BREAKPOINT_LEN_8:
426 align = 7;
427 break;
428#endif
429 default:
430 WARN_ON_ONCE(1);
431 return -EINVAL;
432 }
433
434 /*
435 * Check that the low-order bits of the address are appropriate
436 * for the alignment implied by len.
437 */
438 if (hw->address & align)
439 return -EINVAL;
440
441 return 0;
442}
443
444/*
445 * Dump the debug register contents to the user.
446 * We can't dump our per cpu values because it
447 * may contain cpu wide breakpoint, something that
448 * doesn't belong to the current task.
449 *
450 * TODO: include non-ptrace user breakpoints (perf)
451 */
452void aout_dump_debugregs(struct user *dump)
453{
454 int i;
455 int dr7 = 0;
456 struct perf_event *bp;
457 struct arch_hw_breakpoint *info;
458 struct thread_struct *thread = ¤t->thread;
459
460 for (i = 0; i < HBP_NUM; i++) {
461 bp = thread->ptrace_bps[i];
462
463 if (bp && !bp->attr.disabled) {
464 dump->u_debugreg[i] = bp->attr.bp_addr;
465 info = counter_arch_bp(bp);
466 dr7 |= encode_dr7(i, info->len, info->type);
467 } else {
468 dump->u_debugreg[i] = 0;
469 }
470 }
471
472 dump->u_debugreg[4] = 0;
473 dump->u_debugreg[5] = 0;
474 dump->u_debugreg[6] = current->thread.debugreg6;
475
476 dump->u_debugreg[7] = dr7;
477}
478EXPORT_SYMBOL_GPL(aout_dump_debugregs);
479
480/*
481 * Release the user breakpoints used by ptrace
482 */
483void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
484{
485 int i;
486 struct thread_struct *t = &tsk->thread;
487
488 for (i = 0; i < HBP_NUM; i++) {
489 unregister_hw_breakpoint(t->ptrace_bps[i]);
490 t->ptrace_bps[i] = NULL;
491 }
492
493 t->debugreg6 = 0;
494 t->ptrace_dr7 = 0;
495}
496
497void hw_breakpoint_restore(void)
498{
499 set_debugreg(__this_cpu_read(cpu_debugreg[0]), 0);
500 set_debugreg(__this_cpu_read(cpu_debugreg[1]), 1);
501 set_debugreg(__this_cpu_read(cpu_debugreg[2]), 2);
502 set_debugreg(__this_cpu_read(cpu_debugreg[3]), 3);
503 set_debugreg(current->thread.debugreg6, 6);
504 set_debugreg(__this_cpu_read(cpu_dr7), 7);
505}
506EXPORT_SYMBOL_GPL(hw_breakpoint_restore);
507
508/*
509 * Handle debug exception notifications.
510 *
511 * Return value is either NOTIFY_STOP or NOTIFY_DONE as explained below.
512 *
513 * NOTIFY_DONE returned if one of the following conditions is true.
514 * i) When the causative address is from user-space and the exception
515 * is a valid one, i.e. not triggered as a result of lazy debug register
516 * switching
517 * ii) When there are more bits than trap<n> set in DR6 register (such
518 * as BD, BS or BT) indicating that more than one debug condition is
519 * met and requires some more action in do_debug().
520 *
521 * NOTIFY_STOP returned for all other cases
522 *
523 */
524static int hw_breakpoint_handler(struct die_args *args)
525{
526 int i, cpu, rc = NOTIFY_STOP;
527 struct perf_event *bp;
528 unsigned long dr6;
529 unsigned long *dr6_p;
530
531 /* The DR6 value is pointed by args->err */
532 dr6_p = (unsigned long *)ERR_PTR(args->err);
533 dr6 = *dr6_p;
534
535 /* If it's a single step, TRAP bits are random */
536 if (dr6 & DR_STEP)
537 return NOTIFY_DONE;
538
539 /* Do an early return if no trap bits are set in DR6 */
540 if ((dr6 & DR_TRAP_BITS) == 0)
541 return NOTIFY_DONE;
542
543 /*
544 * Assert that local interrupts are disabled
545 * Reset the DRn bits in the virtualized register value.
546 * The ptrace trigger routine will add in whatever is needed.
547 */
548 current->thread.debugreg6 &= ~DR_TRAP_BITS;
549 cpu = get_cpu();
550
551 /* Handle all the breakpoints that were triggered */
552 for (i = 0; i < HBP_NUM; ++i) {
553 if (likely(!(dr6 & (DR_TRAP0 << i))))
554 continue;
555
556 /*
557 * The counter may be concurrently released but that can only
558 * occur from a call_rcu() path. We can then safely fetch
559 * the breakpoint, use its callback, touch its counter
560 * while we are in an rcu_read_lock() path.
561 */
562 rcu_read_lock();
563
564 bp = per_cpu(bp_per_reg[i], cpu);
565 /*
566 * Reset the 'i'th TRAP bit in dr6 to denote completion of
567 * exception handling
568 */
569 (*dr6_p) &= ~(DR_TRAP0 << i);
570 /*
571 * bp can be NULL due to lazy debug register switching
572 * or due to concurrent perf counter removing.
573 */
574 if (!bp) {
575 rcu_read_unlock();
576 break;
577 }
578
579 perf_bp_event(bp, args->regs);
580
581 /*
582 * Set up resume flag to avoid breakpoint recursion when
583 * returning back to origin.
584 */
585 if (bp->hw.info.type == X86_BREAKPOINT_EXECUTE)
586 args->regs->flags |= X86_EFLAGS_RF;
587
588 rcu_read_unlock();
589 }
590 /*
591 * Further processing in do_debug() is needed for a) user-space
592 * breakpoints (to generate signals) and b) when the system has
593 * taken exception due to multiple causes
594 */
595 if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
596 (dr6 & (~DR_TRAP_BITS)))
597 rc = NOTIFY_DONE;
598
599 put_cpu();
600
601 return rc;
602}
603
604/*
605 * Handle debug exception notifications.
606 */
607int hw_breakpoint_exceptions_notify(
608 struct notifier_block *unused, unsigned long val, void *data)
609{
610 if (val != DIE_DEBUG)
611 return NOTIFY_DONE;
612
613 return hw_breakpoint_handler(data);
614}
615
616void hw_breakpoint_pmu_read(struct perf_event *bp)
617{
618 /* TODO */
619}