1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7 * Copyright (C) 2000 Silicon Graphics, Inc.
   8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11 * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12 */
  13#ifndef _ASM_MIPSREGS_H
  14#define _ASM_MIPSREGS_H
  15
  16#include <linux/linkage.h>
  17#include <linux/types.h>
  18#include <asm/hazards.h>
  19#include <asm/isa-rev.h>
  20#include <asm/war.h>
  21
  22/*
  23 * The following macros are especially useful for __asm__
  24 * inline assembler.
  25 */
  26#ifndef __STR
  27#define __STR(x) #x
  28#endif
  29#ifndef STR
  30#define STR(x) __STR(x)
  31#endif
  32
  33/*
  34 *  Configure language
  35 */
  36#ifdef __ASSEMBLY__
  37#define _ULCAST_
  38#define _U64CAST_
  39#else
  40#define _ULCAST_ (unsigned long)
  41#define _U64CAST_ (u64)
  42#endif
  43
  44/*
  45 * Coprocessor 0 register names
  46 */
  47#define CP0_INDEX $0
  48#define CP0_RANDOM $1
  49#define CP0_ENTRYLO0 $2
  50#define CP0_ENTRYLO1 $3
  51#define CP0_CONF $3
  52#define CP0_GLOBALNUMBER $3, 1
  53#define CP0_CONTEXT $4
  54#define CP0_PAGEMASK $5
  55#define CP0_PAGEGRAIN $5, 1
  56#define CP0_SEGCTL0 $5, 2
  57#define CP0_SEGCTL1 $5, 3
  58#define CP0_SEGCTL2 $5, 4
  59#define CP0_WIRED $6
  60#define CP0_INFO $7
  61#define CP0_HWRENA $7
  62#define CP0_BADVADDR $8
  63#define CP0_BADINSTR $8, 1
  64#define CP0_COUNT $9
  65#define CP0_ENTRYHI $10
  66#define CP0_GUESTCTL1 $10, 4
  67#define CP0_GUESTCTL2 $10, 5
  68#define CP0_GUESTCTL3 $10, 6
  69#define CP0_COMPARE $11
  70#define CP0_GUESTCTL0EXT $11, 4
  71#define CP0_STATUS $12
  72#define CP0_GUESTCTL0 $12, 6
  73#define CP0_GTOFFSET $12, 7
  74#define CP0_CAUSE $13
  75#define CP0_EPC $14
  76#define CP0_PRID $15
  77#define CP0_EBASE $15, 1
  78#define CP0_CMGCRBASE $15, 3
  79#define CP0_CONFIG $16
  80#define CP0_CONFIG3 $16, 3
  81#define CP0_CONFIG5 $16, 5
  82#define CP0_CONFIG6 $16, 6
  83#define CP0_LLADDR $17
  84#define CP0_WATCHLO $18
  85#define CP0_WATCHHI $19
  86#define CP0_XCONTEXT $20
  87#define CP0_FRAMEMASK $21
  88#define CP0_DIAGNOSTIC $22
 
  89#define CP0_DEBUG $23
  90#define CP0_DEPC $24
  91#define CP0_PERFORMANCE $25
  92#define CP0_ECC $26
  93#define CP0_CACHEERR $27
  94#define CP0_TAGLO $28
  95#define CP0_TAGHI $29
  96#define CP0_ERROREPC $30
  97#define CP0_DESAVE $31
  98
  99/*
 100 * R4640/R4650 cp0 register names.  These registers are listed
 101 * here only for completeness; without MMU these CPUs are not useable
 102 * by Linux.  A future ELKS port might take make Linux run on them
 103 * though ...
 104 */
 105#define CP0_IBASE $0
 106#define CP0_IBOUND $1
 107#define CP0_DBASE $2
 108#define CP0_DBOUND $3
 109#define CP0_CALG $17
 110#define CP0_IWATCH $18
 111#define CP0_DWATCH $19
 112
 113/*
 114 * Coprocessor 0 Set 1 register names
 115 */
 116#define CP0_S1_DERRADDR0  $26
 117#define CP0_S1_DERRADDR1  $27
 118#define CP0_S1_INTCONTROL $20
 119
 120/*
 121 * Coprocessor 0 Set 2 register names
 122 */
 123#define CP0_S2_SRSCTL	  $12	/* MIPSR2 */
 124
 125/*
 126 * Coprocessor 0 Set 3 register names
 127 */
 128#define CP0_S3_SRSMAP	  $12	/* MIPSR2 */
 129
 130/*
 131 *  TX39 Series
 132 */
 133#define CP0_TX39_CACHE	$7
 134
 135
 136/* Generic EntryLo bit definitions */
 137#define ENTRYLO_G		(_ULCAST_(1) << 0)
 138#define ENTRYLO_V		(_ULCAST_(1) << 1)
 139#define ENTRYLO_D		(_ULCAST_(1) << 2)
 140#define ENTRYLO_C_SHIFT		3
 141#define ENTRYLO_C		(_ULCAST_(7) << ENTRYLO_C_SHIFT)
 142
 143/* R3000 EntryLo bit definitions */
 144#define R3K_ENTRYLO_G		(_ULCAST_(1) << 8)
 145#define R3K_ENTRYLO_V		(_ULCAST_(1) << 9)
 146#define R3K_ENTRYLO_D		(_ULCAST_(1) << 10)
 147#define R3K_ENTRYLO_N		(_ULCAST_(1) << 11)
 148
 149/* MIPS32/64 EntryLo bit definitions */
 150#define MIPS_ENTRYLO_PFN_SHIFT	6
 151#define MIPS_ENTRYLO_XI		(_ULCAST_(1) << (BITS_PER_LONG - 2))
 152#define MIPS_ENTRYLO_RI		(_ULCAST_(1) << (BITS_PER_LONG - 1))
 153
 154/*
 155 * MIPSr6+ GlobalNumber register definitions
 156 */
 157#define MIPS_GLOBALNUMBER_VP_SHF	0
 158#define MIPS_GLOBALNUMBER_VP		(_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 159#define MIPS_GLOBALNUMBER_CORE_SHF	8
 160#define MIPS_GLOBALNUMBER_CORE		(_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 161#define MIPS_GLOBALNUMBER_CLUSTER_SHF	16
 162#define MIPS_GLOBALNUMBER_CLUSTER	(_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 163
 164/*
 165 * Values for PageMask register
 166 */
 167#ifdef CONFIG_CPU_VR41XX
 168
 169/* Why doesn't stupidity hurt ... */
 170
 171#define PM_1K		0x00000000
 172#define PM_4K		0x00001800
 173#define PM_16K		0x00007800
 174#define PM_64K		0x0001f800
 175#define PM_256K		0x0007f800
 176
 177#else
 178
 179#define PM_4K		0x00000000
 180#define PM_8K		0x00002000
 181#define PM_16K		0x00006000
 182#define PM_32K		0x0000e000
 183#define PM_64K		0x0001e000
 184#define PM_128K		0x0003e000
 185#define PM_256K		0x0007e000
 186#define PM_512K		0x000fe000
 187#define PM_1M		0x001fe000
 188#define PM_2M		0x003fe000
 189#define PM_4M		0x007fe000
 190#define PM_8M		0x00ffe000
 191#define PM_16M		0x01ffe000
 192#define PM_32M		0x03ffe000
 193#define PM_64M		0x07ffe000
 194#define PM_256M		0x1fffe000
 195#define PM_1G		0x7fffe000
 196
 197#endif
 198
 199/*
 200 * Default page size for a given kernel configuration
 201 */
 202#ifdef CONFIG_PAGE_SIZE_4KB
 203#define PM_DEFAULT_MASK PM_4K
 204#elif defined(CONFIG_PAGE_SIZE_8KB)
 205#define PM_DEFAULT_MASK PM_8K
 206#elif defined(CONFIG_PAGE_SIZE_16KB)
 207#define PM_DEFAULT_MASK PM_16K
 208#elif defined(CONFIG_PAGE_SIZE_32KB)
 209#define PM_DEFAULT_MASK PM_32K
 210#elif defined(CONFIG_PAGE_SIZE_64KB)
 211#define PM_DEFAULT_MASK PM_64K
 212#else
 213#error Bad page size configuration!
 214#endif
 215
 216/*
 217 * Default huge tlb size for a given kernel configuration
 218 */
 219#ifdef CONFIG_PAGE_SIZE_4KB
 220#define PM_HUGE_MASK	PM_1M
 221#elif defined(CONFIG_PAGE_SIZE_8KB)
 222#define PM_HUGE_MASK	PM_4M
 223#elif defined(CONFIG_PAGE_SIZE_16KB)
 224#define PM_HUGE_MASK	PM_16M
 225#elif defined(CONFIG_PAGE_SIZE_32KB)
 226#define PM_HUGE_MASK	PM_64M
 227#elif defined(CONFIG_PAGE_SIZE_64KB)
 228#define PM_HUGE_MASK	PM_256M
 229#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 230#error Bad page size configuration for hugetlbfs!
 231#endif
 232
 233/*
 234 * Wired register bits
 235 */
 236#define MIPSR6_WIRED_LIMIT_SHIFT 16
 237#define MIPSR6_WIRED_LIMIT	(_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
 238#define MIPSR6_WIRED_WIRED_SHIFT 0
 239#define MIPSR6_WIRED_WIRED	(_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
 240
 241/*
 242 * Values used for computation of new tlb entries
 243 */
 244#define PL_4K		12
 245#define PL_16K		14
 246#define PL_64K		16
 247#define PL_256K		18
 248#define PL_1M		20
 249#define PL_4M		22
 250#define PL_16M		24
 251#define PL_64M		26
 252#define PL_256M		28
 253
 254/*
 255 * PageGrain bits
 256 */
 257#define PG_RIE		(_ULCAST_(1) <<	 31)
 258#define PG_XIE		(_ULCAST_(1) <<	 30)
 259#define PG_ELPA		(_ULCAST_(1) <<	 29)
 260#define PG_ESP		(_ULCAST_(1) <<	 28)
 261#define PG_IEC		(_ULCAST_(1) <<  27)
 262
 263/* MIPS32/64 EntryHI bit definitions */
 264#define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)
 265#define MIPS_ENTRYHI_ASIDX	(_ULCAST_(0x3) << 8)
 266#define MIPS_ENTRYHI_ASID	(_ULCAST_(0xff) << 0)
 267
 268/*
 269 * R4x00 interrupt enable / cause bits
 270 */
 271#define IE_SW0		(_ULCAST_(1) <<	 8)
 272#define IE_SW1		(_ULCAST_(1) <<	 9)
 273#define IE_IRQ0		(_ULCAST_(1) << 10)
 274#define IE_IRQ1		(_ULCAST_(1) << 11)
 275#define IE_IRQ2		(_ULCAST_(1) << 12)
 276#define IE_IRQ3		(_ULCAST_(1) << 13)
 277#define IE_IRQ4		(_ULCAST_(1) << 14)
 278#define IE_IRQ5		(_ULCAST_(1) << 15)
 279
 280/*
 281 * R4x00 interrupt cause bits
 282 */
 283#define C_SW0		(_ULCAST_(1) <<	 8)
 284#define C_SW1		(_ULCAST_(1) <<	 9)
 285#define C_IRQ0		(_ULCAST_(1) << 10)
 286#define C_IRQ1		(_ULCAST_(1) << 11)
 287#define C_IRQ2		(_ULCAST_(1) << 12)
 288#define C_IRQ3		(_ULCAST_(1) << 13)
 289#define C_IRQ4		(_ULCAST_(1) << 14)
 290#define C_IRQ5		(_ULCAST_(1) << 15)
 291
 292/*
 293 * Bitfields in the R4xx0 cp0 status register
 294 */
 295#define ST0_IE			0x00000001
 296#define ST0_EXL			0x00000002
 297#define ST0_ERL			0x00000004
 298#define ST0_KSU			0x00000018
 299#  define KSU_USER		0x00000010
 300#  define KSU_SUPERVISOR	0x00000008
 301#  define KSU_KERNEL		0x00000000
 302#define ST0_UX			0x00000020
 303#define ST0_SX			0x00000040
 304#define ST0_KX			0x00000080
 305#define ST0_DE			0x00010000
 306#define ST0_CE			0x00020000
 307
 308/*
 309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 310 * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 311 * processors.
 312 */
 313#define ST0_CO			0x08000000
 314
 315/*
 316 * Bitfields in the R[23]000 cp0 status register.
 317 */
 318#define ST0_IEC			0x00000001
 319#define ST0_KUC			0x00000002
 320#define ST0_IEP			0x00000004
 321#define ST0_KUP			0x00000008
 322#define ST0_IEO			0x00000010
 323#define ST0_KUO			0x00000020
 324/* bits 6 & 7 are reserved on R[23]000 */
 325#define ST0_ISC			0x00010000
 326#define ST0_SWC			0x00020000
 327#define ST0_CM			0x00080000
 328
 329/*
 330 * Bits specific to the R4640/R4650
 331 */
 332#define ST0_UM			(_ULCAST_(1) <<	 4)
 333#define ST0_IL			(_ULCAST_(1) << 23)
 334#define ST0_DL			(_ULCAST_(1) << 24)
 335
 336/*
 337 * Enable the MIPS MDMX and DSP ASEs
 338 */
 339#define ST0_MX			0x01000000
 340
 341/*
 342 * Status register bits available in all MIPS CPUs.
 343 */
 344#define ST0_IM			0x0000ff00
 345#define	 STATUSB_IP0		8
 346#define	 STATUSF_IP0		(_ULCAST_(1) <<	 8)
 347#define	 STATUSB_IP1		9
 348#define	 STATUSF_IP1		(_ULCAST_(1) <<	 9)
 349#define	 STATUSB_IP2		10
 350#define	 STATUSF_IP2		(_ULCAST_(1) << 10)
 351#define	 STATUSB_IP3		11
 352#define	 STATUSF_IP3		(_ULCAST_(1) << 11)
 353#define	 STATUSB_IP4		12
 354#define	 STATUSF_IP4		(_ULCAST_(1) << 12)
 355#define	 STATUSB_IP5		13
 356#define	 STATUSF_IP5		(_ULCAST_(1) << 13)
 357#define	 STATUSB_IP6		14
 358#define	 STATUSF_IP6		(_ULCAST_(1) << 14)
 359#define	 STATUSB_IP7		15
 360#define	 STATUSF_IP7		(_ULCAST_(1) << 15)
 361#define	 STATUSB_IP8		0
 362#define	 STATUSF_IP8		(_ULCAST_(1) <<	 0)
 363#define	 STATUSB_IP9		1
 364#define	 STATUSF_IP9		(_ULCAST_(1) <<	 1)
 365#define	 STATUSB_IP10		2
 366#define	 STATUSF_IP10		(_ULCAST_(1) <<	 2)
 367#define	 STATUSB_IP11		3
 368#define	 STATUSF_IP11		(_ULCAST_(1) <<	 3)
 369#define	 STATUSB_IP12		4
 370#define	 STATUSF_IP12		(_ULCAST_(1) <<	 4)
 371#define	 STATUSB_IP13		5
 372#define	 STATUSF_IP13		(_ULCAST_(1) <<	 5)
 373#define	 STATUSB_IP14		6
 374#define	 STATUSF_IP14		(_ULCAST_(1) <<	 6)
 375#define	 STATUSB_IP15		7
 376#define	 STATUSF_IP15		(_ULCAST_(1) <<	 7)
 377#define ST0_CH			0x00040000
 378#define ST0_NMI			0x00080000
 379#define ST0_SR			0x00100000
 380#define ST0_TS			0x00200000
 381#define ST0_BEV			0x00400000
 382#define ST0_RE			0x02000000
 383#define ST0_FR			0x04000000
 384#define ST0_CU			0xf0000000
 385#define ST0_CU0			0x10000000
 386#define ST0_CU1			0x20000000
 387#define ST0_CU2			0x40000000
 388#define ST0_CU3			0x80000000
 389#define ST0_XX			0x80000000	/* MIPS IV naming */
 390
 391/*
 392 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 393 */
 394#define INTCTLB_IPFDC		23
 395#define INTCTLF_IPFDC		(_ULCAST_(7) << INTCTLB_IPFDC)
 396#define INTCTLB_IPPCI		26
 397#define INTCTLF_IPPCI		(_ULCAST_(7) << INTCTLB_IPPCI)
 398#define INTCTLB_IPTI		29
 399#define INTCTLF_IPTI		(_ULCAST_(7) << INTCTLB_IPTI)
 400
 401/*
 402 * Bitfields and bit numbers in the coprocessor 0 cause register.
 403 *
 404 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 405 */
 406#define CAUSEB_EXCCODE		2
 407#define CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
 408#define CAUSEB_IP		8
 409#define CAUSEF_IP		(_ULCAST_(255) <<  8)
 410#define	 CAUSEB_IP0		8
 411#define	 CAUSEF_IP0		(_ULCAST_(1)   <<  8)
 412#define	 CAUSEB_IP1		9
 413#define	 CAUSEF_IP1		(_ULCAST_(1)   <<  9)
 414#define	 CAUSEB_IP2		10
 415#define	 CAUSEF_IP2		(_ULCAST_(1)   << 10)
 416#define	 CAUSEB_IP3		11
 417#define	 CAUSEF_IP3		(_ULCAST_(1)   << 11)
 418#define	 CAUSEB_IP4		12
 419#define	 CAUSEF_IP4		(_ULCAST_(1)   << 12)
 420#define	 CAUSEB_IP5		13
 421#define	 CAUSEF_IP5		(_ULCAST_(1)   << 13)
 422#define	 CAUSEB_IP6		14
 423#define	 CAUSEF_IP6		(_ULCAST_(1)   << 14)
 424#define	 CAUSEB_IP7		15
 425#define	 CAUSEF_IP7		(_ULCAST_(1)   << 15)
 426#define CAUSEB_FDCI		21
 427#define CAUSEF_FDCI		(_ULCAST_(1)   << 21)
 428#define CAUSEB_WP		22
 429#define CAUSEF_WP		(_ULCAST_(1)   << 22)
 430#define CAUSEB_IV		23
 431#define CAUSEF_IV		(_ULCAST_(1)   << 23)
 432#define CAUSEB_PCI		26
 433#define CAUSEF_PCI		(_ULCAST_(1)   << 26)
 434#define CAUSEB_DC		27
 435#define CAUSEF_DC		(_ULCAST_(1)   << 27)
 436#define CAUSEB_CE		28
 437#define CAUSEF_CE		(_ULCAST_(3)   << 28)
 438#define CAUSEB_TI		30
 439#define CAUSEF_TI		(_ULCAST_(1)   << 30)
 440#define CAUSEB_BD		31
 441#define CAUSEF_BD		(_ULCAST_(1)   << 31)
 442
 443/*
 444 * Cause.ExcCode trap codes.
 445 */
 446#define EXCCODE_INT		0	/* Interrupt pending */
 447#define EXCCODE_MOD		1	/* TLB modified fault */
 448#define EXCCODE_TLBL		2	/* TLB miss on load or ifetch */
 449#define EXCCODE_TLBS		3	/* TLB miss on a store */
 450#define EXCCODE_ADEL		4	/* Address error on a load or ifetch */
 451#define EXCCODE_ADES		5	/* Address error on a store */
 452#define EXCCODE_IBE		6	/* Bus error on an ifetch */
 453#define EXCCODE_DBE		7	/* Bus error on a load or store */
 454#define EXCCODE_SYS		8	/* System call */
 455#define EXCCODE_BP		9	/* Breakpoint */
 456#define EXCCODE_RI		10	/* Reserved instruction exception */
 457#define EXCCODE_CPU		11	/* Coprocessor unusable */
 458#define EXCCODE_OV		12	/* Arithmetic overflow */
 459#define EXCCODE_TR		13	/* Trap instruction */
 460#define EXCCODE_MSAFPE		14	/* MSA floating point exception */
 461#define EXCCODE_FPE		15	/* Floating point exception */
 462#define EXCCODE_TLBRI		19	/* TLB Read-Inhibit exception */
 463#define EXCCODE_TLBXI		20	/* TLB Execution-Inhibit exception */
 464#define EXCCODE_MSADIS		21	/* MSA disabled exception */
 465#define EXCCODE_MDMX		22	/* MDMX unusable exception */
 466#define EXCCODE_WATCH		23	/* Watch address reference */
 467#define EXCCODE_MCHECK		24	/* Machine check */
 468#define EXCCODE_THREAD		25	/* Thread exceptions (MT) */
 469#define EXCCODE_DSPDIS		26	/* DSP disabled exception */
 470#define EXCCODE_GE		27	/* Virtualized guest exception (VZ) */
 
 471
 472/* Implementation specific trap codes used by MIPS cores */
 473#define MIPS_EXCCODE_TLBPAR	16	/* TLB parity error exception */
 474
 
 
 
 475/*
 476 * Bits in the coprocessor 0 config register.
 477 */
 478/* Generic bits.  */
 479#define CONF_CM_CACHABLE_NO_WA		0
 480#define CONF_CM_CACHABLE_WA		1
 481#define CONF_CM_UNCACHED		2
 482#define CONF_CM_CACHABLE_NONCOHERENT	3
 483#define CONF_CM_CACHABLE_CE		4
 484#define CONF_CM_CACHABLE_COW		5
 485#define CONF_CM_CACHABLE_CUW		6
 486#define CONF_CM_CACHABLE_ACCELERATED	7
 487#define CONF_CM_CMASK			7
 488#define CONF_BE			(_ULCAST_(1) << 15)
 489
 490/* Bits common to various processors.  */
 491#define CONF_CU			(_ULCAST_(1) <<	 3)
 492#define CONF_DB			(_ULCAST_(1) <<	 4)
 493#define CONF_IB			(_ULCAST_(1) <<	 5)
 494#define CONF_DC			(_ULCAST_(7) <<	 6)
 495#define CONF_IC			(_ULCAST_(7) <<	 9)
 496#define CONF_EB			(_ULCAST_(1) << 13)
 497#define CONF_EM			(_ULCAST_(1) << 14)
 498#define CONF_SM			(_ULCAST_(1) << 16)
 499#define CONF_SC			(_ULCAST_(1) << 17)
 500#define CONF_EW			(_ULCAST_(3) << 18)
 501#define CONF_EP			(_ULCAST_(15)<< 24)
 502#define CONF_EC			(_ULCAST_(7) << 28)
 503#define CONF_CM			(_ULCAST_(1) << 31)
 504
 505/* Bits specific to the R4xx0.	*/
 506#define R4K_CONF_SW		(_ULCAST_(1) << 20)
 507#define R4K_CONF_SS		(_ULCAST_(1) << 21)
 508#define R4K_CONF_SB		(_ULCAST_(3) << 22)
 509
 510/* Bits specific to the R5000.	*/
 511#define R5K_CONF_SE		(_ULCAST_(1) << 12)
 512#define R5K_CONF_SS		(_ULCAST_(3) << 20)
 513
 514/* Bits specific to the RM7000.	 */
 515#define RM7K_CONF_SE		(_ULCAST_(1) <<	 3)
 516#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
 517#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
 518#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
 519#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
 520#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
 521
 522/* Bits specific to the R10000.	 */
 523#define R10K_CONF_DN		(_ULCAST_(3) <<	 3)
 524#define R10K_CONF_CT		(_ULCAST_(1) <<	 5)
 525#define R10K_CONF_PE		(_ULCAST_(1) <<	 6)
 526#define R10K_CONF_PM		(_ULCAST_(3) <<	 7)
 527#define R10K_CONF_EC		(_ULCAST_(15)<<	 9)
 528#define R10K_CONF_SB		(_ULCAST_(1) << 13)
 529#define R10K_CONF_SK		(_ULCAST_(1) << 14)
 530#define R10K_CONF_SS		(_ULCAST_(7) << 16)
 531#define R10K_CONF_SC		(_ULCAST_(7) << 19)
 532#define R10K_CONF_DC		(_ULCAST_(7) << 26)
 533#define R10K_CONF_IC		(_ULCAST_(7) << 29)
 534
 535/* Bits specific to the VR41xx.	 */
 536#define VR41_CONF_CS		(_ULCAST_(1) << 12)
 537#define VR41_CONF_P4K		(_ULCAST_(1) << 13)
 538#define VR41_CONF_BP		(_ULCAST_(1) << 16)
 539#define VR41_CONF_M16		(_ULCAST_(1) << 20)
 540#define VR41_CONF_AD		(_ULCAST_(1) << 23)
 541
 542/* Bits specific to the R30xx.	*/
 543#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
 544#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
 545#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
 546#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
 547#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
 548#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
 549#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
 550#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
 551#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
 552
 553/* Bits specific to the TX49.  */
 554#define TX49_CONF_DC		(_ULCAST_(1) << 16)
 555#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 556#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
 557#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
 558
 559/* Bits specific to the MIPS32/64 PRA.	*/
 560#define MIPS_CONF_VI		(_ULCAST_(1) <<  3)
 561#define MIPS_CONF_MT		(_ULCAST_(7) <<	 7)
 562#define MIPS_CONF_MT_TLB	(_ULCAST_(1) <<  7)
 563#define MIPS_CONF_MT_FTLB	(_ULCAST_(4) <<  7)
 564#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
 565#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
 
 
 
 
 
 
 
 
 
 
 
 566#define MIPS_CONF_M		(_ULCAST_(1) << 31)
 567
 568/*
 569 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 570 */
 571#define MIPS_CONF1_FP		(_ULCAST_(1) <<	 0)
 572#define MIPS_CONF1_EP		(_ULCAST_(1) <<	 1)
 573#define MIPS_CONF1_CA		(_ULCAST_(1) <<	 2)
 574#define MIPS_CONF1_WR		(_ULCAST_(1) <<	 3)
 575#define MIPS_CONF1_PC		(_ULCAST_(1) <<	 4)
 576#define MIPS_CONF1_MD		(_ULCAST_(1) <<	 5)
 577#define MIPS_CONF1_C2		(_ULCAST_(1) <<	 6)
 578#define MIPS_CONF1_DA_SHF	7
 579#define MIPS_CONF1_DA_SZ	3
 580#define MIPS_CONF1_DA		(_ULCAST_(7) <<	 7)
 581#define MIPS_CONF1_DL_SHF	10
 582#define MIPS_CONF1_DL_SZ	3
 583#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
 584#define MIPS_CONF1_DS_SHF	13
 585#define MIPS_CONF1_DS_SZ	3
 586#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
 587#define MIPS_CONF1_IA_SHF	16
 588#define MIPS_CONF1_IA_SZ	3
 589#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
 590#define MIPS_CONF1_IL_SHF	19
 591#define MIPS_CONF1_IL_SZ	3
 592#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
 593#define MIPS_CONF1_IS_SHF	22
 594#define MIPS_CONF1_IS_SZ	3
 595#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
 596#define MIPS_CONF1_TLBS_SHIFT   (25)
 597#define MIPS_CONF1_TLBS_SIZE    (6)
 598#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 599
 600#define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)
 601#define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
 602#define MIPS_CONF2_SS		(_ULCAST_(15)<<	 8)
 603#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
 604#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
 605#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
 606#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
 607#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
 608
 609#define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)
 610#define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)
 611#define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)
 612#define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)
 613#define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)
 614#define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)
 615#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)
 616#define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)
 617#define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)
 618#define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)
 619#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
 620#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)
 621#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)
 622#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)
 623#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)
 624#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)
 625#define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)
 626#define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)
 627#define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)
 628#define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)
 629#define MIPS_CONF3_PW		(_ULCAST_(1) << 24)
 630#define MIPS_CONF3_SC		(_ULCAST_(1) << 25)
 631#define MIPS_CONF3_BI		(_ULCAST_(1) << 26)
 632#define MIPS_CONF3_BP		(_ULCAST_(1) << 27)
 633#define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)
 634#define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)
 635#define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)
 636
 637#define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)
 638#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)
 639#define MIPS_CONF4_FTLBSETS_SHIFT	(0)
 640#define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 641#define MIPS_CONF4_FTLBWAYS_SHIFT	(4)
 642#define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 643#define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)
 644/* bits 10:8 in FTLB-only configurations */
 645#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 646/* bits 12:8 in VTLB-FTLB only configurations */
 647#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 648#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)
 649#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 650#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)
 651#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)
 652#define MIPS_CONF4_KSCREXIST_SHIFT	(16)
 653#define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 654#define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)
 655#define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 656#define MIPS_CONF4_AE		(_ULCAST_(1) << 28)
 657#define MIPS_CONF4_IE		(_ULCAST_(3) << 29)
 658#define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)
 659
 660#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)
 661#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
 662#define MIPS_CONF5_MRP		(_ULCAST_(1) << 3)
 663#define MIPS_CONF5_LLB		(_ULCAST_(1) << 4)
 664#define MIPS_CONF5_MVH		(_ULCAST_(1) << 5)
 665#define MIPS_CONF5_VP		(_ULCAST_(1) << 7)
 666#define MIPS_CONF5_SBRI		(_ULCAST_(1) << 6)
 667#define MIPS_CONF5_FRE		(_ULCAST_(1) << 8)
 668#define MIPS_CONF5_UFE		(_ULCAST_(1) << 9)
 669#define MIPS_CONF5_CA2		(_ULCAST_(1) << 14)
 670#define MIPS_CONF5_MI		(_ULCAST_(1) << 17)
 671#define MIPS_CONF5_CRCP		(_ULCAST_(1) << 18)
 672#define MIPS_CONF5_MSAEN	(_ULCAST_(1) << 27)
 673#define MIPS_CONF5_EVA		(_ULCAST_(1) << 28)
 674#define MIPS_CONF5_CV		(_ULCAST_(1) << 29)
 675#define MIPS_CONF5_K		(_ULCAST_(1) << 30)
 676
 677#define MIPS_CONF6_SYND		(_ULCAST_(1) << 13)
 
 
 
 
 
 
 
 
 
 
 678/* proAptiv FTLB on/off bit */
 679#define MIPS_CONF6_FTLBEN	(_ULCAST_(1) << 15)
 680/* Loongson-3 FTLB on/off bit */
 681#define MIPS_CONF6_FTLBDIS	(_ULCAST_(1) << 22)
 682/* FTLB probability bits */
 683#define MIPS_CONF6_FTLBP_SHIFT	(16)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 684
 685#define MIPS_CONF7_WII		(_ULCAST_(1) << 31)
 686
 687#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)
 688
 689#define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
 690#define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
 691
 
 
 
 692/* Ingenic Config7 bits */
 693#define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
 694
 695/* Config7 Bits specific to MIPS Technologies. */
 696
 697/* Performance counters implemented Per TC */
 698#define MTI_CONF7_PTC		(_ULCAST_(1) << 19)
 699
 700/* WatchLo* register definitions */
 701#define MIPS_WATCHLO_IRW	(_ULCAST_(0x7) << 0)
 702
 703/* WatchHi* register definitions */
 704#define MIPS_WATCHHI_M		(_ULCAST_(1) << 31)
 705#define MIPS_WATCHHI_G		(_ULCAST_(1) << 30)
 706#define MIPS_WATCHHI_WM		(_ULCAST_(0x3) << 28)
 707#define MIPS_WATCHHI_WM_R_RVA	(_ULCAST_(0) << 28)
 708#define MIPS_WATCHHI_WM_R_GPA	(_ULCAST_(1) << 28)
 709#define MIPS_WATCHHI_WM_G_GVA	(_ULCAST_(2) << 28)
 710#define MIPS_WATCHHI_EAS	(_ULCAST_(0x3) << 24)
 711#define MIPS_WATCHHI_ASID	(_ULCAST_(0xff) << 16)
 712#define MIPS_WATCHHI_MASK	(_ULCAST_(0x1ff) << 3)
 713#define MIPS_WATCHHI_I		(_ULCAST_(1) << 2)
 714#define MIPS_WATCHHI_R		(_ULCAST_(1) << 1)
 715#define MIPS_WATCHHI_W		(_ULCAST_(1) << 0)
 716#define MIPS_WATCHHI_IRW	(_ULCAST_(0x7) << 0)
 717
 718/* PerfCnt control register definitions */
 719#define MIPS_PERFCTRL_EXL	(_ULCAST_(1) << 0)
 720#define MIPS_PERFCTRL_K		(_ULCAST_(1) << 1)
 721#define MIPS_PERFCTRL_S		(_ULCAST_(1) << 2)
 722#define MIPS_PERFCTRL_U		(_ULCAST_(1) << 3)
 723#define MIPS_PERFCTRL_IE	(_ULCAST_(1) << 4)
 724#define MIPS_PERFCTRL_EVENT_S	5
 725#define MIPS_PERFCTRL_EVENT	(_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 726#define MIPS_PERFCTRL_PCTD	(_ULCAST_(1) << 15)
 727#define MIPS_PERFCTRL_EC	(_ULCAST_(0x3) << 23)
 728#define MIPS_PERFCTRL_EC_R	(_ULCAST_(0) << 23)
 729#define MIPS_PERFCTRL_EC_RI	(_ULCAST_(1) << 23)
 730#define MIPS_PERFCTRL_EC_G	(_ULCAST_(2) << 23)
 731#define MIPS_PERFCTRL_EC_GRI	(_ULCAST_(3) << 23)
 732#define MIPS_PERFCTRL_W		(_ULCAST_(1) << 30)
 733#define MIPS_PERFCTRL_M		(_ULCAST_(1) << 31)
 734
 735/* PerfCnt control register MT extensions used by MIPS cores */
 736#define MIPS_PERFCTRL_VPEID_S	16
 737#define MIPS_PERFCTRL_VPEID	(_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 738#define MIPS_PERFCTRL_TCID_S	22
 739#define MIPS_PERFCTRL_TCID	(_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 740#define MIPS_PERFCTRL_MT_EN	(_ULCAST_(0x3) << 20)
 741#define MIPS_PERFCTRL_MT_EN_ALL	(_ULCAST_(0) << 20)
 742#define MIPS_PERFCTRL_MT_EN_VPE	(_ULCAST_(1) << 20)
 743#define MIPS_PERFCTRL_MT_EN_TC	(_ULCAST_(2) << 20)
 744
 745/* PerfCnt control register MT extensions used by BMIPS5000 */
 746#define BRCM_PERFCTRL_TC	(_ULCAST_(1) << 30)
 747
 748/* PerfCnt control register MT extensions used by Netlogic XLR */
 749#define XLR_PERFCTRL_ALLTHREADS	(_ULCAST_(1) << 13)
 750
 751/* MAAR bit definitions */
 752#define MIPS_MAAR_VH		(_U64CAST_(1) << 63)
 753#define MIPS_MAAR_ADDR		((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 754#define MIPS_MAAR_ADDR_SHIFT	12
 755#define MIPS_MAAR_S		(_ULCAST_(1) << 1)
 756#define MIPS_MAAR_VL		(_ULCAST_(1) << 0)
 
 
 
 
 
 
 
 
 757
 758/* MAARI bit definitions */
 759#define MIPS_MAARI_INDEX	(_ULCAST_(0x3f) << 0)
 760
 761/* EBase bit definitions */
 762#define MIPS_EBASE_CPUNUM_SHIFT	0
 763#define MIPS_EBASE_CPUNUM	(_ULCAST_(0x3ff) << 0)
 764#define MIPS_EBASE_WG_SHIFT	11
 765#define MIPS_EBASE_WG		(_ULCAST_(1) << 11)
 766#define MIPS_EBASE_BASE_SHIFT	12
 767#define MIPS_EBASE_BASE		(~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 768
 769/* CMGCRBase bit definitions */
 770#define MIPS_CMGCRB_BASE	11
 771#define MIPS_CMGCRF_BASE	(~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 772
 773/* LLAddr bit definitions */
 774#define MIPS_LLADDR_LLB_SHIFT	0
 775#define MIPS_LLADDR_LLB		(_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 776
 777/*
 778 * Bits in the MIPS32 Memory Segmentation registers.
 779 */
 780#define MIPS_SEGCFG_PA_SHIFT	9
 781#define MIPS_SEGCFG_PA		(_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 782#define MIPS_SEGCFG_AM_SHIFT	4
 783#define MIPS_SEGCFG_AM		(_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 784#define MIPS_SEGCFG_EU_SHIFT	3
 785#define MIPS_SEGCFG_EU		(_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 786#define MIPS_SEGCFG_C_SHIFT	0
 787#define MIPS_SEGCFG_C		(_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 788
 789#define MIPS_SEGCFG_UUSK	_ULCAST_(7)
 790#define MIPS_SEGCFG_USK		_ULCAST_(5)
 791#define MIPS_SEGCFG_MUSUK	_ULCAST_(4)
 792#define MIPS_SEGCFG_MUSK	_ULCAST_(3)
 793#define MIPS_SEGCFG_MSK		_ULCAST_(2)
 794#define MIPS_SEGCFG_MK		_ULCAST_(1)
 795#define MIPS_SEGCFG_UK		_ULCAST_(0)
 796
 797#define MIPS_PWFIELD_GDI_SHIFT	24
 798#define MIPS_PWFIELD_GDI_MASK	0x3f000000
 799#define MIPS_PWFIELD_UDI_SHIFT	18
 800#define MIPS_PWFIELD_UDI_MASK	0x00fc0000
 801#define MIPS_PWFIELD_MDI_SHIFT	12
 802#define MIPS_PWFIELD_MDI_MASK	0x0003f000
 803#define MIPS_PWFIELD_PTI_SHIFT	6
 804#define MIPS_PWFIELD_PTI_MASK	0x00000fc0
 805#define MIPS_PWFIELD_PTEI_SHIFT	0
 806#define MIPS_PWFIELD_PTEI_MASK	0x0000003f
 807
 808#define MIPS_PWSIZE_PS_SHIFT	30
 809#define MIPS_PWSIZE_PS_MASK	0x40000000
 810#define MIPS_PWSIZE_GDW_SHIFT	24
 811#define MIPS_PWSIZE_GDW_MASK	0x3f000000
 812#define MIPS_PWSIZE_UDW_SHIFT	18
 813#define MIPS_PWSIZE_UDW_MASK	0x00fc0000
 814#define MIPS_PWSIZE_MDW_SHIFT	12
 815#define MIPS_PWSIZE_MDW_MASK	0x0003f000
 816#define MIPS_PWSIZE_PTW_SHIFT	6
 817#define MIPS_PWSIZE_PTW_MASK	0x00000fc0
 818#define MIPS_PWSIZE_PTEW_SHIFT	0
 819#define MIPS_PWSIZE_PTEW_MASK	0x0000003f
 820
 821#define MIPS_PWCTL_PWEN_SHIFT	31
 822#define MIPS_PWCTL_PWEN_MASK	0x80000000
 823#define MIPS_PWCTL_XK_SHIFT	28
 824#define MIPS_PWCTL_XK_MASK	0x10000000
 825#define MIPS_PWCTL_XS_SHIFT	27
 826#define MIPS_PWCTL_XS_MASK	0x08000000
 827#define MIPS_PWCTL_XU_SHIFT	26
 828#define MIPS_PWCTL_XU_MASK	0x04000000
 829#define MIPS_PWCTL_DPH_SHIFT	7
 830#define MIPS_PWCTL_DPH_MASK	0x00000080
 831#define MIPS_PWCTL_HUGEPG_SHIFT	6
 832#define MIPS_PWCTL_HUGEPG_MASK	0x00000060
 833#define MIPS_PWCTL_PSN_SHIFT	0
 834#define MIPS_PWCTL_PSN_MASK	0x0000003f
 835
 836/* GuestCtl0 fields */
 837#define MIPS_GCTL0_GM_SHIFT	31
 838#define MIPS_GCTL0_GM		(_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 839#define MIPS_GCTL0_RI_SHIFT	30
 840#define MIPS_GCTL0_RI		(_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 841#define MIPS_GCTL0_MC_SHIFT	29
 842#define MIPS_GCTL0_MC		(_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 843#define MIPS_GCTL0_CP0_SHIFT	28
 844#define MIPS_GCTL0_CP0		(_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 845#define MIPS_GCTL0_AT_SHIFT	26
 846#define MIPS_GCTL0_AT		(_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 847#define MIPS_GCTL0_GT_SHIFT	25
 848#define MIPS_GCTL0_GT		(_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 849#define MIPS_GCTL0_CG_SHIFT	24
 850#define MIPS_GCTL0_CG		(_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 851#define MIPS_GCTL0_CF_SHIFT	23
 852#define MIPS_GCTL0_CF		(_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 853#define MIPS_GCTL0_G1_SHIFT	22
 854#define MIPS_GCTL0_G1		(_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 855#define MIPS_GCTL0_G0E_SHIFT	19
 856#define MIPS_GCTL0_G0E		(_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 857#define MIPS_GCTL0_PT_SHIFT	18
 858#define MIPS_GCTL0_PT		(_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 859#define MIPS_GCTL0_RAD_SHIFT	9
 860#define MIPS_GCTL0_RAD		(_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 861#define MIPS_GCTL0_DRG_SHIFT	8
 862#define MIPS_GCTL0_DRG		(_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 863#define MIPS_GCTL0_G2_SHIFT	7
 864#define MIPS_GCTL0_G2		(_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 865#define MIPS_GCTL0_GEXC_SHIFT	2
 866#define MIPS_GCTL0_GEXC		(_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 867#define MIPS_GCTL0_SFC2_SHIFT	1
 868#define MIPS_GCTL0_SFC2		(_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 869#define MIPS_GCTL0_SFC1_SHIFT	0
 870#define MIPS_GCTL0_SFC1		(_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 871
 872/* GuestCtl0.AT Guest address translation control */
 873#define MIPS_GCTL0_AT_ROOT	1  /* Guest MMU under Root control */
 874#define MIPS_GCTL0_AT_GUEST	3  /* Guest MMU under Guest control */
 875
 876/* GuestCtl0.GExcCode Hypervisor exception cause codes */
 877#define MIPS_GCTL0_GEXC_GPSI	0  /* Guest Privileged Sensitive Instruction */
 878#define MIPS_GCTL0_GEXC_GSFC	1  /* Guest Software Field Change */
 879#define MIPS_GCTL0_GEXC_HC	2  /* Hypercall */
 880#define MIPS_GCTL0_GEXC_GRR	3  /* Guest Reserved Instruction Redirect */
 881#define MIPS_GCTL0_GEXC_GVA	8  /* Guest Virtual Address available */
 882#define MIPS_GCTL0_GEXC_GHFC	9  /* Guest Hardware Field Change */
 883#define MIPS_GCTL0_GEXC_GPA	10 /* Guest Physical Address available */
 884
 885/* GuestCtl0Ext fields */
 886#define MIPS_GCTL0EXT_RPW_SHIFT	8
 887#define MIPS_GCTL0EXT_RPW	(_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 888#define MIPS_GCTL0EXT_NCC_SHIFT	6
 889#define MIPS_GCTL0EXT_NCC	(_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 890#define MIPS_GCTL0EXT_CGI_SHIFT	4
 891#define MIPS_GCTL0EXT_CGI	(_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 892#define MIPS_GCTL0EXT_FCD_SHIFT	3
 893#define MIPS_GCTL0EXT_FCD	(_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 894#define MIPS_GCTL0EXT_OG_SHIFT	2
 895#define MIPS_GCTL0EXT_OG	(_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 896#define MIPS_GCTL0EXT_BG_SHIFT	1
 897#define MIPS_GCTL0EXT_BG	(_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 898#define MIPS_GCTL0EXT_MG_SHIFT	0
 899#define MIPS_GCTL0EXT_MG	(_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 900
 901/* GuestCtl0Ext.RPW Root page walk configuration */
 902#define MIPS_GCTL0EXT_RPW_BOTH	0  /* Root PW for GPA->RPA and RVA->RPA */
 903#define MIPS_GCTL0EXT_RPW_GPA	2  /* Root PW for GPA->RPA */
 904#define MIPS_GCTL0EXT_RPW_RVA	3  /* Root PW for RVA->RPA */
 905
 906/* GuestCtl0Ext.NCC Nested cache coherency attributes */
 907#define MIPS_GCTL0EXT_NCC_IND	0  /* Guest CCA independent of Root CCA */
 908#define MIPS_GCTL0EXT_NCC_MOD	1  /* Guest CCA modified by Root CCA */
 909
 910/* GuestCtl1 fields */
 911#define MIPS_GCTL1_ID_SHIFT	0
 912#define MIPS_GCTL1_ID_WIDTH	8
 913#define MIPS_GCTL1_ID		(_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 914#define MIPS_GCTL1_RID_SHIFT	16
 915#define MIPS_GCTL1_RID_WIDTH	8
 916#define MIPS_GCTL1_RID		(_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 917#define MIPS_GCTL1_EID_SHIFT	24
 918#define MIPS_GCTL1_EID_WIDTH	8
 919#define MIPS_GCTL1_EID		(_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 920
 921/* GuestID reserved for root context */
 922#define MIPS_GCTL1_ROOT_GUESTID	0
 923
 924/* CDMMBase register bit definitions */
 925#define MIPS_CDMMBASE_SIZE_SHIFT 0
 926#define MIPS_CDMMBASE_SIZE	(_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 927#define MIPS_CDMMBASE_CI	(_ULCAST_(1) << 9)
 928#define MIPS_CDMMBASE_EN	(_ULCAST_(1) << 10)
 929#define MIPS_CDMMBASE_ADDR_SHIFT 11
 930#define MIPS_CDMMBASE_ADDR_START 15
 931
 932/* RDHWR register numbers */
 933#define MIPS_HWR_CPUNUM		0	/* CPU number */
 934#define MIPS_HWR_SYNCISTEP	1	/* SYNCI step size */
 935#define MIPS_HWR_CC		2	/* Cycle counter */
 936#define MIPS_HWR_CCRES		3	/* Cycle counter resolution */
 937#define MIPS_HWR_ULR		29	/* UserLocal */
 938#define MIPS_HWR_IMPL1		30	/* Implementation dependent */
 939#define MIPS_HWR_IMPL2		31	/* Implementation dependent */
 940
 941/* Bits in HWREna register */
 942#define MIPS_HWRENA_CPUNUM	(_ULCAST_(1) << MIPS_HWR_CPUNUM)
 943#define MIPS_HWRENA_SYNCISTEP	(_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 944#define MIPS_HWRENA_CC		(_ULCAST_(1) << MIPS_HWR_CC)
 945#define MIPS_HWRENA_CCRES	(_ULCAST_(1) << MIPS_HWR_CCRES)
 946#define MIPS_HWRENA_ULR		(_ULCAST_(1) << MIPS_HWR_ULR)
 947#define MIPS_HWRENA_IMPL1	(_ULCAST_(1) << MIPS_HWR_IMPL1)
 948#define MIPS_HWRENA_IMPL2	(_ULCAST_(1) << MIPS_HWR_IMPL2)
 949
 950/*
 951 * Bitfields in the TX39 family CP0 Configuration Register 3
 952 */
 953#define TX39_CONF_ICS_SHIFT	19
 954#define TX39_CONF_ICS_MASK	0x00380000
 955#define TX39_CONF_ICS_1KB	0x00000000
 956#define TX39_CONF_ICS_2KB	0x00080000
 957#define TX39_CONF_ICS_4KB	0x00100000
 958#define TX39_CONF_ICS_8KB	0x00180000
 959#define TX39_CONF_ICS_16KB	0x00200000
 960
 961#define TX39_CONF_DCS_SHIFT	16
 962#define TX39_CONF_DCS_MASK	0x00070000
 963#define TX39_CONF_DCS_1KB	0x00000000
 964#define TX39_CONF_DCS_2KB	0x00010000
 965#define TX39_CONF_DCS_4KB	0x00020000
 966#define TX39_CONF_DCS_8KB	0x00030000
 967#define TX39_CONF_DCS_16KB	0x00040000
 968
 969#define TX39_CONF_CWFON		0x00004000
 970#define TX39_CONF_WBON		0x00002000
 971#define TX39_CONF_RF_SHIFT	10
 972#define TX39_CONF_RF_MASK	0x00000c00
 973#define TX39_CONF_DOZE		0x00000200
 974#define TX39_CONF_HALT		0x00000100
 975#define TX39_CONF_LOCK		0x00000080
 976#define TX39_CONF_ICE		0x00000020
 977#define TX39_CONF_DCE		0x00000010
 978#define TX39_CONF_IRSIZE_SHIFT	2
 979#define TX39_CONF_IRSIZE_MASK	0x0000000c
 980#define TX39_CONF_DRSIZE_SHIFT	0
 981#define TX39_CONF_DRSIZE_MASK	0x00000003
 982
 983/*
 984 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 985 */
 986/* Disable Branch Target Address Cache */
 987#define R10K_DIAG_D_BTAC	(_ULCAST_(1) << 27)
 988/* Enable Branch Prediction Global History */
 989#define R10K_DIAG_E_GHIST	(_ULCAST_(1) << 26)
 990/* Disable Branch Return Cache */
 991#define R10K_DIAG_D_BRC		(_ULCAST_(1) << 22)
 992
 
 
 993/* Flush ITLB */
 994#define LOONGSON_DIAG_ITLB	(_ULCAST_(1) << 2)
 995/* Flush DTLB */
 996#define LOONGSON_DIAG_DTLB	(_ULCAST_(1) << 3)
 
 
 997/* Flush VTLB */
 998#define LOONGSON_DIAG_VTLB	(_ULCAST_(1) << 12)
 999/* Flush FTLB */
1000#define LOONGSON_DIAG_FTLB	(_ULCAST_(1) << 13)
1001
 
 
 
 
 
 
 
1002/* CvmCtl register field definitions */
1003#define CVMCTL_IPPCI_SHIFT	7
1004#define CVMCTL_IPPCI		(_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1005#define CVMCTL_IPTI_SHIFT	4
1006#define CVMCTL_IPTI		(_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1007
1008/* CvmMemCtl2 register field definitions */
1009#define CVMMEMCTL2_INHIBITTS	(_U64CAST_(1) << 17)
1010
1011/* CvmVMConfig register field definitions */
1012#define CVMVMCONF_DGHT		(_U64CAST_(1) << 60)
1013#define CVMVMCONF_MMUSIZEM1_S	12
1014#define CVMVMCONF_MMUSIZEM1	(_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1015#define CVMVMCONF_RMMUSIZEM1_S	0
1016#define CVMVMCONF_RMMUSIZEM1	(_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1017
1018/*
1019 * Coprocessor 1 (FPU) register names
1020 */
1021#define CP1_REVISION	$0
1022#define CP1_UFR		$1
1023#define CP1_UNFR	$4
1024#define CP1_FCCR	$25
1025#define CP1_FEXR	$26
1026#define CP1_FENR	$28
1027#define CP1_STATUS	$31
1028
1029
1030/*
1031 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1032 */
1033#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
1034#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
1035#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
1036#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
1037#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
1038#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
1039#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
1040#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
1041#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
1042#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
1043
1044/*
1045 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1046 */
1047#define MIPS_FCCR_CONDX_S	0
1048#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1049#define MIPS_FCCR_COND0_S	0
1050#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
1051#define MIPS_FCCR_COND1_S	1
1052#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
1053#define MIPS_FCCR_COND2_S	2
1054#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
1055#define MIPS_FCCR_COND3_S	3
1056#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
1057#define MIPS_FCCR_COND4_S	4
1058#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
1059#define MIPS_FCCR_COND5_S	5
1060#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
1061#define MIPS_FCCR_COND6_S	6
1062#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
1063#define MIPS_FCCR_COND7_S	7
1064#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
1065
1066/*
1067 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1068 */
1069#define MIPS_FENR_FS_S		2
1070#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
1071
1072/*
1073 * FPU Status Register Values
1074 */
1075#define FPU_CSR_COND_S	23					/* $fcc0 */
1076#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
1077
1078#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
1079#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
1080
1081#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
1082#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
1083#define FPU_CSR_COND1_S	25					/* $fcc1 */
1084#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
1085#define FPU_CSR_COND2_S	26					/* $fcc2 */
1086#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
1087#define FPU_CSR_COND3_S	27					/* $fcc3 */
1088#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
1089#define FPU_CSR_COND4_S	28					/* $fcc4 */
1090#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
1091#define FPU_CSR_COND5_S	29					/* $fcc5 */
1092#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
1093#define FPU_CSR_COND6_S	30					/* $fcc6 */
1094#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
1095#define FPU_CSR_COND7_S	31					/* $fcc7 */
1096#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
1097
1098/*
1099 * Bits 22:20 of the FPU Status Register will be read as 0,
1100 * and should be written as zero.
 
 
1101 */
1102#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
1103
 
1104#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
1105#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
1106
1107/*
1108 * X the exception cause indicator
1109 * E the exception enable
1110 * S the sticky/flag bit
1111*/
1112#define FPU_CSR_ALL_X	0x0003f000
1113#define FPU_CSR_UNI_X	0x00020000
1114#define FPU_CSR_INV_X	0x00010000
1115#define FPU_CSR_DIV_X	0x00008000
1116#define FPU_CSR_OVF_X	0x00004000
1117#define FPU_CSR_UDF_X	0x00002000
1118#define FPU_CSR_INE_X	0x00001000
1119
1120#define FPU_CSR_ALL_E	0x00000f80
1121#define FPU_CSR_INV_E	0x00000800
1122#define FPU_CSR_DIV_E	0x00000400
1123#define FPU_CSR_OVF_E	0x00000200
1124#define FPU_CSR_UDF_E	0x00000100
1125#define FPU_CSR_INE_E	0x00000080
1126
1127#define FPU_CSR_ALL_S	0x0000007c
1128#define FPU_CSR_INV_S	0x00000040
1129#define FPU_CSR_DIV_S	0x00000020
1130#define FPU_CSR_OVF_S	0x00000010
1131#define FPU_CSR_UDF_S	0x00000008
1132#define FPU_CSR_INE_S	0x00000004
1133
1134/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1135#define FPU_CSR_RM	0x00000003
1136#define FPU_CSR_RN	0x0	/* nearest */
1137#define FPU_CSR_RZ	0x1	/* towards zero */
1138#define FPU_CSR_RU	0x2	/* towards +Infinity */
1139#define FPU_CSR_RD	0x3	/* towards -Infinity */
1140
1141
1142#ifndef __ASSEMBLY__
1143
1144/*
1145 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1146 */
1147#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1148    defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1149#define get_isa16_mode(x)		((x) & 0x1)
1150#define msk_isa16_mode(x)		((x) & ~0x1)
1151#define set_isa16_mode(x)		do { (x) |= 0x1; } while(0)
1152#else
1153#define get_isa16_mode(x)		0
1154#define msk_isa16_mode(x)		(x)
1155#define set_isa16_mode(x)		do { } while(0)
1156#endif
1157
1158/*
1159 * microMIPS instructions can be 16-bit or 32-bit in length. This
1160 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1161 */
1162static inline int mm_insn_16bit(u16 insn)
1163{
1164	u16 opcode = (insn >> 10) & 0x7;
1165
1166	return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1167}
1168
1169/*
1170 * Helper macros for generating raw instruction encodings in inline asm.
1171 */
1172#ifdef CONFIG_CPU_MICROMIPS
1173#define _ASM_INSN16_IF_MM(_enc)			\
1174	".insn\n\t"				\
1175	".hword (" #_enc ")\n\t"
1176#define _ASM_INSN32_IF_MM(_enc)			\
1177	".insn\n\t"				\
1178	".hword ((" #_enc ") >> 16)\n\t"	\
1179	".hword ((" #_enc ") & 0xffff)\n\t"
1180#else
1181#define _ASM_INSN_IF_MIPS(_enc)			\
1182	".insn\n\t"				\
1183	".word (" #_enc ")\n\t"
1184#endif
1185
1186#ifndef _ASM_INSN16_IF_MM
1187#define _ASM_INSN16_IF_MM(_enc)
1188#endif
1189#ifndef _ASM_INSN32_IF_MM
1190#define _ASM_INSN32_IF_MM(_enc)
1191#endif
1192#ifndef _ASM_INSN_IF_MIPS
1193#define _ASM_INSN_IF_MIPS(_enc)
1194#endif
1195
1196/*
1197 * parse_r var, r - Helper assembler macro for parsing register names.
1198 *
1199 * This converts the register name in $n form provided in \r to the
1200 * corresponding register number, which is assigned to the variable \var. It is
1201 * needed to allow explicit encoding of instructions in inline assembly where
1202 * registers are chosen by the compiler in $n form, allowing us to avoid using
1203 * fixed register numbers.
1204 *
1205 * It also allows newer instructions (not implemented by the assembler) to be
1206 * transparently implemented using assembler macros, instead of needing separate
1207 * cases depending on toolchain support.
1208 *
1209 * Simple usage example:
1210 * __asm__ __volatile__("parse_r __rt, %0\n\t"
1211 *			".insn\n\t"
1212 *			"# di    %0\n\t"
1213 *			".word   (0x41606000 | (__rt << 16))"
1214 *			: "=r" (status);
1215 */
1216
1217/* Match an individual register number and assign to \var */
1218#define _IFC_REG(n)				\
1219	".ifc	\\r, $" #n "\n\t"		\
1220	"\\var	= " #n "\n\t"			\
1221	".endif\n\t"
1222
1223__asm__(".macro	parse_r var r\n\t"
1224	"\\var	= -1\n\t"
1225	_IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
1226	_IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
1227	_IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
1228	_IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1229	_IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1230	_IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1231	_IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1232	_IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1233	".iflt	\\var\n\t"
1234	".error	\"Unable to parse register name \\r\"\n\t"
1235	".endif\n\t"
1236	".endm");
1237
1238#undef _IFC_REG
1239
1240/*
1241 * C macros for generating assembler macros for common instruction formats.
1242 *
1243 * The names of the operands can be chosen by the caller, and the encoding of
1244 * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1245 * the ENC encodings.
1246 */
1247
1248/* Instructions with no operands */
1249#define _ASM_MACRO_0(OP, ENC)						\
1250	__asm__(".macro	" #OP "\n\t"					\
1251		ENC							\
1252		".endm")
1253
1254/* Instructions with 1 register operand & 1 immediate operand */
1255#define _ASM_MACRO_1R1I(OP, R1, I2, ENC)				\
1256	__asm__(".macro	" #OP " " #R1 ", " #I2 "\n\t"			\
1257		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1258		ENC							\
1259		".endm")
1260
1261/* Instructions with 2 register operands */
1262#define _ASM_MACRO_2R(OP, R1, R2, ENC)					\
1263	__asm__(".macro	" #OP " " #R1 ", " #R2 "\n\t"			\
1264		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1265		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1266		ENC							\
1267		".endm")
1268
1269/* Instructions with 3 register operands */
1270#define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)				\
1271	__asm__(".macro	" #OP " " #R1 ", " #R2 ", " #R3 "\n\t"		\
1272		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1273		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1274		"parse_r __" #R3 ", \\" #R3 "\n\t"			\
1275		ENC							\
1276		".endm")
1277
1278/* Instructions with 2 register operands and 1 optional select operand */
1279#define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)				\
1280	__asm__(".macro	" #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"	\
1281		"parse_r __" #R1 ", \\" #R1 "\n\t"			\
1282		"parse_r __" #R2 ", \\" #R2 "\n\t"			\
1283		ENC							\
1284		".endm")
1285
1286/*
1287 * TLB Invalidate Flush
1288 */
1289static inline void tlbinvf(void)
1290{
1291	__asm__ __volatile__(
1292		".set push\n\t"
1293		".set noreorder\n\t"
1294		"# tlbinvf\n\t"
1295		_ASM_INSN_IF_MIPS(0x42000004)
1296		_ASM_INSN32_IF_MM(0x0000537c)
1297		".set pop");
1298}
1299
1300
1301/*
1302 * Functions to access the R10000 performance counters.	 These are basically
1303 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1304 * performance counter number encoded into bits 1 ... 5 of the instruction.
1305 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1306 * disassembler these will look like an access to sel 0 or 1.
1307 */
1308#define read_r10k_perf_cntr(counter)				\
1309({								\
1310	unsigned int __res;					\
1311	__asm__ __volatile__(					\
1312	"mfpc\t%0, %1"						\
1313	: "=r" (__res)						\
1314	: "i" (counter));					\
1315								\
1316	__res;							\
1317})
1318
1319#define write_r10k_perf_cntr(counter,val)			\
1320do {								\
1321	__asm__ __volatile__(					\
1322	"mtpc\t%0, %1"						\
1323	:							\
1324	: "r" (val), "i" (counter));				\
1325} while (0)
1326
1327#define read_r10k_perf_event(counter)				\
1328({								\
1329	unsigned int __res;					\
1330	__asm__ __volatile__(					\
1331	"mfps\t%0, %1"						\
1332	: "=r" (__res)						\
1333	: "i" (counter));					\
1334								\
1335	__res;							\
1336})
1337
1338#define write_r10k_perf_cntl(counter,val)			\
1339do {								\
1340	__asm__ __volatile__(					\
1341	"mtps\t%0, %1"						\
1342	:							\
1343	: "r" (val), "i" (counter));				\
1344} while (0)
1345
1346
1347/*
1348 * Macros to access the system control coprocessor
1349 */
1350
1351#define ___read_32bit_c0_register(source, sel, vol)			\
1352({ unsigned int __res;							\
1353	if (sel == 0)							\
1354		__asm__ vol(						\
1355			"mfc0\t%0, " #source "\n\t"			\
1356			: "=r" (__res));				\
1357	else								\
1358		__asm__ vol(						\
1359			".set\tpush\n\t"				\
1360			".set\tmips32\n\t"				\
1361			"mfc0\t%0, " #source ", " #sel "\n\t"		\
1362			".set\tpop\n\t"					\
1363			: "=r" (__res));				\
1364	__res;								\
1365})
1366
1367#define ___read_64bit_c0_register(source, sel, vol)			\
1368({ unsigned long long __res;						\
1369	if (sizeof(unsigned long) == 4)					\
1370		__res = __read_64bit_c0_split(source, sel, vol);	\
1371	else if (sel == 0)						\
1372		__asm__ vol(						\
1373			".set\tpush\n\t"				\
1374			".set\tmips3\n\t"				\
1375			"dmfc0\t%0, " #source "\n\t"			\
1376			".set\tpop"					\
1377			: "=r" (__res));				\
1378	else								\
1379		__asm__ vol(						\
1380			".set\tpush\n\t"				\
1381			".set\tmips64\n\t"				\
1382			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
1383			".set\tpop"					\
1384			: "=r" (__res));				\
1385	__res;								\
1386})
1387
1388#define __read_32bit_c0_register(source, sel)				\
1389	___read_32bit_c0_register(source, sel, __volatile__)
1390
1391#define __read_const_32bit_c0_register(source, sel)			\
1392	___read_32bit_c0_register(source, sel,)
1393
1394#define __read_64bit_c0_register(source, sel)				\
1395	___read_64bit_c0_register(source, sel, __volatile__)
1396
1397#define __read_const_64bit_c0_register(source, sel)			\
1398	___read_64bit_c0_register(source, sel,)
1399
1400#define __write_32bit_c0_register(register, sel, value)			\
1401do {									\
1402	if (sel == 0)							\
1403		__asm__ __volatile__(					\
1404			"mtc0\t%z0, " #register "\n\t"			\
1405			: : "Jr" ((unsigned int)(value)));		\
1406	else								\
1407		__asm__ __volatile__(					\
1408			".set\tpush\n\t"				\
1409			".set\tmips32\n\t"				\
1410			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
1411			".set\tpop"					\
1412			: : "Jr" ((unsigned int)(value)));		\
1413} while (0)
1414
1415#define __write_64bit_c0_register(register, sel, value)			\
1416do {									\
1417	if (sizeof(unsigned long) == 4)					\
1418		__write_64bit_c0_split(register, sel, value);		\
1419	else if (sel == 0)						\
1420		__asm__ __volatile__(					\
1421			".set\tpush\n\t"				\
1422			".set\tmips3\n\t"				\
1423			"dmtc0\t%z0, " #register "\n\t"			\
1424			".set\tpop"					\
1425			: : "Jr" (value));				\
1426	else								\
1427		__asm__ __volatile__(					\
1428			".set\tpush\n\t"				\
1429			".set\tmips64\n\t"				\
1430			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
1431			".set\tpop"					\
1432			: : "Jr" (value));				\
1433} while (0)
1434
1435#define __read_ulong_c0_register(reg, sel)				\
1436	((sizeof(unsigned long) == 4) ?					\
1437	(unsigned long) __read_32bit_c0_register(reg, sel) :		\
1438	(unsigned long) __read_64bit_c0_register(reg, sel))
1439
1440#define __read_const_ulong_c0_register(reg, sel)			\
1441	((sizeof(unsigned long) == 4) ?					\
1442	(unsigned long) __read_const_32bit_c0_register(reg, sel) :	\
1443	(unsigned long) __read_const_64bit_c0_register(reg, sel))
1444
1445#define __write_ulong_c0_register(reg, sel, val)			\
1446do {									\
1447	if (sizeof(unsigned long) == 4)					\
1448		__write_32bit_c0_register(reg, sel, val);		\
1449	else								\
1450		__write_64bit_c0_register(reg, sel, val);		\
1451} while (0)
1452
1453/*
1454 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1455 */
1456#define __read_32bit_c0_ctrl_register(source)				\
1457({ unsigned int __res;							\
1458	__asm__ __volatile__(						\
1459		"cfc0\t%0, " #source "\n\t"				\
1460		: "=r" (__res));					\
1461	__res;								\
1462})
1463
1464#define __write_32bit_c0_ctrl_register(register, value)			\
1465do {									\
1466	__asm__ __volatile__(						\
1467		"ctc0\t%z0, " #register "\n\t"				\
1468		: : "Jr" ((unsigned int)(value)));			\
1469} while (0)
1470
1471/*
1472 * These versions are only needed for systems with more than 38 bits of
1473 * physical address space running the 32-bit kernel.  That's none atm :-)
1474 */
1475#define __read_64bit_c0_split(source, sel, vol)				\
1476({									\
1477	unsigned long long __val;					\
1478	unsigned long __flags;						\
1479									\
1480	local_irq_save(__flags);					\
1481	if (sel == 0)							\
1482		__asm__ vol(						\
1483			".set\tpush\n\t"				\
1484			".set\tmips64\n\t"				\
1485			"dmfc0\t%L0, " #source "\n\t"			\
1486			"dsra\t%M0, %L0, 32\n\t"			\
1487			"sll\t%L0, %L0, 0\n\t"				\
1488			".set\tpop"					\
1489			: "=r" (__val));				\
1490	else								\
1491		__asm__ vol(						\
1492			".set\tpush\n\t"				\
1493			".set\tmips64\n\t"				\
1494			"dmfc0\t%L0, " #source ", " #sel "\n\t"		\
1495			"dsra\t%M0, %L0, 32\n\t"			\
1496			"sll\t%L0, %L0, 0\n\t"				\
1497			".set\tpop"					\
1498			: "=r" (__val));				\
1499	local_irq_restore(__flags);					\
1500									\
1501	__val;								\
1502})
1503
1504#define __write_64bit_c0_split(source, sel, val)			\
1505do {									\
1506	unsigned long long __tmp = (val);				\
1507	unsigned long __flags;						\
1508									\
1509	local_irq_save(__flags);					\
1510	if (MIPS_ISA_REV >= 2)						\
1511		__asm__ __volatile__(					\
1512			".set\tpush\n\t"				\
1513			".set\t" MIPS_ISA_LEVEL "\n\t"			\
1514			"dins\t%L0, %M0, 32, 32\n\t"			\
1515			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1516			".set\tpop"					\
1517			: "+r" (__tmp));				\
1518	else if (sel == 0)						\
1519		__asm__ __volatile__(					\
1520			".set\tpush\n\t"				\
1521			".set\tmips64\n\t"				\
1522			"dsll\t%L0, %L0, 32\n\t"			\
1523			"dsrl\t%L0, %L0, 32\n\t"			\
1524			"dsll\t%M0, %M0, 32\n\t"			\
1525			"or\t%L0, %L0, %M0\n\t"				\
1526			"dmtc0\t%L0, " #source "\n\t"			\
1527			".set\tpop"					\
1528			: "+r" (__tmp));				\
1529	else								\
1530		__asm__ __volatile__(					\
1531			".set\tpush\n\t"				\
1532			".set\tmips64\n\t"				\
1533			"dsll\t%L0, %L0, 32\n\t"			\
1534			"dsrl\t%L0, %L0, 32\n\t"			\
1535			"dsll\t%M0, %M0, 32\n\t"			\
1536			"or\t%L0, %L0, %M0\n\t"				\
1537			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
1538			".set\tpop"					\
1539			: "+r" (__tmp));				\
1540	local_irq_restore(__flags);					\
1541} while (0)
1542
1543#ifndef TOOLCHAIN_SUPPORTS_XPA
1544_ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1545	_ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1546	_ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1547_ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1548	_ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1549	_ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1550#define _ASM_SET_XPA ""
1551#else	/* !TOOLCHAIN_SUPPORTS_XPA */
1552#define _ASM_SET_XPA ".set\txpa\n\t"
1553#endif
1554
1555#define __readx_32bit_c0_register(source, sel)				\
1556({									\
1557	unsigned int __res;						\
1558									\
1559	__asm__ __volatile__(						\
1560	"	.set	push					\n"	\
1561	"	.set	mips32r2				\n"	\
1562	_ASM_SET_XPA							\
1563	"	mfhc0	%0, " #source ", %1			\n"	\
1564	"	.set	pop					\n"	\
1565	: "=r" (__res)							\
1566	: "i" (sel));							\
1567	__res;								\
1568})
1569
1570#define __writex_32bit_c0_register(register, sel, value)		\
1571do {									\
1572	__asm__ __volatile__(						\
1573	"	.set	push					\n"	\
1574	"	.set	mips32r2				\n"	\
1575	_ASM_SET_XPA							\
1576	"	mthc0	%z0, " #register ", %1			\n"	\
1577	"	.set	pop					\n"	\
1578	:								\
1579	: "Jr" (value), "i" (sel));					\
1580} while (0)
1581
1582#define read_c0_index()		__read_32bit_c0_register($0, 0)
1583#define write_c0_index(val)	__write_32bit_c0_register($0, 0, val)
1584
1585#define read_c0_random()	__read_32bit_c0_register($1, 0)
1586#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
1587
1588#define read_c0_entrylo0()	__read_ulong_c0_register($2, 0)
1589#define write_c0_entrylo0(val)	__write_ulong_c0_register($2, 0, val)
1590
1591#define readx_c0_entrylo0()	__readx_32bit_c0_register($2, 0)
1592#define writex_c0_entrylo0(val)	__writex_32bit_c0_register($2, 0, val)
1593
1594#define read_c0_entrylo1()	__read_ulong_c0_register($3, 0)
1595#define write_c0_entrylo1(val)	__write_ulong_c0_register($3, 0, val)
1596
1597#define readx_c0_entrylo1()	__readx_32bit_c0_register($3, 0)
1598#define writex_c0_entrylo1(val)	__writex_32bit_c0_register($3, 0, val)
1599
1600#define read_c0_conf()		__read_32bit_c0_register($3, 0)
1601#define write_c0_conf(val)	__write_32bit_c0_register($3, 0, val)
1602
1603#define read_c0_globalnumber()	__read_32bit_c0_register($3, 1)
1604
1605#define read_c0_context()	__read_ulong_c0_register($4, 0)
1606#define write_c0_context(val)	__write_ulong_c0_register($4, 0, val)
1607
1608#define read_c0_contextconfig()		__read_32bit_c0_register($4, 1)
1609#define write_c0_contextconfig(val)	__write_32bit_c0_register($4, 1, val)
1610
1611#define read_c0_userlocal()	__read_ulong_c0_register($4, 2)
1612#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1613
1614#define read_c0_xcontextconfig()	__read_ulong_c0_register($4, 3)
1615#define write_c0_xcontextconfig(val)	__write_ulong_c0_register($4, 3, val)
1616
1617#define read_c0_memorymapid()		__read_32bit_c0_register($4, 5)
1618#define write_c0_memorymapid(val)	__write_32bit_c0_register($4, 5, val)
1619
1620#define read_c0_pagemask()	__read_32bit_c0_register($5, 0)
1621#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
1622
1623#define read_c0_pagegrain()	__read_32bit_c0_register($5, 1)
1624#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1625
1626#define read_c0_wired()		__read_32bit_c0_register($6, 0)
1627#define write_c0_wired(val)	__write_32bit_c0_register($6, 0, val)
1628
1629#define read_c0_info()		__read_32bit_c0_register($7, 0)
1630
1631#define read_c0_cache()		__read_32bit_c0_register($7, 0) /* TX39xx */
1632#define write_c0_cache(val)	__write_32bit_c0_register($7, 0, val)
1633
1634#define read_c0_badvaddr()	__read_ulong_c0_register($8, 0)
1635#define write_c0_badvaddr(val)	__write_ulong_c0_register($8, 0, val)
1636
1637#define read_c0_badinstr()	__read_32bit_c0_register($8, 1)
1638#define read_c0_badinstrp()	__read_32bit_c0_register($8, 2)
1639
1640#define read_c0_count()		__read_32bit_c0_register($9, 0)
1641#define write_c0_count(val)	__write_32bit_c0_register($9, 0, val)
1642
1643#define read_c0_count2()	__read_32bit_c0_register($9, 6) /* pnx8550 */
1644#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
1645
1646#define read_c0_count3()	__read_32bit_c0_register($9, 7) /* pnx8550 */
1647#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
1648
1649#define read_c0_entryhi()	__read_ulong_c0_register($10, 0)
1650#define write_c0_entryhi(val)	__write_ulong_c0_register($10, 0, val)
1651
1652#define read_c0_guestctl1()	__read_32bit_c0_register($10, 4)
1653#define write_c0_guestctl1(val)	__write_32bit_c0_register($10, 4, val)
1654
1655#define read_c0_guestctl2()	__read_32bit_c0_register($10, 5)
1656#define write_c0_guestctl2(val)	__write_32bit_c0_register($10, 5, val)
1657
1658#define read_c0_guestctl3()	__read_32bit_c0_register($10, 6)
1659#define write_c0_guestctl3(val)	__write_32bit_c0_register($10, 6, val)
1660
1661#define read_c0_compare()	__read_32bit_c0_register($11, 0)
1662#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
1663
1664#define read_c0_guestctl0ext()	__read_32bit_c0_register($11, 4)
1665#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1666
1667#define read_c0_compare2()	__read_32bit_c0_register($11, 6) /* pnx8550 */
1668#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
1669
1670#define read_c0_compare3()	__read_32bit_c0_register($11, 7) /* pnx8550 */
1671#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
1672
1673#define read_c0_status()	__read_32bit_c0_register($12, 0)
1674
1675#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
1676
1677#define read_c0_guestctl0()	__read_32bit_c0_register($12, 6)
1678#define write_c0_guestctl0(val)	__write_32bit_c0_register($12, 6, val)
1679
1680#define read_c0_gtoffset()	__read_32bit_c0_register($12, 7)
1681#define write_c0_gtoffset(val)	__write_32bit_c0_register($12, 7, val)
1682
1683#define read_c0_cause()		__read_32bit_c0_register($13, 0)
1684#define write_c0_cause(val)	__write_32bit_c0_register($13, 0, val)
1685
1686#define read_c0_epc()		__read_ulong_c0_register($14, 0)
1687#define write_c0_epc(val)	__write_ulong_c0_register($14, 0, val)
1688
1689#define read_c0_prid()		__read_const_32bit_c0_register($15, 0)
1690
1691#define read_c0_cmgcrbase()	__read_ulong_c0_register($15, 3)
1692
1693#define read_c0_config()	__read_32bit_c0_register($16, 0)
1694#define read_c0_config1()	__read_32bit_c0_register($16, 1)
1695#define read_c0_config2()	__read_32bit_c0_register($16, 2)
1696#define read_c0_config3()	__read_32bit_c0_register($16, 3)
1697#define read_c0_config4()	__read_32bit_c0_register($16, 4)
1698#define read_c0_config5()	__read_32bit_c0_register($16, 5)
1699#define read_c0_config6()	__read_32bit_c0_register($16, 6)
1700#define read_c0_config7()	__read_32bit_c0_register($16, 7)
1701#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
1702#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
1703#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
1704#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
1705#define write_c0_config4(val)	__write_32bit_c0_register($16, 4, val)
1706#define write_c0_config5(val)	__write_32bit_c0_register($16, 5, val)
1707#define write_c0_config6(val)	__write_32bit_c0_register($16, 6, val)
1708#define write_c0_config7(val)	__write_32bit_c0_register($16, 7, val)
1709
1710#define read_c0_lladdr()	__read_ulong_c0_register($17, 0)
1711#define write_c0_lladdr(val)	__write_ulong_c0_register($17, 0, val)
1712#define read_c0_maar()		__read_ulong_c0_register($17, 1)
1713#define write_c0_maar(val)	__write_ulong_c0_register($17, 1, val)
 
 
1714#define read_c0_maari()		__read_32bit_c0_register($17, 2)
1715#define write_c0_maari(val)	__write_32bit_c0_register($17, 2, val)
1716
1717/*
1718 * The WatchLo register.  There may be up to 8 of them.
1719 */
1720#define read_c0_watchlo0()	__read_ulong_c0_register($18, 0)
1721#define read_c0_watchlo1()	__read_ulong_c0_register($18, 1)
1722#define read_c0_watchlo2()	__read_ulong_c0_register($18, 2)
1723#define read_c0_watchlo3()	__read_ulong_c0_register($18, 3)
1724#define read_c0_watchlo4()	__read_ulong_c0_register($18, 4)
1725#define read_c0_watchlo5()	__read_ulong_c0_register($18, 5)
1726#define read_c0_watchlo6()	__read_ulong_c0_register($18, 6)
1727#define read_c0_watchlo7()	__read_ulong_c0_register($18, 7)
1728#define write_c0_watchlo0(val)	__write_ulong_c0_register($18, 0, val)
1729#define write_c0_watchlo1(val)	__write_ulong_c0_register($18, 1, val)
1730#define write_c0_watchlo2(val)	__write_ulong_c0_register($18, 2, val)
1731#define write_c0_watchlo3(val)	__write_ulong_c0_register($18, 3, val)
1732#define write_c0_watchlo4(val)	__write_ulong_c0_register($18, 4, val)
1733#define write_c0_watchlo5(val)	__write_ulong_c0_register($18, 5, val)
1734#define write_c0_watchlo6(val)	__write_ulong_c0_register($18, 6, val)
1735#define write_c0_watchlo7(val)	__write_ulong_c0_register($18, 7, val)
1736
1737/*
1738 * The WatchHi register.  There may be up to 8 of them.
1739 */
1740#define read_c0_watchhi0()	__read_32bit_c0_register($19, 0)
1741#define read_c0_watchhi1()	__read_32bit_c0_register($19, 1)
1742#define read_c0_watchhi2()	__read_32bit_c0_register($19, 2)
1743#define read_c0_watchhi3()	__read_32bit_c0_register($19, 3)
1744#define read_c0_watchhi4()	__read_32bit_c0_register($19, 4)
1745#define read_c0_watchhi5()	__read_32bit_c0_register($19, 5)
1746#define read_c0_watchhi6()	__read_32bit_c0_register($19, 6)
1747#define read_c0_watchhi7()	__read_32bit_c0_register($19, 7)
1748
1749#define write_c0_watchhi0(val)	__write_32bit_c0_register($19, 0, val)
1750#define write_c0_watchhi1(val)	__write_32bit_c0_register($19, 1, val)
1751#define write_c0_watchhi2(val)	__write_32bit_c0_register($19, 2, val)
1752#define write_c0_watchhi3(val)	__write_32bit_c0_register($19, 3, val)
1753#define write_c0_watchhi4(val)	__write_32bit_c0_register($19, 4, val)
1754#define write_c0_watchhi5(val)	__write_32bit_c0_register($19, 5, val)
1755#define write_c0_watchhi6(val)	__write_32bit_c0_register($19, 6, val)
1756#define write_c0_watchhi7(val)	__write_32bit_c0_register($19, 7, val)
1757
1758#define read_c0_xcontext()	__read_ulong_c0_register($20, 0)
1759#define write_c0_xcontext(val)	__write_ulong_c0_register($20, 0, val)
1760
1761#define read_c0_intcontrol()	__read_32bit_c0_ctrl_register($20)
1762#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1763
1764#define read_c0_framemask()	__read_32bit_c0_register($21, 0)
1765#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1766
1767#define read_c0_diag()		__read_32bit_c0_register($22, 0)
1768#define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
1769
1770/* R10K CP0 Branch Diagnostic register is 64bits wide */
1771#define read_c0_r10k_diag()	__read_64bit_c0_register($22, 0)
1772#define write_c0_r10k_diag(val)	__write_64bit_c0_register($22, 0, val)
1773
1774#define read_c0_diag1()		__read_32bit_c0_register($22, 1)
1775#define write_c0_diag1(val)	__write_32bit_c0_register($22, 1, val)
1776
1777#define read_c0_diag2()		__read_32bit_c0_register($22, 2)
1778#define write_c0_diag2(val)	__write_32bit_c0_register($22, 2, val)
1779
1780#define read_c0_diag3()		__read_32bit_c0_register($22, 3)
1781#define write_c0_diag3(val)	__write_32bit_c0_register($22, 3, val)
1782
1783#define read_c0_diag4()		__read_32bit_c0_register($22, 4)
1784#define write_c0_diag4(val)	__write_32bit_c0_register($22, 4, val)
1785
1786#define read_c0_diag5()		__read_32bit_c0_register($22, 5)
1787#define write_c0_diag5(val)	__write_32bit_c0_register($22, 5, val)
1788
1789#define read_c0_debug()		__read_32bit_c0_register($23, 0)
1790#define write_c0_debug(val)	__write_32bit_c0_register($23, 0, val)
1791
1792#define read_c0_depc()		__read_ulong_c0_register($24, 0)
1793#define write_c0_depc(val)	__write_ulong_c0_register($24, 0, val)
1794
1795/*
1796 * MIPS32 / MIPS64 performance counters
1797 */
1798#define read_c0_perfctrl0()	__read_32bit_c0_register($25, 0)
1799#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1800#define read_c0_perfcntr0()	__read_32bit_c0_register($25, 1)
1801#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1802#define read_c0_perfcntr0_64()	__read_64bit_c0_register($25, 1)
1803#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1804#define read_c0_perfctrl1()	__read_32bit_c0_register($25, 2)
1805#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1806#define read_c0_perfcntr1()	__read_32bit_c0_register($25, 3)
1807#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1808#define read_c0_perfcntr1_64()	__read_64bit_c0_register($25, 3)
1809#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1810#define read_c0_perfctrl2()	__read_32bit_c0_register($25, 4)
1811#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1812#define read_c0_perfcntr2()	__read_32bit_c0_register($25, 5)
1813#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1814#define read_c0_perfcntr2_64()	__read_64bit_c0_register($25, 5)
1815#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1816#define read_c0_perfctrl3()	__read_32bit_c0_register($25, 6)
1817#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1818#define read_c0_perfcntr3()	__read_32bit_c0_register($25, 7)
1819#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1820#define read_c0_perfcntr3_64()	__read_64bit_c0_register($25, 7)
1821#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1822
1823#define read_c0_ecc()		__read_32bit_c0_register($26, 0)
1824#define write_c0_ecc(val)	__write_32bit_c0_register($26, 0, val)
1825
1826#define read_c0_derraddr0()	__read_ulong_c0_register($26, 1)
1827#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1828
1829#define read_c0_cacheerr()	__read_32bit_c0_register($27, 0)
1830
1831#define read_c0_derraddr1()	__read_ulong_c0_register($27, 1)
1832#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1833
1834#define read_c0_taglo()		__read_32bit_c0_register($28, 0)
1835#define write_c0_taglo(val)	__write_32bit_c0_register($28, 0, val)
1836
1837#define read_c0_dtaglo()	__read_32bit_c0_register($28, 2)
1838#define write_c0_dtaglo(val)	__write_32bit_c0_register($28, 2, val)
1839
1840#define read_c0_ddatalo()	__read_32bit_c0_register($28, 3)
1841#define write_c0_ddatalo(val)	__write_32bit_c0_register($28, 3, val)
1842
1843#define read_c0_staglo()	__read_32bit_c0_register($28, 4)
1844#define write_c0_staglo(val)	__write_32bit_c0_register($28, 4, val)
1845
1846#define read_c0_taghi()		__read_32bit_c0_register($29, 0)
1847#define write_c0_taghi(val)	__write_32bit_c0_register($29, 0, val)
1848
1849#define read_c0_errorepc()	__read_ulong_c0_register($30, 0)
1850#define write_c0_errorepc(val)	__write_ulong_c0_register($30, 0, val)
1851
1852/* MIPSR2 */
1853#define read_c0_hwrena()	__read_32bit_c0_register($7, 0)
1854#define write_c0_hwrena(val)	__write_32bit_c0_register($7, 0, val)
1855
1856#define read_c0_intctl()	__read_32bit_c0_register($12, 1)
1857#define write_c0_intctl(val)	__write_32bit_c0_register($12, 1, val)
1858
1859#define read_c0_srsctl()	__read_32bit_c0_register($12, 2)
1860#define write_c0_srsctl(val)	__write_32bit_c0_register($12, 2, val)
1861
1862#define read_c0_srsmap()	__read_32bit_c0_register($12, 3)
1863#define write_c0_srsmap(val)	__write_32bit_c0_register($12, 3, val)
1864
1865#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
1866#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
1867
1868#define read_c0_ebase_64()	__read_64bit_c0_register($15, 1)
1869#define write_c0_ebase_64(val)	__write_64bit_c0_register($15, 1, val)
1870
1871#define read_c0_cdmmbase()	__read_ulong_c0_register($15, 2)
1872#define write_c0_cdmmbase(val)	__write_ulong_c0_register($15, 2, val)
1873
1874/* MIPSR3 */
1875#define read_c0_segctl0()	__read_32bit_c0_register($5, 2)
1876#define write_c0_segctl0(val)	__write_32bit_c0_register($5, 2, val)
1877
1878#define read_c0_segctl1()	__read_32bit_c0_register($5, 3)
1879#define write_c0_segctl1(val)	__write_32bit_c0_register($5, 3, val)
1880
1881#define read_c0_segctl2()	__read_32bit_c0_register($5, 4)
1882#define write_c0_segctl2(val)	__write_32bit_c0_register($5, 4, val)
1883
1884/* Hardware Page Table Walker */
1885#define read_c0_pwbase()	__read_ulong_c0_register($5, 5)
1886#define write_c0_pwbase(val)	__write_ulong_c0_register($5, 5, val)
1887
1888#define read_c0_pwfield()	__read_ulong_c0_register($5, 6)
1889#define write_c0_pwfield(val)	__write_ulong_c0_register($5, 6, val)
1890
1891#define read_c0_pwsize()	__read_ulong_c0_register($5, 7)
1892#define write_c0_pwsize(val)	__write_ulong_c0_register($5, 7, val)
1893
1894#define read_c0_pwctl()		__read_32bit_c0_register($6, 6)
1895#define write_c0_pwctl(val)	__write_32bit_c0_register($6, 6, val)
1896
1897#define read_c0_pgd()		__read_64bit_c0_register($9, 7)
1898#define write_c0_pgd(val)	__write_64bit_c0_register($9, 7, val)
1899
1900#define read_c0_kpgd()		__read_64bit_c0_register($31, 7)
1901#define write_c0_kpgd(val)	__write_64bit_c0_register($31, 7, val)
1902
1903/* Cavium OCTEON (cnMIPS) */
1904#define read_c0_cvmcount()	__read_ulong_c0_register($9, 6)
1905#define write_c0_cvmcount(val)	__write_ulong_c0_register($9, 6, val)
1906
1907#define read_c0_cvmctl()	__read_64bit_c0_register($9, 7)
1908#define write_c0_cvmctl(val)	__write_64bit_c0_register($9, 7, val)
1909
1910#define read_c0_cvmmemctl()	__read_64bit_c0_register($11, 7)
1911#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1912
1913#define read_c0_cvmmemctl2()	__read_64bit_c0_register($16, 6)
1914#define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1915
1916#define read_c0_cvmvmconfig()	__read_64bit_c0_register($16, 7)
1917#define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1918
1919/*
1920 * The cacheerr registers are not standardized.	 On OCTEON, they are
1921 * 64 bits wide.
1922 */
1923#define read_octeon_c0_icacheerr()	__read_64bit_c0_register($27, 0)
1924#define write_octeon_c0_icacheerr(val)	__write_64bit_c0_register($27, 0, val)
1925
1926#define read_octeon_c0_dcacheerr()	__read_64bit_c0_register($27, 1)
1927#define write_octeon_c0_dcacheerr(val)	__write_64bit_c0_register($27, 1, val)
1928
1929/* BMIPS3300 */
1930#define read_c0_brcm_config_0()		__read_32bit_c0_register($22, 0)
1931#define write_c0_brcm_config_0(val)	__write_32bit_c0_register($22, 0, val)
1932
1933#define read_c0_brcm_bus_pll()		__read_32bit_c0_register($22, 4)
1934#define write_c0_brcm_bus_pll(val)	__write_32bit_c0_register($22, 4, val)
1935
1936#define read_c0_brcm_reset()		__read_32bit_c0_register($22, 5)
1937#define write_c0_brcm_reset(val)	__write_32bit_c0_register($22, 5, val)
1938
1939/* BMIPS43xx */
1940#define read_c0_brcm_cmt_intr()		__read_32bit_c0_register($22, 1)
1941#define write_c0_brcm_cmt_intr(val)	__write_32bit_c0_register($22, 1, val)
1942
1943#define read_c0_brcm_cmt_ctrl()		__read_32bit_c0_register($22, 2)
1944#define write_c0_brcm_cmt_ctrl(val)	__write_32bit_c0_register($22, 2, val)
1945
1946#define read_c0_brcm_cmt_local()	__read_32bit_c0_register($22, 3)
1947#define write_c0_brcm_cmt_local(val)	__write_32bit_c0_register($22, 3, val)
1948
1949#define read_c0_brcm_config_1()		__read_32bit_c0_register($22, 5)
1950#define write_c0_brcm_config_1(val)	__write_32bit_c0_register($22, 5, val)
1951
1952#define read_c0_brcm_cbr()		__read_32bit_c0_register($22, 6)
1953#define write_c0_brcm_cbr(val)		__write_32bit_c0_register($22, 6, val)
1954
1955/* BMIPS5000 */
1956#define read_c0_brcm_config()		__read_32bit_c0_register($22, 0)
1957#define write_c0_brcm_config(val)	__write_32bit_c0_register($22, 0, val)
1958
1959#define read_c0_brcm_mode()		__read_32bit_c0_register($22, 1)
1960#define write_c0_brcm_mode(val)		__write_32bit_c0_register($22, 1, val)
1961
1962#define read_c0_brcm_action()		__read_32bit_c0_register($22, 2)
1963#define write_c0_brcm_action(val)	__write_32bit_c0_register($22, 2, val)
1964
1965#define read_c0_brcm_edsp()		__read_32bit_c0_register($22, 3)
1966#define write_c0_brcm_edsp(val)		__write_32bit_c0_register($22, 3, val)
1967
1968#define read_c0_brcm_bootvec()		__read_32bit_c0_register($22, 4)
1969#define write_c0_brcm_bootvec(val)	__write_32bit_c0_register($22, 4, val)
1970
1971#define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
1972#define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22, 7, val)
1973
 
 
 
1974/*
1975 * Macros to access the guest system control coprocessor
1976 */
1977
1978#ifndef TOOLCHAIN_SUPPORTS_VIRT
1979_ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1980	_ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1981	_ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1982_ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1983	_ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1984	_ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1985_ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1986	_ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1987	_ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1988_ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1989	_ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1990	_ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1991_ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
1992		       _ASM_INSN32_IF_MM(0x0000017c));
1993_ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
1994		       _ASM_INSN32_IF_MM(0x0000117c));
1995_ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
1996		       _ASM_INSN32_IF_MM(0x0000217c));
1997_ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
1998		       _ASM_INSN32_IF_MM(0x0000317c));
1999_ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2000		       _ASM_INSN32_IF_MM(0x0000517c));
2001#define _ASM_SET_VIRT ""
2002#else	/* !TOOLCHAIN_SUPPORTS_VIRT */
2003#define _ASM_SET_VIRT ".set\tvirt\n\t"
2004#endif
2005
2006#define __read_32bit_gc0_register(source, sel)				\
2007({ int __res;								\
2008	__asm__ __volatile__(						\
2009		".set\tpush\n\t"					\
2010		".set\tmips32r2\n\t"					\
2011		_ASM_SET_VIRT						\
2012		"mfgc0\t%0, " #source ", %1\n\t"			\
2013		".set\tpop"						\
2014		: "=r" (__res)						\
2015		: "i" (sel));						\
2016	__res;								\
2017})
2018
2019#define __read_64bit_gc0_register(source, sel)				\
2020({ unsigned long long __res;						\
2021	__asm__ __volatile__(						\
2022		".set\tpush\n\t"					\
2023		".set\tmips64r2\n\t"					\
2024		_ASM_SET_VIRT						\
2025		"dmfgc0\t%0, " #source ", %1\n\t"			\
2026		".set\tpop"						\
2027		: "=r" (__res)						\
2028		: "i" (sel));						\
2029	__res;								\
2030})
2031
2032#define __write_32bit_gc0_register(register, sel, value)		\
2033do {									\
2034	__asm__ __volatile__(						\
2035		".set\tpush\n\t"					\
2036		".set\tmips32r2\n\t"					\
2037		_ASM_SET_VIRT						\
2038		"mtgc0\t%z0, " #register ", %1\n\t"			\
2039		".set\tpop"						\
2040		: : "Jr" ((unsigned int)(value)),			\
2041		    "i" (sel));						\
2042} while (0)
2043
2044#define __write_64bit_gc0_register(register, sel, value)		\
2045do {									\
2046	__asm__ __volatile__(						\
2047		".set\tpush\n\t"					\
2048		".set\tmips64r2\n\t"					\
2049		_ASM_SET_VIRT						\
2050		"dmtgc0\t%z0, " #register ", %1\n\t"			\
2051		".set\tpop"						\
2052		: : "Jr" (value),					\
2053		    "i" (sel));						\
2054} while (0)
2055
2056#define __read_ulong_gc0_register(reg, sel)				\
2057	((sizeof(unsigned long) == 4) ?					\
2058	(unsigned long) __read_32bit_gc0_register(reg, sel) :		\
2059	(unsigned long) __read_64bit_gc0_register(reg, sel))
2060
2061#define __write_ulong_gc0_register(reg, sel, val)			\
2062do {									\
2063	if (sizeof(unsigned long) == 4)					\
2064		__write_32bit_gc0_register(reg, sel, val);		\
2065	else								\
2066		__write_64bit_gc0_register(reg, sel, val);		\
2067} while (0)
2068
2069#define read_gc0_index()		__read_32bit_gc0_register($0, 0)
2070#define write_gc0_index(val)		__write_32bit_gc0_register($0, 0, val)
2071
2072#define read_gc0_entrylo0()		__read_ulong_gc0_register($2, 0)
2073#define write_gc0_entrylo0(val)		__write_ulong_gc0_register($2, 0, val)
2074
2075#define read_gc0_entrylo1()		__read_ulong_gc0_register($3, 0)
2076#define write_gc0_entrylo1(val)		__write_ulong_gc0_register($3, 0, val)
2077
2078#define read_gc0_context()		__read_ulong_gc0_register($4, 0)
2079#define write_gc0_context(val)		__write_ulong_gc0_register($4, 0, val)
2080
2081#define read_gc0_contextconfig()	__read_32bit_gc0_register($4, 1)
2082#define write_gc0_contextconfig(val)	__write_32bit_gc0_register($4, 1, val)
2083
2084#define read_gc0_userlocal()		__read_ulong_gc0_register($4, 2)
2085#define write_gc0_userlocal(val)	__write_ulong_gc0_register($4, 2, val)
2086
2087#define read_gc0_xcontextconfig()	__read_ulong_gc0_register($4, 3)
2088#define write_gc0_xcontextconfig(val)	__write_ulong_gc0_register($4, 3, val)
2089
2090#define read_gc0_pagemask()		__read_32bit_gc0_register($5, 0)
2091#define write_gc0_pagemask(val)		__write_32bit_gc0_register($5, 0, val)
2092
2093#define read_gc0_pagegrain()		__read_32bit_gc0_register($5, 1)
2094#define write_gc0_pagegrain(val)	__write_32bit_gc0_register($5, 1, val)
2095
2096#define read_gc0_segctl0()		__read_ulong_gc0_register($5, 2)
2097#define write_gc0_segctl0(val)		__write_ulong_gc0_register($5, 2, val)
2098
2099#define read_gc0_segctl1()		__read_ulong_gc0_register($5, 3)
2100#define write_gc0_segctl1(val)		__write_ulong_gc0_register($5, 3, val)
2101
2102#define read_gc0_segctl2()		__read_ulong_gc0_register($5, 4)
2103#define write_gc0_segctl2(val)		__write_ulong_gc0_register($5, 4, val)
2104
2105#define read_gc0_pwbase()		__read_ulong_gc0_register($5, 5)
2106#define write_gc0_pwbase(val)		__write_ulong_gc0_register($5, 5, val)
2107
2108#define read_gc0_pwfield()		__read_ulong_gc0_register($5, 6)
2109#define write_gc0_pwfield(val)		__write_ulong_gc0_register($5, 6, val)
2110
2111#define read_gc0_pwsize()		__read_ulong_gc0_register($5, 7)
2112#define write_gc0_pwsize(val)		__write_ulong_gc0_register($5, 7, val)
2113
2114#define read_gc0_wired()		__read_32bit_gc0_register($6, 0)
2115#define write_gc0_wired(val)		__write_32bit_gc0_register($6, 0, val)
2116
2117#define read_gc0_pwctl()		__read_32bit_gc0_register($6, 6)
2118#define write_gc0_pwctl(val)		__write_32bit_gc0_register($6, 6, val)
2119
2120#define read_gc0_hwrena()		__read_32bit_gc0_register($7, 0)
2121#define write_gc0_hwrena(val)		__write_32bit_gc0_register($7, 0, val)
2122
2123#define read_gc0_badvaddr()		__read_ulong_gc0_register($8, 0)
2124#define write_gc0_badvaddr(val)		__write_ulong_gc0_register($8, 0, val)
2125
2126#define read_gc0_badinstr()		__read_32bit_gc0_register($8, 1)
2127#define write_gc0_badinstr(val)		__write_32bit_gc0_register($8, 1, val)
2128
2129#define read_gc0_badinstrp()		__read_32bit_gc0_register($8, 2)
2130#define write_gc0_badinstrp(val)	__write_32bit_gc0_register($8, 2, val)
2131
2132#define read_gc0_count()		__read_32bit_gc0_register($9, 0)
2133
2134#define read_gc0_entryhi()		__read_ulong_gc0_register($10, 0)
2135#define write_gc0_entryhi(val)		__write_ulong_gc0_register($10, 0, val)
2136
2137#define read_gc0_compare()		__read_32bit_gc0_register($11, 0)
2138#define write_gc0_compare(val)		__write_32bit_gc0_register($11, 0, val)
2139
2140#define read_gc0_status()		__read_32bit_gc0_register($12, 0)
2141#define write_gc0_status(val)		__write_32bit_gc0_register($12, 0, val)
2142
2143#define read_gc0_intctl()		__read_32bit_gc0_register($12, 1)
2144#define write_gc0_intctl(val)		__write_32bit_gc0_register($12, 1, val)
2145
2146#define read_gc0_cause()		__read_32bit_gc0_register($13, 0)
2147#define write_gc0_cause(val)		__write_32bit_gc0_register($13, 0, val)
2148
2149#define read_gc0_epc()			__read_ulong_gc0_register($14, 0)
2150#define write_gc0_epc(val)		__write_ulong_gc0_register($14, 0, val)
2151
2152#define read_gc0_prid()			__read_32bit_gc0_register($15, 0)
2153
2154#define read_gc0_ebase()		__read_32bit_gc0_register($15, 1)
2155#define write_gc0_ebase(val)		__write_32bit_gc0_register($15, 1, val)
2156
2157#define read_gc0_ebase_64()		__read_64bit_gc0_register($15, 1)
2158#define write_gc0_ebase_64(val)		__write_64bit_gc0_register($15, 1, val)
2159
2160#define read_gc0_config()		__read_32bit_gc0_register($16, 0)
2161#define read_gc0_config1()		__read_32bit_gc0_register($16, 1)
2162#define read_gc0_config2()		__read_32bit_gc0_register($16, 2)
2163#define read_gc0_config3()		__read_32bit_gc0_register($16, 3)
2164#define read_gc0_config4()		__read_32bit_gc0_register($16, 4)
2165#define read_gc0_config5()		__read_32bit_gc0_register($16, 5)
2166#define read_gc0_config6()		__read_32bit_gc0_register($16, 6)
2167#define read_gc0_config7()		__read_32bit_gc0_register($16, 7)
2168#define write_gc0_config(val)		__write_32bit_gc0_register($16, 0, val)
2169#define write_gc0_config1(val)		__write_32bit_gc0_register($16, 1, val)
2170#define write_gc0_config2(val)		__write_32bit_gc0_register($16, 2, val)
2171#define write_gc0_config3(val)		__write_32bit_gc0_register($16, 3, val)
2172#define write_gc0_config4(val)		__write_32bit_gc0_register($16, 4, val)
2173#define write_gc0_config5(val)		__write_32bit_gc0_register($16, 5, val)
2174#define write_gc0_config6(val)		__write_32bit_gc0_register($16, 6, val)
2175#define write_gc0_config7(val)		__write_32bit_gc0_register($16, 7, val)
2176
2177#define read_gc0_lladdr()		__read_ulong_gc0_register($17, 0)
2178#define write_gc0_lladdr(val)		__write_ulong_gc0_register($17, 0, val)
2179
2180#define read_gc0_watchlo0()		__read_ulong_gc0_register($18, 0)
2181#define read_gc0_watchlo1()		__read_ulong_gc0_register($18, 1)
2182#define read_gc0_watchlo2()		__read_ulong_gc0_register($18, 2)
2183#define read_gc0_watchlo3()		__read_ulong_gc0_register($18, 3)
2184#define read_gc0_watchlo4()		__read_ulong_gc0_register($18, 4)
2185#define read_gc0_watchlo5()		__read_ulong_gc0_register($18, 5)
2186#define read_gc0_watchlo6()		__read_ulong_gc0_register($18, 6)
2187#define read_gc0_watchlo7()		__read_ulong_gc0_register($18, 7)
2188#define write_gc0_watchlo0(val)		__write_ulong_gc0_register($18, 0, val)
2189#define write_gc0_watchlo1(val)		__write_ulong_gc0_register($18, 1, val)
2190#define write_gc0_watchlo2(val)		__write_ulong_gc0_register($18, 2, val)
2191#define write_gc0_watchlo3(val)		__write_ulong_gc0_register($18, 3, val)
2192#define write_gc0_watchlo4(val)		__write_ulong_gc0_register($18, 4, val)
2193#define write_gc0_watchlo5(val)		__write_ulong_gc0_register($18, 5, val)
2194#define write_gc0_watchlo6(val)		__write_ulong_gc0_register($18, 6, val)
2195#define write_gc0_watchlo7(val)		__write_ulong_gc0_register($18, 7, val)
2196
2197#define read_gc0_watchhi0()		__read_32bit_gc0_register($19, 0)
2198#define read_gc0_watchhi1()		__read_32bit_gc0_register($19, 1)
2199#define read_gc0_watchhi2()		__read_32bit_gc0_register($19, 2)
2200#define read_gc0_watchhi3()		__read_32bit_gc0_register($19, 3)
2201#define read_gc0_watchhi4()		__read_32bit_gc0_register($19, 4)
2202#define read_gc0_watchhi5()		__read_32bit_gc0_register($19, 5)
2203#define read_gc0_watchhi6()		__read_32bit_gc0_register($19, 6)
2204#define read_gc0_watchhi7()		__read_32bit_gc0_register($19, 7)
2205#define write_gc0_watchhi0(val)		__write_32bit_gc0_register($19, 0, val)
2206#define write_gc0_watchhi1(val)		__write_32bit_gc0_register($19, 1, val)
2207#define write_gc0_watchhi2(val)		__write_32bit_gc0_register($19, 2, val)
2208#define write_gc0_watchhi3(val)		__write_32bit_gc0_register($19, 3, val)
2209#define write_gc0_watchhi4(val)		__write_32bit_gc0_register($19, 4, val)
2210#define write_gc0_watchhi5(val)		__write_32bit_gc0_register($19, 5, val)
2211#define write_gc0_watchhi6(val)		__write_32bit_gc0_register($19, 6, val)
2212#define write_gc0_watchhi7(val)		__write_32bit_gc0_register($19, 7, val)
2213
2214#define read_gc0_xcontext()		__read_ulong_gc0_register($20, 0)
2215#define write_gc0_xcontext(val)		__write_ulong_gc0_register($20, 0, val)
2216
2217#define read_gc0_perfctrl0()		__read_32bit_gc0_register($25, 0)
2218#define write_gc0_perfctrl0(val)	__write_32bit_gc0_register($25, 0, val)
2219#define read_gc0_perfcntr0()		__read_32bit_gc0_register($25, 1)
2220#define write_gc0_perfcntr0(val)	__write_32bit_gc0_register($25, 1, val)
2221#define read_gc0_perfcntr0_64()		__read_64bit_gc0_register($25, 1)
2222#define write_gc0_perfcntr0_64(val)	__write_64bit_gc0_register($25, 1, val)
2223#define read_gc0_perfctrl1()		__read_32bit_gc0_register($25, 2)
2224#define write_gc0_perfctrl1(val)	__write_32bit_gc0_register($25, 2, val)
2225#define read_gc0_perfcntr1()		__read_32bit_gc0_register($25, 3)
2226#define write_gc0_perfcntr1(val)	__write_32bit_gc0_register($25, 3, val)
2227#define read_gc0_perfcntr1_64()		__read_64bit_gc0_register($25, 3)
2228#define write_gc0_perfcntr1_64(val)	__write_64bit_gc0_register($25, 3, val)
2229#define read_gc0_perfctrl2()		__read_32bit_gc0_register($25, 4)
2230#define write_gc0_perfctrl2(val)	__write_32bit_gc0_register($25, 4, val)
2231#define read_gc0_perfcntr2()		__read_32bit_gc0_register($25, 5)
2232#define write_gc0_perfcntr2(val)	__write_32bit_gc0_register($25, 5, val)
2233#define read_gc0_perfcntr2_64()		__read_64bit_gc0_register($25, 5)
2234#define write_gc0_perfcntr2_64(val)	__write_64bit_gc0_register($25, 5, val)
2235#define read_gc0_perfctrl3()		__read_32bit_gc0_register($25, 6)
2236#define write_gc0_perfctrl3(val)	__write_32bit_gc0_register($25, 6, val)
2237#define read_gc0_perfcntr3()		__read_32bit_gc0_register($25, 7)
2238#define write_gc0_perfcntr3(val)	__write_32bit_gc0_register($25, 7, val)
2239#define read_gc0_perfcntr3_64()		__read_64bit_gc0_register($25, 7)
2240#define write_gc0_perfcntr3_64(val)	__write_64bit_gc0_register($25, 7, val)
2241
2242#define read_gc0_errorepc()		__read_ulong_gc0_register($30, 0)
2243#define write_gc0_errorepc(val)		__write_ulong_gc0_register($30, 0, val)
2244
2245#define read_gc0_kscratch1()		__read_ulong_gc0_register($31, 2)
2246#define read_gc0_kscratch2()		__read_ulong_gc0_register($31, 3)
2247#define read_gc0_kscratch3()		__read_ulong_gc0_register($31, 4)
2248#define read_gc0_kscratch4()		__read_ulong_gc0_register($31, 5)
2249#define read_gc0_kscratch5()		__read_ulong_gc0_register($31, 6)
2250#define read_gc0_kscratch6()		__read_ulong_gc0_register($31, 7)
2251#define write_gc0_kscratch1(val)	__write_ulong_gc0_register($31, 2, val)
2252#define write_gc0_kscratch2(val)	__write_ulong_gc0_register($31, 3, val)
2253#define write_gc0_kscratch3(val)	__write_ulong_gc0_register($31, 4, val)
2254#define write_gc0_kscratch4(val)	__write_ulong_gc0_register($31, 5, val)
2255#define write_gc0_kscratch5(val)	__write_ulong_gc0_register($31, 6, val)
2256#define write_gc0_kscratch6(val)	__write_ulong_gc0_register($31, 7, val)
2257
2258/* Cavium OCTEON (cnMIPS) */
2259#define read_gc0_cvmcount()		__read_ulong_gc0_register($9, 6)
2260#define write_gc0_cvmcount(val)		__write_ulong_gc0_register($9, 6, val)
2261
2262#define read_gc0_cvmctl()		__read_64bit_gc0_register($9, 7)
2263#define write_gc0_cvmctl(val)		__write_64bit_gc0_register($9, 7, val)
2264
2265#define read_gc0_cvmmemctl()		__read_64bit_gc0_register($11, 7)
2266#define write_gc0_cvmmemctl(val)	__write_64bit_gc0_register($11, 7, val)
2267
2268#define read_gc0_cvmmemctl2()		__read_64bit_gc0_register($16, 6)
2269#define write_gc0_cvmmemctl2(val)	__write_64bit_gc0_register($16, 6, val)
2270
2271/*
2272 * Macros to access the floating point coprocessor control registers
2273 */
2274#define _read_32bit_cp1_register(source, gas_hardfloat)			\
2275({									\
2276	unsigned int __res;						\
2277									\
2278	__asm__ __volatile__(						\
2279	"	.set	push					\n"	\
2280	"	.set	reorder					\n"	\
2281	"	# gas fails to assemble cfc1 for some archs,	\n"	\
2282	"	# like Octeon.					\n"	\
2283	"	.set	mips1					\n"	\
2284	"	"STR(gas_hardfloat)"				\n"	\
2285	"	cfc1	%0,"STR(source)"			\n"	\
2286	"	.set	pop					\n"	\
2287	: "=r" (__res));						\
2288	__res;								\
2289})
2290
2291#define _write_32bit_cp1_register(dest, val, gas_hardfloat)		\
2292do {									\
2293	__asm__ __volatile__(						\
2294	"	.set	push					\n"	\
2295	"	.set	reorder					\n"	\
2296	"	"STR(gas_hardfloat)"				\n"	\
2297	"	ctc1	%0,"STR(dest)"				\n"	\
2298	"	.set	pop					\n"	\
2299	: : "r" (val));							\
2300} while (0)
2301
2302#ifdef GAS_HAS_SET_HARDFLOAT
2303#define read_32bit_cp1_register(source)					\
2304	_read_32bit_cp1_register(source, .set hardfloat)
2305#define write_32bit_cp1_register(dest, val)				\
2306	_write_32bit_cp1_register(dest, val, .set hardfloat)
2307#else
2308#define read_32bit_cp1_register(source)					\
2309	_read_32bit_cp1_register(source, )
2310#define write_32bit_cp1_register(dest, val)				\
2311	_write_32bit_cp1_register(dest, val, )
2312#endif
2313
2314#ifdef TOOLCHAIN_SUPPORTS_DSP
2315#define rddsp(mask)							\
2316({									\
2317	unsigned int __dspctl;						\
2318									\
2319	__asm__ __volatile__(						\
2320	"	.set push					\n"	\
2321	"	.set " MIPS_ISA_LEVEL "				\n"	\
2322	"	.set dsp					\n"	\
2323	"	rddsp	%0, %x1					\n"	\
2324	"	.set pop					\n"	\
2325	: "=r" (__dspctl)						\
2326	: "i" (mask));							\
2327	__dspctl;							\
2328})
2329
2330#define wrdsp(val, mask)						\
2331do {									\
2332	__asm__ __volatile__(						\
2333	"	.set push					\n"	\
2334	"	.set " MIPS_ISA_LEVEL "				\n"	\
2335	"	.set dsp					\n"	\
2336	"	wrdsp	%0, %x1					\n"	\
2337	"	.set pop					\n"	\
2338	:								\
2339	: "r" (val), "i" (mask));					\
2340} while (0)
2341
2342#define mflo0()								\
2343({									\
2344	long mflo0;							\
2345	__asm__(							\
2346	"	.set push					\n"	\
2347	"	.set " MIPS_ISA_LEVEL "				\n"	\
2348	"	.set dsp					\n"	\
2349	"	mflo %0, $ac0					\n"	\
2350	"	.set pop					\n" 	\
2351	: "=r" (mflo0)); 						\
2352	mflo0;								\
2353})
2354
2355#define mflo1()								\
2356({									\
2357	long mflo1;							\
2358	__asm__(							\
2359	"	.set push					\n"	\
2360	"	.set " MIPS_ISA_LEVEL "				\n"	\
2361	"	.set dsp					\n"	\
2362	"	mflo %0, $ac1					\n"	\
2363	"	.set pop					\n" 	\
2364	: "=r" (mflo1)); 						\
2365	mflo1;								\
2366})
2367
2368#define mflo2()								\
2369({									\
2370	long mflo2;							\
2371	__asm__(							\
2372	"	.set push					\n"	\
2373	"	.set " MIPS_ISA_LEVEL "				\n"	\
2374	"	.set dsp					\n"	\
2375	"	mflo %0, $ac2					\n"	\
2376	"	.set pop					\n" 	\
2377	: "=r" (mflo2)); 						\
2378	mflo2;								\
2379})
2380
2381#define mflo3()								\
2382({									\
2383	long mflo3;							\
2384	__asm__(							\
2385	"	.set push					\n"	\
2386	"	.set " MIPS_ISA_LEVEL "				\n"	\
2387	"	.set dsp					\n"	\
2388	"	mflo %0, $ac3					\n"	\
2389	"	.set pop					\n" 	\
2390	: "=r" (mflo3)); 						\
2391	mflo3;								\
2392})
2393
2394#define mfhi0()								\
2395({									\
2396	long mfhi0;							\
2397	__asm__(							\
2398	"	.set push					\n"	\
2399	"	.set " MIPS_ISA_LEVEL "				\n"	\
2400	"	.set dsp					\n"	\
2401	"	mfhi %0, $ac0					\n"	\
2402	"	.set pop					\n" 	\
2403	: "=r" (mfhi0)); 						\
2404	mfhi0;								\
2405})
2406
2407#define mfhi1()								\
2408({									\
2409	long mfhi1;							\
2410	__asm__(							\
2411	"	.set push					\n"	\
2412	"	.set " MIPS_ISA_LEVEL "				\n"	\
2413	"	.set dsp					\n"	\
2414	"	mfhi %0, $ac1					\n"	\
2415	"	.set pop					\n" 	\
2416	: "=r" (mfhi1)); 						\
2417	mfhi1;								\
2418})
2419
2420#define mfhi2()								\
2421({									\
2422	long mfhi2;							\
2423	__asm__(							\
2424	"	.set push					\n"	\
2425	"	.set " MIPS_ISA_LEVEL "				\n"	\
2426	"	.set dsp					\n"	\
2427	"	mfhi %0, $ac2					\n"	\
2428	"	.set pop					\n" 	\
2429	: "=r" (mfhi2)); 						\
2430	mfhi2;								\
2431})
2432
2433#define mfhi3()								\
2434({									\
2435	long mfhi3;							\
2436	__asm__(							\
2437	"	.set push					\n"	\
2438	"	.set " MIPS_ISA_LEVEL "				\n"	\
2439	"	.set dsp					\n"	\
2440	"	mfhi %0, $ac3					\n"	\
2441	"	.set pop					\n" 	\
2442	: "=r" (mfhi3)); 						\
2443	mfhi3;								\
2444})
2445
2446
2447#define mtlo0(x)							\
2448({									\
2449	__asm__(							\
2450	"	.set push					\n"	\
2451	"	.set " MIPS_ISA_LEVEL "				\n"	\
2452	"	.set dsp					\n"	\
2453	"	mtlo %0, $ac0					\n"	\
2454	"	.set pop					\n"	\
2455	:								\
2456	: "r" (x));							\
2457})
2458
2459#define mtlo1(x)							\
2460({									\
2461	__asm__(							\
2462	"	.set push					\n"	\
2463	"	.set " MIPS_ISA_LEVEL "				\n"	\
2464	"	.set dsp					\n"	\
2465	"	mtlo %0, $ac1					\n"	\
2466	"	.set pop					\n"	\
2467	:								\
2468	: "r" (x));							\
2469})
2470
2471#define mtlo2(x)							\
2472({									\
2473	__asm__(							\
2474	"	.set push					\n"	\
2475	"	.set " MIPS_ISA_LEVEL "				\n"	\
2476	"	.set dsp					\n"	\
2477	"	mtlo %0, $ac2					\n"	\
2478	"	.set pop					\n"	\
2479	:								\
2480	: "r" (x));							\
2481})
2482
2483#define mtlo3(x)							\
2484({									\
2485	__asm__(							\
2486	"	.set push					\n"	\
2487	"	.set " MIPS_ISA_LEVEL "				\n"	\
2488	"	.set dsp					\n"	\
2489	"	mtlo %0, $ac3					\n"	\
2490	"	.set pop					\n"	\
2491	:								\
2492	: "r" (x));							\
2493})
2494
2495#define mthi0(x)							\
2496({									\
2497	__asm__(							\
2498	"	.set push					\n"	\
2499	"	.set " MIPS_ISA_LEVEL "				\n"	\
2500	"	.set dsp					\n"	\
2501	"	mthi %0, $ac0					\n"	\
2502	"	.set pop					\n"	\
2503	:								\
2504	: "r" (x));							\
2505})
2506
2507#define mthi1(x)							\
2508({									\
2509	__asm__(							\
2510	"	.set push					\n"	\
2511	"	.set " MIPS_ISA_LEVEL "				\n"	\
2512	"	.set dsp					\n"	\
2513	"	mthi %0, $ac1					\n"	\
2514	"	.set pop					\n"	\
2515	:								\
2516	: "r" (x));							\
2517})
2518
2519#define mthi2(x)							\
2520({									\
2521	__asm__(							\
2522	"	.set push					\n"	\
2523	"	.set " MIPS_ISA_LEVEL "				\n"	\
2524	"	.set dsp					\n"	\
2525	"	mthi %0, $ac2					\n"	\
2526	"	.set pop					\n"	\
2527	:								\
2528	: "r" (x));							\
2529})
2530
2531#define mthi3(x)							\
2532({									\
2533	__asm__(							\
2534	"	.set push					\n"	\
2535	"	.set " MIPS_ISA_LEVEL "				\n"	\
2536	"	.set dsp					\n"	\
2537	"	mthi %0, $ac3					\n"	\
2538	"	.set pop					\n"	\
2539	:								\
2540	: "r" (x));							\
2541})
2542
2543#else
2544
2545#define rddsp(mask)							\
2546({									\
2547	unsigned int __res;						\
2548									\
2549	__asm__ __volatile__(						\
2550	"	.set	push					\n"	\
2551	"	.set	noat					\n"	\
2552	"	# rddsp $1, %x1					\n"	\
2553	_ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))			\
2554	_ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))			\
2555	"	move	%0, $1					\n"	\
2556	"	.set	pop					\n"	\
2557	: "=r" (__res)							\
2558	: "i" (mask));							\
2559	__res;								\
2560})
2561
2562#define wrdsp(val, mask)						\
2563do {									\
2564	__asm__ __volatile__(						\
2565	"	.set	push					\n"	\
2566	"	.set	noat					\n"	\
2567	"	move	$1, %0					\n"	\
2568	"	# wrdsp $1, %x1					\n"	\
2569	_ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))			\
2570	_ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))			\
2571	"	.set	pop					\n"	\
2572	:								\
2573	: "r" (val), "i" (mask));					\
2574} while (0)
2575
2576#define _dsp_mfxxx(ins)							\
2577({									\
2578	unsigned long __treg;						\
2579									\
2580	__asm__ __volatile__(						\
2581	"	.set	push					\n"	\
2582	"	.set	noat					\n"	\
2583	_ASM_INSN_IF_MIPS(0x00000810 | %X1)				\
2584	_ASM_INSN32_IF_MM(0x0001007c | %x1)				\
2585	"	move	%0, $1					\n"	\
2586	"	.set	pop					\n"	\
2587	: "=r" (__treg)							\
2588	: "i" (ins));							\
2589	__treg;								\
2590})
2591
2592#define _dsp_mtxxx(val, ins)						\
2593do {									\
2594	__asm__ __volatile__(						\
2595	"	.set	push					\n"	\
2596	"	.set	noat					\n"	\
2597	"	move	$1, %0					\n"	\
2598	_ASM_INSN_IF_MIPS(0x00200011 | %X1)				\
2599	_ASM_INSN32_IF_MM(0x0001207c | %x1)				\
2600	"	.set	pop					\n"	\
2601	:								\
2602	: "r" (val), "i" (ins));					\
2603} while (0)
2604
2605#ifdef CONFIG_CPU_MICROMIPS
2606
2607#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2608#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2609
2610#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2611#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2612
2613#else  /* !CONFIG_CPU_MICROMIPS */
2614
2615#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2616#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2617
2618#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2619#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2620
2621#endif /* CONFIG_CPU_MICROMIPS */
2622
2623#define mflo0() _dsp_mflo(0)
2624#define mflo1() _dsp_mflo(1)
2625#define mflo2() _dsp_mflo(2)
2626#define mflo3() _dsp_mflo(3)
2627
2628#define mfhi0() _dsp_mfhi(0)
2629#define mfhi1() _dsp_mfhi(1)
2630#define mfhi2() _dsp_mfhi(2)
2631#define mfhi3() _dsp_mfhi(3)
2632
2633#define mtlo0(x) _dsp_mtlo(x, 0)
2634#define mtlo1(x) _dsp_mtlo(x, 1)
2635#define mtlo2(x) _dsp_mtlo(x, 2)
2636#define mtlo3(x) _dsp_mtlo(x, 3)
2637
2638#define mthi0(x) _dsp_mthi(x, 0)
2639#define mthi1(x) _dsp_mthi(x, 1)
2640#define mthi2(x) _dsp_mthi(x, 2)
2641#define mthi3(x) _dsp_mthi(x, 3)
2642
2643#endif
2644
2645/*
2646 * TLB operations.
2647 *
2648 * It is responsibility of the caller to take care of any TLB hazards.
2649 */
2650static inline void tlb_probe(void)
2651{
2652	__asm__ __volatile__(
2653		".set noreorder\n\t"
2654		"tlbp\n\t"
2655		".set reorder");
2656}
2657
2658static inline void tlb_read(void)
2659{
2660#if MIPS34K_MISSED_ITLB_WAR
2661	int res = 0;
2662
2663	__asm__ __volatile__(
2664	"	.set	push					\n"
2665	"	.set	noreorder				\n"
2666	"	.set	noat					\n"
2667	"	.set	mips32r2				\n"
2668	"	.word	0x41610001		# dvpe $1	\n"
2669	"	move	%0, $1					\n"
2670	"	ehb						\n"
2671	"	.set	pop					\n"
2672	: "=r" (res));
2673
2674	instruction_hazard();
2675#endif
2676
2677	__asm__ __volatile__(
2678		".set noreorder\n\t"
2679		"tlbr\n\t"
2680		".set reorder");
2681
2682#if MIPS34K_MISSED_ITLB_WAR
2683	if ((res & _ULCAST_(1)))
2684		__asm__ __volatile__(
2685		"	.set	push				\n"
2686		"	.set	noreorder			\n"
2687		"	.set	noat				\n"
2688		"	.set	mips32r2			\n"
2689		"	.word	0x41600021	# evpe		\n"
2690		"	ehb					\n"
2691		"	.set	pop				\n");
2692#endif
2693}
2694
2695static inline void tlb_write_indexed(void)
2696{
2697	__asm__ __volatile__(
2698		".set noreorder\n\t"
2699		"tlbwi\n\t"
2700		".set reorder");
2701}
2702
2703static inline void tlb_write_random(void)
2704{
2705	__asm__ __volatile__(
2706		".set noreorder\n\t"
2707		"tlbwr\n\t"
2708		".set reorder");
2709}
2710
2711/*
2712 * Guest TLB operations.
2713 *
2714 * It is responsibility of the caller to take care of any TLB hazards.
2715 */
2716static inline void guest_tlb_probe(void)
2717{
2718	__asm__ __volatile__(
2719		".set push\n\t"
2720		".set noreorder\n\t"
2721		_ASM_SET_VIRT
2722		"tlbgp\n\t"
2723		".set pop");
2724}
2725
2726static inline void guest_tlb_read(void)
2727{
2728	__asm__ __volatile__(
2729		".set push\n\t"
2730		".set noreorder\n\t"
2731		_ASM_SET_VIRT
2732		"tlbgr\n\t"
2733		".set pop");
2734}
2735
2736static inline void guest_tlb_write_indexed(void)
2737{
2738	__asm__ __volatile__(
2739		".set push\n\t"
2740		".set noreorder\n\t"
2741		_ASM_SET_VIRT
2742		"tlbgwi\n\t"
2743		".set pop");
2744}
2745
2746static inline void guest_tlb_write_random(void)
2747{
2748	__asm__ __volatile__(
2749		".set push\n\t"
2750		".set noreorder\n\t"
2751		_ASM_SET_VIRT
2752		"tlbgwr\n\t"
2753		".set pop");
2754}
2755
2756/*
2757 * Guest TLB Invalidate Flush
2758 */
2759static inline void guest_tlbinvf(void)
2760{
2761	__asm__ __volatile__(
2762		".set push\n\t"
2763		".set noreorder\n\t"
2764		_ASM_SET_VIRT
2765		"tlbginvf\n\t"
2766		".set pop");
2767}
2768
2769/*
2770 * Manipulate bits in a register.
2771 */
2772#define __BUILD_SET_COMMON(name)				\
2773static inline unsigned int					\
2774set_##name(unsigned int set)					\
2775{								\
2776	unsigned int res, new;					\
2777								\
2778	res = read_##name();					\
2779	new = res | set;					\
2780	write_##name(new);					\
2781								\
2782	return res;						\
2783}								\
2784								\
2785static inline unsigned int					\
2786clear_##name(unsigned int clear)				\
2787{								\
2788	unsigned int res, new;					\
2789								\
2790	res = read_##name();					\
2791	new = res & ~clear;					\
2792	write_##name(new);					\
2793								\
2794	return res;						\
2795}								\
2796								\
2797static inline unsigned int					\
2798change_##name(unsigned int change, unsigned int val)		\
2799{								\
2800	unsigned int res, new;					\
2801								\
2802	res = read_##name();					\
2803	new = res & ~change;					\
2804	new |= (val & change);					\
2805	write_##name(new);					\
2806								\
2807	return res;						\
2808}
2809
2810/*
2811 * Manipulate bits in a c0 register.
2812 */
2813#define __BUILD_SET_C0(name)	__BUILD_SET_COMMON(c0_##name)
2814
2815__BUILD_SET_C0(status)
2816__BUILD_SET_C0(cause)
2817__BUILD_SET_C0(config)
2818__BUILD_SET_C0(config5)
 
2819__BUILD_SET_C0(config7)
 
2820__BUILD_SET_C0(intcontrol)
2821__BUILD_SET_C0(intctl)
2822__BUILD_SET_C0(srsmap)
2823__BUILD_SET_C0(pagegrain)
2824__BUILD_SET_C0(guestctl0)
2825__BUILD_SET_C0(guestctl0ext)
2826__BUILD_SET_C0(guestctl1)
2827__BUILD_SET_C0(guestctl2)
2828__BUILD_SET_C0(guestctl3)
2829__BUILD_SET_C0(brcm_config_0)
2830__BUILD_SET_C0(brcm_bus_pll)
2831__BUILD_SET_C0(brcm_reset)
2832__BUILD_SET_C0(brcm_cmt_intr)
2833__BUILD_SET_C0(brcm_cmt_ctrl)
2834__BUILD_SET_C0(brcm_config)
2835__BUILD_SET_C0(brcm_mode)
2836
2837/*
2838 * Manipulate bits in a guest c0 register.
2839 */
2840#define __BUILD_SET_GC0(name)	__BUILD_SET_COMMON(gc0_##name)
2841
2842__BUILD_SET_GC0(wired)
2843__BUILD_SET_GC0(status)
2844__BUILD_SET_GC0(cause)
2845__BUILD_SET_GC0(ebase)
2846__BUILD_SET_GC0(config1)
2847
2848/*
2849 * Return low 10 bits of ebase.
2850 * Note that under KVM (MIPSVZ) this returns vcpu id.
2851 */
2852static inline unsigned int get_ebase_cpunum(void)
2853{
2854	return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2855}
2856
2857#endif /* !__ASSEMBLY__ */
2858
2859#endif /* _ASM_MIPSREGS_H */