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1// SPDX-License-Identifier: GPL-2.0-only
2/* cpu_feature_enabled() cannot be used this early */
3#define USE_EARLY_PGTABLE_L5
4
5#include <linux/memblock.h>
6#include <linux/linkage.h>
7#include <linux/bitops.h>
8#include <linux/kernel.h>
9#include <linux/export.h>
10#include <linux/percpu.h>
11#include <linux/string.h>
12#include <linux/ctype.h>
13#include <linux/delay.h>
14#include <linux/sched/mm.h>
15#include <linux/sched/clock.h>
16#include <linux/sched/task.h>
17#include <linux/init.h>
18#include <linux/kprobes.h>
19#include <linux/kgdb.h>
20#include <linux/smp.h>
21#include <linux/io.h>
22#include <linux/syscore_ops.h>
23
24#include <asm/stackprotector.h>
25#include <asm/perf_event.h>
26#include <asm/mmu_context.h>
27#include <asm/archrandom.h>
28#include <asm/hypervisor.h>
29#include <asm/processor.h>
30#include <asm/tlbflush.h>
31#include <asm/debugreg.h>
32#include <asm/sections.h>
33#include <asm/vsyscall.h>
34#include <linux/topology.h>
35#include <linux/cpumask.h>
36#include <asm/pgtable.h>
37#include <linux/atomic.h>
38#include <asm/proto.h>
39#include <asm/setup.h>
40#include <asm/apic.h>
41#include <asm/desc.h>
42#include <asm/fpu/internal.h>
43#include <asm/mtrr.h>
44#include <asm/hwcap2.h>
45#include <linux/numa.h>
46#include <asm/asm.h>
47#include <asm/bugs.h>
48#include <asm/cpu.h>
49#include <asm/mce.h>
50#include <asm/msr.h>
51#include <asm/pat.h>
52#include <asm/microcode.h>
53#include <asm/microcode_intel.h>
54#include <asm/intel-family.h>
55#include <asm/cpu_device_id.h>
56
57#ifdef CONFIG_X86_LOCAL_APIC
58#include <asm/uv/uv.h>
59#endif
60
61#include "cpu.h"
62
63u32 elf_hwcap2 __read_mostly;
64
65/* all of these masks are initialized in setup_cpu_local_masks() */
66cpumask_var_t cpu_initialized_mask;
67cpumask_var_t cpu_callout_mask;
68cpumask_var_t cpu_callin_mask;
69
70/* representing cpus for which sibling maps can be computed */
71cpumask_var_t cpu_sibling_setup_mask;
72
73/* Number of siblings per CPU package */
74int smp_num_siblings = 1;
75EXPORT_SYMBOL(smp_num_siblings);
76
77/* Last level cache ID of each logical CPU */
78DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
79
80/* correctly size the local cpu masks */
81void __init setup_cpu_local_masks(void)
82{
83 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
84 alloc_bootmem_cpumask_var(&cpu_callin_mask);
85 alloc_bootmem_cpumask_var(&cpu_callout_mask);
86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
87}
88
89static void default_init(struct cpuinfo_x86 *c)
90{
91#ifdef CONFIG_X86_64
92 cpu_detect_cache_sizes(c);
93#else
94 /* Not much we can do here... */
95 /* Check if at least it has cpuid */
96 if (c->cpuid_level == -1) {
97 /* No cpuid. It must be an ancient CPU */
98 if (c->x86 == 4)
99 strcpy(c->x86_model_id, "486");
100 else if (c->x86 == 3)
101 strcpy(c->x86_model_id, "386");
102 }
103#endif
104}
105
106static const struct cpu_dev default_cpu = {
107 .c_init = default_init,
108 .c_vendor = "Unknown",
109 .c_x86_vendor = X86_VENDOR_UNKNOWN,
110};
111
112static const struct cpu_dev *this_cpu = &default_cpu;
113
114DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
115#ifdef CONFIG_X86_64
116 /*
117 * We need valid kernel segments for data and code in long mode too
118 * IRET will check the segment types kkeil 2000/10/28
119 * Also sysret mandates a special GDT layout
120 *
121 * TLS descriptors are currently at a different place compared to i386.
122 * Hopefully nobody expects them at a fixed place (Wine?)
123 */
124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
130#else
131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
135 /*
136 * Segments used for calling PnP BIOS have byte granularity.
137 * They code segments and data segments have fixed 64k limits,
138 * the transfer segment sizes are set at run time.
139 */
140 /* 32-bit code */
141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
142 /* 16-bit code */
143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
144 /* 16-bit data */
145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
146 /* 16-bit data */
147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 /* 16-bit data */
149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 /*
151 * The APM segments have byte granularity and their bases
152 * are set at run time. All have 64k limits.
153 */
154 /* 32-bit code */
155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
156 /* 16-bit code */
157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
158 /* data */
159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
160
161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 GDT_STACK_CANARY_INIT
164#endif
165} };
166EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
167
168static int __init x86_mpx_setup(char *s)
169{
170 /* require an exact match without trailing characters */
171 if (strlen(s))
172 return 0;
173
174 /* do not emit a message if the feature is not present */
175 if (!boot_cpu_has(X86_FEATURE_MPX))
176 return 1;
177
178 setup_clear_cpu_cap(X86_FEATURE_MPX);
179 pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
180 return 1;
181}
182__setup("nompx", x86_mpx_setup);
183
184#ifdef CONFIG_X86_64
185static int __init x86_nopcid_setup(char *s)
186{
187 /* nopcid doesn't accept parameters */
188 if (s)
189 return -EINVAL;
190
191 /* do not emit a message if the feature is not present */
192 if (!boot_cpu_has(X86_FEATURE_PCID))
193 return 0;
194
195 setup_clear_cpu_cap(X86_FEATURE_PCID);
196 pr_info("nopcid: PCID feature disabled\n");
197 return 0;
198}
199early_param("nopcid", x86_nopcid_setup);
200#endif
201
202static int __init x86_noinvpcid_setup(char *s)
203{
204 /* noinvpcid doesn't accept parameters */
205 if (s)
206 return -EINVAL;
207
208 /* do not emit a message if the feature is not present */
209 if (!boot_cpu_has(X86_FEATURE_INVPCID))
210 return 0;
211
212 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
213 pr_info("noinvpcid: INVPCID feature disabled\n");
214 return 0;
215}
216early_param("noinvpcid", x86_noinvpcid_setup);
217
218#ifdef CONFIG_X86_32
219static int cachesize_override = -1;
220static int disable_x86_serial_nr = 1;
221
222static int __init cachesize_setup(char *str)
223{
224 get_option(&str, &cachesize_override);
225 return 1;
226}
227__setup("cachesize=", cachesize_setup);
228
229static int __init x86_sep_setup(char *s)
230{
231 setup_clear_cpu_cap(X86_FEATURE_SEP);
232 return 1;
233}
234__setup("nosep", x86_sep_setup);
235
236/* Standard macro to see if a specific flag is changeable */
237static inline int flag_is_changeable_p(u32 flag)
238{
239 u32 f1, f2;
240
241 /*
242 * Cyrix and IDT cpus allow disabling of CPUID
243 * so the code below may return different results
244 * when it is executed before and after enabling
245 * the CPUID. Add "volatile" to not allow gcc to
246 * optimize the subsequent calls to this function.
247 */
248 asm volatile ("pushfl \n\t"
249 "pushfl \n\t"
250 "popl %0 \n\t"
251 "movl %0, %1 \n\t"
252 "xorl %2, %0 \n\t"
253 "pushl %0 \n\t"
254 "popfl \n\t"
255 "pushfl \n\t"
256 "popl %0 \n\t"
257 "popfl \n\t"
258
259 : "=&r" (f1), "=&r" (f2)
260 : "ir" (flag));
261
262 return ((f1^f2) & flag) != 0;
263}
264
265/* Probe for the CPUID instruction */
266int have_cpuid_p(void)
267{
268 return flag_is_changeable_p(X86_EFLAGS_ID);
269}
270
271static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
272{
273 unsigned long lo, hi;
274
275 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
276 return;
277
278 /* Disable processor serial number: */
279
280 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
281 lo |= 0x200000;
282 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
283
284 pr_notice("CPU serial number disabled.\n");
285 clear_cpu_cap(c, X86_FEATURE_PN);
286
287 /* Disabling the serial number may affect the cpuid level */
288 c->cpuid_level = cpuid_eax(0);
289}
290
291static int __init x86_serial_nr_setup(char *s)
292{
293 disable_x86_serial_nr = 0;
294 return 1;
295}
296__setup("serialnumber", x86_serial_nr_setup);
297#else
298static inline int flag_is_changeable_p(u32 flag)
299{
300 return 1;
301}
302static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
303{
304}
305#endif
306
307static __init int setup_disable_smep(char *arg)
308{
309 setup_clear_cpu_cap(X86_FEATURE_SMEP);
310 /* Check for things that depend on SMEP being enabled: */
311 check_mpx_erratum(&boot_cpu_data);
312 return 1;
313}
314__setup("nosmep", setup_disable_smep);
315
316static __always_inline void setup_smep(struct cpuinfo_x86 *c)
317{
318 if (cpu_has(c, X86_FEATURE_SMEP))
319 cr4_set_bits(X86_CR4_SMEP);
320}
321
322static __init int setup_disable_smap(char *arg)
323{
324 setup_clear_cpu_cap(X86_FEATURE_SMAP);
325 return 1;
326}
327__setup("nosmap", setup_disable_smap);
328
329static __always_inline void setup_smap(struct cpuinfo_x86 *c)
330{
331 unsigned long eflags = native_save_fl();
332
333 /* This should have been cleared long ago */
334 BUG_ON(eflags & X86_EFLAGS_AC);
335
336 if (cpu_has(c, X86_FEATURE_SMAP)) {
337#ifdef CONFIG_X86_SMAP
338 cr4_set_bits(X86_CR4_SMAP);
339#else
340 cr4_clear_bits(X86_CR4_SMAP);
341#endif
342 }
343}
344
345static __always_inline void setup_umip(struct cpuinfo_x86 *c)
346{
347 /* Check the boot processor, plus build option for UMIP. */
348 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
349 goto out;
350
351 /* Check the current processor's cpuid bits. */
352 if (!cpu_has(c, X86_FEATURE_UMIP))
353 goto out;
354
355 cr4_set_bits(X86_CR4_UMIP);
356
357 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
358
359 return;
360
361out:
362 /*
363 * Make sure UMIP is disabled in case it was enabled in a
364 * previous boot (e.g., via kexec).
365 */
366 cr4_clear_bits(X86_CR4_UMIP);
367}
368
369static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
370static unsigned long cr4_pinned_bits __ro_after_init;
371
372void native_write_cr0(unsigned long val)
373{
374 unsigned long bits_missing = 0;
375
376set_register:
377 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order));
378
379 if (static_branch_likely(&cr_pinning)) {
380 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
381 bits_missing = X86_CR0_WP;
382 val |= bits_missing;
383 goto set_register;
384 }
385 /* Warn after we've set the missing bits. */
386 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
387 }
388}
389EXPORT_SYMBOL(native_write_cr0);
390
391void native_write_cr4(unsigned long val)
392{
393 unsigned long bits_missing = 0;
394
395set_register:
396 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));
397
398 if (static_branch_likely(&cr_pinning)) {
399 if (unlikely((val & cr4_pinned_bits) != cr4_pinned_bits)) {
400 bits_missing = ~val & cr4_pinned_bits;
401 val |= bits_missing;
402 goto set_register;
403 }
404 /* Warn after we've set the missing bits. */
405 WARN_ONCE(bits_missing, "CR4 bits went missing: %lx!?\n",
406 bits_missing);
407 }
408}
409EXPORT_SYMBOL(native_write_cr4);
410
411void cr4_init(void)
412{
413 unsigned long cr4 = __read_cr4();
414
415 if (boot_cpu_has(X86_FEATURE_PCID))
416 cr4 |= X86_CR4_PCIDE;
417 if (static_branch_likely(&cr_pinning))
418 cr4 |= cr4_pinned_bits;
419
420 __write_cr4(cr4);
421
422 /* Initialize cr4 shadow for this CPU. */
423 this_cpu_write(cpu_tlbstate.cr4, cr4);
424}
425
426/*
427 * Once CPU feature detection is finished (and boot params have been
428 * parsed), record any of the sensitive CR bits that are set, and
429 * enable CR pinning.
430 */
431static void __init setup_cr_pinning(void)
432{
433 unsigned long mask;
434
435 mask = (X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP);
436 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & mask;
437 static_key_enable(&cr_pinning.key);
438}
439
440/*
441 * Protection Keys are not available in 32-bit mode.
442 */
443static bool pku_disabled;
444
445static __always_inline void setup_pku(struct cpuinfo_x86 *c)
446{
447 struct pkru_state *pk;
448
449 /* check the boot processor, plus compile options for PKU: */
450 if (!cpu_feature_enabled(X86_FEATURE_PKU))
451 return;
452 /* checks the actual processor's cpuid bits: */
453 if (!cpu_has(c, X86_FEATURE_PKU))
454 return;
455 if (pku_disabled)
456 return;
457
458 cr4_set_bits(X86_CR4_PKE);
459 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
460 if (pk)
461 pk->pkru = init_pkru_value;
462 /*
463 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
464 * cpuid bit to be set. We need to ensure that we
465 * update that bit in this CPU's "cpu_info".
466 */
467 get_cpu_cap(c);
468}
469
470#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
471static __init int setup_disable_pku(char *arg)
472{
473 /*
474 * Do not clear the X86_FEATURE_PKU bit. All of the
475 * runtime checks are against OSPKE so clearing the
476 * bit does nothing.
477 *
478 * This way, we will see "pku" in cpuinfo, but not
479 * "ospke", which is exactly what we want. It shows
480 * that the CPU has PKU, but the OS has not enabled it.
481 * This happens to be exactly how a system would look
482 * if we disabled the config option.
483 */
484 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
485 pku_disabled = true;
486 return 1;
487}
488__setup("nopku", setup_disable_pku);
489#endif /* CONFIG_X86_64 */
490
491/*
492 * Some CPU features depend on higher CPUID levels, which may not always
493 * be available due to CPUID level capping or broken virtualization
494 * software. Add those features to this table to auto-disable them.
495 */
496struct cpuid_dependent_feature {
497 u32 feature;
498 u32 level;
499};
500
501static const struct cpuid_dependent_feature
502cpuid_dependent_features[] = {
503 { X86_FEATURE_MWAIT, 0x00000005 },
504 { X86_FEATURE_DCA, 0x00000009 },
505 { X86_FEATURE_XSAVE, 0x0000000d },
506 { 0, 0 }
507};
508
509static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
510{
511 const struct cpuid_dependent_feature *df;
512
513 for (df = cpuid_dependent_features; df->feature; df++) {
514
515 if (!cpu_has(c, df->feature))
516 continue;
517 /*
518 * Note: cpuid_level is set to -1 if unavailable, but
519 * extended_extended_level is set to 0 if unavailable
520 * and the legitimate extended levels are all negative
521 * when signed; hence the weird messing around with
522 * signs here...
523 */
524 if (!((s32)df->level < 0 ?
525 (u32)df->level > (u32)c->extended_cpuid_level :
526 (s32)df->level > (s32)c->cpuid_level))
527 continue;
528
529 clear_cpu_cap(c, df->feature);
530 if (!warn)
531 continue;
532
533 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
534 x86_cap_flag(df->feature), df->level);
535 }
536}
537
538/*
539 * Naming convention should be: <Name> [(<Codename>)]
540 * This table only is used unless init_<vendor>() below doesn't set it;
541 * in particular, if CPUID levels 0x80000002..4 are supported, this
542 * isn't used
543 */
544
545/* Look up CPU names by table lookup. */
546static const char *table_lookup_model(struct cpuinfo_x86 *c)
547{
548#ifdef CONFIG_X86_32
549 const struct legacy_cpu_model_info *info;
550
551 if (c->x86_model >= 16)
552 return NULL; /* Range check */
553
554 if (!this_cpu)
555 return NULL;
556
557 info = this_cpu->legacy_models;
558
559 while (info->family) {
560 if (info->family == c->x86)
561 return info->model_names[c->x86_model];
562 info++;
563 }
564#endif
565 return NULL; /* Not found */
566}
567
568__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
569__u32 cpu_caps_set[NCAPINTS + NBUGINTS];
570
571void load_percpu_segment(int cpu)
572{
573#ifdef CONFIG_X86_32
574 loadsegment(fs, __KERNEL_PERCPU);
575#else
576 __loadsegment_simple(gs, 0);
577 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
578#endif
579 load_stack_canary_segment();
580}
581
582#ifdef CONFIG_X86_32
583/* The 32-bit entry code needs to find cpu_entry_area. */
584DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
585#endif
586
587/* Load the original GDT from the per-cpu structure */
588void load_direct_gdt(int cpu)
589{
590 struct desc_ptr gdt_descr;
591
592 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
593 gdt_descr.size = GDT_SIZE - 1;
594 load_gdt(&gdt_descr);
595}
596EXPORT_SYMBOL_GPL(load_direct_gdt);
597
598/* Load a fixmap remapping of the per-cpu GDT */
599void load_fixmap_gdt(int cpu)
600{
601 struct desc_ptr gdt_descr;
602
603 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
604 gdt_descr.size = GDT_SIZE - 1;
605 load_gdt(&gdt_descr);
606}
607EXPORT_SYMBOL_GPL(load_fixmap_gdt);
608
609/*
610 * Current gdt points %fs at the "master" per-cpu area: after this,
611 * it's on the real one.
612 */
613void switch_to_new_gdt(int cpu)
614{
615 /* Load the original GDT */
616 load_direct_gdt(cpu);
617 /* Reload the per-cpu base */
618 load_percpu_segment(cpu);
619}
620
621static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
622
623static void get_model_name(struct cpuinfo_x86 *c)
624{
625 unsigned int *v;
626 char *p, *q, *s;
627
628 if (c->extended_cpuid_level < 0x80000004)
629 return;
630
631 v = (unsigned int *)c->x86_model_id;
632 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
633 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
634 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
635 c->x86_model_id[48] = 0;
636
637 /* Trim whitespace */
638 p = q = s = &c->x86_model_id[0];
639
640 while (*p == ' ')
641 p++;
642
643 while (*p) {
644 /* Note the last non-whitespace index */
645 if (!isspace(*p))
646 s = q;
647
648 *q++ = *p++;
649 }
650
651 *(s + 1) = '\0';
652}
653
654void detect_num_cpu_cores(struct cpuinfo_x86 *c)
655{
656 unsigned int eax, ebx, ecx, edx;
657
658 c->x86_max_cores = 1;
659 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
660 return;
661
662 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
663 if (eax & 0x1f)
664 c->x86_max_cores = (eax >> 26) + 1;
665}
666
667void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
668{
669 unsigned int n, dummy, ebx, ecx, edx, l2size;
670
671 n = c->extended_cpuid_level;
672
673 if (n >= 0x80000005) {
674 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
675 c->x86_cache_size = (ecx>>24) + (edx>>24);
676#ifdef CONFIG_X86_64
677 /* On K8 L1 TLB is inclusive, so don't count it */
678 c->x86_tlbsize = 0;
679#endif
680 }
681
682 if (n < 0x80000006) /* Some chips just has a large L1. */
683 return;
684
685 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
686 l2size = ecx >> 16;
687
688#ifdef CONFIG_X86_64
689 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
690#else
691 /* do processor-specific cache resizing */
692 if (this_cpu->legacy_cache_size)
693 l2size = this_cpu->legacy_cache_size(c, l2size);
694
695 /* Allow user to override all this if necessary. */
696 if (cachesize_override != -1)
697 l2size = cachesize_override;
698
699 if (l2size == 0)
700 return; /* Again, no L2 cache is possible */
701#endif
702
703 c->x86_cache_size = l2size;
704}
705
706u16 __read_mostly tlb_lli_4k[NR_INFO];
707u16 __read_mostly tlb_lli_2m[NR_INFO];
708u16 __read_mostly tlb_lli_4m[NR_INFO];
709u16 __read_mostly tlb_lld_4k[NR_INFO];
710u16 __read_mostly tlb_lld_2m[NR_INFO];
711u16 __read_mostly tlb_lld_4m[NR_INFO];
712u16 __read_mostly tlb_lld_1g[NR_INFO];
713
714static void cpu_detect_tlb(struct cpuinfo_x86 *c)
715{
716 if (this_cpu->c_detect_tlb)
717 this_cpu->c_detect_tlb(c);
718
719 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
720 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
721 tlb_lli_4m[ENTRIES]);
722
723 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
724 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
725 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
726}
727
728int detect_ht_early(struct cpuinfo_x86 *c)
729{
730#ifdef CONFIG_SMP
731 u32 eax, ebx, ecx, edx;
732
733 if (!cpu_has(c, X86_FEATURE_HT))
734 return -1;
735
736 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
737 return -1;
738
739 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
740 return -1;
741
742 cpuid(1, &eax, &ebx, &ecx, &edx);
743
744 smp_num_siblings = (ebx & 0xff0000) >> 16;
745 if (smp_num_siblings == 1)
746 pr_info_once("CPU0: Hyper-Threading is disabled\n");
747#endif
748 return 0;
749}
750
751void detect_ht(struct cpuinfo_x86 *c)
752{
753#ifdef CONFIG_SMP
754 int index_msb, core_bits;
755
756 if (detect_ht_early(c) < 0)
757 return;
758
759 index_msb = get_count_order(smp_num_siblings);
760 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
761
762 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
763
764 index_msb = get_count_order(smp_num_siblings);
765
766 core_bits = get_count_order(c->x86_max_cores);
767
768 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
769 ((1 << core_bits) - 1);
770#endif
771}
772
773static void get_cpu_vendor(struct cpuinfo_x86 *c)
774{
775 char *v = c->x86_vendor_id;
776 int i;
777
778 for (i = 0; i < X86_VENDOR_NUM; i++) {
779 if (!cpu_devs[i])
780 break;
781
782 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
783 (cpu_devs[i]->c_ident[1] &&
784 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
785
786 this_cpu = cpu_devs[i];
787 c->x86_vendor = this_cpu->c_x86_vendor;
788 return;
789 }
790 }
791
792 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
793 "CPU: Your system may be unstable.\n", v);
794
795 c->x86_vendor = X86_VENDOR_UNKNOWN;
796 this_cpu = &default_cpu;
797}
798
799void cpu_detect(struct cpuinfo_x86 *c)
800{
801 /* Get vendor name */
802 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
803 (unsigned int *)&c->x86_vendor_id[0],
804 (unsigned int *)&c->x86_vendor_id[8],
805 (unsigned int *)&c->x86_vendor_id[4]);
806
807 c->x86 = 4;
808 /* Intel-defined flags: level 0x00000001 */
809 if (c->cpuid_level >= 0x00000001) {
810 u32 junk, tfms, cap0, misc;
811
812 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
813 c->x86 = x86_family(tfms);
814 c->x86_model = x86_model(tfms);
815 c->x86_stepping = x86_stepping(tfms);
816
817 if (cap0 & (1<<19)) {
818 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
819 c->x86_cache_alignment = c->x86_clflush_size;
820 }
821 }
822}
823
824static void apply_forced_caps(struct cpuinfo_x86 *c)
825{
826 int i;
827
828 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
829 c->x86_capability[i] &= ~cpu_caps_cleared[i];
830 c->x86_capability[i] |= cpu_caps_set[i];
831 }
832}
833
834static void init_speculation_control(struct cpuinfo_x86 *c)
835{
836 /*
837 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
838 * and they also have a different bit for STIBP support. Also,
839 * a hypervisor might have set the individual AMD bits even on
840 * Intel CPUs, for finer-grained selection of what's available.
841 */
842 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
843 set_cpu_cap(c, X86_FEATURE_IBRS);
844 set_cpu_cap(c, X86_FEATURE_IBPB);
845 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
846 }
847
848 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
849 set_cpu_cap(c, X86_FEATURE_STIBP);
850
851 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
852 cpu_has(c, X86_FEATURE_VIRT_SSBD))
853 set_cpu_cap(c, X86_FEATURE_SSBD);
854
855 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
856 set_cpu_cap(c, X86_FEATURE_IBRS);
857 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
858 }
859
860 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
861 set_cpu_cap(c, X86_FEATURE_IBPB);
862
863 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
864 set_cpu_cap(c, X86_FEATURE_STIBP);
865 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
866 }
867
868 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
869 set_cpu_cap(c, X86_FEATURE_SSBD);
870 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
871 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
872 }
873}
874
875static void init_cqm(struct cpuinfo_x86 *c)
876{
877 if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
878 c->x86_cache_max_rmid = -1;
879 c->x86_cache_occ_scale = -1;
880 return;
881 }
882
883 /* will be overridden if occupancy monitoring exists */
884 c->x86_cache_max_rmid = cpuid_ebx(0xf);
885
886 if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) ||
887 cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) ||
888 cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) {
889 u32 eax, ebx, ecx, edx;
890
891 /* QoS sub-leaf, EAX=0Fh, ECX=1 */
892 cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx);
893
894 c->x86_cache_max_rmid = ecx;
895 c->x86_cache_occ_scale = ebx;
896 }
897}
898
899void get_cpu_cap(struct cpuinfo_x86 *c)
900{
901 u32 eax, ebx, ecx, edx;
902
903 /* Intel-defined flags: level 0x00000001 */
904 if (c->cpuid_level >= 0x00000001) {
905 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
906
907 c->x86_capability[CPUID_1_ECX] = ecx;
908 c->x86_capability[CPUID_1_EDX] = edx;
909 }
910
911 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
912 if (c->cpuid_level >= 0x00000006)
913 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
914
915 /* Additional Intel-defined flags: level 0x00000007 */
916 if (c->cpuid_level >= 0x00000007) {
917 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
918 c->x86_capability[CPUID_7_0_EBX] = ebx;
919 c->x86_capability[CPUID_7_ECX] = ecx;
920 c->x86_capability[CPUID_7_EDX] = edx;
921
922 /* Check valid sub-leaf index before accessing it */
923 if (eax >= 1) {
924 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
925 c->x86_capability[CPUID_7_1_EAX] = eax;
926 }
927 }
928
929 /* Extended state features: level 0x0000000d */
930 if (c->cpuid_level >= 0x0000000d) {
931 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
932
933 c->x86_capability[CPUID_D_1_EAX] = eax;
934 }
935
936 /* AMD-defined flags: level 0x80000001 */
937 eax = cpuid_eax(0x80000000);
938 c->extended_cpuid_level = eax;
939
940 if ((eax & 0xffff0000) == 0x80000000) {
941 if (eax >= 0x80000001) {
942 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
943
944 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
945 c->x86_capability[CPUID_8000_0001_EDX] = edx;
946 }
947 }
948
949 if (c->extended_cpuid_level >= 0x80000007) {
950 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
951
952 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
953 c->x86_power = edx;
954 }
955
956 if (c->extended_cpuid_level >= 0x80000008) {
957 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
958 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
959 }
960
961 if (c->extended_cpuid_level >= 0x8000000a)
962 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
963
964 init_scattered_cpuid_features(c);
965 init_speculation_control(c);
966 init_cqm(c);
967
968 /*
969 * Clear/Set all flags overridden by options, after probe.
970 * This needs to happen each time we re-probe, which may happen
971 * several times during CPU initialization.
972 */
973 apply_forced_caps(c);
974}
975
976void get_cpu_address_sizes(struct cpuinfo_x86 *c)
977{
978 u32 eax, ebx, ecx, edx;
979
980 if (c->extended_cpuid_level >= 0x80000008) {
981 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
982
983 c->x86_virt_bits = (eax >> 8) & 0xff;
984 c->x86_phys_bits = eax & 0xff;
985 }
986#ifdef CONFIG_X86_32
987 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
988 c->x86_phys_bits = 36;
989#endif
990 c->x86_cache_bits = c->x86_phys_bits;
991}
992
993static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
994{
995#ifdef CONFIG_X86_32
996 int i;
997
998 /*
999 * First of all, decide if this is a 486 or higher
1000 * It's a 486 if we can modify the AC flag
1001 */
1002 if (flag_is_changeable_p(X86_EFLAGS_AC))
1003 c->x86 = 4;
1004 else
1005 c->x86 = 3;
1006
1007 for (i = 0; i < X86_VENDOR_NUM; i++)
1008 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1009 c->x86_vendor_id[0] = 0;
1010 cpu_devs[i]->c_identify(c);
1011 if (c->x86_vendor_id[0]) {
1012 get_cpu_vendor(c);
1013 break;
1014 }
1015 }
1016#endif
1017}
1018
1019#define NO_SPECULATION BIT(0)
1020#define NO_MELTDOWN BIT(1)
1021#define NO_SSB BIT(2)
1022#define NO_L1TF BIT(3)
1023#define NO_MDS BIT(4)
1024#define MSBDS_ONLY BIT(5)
1025#define NO_SWAPGS BIT(6)
1026#define NO_ITLB_MULTIHIT BIT(7)
1027
1028#define VULNWL(_vendor, _family, _model, _whitelist) \
1029 { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist }
1030
1031#define VULNWL_INTEL(model, whitelist) \
1032 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1033
1034#define VULNWL_AMD(family, whitelist) \
1035 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1036
1037#define VULNWL_HYGON(family, whitelist) \
1038 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1039
1040static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1041 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1042 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1043 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1044 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1045
1046 /* Intel Family 6 */
1047 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1048 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1049 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1050 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1051 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1052
1053 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1054 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1055 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1056 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1057 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1058 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1059
1060 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1061
1062 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1063 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1064
1065 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1066 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1067 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1068
1069 /*
1070 * Technically, swapgs isn't serializing on AMD (despite it previously
1071 * being documented as such in the APM). But according to AMD, %gs is
1072 * updated non-speculatively, and the issuing of %gs-relative memory
1073 * operands will be blocked until the %gs update completes, which is
1074 * good enough for our purposes.
1075 */
1076
1077 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1078
1079 /* AMD Family 0xf - 0x12 */
1080 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1081 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1083 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1084
1085 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1086 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1087 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1088 {}
1089};
1090
1091static bool __init cpu_matches(unsigned long which)
1092{
1093 const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist);
1094
1095 return m && !!(m->driver_data & which);
1096}
1097
1098u64 x86_read_arch_cap_msr(void)
1099{
1100 u64 ia32_cap = 0;
1101
1102 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1103 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1104
1105 return ia32_cap;
1106}
1107
1108static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1109{
1110 u64 ia32_cap = x86_read_arch_cap_msr();
1111
1112 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1113 if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1114 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1115
1116 if (cpu_matches(NO_SPECULATION))
1117 return;
1118
1119 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1120 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1121
1122 if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) &&
1123 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1124 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1125
1126 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1127 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1128
1129 if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) {
1130 setup_force_cpu_bug(X86_BUG_MDS);
1131 if (cpu_matches(MSBDS_ONLY))
1132 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1133 }
1134
1135 if (!cpu_matches(NO_SWAPGS))
1136 setup_force_cpu_bug(X86_BUG_SWAPGS);
1137
1138 /*
1139 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1140 * - TSX is supported or
1141 * - TSX_CTRL is present
1142 *
1143 * TSX_CTRL check is needed for cases when TSX could be disabled before
1144 * the kernel boot e.g. kexec.
1145 * TSX_CTRL check alone is not sufficient for cases when the microcode
1146 * update is not present or running as guest that don't get TSX_CTRL.
1147 */
1148 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1149 (cpu_has(c, X86_FEATURE_RTM) ||
1150 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1151 setup_force_cpu_bug(X86_BUG_TAA);
1152
1153 if (cpu_matches(NO_MELTDOWN))
1154 return;
1155
1156 /* Rogue Data Cache Load? No! */
1157 if (ia32_cap & ARCH_CAP_RDCL_NO)
1158 return;
1159
1160 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1161
1162 if (cpu_matches(NO_L1TF))
1163 return;
1164
1165 setup_force_cpu_bug(X86_BUG_L1TF);
1166}
1167
1168/*
1169 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1170 * unfortunately, that's not true in practice because of early VIA
1171 * chips and (more importantly) broken virtualizers that are not easy
1172 * to detect. In the latter case it doesn't even *fail* reliably, so
1173 * probing for it doesn't even work. Disable it completely on 32-bit
1174 * unless we can find a reliable way to detect all the broken cases.
1175 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1176 */
1177static void detect_nopl(void)
1178{
1179#ifdef CONFIG_X86_32
1180 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1181#else
1182 setup_force_cpu_cap(X86_FEATURE_NOPL);
1183#endif
1184}
1185
1186/*
1187 * Do minimum CPU detection early.
1188 * Fields really needed: vendor, cpuid_level, family, model, mask,
1189 * cache alignment.
1190 * The others are not touched to avoid unwanted side effects.
1191 *
1192 * WARNING: this function is only called on the boot CPU. Don't add code
1193 * here that is supposed to run on all CPUs.
1194 */
1195static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1196{
1197#ifdef CONFIG_X86_64
1198 c->x86_clflush_size = 64;
1199 c->x86_phys_bits = 36;
1200 c->x86_virt_bits = 48;
1201#else
1202 c->x86_clflush_size = 32;
1203 c->x86_phys_bits = 32;
1204 c->x86_virt_bits = 32;
1205#endif
1206 c->x86_cache_alignment = c->x86_clflush_size;
1207
1208 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1209 c->extended_cpuid_level = 0;
1210
1211 if (!have_cpuid_p())
1212 identify_cpu_without_cpuid(c);
1213
1214 /* cyrix could have cpuid enabled via c_identify()*/
1215 if (have_cpuid_p()) {
1216 cpu_detect(c);
1217 get_cpu_vendor(c);
1218 get_cpu_cap(c);
1219 get_cpu_address_sizes(c);
1220 setup_force_cpu_cap(X86_FEATURE_CPUID);
1221
1222 if (this_cpu->c_early_init)
1223 this_cpu->c_early_init(c);
1224
1225 c->cpu_index = 0;
1226 filter_cpuid_features(c, false);
1227
1228 if (this_cpu->c_bsp_init)
1229 this_cpu->c_bsp_init(c);
1230 } else {
1231 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1232 }
1233
1234 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1235
1236 cpu_set_bug_bits(c);
1237
1238 fpu__init_system(c);
1239
1240#ifdef CONFIG_X86_32
1241 /*
1242 * Regardless of whether PCID is enumerated, the SDM says
1243 * that it can't be enabled in 32-bit mode.
1244 */
1245 setup_clear_cpu_cap(X86_FEATURE_PCID);
1246#endif
1247
1248 /*
1249 * Later in the boot process pgtable_l5_enabled() relies on
1250 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1251 * enabled by this point we need to clear the feature bit to avoid
1252 * false-positives at the later stage.
1253 *
1254 * pgtable_l5_enabled() can be false here for several reasons:
1255 * - 5-level paging is disabled compile-time;
1256 * - it's 32-bit kernel;
1257 * - machine doesn't support 5-level paging;
1258 * - user specified 'no5lvl' in kernel command line.
1259 */
1260 if (!pgtable_l5_enabled())
1261 setup_clear_cpu_cap(X86_FEATURE_LA57);
1262
1263 detect_nopl();
1264}
1265
1266void __init early_cpu_init(void)
1267{
1268 const struct cpu_dev *const *cdev;
1269 int count = 0;
1270
1271#ifdef CONFIG_PROCESSOR_SELECT
1272 pr_info("KERNEL supported cpus:\n");
1273#endif
1274
1275 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1276 const struct cpu_dev *cpudev = *cdev;
1277
1278 if (count >= X86_VENDOR_NUM)
1279 break;
1280 cpu_devs[count] = cpudev;
1281 count++;
1282
1283#ifdef CONFIG_PROCESSOR_SELECT
1284 {
1285 unsigned int j;
1286
1287 for (j = 0; j < 2; j++) {
1288 if (!cpudev->c_ident[j])
1289 continue;
1290 pr_info(" %s %s\n", cpudev->c_vendor,
1291 cpudev->c_ident[j]);
1292 }
1293 }
1294#endif
1295 }
1296 early_identify_cpu(&boot_cpu_data);
1297}
1298
1299static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1300{
1301#ifdef CONFIG_X86_64
1302 /*
1303 * Empirically, writing zero to a segment selector on AMD does
1304 * not clear the base, whereas writing zero to a segment
1305 * selector on Intel does clear the base. Intel's behavior
1306 * allows slightly faster context switches in the common case
1307 * where GS is unused by the prev and next threads.
1308 *
1309 * Since neither vendor documents this anywhere that I can see,
1310 * detect it directly instead of hardcoding the choice by
1311 * vendor.
1312 *
1313 * I've designated AMD's behavior as the "bug" because it's
1314 * counterintuitive and less friendly.
1315 */
1316
1317 unsigned long old_base, tmp;
1318 rdmsrl(MSR_FS_BASE, old_base);
1319 wrmsrl(MSR_FS_BASE, 1);
1320 loadsegment(fs, 0);
1321 rdmsrl(MSR_FS_BASE, tmp);
1322 if (tmp != 0)
1323 set_cpu_bug(c, X86_BUG_NULL_SEG);
1324 wrmsrl(MSR_FS_BASE, old_base);
1325#endif
1326}
1327
1328static void generic_identify(struct cpuinfo_x86 *c)
1329{
1330 c->extended_cpuid_level = 0;
1331
1332 if (!have_cpuid_p())
1333 identify_cpu_without_cpuid(c);
1334
1335 /* cyrix could have cpuid enabled via c_identify()*/
1336 if (!have_cpuid_p())
1337 return;
1338
1339 cpu_detect(c);
1340
1341 get_cpu_vendor(c);
1342
1343 get_cpu_cap(c);
1344
1345 get_cpu_address_sizes(c);
1346
1347 if (c->cpuid_level >= 0x00000001) {
1348 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1349#ifdef CONFIG_X86_32
1350# ifdef CONFIG_SMP
1351 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1352# else
1353 c->apicid = c->initial_apicid;
1354# endif
1355#endif
1356 c->phys_proc_id = c->initial_apicid;
1357 }
1358
1359 get_model_name(c); /* Default name */
1360
1361 detect_null_seg_behavior(c);
1362
1363 /*
1364 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1365 * systems that run Linux at CPL > 0 may or may not have the
1366 * issue, but, even if they have the issue, there's absolutely
1367 * nothing we can do about it because we can't use the real IRET
1368 * instruction.
1369 *
1370 * NB: For the time being, only 32-bit kernels support
1371 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1372 * whether to apply espfix using paravirt hooks. If any
1373 * non-paravirt system ever shows up that does *not* have the
1374 * ESPFIX issue, we can change this.
1375 */
1376#ifdef CONFIG_X86_32
1377# ifdef CONFIG_PARAVIRT_XXL
1378 do {
1379 extern void native_iret(void);
1380 if (pv_ops.cpu.iret == native_iret)
1381 set_cpu_bug(c, X86_BUG_ESPFIX);
1382 } while (0);
1383# else
1384 set_cpu_bug(c, X86_BUG_ESPFIX);
1385# endif
1386#endif
1387}
1388
1389static void x86_init_cache_qos(struct cpuinfo_x86 *c)
1390{
1391 /*
1392 * The heavy lifting of max_rmid and cache_occ_scale are handled
1393 * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu
1394 * in case CQM bits really aren't there in this CPU.
1395 */
1396 if (c != &boot_cpu_data) {
1397 boot_cpu_data.x86_cache_max_rmid =
1398 min(boot_cpu_data.x86_cache_max_rmid,
1399 c->x86_cache_max_rmid);
1400 }
1401}
1402
1403/*
1404 * Validate that ACPI/mptables have the same information about the
1405 * effective APIC id and update the package map.
1406 */
1407static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1408{
1409#ifdef CONFIG_SMP
1410 unsigned int apicid, cpu = smp_processor_id();
1411
1412 apicid = apic->cpu_present_to_apicid(cpu);
1413
1414 if (apicid != c->apicid) {
1415 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1416 cpu, apicid, c->initial_apicid);
1417 }
1418 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1419 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1420#else
1421 c->logical_proc_id = 0;
1422#endif
1423}
1424
1425/*
1426 * This does the hard work of actually picking apart the CPU stuff...
1427 */
1428static void identify_cpu(struct cpuinfo_x86 *c)
1429{
1430 int i;
1431
1432 c->loops_per_jiffy = loops_per_jiffy;
1433 c->x86_cache_size = 0;
1434 c->x86_vendor = X86_VENDOR_UNKNOWN;
1435 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1436 c->x86_vendor_id[0] = '\0'; /* Unset */
1437 c->x86_model_id[0] = '\0'; /* Unset */
1438 c->x86_max_cores = 1;
1439 c->x86_coreid_bits = 0;
1440 c->cu_id = 0xff;
1441#ifdef CONFIG_X86_64
1442 c->x86_clflush_size = 64;
1443 c->x86_phys_bits = 36;
1444 c->x86_virt_bits = 48;
1445#else
1446 c->cpuid_level = -1; /* CPUID not detected */
1447 c->x86_clflush_size = 32;
1448 c->x86_phys_bits = 32;
1449 c->x86_virt_bits = 32;
1450#endif
1451 c->x86_cache_alignment = c->x86_clflush_size;
1452 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1453
1454 generic_identify(c);
1455
1456 if (this_cpu->c_identify)
1457 this_cpu->c_identify(c);
1458
1459 /* Clear/Set all flags overridden by options, after probe */
1460 apply_forced_caps(c);
1461
1462#ifdef CONFIG_X86_64
1463 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1464#endif
1465
1466 /*
1467 * Vendor-specific initialization. In this section we
1468 * canonicalize the feature flags, meaning if there are
1469 * features a certain CPU supports which CPUID doesn't
1470 * tell us, CPUID claiming incorrect flags, or other bugs,
1471 * we handle them here.
1472 *
1473 * At the end of this section, c->x86_capability better
1474 * indicate the features this CPU genuinely supports!
1475 */
1476 if (this_cpu->c_init)
1477 this_cpu->c_init(c);
1478
1479 /* Disable the PN if appropriate */
1480 squash_the_stupid_serial_number(c);
1481
1482 /* Set up SMEP/SMAP/UMIP */
1483 setup_smep(c);
1484 setup_smap(c);
1485 setup_umip(c);
1486
1487 /*
1488 * The vendor-specific functions might have changed features.
1489 * Now we do "generic changes."
1490 */
1491
1492 /* Filter out anything that depends on CPUID levels we don't have */
1493 filter_cpuid_features(c, true);
1494
1495 /* If the model name is still unset, do table lookup. */
1496 if (!c->x86_model_id[0]) {
1497 const char *p;
1498 p = table_lookup_model(c);
1499 if (p)
1500 strcpy(c->x86_model_id, p);
1501 else
1502 /* Last resort... */
1503 sprintf(c->x86_model_id, "%02x/%02x",
1504 c->x86, c->x86_model);
1505 }
1506
1507#ifdef CONFIG_X86_64
1508 detect_ht(c);
1509#endif
1510
1511 x86_init_rdrand(c);
1512 x86_init_cache_qos(c);
1513 setup_pku(c);
1514
1515 /*
1516 * Clear/Set all flags overridden by options, need do it
1517 * before following smp all cpus cap AND.
1518 */
1519 apply_forced_caps(c);
1520
1521 /*
1522 * On SMP, boot_cpu_data holds the common feature set between
1523 * all CPUs; so make sure that we indicate which features are
1524 * common between the CPUs. The first time this routine gets
1525 * executed, c == &boot_cpu_data.
1526 */
1527 if (c != &boot_cpu_data) {
1528 /* AND the already accumulated flags with these */
1529 for (i = 0; i < NCAPINTS; i++)
1530 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1531
1532 /* OR, i.e. replicate the bug flags */
1533 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1534 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1535 }
1536
1537 /* Init Machine Check Exception if available. */
1538 mcheck_cpu_init(c);
1539
1540 select_idle_routine(c);
1541
1542#ifdef CONFIG_NUMA
1543 numa_add_cpu(smp_processor_id());
1544#endif
1545}
1546
1547/*
1548 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1549 * on 32-bit kernels:
1550 */
1551#ifdef CONFIG_X86_32
1552void enable_sep_cpu(void)
1553{
1554 struct tss_struct *tss;
1555 int cpu;
1556
1557 if (!boot_cpu_has(X86_FEATURE_SEP))
1558 return;
1559
1560 cpu = get_cpu();
1561 tss = &per_cpu(cpu_tss_rw, cpu);
1562
1563 /*
1564 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1565 * see the big comment in struct x86_hw_tss's definition.
1566 */
1567
1568 tss->x86_tss.ss1 = __KERNEL_CS;
1569 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1570 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1571 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1572
1573 put_cpu();
1574}
1575#endif
1576
1577void __init identify_boot_cpu(void)
1578{
1579 identify_cpu(&boot_cpu_data);
1580#ifdef CONFIG_X86_32
1581 sysenter_setup();
1582 enable_sep_cpu();
1583#endif
1584 cpu_detect_tlb(&boot_cpu_data);
1585 setup_cr_pinning();
1586
1587 tsx_init();
1588}
1589
1590void identify_secondary_cpu(struct cpuinfo_x86 *c)
1591{
1592 BUG_ON(c == &boot_cpu_data);
1593 identify_cpu(c);
1594#ifdef CONFIG_X86_32
1595 enable_sep_cpu();
1596#endif
1597 mtrr_ap_init();
1598 validate_apic_and_package_id(c);
1599 x86_spec_ctrl_setup_ap();
1600}
1601
1602static __init int setup_noclflush(char *arg)
1603{
1604 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1605 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1606 return 1;
1607}
1608__setup("noclflush", setup_noclflush);
1609
1610void print_cpu_info(struct cpuinfo_x86 *c)
1611{
1612 const char *vendor = NULL;
1613
1614 if (c->x86_vendor < X86_VENDOR_NUM) {
1615 vendor = this_cpu->c_vendor;
1616 } else {
1617 if (c->cpuid_level >= 0)
1618 vendor = c->x86_vendor_id;
1619 }
1620
1621 if (vendor && !strstr(c->x86_model_id, vendor))
1622 pr_cont("%s ", vendor);
1623
1624 if (c->x86_model_id[0])
1625 pr_cont("%s", c->x86_model_id);
1626 else
1627 pr_cont("%d86", c->x86);
1628
1629 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1630
1631 if (c->x86_stepping || c->cpuid_level >= 0)
1632 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1633 else
1634 pr_cont(")\n");
1635}
1636
1637/*
1638 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1639 * But we need to keep a dummy __setup around otherwise it would
1640 * show up as an environment variable for init.
1641 */
1642static __init int setup_clearcpuid(char *arg)
1643{
1644 return 1;
1645}
1646__setup("clearcpuid=", setup_clearcpuid);
1647
1648#ifdef CONFIG_X86_64
1649DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1650 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1651EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1652
1653/*
1654 * The following percpu variables are hot. Align current_task to
1655 * cacheline size such that they fall in the same cacheline.
1656 */
1657DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1658 &init_task;
1659EXPORT_PER_CPU_SYMBOL(current_task);
1660
1661DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1662DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1663
1664DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1665EXPORT_PER_CPU_SYMBOL(__preempt_count);
1666
1667/* May not be marked __init: used by software suspend */
1668void syscall_init(void)
1669{
1670 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1671 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1672
1673#ifdef CONFIG_IA32_EMULATION
1674 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1675 /*
1676 * This only works on Intel CPUs.
1677 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1678 * This does not cause SYSENTER to jump to the wrong location, because
1679 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1680 */
1681 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1682 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1683 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1684 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1685#else
1686 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1687 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1688 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1689 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1690#endif
1691
1692 /* Flags to clear on syscall */
1693 wrmsrl(MSR_SYSCALL_MASK,
1694 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1695 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1696}
1697
1698DEFINE_PER_CPU(int, debug_stack_usage);
1699DEFINE_PER_CPU(u32, debug_idt_ctr);
1700
1701void debug_stack_set_zero(void)
1702{
1703 this_cpu_inc(debug_idt_ctr);
1704 load_current_idt();
1705}
1706NOKPROBE_SYMBOL(debug_stack_set_zero);
1707
1708void debug_stack_reset(void)
1709{
1710 if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1711 return;
1712 if (this_cpu_dec_return(debug_idt_ctr) == 0)
1713 load_current_idt();
1714}
1715NOKPROBE_SYMBOL(debug_stack_reset);
1716
1717#else /* CONFIG_X86_64 */
1718
1719DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1720EXPORT_PER_CPU_SYMBOL(current_task);
1721DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1722EXPORT_PER_CPU_SYMBOL(__preempt_count);
1723
1724/*
1725 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1726 * the top of the kernel stack. Use an extra percpu variable to track the
1727 * top of the kernel stack directly.
1728 */
1729DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1730 (unsigned long)&init_thread_union + THREAD_SIZE;
1731EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1732
1733#ifdef CONFIG_STACKPROTECTOR
1734DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1735#endif
1736
1737#endif /* CONFIG_X86_64 */
1738
1739/*
1740 * Clear all 6 debug registers:
1741 */
1742static void clear_all_debug_regs(void)
1743{
1744 int i;
1745
1746 for (i = 0; i < 8; i++) {
1747 /* Ignore db4, db5 */
1748 if ((i == 4) || (i == 5))
1749 continue;
1750
1751 set_debugreg(0, i);
1752 }
1753}
1754
1755#ifdef CONFIG_KGDB
1756/*
1757 * Restore debug regs if using kgdbwait and you have a kernel debugger
1758 * connection established.
1759 */
1760static void dbg_restore_debug_regs(void)
1761{
1762 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1763 arch_kgdb_ops.correct_hw_break();
1764}
1765#else /* ! CONFIG_KGDB */
1766#define dbg_restore_debug_regs()
1767#endif /* ! CONFIG_KGDB */
1768
1769static void wait_for_master_cpu(int cpu)
1770{
1771#ifdef CONFIG_SMP
1772 /*
1773 * wait for ACK from master CPU before continuing
1774 * with AP initialization
1775 */
1776 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1777 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1778 cpu_relax();
1779#endif
1780}
1781
1782#ifdef CONFIG_X86_64
1783static void setup_getcpu(int cpu)
1784{
1785 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1786 struct desc_struct d = { };
1787
1788 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1789 write_rdtscp_aux(cpudata);
1790
1791 /* Store CPU and node number in limit. */
1792 d.limit0 = cpudata;
1793 d.limit1 = cpudata >> 16;
1794
1795 d.type = 5; /* RO data, expand down, accessed */
1796 d.dpl = 3; /* Visible to user code */
1797 d.s = 1; /* Not a system segment */
1798 d.p = 1; /* Present */
1799 d.d = 1; /* 32-bit */
1800
1801 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1802}
1803#endif
1804
1805/*
1806 * cpu_init() initializes state that is per-CPU. Some data is already
1807 * initialized (naturally) in the bootstrap process, such as the GDT
1808 * and IDT. We reload them nevertheless, this function acts as a
1809 * 'CPU state barrier', nothing should get across.
1810 */
1811#ifdef CONFIG_X86_64
1812
1813void cpu_init(void)
1814{
1815 int cpu = raw_smp_processor_id();
1816 struct task_struct *me;
1817 struct tss_struct *t;
1818 int i;
1819
1820 wait_for_master_cpu(cpu);
1821
1822 if (cpu)
1823 load_ucode_ap();
1824
1825 t = &per_cpu(cpu_tss_rw, cpu);
1826
1827#ifdef CONFIG_NUMA
1828 if (this_cpu_read(numa_node) == 0 &&
1829 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1830 set_numa_node(early_cpu_to_node(cpu));
1831#endif
1832 setup_getcpu(cpu);
1833
1834 me = current;
1835
1836 pr_debug("Initializing CPU#%d\n", cpu);
1837
1838 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1839
1840 /*
1841 * Initialize the per-CPU GDT with the boot GDT,
1842 * and set up the GDT descriptor:
1843 */
1844
1845 switch_to_new_gdt(cpu);
1846 loadsegment(fs, 0);
1847
1848 load_current_idt();
1849
1850 memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1851 syscall_init();
1852
1853 wrmsrl(MSR_FS_BASE, 0);
1854 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1855 barrier();
1856
1857 x86_configure_nx();
1858 x2apic_setup();
1859
1860 /*
1861 * set up and load the per-CPU TSS
1862 */
1863 if (!t->x86_tss.ist[0]) {
1864 t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1865 t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1866 t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1867 t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1868 }
1869
1870 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1871
1872 /*
1873 * <= is required because the CPU will access up to
1874 * 8 bits beyond the end of the IO permission bitmap.
1875 */
1876 for (i = 0; i <= IO_BITMAP_LONGS; i++)
1877 t->io_bitmap[i] = ~0UL;
1878
1879 mmgrab(&init_mm);
1880 me->active_mm = &init_mm;
1881 BUG_ON(me->mm);
1882 initialize_tlbstate_and_flush();
1883 enter_lazy_tlb(&init_mm, me);
1884
1885 /*
1886 * Initialize the TSS. sp0 points to the entry trampoline stack
1887 * regardless of what task is running.
1888 */
1889 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1890 load_TR_desc();
1891 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1892
1893 load_mm_ldt(&init_mm);
1894
1895 clear_all_debug_regs();
1896 dbg_restore_debug_regs();
1897
1898 fpu__init_cpu();
1899
1900 if (is_uv_system())
1901 uv_cpu_init();
1902
1903 load_fixmap_gdt(cpu);
1904}
1905
1906#else
1907
1908void cpu_init(void)
1909{
1910 int cpu = smp_processor_id();
1911 struct task_struct *curr = current;
1912 struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu);
1913
1914 wait_for_master_cpu(cpu);
1915
1916 show_ucode_info_early();
1917
1918 pr_info("Initializing CPU#%d\n", cpu);
1919
1920 if (cpu_feature_enabled(X86_FEATURE_VME) ||
1921 boot_cpu_has(X86_FEATURE_TSC) ||
1922 boot_cpu_has(X86_FEATURE_DE))
1923 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1924
1925 load_current_idt();
1926 switch_to_new_gdt(cpu);
1927
1928 /*
1929 * Set up and load the per-CPU TSS and LDT
1930 */
1931 mmgrab(&init_mm);
1932 curr->active_mm = &init_mm;
1933 BUG_ON(curr->mm);
1934 initialize_tlbstate_and_flush();
1935 enter_lazy_tlb(&init_mm, curr);
1936
1937 /*
1938 * Initialize the TSS. sp0 points to the entry trampoline stack
1939 * regardless of what task is running.
1940 */
1941 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1942 load_TR_desc();
1943 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1944
1945 load_mm_ldt(&init_mm);
1946
1947 t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
1948
1949#ifdef CONFIG_DOUBLEFAULT
1950 /* Set up doublefault TSS pointer in the GDT */
1951 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1952#endif
1953
1954 clear_all_debug_regs();
1955 dbg_restore_debug_regs();
1956
1957 fpu__init_cpu();
1958
1959 load_fixmap_gdt(cpu);
1960}
1961#endif
1962
1963/*
1964 * The microcode loader calls this upon late microcode load to recheck features,
1965 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1966 * hotplug lock.
1967 */
1968void microcode_check(void)
1969{
1970 struct cpuinfo_x86 info;
1971
1972 perf_check_microcode();
1973
1974 /* Reload CPUID max function as it might've changed. */
1975 info.cpuid_level = cpuid_eax(0);
1976
1977 /*
1978 * Copy all capability leafs to pick up the synthetic ones so that
1979 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1980 * get overwritten in get_cpu_cap().
1981 */
1982 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1983
1984 get_cpu_cap(&info);
1985
1986 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1987 return;
1988
1989 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1990 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1991}
1992
1993/*
1994 * Invoked from core CPU hotplug code after hotplug operations
1995 */
1996void arch_smt_update(void)
1997{
1998 /* Handle the speculative execution misfeatures */
1999 cpu_bugs_smt_update();
2000 /* Check whether IPI broadcasting can be enabled */
2001 apic_smt_update();
2002}
1// SPDX-License-Identifier: GPL-2.0-only
2/* cpu_feature_enabled() cannot be used this early */
3#define USE_EARLY_PGTABLE_L5
4
5#include <linux/memblock.h>
6#include <linux/linkage.h>
7#include <linux/bitops.h>
8#include <linux/kernel.h>
9#include <linux/export.h>
10#include <linux/percpu.h>
11#include <linux/string.h>
12#include <linux/ctype.h>
13#include <linux/delay.h>
14#include <linux/sched/mm.h>
15#include <linux/sched/clock.h>
16#include <linux/sched/task.h>
17#include <linux/sched/smt.h>
18#include <linux/init.h>
19#include <linux/kprobes.h>
20#include <linux/kgdb.h>
21#include <linux/smp.h>
22#include <linux/io.h>
23#include <linux/syscore_ops.h>
24#include <linux/pgtable.h>
25
26#include <asm/stackprotector.h>
27#include <asm/perf_event.h>
28#include <asm/mmu_context.h>
29#include <asm/doublefault.h>
30#include <asm/archrandom.h>
31#include <asm/hypervisor.h>
32#include <asm/processor.h>
33#include <asm/tlbflush.h>
34#include <asm/debugreg.h>
35#include <asm/sections.h>
36#include <asm/vsyscall.h>
37#include <linux/topology.h>
38#include <linux/cpumask.h>
39#include <linux/atomic.h>
40#include <asm/proto.h>
41#include <asm/setup.h>
42#include <asm/apic.h>
43#include <asm/desc.h>
44#include <asm/fpu/internal.h>
45#include <asm/mtrr.h>
46#include <asm/hwcap2.h>
47#include <linux/numa.h>
48#include <asm/numa.h>
49#include <asm/asm.h>
50#include <asm/bugs.h>
51#include <asm/cpu.h>
52#include <asm/mce.h>
53#include <asm/msr.h>
54#include <asm/memtype.h>
55#include <asm/microcode.h>
56#include <asm/microcode_intel.h>
57#include <asm/intel-family.h>
58#include <asm/cpu_device_id.h>
59#include <asm/uv/uv.h>
60
61#include "cpu.h"
62
63u32 elf_hwcap2 __read_mostly;
64
65/* all of these masks are initialized in setup_cpu_local_masks() */
66cpumask_var_t cpu_initialized_mask;
67cpumask_var_t cpu_callout_mask;
68cpumask_var_t cpu_callin_mask;
69
70/* representing cpus for which sibling maps can be computed */
71cpumask_var_t cpu_sibling_setup_mask;
72
73/* Number of siblings per CPU package */
74int smp_num_siblings = 1;
75EXPORT_SYMBOL(smp_num_siblings);
76
77/* Last level cache ID of each logical CPU */
78DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
79
80/* correctly size the local cpu masks */
81void __init setup_cpu_local_masks(void)
82{
83 alloc_bootmem_cpumask_var(&cpu_initialized_mask);
84 alloc_bootmem_cpumask_var(&cpu_callin_mask);
85 alloc_bootmem_cpumask_var(&cpu_callout_mask);
86 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
87}
88
89static void default_init(struct cpuinfo_x86 *c)
90{
91#ifdef CONFIG_X86_64
92 cpu_detect_cache_sizes(c);
93#else
94 /* Not much we can do here... */
95 /* Check if at least it has cpuid */
96 if (c->cpuid_level == -1) {
97 /* No cpuid. It must be an ancient CPU */
98 if (c->x86 == 4)
99 strcpy(c->x86_model_id, "486");
100 else if (c->x86 == 3)
101 strcpy(c->x86_model_id, "386");
102 }
103#endif
104}
105
106static const struct cpu_dev default_cpu = {
107 .c_init = default_init,
108 .c_vendor = "Unknown",
109 .c_x86_vendor = X86_VENDOR_UNKNOWN,
110};
111
112static const struct cpu_dev *this_cpu = &default_cpu;
113
114DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
115#ifdef CONFIG_X86_64
116 /*
117 * We need valid kernel segments for data and code in long mode too
118 * IRET will check the segment types kkeil 2000/10/28
119 * Also sysret mandates a special GDT layout
120 *
121 * TLS descriptors are currently at a different place compared to i386.
122 * Hopefully nobody expects them at a fixed place (Wine?)
123 */
124 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
125 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
126 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
127 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
128 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
129 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
130#else
131 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
132 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
133 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
134 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
135 /*
136 * Segments used for calling PnP BIOS have byte granularity.
137 * They code segments and data segments have fixed 64k limits,
138 * the transfer segment sizes are set at run time.
139 */
140 /* 32-bit code */
141 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
142 /* 16-bit code */
143 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
144 /* 16-bit data */
145 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
146 /* 16-bit data */
147 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0),
148 /* 16-bit data */
149 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0),
150 /*
151 * The APM segments have byte granularity and their bases
152 * are set at run time. All have 64k limits.
153 */
154 /* 32-bit code */
155 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
156 /* 16-bit code */
157 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
158 /* data */
159 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
160
161 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
162 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
163 GDT_STACK_CANARY_INIT
164#endif
165} };
166EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
167
168#ifdef CONFIG_X86_64
169static int __init x86_nopcid_setup(char *s)
170{
171 /* nopcid doesn't accept parameters */
172 if (s)
173 return -EINVAL;
174
175 /* do not emit a message if the feature is not present */
176 if (!boot_cpu_has(X86_FEATURE_PCID))
177 return 0;
178
179 setup_clear_cpu_cap(X86_FEATURE_PCID);
180 pr_info("nopcid: PCID feature disabled\n");
181 return 0;
182}
183early_param("nopcid", x86_nopcid_setup);
184#endif
185
186static int __init x86_noinvpcid_setup(char *s)
187{
188 /* noinvpcid doesn't accept parameters */
189 if (s)
190 return -EINVAL;
191
192 /* do not emit a message if the feature is not present */
193 if (!boot_cpu_has(X86_FEATURE_INVPCID))
194 return 0;
195
196 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
197 pr_info("noinvpcid: INVPCID feature disabled\n");
198 return 0;
199}
200early_param("noinvpcid", x86_noinvpcid_setup);
201
202#ifdef CONFIG_X86_32
203static int cachesize_override = -1;
204static int disable_x86_serial_nr = 1;
205
206static int __init cachesize_setup(char *str)
207{
208 get_option(&str, &cachesize_override);
209 return 1;
210}
211__setup("cachesize=", cachesize_setup);
212
213static int __init x86_sep_setup(char *s)
214{
215 setup_clear_cpu_cap(X86_FEATURE_SEP);
216 return 1;
217}
218__setup("nosep", x86_sep_setup);
219
220/* Standard macro to see if a specific flag is changeable */
221static inline int flag_is_changeable_p(u32 flag)
222{
223 u32 f1, f2;
224
225 /*
226 * Cyrix and IDT cpus allow disabling of CPUID
227 * so the code below may return different results
228 * when it is executed before and after enabling
229 * the CPUID. Add "volatile" to not allow gcc to
230 * optimize the subsequent calls to this function.
231 */
232 asm volatile ("pushfl \n\t"
233 "pushfl \n\t"
234 "popl %0 \n\t"
235 "movl %0, %1 \n\t"
236 "xorl %2, %0 \n\t"
237 "pushl %0 \n\t"
238 "popfl \n\t"
239 "pushfl \n\t"
240 "popl %0 \n\t"
241 "popfl \n\t"
242
243 : "=&r" (f1), "=&r" (f2)
244 : "ir" (flag));
245
246 return ((f1^f2) & flag) != 0;
247}
248
249/* Probe for the CPUID instruction */
250int have_cpuid_p(void)
251{
252 return flag_is_changeable_p(X86_EFLAGS_ID);
253}
254
255static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
256{
257 unsigned long lo, hi;
258
259 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
260 return;
261
262 /* Disable processor serial number: */
263
264 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
265 lo |= 0x200000;
266 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
267
268 pr_notice("CPU serial number disabled.\n");
269 clear_cpu_cap(c, X86_FEATURE_PN);
270
271 /* Disabling the serial number may affect the cpuid level */
272 c->cpuid_level = cpuid_eax(0);
273}
274
275static int __init x86_serial_nr_setup(char *s)
276{
277 disable_x86_serial_nr = 0;
278 return 1;
279}
280__setup("serialnumber", x86_serial_nr_setup);
281#else
282static inline int flag_is_changeable_p(u32 flag)
283{
284 return 1;
285}
286static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
287{
288}
289#endif
290
291static __init int setup_disable_smep(char *arg)
292{
293 setup_clear_cpu_cap(X86_FEATURE_SMEP);
294 return 1;
295}
296__setup("nosmep", setup_disable_smep);
297
298static __always_inline void setup_smep(struct cpuinfo_x86 *c)
299{
300 if (cpu_has(c, X86_FEATURE_SMEP))
301 cr4_set_bits(X86_CR4_SMEP);
302}
303
304static __init int setup_disable_smap(char *arg)
305{
306 setup_clear_cpu_cap(X86_FEATURE_SMAP);
307 return 1;
308}
309__setup("nosmap", setup_disable_smap);
310
311static __always_inline void setup_smap(struct cpuinfo_x86 *c)
312{
313 unsigned long eflags = native_save_fl();
314
315 /* This should have been cleared long ago */
316 BUG_ON(eflags & X86_EFLAGS_AC);
317
318 if (cpu_has(c, X86_FEATURE_SMAP)) {
319#ifdef CONFIG_X86_SMAP
320 cr4_set_bits(X86_CR4_SMAP);
321#else
322 cr4_clear_bits(X86_CR4_SMAP);
323#endif
324 }
325}
326
327static __always_inline void setup_umip(struct cpuinfo_x86 *c)
328{
329 /* Check the boot processor, plus build option for UMIP. */
330 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
331 goto out;
332
333 /* Check the current processor's cpuid bits. */
334 if (!cpu_has(c, X86_FEATURE_UMIP))
335 goto out;
336
337 cr4_set_bits(X86_CR4_UMIP);
338
339 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
340
341 return;
342
343out:
344 /*
345 * Make sure UMIP is disabled in case it was enabled in a
346 * previous boot (e.g., via kexec).
347 */
348 cr4_clear_bits(X86_CR4_UMIP);
349}
350
351/* These bits should not change their value after CPU init is finished. */
352static const unsigned long cr4_pinned_mask =
353 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE;
354static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
355static unsigned long cr4_pinned_bits __ro_after_init;
356
357void native_write_cr0(unsigned long val)
358{
359 unsigned long bits_missing = 0;
360
361set_register:
362 asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order));
363
364 if (static_branch_likely(&cr_pinning)) {
365 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
366 bits_missing = X86_CR0_WP;
367 val |= bits_missing;
368 goto set_register;
369 }
370 /* Warn after we've set the missing bits. */
371 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
372 }
373}
374EXPORT_SYMBOL(native_write_cr0);
375
376void native_write_cr4(unsigned long val)
377{
378 unsigned long bits_changed = 0;
379
380set_register:
381 asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));
382
383 if (static_branch_likely(&cr_pinning)) {
384 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
385 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
386 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
387 goto set_register;
388 }
389 /* Warn after we've corrected the changed bits. */
390 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
391 bits_changed);
392 }
393}
394#if IS_MODULE(CONFIG_LKDTM)
395EXPORT_SYMBOL_GPL(native_write_cr4);
396#endif
397
398void cr4_update_irqsoff(unsigned long set, unsigned long clear)
399{
400 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
401
402 lockdep_assert_irqs_disabled();
403
404 newval = (cr4 & ~clear) | set;
405 if (newval != cr4) {
406 this_cpu_write(cpu_tlbstate.cr4, newval);
407 __write_cr4(newval);
408 }
409}
410EXPORT_SYMBOL(cr4_update_irqsoff);
411
412/* Read the CR4 shadow. */
413unsigned long cr4_read_shadow(void)
414{
415 return this_cpu_read(cpu_tlbstate.cr4);
416}
417EXPORT_SYMBOL_GPL(cr4_read_shadow);
418
419void cr4_init(void)
420{
421 unsigned long cr4 = __read_cr4();
422
423 if (boot_cpu_has(X86_FEATURE_PCID))
424 cr4 |= X86_CR4_PCIDE;
425 if (static_branch_likely(&cr_pinning))
426 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
427
428 __write_cr4(cr4);
429
430 /* Initialize cr4 shadow for this CPU. */
431 this_cpu_write(cpu_tlbstate.cr4, cr4);
432}
433
434/*
435 * Once CPU feature detection is finished (and boot params have been
436 * parsed), record any of the sensitive CR bits that are set, and
437 * enable CR pinning.
438 */
439static void __init setup_cr_pinning(void)
440{
441 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
442 static_key_enable(&cr_pinning.key);
443}
444
445static __init int x86_nofsgsbase_setup(char *arg)
446{
447 /* Require an exact match without trailing characters. */
448 if (strlen(arg))
449 return 0;
450
451 /* Do not emit a message if the feature is not present. */
452 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
453 return 1;
454
455 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
456 pr_info("FSGSBASE disabled via kernel command line\n");
457 return 1;
458}
459__setup("nofsgsbase", x86_nofsgsbase_setup);
460
461/*
462 * Protection Keys are not available in 32-bit mode.
463 */
464static bool pku_disabled;
465
466static __always_inline void setup_pku(struct cpuinfo_x86 *c)
467{
468 struct pkru_state *pk;
469
470 /* check the boot processor, plus compile options for PKU: */
471 if (!cpu_feature_enabled(X86_FEATURE_PKU))
472 return;
473 /* checks the actual processor's cpuid bits: */
474 if (!cpu_has(c, X86_FEATURE_PKU))
475 return;
476 if (pku_disabled)
477 return;
478
479 cr4_set_bits(X86_CR4_PKE);
480 pk = get_xsave_addr(&init_fpstate.xsave, XFEATURE_PKRU);
481 if (pk)
482 pk->pkru = init_pkru_value;
483 /*
484 * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
485 * cpuid bit to be set. We need to ensure that we
486 * update that bit in this CPU's "cpu_info".
487 */
488 set_cpu_cap(c, X86_FEATURE_OSPKE);
489}
490
491#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
492static __init int setup_disable_pku(char *arg)
493{
494 /*
495 * Do not clear the X86_FEATURE_PKU bit. All of the
496 * runtime checks are against OSPKE so clearing the
497 * bit does nothing.
498 *
499 * This way, we will see "pku" in cpuinfo, but not
500 * "ospke", which is exactly what we want. It shows
501 * that the CPU has PKU, but the OS has not enabled it.
502 * This happens to be exactly how a system would look
503 * if we disabled the config option.
504 */
505 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
506 pku_disabled = true;
507 return 1;
508}
509__setup("nopku", setup_disable_pku);
510#endif /* CONFIG_X86_64 */
511
512/*
513 * Some CPU features depend on higher CPUID levels, which may not always
514 * be available due to CPUID level capping or broken virtualization
515 * software. Add those features to this table to auto-disable them.
516 */
517struct cpuid_dependent_feature {
518 u32 feature;
519 u32 level;
520};
521
522static const struct cpuid_dependent_feature
523cpuid_dependent_features[] = {
524 { X86_FEATURE_MWAIT, 0x00000005 },
525 { X86_FEATURE_DCA, 0x00000009 },
526 { X86_FEATURE_XSAVE, 0x0000000d },
527 { 0, 0 }
528};
529
530static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
531{
532 const struct cpuid_dependent_feature *df;
533
534 for (df = cpuid_dependent_features; df->feature; df++) {
535
536 if (!cpu_has(c, df->feature))
537 continue;
538 /*
539 * Note: cpuid_level is set to -1 if unavailable, but
540 * extended_extended_level is set to 0 if unavailable
541 * and the legitimate extended levels are all negative
542 * when signed; hence the weird messing around with
543 * signs here...
544 */
545 if (!((s32)df->level < 0 ?
546 (u32)df->level > (u32)c->extended_cpuid_level :
547 (s32)df->level > (s32)c->cpuid_level))
548 continue;
549
550 clear_cpu_cap(c, df->feature);
551 if (!warn)
552 continue;
553
554 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
555 x86_cap_flag(df->feature), df->level);
556 }
557}
558
559/*
560 * Naming convention should be: <Name> [(<Codename>)]
561 * This table only is used unless init_<vendor>() below doesn't set it;
562 * in particular, if CPUID levels 0x80000002..4 are supported, this
563 * isn't used
564 */
565
566/* Look up CPU names by table lookup. */
567static const char *table_lookup_model(struct cpuinfo_x86 *c)
568{
569#ifdef CONFIG_X86_32
570 const struct legacy_cpu_model_info *info;
571
572 if (c->x86_model >= 16)
573 return NULL; /* Range check */
574
575 if (!this_cpu)
576 return NULL;
577
578 info = this_cpu->legacy_models;
579
580 while (info->family) {
581 if (info->family == c->x86)
582 return info->model_names[c->x86_model];
583 info++;
584 }
585#endif
586 return NULL; /* Not found */
587}
588
589/* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
590__u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
591__u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
592
593void load_percpu_segment(int cpu)
594{
595#ifdef CONFIG_X86_32
596 loadsegment(fs, __KERNEL_PERCPU);
597#else
598 __loadsegment_simple(gs, 0);
599 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
600#endif
601 load_stack_canary_segment();
602}
603
604#ifdef CONFIG_X86_32
605/* The 32-bit entry code needs to find cpu_entry_area. */
606DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
607#endif
608
609/* Load the original GDT from the per-cpu structure */
610void load_direct_gdt(int cpu)
611{
612 struct desc_ptr gdt_descr;
613
614 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
615 gdt_descr.size = GDT_SIZE - 1;
616 load_gdt(&gdt_descr);
617}
618EXPORT_SYMBOL_GPL(load_direct_gdt);
619
620/* Load a fixmap remapping of the per-cpu GDT */
621void load_fixmap_gdt(int cpu)
622{
623 struct desc_ptr gdt_descr;
624
625 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
626 gdt_descr.size = GDT_SIZE - 1;
627 load_gdt(&gdt_descr);
628}
629EXPORT_SYMBOL_GPL(load_fixmap_gdt);
630
631/*
632 * Current gdt points %fs at the "master" per-cpu area: after this,
633 * it's on the real one.
634 */
635void switch_to_new_gdt(int cpu)
636{
637 /* Load the original GDT */
638 load_direct_gdt(cpu);
639 /* Reload the per-cpu base */
640 load_percpu_segment(cpu);
641}
642
643static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
644
645static void get_model_name(struct cpuinfo_x86 *c)
646{
647 unsigned int *v;
648 char *p, *q, *s;
649
650 if (c->extended_cpuid_level < 0x80000004)
651 return;
652
653 v = (unsigned int *)c->x86_model_id;
654 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
655 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
656 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
657 c->x86_model_id[48] = 0;
658
659 /* Trim whitespace */
660 p = q = s = &c->x86_model_id[0];
661
662 while (*p == ' ')
663 p++;
664
665 while (*p) {
666 /* Note the last non-whitespace index */
667 if (!isspace(*p))
668 s = q;
669
670 *q++ = *p++;
671 }
672
673 *(s + 1) = '\0';
674}
675
676void detect_num_cpu_cores(struct cpuinfo_x86 *c)
677{
678 unsigned int eax, ebx, ecx, edx;
679
680 c->x86_max_cores = 1;
681 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
682 return;
683
684 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
685 if (eax & 0x1f)
686 c->x86_max_cores = (eax >> 26) + 1;
687}
688
689void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
690{
691 unsigned int n, dummy, ebx, ecx, edx, l2size;
692
693 n = c->extended_cpuid_level;
694
695 if (n >= 0x80000005) {
696 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
697 c->x86_cache_size = (ecx>>24) + (edx>>24);
698#ifdef CONFIG_X86_64
699 /* On K8 L1 TLB is inclusive, so don't count it */
700 c->x86_tlbsize = 0;
701#endif
702 }
703
704 if (n < 0x80000006) /* Some chips just has a large L1. */
705 return;
706
707 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
708 l2size = ecx >> 16;
709
710#ifdef CONFIG_X86_64
711 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
712#else
713 /* do processor-specific cache resizing */
714 if (this_cpu->legacy_cache_size)
715 l2size = this_cpu->legacy_cache_size(c, l2size);
716
717 /* Allow user to override all this if necessary. */
718 if (cachesize_override != -1)
719 l2size = cachesize_override;
720
721 if (l2size == 0)
722 return; /* Again, no L2 cache is possible */
723#endif
724
725 c->x86_cache_size = l2size;
726}
727
728u16 __read_mostly tlb_lli_4k[NR_INFO];
729u16 __read_mostly tlb_lli_2m[NR_INFO];
730u16 __read_mostly tlb_lli_4m[NR_INFO];
731u16 __read_mostly tlb_lld_4k[NR_INFO];
732u16 __read_mostly tlb_lld_2m[NR_INFO];
733u16 __read_mostly tlb_lld_4m[NR_INFO];
734u16 __read_mostly tlb_lld_1g[NR_INFO];
735
736static void cpu_detect_tlb(struct cpuinfo_x86 *c)
737{
738 if (this_cpu->c_detect_tlb)
739 this_cpu->c_detect_tlb(c);
740
741 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
742 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
743 tlb_lli_4m[ENTRIES]);
744
745 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
746 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
747 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
748}
749
750int detect_ht_early(struct cpuinfo_x86 *c)
751{
752#ifdef CONFIG_SMP
753 u32 eax, ebx, ecx, edx;
754
755 if (!cpu_has(c, X86_FEATURE_HT))
756 return -1;
757
758 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
759 return -1;
760
761 if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
762 return -1;
763
764 cpuid(1, &eax, &ebx, &ecx, &edx);
765
766 smp_num_siblings = (ebx & 0xff0000) >> 16;
767 if (smp_num_siblings == 1)
768 pr_info_once("CPU0: Hyper-Threading is disabled\n");
769#endif
770 return 0;
771}
772
773void detect_ht(struct cpuinfo_x86 *c)
774{
775#ifdef CONFIG_SMP
776 int index_msb, core_bits;
777
778 if (detect_ht_early(c) < 0)
779 return;
780
781 index_msb = get_count_order(smp_num_siblings);
782 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
783
784 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
785
786 index_msb = get_count_order(smp_num_siblings);
787
788 core_bits = get_count_order(c->x86_max_cores);
789
790 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
791 ((1 << core_bits) - 1);
792#endif
793}
794
795static void get_cpu_vendor(struct cpuinfo_x86 *c)
796{
797 char *v = c->x86_vendor_id;
798 int i;
799
800 for (i = 0; i < X86_VENDOR_NUM; i++) {
801 if (!cpu_devs[i])
802 break;
803
804 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
805 (cpu_devs[i]->c_ident[1] &&
806 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
807
808 this_cpu = cpu_devs[i];
809 c->x86_vendor = this_cpu->c_x86_vendor;
810 return;
811 }
812 }
813
814 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
815 "CPU: Your system may be unstable.\n", v);
816
817 c->x86_vendor = X86_VENDOR_UNKNOWN;
818 this_cpu = &default_cpu;
819}
820
821void cpu_detect(struct cpuinfo_x86 *c)
822{
823 /* Get vendor name */
824 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
825 (unsigned int *)&c->x86_vendor_id[0],
826 (unsigned int *)&c->x86_vendor_id[8],
827 (unsigned int *)&c->x86_vendor_id[4]);
828
829 c->x86 = 4;
830 /* Intel-defined flags: level 0x00000001 */
831 if (c->cpuid_level >= 0x00000001) {
832 u32 junk, tfms, cap0, misc;
833
834 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
835 c->x86 = x86_family(tfms);
836 c->x86_model = x86_model(tfms);
837 c->x86_stepping = x86_stepping(tfms);
838
839 if (cap0 & (1<<19)) {
840 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
841 c->x86_cache_alignment = c->x86_clflush_size;
842 }
843 }
844}
845
846static void apply_forced_caps(struct cpuinfo_x86 *c)
847{
848 int i;
849
850 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
851 c->x86_capability[i] &= ~cpu_caps_cleared[i];
852 c->x86_capability[i] |= cpu_caps_set[i];
853 }
854}
855
856static void init_speculation_control(struct cpuinfo_x86 *c)
857{
858 /*
859 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
860 * and they also have a different bit for STIBP support. Also,
861 * a hypervisor might have set the individual AMD bits even on
862 * Intel CPUs, for finer-grained selection of what's available.
863 */
864 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
865 set_cpu_cap(c, X86_FEATURE_IBRS);
866 set_cpu_cap(c, X86_FEATURE_IBPB);
867 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
868 }
869
870 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
871 set_cpu_cap(c, X86_FEATURE_STIBP);
872
873 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
874 cpu_has(c, X86_FEATURE_VIRT_SSBD))
875 set_cpu_cap(c, X86_FEATURE_SSBD);
876
877 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
878 set_cpu_cap(c, X86_FEATURE_IBRS);
879 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
880 }
881
882 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
883 set_cpu_cap(c, X86_FEATURE_IBPB);
884
885 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
886 set_cpu_cap(c, X86_FEATURE_STIBP);
887 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
888 }
889
890 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
891 set_cpu_cap(c, X86_FEATURE_SSBD);
892 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
893 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
894 }
895}
896
897void get_cpu_cap(struct cpuinfo_x86 *c)
898{
899 u32 eax, ebx, ecx, edx;
900
901 /* Intel-defined flags: level 0x00000001 */
902 if (c->cpuid_level >= 0x00000001) {
903 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
904
905 c->x86_capability[CPUID_1_ECX] = ecx;
906 c->x86_capability[CPUID_1_EDX] = edx;
907 }
908
909 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
910 if (c->cpuid_level >= 0x00000006)
911 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
912
913 /* Additional Intel-defined flags: level 0x00000007 */
914 if (c->cpuid_level >= 0x00000007) {
915 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
916 c->x86_capability[CPUID_7_0_EBX] = ebx;
917 c->x86_capability[CPUID_7_ECX] = ecx;
918 c->x86_capability[CPUID_7_EDX] = edx;
919
920 /* Check valid sub-leaf index before accessing it */
921 if (eax >= 1) {
922 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
923 c->x86_capability[CPUID_7_1_EAX] = eax;
924 }
925 }
926
927 /* Extended state features: level 0x0000000d */
928 if (c->cpuid_level >= 0x0000000d) {
929 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
930
931 c->x86_capability[CPUID_D_1_EAX] = eax;
932 }
933
934 /* AMD-defined flags: level 0x80000001 */
935 eax = cpuid_eax(0x80000000);
936 c->extended_cpuid_level = eax;
937
938 if ((eax & 0xffff0000) == 0x80000000) {
939 if (eax >= 0x80000001) {
940 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
941
942 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
943 c->x86_capability[CPUID_8000_0001_EDX] = edx;
944 }
945 }
946
947 if (c->extended_cpuid_level >= 0x80000007) {
948 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
949
950 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
951 c->x86_power = edx;
952 }
953
954 if (c->extended_cpuid_level >= 0x80000008) {
955 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
956 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
957 }
958
959 if (c->extended_cpuid_level >= 0x8000000a)
960 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
961
962 init_scattered_cpuid_features(c);
963 init_speculation_control(c);
964
965 /*
966 * Clear/Set all flags overridden by options, after probe.
967 * This needs to happen each time we re-probe, which may happen
968 * several times during CPU initialization.
969 */
970 apply_forced_caps(c);
971}
972
973void get_cpu_address_sizes(struct cpuinfo_x86 *c)
974{
975 u32 eax, ebx, ecx, edx;
976
977 if (c->extended_cpuid_level >= 0x80000008) {
978 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
979
980 c->x86_virt_bits = (eax >> 8) & 0xff;
981 c->x86_phys_bits = eax & 0xff;
982 }
983#ifdef CONFIG_X86_32
984 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
985 c->x86_phys_bits = 36;
986#endif
987 c->x86_cache_bits = c->x86_phys_bits;
988}
989
990static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
991{
992#ifdef CONFIG_X86_32
993 int i;
994
995 /*
996 * First of all, decide if this is a 486 or higher
997 * It's a 486 if we can modify the AC flag
998 */
999 if (flag_is_changeable_p(X86_EFLAGS_AC))
1000 c->x86 = 4;
1001 else
1002 c->x86 = 3;
1003
1004 for (i = 0; i < X86_VENDOR_NUM; i++)
1005 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1006 c->x86_vendor_id[0] = 0;
1007 cpu_devs[i]->c_identify(c);
1008 if (c->x86_vendor_id[0]) {
1009 get_cpu_vendor(c);
1010 break;
1011 }
1012 }
1013#endif
1014}
1015
1016#define NO_SPECULATION BIT(0)
1017#define NO_MELTDOWN BIT(1)
1018#define NO_SSB BIT(2)
1019#define NO_L1TF BIT(3)
1020#define NO_MDS BIT(4)
1021#define MSBDS_ONLY BIT(5)
1022#define NO_SWAPGS BIT(6)
1023#define NO_ITLB_MULTIHIT BIT(7)
1024#define NO_SPECTRE_V2 BIT(8)
1025
1026#define VULNWL(vendor, family, model, whitelist) \
1027 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1028
1029#define VULNWL_INTEL(model, whitelist) \
1030 VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist)
1031
1032#define VULNWL_AMD(family, whitelist) \
1033 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1034
1035#define VULNWL_HYGON(family, whitelist) \
1036 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1037
1038static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1039 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1040 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1041 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1042 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1043
1044 /* Intel Family 6 */
1045 VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1046 VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1047 VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1048 VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1049 VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1050
1051 VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1052 VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1053 VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1054 VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1055 VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1056 VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1057
1058 VULNWL_INTEL(CORE_YONAH, NO_SSB),
1059
1060 VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1061 VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1062
1063 VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1064 VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1065 VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1066
1067 /*
1068 * Technically, swapgs isn't serializing on AMD (despite it previously
1069 * being documented as such in the APM). But according to AMD, %gs is
1070 * updated non-speculatively, and the issuing of %gs-relative memory
1071 * operands will be blocked until the %gs update completes, which is
1072 * good enough for our purposes.
1073 */
1074
1075 VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT),
1076
1077 /* AMD Family 0xf - 0x12 */
1078 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1079 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1080 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1081 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1082
1083 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1084 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1085 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1086
1087 /* Zhaoxin Family 7 */
1088 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1089 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1090 {}
1091};
1092
1093#define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
1094 X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
1095 INTEL_FAM6_##model, steppings, \
1096 X86_FEATURE_ANY, issues)
1097
1098#define SRBDS BIT(0)
1099
1100static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1101 VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1102 VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS),
1103 VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS),
1104 VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS),
1105 VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1106 VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS),
1107 VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS),
1108 VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS),
1109 VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS),
1110 VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS),
1111 {}
1112};
1113
1114static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1115{
1116 const struct x86_cpu_id *m = x86_match_cpu(table);
1117
1118 return m && !!(m->driver_data & which);
1119}
1120
1121u64 x86_read_arch_cap_msr(void)
1122{
1123 u64 ia32_cap = 0;
1124
1125 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1126 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
1127
1128 return ia32_cap;
1129}
1130
1131static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1132{
1133 u64 ia32_cap = x86_read_arch_cap_msr();
1134
1135 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1136 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1137 !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO))
1138 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1139
1140 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1141 return;
1142
1143 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1144
1145 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1146 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1147
1148 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1149 !(ia32_cap & ARCH_CAP_SSB_NO) &&
1150 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1151 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1152
1153 if (ia32_cap & ARCH_CAP_IBRS_ALL)
1154 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1155
1156 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1157 !(ia32_cap & ARCH_CAP_MDS_NO)) {
1158 setup_force_cpu_bug(X86_BUG_MDS);
1159 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1160 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1161 }
1162
1163 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1164 setup_force_cpu_bug(X86_BUG_SWAPGS);
1165
1166 /*
1167 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1168 * - TSX is supported or
1169 * - TSX_CTRL is present
1170 *
1171 * TSX_CTRL check is needed for cases when TSX could be disabled before
1172 * the kernel boot e.g. kexec.
1173 * TSX_CTRL check alone is not sufficient for cases when the microcode
1174 * update is not present or running as guest that don't get TSX_CTRL.
1175 */
1176 if (!(ia32_cap & ARCH_CAP_TAA_NO) &&
1177 (cpu_has(c, X86_FEATURE_RTM) ||
1178 (ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
1179 setup_force_cpu_bug(X86_BUG_TAA);
1180
1181 /*
1182 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1183 * in the vulnerability blacklist.
1184 */
1185 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1186 cpu_has(c, X86_FEATURE_RDSEED)) &&
1187 cpu_matches(cpu_vuln_blacklist, SRBDS))
1188 setup_force_cpu_bug(X86_BUG_SRBDS);
1189
1190 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1191 return;
1192
1193 /* Rogue Data Cache Load? No! */
1194 if (ia32_cap & ARCH_CAP_RDCL_NO)
1195 return;
1196
1197 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1198
1199 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1200 return;
1201
1202 setup_force_cpu_bug(X86_BUG_L1TF);
1203}
1204
1205/*
1206 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1207 * unfortunately, that's not true in practice because of early VIA
1208 * chips and (more importantly) broken virtualizers that are not easy
1209 * to detect. In the latter case it doesn't even *fail* reliably, so
1210 * probing for it doesn't even work. Disable it completely on 32-bit
1211 * unless we can find a reliable way to detect all the broken cases.
1212 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1213 */
1214static void detect_nopl(void)
1215{
1216#ifdef CONFIG_X86_32
1217 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1218#else
1219 setup_force_cpu_cap(X86_FEATURE_NOPL);
1220#endif
1221}
1222
1223/*
1224 * Do minimum CPU detection early.
1225 * Fields really needed: vendor, cpuid_level, family, model, mask,
1226 * cache alignment.
1227 * The others are not touched to avoid unwanted side effects.
1228 *
1229 * WARNING: this function is only called on the boot CPU. Don't add code
1230 * here that is supposed to run on all CPUs.
1231 */
1232static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1233{
1234#ifdef CONFIG_X86_64
1235 c->x86_clflush_size = 64;
1236 c->x86_phys_bits = 36;
1237 c->x86_virt_bits = 48;
1238#else
1239 c->x86_clflush_size = 32;
1240 c->x86_phys_bits = 32;
1241 c->x86_virt_bits = 32;
1242#endif
1243 c->x86_cache_alignment = c->x86_clflush_size;
1244
1245 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1246 c->extended_cpuid_level = 0;
1247
1248 if (!have_cpuid_p())
1249 identify_cpu_without_cpuid(c);
1250
1251 /* cyrix could have cpuid enabled via c_identify()*/
1252 if (have_cpuid_p()) {
1253 cpu_detect(c);
1254 get_cpu_vendor(c);
1255 get_cpu_cap(c);
1256 get_cpu_address_sizes(c);
1257 setup_force_cpu_cap(X86_FEATURE_CPUID);
1258
1259 if (this_cpu->c_early_init)
1260 this_cpu->c_early_init(c);
1261
1262 c->cpu_index = 0;
1263 filter_cpuid_features(c, false);
1264
1265 if (this_cpu->c_bsp_init)
1266 this_cpu->c_bsp_init(c);
1267 } else {
1268 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1269 }
1270
1271 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1272
1273 cpu_set_bug_bits(c);
1274
1275 cpu_set_core_cap_bits(c);
1276
1277 fpu__init_system(c);
1278
1279#ifdef CONFIG_X86_32
1280 /*
1281 * Regardless of whether PCID is enumerated, the SDM says
1282 * that it can't be enabled in 32-bit mode.
1283 */
1284 setup_clear_cpu_cap(X86_FEATURE_PCID);
1285#endif
1286
1287 /*
1288 * Later in the boot process pgtable_l5_enabled() relies on
1289 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1290 * enabled by this point we need to clear the feature bit to avoid
1291 * false-positives at the later stage.
1292 *
1293 * pgtable_l5_enabled() can be false here for several reasons:
1294 * - 5-level paging is disabled compile-time;
1295 * - it's 32-bit kernel;
1296 * - machine doesn't support 5-level paging;
1297 * - user specified 'no5lvl' in kernel command line.
1298 */
1299 if (!pgtable_l5_enabled())
1300 setup_clear_cpu_cap(X86_FEATURE_LA57);
1301
1302 detect_nopl();
1303}
1304
1305void __init early_cpu_init(void)
1306{
1307 const struct cpu_dev *const *cdev;
1308 int count = 0;
1309
1310#ifdef CONFIG_PROCESSOR_SELECT
1311 pr_info("KERNEL supported cpus:\n");
1312#endif
1313
1314 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1315 const struct cpu_dev *cpudev = *cdev;
1316
1317 if (count >= X86_VENDOR_NUM)
1318 break;
1319 cpu_devs[count] = cpudev;
1320 count++;
1321
1322#ifdef CONFIG_PROCESSOR_SELECT
1323 {
1324 unsigned int j;
1325
1326 for (j = 0; j < 2; j++) {
1327 if (!cpudev->c_ident[j])
1328 continue;
1329 pr_info(" %s %s\n", cpudev->c_vendor,
1330 cpudev->c_ident[j]);
1331 }
1332 }
1333#endif
1334 }
1335 early_identify_cpu(&boot_cpu_data);
1336}
1337
1338static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
1339{
1340#ifdef CONFIG_X86_64
1341 /*
1342 * Empirically, writing zero to a segment selector on AMD does
1343 * not clear the base, whereas writing zero to a segment
1344 * selector on Intel does clear the base. Intel's behavior
1345 * allows slightly faster context switches in the common case
1346 * where GS is unused by the prev and next threads.
1347 *
1348 * Since neither vendor documents this anywhere that I can see,
1349 * detect it directly instead of hardcoding the choice by
1350 * vendor.
1351 *
1352 * I've designated AMD's behavior as the "bug" because it's
1353 * counterintuitive and less friendly.
1354 */
1355
1356 unsigned long old_base, tmp;
1357 rdmsrl(MSR_FS_BASE, old_base);
1358 wrmsrl(MSR_FS_BASE, 1);
1359 loadsegment(fs, 0);
1360 rdmsrl(MSR_FS_BASE, tmp);
1361 if (tmp != 0)
1362 set_cpu_bug(c, X86_BUG_NULL_SEG);
1363 wrmsrl(MSR_FS_BASE, old_base);
1364#endif
1365}
1366
1367static void generic_identify(struct cpuinfo_x86 *c)
1368{
1369 c->extended_cpuid_level = 0;
1370
1371 if (!have_cpuid_p())
1372 identify_cpu_without_cpuid(c);
1373
1374 /* cyrix could have cpuid enabled via c_identify()*/
1375 if (!have_cpuid_p())
1376 return;
1377
1378 cpu_detect(c);
1379
1380 get_cpu_vendor(c);
1381
1382 get_cpu_cap(c);
1383
1384 get_cpu_address_sizes(c);
1385
1386 if (c->cpuid_level >= 0x00000001) {
1387 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
1388#ifdef CONFIG_X86_32
1389# ifdef CONFIG_SMP
1390 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1391# else
1392 c->apicid = c->initial_apicid;
1393# endif
1394#endif
1395 c->phys_proc_id = c->initial_apicid;
1396 }
1397
1398 get_model_name(c); /* Default name */
1399
1400 detect_null_seg_behavior(c);
1401
1402 /*
1403 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1404 * systems that run Linux at CPL > 0 may or may not have the
1405 * issue, but, even if they have the issue, there's absolutely
1406 * nothing we can do about it because we can't use the real IRET
1407 * instruction.
1408 *
1409 * NB: For the time being, only 32-bit kernels support
1410 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1411 * whether to apply espfix using paravirt hooks. If any
1412 * non-paravirt system ever shows up that does *not* have the
1413 * ESPFIX issue, we can change this.
1414 */
1415#ifdef CONFIG_X86_32
1416# ifdef CONFIG_PARAVIRT_XXL
1417 do {
1418 extern void native_iret(void);
1419 if (pv_ops.cpu.iret == native_iret)
1420 set_cpu_bug(c, X86_BUG_ESPFIX);
1421 } while (0);
1422# else
1423 set_cpu_bug(c, X86_BUG_ESPFIX);
1424# endif
1425#endif
1426}
1427
1428/*
1429 * Validate that ACPI/mptables have the same information about the
1430 * effective APIC id and update the package map.
1431 */
1432static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
1433{
1434#ifdef CONFIG_SMP
1435 unsigned int apicid, cpu = smp_processor_id();
1436
1437 apicid = apic->cpu_present_to_apicid(cpu);
1438
1439 if (apicid != c->apicid) {
1440 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
1441 cpu, apicid, c->initial_apicid);
1442 }
1443 BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
1444 BUG_ON(topology_update_die_map(c->cpu_die_id, cpu));
1445#else
1446 c->logical_proc_id = 0;
1447#endif
1448}
1449
1450/*
1451 * This does the hard work of actually picking apart the CPU stuff...
1452 */
1453static void identify_cpu(struct cpuinfo_x86 *c)
1454{
1455 int i;
1456
1457 c->loops_per_jiffy = loops_per_jiffy;
1458 c->x86_cache_size = 0;
1459 c->x86_vendor = X86_VENDOR_UNKNOWN;
1460 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1461 c->x86_vendor_id[0] = '\0'; /* Unset */
1462 c->x86_model_id[0] = '\0'; /* Unset */
1463 c->x86_max_cores = 1;
1464 c->x86_coreid_bits = 0;
1465 c->cu_id = 0xff;
1466#ifdef CONFIG_X86_64
1467 c->x86_clflush_size = 64;
1468 c->x86_phys_bits = 36;
1469 c->x86_virt_bits = 48;
1470#else
1471 c->cpuid_level = -1; /* CPUID not detected */
1472 c->x86_clflush_size = 32;
1473 c->x86_phys_bits = 32;
1474 c->x86_virt_bits = 32;
1475#endif
1476 c->x86_cache_alignment = c->x86_clflush_size;
1477 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1478#ifdef CONFIG_X86_VMX_FEATURE_NAMES
1479 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1480#endif
1481
1482 generic_identify(c);
1483
1484 if (this_cpu->c_identify)
1485 this_cpu->c_identify(c);
1486
1487 /* Clear/Set all flags overridden by options, after probe */
1488 apply_forced_caps(c);
1489
1490#ifdef CONFIG_X86_64
1491 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1492#endif
1493
1494 /*
1495 * Vendor-specific initialization. In this section we
1496 * canonicalize the feature flags, meaning if there are
1497 * features a certain CPU supports which CPUID doesn't
1498 * tell us, CPUID claiming incorrect flags, or other bugs,
1499 * we handle them here.
1500 *
1501 * At the end of this section, c->x86_capability better
1502 * indicate the features this CPU genuinely supports!
1503 */
1504 if (this_cpu->c_init)
1505 this_cpu->c_init(c);
1506
1507 /* Disable the PN if appropriate */
1508 squash_the_stupid_serial_number(c);
1509
1510 /* Set up SMEP/SMAP/UMIP */
1511 setup_smep(c);
1512 setup_smap(c);
1513 setup_umip(c);
1514
1515 /* Enable FSGSBASE instructions if available. */
1516 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1517 cr4_set_bits(X86_CR4_FSGSBASE);
1518 elf_hwcap2 |= HWCAP2_FSGSBASE;
1519 }
1520
1521 /*
1522 * The vendor-specific functions might have changed features.
1523 * Now we do "generic changes."
1524 */
1525
1526 /* Filter out anything that depends on CPUID levels we don't have */
1527 filter_cpuid_features(c, true);
1528
1529 /* If the model name is still unset, do table lookup. */
1530 if (!c->x86_model_id[0]) {
1531 const char *p;
1532 p = table_lookup_model(c);
1533 if (p)
1534 strcpy(c->x86_model_id, p);
1535 else
1536 /* Last resort... */
1537 sprintf(c->x86_model_id, "%02x/%02x",
1538 c->x86, c->x86_model);
1539 }
1540
1541#ifdef CONFIG_X86_64
1542 detect_ht(c);
1543#endif
1544
1545 x86_init_rdrand(c);
1546 setup_pku(c);
1547
1548 /*
1549 * Clear/Set all flags overridden by options, need do it
1550 * before following smp all cpus cap AND.
1551 */
1552 apply_forced_caps(c);
1553
1554 /*
1555 * On SMP, boot_cpu_data holds the common feature set between
1556 * all CPUs; so make sure that we indicate which features are
1557 * common between the CPUs. The first time this routine gets
1558 * executed, c == &boot_cpu_data.
1559 */
1560 if (c != &boot_cpu_data) {
1561 /* AND the already accumulated flags with these */
1562 for (i = 0; i < NCAPINTS; i++)
1563 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1564
1565 /* OR, i.e. replicate the bug flags */
1566 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1567 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1568 }
1569
1570 /* Init Machine Check Exception if available. */
1571 mcheck_cpu_init(c);
1572
1573 select_idle_routine(c);
1574
1575#ifdef CONFIG_NUMA
1576 numa_add_cpu(smp_processor_id());
1577#endif
1578}
1579
1580/*
1581 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1582 * on 32-bit kernels:
1583 */
1584#ifdef CONFIG_X86_32
1585void enable_sep_cpu(void)
1586{
1587 struct tss_struct *tss;
1588 int cpu;
1589
1590 if (!boot_cpu_has(X86_FEATURE_SEP))
1591 return;
1592
1593 cpu = get_cpu();
1594 tss = &per_cpu(cpu_tss_rw, cpu);
1595
1596 /*
1597 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1598 * see the big comment in struct x86_hw_tss's definition.
1599 */
1600
1601 tss->x86_tss.ss1 = __KERNEL_CS;
1602 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1603 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1604 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1605
1606 put_cpu();
1607}
1608#endif
1609
1610void __init identify_boot_cpu(void)
1611{
1612 identify_cpu(&boot_cpu_data);
1613#ifdef CONFIG_X86_32
1614 sysenter_setup();
1615 enable_sep_cpu();
1616#endif
1617 cpu_detect_tlb(&boot_cpu_data);
1618 setup_cr_pinning();
1619
1620 tsx_init();
1621}
1622
1623void identify_secondary_cpu(struct cpuinfo_x86 *c)
1624{
1625 BUG_ON(c == &boot_cpu_data);
1626 identify_cpu(c);
1627#ifdef CONFIG_X86_32
1628 enable_sep_cpu();
1629#endif
1630 mtrr_ap_init();
1631 validate_apic_and_package_id(c);
1632 x86_spec_ctrl_setup_ap();
1633 update_srbds_msr();
1634}
1635
1636static __init int setup_noclflush(char *arg)
1637{
1638 setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1639 setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1640 return 1;
1641}
1642__setup("noclflush", setup_noclflush);
1643
1644void print_cpu_info(struct cpuinfo_x86 *c)
1645{
1646 const char *vendor = NULL;
1647
1648 if (c->x86_vendor < X86_VENDOR_NUM) {
1649 vendor = this_cpu->c_vendor;
1650 } else {
1651 if (c->cpuid_level >= 0)
1652 vendor = c->x86_vendor_id;
1653 }
1654
1655 if (vendor && !strstr(c->x86_model_id, vendor))
1656 pr_cont("%s ", vendor);
1657
1658 if (c->x86_model_id[0])
1659 pr_cont("%s", c->x86_model_id);
1660 else
1661 pr_cont("%d86", c->x86);
1662
1663 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1664
1665 if (c->x86_stepping || c->cpuid_level >= 0)
1666 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1667 else
1668 pr_cont(")\n");
1669}
1670
1671/*
1672 * clearcpuid= was already parsed in fpu__init_parse_early_param.
1673 * But we need to keep a dummy __setup around otherwise it would
1674 * show up as an environment variable for init.
1675 */
1676static __init int setup_clearcpuid(char *arg)
1677{
1678 return 1;
1679}
1680__setup("clearcpuid=", setup_clearcpuid);
1681
1682#ifdef CONFIG_X86_64
1683DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
1684 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
1685EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
1686
1687/*
1688 * The following percpu variables are hot. Align current_task to
1689 * cacheline size such that they fall in the same cacheline.
1690 */
1691DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1692 &init_task;
1693EXPORT_PER_CPU_SYMBOL(current_task);
1694
1695DEFINE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
1696DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1697
1698DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1699EXPORT_PER_CPU_SYMBOL(__preempt_count);
1700
1701/* May not be marked __init: used by software suspend */
1702void syscall_init(void)
1703{
1704 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1705 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1706
1707#ifdef CONFIG_IA32_EMULATION
1708 wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1709 /*
1710 * This only works on Intel CPUs.
1711 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1712 * This does not cause SYSENTER to jump to the wrong location, because
1713 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1714 */
1715 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1716 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
1717 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
1718 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1719#else
1720 wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1721 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1722 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1723 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1724#endif
1725
1726 /* Flags to clear on syscall */
1727 wrmsrl(MSR_SYSCALL_MASK,
1728 X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1729 X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1730}
1731
1732#else /* CONFIG_X86_64 */
1733
1734DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1735EXPORT_PER_CPU_SYMBOL(current_task);
1736DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1737EXPORT_PER_CPU_SYMBOL(__preempt_count);
1738
1739/*
1740 * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1741 * the top of the kernel stack. Use an extra percpu variable to track the
1742 * top of the kernel stack directly.
1743 */
1744DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1745 (unsigned long)&init_thread_union + THREAD_SIZE;
1746EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1747
1748#ifdef CONFIG_STACKPROTECTOR
1749DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1750#endif
1751
1752#endif /* CONFIG_X86_64 */
1753
1754/*
1755 * Clear all 6 debug registers:
1756 */
1757static void clear_all_debug_regs(void)
1758{
1759 int i;
1760
1761 for (i = 0; i < 8; i++) {
1762 /* Ignore db4, db5 */
1763 if ((i == 4) || (i == 5))
1764 continue;
1765
1766 set_debugreg(0, i);
1767 }
1768}
1769
1770#ifdef CONFIG_KGDB
1771/*
1772 * Restore debug regs if using kgdbwait and you have a kernel debugger
1773 * connection established.
1774 */
1775static void dbg_restore_debug_regs(void)
1776{
1777 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1778 arch_kgdb_ops.correct_hw_break();
1779}
1780#else /* ! CONFIG_KGDB */
1781#define dbg_restore_debug_regs()
1782#endif /* ! CONFIG_KGDB */
1783
1784static void wait_for_master_cpu(int cpu)
1785{
1786#ifdef CONFIG_SMP
1787 /*
1788 * wait for ACK from master CPU before continuing
1789 * with AP initialization
1790 */
1791 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1792 while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1793 cpu_relax();
1794#endif
1795}
1796
1797#ifdef CONFIG_X86_64
1798static inline void setup_getcpu(int cpu)
1799{
1800 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
1801 struct desc_struct d = { };
1802
1803 if (boot_cpu_has(X86_FEATURE_RDTSCP))
1804 write_rdtscp_aux(cpudata);
1805
1806 /* Store CPU and node number in limit. */
1807 d.limit0 = cpudata;
1808 d.limit1 = cpudata >> 16;
1809
1810 d.type = 5; /* RO data, expand down, accessed */
1811 d.dpl = 3; /* Visible to user code */
1812 d.s = 1; /* Not a system segment */
1813 d.p = 1; /* Present */
1814 d.d = 1; /* 32-bit */
1815
1816 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
1817}
1818
1819static inline void ucode_cpu_init(int cpu)
1820{
1821 if (cpu)
1822 load_ucode_ap();
1823}
1824
1825static inline void tss_setup_ist(struct tss_struct *tss)
1826{
1827 /* Set up the per-CPU TSS IST stacks */
1828 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
1829 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
1830 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
1831 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
1832}
1833
1834#else /* CONFIG_X86_64 */
1835
1836static inline void setup_getcpu(int cpu) { }
1837
1838static inline void ucode_cpu_init(int cpu)
1839{
1840 show_ucode_info_early();
1841}
1842
1843static inline void tss_setup_ist(struct tss_struct *tss) { }
1844
1845#endif /* !CONFIG_X86_64 */
1846
1847static inline void tss_setup_io_bitmap(struct tss_struct *tss)
1848{
1849 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
1850
1851#ifdef CONFIG_X86_IOPL_IOPERM
1852 tss->io_bitmap.prev_max = 0;
1853 tss->io_bitmap.prev_sequence = 0;
1854 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
1855 /*
1856 * Invalidate the extra array entry past the end of the all
1857 * permission bitmap as required by the hardware.
1858 */
1859 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
1860#endif
1861}
1862
1863/*
1864 * cpu_init() initializes state that is per-CPU. Some data is already
1865 * initialized (naturally) in the bootstrap process, such as the GDT
1866 * and IDT. We reload them nevertheless, this function acts as a
1867 * 'CPU state barrier', nothing should get across.
1868 */
1869void cpu_init(void)
1870{
1871 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
1872 struct task_struct *cur = current;
1873 int cpu = raw_smp_processor_id();
1874
1875 wait_for_master_cpu(cpu);
1876
1877 ucode_cpu_init(cpu);
1878
1879#ifdef CONFIG_NUMA
1880 if (this_cpu_read(numa_node) == 0 &&
1881 early_cpu_to_node(cpu) != NUMA_NO_NODE)
1882 set_numa_node(early_cpu_to_node(cpu));
1883#endif
1884 setup_getcpu(cpu);
1885
1886 pr_debug("Initializing CPU#%d\n", cpu);
1887
1888 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
1889 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
1890 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1891
1892 /*
1893 * Initialize the per-CPU GDT with the boot GDT,
1894 * and set up the GDT descriptor:
1895 */
1896 switch_to_new_gdt(cpu);
1897 load_current_idt();
1898
1899 if (IS_ENABLED(CONFIG_X86_64)) {
1900 loadsegment(fs, 0);
1901 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1902 syscall_init();
1903
1904 wrmsrl(MSR_FS_BASE, 0);
1905 wrmsrl(MSR_KERNEL_GS_BASE, 0);
1906 barrier();
1907
1908 x2apic_setup();
1909 }
1910
1911 mmgrab(&init_mm);
1912 cur->active_mm = &init_mm;
1913 BUG_ON(cur->mm);
1914 initialize_tlbstate_and_flush();
1915 enter_lazy_tlb(&init_mm, cur);
1916
1917 /* Initialize the TSS. */
1918 tss_setup_ist(tss);
1919 tss_setup_io_bitmap(tss);
1920 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
1921
1922 load_TR_desc();
1923 /*
1924 * sp0 points to the entry trampoline stack regardless of what task
1925 * is running.
1926 */
1927 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
1928
1929 load_mm_ldt(&init_mm);
1930
1931 clear_all_debug_regs();
1932 dbg_restore_debug_regs();
1933
1934 doublefault_init_cpu_tss();
1935
1936 fpu__init_cpu();
1937
1938 if (is_uv_system())
1939 uv_cpu_init();
1940
1941 load_fixmap_gdt(cpu);
1942}
1943
1944/*
1945 * The microcode loader calls this upon late microcode load to recheck features,
1946 * only when microcode has been updated. Caller holds microcode_mutex and CPU
1947 * hotplug lock.
1948 */
1949void microcode_check(void)
1950{
1951 struct cpuinfo_x86 info;
1952
1953 perf_check_microcode();
1954
1955 /* Reload CPUID max function as it might've changed. */
1956 info.cpuid_level = cpuid_eax(0);
1957
1958 /*
1959 * Copy all capability leafs to pick up the synthetic ones so that
1960 * memcmp() below doesn't fail on that. The ones coming from CPUID will
1961 * get overwritten in get_cpu_cap().
1962 */
1963 memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability));
1964
1965 get_cpu_cap(&info);
1966
1967 if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)))
1968 return;
1969
1970 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
1971 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
1972}
1973
1974/*
1975 * Invoked from core CPU hotplug code after hotplug operations
1976 */
1977void arch_smt_update(void)
1978{
1979 /* Handle the speculative execution misfeatures */
1980 cpu_bugs_smt_update();
1981 /* Check whether IPI broadcasting can be enabled */
1982 apic_smt_update();
1983}