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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <linux/uaccess.h>
30
31/* Hardware capabilities */
32unsigned int elf_hwcap __read_mostly;
33EXPORT_SYMBOL_GPL(elf_hwcap);
34
35#ifdef CONFIG_MIPS_FP_SUPPORT
36
37/*
38 * Get the FPU Implementation/Revision.
39 */
40static inline unsigned long cpu_get_fpu_id(void)
41{
42 unsigned long tmp, fpu_id;
43
44 tmp = read_c0_status();
45 __enable_fpu(FPU_AS_IS);
46 fpu_id = read_32bit_cp1_register(CP1_REVISION);
47 write_c0_status(tmp);
48 return fpu_id;
49}
50
51/*
52 * Check if the CPU has an external FPU.
53 */
54static inline int __cpu_has_fpu(void)
55{
56 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
57}
58
59/*
60 * Determine the FCSR mask for FPU hardware.
61 */
62static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
63{
64 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
65
66 fcsr = c->fpu_csr31;
67 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
68
69 sr = read_c0_status();
70 __enable_fpu(FPU_AS_IS);
71
72 fcsr0 = fcsr & mask;
73 write_32bit_cp1_register(CP1_STATUS, fcsr0);
74 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
75
76 fcsr1 = fcsr | ~mask;
77 write_32bit_cp1_register(CP1_STATUS, fcsr1);
78 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
79
80 write_32bit_cp1_register(CP1_STATUS, fcsr);
81
82 write_c0_status(sr);
83
84 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
85}
86
87/*
88 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
89 * supported by FPU hardware.
90 */
91static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
92{
93 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
94 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
95 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
96 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
97
98 sr = read_c0_status();
99 __enable_fpu(FPU_AS_IS);
100
101 fir = read_32bit_cp1_register(CP1_REVISION);
102 if (fir & MIPS_FPIR_HAS2008) {
103 fcsr = read_32bit_cp1_register(CP1_STATUS);
104
105 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
106 write_32bit_cp1_register(CP1_STATUS, fcsr0);
107 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
108
109 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
110 write_32bit_cp1_register(CP1_STATUS, fcsr1);
111 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
112
113 write_32bit_cp1_register(CP1_STATUS, fcsr);
114
115 if (!(fcsr0 & FPU_CSR_NAN2008))
116 c->options |= MIPS_CPU_NAN_LEGACY;
117 if (fcsr1 & FPU_CSR_NAN2008)
118 c->options |= MIPS_CPU_NAN_2008;
119
120 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
121 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
122 else
123 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
124
125 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
126 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
127 else
128 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
129 } else {
130 c->options |= MIPS_CPU_NAN_LEGACY;
131 }
132
133 write_c0_status(sr);
134 } else {
135 c->options |= MIPS_CPU_NAN_LEGACY;
136 }
137}
138
139/*
140 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
141 * ABS.fmt/NEG.fmt execution mode.
142 */
143static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
144
145/*
146 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
147 * to support by the FPU emulator according to the IEEE 754 conformance
148 * mode selected. Note that "relaxed" straps the emulator so that it
149 * allows 2008-NaN binaries even for legacy processors.
150 */
151static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
152{
153 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
154 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
155 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
156
157 switch (ieee754) {
158 case STRICT:
159 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
160 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
161 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
162 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
163 } else {
164 c->options |= MIPS_CPU_NAN_LEGACY;
165 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
166 }
167 break;
168 case LEGACY:
169 c->options |= MIPS_CPU_NAN_LEGACY;
170 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
171 break;
172 case STD2008:
173 c->options |= MIPS_CPU_NAN_2008;
174 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
175 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
176 break;
177 case RELAXED:
178 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
179 break;
180 }
181}
182
183/*
184 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
185 * according to the "ieee754=" parameter.
186 */
187static void cpu_set_nan_2008(struct cpuinfo_mips *c)
188{
189 switch (ieee754) {
190 case STRICT:
191 mips_use_nan_legacy = !!cpu_has_nan_legacy;
192 mips_use_nan_2008 = !!cpu_has_nan_2008;
193 break;
194 case LEGACY:
195 mips_use_nan_legacy = !!cpu_has_nan_legacy;
196 mips_use_nan_2008 = !cpu_has_nan_legacy;
197 break;
198 case STD2008:
199 mips_use_nan_legacy = !cpu_has_nan_2008;
200 mips_use_nan_2008 = !!cpu_has_nan_2008;
201 break;
202 case RELAXED:
203 mips_use_nan_legacy = true;
204 mips_use_nan_2008 = true;
205 break;
206 }
207}
208
209/*
210 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
211 * settings:
212 *
213 * strict: accept binaries that request a NaN encoding supported by the FPU
214 * legacy: only accept legacy-NaN binaries
215 * 2008: only accept 2008-NaN binaries
216 * relaxed: accept any binaries regardless of whether supported by the FPU
217 */
218static int __init ieee754_setup(char *s)
219{
220 if (!s)
221 return -1;
222 else if (!strcmp(s, "strict"))
223 ieee754 = STRICT;
224 else if (!strcmp(s, "legacy"))
225 ieee754 = LEGACY;
226 else if (!strcmp(s, "2008"))
227 ieee754 = STD2008;
228 else if (!strcmp(s, "relaxed"))
229 ieee754 = RELAXED;
230 else
231 return -1;
232
233 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
234 cpu_set_nofpu_2008(&boot_cpu_data);
235 cpu_set_nan_2008(&boot_cpu_data);
236
237 return 0;
238}
239
240early_param("ieee754", ieee754_setup);
241
242/*
243 * Set the FIR feature flags for the FPU emulator.
244 */
245static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
246{
247 u32 value;
248
249 value = 0;
250 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
251 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
252 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
253 value |= MIPS_FPIR_D | MIPS_FPIR_S;
254 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
255 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
256 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
257 if (c->options & MIPS_CPU_NAN_2008)
258 value |= MIPS_FPIR_HAS2008;
259 c->fpu_id = value;
260}
261
262/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
263static unsigned int mips_nofpu_msk31;
264
265/*
266 * Set options for FPU hardware.
267 */
268static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
269{
270 c->fpu_id = cpu_get_fpu_id();
271 mips_nofpu_msk31 = c->fpu_msk31;
272
273 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
274 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
275 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
276 if (c->fpu_id & MIPS_FPIR_3D)
277 c->ases |= MIPS_ASE_MIPS3D;
278 if (c->fpu_id & MIPS_FPIR_UFRP)
279 c->options |= MIPS_CPU_UFR;
280 if (c->fpu_id & MIPS_FPIR_FREP)
281 c->options |= MIPS_CPU_FRE;
282 }
283
284 cpu_set_fpu_fcsr_mask(c);
285 cpu_set_fpu_2008(c);
286 cpu_set_nan_2008(c);
287}
288
289/*
290 * Set options for the FPU emulator.
291 */
292static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
293{
294 c->options &= ~MIPS_CPU_FPU;
295 c->fpu_msk31 = mips_nofpu_msk31;
296
297 cpu_set_nofpu_2008(c);
298 cpu_set_nan_2008(c);
299 cpu_set_nofpu_id(c);
300}
301
302static int mips_fpu_disabled;
303
304static int __init fpu_disable(char *s)
305{
306 cpu_set_nofpu_opts(&boot_cpu_data);
307 mips_fpu_disabled = 1;
308
309 return 1;
310}
311
312__setup("nofpu", fpu_disable);
313
314#else /* !CONFIG_MIPS_FP_SUPPORT */
315
316#define mips_fpu_disabled 1
317
318static inline unsigned long cpu_get_fpu_id(void)
319{
320 return FPIR_IMP_NONE;
321}
322
323static inline int __cpu_has_fpu(void)
324{
325 return 0;
326}
327
328static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
329{
330 /* no-op */
331}
332
333static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
334{
335 /* no-op */
336}
337
338#endif /* CONFIG_MIPS_FP_SUPPORT */
339
340static inline unsigned long cpu_get_msa_id(void)
341{
342 unsigned long status, msa_id;
343
344 status = read_c0_status();
345 __enable_fpu(FPU_64BIT);
346 enable_msa();
347 msa_id = read_msa_ir();
348 disable_msa();
349 write_c0_status(status);
350 return msa_id;
351}
352
353static int mips_dsp_disabled;
354
355static int __init dsp_disable(char *s)
356{
357 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
358 mips_dsp_disabled = 1;
359
360 return 1;
361}
362
363__setup("nodsp", dsp_disable);
364
365static int mips_htw_disabled;
366
367static int __init htw_disable(char *s)
368{
369 mips_htw_disabled = 1;
370 cpu_data[0].options &= ~MIPS_CPU_HTW;
371 write_c0_pwctl(read_c0_pwctl() &
372 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
373
374 return 1;
375}
376
377__setup("nohtw", htw_disable);
378
379static int mips_ftlb_disabled;
380static int mips_has_ftlb_configured;
381
382enum ftlb_flags {
383 FTLB_EN = 1 << 0,
384 FTLB_SET_PROB = 1 << 1,
385};
386
387static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
388
389static int __init ftlb_disable(char *s)
390{
391 unsigned int config4, mmuextdef;
392
393 /*
394 * If the core hasn't done any FTLB configuration, there is nothing
395 * for us to do here.
396 */
397 if (!mips_has_ftlb_configured)
398 return 1;
399
400 /* Disable it in the boot cpu */
401 if (set_ftlb_enable(&cpu_data[0], 0)) {
402 pr_warn("Can't turn FTLB off\n");
403 return 1;
404 }
405
406 config4 = read_c0_config4();
407
408 /* Check that FTLB has been disabled */
409 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
410 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
411 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
412 /* This should never happen */
413 pr_warn("FTLB could not be disabled!\n");
414 return 1;
415 }
416
417 mips_ftlb_disabled = 1;
418 mips_has_ftlb_configured = 0;
419
420 /*
421 * noftlb is mainly used for debug purposes so print
422 * an informative message instead of using pr_debug()
423 */
424 pr_info("FTLB has been disabled\n");
425
426 /*
427 * Some of these bits are duplicated in the decode_config4.
428 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
429 * once FTLB has been disabled so undo what decode_config4 did.
430 */
431 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
432 cpu_data[0].tlbsizeftlbsets;
433 cpu_data[0].tlbsizeftlbsets = 0;
434 cpu_data[0].tlbsizeftlbways = 0;
435
436 return 1;
437}
438
439__setup("noftlb", ftlb_disable);
440
441/*
442 * Check if the CPU has per tc perf counters
443 */
444static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
445{
446 if (read_c0_config7() & MTI_CONF7_PTC)
447 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
448}
449
450static inline void check_errata(void)
451{
452 struct cpuinfo_mips *c = ¤t_cpu_data;
453
454 switch (current_cpu_type()) {
455 case CPU_34K:
456 /*
457 * Erratum "RPS May Cause Incorrect Instruction Execution"
458 * This code only handles VPE0, any SMP/RTOS code
459 * making use of VPE1 will be responsable for that VPE.
460 */
461 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
462 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
463 break;
464 default:
465 break;
466 }
467}
468
469void __init check_bugs32(void)
470{
471 check_errata();
472}
473
474/*
475 * Probe whether cpu has config register by trying to play with
476 * alternate cache bit and see whether it matters.
477 * It's used by cpu_probe to distinguish between R3000A and R3081.
478 */
479static inline int cpu_has_confreg(void)
480{
481#ifdef CONFIG_CPU_R3000
482 extern unsigned long r3k_cache_size(unsigned long);
483 unsigned long size1, size2;
484 unsigned long cfg = read_c0_conf();
485
486 size1 = r3k_cache_size(ST0_ISC);
487 write_c0_conf(cfg ^ R30XX_CONF_AC);
488 size2 = r3k_cache_size(ST0_ISC);
489 write_c0_conf(cfg);
490 return size1 != size2;
491#else
492 return 0;
493#endif
494}
495
496static inline void set_elf_platform(int cpu, const char *plat)
497{
498 if (cpu == 0)
499 __elf_platform = plat;
500}
501
502static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
503{
504#ifdef __NEED_VMBITS_PROBE
505 write_c0_entryhi(0x3fffffffffffe000ULL);
506 back_to_back_c0_hazard();
507 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
508#endif
509}
510
511static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
512{
513 switch (isa) {
514 case MIPS_CPU_ISA_M64R2:
515 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
516 /* fall through */
517 case MIPS_CPU_ISA_M64R1:
518 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
519 /* fall through */
520 case MIPS_CPU_ISA_V:
521 c->isa_level |= MIPS_CPU_ISA_V;
522 /* fall through */
523 case MIPS_CPU_ISA_IV:
524 c->isa_level |= MIPS_CPU_ISA_IV;
525 /* fall through */
526 case MIPS_CPU_ISA_III:
527 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
528 break;
529
530 /* R6 incompatible with everything else */
531 case MIPS_CPU_ISA_M64R6:
532 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
533 /* fall through */
534 case MIPS_CPU_ISA_M32R6:
535 c->isa_level |= MIPS_CPU_ISA_M32R6;
536 /* Break here so we don't add incompatible ISAs */
537 break;
538 case MIPS_CPU_ISA_M32R2:
539 c->isa_level |= MIPS_CPU_ISA_M32R2;
540 /* fall through */
541 case MIPS_CPU_ISA_M32R1:
542 c->isa_level |= MIPS_CPU_ISA_M32R1;
543 /* fall through */
544 case MIPS_CPU_ISA_II:
545 c->isa_level |= MIPS_CPU_ISA_II;
546 break;
547 }
548}
549
550static char unknown_isa[] = KERN_ERR \
551 "Unsupported ISA type, c0.config0: %d.";
552
553static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
554{
555
556 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
557
558 /*
559 * 0 = All TLBWR instructions go to FTLB
560 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
561 * FTLB and 1 goes to the VTLB.
562 * 2 = 7:1: As above with 7:1 ratio.
563 * 3 = 3:1: As above with 3:1 ratio.
564 *
565 * Use the linear midpoint as the probability threshold.
566 */
567 if (probability >= 12)
568 return 1;
569 else if (probability >= 6)
570 return 2;
571 else
572 /*
573 * So FTLB is less than 4 times bigger than VTLB.
574 * A 3:1 ratio can still be useful though.
575 */
576 return 3;
577}
578
579static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
580{
581 unsigned int config;
582
583 /* It's implementation dependent how the FTLB can be enabled */
584 switch (c->cputype) {
585 case CPU_PROAPTIV:
586 case CPU_P5600:
587 case CPU_P6600:
588 /* proAptiv & related cores use Config6 to enable the FTLB */
589 config = read_c0_config6();
590
591 if (flags & FTLB_EN)
592 config |= MIPS_CONF6_FTLBEN;
593 else
594 config &= ~MIPS_CONF6_FTLBEN;
595
596 if (flags & FTLB_SET_PROB) {
597 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
598 config |= calculate_ftlb_probability(c)
599 << MIPS_CONF6_FTLBP_SHIFT;
600 }
601
602 write_c0_config6(config);
603 back_to_back_c0_hazard();
604 break;
605 case CPU_I6400:
606 case CPU_I6500:
607 /* There's no way to disable the FTLB */
608 if (!(flags & FTLB_EN))
609 return 1;
610 return 0;
611 case CPU_LOONGSON3:
612 /* Flush ITLB, DTLB, VTLB and FTLB */
613 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
614 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
615 /* Loongson-3 cores use Config6 to enable the FTLB */
616 config = read_c0_config6();
617 if (flags & FTLB_EN)
618 /* Enable FTLB */
619 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
620 else
621 /* Disable FTLB */
622 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
623 break;
624 default:
625 return 1;
626 }
627
628 return 0;
629}
630
631static inline unsigned int decode_config0(struct cpuinfo_mips *c)
632{
633 unsigned int config0;
634 int isa, mt;
635
636 config0 = read_c0_config();
637
638 /*
639 * Look for Standard TLB or Dual VTLB and FTLB
640 */
641 mt = config0 & MIPS_CONF_MT;
642 if (mt == MIPS_CONF_MT_TLB)
643 c->options |= MIPS_CPU_TLB;
644 else if (mt == MIPS_CONF_MT_FTLB)
645 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
646
647 isa = (config0 & MIPS_CONF_AT) >> 13;
648 switch (isa) {
649 case 0:
650 switch ((config0 & MIPS_CONF_AR) >> 10) {
651 case 0:
652 set_isa(c, MIPS_CPU_ISA_M32R1);
653 break;
654 case 1:
655 set_isa(c, MIPS_CPU_ISA_M32R2);
656 break;
657 case 2:
658 set_isa(c, MIPS_CPU_ISA_M32R6);
659 break;
660 default:
661 goto unknown;
662 }
663 break;
664 case 2:
665 switch ((config0 & MIPS_CONF_AR) >> 10) {
666 case 0:
667 set_isa(c, MIPS_CPU_ISA_M64R1);
668 break;
669 case 1:
670 set_isa(c, MIPS_CPU_ISA_M64R2);
671 break;
672 case 2:
673 set_isa(c, MIPS_CPU_ISA_M64R6);
674 break;
675 default:
676 goto unknown;
677 }
678 break;
679 default:
680 goto unknown;
681 }
682
683 return config0 & MIPS_CONF_M;
684
685unknown:
686 panic(unknown_isa, config0);
687}
688
689static inline unsigned int decode_config1(struct cpuinfo_mips *c)
690{
691 unsigned int config1;
692
693 config1 = read_c0_config1();
694
695 if (config1 & MIPS_CONF1_MD)
696 c->ases |= MIPS_ASE_MDMX;
697 if (config1 & MIPS_CONF1_PC)
698 c->options |= MIPS_CPU_PERF;
699 if (config1 & MIPS_CONF1_WR)
700 c->options |= MIPS_CPU_WATCH;
701 if (config1 & MIPS_CONF1_CA)
702 c->ases |= MIPS_ASE_MIPS16;
703 if (config1 & MIPS_CONF1_EP)
704 c->options |= MIPS_CPU_EJTAG;
705 if (config1 & MIPS_CONF1_FP) {
706 c->options |= MIPS_CPU_FPU;
707 c->options |= MIPS_CPU_32FPR;
708 }
709 if (cpu_has_tlb) {
710 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
711 c->tlbsizevtlb = c->tlbsize;
712 c->tlbsizeftlbsets = 0;
713 }
714
715 return config1 & MIPS_CONF_M;
716}
717
718static inline unsigned int decode_config2(struct cpuinfo_mips *c)
719{
720 unsigned int config2;
721
722 config2 = read_c0_config2();
723
724 if (config2 & MIPS_CONF2_SL)
725 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
726
727 return config2 & MIPS_CONF_M;
728}
729
730static inline unsigned int decode_config3(struct cpuinfo_mips *c)
731{
732 unsigned int config3;
733
734 config3 = read_c0_config3();
735
736 if (config3 & MIPS_CONF3_SM) {
737 c->ases |= MIPS_ASE_SMARTMIPS;
738 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
739 }
740 if (config3 & MIPS_CONF3_RXI)
741 c->options |= MIPS_CPU_RIXI;
742 if (config3 & MIPS_CONF3_CTXTC)
743 c->options |= MIPS_CPU_CTXTC;
744 if (config3 & MIPS_CONF3_DSP)
745 c->ases |= MIPS_ASE_DSP;
746 if (config3 & MIPS_CONF3_DSP2P) {
747 c->ases |= MIPS_ASE_DSP2P;
748 if (cpu_has_mips_r6)
749 c->ases |= MIPS_ASE_DSP3;
750 }
751 if (config3 & MIPS_CONF3_VINT)
752 c->options |= MIPS_CPU_VINT;
753 if (config3 & MIPS_CONF3_VEIC)
754 c->options |= MIPS_CPU_VEIC;
755 if (config3 & MIPS_CONF3_LPA)
756 c->options |= MIPS_CPU_LPA;
757 if (config3 & MIPS_CONF3_MT)
758 c->ases |= MIPS_ASE_MIPSMT;
759 if (config3 & MIPS_CONF3_ULRI)
760 c->options |= MIPS_CPU_ULRI;
761 if (config3 & MIPS_CONF3_ISA)
762 c->options |= MIPS_CPU_MICROMIPS;
763 if (config3 & MIPS_CONF3_VZ)
764 c->ases |= MIPS_ASE_VZ;
765 if (config3 & MIPS_CONF3_SC)
766 c->options |= MIPS_CPU_SEGMENTS;
767 if (config3 & MIPS_CONF3_BI)
768 c->options |= MIPS_CPU_BADINSTR;
769 if (config3 & MIPS_CONF3_BP)
770 c->options |= MIPS_CPU_BADINSTRP;
771 if (config3 & MIPS_CONF3_MSA)
772 c->ases |= MIPS_ASE_MSA;
773 if (config3 & MIPS_CONF3_PW) {
774 c->htw_seq = 0;
775 c->options |= MIPS_CPU_HTW;
776 }
777 if (config3 & MIPS_CONF3_CDMM)
778 c->options |= MIPS_CPU_CDMM;
779 if (config3 & MIPS_CONF3_SP)
780 c->options |= MIPS_CPU_SP;
781
782 return config3 & MIPS_CONF_M;
783}
784
785static inline unsigned int decode_config4(struct cpuinfo_mips *c)
786{
787 unsigned int config4;
788 unsigned int newcf4;
789 unsigned int mmuextdef;
790 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
791 unsigned long asid_mask;
792
793 config4 = read_c0_config4();
794
795 if (cpu_has_tlb) {
796 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
797 c->options |= MIPS_CPU_TLBINV;
798
799 /*
800 * R6 has dropped the MMUExtDef field from config4.
801 * On R6 the fields always describe the FTLB, and only if it is
802 * present according to Config.MT.
803 */
804 if (!cpu_has_mips_r6)
805 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
806 else if (cpu_has_ftlb)
807 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
808 else
809 mmuextdef = 0;
810
811 switch (mmuextdef) {
812 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
813 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
814 c->tlbsizevtlb = c->tlbsize;
815 break;
816 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
817 c->tlbsizevtlb +=
818 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
819 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
820 c->tlbsize = c->tlbsizevtlb;
821 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
822 /* fall through */
823 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
824 if (mips_ftlb_disabled)
825 break;
826 newcf4 = (config4 & ~ftlb_page) |
827 (page_size_ftlb(mmuextdef) <<
828 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
829 write_c0_config4(newcf4);
830 back_to_back_c0_hazard();
831 config4 = read_c0_config4();
832 if (config4 != newcf4) {
833 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
834 PAGE_SIZE, config4);
835 /* Switch FTLB off */
836 set_ftlb_enable(c, 0);
837 mips_ftlb_disabled = 1;
838 break;
839 }
840 c->tlbsizeftlbsets = 1 <<
841 ((config4 & MIPS_CONF4_FTLBSETS) >>
842 MIPS_CONF4_FTLBSETS_SHIFT);
843 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
844 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
845 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
846 mips_has_ftlb_configured = 1;
847 break;
848 }
849 }
850
851 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
852 >> MIPS_CONF4_KSCREXIST_SHIFT;
853
854 asid_mask = MIPS_ENTRYHI_ASID;
855 if (config4 & MIPS_CONF4_AE)
856 asid_mask |= MIPS_ENTRYHI_ASIDX;
857 set_cpu_asid_mask(c, asid_mask);
858
859 /*
860 * Warn if the computed ASID mask doesn't match the mask the kernel
861 * is built for. This may indicate either a serious problem or an
862 * easy optimisation opportunity, but either way should be addressed.
863 */
864 WARN_ON(asid_mask != cpu_asid_mask(c));
865
866 return config4 & MIPS_CONF_M;
867}
868
869static inline unsigned int decode_config5(struct cpuinfo_mips *c)
870{
871 unsigned int config5, max_mmid_width;
872 unsigned long asid_mask;
873
874 config5 = read_c0_config5();
875 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
876
877 if (cpu_has_mips_r6) {
878 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
879 config5 |= MIPS_CONF5_MI;
880 else
881 config5 &= ~MIPS_CONF5_MI;
882 }
883
884 write_c0_config5(config5);
885
886 if (config5 & MIPS_CONF5_EVA)
887 c->options |= MIPS_CPU_EVA;
888 if (config5 & MIPS_CONF5_MRP)
889 c->options |= MIPS_CPU_MAAR;
890 if (config5 & MIPS_CONF5_LLB)
891 c->options |= MIPS_CPU_RW_LLB;
892 if (config5 & MIPS_CONF5_MVH)
893 c->options |= MIPS_CPU_MVH;
894 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
895 c->options |= MIPS_CPU_VP;
896 if (config5 & MIPS_CONF5_CA2)
897 c->ases |= MIPS_ASE_MIPS16E2;
898
899 if (config5 & MIPS_CONF5_CRCP)
900 elf_hwcap |= HWCAP_MIPS_CRC32;
901
902 if (cpu_has_mips_r6) {
903 /* Ensure the write to config5 above takes effect */
904 back_to_back_c0_hazard();
905
906 /* Check whether we successfully enabled MMID support */
907 config5 = read_c0_config5();
908 if (config5 & MIPS_CONF5_MI)
909 c->options |= MIPS_CPU_MMID;
910
911 /*
912 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
913 * for the CPU we're running on, or if CPUs in an SMP system
914 * have inconsistent MMID support.
915 */
916 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
917
918 if (cpu_has_mmid) {
919 write_c0_memorymapid(~0ul);
920 back_to_back_c0_hazard();
921 asid_mask = read_c0_memorymapid();
922
923 /*
924 * We maintain a bitmap to track MMID allocation, and
925 * need a sensible upper bound on the size of that
926 * bitmap. The initial CPU with MMID support (I6500)
927 * supports 16 bit MMIDs, which gives us an 8KiB
928 * bitmap. The architecture recommends that hardware
929 * support 32 bit MMIDs, which would give us a 512MiB
930 * bitmap - that's too big in most cases.
931 *
932 * Cap MMID width at 16 bits for now & we can revisit
933 * this if & when hardware supports anything wider.
934 */
935 max_mmid_width = 16;
936 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
937 pr_info("Capping MMID width at %d bits",
938 max_mmid_width);
939 asid_mask = GENMASK(max_mmid_width - 1, 0);
940 }
941
942 set_cpu_asid_mask(c, asid_mask);
943 }
944 }
945
946 return config5 & MIPS_CONF_M;
947}
948
949static void decode_configs(struct cpuinfo_mips *c)
950{
951 int ok;
952
953 /* MIPS32 or MIPS64 compliant CPU. */
954 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
955 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
956
957 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
958
959 /* Enable FTLB if present and not disabled */
960 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
961
962 ok = decode_config0(c); /* Read Config registers. */
963 BUG_ON(!ok); /* Arch spec violation! */
964 if (ok)
965 ok = decode_config1(c);
966 if (ok)
967 ok = decode_config2(c);
968 if (ok)
969 ok = decode_config3(c);
970 if (ok)
971 ok = decode_config4(c);
972 if (ok)
973 ok = decode_config5(c);
974
975 /* Probe the EBase.WG bit */
976 if (cpu_has_mips_r2_r6) {
977 u64 ebase;
978 unsigned int status;
979
980 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
981 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
982 : (s32)read_c0_ebase();
983 if (ebase & MIPS_EBASE_WG) {
984 /* WG bit already set, we can avoid the clumsy probe */
985 c->options |= MIPS_CPU_EBASE_WG;
986 } else {
987 /* Its UNDEFINED to change EBase while BEV=0 */
988 status = read_c0_status();
989 write_c0_status(status | ST0_BEV);
990 irq_enable_hazard();
991 /*
992 * On pre-r6 cores, this may well clobber the upper bits
993 * of EBase. This is hard to avoid without potentially
994 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
995 */
996 if (cpu_has_mips64r6)
997 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
998 else
999 write_c0_ebase(ebase | MIPS_EBASE_WG);
1000 back_to_back_c0_hazard();
1001 /* Restore BEV */
1002 write_c0_status(status);
1003 if (read_c0_ebase() & MIPS_EBASE_WG) {
1004 c->options |= MIPS_CPU_EBASE_WG;
1005 write_c0_ebase(ebase);
1006 }
1007 }
1008 }
1009
1010 /* configure the FTLB write probability */
1011 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1012
1013 mips_probe_watch_registers(c);
1014
1015#ifndef CONFIG_MIPS_CPS
1016 if (cpu_has_mips_r2_r6) {
1017 unsigned int core;
1018
1019 core = get_ebase_cpunum();
1020 if (cpu_has_mipsmt)
1021 core >>= fls(core_nvpes()) - 1;
1022 cpu_set_core(c, core);
1023 }
1024#endif
1025}
1026
1027/*
1028 * Probe for certain guest capabilities by writing config bits and reading back.
1029 * Finally write back the original value.
1030 */
1031#define probe_gc0_config(name, maxconf, bits) \
1032do { \
1033 unsigned int tmp; \
1034 tmp = read_gc0_##name(); \
1035 write_gc0_##name(tmp | (bits)); \
1036 back_to_back_c0_hazard(); \
1037 maxconf = read_gc0_##name(); \
1038 write_gc0_##name(tmp); \
1039} while (0)
1040
1041/*
1042 * Probe for dynamic guest capabilities by changing certain config bits and
1043 * reading back to see if they change. Finally write back the original value.
1044 */
1045#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
1046do { \
1047 maxconf = read_gc0_##name(); \
1048 write_gc0_##name(maxconf ^ (bits)); \
1049 back_to_back_c0_hazard(); \
1050 dynconf = maxconf ^ read_gc0_##name(); \
1051 write_gc0_##name(maxconf); \
1052 maxconf |= dynconf; \
1053} while (0)
1054
1055static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1056{
1057 unsigned int config0;
1058
1059 probe_gc0_config(config, config0, MIPS_CONF_M);
1060
1061 if (config0 & MIPS_CONF_M)
1062 c->guest.conf |= BIT(1);
1063 return config0 & MIPS_CONF_M;
1064}
1065
1066static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1067{
1068 unsigned int config1, config1_dyn;
1069
1070 probe_gc0_config_dyn(config1, config1, config1_dyn,
1071 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1072 MIPS_CONF1_FP);
1073
1074 if (config1 & MIPS_CONF1_FP)
1075 c->guest.options |= MIPS_CPU_FPU;
1076 if (config1_dyn & MIPS_CONF1_FP)
1077 c->guest.options_dyn |= MIPS_CPU_FPU;
1078
1079 if (config1 & MIPS_CONF1_WR)
1080 c->guest.options |= MIPS_CPU_WATCH;
1081 if (config1_dyn & MIPS_CONF1_WR)
1082 c->guest.options_dyn |= MIPS_CPU_WATCH;
1083
1084 if (config1 & MIPS_CONF1_PC)
1085 c->guest.options |= MIPS_CPU_PERF;
1086 if (config1_dyn & MIPS_CONF1_PC)
1087 c->guest.options_dyn |= MIPS_CPU_PERF;
1088
1089 if (config1 & MIPS_CONF_M)
1090 c->guest.conf |= BIT(2);
1091 return config1 & MIPS_CONF_M;
1092}
1093
1094static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1095{
1096 unsigned int config2;
1097
1098 probe_gc0_config(config2, config2, MIPS_CONF_M);
1099
1100 if (config2 & MIPS_CONF_M)
1101 c->guest.conf |= BIT(3);
1102 return config2 & MIPS_CONF_M;
1103}
1104
1105static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1106{
1107 unsigned int config3, config3_dyn;
1108
1109 probe_gc0_config_dyn(config3, config3, config3_dyn,
1110 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1111 MIPS_CONF3_CTXTC);
1112
1113 if (config3 & MIPS_CONF3_CTXTC)
1114 c->guest.options |= MIPS_CPU_CTXTC;
1115 if (config3_dyn & MIPS_CONF3_CTXTC)
1116 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1117
1118 if (config3 & MIPS_CONF3_PW)
1119 c->guest.options |= MIPS_CPU_HTW;
1120
1121 if (config3 & MIPS_CONF3_ULRI)
1122 c->guest.options |= MIPS_CPU_ULRI;
1123
1124 if (config3 & MIPS_CONF3_SC)
1125 c->guest.options |= MIPS_CPU_SEGMENTS;
1126
1127 if (config3 & MIPS_CONF3_BI)
1128 c->guest.options |= MIPS_CPU_BADINSTR;
1129 if (config3 & MIPS_CONF3_BP)
1130 c->guest.options |= MIPS_CPU_BADINSTRP;
1131
1132 if (config3 & MIPS_CONF3_MSA)
1133 c->guest.ases |= MIPS_ASE_MSA;
1134 if (config3_dyn & MIPS_CONF3_MSA)
1135 c->guest.ases_dyn |= MIPS_ASE_MSA;
1136
1137 if (config3 & MIPS_CONF_M)
1138 c->guest.conf |= BIT(4);
1139 return config3 & MIPS_CONF_M;
1140}
1141
1142static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1143{
1144 unsigned int config4;
1145
1146 probe_gc0_config(config4, config4,
1147 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1148
1149 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1150 >> MIPS_CONF4_KSCREXIST_SHIFT;
1151
1152 if (config4 & MIPS_CONF_M)
1153 c->guest.conf |= BIT(5);
1154 return config4 & MIPS_CONF_M;
1155}
1156
1157static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1158{
1159 unsigned int config5, config5_dyn;
1160
1161 probe_gc0_config_dyn(config5, config5, config5_dyn,
1162 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1163
1164 if (config5 & MIPS_CONF5_MRP)
1165 c->guest.options |= MIPS_CPU_MAAR;
1166 if (config5_dyn & MIPS_CONF5_MRP)
1167 c->guest.options_dyn |= MIPS_CPU_MAAR;
1168
1169 if (config5 & MIPS_CONF5_LLB)
1170 c->guest.options |= MIPS_CPU_RW_LLB;
1171
1172 if (config5 & MIPS_CONF5_MVH)
1173 c->guest.options |= MIPS_CPU_MVH;
1174
1175 if (config5 & MIPS_CONF_M)
1176 c->guest.conf |= BIT(6);
1177 return config5 & MIPS_CONF_M;
1178}
1179
1180static inline void decode_guest_configs(struct cpuinfo_mips *c)
1181{
1182 unsigned int ok;
1183
1184 ok = decode_guest_config0(c);
1185 if (ok)
1186 ok = decode_guest_config1(c);
1187 if (ok)
1188 ok = decode_guest_config2(c);
1189 if (ok)
1190 ok = decode_guest_config3(c);
1191 if (ok)
1192 ok = decode_guest_config4(c);
1193 if (ok)
1194 decode_guest_config5(c);
1195}
1196
1197static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1198{
1199 unsigned int guestctl0, temp;
1200
1201 guestctl0 = read_c0_guestctl0();
1202
1203 if (guestctl0 & MIPS_GCTL0_G0E)
1204 c->options |= MIPS_CPU_GUESTCTL0EXT;
1205 if (guestctl0 & MIPS_GCTL0_G1)
1206 c->options |= MIPS_CPU_GUESTCTL1;
1207 if (guestctl0 & MIPS_GCTL0_G2)
1208 c->options |= MIPS_CPU_GUESTCTL2;
1209 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1210 c->options |= MIPS_CPU_GUESTID;
1211
1212 /*
1213 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1214 * first, otherwise all data accesses will be fully virtualised
1215 * as if they were performed by guest mode.
1216 */
1217 write_c0_guestctl1(0);
1218 tlbw_use_hazard();
1219
1220 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1221 back_to_back_c0_hazard();
1222 temp = read_c0_guestctl0();
1223
1224 if (temp & MIPS_GCTL0_DRG) {
1225 write_c0_guestctl0(guestctl0);
1226 c->options |= MIPS_CPU_DRG;
1227 }
1228 }
1229}
1230
1231static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1232{
1233 if (cpu_has_guestid) {
1234 /* determine the number of bits of GuestID available */
1235 write_c0_guestctl1(MIPS_GCTL1_ID);
1236 back_to_back_c0_hazard();
1237 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1238 >> MIPS_GCTL1_ID_SHIFT;
1239 write_c0_guestctl1(0);
1240 }
1241}
1242
1243static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1244{
1245 /* determine the number of bits of GTOffset available */
1246 write_c0_gtoffset(0xffffffff);
1247 back_to_back_c0_hazard();
1248 c->gtoffset_mask = read_c0_gtoffset();
1249 write_c0_gtoffset(0);
1250}
1251
1252static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1253{
1254 cpu_probe_guestctl0(c);
1255 if (cpu_has_guestctl1)
1256 cpu_probe_guestctl1(c);
1257
1258 cpu_probe_gtoffset(c);
1259
1260 decode_guest_configs(c);
1261}
1262
1263#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1264 | MIPS_CPU_COUNTER)
1265
1266static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1267{
1268 switch (c->processor_id & PRID_IMP_MASK) {
1269 case PRID_IMP_R2000:
1270 c->cputype = CPU_R2000;
1271 __cpu_name[cpu] = "R2000";
1272 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1273 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1274 MIPS_CPU_NOFPUEX;
1275 if (__cpu_has_fpu())
1276 c->options |= MIPS_CPU_FPU;
1277 c->tlbsize = 64;
1278 break;
1279 case PRID_IMP_R3000:
1280 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1281 if (cpu_has_confreg()) {
1282 c->cputype = CPU_R3081E;
1283 __cpu_name[cpu] = "R3081";
1284 } else {
1285 c->cputype = CPU_R3000A;
1286 __cpu_name[cpu] = "R3000A";
1287 }
1288 } else {
1289 c->cputype = CPU_R3000;
1290 __cpu_name[cpu] = "R3000";
1291 }
1292 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1293 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1294 MIPS_CPU_NOFPUEX;
1295 if (__cpu_has_fpu())
1296 c->options |= MIPS_CPU_FPU;
1297 c->tlbsize = 64;
1298 break;
1299 case PRID_IMP_R4000:
1300 if (read_c0_config() & CONF_SC) {
1301 if ((c->processor_id & PRID_REV_MASK) >=
1302 PRID_REV_R4400) {
1303 c->cputype = CPU_R4400PC;
1304 __cpu_name[cpu] = "R4400PC";
1305 } else {
1306 c->cputype = CPU_R4000PC;
1307 __cpu_name[cpu] = "R4000PC";
1308 }
1309 } else {
1310 int cca = read_c0_config() & CONF_CM_CMASK;
1311 int mc;
1312
1313 /*
1314 * SC and MC versions can't be reliably told apart,
1315 * but only the latter support coherent caching
1316 * modes so assume the firmware has set the KSEG0
1317 * coherency attribute reasonably (if uncached, we
1318 * assume SC).
1319 */
1320 switch (cca) {
1321 case CONF_CM_CACHABLE_CE:
1322 case CONF_CM_CACHABLE_COW:
1323 case CONF_CM_CACHABLE_CUW:
1324 mc = 1;
1325 break;
1326 default:
1327 mc = 0;
1328 break;
1329 }
1330 if ((c->processor_id & PRID_REV_MASK) >=
1331 PRID_REV_R4400) {
1332 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1333 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1334 } else {
1335 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1336 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1337 }
1338 }
1339
1340 set_isa(c, MIPS_CPU_ISA_III);
1341 c->fpu_msk31 |= FPU_CSR_CONDX;
1342 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1343 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1344 MIPS_CPU_LLSC;
1345 c->tlbsize = 48;
1346 break;
1347 case PRID_IMP_VR41XX:
1348 set_isa(c, MIPS_CPU_ISA_III);
1349 c->fpu_msk31 |= FPU_CSR_CONDX;
1350 c->options = R4K_OPTS;
1351 c->tlbsize = 32;
1352 switch (c->processor_id & 0xf0) {
1353 case PRID_REV_VR4111:
1354 c->cputype = CPU_VR4111;
1355 __cpu_name[cpu] = "NEC VR4111";
1356 break;
1357 case PRID_REV_VR4121:
1358 c->cputype = CPU_VR4121;
1359 __cpu_name[cpu] = "NEC VR4121";
1360 break;
1361 case PRID_REV_VR4122:
1362 if ((c->processor_id & 0xf) < 0x3) {
1363 c->cputype = CPU_VR4122;
1364 __cpu_name[cpu] = "NEC VR4122";
1365 } else {
1366 c->cputype = CPU_VR4181A;
1367 __cpu_name[cpu] = "NEC VR4181A";
1368 }
1369 break;
1370 case PRID_REV_VR4130:
1371 if ((c->processor_id & 0xf) < 0x4) {
1372 c->cputype = CPU_VR4131;
1373 __cpu_name[cpu] = "NEC VR4131";
1374 } else {
1375 c->cputype = CPU_VR4133;
1376 c->options |= MIPS_CPU_LLSC;
1377 __cpu_name[cpu] = "NEC VR4133";
1378 }
1379 break;
1380 default:
1381 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1382 c->cputype = CPU_VR41XX;
1383 __cpu_name[cpu] = "NEC Vr41xx";
1384 break;
1385 }
1386 break;
1387 case PRID_IMP_R4600:
1388 c->cputype = CPU_R4600;
1389 __cpu_name[cpu] = "R4600";
1390 set_isa(c, MIPS_CPU_ISA_III);
1391 c->fpu_msk31 |= FPU_CSR_CONDX;
1392 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1393 MIPS_CPU_LLSC;
1394 c->tlbsize = 48;
1395 break;
1396 #if 0
1397 case PRID_IMP_R4650:
1398 /*
1399 * This processor doesn't have an MMU, so it's not
1400 * "real easy" to run Linux on it. It is left purely
1401 * for documentation. Commented out because it shares
1402 * it's c0_prid id number with the TX3900.
1403 */
1404 c->cputype = CPU_R4650;
1405 __cpu_name[cpu] = "R4650";
1406 set_isa(c, MIPS_CPU_ISA_III);
1407 c->fpu_msk31 |= FPU_CSR_CONDX;
1408 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1409 c->tlbsize = 48;
1410 break;
1411 #endif
1412 case PRID_IMP_TX39:
1413 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1414 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1415
1416 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1417 c->cputype = CPU_TX3927;
1418 __cpu_name[cpu] = "TX3927";
1419 c->tlbsize = 64;
1420 } else {
1421 switch (c->processor_id & PRID_REV_MASK) {
1422 case PRID_REV_TX3912:
1423 c->cputype = CPU_TX3912;
1424 __cpu_name[cpu] = "TX3912";
1425 c->tlbsize = 32;
1426 break;
1427 case PRID_REV_TX3922:
1428 c->cputype = CPU_TX3922;
1429 __cpu_name[cpu] = "TX3922";
1430 c->tlbsize = 64;
1431 break;
1432 }
1433 }
1434 break;
1435 case PRID_IMP_R4700:
1436 c->cputype = CPU_R4700;
1437 __cpu_name[cpu] = "R4700";
1438 set_isa(c, MIPS_CPU_ISA_III);
1439 c->fpu_msk31 |= FPU_CSR_CONDX;
1440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1441 MIPS_CPU_LLSC;
1442 c->tlbsize = 48;
1443 break;
1444 case PRID_IMP_TX49:
1445 c->cputype = CPU_TX49XX;
1446 __cpu_name[cpu] = "R49XX";
1447 set_isa(c, MIPS_CPU_ISA_III);
1448 c->fpu_msk31 |= FPU_CSR_CONDX;
1449 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1450 if (!(c->processor_id & 0x08))
1451 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1452 c->tlbsize = 48;
1453 break;
1454 case PRID_IMP_R5000:
1455 c->cputype = CPU_R5000;
1456 __cpu_name[cpu] = "R5000";
1457 set_isa(c, MIPS_CPU_ISA_IV);
1458 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1459 MIPS_CPU_LLSC;
1460 c->tlbsize = 48;
1461 break;
1462 case PRID_IMP_R5500:
1463 c->cputype = CPU_R5500;
1464 __cpu_name[cpu] = "R5500";
1465 set_isa(c, MIPS_CPU_ISA_IV);
1466 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1467 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1468 c->tlbsize = 48;
1469 break;
1470 case PRID_IMP_NEVADA:
1471 c->cputype = CPU_NEVADA;
1472 __cpu_name[cpu] = "Nevada";
1473 set_isa(c, MIPS_CPU_ISA_IV);
1474 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1475 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1476 c->tlbsize = 48;
1477 break;
1478 case PRID_IMP_RM7000:
1479 c->cputype = CPU_RM7000;
1480 __cpu_name[cpu] = "RM7000";
1481 set_isa(c, MIPS_CPU_ISA_IV);
1482 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1483 MIPS_CPU_LLSC;
1484 /*
1485 * Undocumented RM7000: Bit 29 in the info register of
1486 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1487 * entries.
1488 *
1489 * 29 1 => 64 entry JTLB
1490 * 0 => 48 entry JTLB
1491 */
1492 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1493 break;
1494 case PRID_IMP_R10000:
1495 c->cputype = CPU_R10000;
1496 __cpu_name[cpu] = "R10000";
1497 set_isa(c, MIPS_CPU_ISA_IV);
1498 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1499 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1500 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1501 MIPS_CPU_LLSC;
1502 c->tlbsize = 64;
1503 break;
1504 case PRID_IMP_R12000:
1505 c->cputype = CPU_R12000;
1506 __cpu_name[cpu] = "R12000";
1507 set_isa(c, MIPS_CPU_ISA_IV);
1508 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1509 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1510 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1511 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1512 c->tlbsize = 64;
1513 break;
1514 case PRID_IMP_R14000:
1515 if (((c->processor_id >> 4) & 0x0f) > 2) {
1516 c->cputype = CPU_R16000;
1517 __cpu_name[cpu] = "R16000";
1518 } else {
1519 c->cputype = CPU_R14000;
1520 __cpu_name[cpu] = "R14000";
1521 }
1522 set_isa(c, MIPS_CPU_ISA_IV);
1523 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1524 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1525 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1526 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1527 c->tlbsize = 64;
1528 break;
1529 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1530 switch (c->processor_id & PRID_REV_MASK) {
1531 case PRID_REV_LOONGSON2E:
1532 c->cputype = CPU_LOONGSON2;
1533 __cpu_name[cpu] = "ICT Loongson-2";
1534 set_elf_platform(cpu, "loongson2e");
1535 set_isa(c, MIPS_CPU_ISA_III);
1536 c->fpu_msk31 |= FPU_CSR_CONDX;
1537 break;
1538 case PRID_REV_LOONGSON2F:
1539 c->cputype = CPU_LOONGSON2;
1540 __cpu_name[cpu] = "ICT Loongson-2";
1541 set_elf_platform(cpu, "loongson2f");
1542 set_isa(c, MIPS_CPU_ISA_III);
1543 c->fpu_msk31 |= FPU_CSR_CONDX;
1544 break;
1545 case PRID_REV_LOONGSON3A_R1:
1546 c->cputype = CPU_LOONGSON3;
1547 __cpu_name[cpu] = "ICT Loongson-3";
1548 set_elf_platform(cpu, "loongson3a");
1549 set_isa(c, MIPS_CPU_ISA_M64R1);
1550 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1551 MIPS_ASE_LOONGSON_EXT);
1552 break;
1553 case PRID_REV_LOONGSON3B_R1:
1554 case PRID_REV_LOONGSON3B_R2:
1555 c->cputype = CPU_LOONGSON3;
1556 __cpu_name[cpu] = "ICT Loongson-3";
1557 set_elf_platform(cpu, "loongson3b");
1558 set_isa(c, MIPS_CPU_ISA_M64R1);
1559 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1560 MIPS_ASE_LOONGSON_EXT);
1561 break;
1562 }
1563
1564 c->options = R4K_OPTS |
1565 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1566 MIPS_CPU_32FPR;
1567 c->tlbsize = 64;
1568 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1569 break;
1570 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1571 decode_configs(c);
1572
1573 c->cputype = CPU_LOONGSON1;
1574
1575 switch (c->processor_id & PRID_REV_MASK) {
1576 case PRID_REV_LOONGSON1B:
1577 __cpu_name[cpu] = "Loongson 1B";
1578 break;
1579 }
1580
1581 break;
1582 }
1583}
1584
1585static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1586{
1587 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1588 switch (c->processor_id & PRID_IMP_MASK) {
1589 case PRID_IMP_QEMU_GENERIC:
1590 c->writecombine = _CACHE_UNCACHED;
1591 c->cputype = CPU_QEMU_GENERIC;
1592 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1593 break;
1594 case PRID_IMP_4KC:
1595 c->cputype = CPU_4KC;
1596 c->writecombine = _CACHE_UNCACHED;
1597 __cpu_name[cpu] = "MIPS 4Kc";
1598 break;
1599 case PRID_IMP_4KEC:
1600 case PRID_IMP_4KECR2:
1601 c->cputype = CPU_4KEC;
1602 c->writecombine = _CACHE_UNCACHED;
1603 __cpu_name[cpu] = "MIPS 4KEc";
1604 break;
1605 case PRID_IMP_4KSC:
1606 case PRID_IMP_4KSD:
1607 c->cputype = CPU_4KSC;
1608 c->writecombine = _CACHE_UNCACHED;
1609 __cpu_name[cpu] = "MIPS 4KSc";
1610 break;
1611 case PRID_IMP_5KC:
1612 c->cputype = CPU_5KC;
1613 c->writecombine = _CACHE_UNCACHED;
1614 __cpu_name[cpu] = "MIPS 5Kc";
1615 break;
1616 case PRID_IMP_5KE:
1617 c->cputype = CPU_5KE;
1618 c->writecombine = _CACHE_UNCACHED;
1619 __cpu_name[cpu] = "MIPS 5KE";
1620 break;
1621 case PRID_IMP_20KC:
1622 c->cputype = CPU_20KC;
1623 c->writecombine = _CACHE_UNCACHED;
1624 __cpu_name[cpu] = "MIPS 20Kc";
1625 break;
1626 case PRID_IMP_24K:
1627 c->cputype = CPU_24K;
1628 c->writecombine = _CACHE_UNCACHED;
1629 __cpu_name[cpu] = "MIPS 24Kc";
1630 break;
1631 case PRID_IMP_24KE:
1632 c->cputype = CPU_24K;
1633 c->writecombine = _CACHE_UNCACHED;
1634 __cpu_name[cpu] = "MIPS 24KEc";
1635 break;
1636 case PRID_IMP_25KF:
1637 c->cputype = CPU_25KF;
1638 c->writecombine = _CACHE_UNCACHED;
1639 __cpu_name[cpu] = "MIPS 25Kc";
1640 break;
1641 case PRID_IMP_34K:
1642 c->cputype = CPU_34K;
1643 c->writecombine = _CACHE_UNCACHED;
1644 __cpu_name[cpu] = "MIPS 34Kc";
1645 cpu_set_mt_per_tc_perf(c);
1646 break;
1647 case PRID_IMP_74K:
1648 c->cputype = CPU_74K;
1649 c->writecombine = _CACHE_UNCACHED;
1650 __cpu_name[cpu] = "MIPS 74Kc";
1651 break;
1652 case PRID_IMP_M14KC:
1653 c->cputype = CPU_M14KC;
1654 c->writecombine = _CACHE_UNCACHED;
1655 __cpu_name[cpu] = "MIPS M14Kc";
1656 break;
1657 case PRID_IMP_M14KEC:
1658 c->cputype = CPU_M14KEC;
1659 c->writecombine = _CACHE_UNCACHED;
1660 __cpu_name[cpu] = "MIPS M14KEc";
1661 break;
1662 case PRID_IMP_1004K:
1663 c->cputype = CPU_1004K;
1664 c->writecombine = _CACHE_UNCACHED;
1665 __cpu_name[cpu] = "MIPS 1004Kc";
1666 cpu_set_mt_per_tc_perf(c);
1667 break;
1668 case PRID_IMP_1074K:
1669 c->cputype = CPU_1074K;
1670 c->writecombine = _CACHE_UNCACHED;
1671 __cpu_name[cpu] = "MIPS 1074Kc";
1672 break;
1673 case PRID_IMP_INTERAPTIV_UP:
1674 c->cputype = CPU_INTERAPTIV;
1675 __cpu_name[cpu] = "MIPS interAptiv";
1676 cpu_set_mt_per_tc_perf(c);
1677 break;
1678 case PRID_IMP_INTERAPTIV_MP:
1679 c->cputype = CPU_INTERAPTIV;
1680 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1681 cpu_set_mt_per_tc_perf(c);
1682 break;
1683 case PRID_IMP_PROAPTIV_UP:
1684 c->cputype = CPU_PROAPTIV;
1685 __cpu_name[cpu] = "MIPS proAptiv";
1686 break;
1687 case PRID_IMP_PROAPTIV_MP:
1688 c->cputype = CPU_PROAPTIV;
1689 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1690 break;
1691 case PRID_IMP_P5600:
1692 c->cputype = CPU_P5600;
1693 __cpu_name[cpu] = "MIPS P5600";
1694 break;
1695 case PRID_IMP_P6600:
1696 c->cputype = CPU_P6600;
1697 __cpu_name[cpu] = "MIPS P6600";
1698 break;
1699 case PRID_IMP_I6400:
1700 c->cputype = CPU_I6400;
1701 __cpu_name[cpu] = "MIPS I6400";
1702 break;
1703 case PRID_IMP_I6500:
1704 c->cputype = CPU_I6500;
1705 __cpu_name[cpu] = "MIPS I6500";
1706 break;
1707 case PRID_IMP_M5150:
1708 c->cputype = CPU_M5150;
1709 __cpu_name[cpu] = "MIPS M5150";
1710 break;
1711 case PRID_IMP_M6250:
1712 c->cputype = CPU_M6250;
1713 __cpu_name[cpu] = "MIPS M6250";
1714 break;
1715 }
1716
1717 decode_configs(c);
1718
1719 spram_config();
1720
1721 switch (__get_cpu_type(c->cputype)) {
1722 case CPU_I6500:
1723 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1724 /* fall-through */
1725 case CPU_I6400:
1726 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1727 /* fall-through */
1728 default:
1729 break;
1730 }
1731}
1732
1733static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1734{
1735 decode_configs(c);
1736 switch (c->processor_id & PRID_IMP_MASK) {
1737 case PRID_IMP_AU1_REV1:
1738 case PRID_IMP_AU1_REV2:
1739 c->cputype = CPU_ALCHEMY;
1740 switch ((c->processor_id >> 24) & 0xff) {
1741 case 0:
1742 __cpu_name[cpu] = "Au1000";
1743 break;
1744 case 1:
1745 __cpu_name[cpu] = "Au1500";
1746 break;
1747 case 2:
1748 __cpu_name[cpu] = "Au1100";
1749 break;
1750 case 3:
1751 __cpu_name[cpu] = "Au1550";
1752 break;
1753 case 4:
1754 __cpu_name[cpu] = "Au1200";
1755 if ((c->processor_id & PRID_REV_MASK) == 2)
1756 __cpu_name[cpu] = "Au1250";
1757 break;
1758 case 5:
1759 __cpu_name[cpu] = "Au1210";
1760 break;
1761 default:
1762 __cpu_name[cpu] = "Au1xxx";
1763 break;
1764 }
1765 break;
1766 }
1767}
1768
1769static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1770{
1771 decode_configs(c);
1772
1773 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1774 switch (c->processor_id & PRID_IMP_MASK) {
1775 case PRID_IMP_SB1:
1776 c->cputype = CPU_SB1;
1777 __cpu_name[cpu] = "SiByte SB1";
1778 /* FPU in pass1 is known to have issues. */
1779 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1780 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1781 break;
1782 case PRID_IMP_SB1A:
1783 c->cputype = CPU_SB1A;
1784 __cpu_name[cpu] = "SiByte SB1A";
1785 break;
1786 }
1787}
1788
1789static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1790{
1791 decode_configs(c);
1792 switch (c->processor_id & PRID_IMP_MASK) {
1793 case PRID_IMP_SR71000:
1794 c->cputype = CPU_SR71000;
1795 __cpu_name[cpu] = "Sandcraft SR71000";
1796 c->scache.ways = 8;
1797 c->tlbsize = 64;
1798 break;
1799 }
1800}
1801
1802static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1803{
1804 decode_configs(c);
1805 switch (c->processor_id & PRID_IMP_MASK) {
1806 case PRID_IMP_PR4450:
1807 c->cputype = CPU_PR4450;
1808 __cpu_name[cpu] = "Philips PR4450";
1809 set_isa(c, MIPS_CPU_ISA_M32R1);
1810 break;
1811 }
1812}
1813
1814static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1815{
1816 decode_configs(c);
1817 switch (c->processor_id & PRID_IMP_MASK) {
1818 case PRID_IMP_BMIPS32_REV4:
1819 case PRID_IMP_BMIPS32_REV8:
1820 c->cputype = CPU_BMIPS32;
1821 __cpu_name[cpu] = "Broadcom BMIPS32";
1822 set_elf_platform(cpu, "bmips32");
1823 break;
1824 case PRID_IMP_BMIPS3300:
1825 case PRID_IMP_BMIPS3300_ALT:
1826 case PRID_IMP_BMIPS3300_BUG:
1827 c->cputype = CPU_BMIPS3300;
1828 __cpu_name[cpu] = "Broadcom BMIPS3300";
1829 set_elf_platform(cpu, "bmips3300");
1830 break;
1831 case PRID_IMP_BMIPS43XX: {
1832 int rev = c->processor_id & PRID_REV_MASK;
1833
1834 if (rev >= PRID_REV_BMIPS4380_LO &&
1835 rev <= PRID_REV_BMIPS4380_HI) {
1836 c->cputype = CPU_BMIPS4380;
1837 __cpu_name[cpu] = "Broadcom BMIPS4380";
1838 set_elf_platform(cpu, "bmips4380");
1839 c->options |= MIPS_CPU_RIXI;
1840 } else {
1841 c->cputype = CPU_BMIPS4350;
1842 __cpu_name[cpu] = "Broadcom BMIPS4350";
1843 set_elf_platform(cpu, "bmips4350");
1844 }
1845 break;
1846 }
1847 case PRID_IMP_BMIPS5000:
1848 case PRID_IMP_BMIPS5200:
1849 c->cputype = CPU_BMIPS5000;
1850 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1851 __cpu_name[cpu] = "Broadcom BMIPS5200";
1852 else
1853 __cpu_name[cpu] = "Broadcom BMIPS5000";
1854 set_elf_platform(cpu, "bmips5000");
1855 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1856 break;
1857 }
1858}
1859
1860static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1861{
1862 decode_configs(c);
1863 switch (c->processor_id & PRID_IMP_MASK) {
1864 case PRID_IMP_CAVIUM_CN38XX:
1865 case PRID_IMP_CAVIUM_CN31XX:
1866 case PRID_IMP_CAVIUM_CN30XX:
1867 c->cputype = CPU_CAVIUM_OCTEON;
1868 __cpu_name[cpu] = "Cavium Octeon";
1869 goto platform;
1870 case PRID_IMP_CAVIUM_CN58XX:
1871 case PRID_IMP_CAVIUM_CN56XX:
1872 case PRID_IMP_CAVIUM_CN50XX:
1873 case PRID_IMP_CAVIUM_CN52XX:
1874 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1875 __cpu_name[cpu] = "Cavium Octeon+";
1876platform:
1877 set_elf_platform(cpu, "octeon");
1878 break;
1879 case PRID_IMP_CAVIUM_CN61XX:
1880 case PRID_IMP_CAVIUM_CN63XX:
1881 case PRID_IMP_CAVIUM_CN66XX:
1882 case PRID_IMP_CAVIUM_CN68XX:
1883 case PRID_IMP_CAVIUM_CNF71XX:
1884 c->cputype = CPU_CAVIUM_OCTEON2;
1885 __cpu_name[cpu] = "Cavium Octeon II";
1886 set_elf_platform(cpu, "octeon2");
1887 break;
1888 case PRID_IMP_CAVIUM_CN70XX:
1889 case PRID_IMP_CAVIUM_CN73XX:
1890 case PRID_IMP_CAVIUM_CNF75XX:
1891 case PRID_IMP_CAVIUM_CN78XX:
1892 c->cputype = CPU_CAVIUM_OCTEON3;
1893 __cpu_name[cpu] = "Cavium Octeon III";
1894 set_elf_platform(cpu, "octeon3");
1895 break;
1896 default:
1897 printk(KERN_INFO "Unknown Octeon chip!\n");
1898 c->cputype = CPU_UNKNOWN;
1899 break;
1900 }
1901}
1902
1903static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1904{
1905 switch (c->processor_id & PRID_IMP_MASK) {
1906 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1907 switch (c->processor_id & PRID_REV_MASK) {
1908 case PRID_REV_LOONGSON3A_R2_0:
1909 case PRID_REV_LOONGSON3A_R2_1:
1910 c->cputype = CPU_LOONGSON3;
1911 __cpu_name[cpu] = "ICT Loongson-3";
1912 set_elf_platform(cpu, "loongson3a");
1913 set_isa(c, MIPS_CPU_ISA_M64R2);
1914 break;
1915 case PRID_REV_LOONGSON3A_R3_0:
1916 case PRID_REV_LOONGSON3A_R3_1:
1917 c->cputype = CPU_LOONGSON3;
1918 __cpu_name[cpu] = "ICT Loongson-3";
1919 set_elf_platform(cpu, "loongson3a");
1920 set_isa(c, MIPS_CPU_ISA_M64R2);
1921 break;
1922 }
1923
1924 decode_configs(c);
1925 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1926 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1927 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1928 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1929 break;
1930 default:
1931 panic("Unknown Loongson Processor ID!");
1932 break;
1933 }
1934}
1935
1936static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1937{
1938 decode_configs(c);
1939
1940 /*
1941 * XBurst misses a config2 register, so config3 decode was skipped in
1942 * decode_configs().
1943 */
1944 decode_config3(c);
1945
1946 /* XBurst does not implement the CP0 counter. */
1947 c->options &= ~MIPS_CPU_COUNTER;
1948 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1949
1950 switch (c->processor_id & PRID_IMP_MASK) {
1951 case PRID_IMP_XBURST:
1952 c->cputype = CPU_XBURST;
1953 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1954 __cpu_name[cpu] = "Ingenic JZRISC";
1955 /*
1956 * The XBurst core by default attempts to avoid branch target
1957 * buffer lookups by detecting & special casing loops. This
1958 * feature will cause BogoMIPS and lpj calculate in error.
1959 * Set cp0 config7 bit 4 to disable this feature.
1960 */
1961 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1962 break;
1963 default:
1964 panic("Unknown Ingenic Processor ID!");
1965 break;
1966 }
1967
1968 /*
1969 * The config0 register in the Xburst CPUs with a processor ID of
1970 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1971 * but they don't actually support this ISA.
1972 */
1973 if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
1974 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1975}
1976
1977static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1978{
1979 decode_configs(c);
1980
1981 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1982 c->cputype = CPU_ALCHEMY;
1983 __cpu_name[cpu] = "Au1300";
1984 /* following stuff is not for Alchemy */
1985 return;
1986 }
1987
1988 c->options = (MIPS_CPU_TLB |
1989 MIPS_CPU_4KEX |
1990 MIPS_CPU_COUNTER |
1991 MIPS_CPU_DIVEC |
1992 MIPS_CPU_WATCH |
1993 MIPS_CPU_EJTAG |
1994 MIPS_CPU_LLSC);
1995
1996 switch (c->processor_id & PRID_IMP_MASK) {
1997 case PRID_IMP_NETLOGIC_XLP2XX:
1998 case PRID_IMP_NETLOGIC_XLP9XX:
1999 case PRID_IMP_NETLOGIC_XLP5XX:
2000 c->cputype = CPU_XLP;
2001 __cpu_name[cpu] = "Broadcom XLPII";
2002 break;
2003
2004 case PRID_IMP_NETLOGIC_XLP8XX:
2005 case PRID_IMP_NETLOGIC_XLP3XX:
2006 c->cputype = CPU_XLP;
2007 __cpu_name[cpu] = "Netlogic XLP";
2008 break;
2009
2010 case PRID_IMP_NETLOGIC_XLR732:
2011 case PRID_IMP_NETLOGIC_XLR716:
2012 case PRID_IMP_NETLOGIC_XLR532:
2013 case PRID_IMP_NETLOGIC_XLR308:
2014 case PRID_IMP_NETLOGIC_XLR532C:
2015 case PRID_IMP_NETLOGIC_XLR516C:
2016 case PRID_IMP_NETLOGIC_XLR508C:
2017 case PRID_IMP_NETLOGIC_XLR308C:
2018 c->cputype = CPU_XLR;
2019 __cpu_name[cpu] = "Netlogic XLR";
2020 break;
2021
2022 case PRID_IMP_NETLOGIC_XLS608:
2023 case PRID_IMP_NETLOGIC_XLS408:
2024 case PRID_IMP_NETLOGIC_XLS404:
2025 case PRID_IMP_NETLOGIC_XLS208:
2026 case PRID_IMP_NETLOGIC_XLS204:
2027 case PRID_IMP_NETLOGIC_XLS108:
2028 case PRID_IMP_NETLOGIC_XLS104:
2029 case PRID_IMP_NETLOGIC_XLS616B:
2030 case PRID_IMP_NETLOGIC_XLS608B:
2031 case PRID_IMP_NETLOGIC_XLS416B:
2032 case PRID_IMP_NETLOGIC_XLS412B:
2033 case PRID_IMP_NETLOGIC_XLS408B:
2034 case PRID_IMP_NETLOGIC_XLS404B:
2035 c->cputype = CPU_XLR;
2036 __cpu_name[cpu] = "Netlogic XLS";
2037 break;
2038
2039 default:
2040 pr_info("Unknown Netlogic chip id [%02x]!\n",
2041 c->processor_id);
2042 c->cputype = CPU_XLR;
2043 break;
2044 }
2045
2046 if (c->cputype == CPU_XLP) {
2047 set_isa(c, MIPS_CPU_ISA_M64R2);
2048 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2049 /* This will be updated again after all threads are woken up */
2050 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2051 } else {
2052 set_isa(c, MIPS_CPU_ISA_M64R1);
2053 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2054 }
2055 c->kscratch_mask = 0xf;
2056}
2057
2058#ifdef CONFIG_64BIT
2059/* For use by uaccess.h */
2060u64 __ua_limit;
2061EXPORT_SYMBOL(__ua_limit);
2062#endif
2063
2064const char *__cpu_name[NR_CPUS];
2065const char *__elf_platform;
2066
2067void cpu_probe(void)
2068{
2069 struct cpuinfo_mips *c = ¤t_cpu_data;
2070 unsigned int cpu = smp_processor_id();
2071
2072 /*
2073 * Set a default elf platform, cpu probe may later
2074 * overwrite it with a more precise value
2075 */
2076 set_elf_platform(cpu, "mips");
2077
2078 c->processor_id = PRID_IMP_UNKNOWN;
2079 c->fpu_id = FPIR_IMP_NONE;
2080 c->cputype = CPU_UNKNOWN;
2081 c->writecombine = _CACHE_UNCACHED;
2082
2083 c->fpu_csr31 = FPU_CSR_RN;
2084 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2085
2086 c->processor_id = read_c0_prid();
2087 switch (c->processor_id & PRID_COMP_MASK) {
2088 case PRID_COMP_LEGACY:
2089 cpu_probe_legacy(c, cpu);
2090 break;
2091 case PRID_COMP_MIPS:
2092 cpu_probe_mips(c, cpu);
2093 break;
2094 case PRID_COMP_ALCHEMY:
2095 cpu_probe_alchemy(c, cpu);
2096 break;
2097 case PRID_COMP_SIBYTE:
2098 cpu_probe_sibyte(c, cpu);
2099 break;
2100 case PRID_COMP_BROADCOM:
2101 cpu_probe_broadcom(c, cpu);
2102 break;
2103 case PRID_COMP_SANDCRAFT:
2104 cpu_probe_sandcraft(c, cpu);
2105 break;
2106 case PRID_COMP_NXP:
2107 cpu_probe_nxp(c, cpu);
2108 break;
2109 case PRID_COMP_CAVIUM:
2110 cpu_probe_cavium(c, cpu);
2111 break;
2112 case PRID_COMP_LOONGSON:
2113 cpu_probe_loongson(c, cpu);
2114 break;
2115 case PRID_COMP_INGENIC_D0:
2116 case PRID_COMP_INGENIC_D1:
2117 case PRID_COMP_INGENIC_E1:
2118 cpu_probe_ingenic(c, cpu);
2119 break;
2120 case PRID_COMP_NETLOGIC:
2121 cpu_probe_netlogic(c, cpu);
2122 break;
2123 }
2124
2125 BUG_ON(!__cpu_name[cpu]);
2126 BUG_ON(c->cputype == CPU_UNKNOWN);
2127
2128 /*
2129 * Platform code can force the cpu type to optimize code
2130 * generation. In that case be sure the cpu type is correctly
2131 * manually setup otherwise it could trigger some nasty bugs.
2132 */
2133 BUG_ON(current_cpu_type() != c->cputype);
2134
2135 if (cpu_has_rixi) {
2136 /* Enable the RIXI exceptions */
2137 set_c0_pagegrain(PG_IEC);
2138 back_to_back_c0_hazard();
2139 /* Verify the IEC bit is set */
2140 if (read_c0_pagegrain() & PG_IEC)
2141 c->options |= MIPS_CPU_RIXIEX;
2142 }
2143
2144 if (mips_fpu_disabled)
2145 c->options &= ~MIPS_CPU_FPU;
2146
2147 if (mips_dsp_disabled)
2148 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2149
2150 if (mips_htw_disabled) {
2151 c->options &= ~MIPS_CPU_HTW;
2152 write_c0_pwctl(read_c0_pwctl() &
2153 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2154 }
2155
2156 if (c->options & MIPS_CPU_FPU)
2157 cpu_set_fpu_opts(c);
2158 else
2159 cpu_set_nofpu_opts(c);
2160
2161 if (cpu_has_bp_ghist)
2162 write_c0_r10k_diag(read_c0_r10k_diag() |
2163 R10K_DIAG_E_GHIST);
2164
2165 if (cpu_has_mips_r2_r6) {
2166 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2167 /* R2 has Performance Counter Interrupt indicator */
2168 c->options |= MIPS_CPU_PCI;
2169 }
2170 else
2171 c->srsets = 1;
2172
2173 if (cpu_has_mips_r6)
2174 elf_hwcap |= HWCAP_MIPS_R6;
2175
2176 if (cpu_has_msa) {
2177 c->msa_id = cpu_get_msa_id();
2178 WARN(c->msa_id & MSA_IR_WRPF,
2179 "Vector register partitioning unimplemented!");
2180 elf_hwcap |= HWCAP_MIPS_MSA;
2181 }
2182
2183 if (cpu_has_mips16)
2184 elf_hwcap |= HWCAP_MIPS_MIPS16;
2185
2186 if (cpu_has_mdmx)
2187 elf_hwcap |= HWCAP_MIPS_MDMX;
2188
2189 if (cpu_has_mips3d)
2190 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2191
2192 if (cpu_has_smartmips)
2193 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2194
2195 if (cpu_has_dsp)
2196 elf_hwcap |= HWCAP_MIPS_DSP;
2197
2198 if (cpu_has_dsp2)
2199 elf_hwcap |= HWCAP_MIPS_DSP2;
2200
2201 if (cpu_has_dsp3)
2202 elf_hwcap |= HWCAP_MIPS_DSP3;
2203
2204 if (cpu_has_mips16e2)
2205 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2206
2207 if (cpu_has_loongson_mmi)
2208 elf_hwcap |= HWCAP_LOONGSON_MMI;
2209
2210 if (cpu_has_loongson_ext)
2211 elf_hwcap |= HWCAP_LOONGSON_EXT;
2212
2213 if (cpu_has_loongson_ext2)
2214 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2215
2216 if (cpu_has_vz)
2217 cpu_probe_vz(c);
2218
2219 cpu_probe_vmbits(c);
2220
2221#ifdef CONFIG_64BIT
2222 if (cpu == 0)
2223 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2224#endif
2225}
2226
2227void cpu_report(void)
2228{
2229 struct cpuinfo_mips *c = ¤t_cpu_data;
2230
2231 pr_info("CPU%d revision is: %08x (%s)\n",
2232 smp_processor_id(), c->processor_id, cpu_name_string());
2233 if (c->options & MIPS_CPU_FPU)
2234 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2235 if (cpu_has_msa)
2236 pr_info("MSA revision is: %08x\n", c->msa_id);
2237}
2238
2239void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2240{
2241 /* Ensure the core number fits in the field */
2242 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2243 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2244
2245 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2246 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2247}
2248
2249void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2250{
2251 /* Ensure the core number fits in the field */
2252 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2253
2254 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2255 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2256}
2257
2258void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2259{
2260 /* Ensure the VP(E) ID fits in the field */
2261 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2262
2263 /* Ensure we're not using VP(E)s without support */
2264 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2265 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2266
2267 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2268 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2269}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <linux/uaccess.h>
30
31#include <asm/mach-loongson64/cpucfg-emul.h>
32
33/* Hardware capabilities */
34unsigned int elf_hwcap __read_mostly;
35EXPORT_SYMBOL_GPL(elf_hwcap);
36
37#ifdef CONFIG_MIPS_FP_SUPPORT
38
39/*
40 * Get the FPU Implementation/Revision.
41 */
42static inline unsigned long cpu_get_fpu_id(void)
43{
44 unsigned long tmp, fpu_id;
45
46 tmp = read_c0_status();
47 __enable_fpu(FPU_AS_IS);
48 fpu_id = read_32bit_cp1_register(CP1_REVISION);
49 write_c0_status(tmp);
50 return fpu_id;
51}
52
53/*
54 * Check if the CPU has an external FPU.
55 */
56static inline int __cpu_has_fpu(void)
57{
58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
59}
60
61/*
62 * Determine the FCSR mask for FPU hardware.
63 */
64static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
65{
66 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
67
68 fcsr = c->fpu_csr31;
69 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
70
71 sr = read_c0_status();
72 __enable_fpu(FPU_AS_IS);
73
74 fcsr0 = fcsr & mask;
75 write_32bit_cp1_register(CP1_STATUS, fcsr0);
76 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
77
78 fcsr1 = fcsr | ~mask;
79 write_32bit_cp1_register(CP1_STATUS, fcsr1);
80 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
81
82 write_32bit_cp1_register(CP1_STATUS, fcsr);
83
84 write_c0_status(sr);
85
86 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
87}
88
89/*
90 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
91 * supported by FPU hardware.
92 */
93static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
94{
95 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
96 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
97 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
98 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
99 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
100
101 sr = read_c0_status();
102 __enable_fpu(FPU_AS_IS);
103
104 fir = read_32bit_cp1_register(CP1_REVISION);
105 if (fir & MIPS_FPIR_HAS2008) {
106 fcsr = read_32bit_cp1_register(CP1_STATUS);
107
108 /*
109 * MAC2008 toolchain never landed in real world, so we're only
110 * testing wether it can be disabled and don't try to enabled
111 * it.
112 */
113 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008 | FPU_CSR_MAC2008);
114 write_32bit_cp1_register(CP1_STATUS, fcsr0);
115 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
116
117 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
118 write_32bit_cp1_register(CP1_STATUS, fcsr1);
119 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
120
121 write_32bit_cp1_register(CP1_STATUS, fcsr);
122
123 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2)) {
124 /*
125 * The bit for MAC2008 might be reused by R6 in future,
126 * so we only test for R2-R5.
127 */
128 if (fcsr0 & FPU_CSR_MAC2008)
129 c->options |= MIPS_CPU_MAC_2008_ONLY;
130 }
131
132 if (!(fcsr0 & FPU_CSR_NAN2008))
133 c->options |= MIPS_CPU_NAN_LEGACY;
134 if (fcsr1 & FPU_CSR_NAN2008)
135 c->options |= MIPS_CPU_NAN_2008;
136
137 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
138 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
139 else
140 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
141
142 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
143 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
144 else
145 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
146 } else {
147 c->options |= MIPS_CPU_NAN_LEGACY;
148 }
149
150 write_c0_status(sr);
151 } else {
152 c->options |= MIPS_CPU_NAN_LEGACY;
153 }
154}
155
156/*
157 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
158 * ABS.fmt/NEG.fmt execution mode.
159 */
160static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
161
162/*
163 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
164 * to support by the FPU emulator according to the IEEE 754 conformance
165 * mode selected. Note that "relaxed" straps the emulator so that it
166 * allows 2008-NaN binaries even for legacy processors.
167 */
168static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
169{
170 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
171 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
172 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
173
174 switch (ieee754) {
175 case STRICT:
176 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
177 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
178 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
179 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
180 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
181 } else {
182 c->options |= MIPS_CPU_NAN_LEGACY;
183 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
184 }
185 break;
186 case LEGACY:
187 c->options |= MIPS_CPU_NAN_LEGACY;
188 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
189 break;
190 case STD2008:
191 c->options |= MIPS_CPU_NAN_2008;
192 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
193 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
194 break;
195 case RELAXED:
196 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
197 break;
198 }
199}
200
201/*
202 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
203 * according to the "ieee754=" parameter.
204 */
205static void cpu_set_nan_2008(struct cpuinfo_mips *c)
206{
207 switch (ieee754) {
208 case STRICT:
209 mips_use_nan_legacy = !!cpu_has_nan_legacy;
210 mips_use_nan_2008 = !!cpu_has_nan_2008;
211 break;
212 case LEGACY:
213 mips_use_nan_legacy = !!cpu_has_nan_legacy;
214 mips_use_nan_2008 = !cpu_has_nan_legacy;
215 break;
216 case STD2008:
217 mips_use_nan_legacy = !cpu_has_nan_2008;
218 mips_use_nan_2008 = !!cpu_has_nan_2008;
219 break;
220 case RELAXED:
221 mips_use_nan_legacy = true;
222 mips_use_nan_2008 = true;
223 break;
224 }
225}
226
227/*
228 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
229 * settings:
230 *
231 * strict: accept binaries that request a NaN encoding supported by the FPU
232 * legacy: only accept legacy-NaN binaries
233 * 2008: only accept 2008-NaN binaries
234 * relaxed: accept any binaries regardless of whether supported by the FPU
235 */
236static int __init ieee754_setup(char *s)
237{
238 if (!s)
239 return -1;
240 else if (!strcmp(s, "strict"))
241 ieee754 = STRICT;
242 else if (!strcmp(s, "legacy"))
243 ieee754 = LEGACY;
244 else if (!strcmp(s, "2008"))
245 ieee754 = STD2008;
246 else if (!strcmp(s, "relaxed"))
247 ieee754 = RELAXED;
248 else
249 return -1;
250
251 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
252 cpu_set_nofpu_2008(&boot_cpu_data);
253 cpu_set_nan_2008(&boot_cpu_data);
254
255 return 0;
256}
257
258early_param("ieee754", ieee754_setup);
259
260/*
261 * Set the FIR feature flags for the FPU emulator.
262 */
263static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
264{
265 u32 value;
266
267 value = 0;
268 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
269 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
270 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
271 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
272 value |= MIPS_FPIR_D | MIPS_FPIR_S;
273 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
274 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
275 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
276 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
277 if (c->options & MIPS_CPU_NAN_2008)
278 value |= MIPS_FPIR_HAS2008;
279 c->fpu_id = value;
280}
281
282/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
283static unsigned int mips_nofpu_msk31;
284
285/*
286 * Set options for FPU hardware.
287 */
288static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
289{
290 c->fpu_id = cpu_get_fpu_id();
291 mips_nofpu_msk31 = c->fpu_msk31;
292
293 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
294 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
295 MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 |
296 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
297 if (c->fpu_id & MIPS_FPIR_3D)
298 c->ases |= MIPS_ASE_MIPS3D;
299 if (c->fpu_id & MIPS_FPIR_UFRP)
300 c->options |= MIPS_CPU_UFR;
301 if (c->fpu_id & MIPS_FPIR_FREP)
302 c->options |= MIPS_CPU_FRE;
303 }
304
305 cpu_set_fpu_fcsr_mask(c);
306 cpu_set_fpu_2008(c);
307 cpu_set_nan_2008(c);
308}
309
310/*
311 * Set options for the FPU emulator.
312 */
313static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
314{
315 c->options &= ~MIPS_CPU_FPU;
316 c->fpu_msk31 = mips_nofpu_msk31;
317
318 cpu_set_nofpu_2008(c);
319 cpu_set_nan_2008(c);
320 cpu_set_nofpu_id(c);
321}
322
323static int mips_fpu_disabled;
324
325static int __init fpu_disable(char *s)
326{
327 cpu_set_nofpu_opts(&boot_cpu_data);
328 mips_fpu_disabled = 1;
329
330 return 1;
331}
332
333__setup("nofpu", fpu_disable);
334
335#else /* !CONFIG_MIPS_FP_SUPPORT */
336
337#define mips_fpu_disabled 1
338
339static inline unsigned long cpu_get_fpu_id(void)
340{
341 return FPIR_IMP_NONE;
342}
343
344static inline int __cpu_has_fpu(void)
345{
346 return 0;
347}
348
349static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
350{
351 /* no-op */
352}
353
354static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
355{
356 /* no-op */
357}
358
359#endif /* CONFIG_MIPS_FP_SUPPORT */
360
361static inline unsigned long cpu_get_msa_id(void)
362{
363 unsigned long status, msa_id;
364
365 status = read_c0_status();
366 __enable_fpu(FPU_64BIT);
367 enable_msa();
368 msa_id = read_msa_ir();
369 disable_msa();
370 write_c0_status(status);
371 return msa_id;
372}
373
374static int mips_dsp_disabled;
375
376static int __init dsp_disable(char *s)
377{
378 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
379 mips_dsp_disabled = 1;
380
381 return 1;
382}
383
384__setup("nodsp", dsp_disable);
385
386static int mips_htw_disabled;
387
388static int __init htw_disable(char *s)
389{
390 mips_htw_disabled = 1;
391 cpu_data[0].options &= ~MIPS_CPU_HTW;
392 write_c0_pwctl(read_c0_pwctl() &
393 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
394
395 return 1;
396}
397
398__setup("nohtw", htw_disable);
399
400static int mips_ftlb_disabled;
401static int mips_has_ftlb_configured;
402
403enum ftlb_flags {
404 FTLB_EN = 1 << 0,
405 FTLB_SET_PROB = 1 << 1,
406};
407
408static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
409
410static int __init ftlb_disable(char *s)
411{
412 unsigned int config4, mmuextdef;
413
414 /*
415 * If the core hasn't done any FTLB configuration, there is nothing
416 * for us to do here.
417 */
418 if (!mips_has_ftlb_configured)
419 return 1;
420
421 /* Disable it in the boot cpu */
422 if (set_ftlb_enable(&cpu_data[0], 0)) {
423 pr_warn("Can't turn FTLB off\n");
424 return 1;
425 }
426
427 config4 = read_c0_config4();
428
429 /* Check that FTLB has been disabled */
430 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
431 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
432 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
433 /* This should never happen */
434 pr_warn("FTLB could not be disabled!\n");
435 return 1;
436 }
437
438 mips_ftlb_disabled = 1;
439 mips_has_ftlb_configured = 0;
440
441 /*
442 * noftlb is mainly used for debug purposes so print
443 * an informative message instead of using pr_debug()
444 */
445 pr_info("FTLB has been disabled\n");
446
447 /*
448 * Some of these bits are duplicated in the decode_config4.
449 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
450 * once FTLB has been disabled so undo what decode_config4 did.
451 */
452 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
453 cpu_data[0].tlbsizeftlbsets;
454 cpu_data[0].tlbsizeftlbsets = 0;
455 cpu_data[0].tlbsizeftlbways = 0;
456
457 return 1;
458}
459
460__setup("noftlb", ftlb_disable);
461
462/*
463 * Check if the CPU has per tc perf counters
464 */
465static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
466{
467 if (read_c0_config7() & MTI_CONF7_PTC)
468 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
469}
470
471static inline void check_errata(void)
472{
473 struct cpuinfo_mips *c = ¤t_cpu_data;
474
475 switch (current_cpu_type()) {
476 case CPU_34K:
477 /*
478 * Erratum "RPS May Cause Incorrect Instruction Execution"
479 * This code only handles VPE0, any SMP/RTOS code
480 * making use of VPE1 will be responsable for that VPE.
481 */
482 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
483 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
484 break;
485 default:
486 break;
487 }
488}
489
490void __init check_bugs32(void)
491{
492 check_errata();
493}
494
495/*
496 * Probe whether cpu has config register by trying to play with
497 * alternate cache bit and see whether it matters.
498 * It's used by cpu_probe to distinguish between R3000A and R3081.
499 */
500static inline int cpu_has_confreg(void)
501{
502#ifdef CONFIG_CPU_R3000
503 extern unsigned long r3k_cache_size(unsigned long);
504 unsigned long size1, size2;
505 unsigned long cfg = read_c0_conf();
506
507 size1 = r3k_cache_size(ST0_ISC);
508 write_c0_conf(cfg ^ R30XX_CONF_AC);
509 size2 = r3k_cache_size(ST0_ISC);
510 write_c0_conf(cfg);
511 return size1 != size2;
512#else
513 return 0;
514#endif
515}
516
517static inline void set_elf_platform(int cpu, const char *plat)
518{
519 if (cpu == 0)
520 __elf_platform = plat;
521}
522
523static inline void set_elf_base_platform(const char *plat)
524{
525 if (__elf_base_platform == NULL) {
526 __elf_base_platform = plat;
527 }
528}
529
530static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
531{
532#ifdef __NEED_VMBITS_PROBE
533 write_c0_entryhi(0x3fffffffffffe000ULL);
534 back_to_back_c0_hazard();
535 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
536#endif
537}
538
539static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
540{
541 switch (isa) {
542 case MIPS_CPU_ISA_M64R5:
543 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
544 set_elf_base_platform("mips64r5");
545 fallthrough;
546 case MIPS_CPU_ISA_M64R2:
547 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
548 set_elf_base_platform("mips64r2");
549 fallthrough;
550 case MIPS_CPU_ISA_M64R1:
551 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
552 set_elf_base_platform("mips64");
553 fallthrough;
554 case MIPS_CPU_ISA_V:
555 c->isa_level |= MIPS_CPU_ISA_V;
556 set_elf_base_platform("mips5");
557 fallthrough;
558 case MIPS_CPU_ISA_IV:
559 c->isa_level |= MIPS_CPU_ISA_IV;
560 set_elf_base_platform("mips4");
561 fallthrough;
562 case MIPS_CPU_ISA_III:
563 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
564 set_elf_base_platform("mips3");
565 break;
566
567 /* R6 incompatible with everything else */
568 case MIPS_CPU_ISA_M64R6:
569 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
570 set_elf_base_platform("mips64r6");
571 fallthrough;
572 case MIPS_CPU_ISA_M32R6:
573 c->isa_level |= MIPS_CPU_ISA_M32R6;
574 set_elf_base_platform("mips32r6");
575 /* Break here so we don't add incompatible ISAs */
576 break;
577 case MIPS_CPU_ISA_M32R5:
578 c->isa_level |= MIPS_CPU_ISA_M32R5;
579 set_elf_base_platform("mips32r5");
580 fallthrough;
581 case MIPS_CPU_ISA_M32R2:
582 c->isa_level |= MIPS_CPU_ISA_M32R2;
583 set_elf_base_platform("mips32r2");
584 fallthrough;
585 case MIPS_CPU_ISA_M32R1:
586 c->isa_level |= MIPS_CPU_ISA_M32R1;
587 set_elf_base_platform("mips32");
588 fallthrough;
589 case MIPS_CPU_ISA_II:
590 c->isa_level |= MIPS_CPU_ISA_II;
591 set_elf_base_platform("mips2");
592 break;
593 }
594}
595
596static char unknown_isa[] = KERN_ERR \
597 "Unsupported ISA type, c0.config0: %d.";
598
599static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
600{
601
602 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
603
604 /*
605 * 0 = All TLBWR instructions go to FTLB
606 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
607 * FTLB and 1 goes to the VTLB.
608 * 2 = 7:1: As above with 7:1 ratio.
609 * 3 = 3:1: As above with 3:1 ratio.
610 *
611 * Use the linear midpoint as the probability threshold.
612 */
613 if (probability >= 12)
614 return 1;
615 else if (probability >= 6)
616 return 2;
617 else
618 /*
619 * So FTLB is less than 4 times bigger than VTLB.
620 * A 3:1 ratio can still be useful though.
621 */
622 return 3;
623}
624
625static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
626{
627 unsigned int config;
628
629 /* It's implementation dependent how the FTLB can be enabled */
630 switch (c->cputype) {
631 case CPU_PROAPTIV:
632 case CPU_P5600:
633 case CPU_P6600:
634 /* proAptiv & related cores use Config6 to enable the FTLB */
635 config = read_c0_config6();
636
637 if (flags & FTLB_EN)
638 config |= MTI_CONF6_FTLBEN;
639 else
640 config &= ~MTI_CONF6_FTLBEN;
641
642 if (flags & FTLB_SET_PROB) {
643 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
644 config |= calculate_ftlb_probability(c)
645 << MTI_CONF6_FTLBP_SHIFT;
646 }
647
648 write_c0_config6(config);
649 back_to_back_c0_hazard();
650 break;
651 case CPU_I6400:
652 case CPU_I6500:
653 /* There's no way to disable the FTLB */
654 if (!(flags & FTLB_EN))
655 return 1;
656 return 0;
657 case CPU_LOONGSON64:
658 /* Flush ITLB, DTLB, VTLB and FTLB */
659 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
660 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
661 /* Loongson-3 cores use Config6 to enable the FTLB */
662 config = read_c0_config6();
663 if (flags & FTLB_EN)
664 /* Enable FTLB */
665 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
666 else
667 /* Disable FTLB */
668 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
669 break;
670 default:
671 return 1;
672 }
673
674 return 0;
675}
676
677static int mm_config(struct cpuinfo_mips *c)
678{
679 unsigned int config0, update, mm;
680
681 config0 = read_c0_config();
682 mm = config0 & MIPS_CONF_MM;
683
684 /*
685 * It's implementation dependent what type of write-merge is supported
686 * and whether it can be enabled/disabled. If it is settable lets make
687 * the merging allowed by default. Some platforms might have
688 * write-through caching unsupported. In this case just ignore the
689 * CP0.Config.MM bit field value.
690 */
691 switch (c->cputype) {
692 case CPU_24K:
693 case CPU_34K:
694 case CPU_74K:
695 case CPU_P5600:
696 case CPU_P6600:
697 c->options |= MIPS_CPU_MM_FULL;
698 update = MIPS_CONF_MM_FULL;
699 break;
700 case CPU_1004K:
701 case CPU_1074K:
702 case CPU_INTERAPTIV:
703 case CPU_PROAPTIV:
704 mm = 0;
705 fallthrough;
706 default:
707 update = 0;
708 break;
709 }
710
711 if (update) {
712 config0 = (config0 & ~MIPS_CONF_MM) | update;
713 write_c0_config(config0);
714 } else if (mm == MIPS_CONF_MM_SYSAD) {
715 c->options |= MIPS_CPU_MM_SYSAD;
716 } else if (mm == MIPS_CONF_MM_FULL) {
717 c->options |= MIPS_CPU_MM_FULL;
718 }
719
720 return 0;
721}
722
723static inline unsigned int decode_config0(struct cpuinfo_mips *c)
724{
725 unsigned int config0;
726 int isa, mt;
727
728 config0 = read_c0_config();
729
730 /*
731 * Look for Standard TLB or Dual VTLB and FTLB
732 */
733 mt = config0 & MIPS_CONF_MT;
734 if (mt == MIPS_CONF_MT_TLB)
735 c->options |= MIPS_CPU_TLB;
736 else if (mt == MIPS_CONF_MT_FTLB)
737 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
738
739 isa = (config0 & MIPS_CONF_AT) >> 13;
740 switch (isa) {
741 case 0:
742 switch ((config0 & MIPS_CONF_AR) >> 10) {
743 case 0:
744 set_isa(c, MIPS_CPU_ISA_M32R1);
745 break;
746 case 1:
747 set_isa(c, MIPS_CPU_ISA_M32R2);
748 break;
749 case 2:
750 set_isa(c, MIPS_CPU_ISA_M32R6);
751 break;
752 default:
753 goto unknown;
754 }
755 break;
756 case 2:
757 switch ((config0 & MIPS_CONF_AR) >> 10) {
758 case 0:
759 set_isa(c, MIPS_CPU_ISA_M64R1);
760 break;
761 case 1:
762 set_isa(c, MIPS_CPU_ISA_M64R2);
763 break;
764 case 2:
765 set_isa(c, MIPS_CPU_ISA_M64R6);
766 break;
767 default:
768 goto unknown;
769 }
770 break;
771 default:
772 goto unknown;
773 }
774
775 return config0 & MIPS_CONF_M;
776
777unknown:
778 panic(unknown_isa, config0);
779}
780
781static inline unsigned int decode_config1(struct cpuinfo_mips *c)
782{
783 unsigned int config1;
784
785 config1 = read_c0_config1();
786
787 if (config1 & MIPS_CONF1_MD)
788 c->ases |= MIPS_ASE_MDMX;
789 if (config1 & MIPS_CONF1_PC)
790 c->options |= MIPS_CPU_PERF;
791 if (config1 & MIPS_CONF1_WR)
792 c->options |= MIPS_CPU_WATCH;
793 if (config1 & MIPS_CONF1_CA)
794 c->ases |= MIPS_ASE_MIPS16;
795 if (config1 & MIPS_CONF1_EP)
796 c->options |= MIPS_CPU_EJTAG;
797 if (config1 & MIPS_CONF1_FP) {
798 c->options |= MIPS_CPU_FPU;
799 c->options |= MIPS_CPU_32FPR;
800 }
801 if (cpu_has_tlb) {
802 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
803 c->tlbsizevtlb = c->tlbsize;
804 c->tlbsizeftlbsets = 0;
805 }
806
807 return config1 & MIPS_CONF_M;
808}
809
810static inline unsigned int decode_config2(struct cpuinfo_mips *c)
811{
812 unsigned int config2;
813
814 config2 = read_c0_config2();
815
816 if (config2 & MIPS_CONF2_SL)
817 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
818
819 return config2 & MIPS_CONF_M;
820}
821
822static inline unsigned int decode_config3(struct cpuinfo_mips *c)
823{
824 unsigned int config3;
825
826 config3 = read_c0_config3();
827
828 if (config3 & MIPS_CONF3_SM) {
829 c->ases |= MIPS_ASE_SMARTMIPS;
830 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
831 }
832 if (config3 & MIPS_CONF3_RXI)
833 c->options |= MIPS_CPU_RIXI;
834 if (config3 & MIPS_CONF3_CTXTC)
835 c->options |= MIPS_CPU_CTXTC;
836 if (config3 & MIPS_CONF3_DSP)
837 c->ases |= MIPS_ASE_DSP;
838 if (config3 & MIPS_CONF3_DSP2P) {
839 c->ases |= MIPS_ASE_DSP2P;
840 if (cpu_has_mips_r6)
841 c->ases |= MIPS_ASE_DSP3;
842 }
843 if (config3 & MIPS_CONF3_VINT)
844 c->options |= MIPS_CPU_VINT;
845 if (config3 & MIPS_CONF3_VEIC)
846 c->options |= MIPS_CPU_VEIC;
847 if (config3 & MIPS_CONF3_LPA)
848 c->options |= MIPS_CPU_LPA;
849 if (config3 & MIPS_CONF3_MT)
850 c->ases |= MIPS_ASE_MIPSMT;
851 if (config3 & MIPS_CONF3_ULRI)
852 c->options |= MIPS_CPU_ULRI;
853 if (config3 & MIPS_CONF3_ISA)
854 c->options |= MIPS_CPU_MICROMIPS;
855 if (config3 & MIPS_CONF3_VZ)
856 c->ases |= MIPS_ASE_VZ;
857 if (config3 & MIPS_CONF3_SC)
858 c->options |= MIPS_CPU_SEGMENTS;
859 if (config3 & MIPS_CONF3_BI)
860 c->options |= MIPS_CPU_BADINSTR;
861 if (config3 & MIPS_CONF3_BP)
862 c->options |= MIPS_CPU_BADINSTRP;
863 if (config3 & MIPS_CONF3_MSA)
864 c->ases |= MIPS_ASE_MSA;
865 if (config3 & MIPS_CONF3_PW) {
866 c->htw_seq = 0;
867 c->options |= MIPS_CPU_HTW;
868 }
869 if (config3 & MIPS_CONF3_CDMM)
870 c->options |= MIPS_CPU_CDMM;
871 if (config3 & MIPS_CONF3_SP)
872 c->options |= MIPS_CPU_SP;
873
874 return config3 & MIPS_CONF_M;
875}
876
877static inline unsigned int decode_config4(struct cpuinfo_mips *c)
878{
879 unsigned int config4;
880 unsigned int newcf4;
881 unsigned int mmuextdef;
882 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
883 unsigned long asid_mask;
884
885 config4 = read_c0_config4();
886
887 if (cpu_has_tlb) {
888 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
889 c->options |= MIPS_CPU_TLBINV;
890
891 /*
892 * R6 has dropped the MMUExtDef field from config4.
893 * On R6 the fields always describe the FTLB, and only if it is
894 * present according to Config.MT.
895 */
896 if (!cpu_has_mips_r6)
897 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
898 else if (cpu_has_ftlb)
899 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
900 else
901 mmuextdef = 0;
902
903 switch (mmuextdef) {
904 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
905 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
906 c->tlbsizevtlb = c->tlbsize;
907 break;
908 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
909 c->tlbsizevtlb +=
910 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
911 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
912 c->tlbsize = c->tlbsizevtlb;
913 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
914 fallthrough;
915 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
916 if (mips_ftlb_disabled)
917 break;
918 newcf4 = (config4 & ~ftlb_page) |
919 (page_size_ftlb(mmuextdef) <<
920 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
921 write_c0_config4(newcf4);
922 back_to_back_c0_hazard();
923 config4 = read_c0_config4();
924 if (config4 != newcf4) {
925 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
926 PAGE_SIZE, config4);
927 /* Switch FTLB off */
928 set_ftlb_enable(c, 0);
929 mips_ftlb_disabled = 1;
930 break;
931 }
932 c->tlbsizeftlbsets = 1 <<
933 ((config4 & MIPS_CONF4_FTLBSETS) >>
934 MIPS_CONF4_FTLBSETS_SHIFT);
935 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
936 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
937 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
938 mips_has_ftlb_configured = 1;
939 break;
940 }
941 }
942
943 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
944 >> MIPS_CONF4_KSCREXIST_SHIFT;
945
946 asid_mask = MIPS_ENTRYHI_ASID;
947 if (config4 & MIPS_CONF4_AE)
948 asid_mask |= MIPS_ENTRYHI_ASIDX;
949 set_cpu_asid_mask(c, asid_mask);
950
951 /*
952 * Warn if the computed ASID mask doesn't match the mask the kernel
953 * is built for. This may indicate either a serious problem or an
954 * easy optimisation opportunity, but either way should be addressed.
955 */
956 WARN_ON(asid_mask != cpu_asid_mask(c));
957
958 return config4 & MIPS_CONF_M;
959}
960
961static inline unsigned int decode_config5(struct cpuinfo_mips *c)
962{
963 unsigned int config5, max_mmid_width;
964 unsigned long asid_mask;
965
966 config5 = read_c0_config5();
967 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
968
969 if (cpu_has_mips_r6) {
970 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
971 config5 |= MIPS_CONF5_MI;
972 else
973 config5 &= ~MIPS_CONF5_MI;
974 }
975
976 write_c0_config5(config5);
977
978 if (config5 & MIPS_CONF5_EVA)
979 c->options |= MIPS_CPU_EVA;
980 if (config5 & MIPS_CONF5_MRP)
981 c->options |= MIPS_CPU_MAAR;
982 if (config5 & MIPS_CONF5_LLB)
983 c->options |= MIPS_CPU_RW_LLB;
984 if (config5 & MIPS_CONF5_MVH)
985 c->options |= MIPS_CPU_MVH;
986 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
987 c->options |= MIPS_CPU_VP;
988 if (config5 & MIPS_CONF5_CA2)
989 c->ases |= MIPS_ASE_MIPS16E2;
990
991 if (config5 & MIPS_CONF5_CRCP)
992 elf_hwcap |= HWCAP_MIPS_CRC32;
993
994 if (cpu_has_mips_r6) {
995 /* Ensure the write to config5 above takes effect */
996 back_to_back_c0_hazard();
997
998 /* Check whether we successfully enabled MMID support */
999 config5 = read_c0_config5();
1000 if (config5 & MIPS_CONF5_MI)
1001 c->options |= MIPS_CPU_MMID;
1002
1003 /*
1004 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
1005 * for the CPU we're running on, or if CPUs in an SMP system
1006 * have inconsistent MMID support.
1007 */
1008 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
1009
1010 if (cpu_has_mmid) {
1011 write_c0_memorymapid(~0ul);
1012 back_to_back_c0_hazard();
1013 asid_mask = read_c0_memorymapid();
1014
1015 /*
1016 * We maintain a bitmap to track MMID allocation, and
1017 * need a sensible upper bound on the size of that
1018 * bitmap. The initial CPU with MMID support (I6500)
1019 * supports 16 bit MMIDs, which gives us an 8KiB
1020 * bitmap. The architecture recommends that hardware
1021 * support 32 bit MMIDs, which would give us a 512MiB
1022 * bitmap - that's too big in most cases.
1023 *
1024 * Cap MMID width at 16 bits for now & we can revisit
1025 * this if & when hardware supports anything wider.
1026 */
1027 max_mmid_width = 16;
1028 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
1029 pr_info("Capping MMID width at %d bits",
1030 max_mmid_width);
1031 asid_mask = GENMASK(max_mmid_width - 1, 0);
1032 }
1033
1034 set_cpu_asid_mask(c, asid_mask);
1035 }
1036 }
1037
1038 return config5 & MIPS_CONF_M;
1039}
1040
1041static void decode_configs(struct cpuinfo_mips *c)
1042{
1043 int ok;
1044
1045 /* MIPS32 or MIPS64 compliant CPU. */
1046 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
1047 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
1048
1049 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
1050
1051 /* Enable FTLB if present and not disabled */
1052 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
1053
1054 ok = decode_config0(c); /* Read Config registers. */
1055 BUG_ON(!ok); /* Arch spec violation! */
1056 if (ok)
1057 ok = decode_config1(c);
1058 if (ok)
1059 ok = decode_config2(c);
1060 if (ok)
1061 ok = decode_config3(c);
1062 if (ok)
1063 ok = decode_config4(c);
1064 if (ok)
1065 ok = decode_config5(c);
1066
1067 /* Probe the EBase.WG bit */
1068 if (cpu_has_mips_r2_r6) {
1069 u64 ebase;
1070 unsigned int status;
1071
1072 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
1073 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
1074 : (s32)read_c0_ebase();
1075 if (ebase & MIPS_EBASE_WG) {
1076 /* WG bit already set, we can avoid the clumsy probe */
1077 c->options |= MIPS_CPU_EBASE_WG;
1078 } else {
1079 /* Its UNDEFINED to change EBase while BEV=0 */
1080 status = read_c0_status();
1081 write_c0_status(status | ST0_BEV);
1082 irq_enable_hazard();
1083 /*
1084 * On pre-r6 cores, this may well clobber the upper bits
1085 * of EBase. This is hard to avoid without potentially
1086 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
1087 */
1088 if (cpu_has_mips64r6)
1089 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
1090 else
1091 write_c0_ebase(ebase | MIPS_EBASE_WG);
1092 back_to_back_c0_hazard();
1093 /* Restore BEV */
1094 write_c0_status(status);
1095 if (read_c0_ebase() & MIPS_EBASE_WG) {
1096 c->options |= MIPS_CPU_EBASE_WG;
1097 write_c0_ebase(ebase);
1098 }
1099 }
1100 }
1101
1102 /* configure the FTLB write probability */
1103 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1104
1105 mips_probe_watch_registers(c);
1106
1107#ifndef CONFIG_MIPS_CPS
1108 if (cpu_has_mips_r2_r6) {
1109 unsigned int core;
1110
1111 core = get_ebase_cpunum();
1112 if (cpu_has_mipsmt)
1113 core >>= fls(core_nvpes()) - 1;
1114 cpu_set_core(c, core);
1115 }
1116#endif
1117}
1118
1119/*
1120 * Probe for certain guest capabilities by writing config bits and reading back.
1121 * Finally write back the original value.
1122 */
1123#define probe_gc0_config(name, maxconf, bits) \
1124do { \
1125 unsigned int tmp; \
1126 tmp = read_gc0_##name(); \
1127 write_gc0_##name(tmp | (bits)); \
1128 back_to_back_c0_hazard(); \
1129 maxconf = read_gc0_##name(); \
1130 write_gc0_##name(tmp); \
1131} while (0)
1132
1133/*
1134 * Probe for dynamic guest capabilities by changing certain config bits and
1135 * reading back to see if they change. Finally write back the original value.
1136 */
1137#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
1138do { \
1139 maxconf = read_gc0_##name(); \
1140 write_gc0_##name(maxconf ^ (bits)); \
1141 back_to_back_c0_hazard(); \
1142 dynconf = maxconf ^ read_gc0_##name(); \
1143 write_gc0_##name(maxconf); \
1144 maxconf |= dynconf; \
1145} while (0)
1146
1147static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1148{
1149 unsigned int config0;
1150
1151 probe_gc0_config(config, config0, MIPS_CONF_M);
1152
1153 if (config0 & MIPS_CONF_M)
1154 c->guest.conf |= BIT(1);
1155 return config0 & MIPS_CONF_M;
1156}
1157
1158static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1159{
1160 unsigned int config1, config1_dyn;
1161
1162 probe_gc0_config_dyn(config1, config1, config1_dyn,
1163 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1164 MIPS_CONF1_FP);
1165
1166 if (config1 & MIPS_CONF1_FP)
1167 c->guest.options |= MIPS_CPU_FPU;
1168 if (config1_dyn & MIPS_CONF1_FP)
1169 c->guest.options_dyn |= MIPS_CPU_FPU;
1170
1171 if (config1 & MIPS_CONF1_WR)
1172 c->guest.options |= MIPS_CPU_WATCH;
1173 if (config1_dyn & MIPS_CONF1_WR)
1174 c->guest.options_dyn |= MIPS_CPU_WATCH;
1175
1176 if (config1 & MIPS_CONF1_PC)
1177 c->guest.options |= MIPS_CPU_PERF;
1178 if (config1_dyn & MIPS_CONF1_PC)
1179 c->guest.options_dyn |= MIPS_CPU_PERF;
1180
1181 if (config1 & MIPS_CONF_M)
1182 c->guest.conf |= BIT(2);
1183 return config1 & MIPS_CONF_M;
1184}
1185
1186static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1187{
1188 unsigned int config2;
1189
1190 probe_gc0_config(config2, config2, MIPS_CONF_M);
1191
1192 if (config2 & MIPS_CONF_M)
1193 c->guest.conf |= BIT(3);
1194 return config2 & MIPS_CONF_M;
1195}
1196
1197static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1198{
1199 unsigned int config3, config3_dyn;
1200
1201 probe_gc0_config_dyn(config3, config3, config3_dyn,
1202 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1203 MIPS_CONF3_CTXTC);
1204
1205 if (config3 & MIPS_CONF3_CTXTC)
1206 c->guest.options |= MIPS_CPU_CTXTC;
1207 if (config3_dyn & MIPS_CONF3_CTXTC)
1208 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1209
1210 if (config3 & MIPS_CONF3_PW)
1211 c->guest.options |= MIPS_CPU_HTW;
1212
1213 if (config3 & MIPS_CONF3_ULRI)
1214 c->guest.options |= MIPS_CPU_ULRI;
1215
1216 if (config3 & MIPS_CONF3_SC)
1217 c->guest.options |= MIPS_CPU_SEGMENTS;
1218
1219 if (config3 & MIPS_CONF3_BI)
1220 c->guest.options |= MIPS_CPU_BADINSTR;
1221 if (config3 & MIPS_CONF3_BP)
1222 c->guest.options |= MIPS_CPU_BADINSTRP;
1223
1224 if (config3 & MIPS_CONF3_MSA)
1225 c->guest.ases |= MIPS_ASE_MSA;
1226 if (config3_dyn & MIPS_CONF3_MSA)
1227 c->guest.ases_dyn |= MIPS_ASE_MSA;
1228
1229 if (config3 & MIPS_CONF_M)
1230 c->guest.conf |= BIT(4);
1231 return config3 & MIPS_CONF_M;
1232}
1233
1234static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1235{
1236 unsigned int config4;
1237
1238 probe_gc0_config(config4, config4,
1239 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1240
1241 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1242 >> MIPS_CONF4_KSCREXIST_SHIFT;
1243
1244 if (config4 & MIPS_CONF_M)
1245 c->guest.conf |= BIT(5);
1246 return config4 & MIPS_CONF_M;
1247}
1248
1249static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1250{
1251 unsigned int config5, config5_dyn;
1252
1253 probe_gc0_config_dyn(config5, config5, config5_dyn,
1254 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1255
1256 if (config5 & MIPS_CONF5_MRP)
1257 c->guest.options |= MIPS_CPU_MAAR;
1258 if (config5_dyn & MIPS_CONF5_MRP)
1259 c->guest.options_dyn |= MIPS_CPU_MAAR;
1260
1261 if (config5 & MIPS_CONF5_LLB)
1262 c->guest.options |= MIPS_CPU_RW_LLB;
1263
1264 if (config5 & MIPS_CONF5_MVH)
1265 c->guest.options |= MIPS_CPU_MVH;
1266
1267 if (config5 & MIPS_CONF_M)
1268 c->guest.conf |= BIT(6);
1269 return config5 & MIPS_CONF_M;
1270}
1271
1272static inline void decode_guest_configs(struct cpuinfo_mips *c)
1273{
1274 unsigned int ok;
1275
1276 ok = decode_guest_config0(c);
1277 if (ok)
1278 ok = decode_guest_config1(c);
1279 if (ok)
1280 ok = decode_guest_config2(c);
1281 if (ok)
1282 ok = decode_guest_config3(c);
1283 if (ok)
1284 ok = decode_guest_config4(c);
1285 if (ok)
1286 decode_guest_config5(c);
1287}
1288
1289static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1290{
1291 unsigned int guestctl0, temp;
1292
1293 guestctl0 = read_c0_guestctl0();
1294
1295 if (guestctl0 & MIPS_GCTL0_G0E)
1296 c->options |= MIPS_CPU_GUESTCTL0EXT;
1297 if (guestctl0 & MIPS_GCTL0_G1)
1298 c->options |= MIPS_CPU_GUESTCTL1;
1299 if (guestctl0 & MIPS_GCTL0_G2)
1300 c->options |= MIPS_CPU_GUESTCTL2;
1301 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1302 c->options |= MIPS_CPU_GUESTID;
1303
1304 /*
1305 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1306 * first, otherwise all data accesses will be fully virtualised
1307 * as if they were performed by guest mode.
1308 */
1309 write_c0_guestctl1(0);
1310 tlbw_use_hazard();
1311
1312 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1313 back_to_back_c0_hazard();
1314 temp = read_c0_guestctl0();
1315
1316 if (temp & MIPS_GCTL0_DRG) {
1317 write_c0_guestctl0(guestctl0);
1318 c->options |= MIPS_CPU_DRG;
1319 }
1320 }
1321}
1322
1323static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1324{
1325 if (cpu_has_guestid) {
1326 /* determine the number of bits of GuestID available */
1327 write_c0_guestctl1(MIPS_GCTL1_ID);
1328 back_to_back_c0_hazard();
1329 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1330 >> MIPS_GCTL1_ID_SHIFT;
1331 write_c0_guestctl1(0);
1332 }
1333}
1334
1335static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1336{
1337 /* determine the number of bits of GTOffset available */
1338 write_c0_gtoffset(0xffffffff);
1339 back_to_back_c0_hazard();
1340 c->gtoffset_mask = read_c0_gtoffset();
1341 write_c0_gtoffset(0);
1342}
1343
1344static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1345{
1346 cpu_probe_guestctl0(c);
1347 if (cpu_has_guestctl1)
1348 cpu_probe_guestctl1(c);
1349
1350 cpu_probe_gtoffset(c);
1351
1352 decode_guest_configs(c);
1353}
1354
1355#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1356 | MIPS_CPU_COUNTER)
1357
1358static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1359{
1360 switch (c->processor_id & PRID_IMP_MASK) {
1361 case PRID_IMP_R2000:
1362 c->cputype = CPU_R2000;
1363 __cpu_name[cpu] = "R2000";
1364 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1365 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1366 MIPS_CPU_NOFPUEX;
1367 if (__cpu_has_fpu())
1368 c->options |= MIPS_CPU_FPU;
1369 c->tlbsize = 64;
1370 break;
1371 case PRID_IMP_R3000:
1372 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1373 if (cpu_has_confreg()) {
1374 c->cputype = CPU_R3081E;
1375 __cpu_name[cpu] = "R3081";
1376 } else {
1377 c->cputype = CPU_R3000A;
1378 __cpu_name[cpu] = "R3000A";
1379 }
1380 } else {
1381 c->cputype = CPU_R3000;
1382 __cpu_name[cpu] = "R3000";
1383 }
1384 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1385 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1386 MIPS_CPU_NOFPUEX;
1387 if (__cpu_has_fpu())
1388 c->options |= MIPS_CPU_FPU;
1389 c->tlbsize = 64;
1390 break;
1391 case PRID_IMP_R4000:
1392 if (read_c0_config() & CONF_SC) {
1393 if ((c->processor_id & PRID_REV_MASK) >=
1394 PRID_REV_R4400) {
1395 c->cputype = CPU_R4400PC;
1396 __cpu_name[cpu] = "R4400PC";
1397 } else {
1398 c->cputype = CPU_R4000PC;
1399 __cpu_name[cpu] = "R4000PC";
1400 }
1401 } else {
1402 int cca = read_c0_config() & CONF_CM_CMASK;
1403 int mc;
1404
1405 /*
1406 * SC and MC versions can't be reliably told apart,
1407 * but only the latter support coherent caching
1408 * modes so assume the firmware has set the KSEG0
1409 * coherency attribute reasonably (if uncached, we
1410 * assume SC).
1411 */
1412 switch (cca) {
1413 case CONF_CM_CACHABLE_CE:
1414 case CONF_CM_CACHABLE_COW:
1415 case CONF_CM_CACHABLE_CUW:
1416 mc = 1;
1417 break;
1418 default:
1419 mc = 0;
1420 break;
1421 }
1422 if ((c->processor_id & PRID_REV_MASK) >=
1423 PRID_REV_R4400) {
1424 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1425 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1426 } else {
1427 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1428 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1429 }
1430 }
1431
1432 set_isa(c, MIPS_CPU_ISA_III);
1433 c->fpu_msk31 |= FPU_CSR_CONDX;
1434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1435 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1436 MIPS_CPU_LLSC;
1437 c->tlbsize = 48;
1438 break;
1439 case PRID_IMP_VR41XX:
1440 set_isa(c, MIPS_CPU_ISA_III);
1441 c->fpu_msk31 |= FPU_CSR_CONDX;
1442 c->options = R4K_OPTS;
1443 c->tlbsize = 32;
1444 switch (c->processor_id & 0xf0) {
1445 case PRID_REV_VR4111:
1446 c->cputype = CPU_VR4111;
1447 __cpu_name[cpu] = "NEC VR4111";
1448 break;
1449 case PRID_REV_VR4121:
1450 c->cputype = CPU_VR4121;
1451 __cpu_name[cpu] = "NEC VR4121";
1452 break;
1453 case PRID_REV_VR4122:
1454 if ((c->processor_id & 0xf) < 0x3) {
1455 c->cputype = CPU_VR4122;
1456 __cpu_name[cpu] = "NEC VR4122";
1457 } else {
1458 c->cputype = CPU_VR4181A;
1459 __cpu_name[cpu] = "NEC VR4181A";
1460 }
1461 break;
1462 case PRID_REV_VR4130:
1463 if ((c->processor_id & 0xf) < 0x4) {
1464 c->cputype = CPU_VR4131;
1465 __cpu_name[cpu] = "NEC VR4131";
1466 } else {
1467 c->cputype = CPU_VR4133;
1468 c->options |= MIPS_CPU_LLSC;
1469 __cpu_name[cpu] = "NEC VR4133";
1470 }
1471 break;
1472 default:
1473 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1474 c->cputype = CPU_VR41XX;
1475 __cpu_name[cpu] = "NEC Vr41xx";
1476 break;
1477 }
1478 break;
1479 case PRID_IMP_R4600:
1480 c->cputype = CPU_R4600;
1481 __cpu_name[cpu] = "R4600";
1482 set_isa(c, MIPS_CPU_ISA_III);
1483 c->fpu_msk31 |= FPU_CSR_CONDX;
1484 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1485 MIPS_CPU_LLSC;
1486 c->tlbsize = 48;
1487 break;
1488 #if 0
1489 case PRID_IMP_R4650:
1490 /*
1491 * This processor doesn't have an MMU, so it's not
1492 * "real easy" to run Linux on it. It is left purely
1493 * for documentation. Commented out because it shares
1494 * it's c0_prid id number with the TX3900.
1495 */
1496 c->cputype = CPU_R4650;
1497 __cpu_name[cpu] = "R4650";
1498 set_isa(c, MIPS_CPU_ISA_III);
1499 c->fpu_msk31 |= FPU_CSR_CONDX;
1500 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1501 c->tlbsize = 48;
1502 break;
1503 #endif
1504 case PRID_IMP_TX39:
1505 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1506 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1507
1508 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1509 c->cputype = CPU_TX3927;
1510 __cpu_name[cpu] = "TX3927";
1511 c->tlbsize = 64;
1512 } else {
1513 switch (c->processor_id & PRID_REV_MASK) {
1514 case PRID_REV_TX3912:
1515 c->cputype = CPU_TX3912;
1516 __cpu_name[cpu] = "TX3912";
1517 c->tlbsize = 32;
1518 break;
1519 case PRID_REV_TX3922:
1520 c->cputype = CPU_TX3922;
1521 __cpu_name[cpu] = "TX3922";
1522 c->tlbsize = 64;
1523 break;
1524 }
1525 }
1526 break;
1527 case PRID_IMP_R4700:
1528 c->cputype = CPU_R4700;
1529 __cpu_name[cpu] = "R4700";
1530 set_isa(c, MIPS_CPU_ISA_III);
1531 c->fpu_msk31 |= FPU_CSR_CONDX;
1532 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1533 MIPS_CPU_LLSC;
1534 c->tlbsize = 48;
1535 break;
1536 case PRID_IMP_TX49:
1537 c->cputype = CPU_TX49XX;
1538 __cpu_name[cpu] = "R49XX";
1539 set_isa(c, MIPS_CPU_ISA_III);
1540 c->fpu_msk31 |= FPU_CSR_CONDX;
1541 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1542 if (!(c->processor_id & 0x08))
1543 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1544 c->tlbsize = 48;
1545 break;
1546 case PRID_IMP_R5000:
1547 c->cputype = CPU_R5000;
1548 __cpu_name[cpu] = "R5000";
1549 set_isa(c, MIPS_CPU_ISA_IV);
1550 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1551 MIPS_CPU_LLSC;
1552 c->tlbsize = 48;
1553 break;
1554 case PRID_IMP_R5500:
1555 c->cputype = CPU_R5500;
1556 __cpu_name[cpu] = "R5500";
1557 set_isa(c, MIPS_CPU_ISA_IV);
1558 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1559 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1560 c->tlbsize = 48;
1561 break;
1562 case PRID_IMP_NEVADA:
1563 c->cputype = CPU_NEVADA;
1564 __cpu_name[cpu] = "Nevada";
1565 set_isa(c, MIPS_CPU_ISA_IV);
1566 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1567 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1568 c->tlbsize = 48;
1569 break;
1570 case PRID_IMP_RM7000:
1571 c->cputype = CPU_RM7000;
1572 __cpu_name[cpu] = "RM7000";
1573 set_isa(c, MIPS_CPU_ISA_IV);
1574 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1575 MIPS_CPU_LLSC;
1576 /*
1577 * Undocumented RM7000: Bit 29 in the info register of
1578 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1579 * entries.
1580 *
1581 * 29 1 => 64 entry JTLB
1582 * 0 => 48 entry JTLB
1583 */
1584 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1585 break;
1586 case PRID_IMP_R10000:
1587 c->cputype = CPU_R10000;
1588 __cpu_name[cpu] = "R10000";
1589 set_isa(c, MIPS_CPU_ISA_IV);
1590 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1591 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1592 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1593 MIPS_CPU_LLSC;
1594 c->tlbsize = 64;
1595 break;
1596 case PRID_IMP_R12000:
1597 c->cputype = CPU_R12000;
1598 __cpu_name[cpu] = "R12000";
1599 set_isa(c, MIPS_CPU_ISA_IV);
1600 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1601 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1602 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1603 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1604 c->tlbsize = 64;
1605 break;
1606 case PRID_IMP_R14000:
1607 if (((c->processor_id >> 4) & 0x0f) > 2) {
1608 c->cputype = CPU_R16000;
1609 __cpu_name[cpu] = "R16000";
1610 } else {
1611 c->cputype = CPU_R14000;
1612 __cpu_name[cpu] = "R14000";
1613 }
1614 set_isa(c, MIPS_CPU_ISA_IV);
1615 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1616 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1617 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1618 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1619 c->tlbsize = 64;
1620 break;
1621 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1622 switch (c->processor_id & PRID_REV_MASK) {
1623 case PRID_REV_LOONGSON2E:
1624 c->cputype = CPU_LOONGSON2EF;
1625 __cpu_name[cpu] = "ICT Loongson-2";
1626 set_elf_platform(cpu, "loongson2e");
1627 set_isa(c, MIPS_CPU_ISA_III);
1628 c->fpu_msk31 |= FPU_CSR_CONDX;
1629 break;
1630 case PRID_REV_LOONGSON2F:
1631 c->cputype = CPU_LOONGSON2EF;
1632 __cpu_name[cpu] = "ICT Loongson-2";
1633 set_elf_platform(cpu, "loongson2f");
1634 set_isa(c, MIPS_CPU_ISA_III);
1635 c->fpu_msk31 |= FPU_CSR_CONDX;
1636 break;
1637 case PRID_REV_LOONGSON3A_R1:
1638 c->cputype = CPU_LOONGSON64;
1639 __cpu_name[cpu] = "ICT Loongson-3";
1640 set_elf_platform(cpu, "loongson3a");
1641 set_isa(c, MIPS_CPU_ISA_M64R1);
1642 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1643 MIPS_ASE_LOONGSON_EXT);
1644 break;
1645 case PRID_REV_LOONGSON3B_R1:
1646 case PRID_REV_LOONGSON3B_R2:
1647 c->cputype = CPU_LOONGSON64;
1648 __cpu_name[cpu] = "ICT Loongson-3";
1649 set_elf_platform(cpu, "loongson3b");
1650 set_isa(c, MIPS_CPU_ISA_M64R1);
1651 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1652 MIPS_ASE_LOONGSON_EXT);
1653 break;
1654 }
1655
1656 c->options = R4K_OPTS |
1657 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1658 MIPS_CPU_32FPR;
1659 c->tlbsize = 64;
1660 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1661 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1662 break;
1663 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1664 decode_configs(c);
1665
1666 c->cputype = CPU_LOONGSON32;
1667
1668 switch (c->processor_id & PRID_REV_MASK) {
1669 case PRID_REV_LOONGSON1B:
1670 __cpu_name[cpu] = "Loongson 1B";
1671 break;
1672 }
1673
1674 break;
1675 }
1676}
1677
1678static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1679{
1680 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1681 switch (c->processor_id & PRID_IMP_MASK) {
1682 case PRID_IMP_QEMU_GENERIC:
1683 c->writecombine = _CACHE_UNCACHED;
1684 c->cputype = CPU_QEMU_GENERIC;
1685 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1686 break;
1687 case PRID_IMP_4KC:
1688 c->cputype = CPU_4KC;
1689 c->writecombine = _CACHE_UNCACHED;
1690 __cpu_name[cpu] = "MIPS 4Kc";
1691 break;
1692 case PRID_IMP_4KEC:
1693 case PRID_IMP_4KECR2:
1694 c->cputype = CPU_4KEC;
1695 c->writecombine = _CACHE_UNCACHED;
1696 __cpu_name[cpu] = "MIPS 4KEc";
1697 break;
1698 case PRID_IMP_4KSC:
1699 case PRID_IMP_4KSD:
1700 c->cputype = CPU_4KSC;
1701 c->writecombine = _CACHE_UNCACHED;
1702 __cpu_name[cpu] = "MIPS 4KSc";
1703 break;
1704 case PRID_IMP_5KC:
1705 c->cputype = CPU_5KC;
1706 c->writecombine = _CACHE_UNCACHED;
1707 __cpu_name[cpu] = "MIPS 5Kc";
1708 break;
1709 case PRID_IMP_5KE:
1710 c->cputype = CPU_5KE;
1711 c->writecombine = _CACHE_UNCACHED;
1712 __cpu_name[cpu] = "MIPS 5KE";
1713 break;
1714 case PRID_IMP_20KC:
1715 c->cputype = CPU_20KC;
1716 c->writecombine = _CACHE_UNCACHED;
1717 __cpu_name[cpu] = "MIPS 20Kc";
1718 break;
1719 case PRID_IMP_24K:
1720 c->cputype = CPU_24K;
1721 c->writecombine = _CACHE_UNCACHED;
1722 __cpu_name[cpu] = "MIPS 24Kc";
1723 break;
1724 case PRID_IMP_24KE:
1725 c->cputype = CPU_24K;
1726 c->writecombine = _CACHE_UNCACHED;
1727 __cpu_name[cpu] = "MIPS 24KEc";
1728 break;
1729 case PRID_IMP_25KF:
1730 c->cputype = CPU_25KF;
1731 c->writecombine = _CACHE_UNCACHED;
1732 __cpu_name[cpu] = "MIPS 25Kc";
1733 break;
1734 case PRID_IMP_34K:
1735 c->cputype = CPU_34K;
1736 c->writecombine = _CACHE_UNCACHED;
1737 __cpu_name[cpu] = "MIPS 34Kc";
1738 cpu_set_mt_per_tc_perf(c);
1739 break;
1740 case PRID_IMP_74K:
1741 c->cputype = CPU_74K;
1742 c->writecombine = _CACHE_UNCACHED;
1743 __cpu_name[cpu] = "MIPS 74Kc";
1744 break;
1745 case PRID_IMP_M14KC:
1746 c->cputype = CPU_M14KC;
1747 c->writecombine = _CACHE_UNCACHED;
1748 __cpu_name[cpu] = "MIPS M14Kc";
1749 break;
1750 case PRID_IMP_M14KEC:
1751 c->cputype = CPU_M14KEC;
1752 c->writecombine = _CACHE_UNCACHED;
1753 __cpu_name[cpu] = "MIPS M14KEc";
1754 break;
1755 case PRID_IMP_1004K:
1756 c->cputype = CPU_1004K;
1757 c->writecombine = _CACHE_UNCACHED;
1758 __cpu_name[cpu] = "MIPS 1004Kc";
1759 cpu_set_mt_per_tc_perf(c);
1760 break;
1761 case PRID_IMP_1074K:
1762 c->cputype = CPU_1074K;
1763 c->writecombine = _CACHE_UNCACHED;
1764 __cpu_name[cpu] = "MIPS 1074Kc";
1765 break;
1766 case PRID_IMP_INTERAPTIV_UP:
1767 c->cputype = CPU_INTERAPTIV;
1768 __cpu_name[cpu] = "MIPS interAptiv";
1769 cpu_set_mt_per_tc_perf(c);
1770 break;
1771 case PRID_IMP_INTERAPTIV_MP:
1772 c->cputype = CPU_INTERAPTIV;
1773 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1774 cpu_set_mt_per_tc_perf(c);
1775 break;
1776 case PRID_IMP_PROAPTIV_UP:
1777 c->cputype = CPU_PROAPTIV;
1778 __cpu_name[cpu] = "MIPS proAptiv";
1779 break;
1780 case PRID_IMP_PROAPTIV_MP:
1781 c->cputype = CPU_PROAPTIV;
1782 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1783 break;
1784 case PRID_IMP_P5600:
1785 c->cputype = CPU_P5600;
1786 __cpu_name[cpu] = "MIPS P5600";
1787 break;
1788 case PRID_IMP_P6600:
1789 c->cputype = CPU_P6600;
1790 __cpu_name[cpu] = "MIPS P6600";
1791 break;
1792 case PRID_IMP_I6400:
1793 c->cputype = CPU_I6400;
1794 __cpu_name[cpu] = "MIPS I6400";
1795 break;
1796 case PRID_IMP_I6500:
1797 c->cputype = CPU_I6500;
1798 __cpu_name[cpu] = "MIPS I6500";
1799 break;
1800 case PRID_IMP_M5150:
1801 c->cputype = CPU_M5150;
1802 __cpu_name[cpu] = "MIPS M5150";
1803 break;
1804 case PRID_IMP_M6250:
1805 c->cputype = CPU_M6250;
1806 __cpu_name[cpu] = "MIPS M6250";
1807 break;
1808 }
1809
1810 decode_configs(c);
1811
1812 spram_config();
1813
1814 mm_config(c);
1815
1816 switch (__get_cpu_type(c->cputype)) {
1817 case CPU_M5150:
1818 case CPU_P5600:
1819 set_isa(c, MIPS_CPU_ISA_M32R5);
1820 break;
1821 case CPU_I6500:
1822 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1823 fallthrough;
1824 case CPU_I6400:
1825 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1826 fallthrough;
1827 default:
1828 break;
1829 }
1830
1831 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1832 * cache/FTLB parity exceptions.
1833 */
1834 switch (__get_cpu_type(c->cputype)) {
1835 case CPU_PROAPTIV:
1836 case CPU_P5600:
1837 case CPU_P6600:
1838 case CPU_I6400:
1839 case CPU_I6500:
1840 c->options |= MIPS_CPU_FTLBPAREX;
1841 break;
1842 }
1843}
1844
1845static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1846{
1847 decode_configs(c);
1848 switch (c->processor_id & PRID_IMP_MASK) {
1849 case PRID_IMP_AU1_REV1:
1850 case PRID_IMP_AU1_REV2:
1851 c->cputype = CPU_ALCHEMY;
1852 switch ((c->processor_id >> 24) & 0xff) {
1853 case 0:
1854 __cpu_name[cpu] = "Au1000";
1855 break;
1856 case 1:
1857 __cpu_name[cpu] = "Au1500";
1858 break;
1859 case 2:
1860 __cpu_name[cpu] = "Au1100";
1861 break;
1862 case 3:
1863 __cpu_name[cpu] = "Au1550";
1864 break;
1865 case 4:
1866 __cpu_name[cpu] = "Au1200";
1867 if ((c->processor_id & PRID_REV_MASK) == 2)
1868 __cpu_name[cpu] = "Au1250";
1869 break;
1870 case 5:
1871 __cpu_name[cpu] = "Au1210";
1872 break;
1873 default:
1874 __cpu_name[cpu] = "Au1xxx";
1875 break;
1876 }
1877 break;
1878 }
1879}
1880
1881static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1882{
1883 decode_configs(c);
1884
1885 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1886 switch (c->processor_id & PRID_IMP_MASK) {
1887 case PRID_IMP_SB1:
1888 c->cputype = CPU_SB1;
1889 __cpu_name[cpu] = "SiByte SB1";
1890 /* FPU in pass1 is known to have issues. */
1891 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1892 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1893 break;
1894 case PRID_IMP_SB1A:
1895 c->cputype = CPU_SB1A;
1896 __cpu_name[cpu] = "SiByte SB1A";
1897 break;
1898 }
1899}
1900
1901static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1902{
1903 decode_configs(c);
1904 switch (c->processor_id & PRID_IMP_MASK) {
1905 case PRID_IMP_SR71000:
1906 c->cputype = CPU_SR71000;
1907 __cpu_name[cpu] = "Sandcraft SR71000";
1908 c->scache.ways = 8;
1909 c->tlbsize = 64;
1910 break;
1911 }
1912}
1913
1914static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1915{
1916 decode_configs(c);
1917 switch (c->processor_id & PRID_IMP_MASK) {
1918 case PRID_IMP_PR4450:
1919 c->cputype = CPU_PR4450;
1920 __cpu_name[cpu] = "Philips PR4450";
1921 set_isa(c, MIPS_CPU_ISA_M32R1);
1922 break;
1923 }
1924}
1925
1926static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1927{
1928 decode_configs(c);
1929 switch (c->processor_id & PRID_IMP_MASK) {
1930 case PRID_IMP_BMIPS32_REV4:
1931 case PRID_IMP_BMIPS32_REV8:
1932 c->cputype = CPU_BMIPS32;
1933 __cpu_name[cpu] = "Broadcom BMIPS32";
1934 set_elf_platform(cpu, "bmips32");
1935 break;
1936 case PRID_IMP_BMIPS3300:
1937 case PRID_IMP_BMIPS3300_ALT:
1938 case PRID_IMP_BMIPS3300_BUG:
1939 c->cputype = CPU_BMIPS3300;
1940 __cpu_name[cpu] = "Broadcom BMIPS3300";
1941 set_elf_platform(cpu, "bmips3300");
1942 break;
1943 case PRID_IMP_BMIPS43XX: {
1944 int rev = c->processor_id & PRID_REV_MASK;
1945
1946 if (rev >= PRID_REV_BMIPS4380_LO &&
1947 rev <= PRID_REV_BMIPS4380_HI) {
1948 c->cputype = CPU_BMIPS4380;
1949 __cpu_name[cpu] = "Broadcom BMIPS4380";
1950 set_elf_platform(cpu, "bmips4380");
1951 c->options |= MIPS_CPU_RIXI;
1952 } else {
1953 c->cputype = CPU_BMIPS4350;
1954 __cpu_name[cpu] = "Broadcom BMIPS4350";
1955 set_elf_platform(cpu, "bmips4350");
1956 }
1957 break;
1958 }
1959 case PRID_IMP_BMIPS5000:
1960 case PRID_IMP_BMIPS5200:
1961 c->cputype = CPU_BMIPS5000;
1962 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1963 __cpu_name[cpu] = "Broadcom BMIPS5200";
1964 else
1965 __cpu_name[cpu] = "Broadcom BMIPS5000";
1966 set_elf_platform(cpu, "bmips5000");
1967 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1968 break;
1969 }
1970}
1971
1972static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1973{
1974 decode_configs(c);
1975 switch (c->processor_id & PRID_IMP_MASK) {
1976 case PRID_IMP_CAVIUM_CN38XX:
1977 case PRID_IMP_CAVIUM_CN31XX:
1978 case PRID_IMP_CAVIUM_CN30XX:
1979 c->cputype = CPU_CAVIUM_OCTEON;
1980 __cpu_name[cpu] = "Cavium Octeon";
1981 goto platform;
1982 case PRID_IMP_CAVIUM_CN58XX:
1983 case PRID_IMP_CAVIUM_CN56XX:
1984 case PRID_IMP_CAVIUM_CN50XX:
1985 case PRID_IMP_CAVIUM_CN52XX:
1986 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1987 __cpu_name[cpu] = "Cavium Octeon+";
1988platform:
1989 set_elf_platform(cpu, "octeon");
1990 break;
1991 case PRID_IMP_CAVIUM_CN61XX:
1992 case PRID_IMP_CAVIUM_CN63XX:
1993 case PRID_IMP_CAVIUM_CN66XX:
1994 case PRID_IMP_CAVIUM_CN68XX:
1995 case PRID_IMP_CAVIUM_CNF71XX:
1996 c->cputype = CPU_CAVIUM_OCTEON2;
1997 __cpu_name[cpu] = "Cavium Octeon II";
1998 set_elf_platform(cpu, "octeon2");
1999 break;
2000 case PRID_IMP_CAVIUM_CN70XX:
2001 case PRID_IMP_CAVIUM_CN73XX:
2002 case PRID_IMP_CAVIUM_CNF75XX:
2003 case PRID_IMP_CAVIUM_CN78XX:
2004 c->cputype = CPU_CAVIUM_OCTEON3;
2005 __cpu_name[cpu] = "Cavium Octeon III";
2006 set_elf_platform(cpu, "octeon3");
2007 break;
2008 default:
2009 printk(KERN_INFO "Unknown Octeon chip!\n");
2010 c->cputype = CPU_UNKNOWN;
2011 break;
2012 }
2013}
2014
2015#ifdef CONFIG_CPU_LOONGSON64
2016#include <loongson_regs.h>
2017
2018static inline void decode_cpucfg(struct cpuinfo_mips *c)
2019{
2020 u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
2021 u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
2022 u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
2023
2024 if (cfg1 & LOONGSON_CFG1_MMI)
2025 c->ases |= MIPS_ASE_LOONGSON_MMI;
2026
2027 if (cfg2 & LOONGSON_CFG2_LEXT1)
2028 c->ases |= MIPS_ASE_LOONGSON_EXT;
2029
2030 if (cfg2 & LOONGSON_CFG2_LEXT2)
2031 c->ases |= MIPS_ASE_LOONGSON_EXT2;
2032
2033 if (cfg2 & LOONGSON_CFG2_LSPW) {
2034 c->options |= MIPS_CPU_LDPTE;
2035 c->guest.options |= MIPS_CPU_LDPTE;
2036 }
2037
2038 if (cfg3 & LOONGSON_CFG3_LCAMP)
2039 c->ases |= MIPS_ASE_LOONGSON_CAM;
2040}
2041
2042static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
2043{
2044 decode_configs(c);
2045
2046 /* All Loongson processors covered here define ExcCode 16 as GSExc. */
2047 c->options |= MIPS_CPU_GSEXCEX;
2048
2049 switch (c->processor_id & PRID_IMP_MASK) {
2050 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
2051 switch (c->processor_id & PRID_REV_MASK) {
2052 case PRID_REV_LOONGSON2K_R1_0:
2053 case PRID_REV_LOONGSON2K_R1_1:
2054 case PRID_REV_LOONGSON2K_R1_2:
2055 case PRID_REV_LOONGSON2K_R1_3:
2056 c->cputype = CPU_LOONGSON64;
2057 __cpu_name[cpu] = "Loongson-2K";
2058 set_elf_platform(cpu, "gs264e");
2059 set_isa(c, MIPS_CPU_ISA_M64R2);
2060 break;
2061 }
2062 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2063 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
2064 MIPS_ASE_LOONGSON_EXT2);
2065 break;
2066 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
2067 switch (c->processor_id & PRID_REV_MASK) {
2068 case PRID_REV_LOONGSON3A_R2_0:
2069 case PRID_REV_LOONGSON3A_R2_1:
2070 c->cputype = CPU_LOONGSON64;
2071 __cpu_name[cpu] = "ICT Loongson-3";
2072 set_elf_platform(cpu, "loongson3a");
2073 set_isa(c, MIPS_CPU_ISA_M64R2);
2074 break;
2075 case PRID_REV_LOONGSON3A_R3_0:
2076 case PRID_REV_LOONGSON3A_R3_1:
2077 c->cputype = CPU_LOONGSON64;
2078 __cpu_name[cpu] = "ICT Loongson-3";
2079 set_elf_platform(cpu, "loongson3a");
2080 set_isa(c, MIPS_CPU_ISA_M64R2);
2081 break;
2082 }
2083 /*
2084 * Loongson-3 Classic did not implement MIPS standard TLBINV
2085 * but implemented TLBINVF and EHINV. As currently we're only
2086 * using these two features, enable MIPS_CPU_TLBINV as well.
2087 *
2088 * Also some early Loongson-3A2000 had wrong TLB type in Config
2089 * register, we correct it here.
2090 */
2091 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
2092 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2093 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
2094 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
2095 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
2096 break;
2097 case PRID_IMP_LOONGSON_64G:
2098 c->cputype = CPU_LOONGSON64;
2099 __cpu_name[cpu] = "ICT Loongson-3";
2100 set_elf_platform(cpu, "loongson3a");
2101 set_isa(c, MIPS_CPU_ISA_M64R2);
2102 decode_cpucfg(c);
2103 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2104 break;
2105 default:
2106 panic("Unknown Loongson Processor ID!");
2107 break;
2108 }
2109}
2110#else
2111static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
2112#endif
2113
2114static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
2115{
2116 decode_configs(c);
2117
2118 /*
2119 * XBurst misses a config2 register, so config3 decode was skipped in
2120 * decode_configs().
2121 */
2122 decode_config3(c);
2123
2124 /* XBurst does not implement the CP0 counter. */
2125 c->options &= ~MIPS_CPU_COUNTER;
2126 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
2127
2128 switch (c->processor_id & PRID_IMP_MASK) {
2129
2130 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
2131 case PRID_IMP_XBURST_REV1:
2132
2133 /*
2134 * The XBurst core by default attempts to avoid branch target
2135 * buffer lookups by detecting & special casing loops. This
2136 * feature will cause BogoMIPS and lpj calculate in error.
2137 * Set cp0 config7 bit 4 to disable this feature.
2138 */
2139 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
2140
2141 switch (c->processor_id & PRID_COMP_MASK) {
2142
2143 /*
2144 * The config0 register in the XBurst CPUs with a processor ID of
2145 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
2146 * but they don't actually support this ISA.
2147 */
2148 case PRID_COMP_INGENIC_D0:
2149 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
2150 break;
2151
2152 /*
2153 * The config0 register in the XBurst CPUs with a processor ID of
2154 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
2155 * mode is not compatible with the MIPS standard, it will cause
2156 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
2157 * when starting the init process. After chip reset, the default
2158 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
2159 * switch back to VTLB mode to prevent getting stuck.
2160 */
2161 case PRID_COMP_INGENIC_D1:
2162 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
2163 break;
2164
2165 default:
2166 break;
2167 }
2168 fallthrough;
2169
2170 /* XBurst®1 with MXU2.0 SIMD ISA */
2171 case PRID_IMP_XBURST_REV2:
2172 c->cputype = CPU_XBURST;
2173 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
2174 __cpu_name[cpu] = "Ingenic XBurst";
2175 break;
2176
2177 /* XBurst®2 with MXU2.1 SIMD ISA */
2178 case PRID_IMP_XBURST2:
2179 c->cputype = CPU_XBURST;
2180 __cpu_name[cpu] = "Ingenic XBurst II";
2181 break;
2182
2183 default:
2184 panic("Unknown Ingenic Processor ID!");
2185 break;
2186 }
2187}
2188
2189static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
2190{
2191 decode_configs(c);
2192
2193 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
2194 c->cputype = CPU_ALCHEMY;
2195 __cpu_name[cpu] = "Au1300";
2196 /* following stuff is not for Alchemy */
2197 return;
2198 }
2199
2200 c->options = (MIPS_CPU_TLB |
2201 MIPS_CPU_4KEX |
2202 MIPS_CPU_COUNTER |
2203 MIPS_CPU_DIVEC |
2204 MIPS_CPU_WATCH |
2205 MIPS_CPU_EJTAG |
2206 MIPS_CPU_LLSC);
2207
2208 switch (c->processor_id & PRID_IMP_MASK) {
2209 case PRID_IMP_NETLOGIC_XLP2XX:
2210 case PRID_IMP_NETLOGIC_XLP9XX:
2211 case PRID_IMP_NETLOGIC_XLP5XX:
2212 c->cputype = CPU_XLP;
2213 __cpu_name[cpu] = "Broadcom XLPII";
2214 break;
2215
2216 case PRID_IMP_NETLOGIC_XLP8XX:
2217 case PRID_IMP_NETLOGIC_XLP3XX:
2218 c->cputype = CPU_XLP;
2219 __cpu_name[cpu] = "Netlogic XLP";
2220 break;
2221
2222 case PRID_IMP_NETLOGIC_XLR732:
2223 case PRID_IMP_NETLOGIC_XLR716:
2224 case PRID_IMP_NETLOGIC_XLR532:
2225 case PRID_IMP_NETLOGIC_XLR308:
2226 case PRID_IMP_NETLOGIC_XLR532C:
2227 case PRID_IMP_NETLOGIC_XLR516C:
2228 case PRID_IMP_NETLOGIC_XLR508C:
2229 case PRID_IMP_NETLOGIC_XLR308C:
2230 c->cputype = CPU_XLR;
2231 __cpu_name[cpu] = "Netlogic XLR";
2232 break;
2233
2234 case PRID_IMP_NETLOGIC_XLS608:
2235 case PRID_IMP_NETLOGIC_XLS408:
2236 case PRID_IMP_NETLOGIC_XLS404:
2237 case PRID_IMP_NETLOGIC_XLS208:
2238 case PRID_IMP_NETLOGIC_XLS204:
2239 case PRID_IMP_NETLOGIC_XLS108:
2240 case PRID_IMP_NETLOGIC_XLS104:
2241 case PRID_IMP_NETLOGIC_XLS616B:
2242 case PRID_IMP_NETLOGIC_XLS608B:
2243 case PRID_IMP_NETLOGIC_XLS416B:
2244 case PRID_IMP_NETLOGIC_XLS412B:
2245 case PRID_IMP_NETLOGIC_XLS408B:
2246 case PRID_IMP_NETLOGIC_XLS404B:
2247 c->cputype = CPU_XLR;
2248 __cpu_name[cpu] = "Netlogic XLS";
2249 break;
2250
2251 default:
2252 pr_info("Unknown Netlogic chip id [%02x]!\n",
2253 c->processor_id);
2254 c->cputype = CPU_XLR;
2255 break;
2256 }
2257
2258 if (c->cputype == CPU_XLP) {
2259 set_isa(c, MIPS_CPU_ISA_M64R2);
2260 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2261 /* This will be updated again after all threads are woken up */
2262 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2263 } else {
2264 set_isa(c, MIPS_CPU_ISA_M64R1);
2265 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2266 }
2267 c->kscratch_mask = 0xf;
2268}
2269
2270#ifdef CONFIG_64BIT
2271/* For use by uaccess.h */
2272u64 __ua_limit;
2273EXPORT_SYMBOL(__ua_limit);
2274#endif
2275
2276const char *__cpu_name[NR_CPUS];
2277const char *__elf_platform;
2278const char *__elf_base_platform;
2279
2280void cpu_probe(void)
2281{
2282 struct cpuinfo_mips *c = ¤t_cpu_data;
2283 unsigned int cpu = smp_processor_id();
2284
2285 /*
2286 * Set a default elf platform, cpu probe may later
2287 * overwrite it with a more precise value
2288 */
2289 set_elf_platform(cpu, "mips");
2290
2291 c->processor_id = PRID_IMP_UNKNOWN;
2292 c->fpu_id = FPIR_IMP_NONE;
2293 c->cputype = CPU_UNKNOWN;
2294 c->writecombine = _CACHE_UNCACHED;
2295
2296 c->fpu_csr31 = FPU_CSR_RN;
2297 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2298
2299 c->processor_id = read_c0_prid();
2300 switch (c->processor_id & PRID_COMP_MASK) {
2301 case PRID_COMP_LEGACY:
2302 cpu_probe_legacy(c, cpu);
2303 break;
2304 case PRID_COMP_MIPS:
2305 cpu_probe_mips(c, cpu);
2306 break;
2307 case PRID_COMP_ALCHEMY:
2308 cpu_probe_alchemy(c, cpu);
2309 break;
2310 case PRID_COMP_SIBYTE:
2311 cpu_probe_sibyte(c, cpu);
2312 break;
2313 case PRID_COMP_BROADCOM:
2314 cpu_probe_broadcom(c, cpu);
2315 break;
2316 case PRID_COMP_SANDCRAFT:
2317 cpu_probe_sandcraft(c, cpu);
2318 break;
2319 case PRID_COMP_NXP:
2320 cpu_probe_nxp(c, cpu);
2321 break;
2322 case PRID_COMP_CAVIUM:
2323 cpu_probe_cavium(c, cpu);
2324 break;
2325 case PRID_COMP_LOONGSON:
2326 cpu_probe_loongson(c, cpu);
2327 break;
2328 case PRID_COMP_INGENIC_13:
2329 case PRID_COMP_INGENIC_D0:
2330 case PRID_COMP_INGENIC_D1:
2331 case PRID_COMP_INGENIC_E1:
2332 cpu_probe_ingenic(c, cpu);
2333 break;
2334 case PRID_COMP_NETLOGIC:
2335 cpu_probe_netlogic(c, cpu);
2336 break;
2337 }
2338
2339 BUG_ON(!__cpu_name[cpu]);
2340 BUG_ON(c->cputype == CPU_UNKNOWN);
2341
2342 /*
2343 * Platform code can force the cpu type to optimize code
2344 * generation. In that case be sure the cpu type is correctly
2345 * manually setup otherwise it could trigger some nasty bugs.
2346 */
2347 BUG_ON(current_cpu_type() != c->cputype);
2348
2349 if (cpu_has_rixi) {
2350 /* Enable the RIXI exceptions */
2351 set_c0_pagegrain(PG_IEC);
2352 back_to_back_c0_hazard();
2353 /* Verify the IEC bit is set */
2354 if (read_c0_pagegrain() & PG_IEC)
2355 c->options |= MIPS_CPU_RIXIEX;
2356 }
2357
2358 if (mips_fpu_disabled)
2359 c->options &= ~MIPS_CPU_FPU;
2360
2361 if (mips_dsp_disabled)
2362 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2363
2364 if (mips_htw_disabled) {
2365 c->options &= ~MIPS_CPU_HTW;
2366 write_c0_pwctl(read_c0_pwctl() &
2367 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2368 }
2369
2370 if (c->options & MIPS_CPU_FPU)
2371 cpu_set_fpu_opts(c);
2372 else
2373 cpu_set_nofpu_opts(c);
2374
2375 if (cpu_has_bp_ghist)
2376 write_c0_r10k_diag(read_c0_r10k_diag() |
2377 R10K_DIAG_E_GHIST);
2378
2379 if (cpu_has_mips_r2_r6) {
2380 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2381 /* R2 has Performance Counter Interrupt indicator */
2382 c->options |= MIPS_CPU_PCI;
2383 }
2384 else
2385 c->srsets = 1;
2386
2387 if (cpu_has_mips_r6)
2388 elf_hwcap |= HWCAP_MIPS_R6;
2389
2390 if (cpu_has_msa) {
2391 c->msa_id = cpu_get_msa_id();
2392 WARN(c->msa_id & MSA_IR_WRPF,
2393 "Vector register partitioning unimplemented!");
2394 elf_hwcap |= HWCAP_MIPS_MSA;
2395 }
2396
2397 if (cpu_has_mips16)
2398 elf_hwcap |= HWCAP_MIPS_MIPS16;
2399
2400 if (cpu_has_mdmx)
2401 elf_hwcap |= HWCAP_MIPS_MDMX;
2402
2403 if (cpu_has_mips3d)
2404 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2405
2406 if (cpu_has_smartmips)
2407 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2408
2409 if (cpu_has_dsp)
2410 elf_hwcap |= HWCAP_MIPS_DSP;
2411
2412 if (cpu_has_dsp2)
2413 elf_hwcap |= HWCAP_MIPS_DSP2;
2414
2415 if (cpu_has_dsp3)
2416 elf_hwcap |= HWCAP_MIPS_DSP3;
2417
2418 if (cpu_has_mips16e2)
2419 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2420
2421 if (cpu_has_loongson_mmi)
2422 elf_hwcap |= HWCAP_LOONGSON_MMI;
2423
2424 if (cpu_has_loongson_ext)
2425 elf_hwcap |= HWCAP_LOONGSON_EXT;
2426
2427 if (cpu_has_loongson_ext2)
2428 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2429
2430 if (cpu_has_vz)
2431 cpu_probe_vz(c);
2432
2433 cpu_probe_vmbits(c);
2434
2435 /* Synthesize CPUCFG data if running on Loongson processors;
2436 * no-op otherwise.
2437 *
2438 * This looks at previously probed features, so keep this at bottom.
2439 */
2440 loongson3_cpucfg_synthesize_data(c);
2441
2442#ifdef CONFIG_64BIT
2443 if (cpu == 0)
2444 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2445#endif
2446}
2447
2448void cpu_report(void)
2449{
2450 struct cpuinfo_mips *c = ¤t_cpu_data;
2451
2452 pr_info("CPU%d revision is: %08x (%s)\n",
2453 smp_processor_id(), c->processor_id, cpu_name_string());
2454 if (c->options & MIPS_CPU_FPU)
2455 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2456 if (cpu_has_msa)
2457 pr_info("MSA revision is: %08x\n", c->msa_id);
2458}
2459
2460void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2461{
2462 /* Ensure the core number fits in the field */
2463 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2464 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2465
2466 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2467 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2468}
2469
2470void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2471{
2472 /* Ensure the core number fits in the field */
2473 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2474
2475 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2476 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2477}
2478
2479void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2480{
2481 /* Ensure the VP(E) ID fits in the field */
2482 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2483
2484 /* Ensure we're not using VP(E)s without support */
2485 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2486 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2487
2488 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2489 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2490}