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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)
9 */
10
11#if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/clk.h>
16#include <linux/console.h>
17#include <linux/delay.h>
18#include <linux/dma-direction.h>
19#include <linux/dmaengine.h>
20#include <linux/dma-mapping.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/irq.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/pm_wakeirq.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33#include <linux/spinlock.h>
34#include <linux/sysrq.h>
35#include <linux/tty_flip.h>
36#include <linux/tty.h>
37
38#include "stm32-usart.h"
39
40static void stm32_stop_tx(struct uart_port *port);
41static void stm32_transmit_chars(struct uart_port *port);
42
43static inline struct stm32_port *to_stm32_port(struct uart_port *port)
44{
45 return container_of(port, struct stm32_port, port);
46}
47
48static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
49{
50 u32 val;
51
52 val = readl_relaxed(port->membase + reg);
53 val |= bits;
54 writel_relaxed(val, port->membase + reg);
55}
56
57static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
58{
59 u32 val;
60
61 val = readl_relaxed(port->membase + reg);
62 val &= ~bits;
63 writel_relaxed(val, port->membase + reg);
64}
65
66static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
67 u32 delay_DDE, u32 baud)
68{
69 u32 rs485_deat_dedt;
70 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
71 bool over8;
72
73 *cr3 |= USART_CR3_DEM;
74 over8 = *cr1 & USART_CR1_OVER8;
75
76 if (over8)
77 rs485_deat_dedt = delay_ADE * baud * 8;
78 else
79 rs485_deat_dedt = delay_ADE * baud * 16;
80
81 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
82 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
83 rs485_deat_dedt_max : rs485_deat_dedt;
84 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
85 USART_CR1_DEAT_MASK;
86 *cr1 |= rs485_deat_dedt;
87
88 if (over8)
89 rs485_deat_dedt = delay_DDE * baud * 8;
90 else
91 rs485_deat_dedt = delay_DDE * baud * 16;
92
93 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
94 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
95 rs485_deat_dedt_max : rs485_deat_dedt;
96 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
97 USART_CR1_DEDT_MASK;
98 *cr1 |= rs485_deat_dedt;
99}
100
101static int stm32_config_rs485(struct uart_port *port,
102 struct serial_rs485 *rs485conf)
103{
104 struct stm32_port *stm32_port = to_stm32_port(port);
105 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
106 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
107 u32 usartdiv, baud, cr1, cr3;
108 bool over8;
109
110 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
111
112 port->rs485 = *rs485conf;
113
114 rs485conf->flags |= SER_RS485_RX_DURING_TX;
115
116 if (rs485conf->flags & SER_RS485_ENABLED) {
117 cr1 = readl_relaxed(port->membase + ofs->cr1);
118 cr3 = readl_relaxed(port->membase + ofs->cr3);
119 usartdiv = readl_relaxed(port->membase + ofs->brr);
120 usartdiv = usartdiv & GENMASK(15, 0);
121 over8 = cr1 & USART_CR1_OVER8;
122
123 if (over8)
124 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
125 << USART_BRR_04_R_SHIFT;
126
127 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
128 stm32_config_reg_rs485(&cr1, &cr3,
129 rs485conf->delay_rts_before_send,
130 rs485conf->delay_rts_after_send, baud);
131
132 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
133 cr3 &= ~USART_CR3_DEP;
134 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
135 } else {
136 cr3 |= USART_CR3_DEP;
137 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
138 }
139
140 writel_relaxed(cr3, port->membase + ofs->cr3);
141 writel_relaxed(cr1, port->membase + ofs->cr1);
142 } else {
143 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
144 stm32_clr_bits(port, ofs->cr1,
145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
146 }
147
148 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
149
150 return 0;
151}
152
153static int stm32_init_rs485(struct uart_port *port,
154 struct platform_device *pdev)
155{
156 struct serial_rs485 *rs485conf = &port->rs485;
157
158 rs485conf->flags = 0;
159 rs485conf->delay_rts_before_send = 0;
160 rs485conf->delay_rts_after_send = 0;
161
162 if (!pdev->dev.of_node)
163 return -ENODEV;
164
165 uart_get_rs485_mode(&pdev->dev, rs485conf);
166
167 return 0;
168}
169
170static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
171 bool threaded)
172{
173 struct stm32_port *stm32_port = to_stm32_port(port);
174 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
175 enum dma_status status;
176 struct dma_tx_state state;
177
178 *sr = readl_relaxed(port->membase + ofs->isr);
179
180 if (threaded && stm32_port->rx_ch) {
181 status = dmaengine_tx_status(stm32_port->rx_ch,
182 stm32_port->rx_ch->cookie,
183 &state);
184 if ((status == DMA_IN_PROGRESS) &&
185 (*last_res != state.residue))
186 return 1;
187 else
188 return 0;
189 } else if (*sr & USART_SR_RXNE) {
190 return 1;
191 }
192 return 0;
193}
194
195static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
196 int *last_res)
197{
198 struct stm32_port *stm32_port = to_stm32_port(port);
199 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
200 unsigned long c;
201
202 if (stm32_port->rx_ch) {
203 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
204 if ((*last_res) == 0)
205 *last_res = RX_BUF_L;
206 } else {
207 c = readl_relaxed(port->membase + ofs->rdr);
208 /* apply RDR data mask */
209 c &= stm32_port->rdr_mask;
210 }
211
212 return c;
213}
214
215static void stm32_receive_chars(struct uart_port *port, bool threaded)
216{
217 struct tty_port *tport = &port->state->port;
218 struct stm32_port *stm32_port = to_stm32_port(port);
219 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
220 unsigned long c;
221 u32 sr;
222 char flag;
223
224 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
225 pm_wakeup_event(tport->tty->dev, 0);
226
227 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
228 sr |= USART_SR_DUMMY_RX;
229 flag = TTY_NORMAL;
230
231 /*
232 * Status bits has to be cleared before reading the RDR:
233 * In FIFO mode, reading the RDR will pop the next data
234 * (if any) along with its status bits into the SR.
235 * Not doing so leads to misalignement between RDR and SR,
236 * and clear status bits of the next rx data.
237 *
238 * Clear errors flags for stm32f7 and stm32h7 compatible
239 * devices. On stm32f4 compatible devices, the error bit is
240 * cleared by the sequence [read SR - read DR].
241 */
242 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
243 stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF |
244 USART_ICR_PECF | USART_ICR_FECF);
245
246 c = stm32_get_char(port, &sr, &stm32_port->last_res);
247 port->icount.rx++;
248 if (sr & USART_SR_ERR_MASK) {
249 if (sr & USART_SR_ORE) {
250 port->icount.overrun++;
251 } else if (sr & USART_SR_PE) {
252 port->icount.parity++;
253 } else if (sr & USART_SR_FE) {
254 /* Break detection if character is null */
255 if (!c) {
256 port->icount.brk++;
257 if (uart_handle_break(port))
258 continue;
259 } else {
260 port->icount.frame++;
261 }
262 }
263
264 sr &= port->read_status_mask;
265
266 if (sr & USART_SR_PE) {
267 flag = TTY_PARITY;
268 } else if (sr & USART_SR_FE) {
269 if (!c)
270 flag = TTY_BREAK;
271 else
272 flag = TTY_FRAME;
273 }
274 }
275
276 if (uart_handle_sysrq_char(port, c))
277 continue;
278 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
279 }
280
281 spin_unlock(&port->lock);
282 tty_flip_buffer_push(tport);
283 spin_lock(&port->lock);
284}
285
286static void stm32_tx_dma_complete(void *arg)
287{
288 struct uart_port *port = arg;
289 struct stm32_port *stm32port = to_stm32_port(port);
290 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
291
292 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
293 stm32port->tx_dma_busy = false;
294
295 /* Let's see if we have pending data to send */
296 stm32_transmit_chars(port);
297}
298
299static void stm32_tx_interrupt_enable(struct uart_port *port)
300{
301 struct stm32_port *stm32_port = to_stm32_port(port);
302 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
303
304 /*
305 * Enables TX FIFO threashold irq when FIFO is enabled,
306 * or TX empty irq when FIFO is disabled
307 */
308 if (stm32_port->fifoen)
309 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
310 else
311 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
312}
313
314static void stm32_tx_interrupt_disable(struct uart_port *port)
315{
316 struct stm32_port *stm32_port = to_stm32_port(port);
317 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
318
319 if (stm32_port->fifoen)
320 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
321 else
322 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
323}
324
325static void stm32_transmit_chars_pio(struct uart_port *port)
326{
327 struct stm32_port *stm32_port = to_stm32_port(port);
328 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
329 struct circ_buf *xmit = &port->state->xmit;
330
331 if (stm32_port->tx_dma_busy) {
332 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
333 stm32_port->tx_dma_busy = false;
334 }
335
336 while (!uart_circ_empty(xmit)) {
337 /* Check that TDR is empty before filling FIFO */
338 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
339 break;
340 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
342 port->icount.tx++;
343 }
344
345 /* rely on TXE irq (mask or unmask) for sending remaining data */
346 if (uart_circ_empty(xmit))
347 stm32_tx_interrupt_disable(port);
348 else
349 stm32_tx_interrupt_enable(port);
350}
351
352static void stm32_transmit_chars_dma(struct uart_port *port)
353{
354 struct stm32_port *stm32port = to_stm32_port(port);
355 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
356 struct circ_buf *xmit = &port->state->xmit;
357 struct dma_async_tx_descriptor *desc = NULL;
358 dma_cookie_t cookie;
359 unsigned int count, i;
360
361 if (stm32port->tx_dma_busy)
362 return;
363
364 stm32port->tx_dma_busy = true;
365
366 count = uart_circ_chars_pending(xmit);
367
368 if (count > TX_BUF_L)
369 count = TX_BUF_L;
370
371 if (xmit->tail < xmit->head) {
372 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
373 } else {
374 size_t one = UART_XMIT_SIZE - xmit->tail;
375 size_t two;
376
377 if (one > count)
378 one = count;
379 two = count - one;
380
381 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
382 if (two)
383 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
384 }
385
386 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
387 stm32port->tx_dma_buf,
388 count,
389 DMA_MEM_TO_DEV,
390 DMA_PREP_INTERRUPT);
391
392 if (!desc) {
393 for (i = count; i > 0; i--)
394 stm32_transmit_chars_pio(port);
395 return;
396 }
397
398 desc->callback = stm32_tx_dma_complete;
399 desc->callback_param = port;
400
401 /* Push current DMA TX transaction in the pending queue */
402 cookie = dmaengine_submit(desc);
403
404 /* Issue pending DMA TX requests */
405 dma_async_issue_pending(stm32port->tx_ch);
406
407 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
408
409 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
410 port->icount.tx += count;
411}
412
413static void stm32_transmit_chars(struct uart_port *port)
414{
415 struct stm32_port *stm32_port = to_stm32_port(port);
416 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
417 struct circ_buf *xmit = &port->state->xmit;
418
419 if (port->x_char) {
420 if (stm32_port->tx_dma_busy)
421 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
422 writel_relaxed(port->x_char, port->membase + ofs->tdr);
423 port->x_char = 0;
424 port->icount.tx++;
425 if (stm32_port->tx_dma_busy)
426 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
427 return;
428 }
429
430 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
431 stm32_tx_interrupt_disable(port);
432 return;
433 }
434
435 if (ofs->icr == UNDEF_REG)
436 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
437 else
438 stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
439
440 if (stm32_port->tx_ch)
441 stm32_transmit_chars_dma(port);
442 else
443 stm32_transmit_chars_pio(port);
444
445 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
446 uart_write_wakeup(port);
447
448 if (uart_circ_empty(xmit))
449 stm32_tx_interrupt_disable(port);
450}
451
452static irqreturn_t stm32_interrupt(int irq, void *ptr)
453{
454 struct uart_port *port = ptr;
455 struct stm32_port *stm32_port = to_stm32_port(port);
456 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
457 u32 sr;
458
459 spin_lock(&port->lock);
460
461 sr = readl_relaxed(port->membase + ofs->isr);
462
463 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
464 writel_relaxed(USART_ICR_RTOCF,
465 port->membase + ofs->icr);
466
467 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
468 writel_relaxed(USART_ICR_WUCF,
469 port->membase + ofs->icr);
470
471 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
472 stm32_receive_chars(port, false);
473
474 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
475 stm32_transmit_chars(port);
476
477 spin_unlock(&port->lock);
478
479 if (stm32_port->rx_ch)
480 return IRQ_WAKE_THREAD;
481 else
482 return IRQ_HANDLED;
483}
484
485static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
486{
487 struct uart_port *port = ptr;
488 struct stm32_port *stm32_port = to_stm32_port(port);
489
490 spin_lock(&port->lock);
491
492 if (stm32_port->rx_ch)
493 stm32_receive_chars(port, true);
494
495 spin_unlock(&port->lock);
496
497 return IRQ_HANDLED;
498}
499
500static unsigned int stm32_tx_empty(struct uart_port *port)
501{
502 struct stm32_port *stm32_port = to_stm32_port(port);
503 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
504
505 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
506}
507
508static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
509{
510 struct stm32_port *stm32_port = to_stm32_port(port);
511 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
512
513 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
514 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
515 else
516 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
517}
518
519static unsigned int stm32_get_mctrl(struct uart_port *port)
520{
521 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
522 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
523}
524
525/* Transmit stop */
526static void stm32_stop_tx(struct uart_port *port)
527{
528 stm32_tx_interrupt_disable(port);
529}
530
531/* There are probably characters waiting to be transmitted. */
532static void stm32_start_tx(struct uart_port *port)
533{
534 struct circ_buf *xmit = &port->state->xmit;
535
536 if (uart_circ_empty(xmit))
537 return;
538
539 stm32_transmit_chars(port);
540}
541
542/* Throttle the remote when input buffer is about to overflow. */
543static void stm32_throttle(struct uart_port *port)
544{
545 struct stm32_port *stm32_port = to_stm32_port(port);
546 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
547 unsigned long flags;
548
549 spin_lock_irqsave(&port->lock, flags);
550 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
551 if (stm32_port->cr3_irq)
552 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
553
554 spin_unlock_irqrestore(&port->lock, flags);
555}
556
557/* Unthrottle the remote, the input buffer can now accept data. */
558static void stm32_unthrottle(struct uart_port *port)
559{
560 struct stm32_port *stm32_port = to_stm32_port(port);
561 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
562 unsigned long flags;
563
564 spin_lock_irqsave(&port->lock, flags);
565 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
566 if (stm32_port->cr3_irq)
567 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
568
569 spin_unlock_irqrestore(&port->lock, flags);
570}
571
572/* Receive stop */
573static void stm32_stop_rx(struct uart_port *port)
574{
575 struct stm32_port *stm32_port = to_stm32_port(port);
576 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
577
578 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
579 if (stm32_port->cr3_irq)
580 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
581
582}
583
584/* Handle breaks - ignored by us */
585static void stm32_break_ctl(struct uart_port *port, int break_state)
586{
587}
588
589static int stm32_startup(struct uart_port *port)
590{
591 struct stm32_port *stm32_port = to_stm32_port(port);
592 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
593 const char *name = to_platform_device(port->dev)->name;
594 u32 val;
595 int ret;
596
597 ret = request_threaded_irq(port->irq, stm32_interrupt,
598 stm32_threaded_interrupt,
599 IRQF_NO_SUSPEND, name, port);
600 if (ret)
601 return ret;
602
603 /* RX FIFO Flush */
604 if (ofs->rqr != UNDEF_REG)
605 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
606
607 /* Tx and RX FIFO configuration */
608 if (stm32_port->fifoen) {
609 val = readl_relaxed(port->membase + ofs->cr3);
610 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
611 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
612 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
613 writel_relaxed(val, port->membase + ofs->cr3);
614 }
615
616 /* RX FIFO enabling */
617 val = stm32_port->cr1_irq | USART_CR1_RE;
618 if (stm32_port->fifoen)
619 val |= USART_CR1_FIFOEN;
620 stm32_set_bits(port, ofs->cr1, val);
621
622 return 0;
623}
624
625static void stm32_shutdown(struct uart_port *port)
626{
627 struct stm32_port *stm32_port = to_stm32_port(port);
628 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
629 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
630 u32 val, isr;
631 int ret;
632
633 val = USART_CR1_TXEIE | USART_CR1_TE;
634 val |= stm32_port->cr1_irq | USART_CR1_RE;
635 val |= BIT(cfg->uart_enable_bit);
636 if (stm32_port->fifoen)
637 val |= USART_CR1_FIFOEN;
638
639 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
640 isr, (isr & USART_SR_TC),
641 10, 100000);
642
643 if (ret)
644 dev_err(port->dev, "transmission complete not set\n");
645
646 stm32_clr_bits(port, ofs->cr1, val);
647
648 free_irq(port->irq, port);
649}
650
651static unsigned int stm32_get_databits(struct ktermios *termios)
652{
653 unsigned int bits;
654
655 tcflag_t cflag = termios->c_cflag;
656
657 switch (cflag & CSIZE) {
658 /*
659 * CSIZE settings are not necessarily supported in hardware.
660 * CSIZE unsupported configurations are handled here to set word length
661 * to 8 bits word as default configuration and to print debug message.
662 */
663 case CS5:
664 bits = 5;
665 break;
666 case CS6:
667 bits = 6;
668 break;
669 case CS7:
670 bits = 7;
671 break;
672 /* default including CS8 */
673 default:
674 bits = 8;
675 break;
676 }
677
678 return bits;
679}
680
681static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
682 struct ktermios *old)
683{
684 struct stm32_port *stm32_port = to_stm32_port(port);
685 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
686 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
687 struct serial_rs485 *rs485conf = &port->rs485;
688 unsigned int baud, bits;
689 u32 usartdiv, mantissa, fraction, oversampling;
690 tcflag_t cflag = termios->c_cflag;
691 u32 cr1, cr2, cr3;
692 unsigned long flags;
693
694 if (!stm32_port->hw_flow_control)
695 cflag &= ~CRTSCTS;
696
697 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
698
699 spin_lock_irqsave(&port->lock, flags);
700
701 /* Stop serial port and reset value */
702 writel_relaxed(0, port->membase + ofs->cr1);
703
704 /* flush RX & TX FIFO */
705 if (ofs->rqr != UNDEF_REG)
706 stm32_set_bits(port, ofs->rqr,
707 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
708
709 cr1 = USART_CR1_TE | USART_CR1_RE;
710 if (stm32_port->fifoen)
711 cr1 |= USART_CR1_FIFOEN;
712 cr2 = 0;
713 cr3 = readl_relaxed(port->membase + ofs->cr3);
714 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
715 | USART_CR3_TXFTCFG_MASK;
716
717 if (cflag & CSTOPB)
718 cr2 |= USART_CR2_STOP_2B;
719
720 bits = stm32_get_databits(termios);
721 stm32_port->rdr_mask = (BIT(bits) - 1);
722
723 if (cflag & PARENB) {
724 bits++;
725 cr1 |= USART_CR1_PCE;
726 }
727
728 /*
729 * Word length configuration:
730 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
731 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
732 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
733 * M0 and M1 already cleared by cr1 initialization.
734 */
735 if (bits == 9)
736 cr1 |= USART_CR1_M0;
737 else if ((bits == 7) && cfg->has_7bits_data)
738 cr1 |= USART_CR1_M1;
739 else if (bits != 8)
740 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
741 , bits);
742
743 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
744 stm32_port->fifoen)) {
745 if (cflag & CSTOPB)
746 bits = bits + 3; /* 1 start bit + 2 stop bits */
747 else
748 bits = bits + 2; /* 1 start bit + 1 stop bit */
749
750 /* RX timeout irq to occur after last stop bit + bits */
751 stm32_port->cr1_irq = USART_CR1_RTOIE;
752 writel_relaxed(bits, port->membase + ofs->rtor);
753 cr2 |= USART_CR2_RTOEN;
754 /* Not using dma, enable fifo threshold irq */
755 if (!stm32_port->rx_ch)
756 stm32_port->cr3_irq = USART_CR3_RXFTIE;
757 }
758
759 cr1 |= stm32_port->cr1_irq;
760 cr3 |= stm32_port->cr3_irq;
761
762 if (cflag & PARODD)
763 cr1 |= USART_CR1_PS;
764
765 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
766 if (cflag & CRTSCTS) {
767 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
768 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
769 }
770
771 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
772
773 /*
774 * The USART supports 16 or 8 times oversampling.
775 * By default we prefer 16 times oversampling, so that the receiver
776 * has a better tolerance to clock deviations.
777 * 8 times oversampling is only used to achieve higher speeds.
778 */
779 if (usartdiv < 16) {
780 oversampling = 8;
781 cr1 |= USART_CR1_OVER8;
782 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
783 } else {
784 oversampling = 16;
785 cr1 &= ~USART_CR1_OVER8;
786 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
787 }
788
789 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
790 fraction = usartdiv % oversampling;
791 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
792
793 uart_update_timeout(port, cflag, baud);
794
795 port->read_status_mask = USART_SR_ORE;
796 if (termios->c_iflag & INPCK)
797 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
798 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
799 port->read_status_mask |= USART_SR_FE;
800
801 /* Characters to ignore */
802 port->ignore_status_mask = 0;
803 if (termios->c_iflag & IGNPAR)
804 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
805 if (termios->c_iflag & IGNBRK) {
806 port->ignore_status_mask |= USART_SR_FE;
807 /*
808 * If we're ignoring parity and break indicators,
809 * ignore overruns too (for real raw support).
810 */
811 if (termios->c_iflag & IGNPAR)
812 port->ignore_status_mask |= USART_SR_ORE;
813 }
814
815 /* Ignore all characters if CREAD is not set */
816 if ((termios->c_cflag & CREAD) == 0)
817 port->ignore_status_mask |= USART_SR_DUMMY_RX;
818
819 if (stm32_port->rx_ch)
820 cr3 |= USART_CR3_DMAR;
821
822 if (rs485conf->flags & SER_RS485_ENABLED) {
823 stm32_config_reg_rs485(&cr1, &cr3,
824 rs485conf->delay_rts_before_send,
825 rs485conf->delay_rts_after_send, baud);
826 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
827 cr3 &= ~USART_CR3_DEP;
828 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
829 } else {
830 cr3 |= USART_CR3_DEP;
831 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
832 }
833
834 } else {
835 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
836 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
837 }
838
839 writel_relaxed(cr3, port->membase + ofs->cr3);
840 writel_relaxed(cr2, port->membase + ofs->cr2);
841 writel_relaxed(cr1, port->membase + ofs->cr1);
842
843 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
844 spin_unlock_irqrestore(&port->lock, flags);
845}
846
847static const char *stm32_type(struct uart_port *port)
848{
849 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
850}
851
852static void stm32_release_port(struct uart_port *port)
853{
854}
855
856static int stm32_request_port(struct uart_port *port)
857{
858 return 0;
859}
860
861static void stm32_config_port(struct uart_port *port, int flags)
862{
863 if (flags & UART_CONFIG_TYPE)
864 port->type = PORT_STM32;
865}
866
867static int
868stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
869{
870 /* No user changeable parameters */
871 return -EINVAL;
872}
873
874static void stm32_pm(struct uart_port *port, unsigned int state,
875 unsigned int oldstate)
876{
877 struct stm32_port *stm32port = container_of(port,
878 struct stm32_port, port);
879 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
880 struct stm32_usart_config *cfg = &stm32port->info->cfg;
881 unsigned long flags = 0;
882
883 switch (state) {
884 case UART_PM_STATE_ON:
885 pm_runtime_get_sync(port->dev);
886 break;
887 case UART_PM_STATE_OFF:
888 spin_lock_irqsave(&port->lock, flags);
889 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
890 spin_unlock_irqrestore(&port->lock, flags);
891 pm_runtime_put_sync(port->dev);
892 break;
893 }
894}
895
896static const struct uart_ops stm32_uart_ops = {
897 .tx_empty = stm32_tx_empty,
898 .set_mctrl = stm32_set_mctrl,
899 .get_mctrl = stm32_get_mctrl,
900 .stop_tx = stm32_stop_tx,
901 .start_tx = stm32_start_tx,
902 .throttle = stm32_throttle,
903 .unthrottle = stm32_unthrottle,
904 .stop_rx = stm32_stop_rx,
905 .break_ctl = stm32_break_ctl,
906 .startup = stm32_startup,
907 .shutdown = stm32_shutdown,
908 .set_termios = stm32_set_termios,
909 .pm = stm32_pm,
910 .type = stm32_type,
911 .release_port = stm32_release_port,
912 .request_port = stm32_request_port,
913 .config_port = stm32_config_port,
914 .verify_port = stm32_verify_port,
915};
916
917static int stm32_init_port(struct stm32_port *stm32port,
918 struct platform_device *pdev)
919{
920 struct uart_port *port = &stm32port->port;
921 struct resource *res;
922 int ret;
923
924 port->iotype = UPIO_MEM;
925 port->flags = UPF_BOOT_AUTOCONF;
926 port->ops = &stm32_uart_ops;
927 port->dev = &pdev->dev;
928 port->fifosize = stm32port->info->cfg.fifosize;
929
930 ret = platform_get_irq(pdev, 0);
931 if (ret <= 0)
932 return ret ? : -ENODEV;
933 port->irq = ret;
934
935 port->rs485_config = stm32_config_rs485;
936
937 stm32_init_rs485(port, pdev);
938
939 if (stm32port->info->cfg.has_wakeup) {
940 stm32port->wakeirq = platform_get_irq(pdev, 1);
941 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
942 return stm32port->wakeirq ? : -ENODEV;
943 }
944
945 stm32port->fifoen = stm32port->info->cfg.has_fifo;
946
947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 port->membase = devm_ioremap_resource(&pdev->dev, res);
949 if (IS_ERR(port->membase))
950 return PTR_ERR(port->membase);
951 port->mapbase = res->start;
952
953 spin_lock_init(&port->lock);
954
955 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
956 if (IS_ERR(stm32port->clk))
957 return PTR_ERR(stm32port->clk);
958
959 /* Ensure that clk rate is correct by enabling the clk */
960 ret = clk_prepare_enable(stm32port->clk);
961 if (ret)
962 return ret;
963
964 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
965 if (!stm32port->port.uartclk) {
966 clk_disable_unprepare(stm32port->clk);
967 ret = -EINVAL;
968 }
969
970 return ret;
971}
972
973static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
974{
975 struct device_node *np = pdev->dev.of_node;
976 int id;
977
978 if (!np)
979 return NULL;
980
981 id = of_alias_get_id(np, "serial");
982 if (id < 0) {
983 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
984 return NULL;
985 }
986
987 if (WARN_ON(id >= STM32_MAX_PORTS))
988 return NULL;
989
990 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
991 "st,hw-flow-ctrl");
992 stm32_ports[id].port.line = id;
993 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
994 stm32_ports[id].cr3_irq = 0;
995 stm32_ports[id].last_res = RX_BUF_L;
996 return &stm32_ports[id];
997}
998
999#ifdef CONFIG_OF
1000static const struct of_device_id stm32_match[] = {
1001 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1002 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1003 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1004 {},
1005};
1006
1007MODULE_DEVICE_TABLE(of, stm32_match);
1008#endif
1009
1010static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
1011 struct platform_device *pdev)
1012{
1013 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1014 struct uart_port *port = &stm32port->port;
1015 struct device *dev = &pdev->dev;
1016 struct dma_slave_config config;
1017 struct dma_async_tx_descriptor *desc = NULL;
1018 dma_cookie_t cookie;
1019 int ret;
1020
1021 /* Request DMA RX channel */
1022 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1023 if (!stm32port->rx_ch) {
1024 dev_info(dev, "rx dma alloc failed\n");
1025 return -ENODEV;
1026 }
1027 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1028 &stm32port->rx_dma_buf,
1029 GFP_KERNEL);
1030 if (!stm32port->rx_buf) {
1031 ret = -ENOMEM;
1032 goto alloc_err;
1033 }
1034
1035 /* Configure DMA channel */
1036 memset(&config, 0, sizeof(config));
1037 config.src_addr = port->mapbase + ofs->rdr;
1038 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1039
1040 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1041 if (ret < 0) {
1042 dev_err(dev, "rx dma channel config failed\n");
1043 ret = -ENODEV;
1044 goto config_err;
1045 }
1046
1047 /* Prepare a DMA cyclic transaction */
1048 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1049 stm32port->rx_dma_buf,
1050 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1051 DMA_PREP_INTERRUPT);
1052 if (!desc) {
1053 dev_err(dev, "rx dma prep cyclic failed\n");
1054 ret = -ENODEV;
1055 goto config_err;
1056 }
1057
1058 /* No callback as dma buffer is drained on usart interrupt */
1059 desc->callback = NULL;
1060 desc->callback_param = NULL;
1061
1062 /* Push current DMA transaction in the pending queue */
1063 cookie = dmaengine_submit(desc);
1064
1065 /* Issue pending DMA requests */
1066 dma_async_issue_pending(stm32port->rx_ch);
1067
1068 return 0;
1069
1070config_err:
1071 dma_free_coherent(&pdev->dev,
1072 RX_BUF_L, stm32port->rx_buf,
1073 stm32port->rx_dma_buf);
1074
1075alloc_err:
1076 dma_release_channel(stm32port->rx_ch);
1077 stm32port->rx_ch = NULL;
1078
1079 return ret;
1080}
1081
1082static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1083 struct platform_device *pdev)
1084{
1085 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1086 struct uart_port *port = &stm32port->port;
1087 struct device *dev = &pdev->dev;
1088 struct dma_slave_config config;
1089 int ret;
1090
1091 stm32port->tx_dma_busy = false;
1092
1093 /* Request DMA TX channel */
1094 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1095 if (!stm32port->tx_ch) {
1096 dev_info(dev, "tx dma alloc failed\n");
1097 return -ENODEV;
1098 }
1099 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1100 &stm32port->tx_dma_buf,
1101 GFP_KERNEL);
1102 if (!stm32port->tx_buf) {
1103 ret = -ENOMEM;
1104 goto alloc_err;
1105 }
1106
1107 /* Configure DMA channel */
1108 memset(&config, 0, sizeof(config));
1109 config.dst_addr = port->mapbase + ofs->tdr;
1110 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1111
1112 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1113 if (ret < 0) {
1114 dev_err(dev, "tx dma channel config failed\n");
1115 ret = -ENODEV;
1116 goto config_err;
1117 }
1118
1119 return 0;
1120
1121config_err:
1122 dma_free_coherent(&pdev->dev,
1123 TX_BUF_L, stm32port->tx_buf,
1124 stm32port->tx_dma_buf);
1125
1126alloc_err:
1127 dma_release_channel(stm32port->tx_ch);
1128 stm32port->tx_ch = NULL;
1129
1130 return ret;
1131}
1132
1133static int stm32_serial_probe(struct platform_device *pdev)
1134{
1135 const struct of_device_id *match;
1136 struct stm32_port *stm32port;
1137 int ret;
1138
1139 stm32port = stm32_of_get_stm32_port(pdev);
1140 if (!stm32port)
1141 return -ENODEV;
1142
1143 match = of_match_device(stm32_match, &pdev->dev);
1144 if (match && match->data)
1145 stm32port->info = (struct stm32_usart_info *)match->data;
1146 else
1147 return -EINVAL;
1148
1149 ret = stm32_init_port(stm32port, pdev);
1150 if (ret)
1151 return ret;
1152
1153 if (stm32port->wakeirq > 0) {
1154 ret = device_init_wakeup(&pdev->dev, true);
1155 if (ret)
1156 goto err_uninit;
1157
1158 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1159 stm32port->wakeirq);
1160 if (ret)
1161 goto err_nowup;
1162
1163 device_set_wakeup_enable(&pdev->dev, false);
1164 }
1165
1166 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1167 if (ret)
1168 goto err_wirq;
1169
1170 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1171 if (ret)
1172 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1173
1174 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1175 if (ret)
1176 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1177
1178 platform_set_drvdata(pdev, &stm32port->port);
1179
1180 pm_runtime_get_noresume(&pdev->dev);
1181 pm_runtime_set_active(&pdev->dev);
1182 pm_runtime_enable(&pdev->dev);
1183 pm_runtime_put_sync(&pdev->dev);
1184
1185 return 0;
1186
1187err_wirq:
1188 if (stm32port->wakeirq > 0)
1189 dev_pm_clear_wake_irq(&pdev->dev);
1190
1191err_nowup:
1192 if (stm32port->wakeirq > 0)
1193 device_init_wakeup(&pdev->dev, false);
1194
1195err_uninit:
1196 clk_disable_unprepare(stm32port->clk);
1197
1198 return ret;
1199}
1200
1201static int stm32_serial_remove(struct platform_device *pdev)
1202{
1203 struct uart_port *port = platform_get_drvdata(pdev);
1204 struct stm32_port *stm32_port = to_stm32_port(port);
1205 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1206 int err;
1207
1208 pm_runtime_get_sync(&pdev->dev);
1209
1210 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1211
1212 if (stm32_port->rx_ch)
1213 dma_release_channel(stm32_port->rx_ch);
1214
1215 if (stm32_port->rx_dma_buf)
1216 dma_free_coherent(&pdev->dev,
1217 RX_BUF_L, stm32_port->rx_buf,
1218 stm32_port->rx_dma_buf);
1219
1220 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1221
1222 if (stm32_port->tx_ch)
1223 dma_release_channel(stm32_port->tx_ch);
1224
1225 if (stm32_port->tx_dma_buf)
1226 dma_free_coherent(&pdev->dev,
1227 TX_BUF_L, stm32_port->tx_buf,
1228 stm32_port->tx_dma_buf);
1229
1230 if (stm32_port->wakeirq > 0) {
1231 dev_pm_clear_wake_irq(&pdev->dev);
1232 device_init_wakeup(&pdev->dev, false);
1233 }
1234
1235 clk_disable_unprepare(stm32_port->clk);
1236
1237 err = uart_remove_one_port(&stm32_usart_driver, port);
1238
1239 pm_runtime_disable(&pdev->dev);
1240 pm_runtime_put_noidle(&pdev->dev);
1241
1242 return err;
1243}
1244
1245
1246#ifdef CONFIG_SERIAL_STM32_CONSOLE
1247static void stm32_console_putchar(struct uart_port *port, int ch)
1248{
1249 struct stm32_port *stm32_port = to_stm32_port(port);
1250 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1251
1252 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1253 cpu_relax();
1254
1255 writel_relaxed(ch, port->membase + ofs->tdr);
1256}
1257
1258static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1259{
1260 struct uart_port *port = &stm32_ports[co->index].port;
1261 struct stm32_port *stm32_port = to_stm32_port(port);
1262 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1263 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1264 unsigned long flags;
1265 u32 old_cr1, new_cr1;
1266 int locked = 1;
1267
1268 local_irq_save(flags);
1269 if (port->sysrq)
1270 locked = 0;
1271 else if (oops_in_progress)
1272 locked = spin_trylock(&port->lock);
1273 else
1274 spin_lock(&port->lock);
1275
1276 /* Save and disable interrupts, enable the transmitter */
1277 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1278 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1279 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1280 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1281
1282 uart_console_write(port, s, cnt, stm32_console_putchar);
1283
1284 /* Restore interrupt state */
1285 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1286
1287 if (locked)
1288 spin_unlock(&port->lock);
1289 local_irq_restore(flags);
1290}
1291
1292static int stm32_console_setup(struct console *co, char *options)
1293{
1294 struct stm32_port *stm32port;
1295 int baud = 9600;
1296 int bits = 8;
1297 int parity = 'n';
1298 int flow = 'n';
1299
1300 if (co->index >= STM32_MAX_PORTS)
1301 return -ENODEV;
1302
1303 stm32port = &stm32_ports[co->index];
1304
1305 /*
1306 * This driver does not support early console initialization
1307 * (use ARM early printk support instead), so we only expect
1308 * this to be called during the uart port registration when the
1309 * driver gets probed and the port should be mapped at that point.
1310 */
1311 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1312 return -ENXIO;
1313
1314 if (options)
1315 uart_parse_options(options, &baud, &parity, &bits, &flow);
1316
1317 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1318}
1319
1320static struct console stm32_console = {
1321 .name = STM32_SERIAL_NAME,
1322 .device = uart_console_device,
1323 .write = stm32_console_write,
1324 .setup = stm32_console_setup,
1325 .flags = CON_PRINTBUFFER,
1326 .index = -1,
1327 .data = &stm32_usart_driver,
1328};
1329
1330#define STM32_SERIAL_CONSOLE (&stm32_console)
1331
1332#else
1333#define STM32_SERIAL_CONSOLE NULL
1334#endif /* CONFIG_SERIAL_STM32_CONSOLE */
1335
1336static struct uart_driver stm32_usart_driver = {
1337 .driver_name = DRIVER_NAME,
1338 .dev_name = STM32_SERIAL_NAME,
1339 .major = 0,
1340 .minor = 0,
1341 .nr = STM32_MAX_PORTS,
1342 .cons = STM32_SERIAL_CONSOLE,
1343};
1344
1345static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port,
1346 bool enable)
1347{
1348 struct stm32_port *stm32_port = to_stm32_port(port);
1349 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1350 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1351 u32 val;
1352
1353 if (stm32_port->wakeirq <= 0)
1354 return;
1355
1356 if (enable) {
1357 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1358 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1359 val = readl_relaxed(port->membase + ofs->cr3);
1360 val &= ~USART_CR3_WUS_MASK;
1361 /* Enable Wake up interrupt from low power on start bit */
1362 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1363 writel_relaxed(val, port->membase + ofs->cr3);
1364 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1365 } else {
1366 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1367 }
1368}
1369
1370static int __maybe_unused stm32_serial_suspend(struct device *dev)
1371{
1372 struct uart_port *port = dev_get_drvdata(dev);
1373
1374 uart_suspend_port(&stm32_usart_driver, port);
1375
1376 if (device_may_wakeup(dev))
1377 stm32_serial_enable_wakeup(port, true);
1378 else
1379 stm32_serial_enable_wakeup(port, false);
1380
1381 pinctrl_pm_select_sleep_state(dev);
1382
1383 return 0;
1384}
1385
1386static int __maybe_unused stm32_serial_resume(struct device *dev)
1387{
1388 struct uart_port *port = dev_get_drvdata(dev);
1389
1390 pinctrl_pm_select_default_state(dev);
1391
1392 if (device_may_wakeup(dev))
1393 stm32_serial_enable_wakeup(port, false);
1394
1395 return uart_resume_port(&stm32_usart_driver, port);
1396}
1397
1398static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev)
1399{
1400 struct uart_port *port = dev_get_drvdata(dev);
1401 struct stm32_port *stm32port = container_of(port,
1402 struct stm32_port, port);
1403
1404 clk_disable_unprepare(stm32port->clk);
1405
1406 return 0;
1407}
1408
1409static int __maybe_unused stm32_serial_runtime_resume(struct device *dev)
1410{
1411 struct uart_port *port = dev_get_drvdata(dev);
1412 struct stm32_port *stm32port = container_of(port,
1413 struct stm32_port, port);
1414
1415 return clk_prepare_enable(stm32port->clk);
1416}
1417
1418static const struct dev_pm_ops stm32_serial_pm_ops = {
1419 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend,
1420 stm32_serial_runtime_resume, NULL)
1421 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1422};
1423
1424static struct platform_driver stm32_serial_driver = {
1425 .probe = stm32_serial_probe,
1426 .remove = stm32_serial_remove,
1427 .driver = {
1428 .name = DRIVER_NAME,
1429 .pm = &stm32_serial_pm_ops,
1430 .of_match_table = of_match_ptr(stm32_match),
1431 },
1432};
1433
1434static int __init usart_init(void)
1435{
1436 static char banner[] __initdata = "STM32 USART driver initialized";
1437 int ret;
1438
1439 pr_info("%s\n", banner);
1440
1441 ret = uart_register_driver(&stm32_usart_driver);
1442 if (ret)
1443 return ret;
1444
1445 ret = platform_driver_register(&stm32_serial_driver);
1446 if (ret)
1447 uart_unregister_driver(&stm32_usart_driver);
1448
1449 return ret;
1450}
1451
1452static void __exit usart_exit(void)
1453{
1454 platform_driver_unregister(&stm32_serial_driver);
1455 uart_unregister_driver(&stm32_usart_driver);
1456}
1457
1458module_init(usart_init);
1459module_exit(usart_exit);
1460
1461MODULE_ALIAS("platform:" DRIVER_NAME);
1462MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1463MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@foss.st.com>
7 * Erwan Le Ray <erwan.leray@foss.st.com>
8 *
9 * Inspired by st-asc.c from STMicroelectronics (c)
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/dma-direction.h>
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/pm_wakeirq.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/spinlock.h>
31#include <linux/sysrq.h>
32#include <linux/tty_flip.h>
33#include <linux/tty.h>
34
35#include "serial_mctrl_gpio.h"
36#include "stm32-usart.h"
37
38static void stm32_usart_stop_tx(struct uart_port *port);
39static void stm32_usart_transmit_chars(struct uart_port *port);
40
41static inline struct stm32_port *to_stm32_port(struct uart_port *port)
42{
43 return container_of(port, struct stm32_port, port);
44}
45
46static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
47{
48 u32 val;
49
50 val = readl_relaxed(port->membase + reg);
51 val |= bits;
52 writel_relaxed(val, port->membase + reg);
53}
54
55static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
56{
57 u32 val;
58
59 val = readl_relaxed(port->membase + reg);
60 val &= ~bits;
61 writel_relaxed(val, port->membase + reg);
62}
63
64static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
65 u32 delay_DDE, u32 baud)
66{
67 u32 rs485_deat_dedt;
68 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
69 bool over8;
70
71 *cr3 |= USART_CR3_DEM;
72 over8 = *cr1 & USART_CR1_OVER8;
73
74 if (over8)
75 rs485_deat_dedt = delay_ADE * baud * 8;
76 else
77 rs485_deat_dedt = delay_ADE * baud * 16;
78
79 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
80 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
81 rs485_deat_dedt_max : rs485_deat_dedt;
82 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
83 USART_CR1_DEAT_MASK;
84 *cr1 |= rs485_deat_dedt;
85
86 if (over8)
87 rs485_deat_dedt = delay_DDE * baud * 8;
88 else
89 rs485_deat_dedt = delay_DDE * baud * 16;
90
91 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
92 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
93 rs485_deat_dedt_max : rs485_deat_dedt;
94 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
95 USART_CR1_DEDT_MASK;
96 *cr1 |= rs485_deat_dedt;
97}
98
99static int stm32_usart_config_rs485(struct uart_port *port,
100 struct serial_rs485 *rs485conf)
101{
102 struct stm32_port *stm32_port = to_stm32_port(port);
103 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
104 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
105 u32 usartdiv, baud, cr1, cr3;
106 bool over8;
107
108 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
109
110 port->rs485 = *rs485conf;
111
112 rs485conf->flags |= SER_RS485_RX_DURING_TX;
113
114 if (rs485conf->flags & SER_RS485_ENABLED) {
115 cr1 = readl_relaxed(port->membase + ofs->cr1);
116 cr3 = readl_relaxed(port->membase + ofs->cr3);
117 usartdiv = readl_relaxed(port->membase + ofs->brr);
118 usartdiv = usartdiv & GENMASK(15, 0);
119 over8 = cr1 & USART_CR1_OVER8;
120
121 if (over8)
122 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
123 << USART_BRR_04_R_SHIFT;
124
125 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
126 stm32_usart_config_reg_rs485(&cr1, &cr3,
127 rs485conf->delay_rts_before_send,
128 rs485conf->delay_rts_after_send,
129 baud);
130
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132 cr3 &= ~USART_CR3_DEP;
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
134 } else {
135 cr3 |= USART_CR3_DEP;
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137 }
138
139 writel_relaxed(cr3, port->membase + ofs->cr3);
140 writel_relaxed(cr1, port->membase + ofs->cr1);
141 } else {
142 stm32_usart_clr_bits(port, ofs->cr3,
143 USART_CR3_DEM | USART_CR3_DEP);
144 stm32_usart_clr_bits(port, ofs->cr1,
145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
146 }
147
148 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
149
150 return 0;
151}
152
153static int stm32_usart_init_rs485(struct uart_port *port,
154 struct platform_device *pdev)
155{
156 struct serial_rs485 *rs485conf = &port->rs485;
157
158 rs485conf->flags = 0;
159 rs485conf->delay_rts_before_send = 0;
160 rs485conf->delay_rts_after_send = 0;
161
162 if (!pdev->dev.of_node)
163 return -ENODEV;
164
165 return uart_get_rs485_mode(port);
166}
167
168static int stm32_usart_pending_rx(struct uart_port *port, u32 *sr,
169 int *last_res, bool threaded)
170{
171 struct stm32_port *stm32_port = to_stm32_port(port);
172 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
173 enum dma_status status;
174 struct dma_tx_state state;
175
176 *sr = readl_relaxed(port->membase + ofs->isr);
177
178 if (threaded && stm32_port->rx_ch) {
179 status = dmaengine_tx_status(stm32_port->rx_ch,
180 stm32_port->rx_ch->cookie,
181 &state);
182 if (status == DMA_IN_PROGRESS && (*last_res != state.residue))
183 return 1;
184 else
185 return 0;
186 } else if (*sr & USART_SR_RXNE) {
187 return 1;
188 }
189 return 0;
190}
191
192static unsigned long stm32_usart_get_char(struct uart_port *port, u32 *sr,
193 int *last_res)
194{
195 struct stm32_port *stm32_port = to_stm32_port(port);
196 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
197 unsigned long c;
198
199 if (stm32_port->rx_ch) {
200 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
201 if ((*last_res) == 0)
202 *last_res = RX_BUF_L;
203 } else {
204 c = readl_relaxed(port->membase + ofs->rdr);
205 /* apply RDR data mask */
206 c &= stm32_port->rdr_mask;
207 }
208
209 return c;
210}
211
212static void stm32_usart_receive_chars(struct uart_port *port, bool threaded)
213{
214 struct tty_port *tport = &port->state->port;
215 struct stm32_port *stm32_port = to_stm32_port(port);
216 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
217 unsigned long c;
218 u32 sr;
219 char flag;
220
221 spin_lock(&port->lock);
222
223 while (stm32_usart_pending_rx(port, &sr, &stm32_port->last_res,
224 threaded)) {
225 sr |= USART_SR_DUMMY_RX;
226 flag = TTY_NORMAL;
227
228 /*
229 * Status bits has to be cleared before reading the RDR:
230 * In FIFO mode, reading the RDR will pop the next data
231 * (if any) along with its status bits into the SR.
232 * Not doing so leads to misalignement between RDR and SR,
233 * and clear status bits of the next rx data.
234 *
235 * Clear errors flags for stm32f7 and stm32h7 compatible
236 * devices. On stm32f4 compatible devices, the error bit is
237 * cleared by the sequence [read SR - read DR].
238 */
239 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
240 writel_relaxed(sr & USART_SR_ERR_MASK,
241 port->membase + ofs->icr);
242
243 c = stm32_usart_get_char(port, &sr, &stm32_port->last_res);
244 port->icount.rx++;
245 if (sr & USART_SR_ERR_MASK) {
246 if (sr & USART_SR_ORE) {
247 port->icount.overrun++;
248 } else if (sr & USART_SR_PE) {
249 port->icount.parity++;
250 } else if (sr & USART_SR_FE) {
251 /* Break detection if character is null */
252 if (!c) {
253 port->icount.brk++;
254 if (uart_handle_break(port))
255 continue;
256 } else {
257 port->icount.frame++;
258 }
259 }
260
261 sr &= port->read_status_mask;
262
263 if (sr & USART_SR_PE) {
264 flag = TTY_PARITY;
265 } else if (sr & USART_SR_FE) {
266 if (!c)
267 flag = TTY_BREAK;
268 else
269 flag = TTY_FRAME;
270 }
271 }
272
273 if (uart_prepare_sysrq_char(port, c))
274 continue;
275 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
276 }
277
278 uart_unlock_and_check_sysrq(port);
279
280 tty_flip_buffer_push(tport);
281}
282
283static void stm32_usart_tx_dma_complete(void *arg)
284{
285 struct uart_port *port = arg;
286 struct stm32_port *stm32port = to_stm32_port(port);
287 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
288 unsigned long flags;
289
290 dmaengine_terminate_async(stm32port->tx_ch);
291 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292 stm32port->tx_dma_busy = false;
293
294 /* Let's see if we have pending data to send */
295 spin_lock_irqsave(&port->lock, flags);
296 stm32_usart_transmit_chars(port);
297 spin_unlock_irqrestore(&port->lock, flags);
298}
299
300static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
301{
302 struct stm32_port *stm32_port = to_stm32_port(port);
303 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
304
305 /*
306 * Enables TX FIFO threashold irq when FIFO is enabled,
307 * or TX empty irq when FIFO is disabled
308 */
309 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
310 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
311 else
312 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
313}
314
315static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
316{
317 struct stm32_port *stm32_port = to_stm32_port(port);
318 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
319
320 if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
321 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
322 else
323 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
324}
325
326static void stm32_usart_transmit_chars_pio(struct uart_port *port)
327{
328 struct stm32_port *stm32_port = to_stm32_port(port);
329 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
330 struct circ_buf *xmit = &port->state->xmit;
331
332 if (stm32_port->tx_dma_busy) {
333 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
334 stm32_port->tx_dma_busy = false;
335 }
336
337 while (!uart_circ_empty(xmit)) {
338 /* Check that TDR is empty before filling FIFO */
339 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
340 break;
341 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
343 port->icount.tx++;
344 }
345
346 /* rely on TXE irq (mask or unmask) for sending remaining data */
347 if (uart_circ_empty(xmit))
348 stm32_usart_tx_interrupt_disable(port);
349 else
350 stm32_usart_tx_interrupt_enable(port);
351}
352
353static void stm32_usart_transmit_chars_dma(struct uart_port *port)
354{
355 struct stm32_port *stm32port = to_stm32_port(port);
356 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
357 struct circ_buf *xmit = &port->state->xmit;
358 struct dma_async_tx_descriptor *desc = NULL;
359 unsigned int count, i;
360
361 if (stm32port->tx_dma_busy)
362 return;
363
364 stm32port->tx_dma_busy = true;
365
366 count = uart_circ_chars_pending(xmit);
367
368 if (count > TX_BUF_L)
369 count = TX_BUF_L;
370
371 if (xmit->tail < xmit->head) {
372 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
373 } else {
374 size_t one = UART_XMIT_SIZE - xmit->tail;
375 size_t two;
376
377 if (one > count)
378 one = count;
379 two = count - one;
380
381 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
382 if (two)
383 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
384 }
385
386 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
387 stm32port->tx_dma_buf,
388 count,
389 DMA_MEM_TO_DEV,
390 DMA_PREP_INTERRUPT);
391
392 if (!desc)
393 goto fallback_err;
394
395 desc->callback = stm32_usart_tx_dma_complete;
396 desc->callback_param = port;
397
398 /* Push current DMA TX transaction in the pending queue */
399 if (dma_submit_error(dmaengine_submit(desc))) {
400 /* dma no yet started, safe to free resources */
401 dmaengine_terminate_async(stm32port->tx_ch);
402 goto fallback_err;
403 }
404
405 /* Issue pending DMA TX requests */
406 dma_async_issue_pending(stm32port->tx_ch);
407
408 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
409
410 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
411 port->icount.tx += count;
412 return;
413
414fallback_err:
415 for (i = count; i > 0; i--)
416 stm32_usart_transmit_chars_pio(port);
417}
418
419static void stm32_usart_transmit_chars(struct uart_port *port)
420{
421 struct stm32_port *stm32_port = to_stm32_port(port);
422 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
423 struct circ_buf *xmit = &port->state->xmit;
424
425 if (port->x_char) {
426 if (stm32_port->tx_dma_busy)
427 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
428 writel_relaxed(port->x_char, port->membase + ofs->tdr);
429 port->x_char = 0;
430 port->icount.tx++;
431 if (stm32_port->tx_dma_busy)
432 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
433 return;
434 }
435
436 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
437 stm32_usart_tx_interrupt_disable(port);
438 return;
439 }
440
441 if (ofs->icr == UNDEF_REG)
442 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
443 else
444 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
445
446 if (stm32_port->tx_ch)
447 stm32_usart_transmit_chars_dma(port);
448 else
449 stm32_usart_transmit_chars_pio(port);
450
451 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
452 uart_write_wakeup(port);
453
454 if (uart_circ_empty(xmit))
455 stm32_usart_tx_interrupt_disable(port);
456}
457
458static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
459{
460 struct uart_port *port = ptr;
461 struct tty_port *tport = &port->state->port;
462 struct stm32_port *stm32_port = to_stm32_port(port);
463 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
464 u32 sr;
465
466 sr = readl_relaxed(port->membase + ofs->isr);
467
468 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
469 writel_relaxed(USART_ICR_RTOCF,
470 port->membase + ofs->icr);
471
472 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
473 /* Clear wake up flag and disable wake up interrupt */
474 writel_relaxed(USART_ICR_WUCF,
475 port->membase + ofs->icr);
476 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
477 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
478 pm_wakeup_event(tport->tty->dev, 0);
479 }
480
481 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
482 stm32_usart_receive_chars(port, false);
483
484 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
485 spin_lock(&port->lock);
486 stm32_usart_transmit_chars(port);
487 spin_unlock(&port->lock);
488 }
489
490 if (stm32_port->rx_ch)
491 return IRQ_WAKE_THREAD;
492 else
493 return IRQ_HANDLED;
494}
495
496static irqreturn_t stm32_usart_threaded_interrupt(int irq, void *ptr)
497{
498 struct uart_port *port = ptr;
499 struct stm32_port *stm32_port = to_stm32_port(port);
500
501 if (stm32_port->rx_ch)
502 stm32_usart_receive_chars(port, true);
503
504 return IRQ_HANDLED;
505}
506
507static unsigned int stm32_usart_tx_empty(struct uart_port *port)
508{
509 struct stm32_port *stm32_port = to_stm32_port(port);
510 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
511
512 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
513 return TIOCSER_TEMT;
514
515 return 0;
516}
517
518static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
519{
520 struct stm32_port *stm32_port = to_stm32_port(port);
521 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
522
523 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
524 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
525 else
526 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
527
528 mctrl_gpio_set(stm32_port->gpios, mctrl);
529}
530
531static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
532{
533 struct stm32_port *stm32_port = to_stm32_port(port);
534 unsigned int ret;
535
536 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
537 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
538
539 return mctrl_gpio_get(stm32_port->gpios, &ret);
540}
541
542static void stm32_usart_enable_ms(struct uart_port *port)
543{
544 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
545}
546
547static void stm32_usart_disable_ms(struct uart_port *port)
548{
549 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
550}
551
552/* Transmit stop */
553static void stm32_usart_stop_tx(struct uart_port *port)
554{
555 struct stm32_port *stm32_port = to_stm32_port(port);
556 struct serial_rs485 *rs485conf = &port->rs485;
557
558 stm32_usart_tx_interrupt_disable(port);
559
560 if (rs485conf->flags & SER_RS485_ENABLED) {
561 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
562 mctrl_gpio_set(stm32_port->gpios,
563 stm32_port->port.mctrl & ~TIOCM_RTS);
564 } else {
565 mctrl_gpio_set(stm32_port->gpios,
566 stm32_port->port.mctrl | TIOCM_RTS);
567 }
568 }
569}
570
571/* There are probably characters waiting to be transmitted. */
572static void stm32_usart_start_tx(struct uart_port *port)
573{
574 struct stm32_port *stm32_port = to_stm32_port(port);
575 struct serial_rs485 *rs485conf = &port->rs485;
576 struct circ_buf *xmit = &port->state->xmit;
577
578 if (uart_circ_empty(xmit))
579 return;
580
581 if (rs485conf->flags & SER_RS485_ENABLED) {
582 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
583 mctrl_gpio_set(stm32_port->gpios,
584 stm32_port->port.mctrl | TIOCM_RTS);
585 } else {
586 mctrl_gpio_set(stm32_port->gpios,
587 stm32_port->port.mctrl & ~TIOCM_RTS);
588 }
589 }
590
591 stm32_usart_transmit_chars(port);
592}
593
594/* Flush the transmit buffer. */
595static void stm32_usart_flush_buffer(struct uart_port *port)
596{
597 struct stm32_port *stm32_port = to_stm32_port(port);
598 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
599
600 if (stm32_port->tx_ch) {
601 dmaengine_terminate_async(stm32_port->tx_ch);
602 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
603 stm32_port->tx_dma_busy = false;
604 }
605}
606
607/* Throttle the remote when input buffer is about to overflow. */
608static void stm32_usart_throttle(struct uart_port *port)
609{
610 struct stm32_port *stm32_port = to_stm32_port(port);
611 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
612 unsigned long flags;
613
614 spin_lock_irqsave(&port->lock, flags);
615 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
616 if (stm32_port->cr3_irq)
617 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
618
619 spin_unlock_irqrestore(&port->lock, flags);
620}
621
622/* Unthrottle the remote, the input buffer can now accept data. */
623static void stm32_usart_unthrottle(struct uart_port *port)
624{
625 struct stm32_port *stm32_port = to_stm32_port(port);
626 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
627 unsigned long flags;
628
629 spin_lock_irqsave(&port->lock, flags);
630 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
631 if (stm32_port->cr3_irq)
632 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
633
634 spin_unlock_irqrestore(&port->lock, flags);
635}
636
637/* Receive stop */
638static void stm32_usart_stop_rx(struct uart_port *port)
639{
640 struct stm32_port *stm32_port = to_stm32_port(port);
641 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
642
643 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
644 if (stm32_port->cr3_irq)
645 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
646}
647
648/* Handle breaks - ignored by us */
649static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
650{
651}
652
653static int stm32_usart_startup(struct uart_port *port)
654{
655 struct stm32_port *stm32_port = to_stm32_port(port);
656 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
657 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
658 const char *name = to_platform_device(port->dev)->name;
659 u32 val;
660 int ret;
661
662 ret = request_threaded_irq(port->irq, stm32_usart_interrupt,
663 stm32_usart_threaded_interrupt,
664 IRQF_ONESHOT | IRQF_NO_SUSPEND,
665 name, port);
666 if (ret)
667 return ret;
668
669 if (stm32_port->swap) {
670 val = readl_relaxed(port->membase + ofs->cr2);
671 val |= USART_CR2_SWAP;
672 writel_relaxed(val, port->membase + ofs->cr2);
673 }
674
675 /* RX FIFO Flush */
676 if (ofs->rqr != UNDEF_REG)
677 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
678
679 /* RX enabling */
680 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
681 stm32_usart_set_bits(port, ofs->cr1, val);
682
683 return 0;
684}
685
686static void stm32_usart_shutdown(struct uart_port *port)
687{
688 struct stm32_port *stm32_port = to_stm32_port(port);
689 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
690 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
691 u32 val, isr;
692 int ret;
693
694 /* Disable modem control interrupts */
695 stm32_usart_disable_ms(port);
696
697 val = USART_CR1_TXEIE | USART_CR1_TE;
698 val |= stm32_port->cr1_irq | USART_CR1_RE;
699 val |= BIT(cfg->uart_enable_bit);
700 if (stm32_port->fifoen)
701 val |= USART_CR1_FIFOEN;
702
703 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
704 isr, (isr & USART_SR_TC),
705 10, 100000);
706
707 /* Send the TC error message only when ISR_TC is not set */
708 if (ret)
709 dev_err(port->dev, "Transmission is not complete\n");
710
711 /* flush RX & TX FIFO */
712 if (ofs->rqr != UNDEF_REG)
713 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
714 port->membase + ofs->rqr);
715
716 stm32_usart_clr_bits(port, ofs->cr1, val);
717
718 free_irq(port->irq, port);
719}
720
721static void stm32_usart_set_termios(struct uart_port *port,
722 struct ktermios *termios,
723 struct ktermios *old)
724{
725 struct stm32_port *stm32_port = to_stm32_port(port);
726 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
727 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
728 struct serial_rs485 *rs485conf = &port->rs485;
729 unsigned int baud, bits;
730 u32 usartdiv, mantissa, fraction, oversampling;
731 tcflag_t cflag = termios->c_cflag;
732 u32 cr1, cr2, cr3, isr;
733 unsigned long flags;
734 int ret;
735
736 if (!stm32_port->hw_flow_control)
737 cflag &= ~CRTSCTS;
738
739 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
740
741 spin_lock_irqsave(&port->lock, flags);
742
743 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
744 isr,
745 (isr & USART_SR_TC),
746 10, 100000);
747
748 /* Send the TC error message only when ISR_TC is not set. */
749 if (ret)
750 dev_err(port->dev, "Transmission is not complete\n");
751
752 /* Stop serial port and reset value */
753 writel_relaxed(0, port->membase + ofs->cr1);
754
755 /* flush RX & TX FIFO */
756 if (ofs->rqr != UNDEF_REG)
757 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
758 port->membase + ofs->rqr);
759
760 cr1 = USART_CR1_TE | USART_CR1_RE;
761 if (stm32_port->fifoen)
762 cr1 |= USART_CR1_FIFOEN;
763 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
764
765 /* Tx and RX FIFO configuration */
766 cr3 = readl_relaxed(port->membase + ofs->cr3);
767 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
768 if (stm32_port->fifoen) {
769 if (stm32_port->txftcfg >= 0)
770 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
771 if (stm32_port->rxftcfg >= 0)
772 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
773 }
774
775 if (cflag & CSTOPB)
776 cr2 |= USART_CR2_STOP_2B;
777
778 bits = tty_get_char_size(cflag);
779 stm32_port->rdr_mask = (BIT(bits) - 1);
780
781 if (cflag & PARENB) {
782 bits++;
783 cr1 |= USART_CR1_PCE;
784 }
785
786 /*
787 * Word length configuration:
788 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
789 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
790 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
791 * M0 and M1 already cleared by cr1 initialization.
792 */
793 if (bits == 9)
794 cr1 |= USART_CR1_M0;
795 else if ((bits == 7) && cfg->has_7bits_data)
796 cr1 |= USART_CR1_M1;
797 else if (bits != 8)
798 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
799 , bits);
800
801 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
802 (stm32_port->fifoen &&
803 stm32_port->rxftcfg >= 0))) {
804 if (cflag & CSTOPB)
805 bits = bits + 3; /* 1 start bit + 2 stop bits */
806 else
807 bits = bits + 2; /* 1 start bit + 1 stop bit */
808
809 /* RX timeout irq to occur after last stop bit + bits */
810 stm32_port->cr1_irq = USART_CR1_RTOIE;
811 writel_relaxed(bits, port->membase + ofs->rtor);
812 cr2 |= USART_CR2_RTOEN;
813 /* Not using dma, enable fifo threshold irq */
814 if (!stm32_port->rx_ch)
815 stm32_port->cr3_irq = USART_CR3_RXFTIE;
816 }
817
818 cr1 |= stm32_port->cr1_irq;
819 cr3 |= stm32_port->cr3_irq;
820
821 if (cflag & PARODD)
822 cr1 |= USART_CR1_PS;
823
824 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
825 if (cflag & CRTSCTS) {
826 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
827 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
828 }
829
830 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
831
832 /*
833 * The USART supports 16 or 8 times oversampling.
834 * By default we prefer 16 times oversampling, so that the receiver
835 * has a better tolerance to clock deviations.
836 * 8 times oversampling is only used to achieve higher speeds.
837 */
838 if (usartdiv < 16) {
839 oversampling = 8;
840 cr1 |= USART_CR1_OVER8;
841 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
842 } else {
843 oversampling = 16;
844 cr1 &= ~USART_CR1_OVER8;
845 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
846 }
847
848 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
849 fraction = usartdiv % oversampling;
850 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
851
852 uart_update_timeout(port, cflag, baud);
853
854 port->read_status_mask = USART_SR_ORE;
855 if (termios->c_iflag & INPCK)
856 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
857 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
858 port->read_status_mask |= USART_SR_FE;
859
860 /* Characters to ignore */
861 port->ignore_status_mask = 0;
862 if (termios->c_iflag & IGNPAR)
863 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
864 if (termios->c_iflag & IGNBRK) {
865 port->ignore_status_mask |= USART_SR_FE;
866 /*
867 * If we're ignoring parity and break indicators,
868 * ignore overruns too (for real raw support).
869 */
870 if (termios->c_iflag & IGNPAR)
871 port->ignore_status_mask |= USART_SR_ORE;
872 }
873
874 /* Ignore all characters if CREAD is not set */
875 if ((termios->c_cflag & CREAD) == 0)
876 port->ignore_status_mask |= USART_SR_DUMMY_RX;
877
878 if (stm32_port->rx_ch)
879 cr3 |= USART_CR3_DMAR;
880
881 if (rs485conf->flags & SER_RS485_ENABLED) {
882 stm32_usart_config_reg_rs485(&cr1, &cr3,
883 rs485conf->delay_rts_before_send,
884 rs485conf->delay_rts_after_send,
885 baud);
886 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
887 cr3 &= ~USART_CR3_DEP;
888 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
889 } else {
890 cr3 |= USART_CR3_DEP;
891 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
892 }
893
894 } else {
895 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
896 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
897 }
898
899 /* Configure wake up from low power on start bit detection */
900 if (stm32_port->wakeup_src) {
901 cr3 &= ~USART_CR3_WUS_MASK;
902 cr3 |= USART_CR3_WUS_START_BIT;
903 }
904
905 writel_relaxed(cr3, port->membase + ofs->cr3);
906 writel_relaxed(cr2, port->membase + ofs->cr2);
907 writel_relaxed(cr1, port->membase + ofs->cr1);
908
909 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
910 spin_unlock_irqrestore(&port->lock, flags);
911
912 /* Handle modem control interrupts */
913 if (UART_ENABLE_MS(port, termios->c_cflag))
914 stm32_usart_enable_ms(port);
915 else
916 stm32_usart_disable_ms(port);
917}
918
919static const char *stm32_usart_type(struct uart_port *port)
920{
921 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
922}
923
924static void stm32_usart_release_port(struct uart_port *port)
925{
926}
927
928static int stm32_usart_request_port(struct uart_port *port)
929{
930 return 0;
931}
932
933static void stm32_usart_config_port(struct uart_port *port, int flags)
934{
935 if (flags & UART_CONFIG_TYPE)
936 port->type = PORT_STM32;
937}
938
939static int
940stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
941{
942 /* No user changeable parameters */
943 return -EINVAL;
944}
945
946static void stm32_usart_pm(struct uart_port *port, unsigned int state,
947 unsigned int oldstate)
948{
949 struct stm32_port *stm32port = container_of(port,
950 struct stm32_port, port);
951 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
952 const struct stm32_usart_config *cfg = &stm32port->info->cfg;
953 unsigned long flags;
954
955 switch (state) {
956 case UART_PM_STATE_ON:
957 pm_runtime_get_sync(port->dev);
958 break;
959 case UART_PM_STATE_OFF:
960 spin_lock_irqsave(&port->lock, flags);
961 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
962 spin_unlock_irqrestore(&port->lock, flags);
963 pm_runtime_put_sync(port->dev);
964 break;
965 }
966}
967
968static const struct uart_ops stm32_uart_ops = {
969 .tx_empty = stm32_usart_tx_empty,
970 .set_mctrl = stm32_usart_set_mctrl,
971 .get_mctrl = stm32_usart_get_mctrl,
972 .stop_tx = stm32_usart_stop_tx,
973 .start_tx = stm32_usart_start_tx,
974 .throttle = stm32_usart_throttle,
975 .unthrottle = stm32_usart_unthrottle,
976 .stop_rx = stm32_usart_stop_rx,
977 .enable_ms = stm32_usart_enable_ms,
978 .break_ctl = stm32_usart_break_ctl,
979 .startup = stm32_usart_startup,
980 .shutdown = stm32_usart_shutdown,
981 .flush_buffer = stm32_usart_flush_buffer,
982 .set_termios = stm32_usart_set_termios,
983 .pm = stm32_usart_pm,
984 .type = stm32_usart_type,
985 .release_port = stm32_usart_release_port,
986 .request_port = stm32_usart_request_port,
987 .config_port = stm32_usart_config_port,
988 .verify_port = stm32_usart_verify_port,
989};
990
991/*
992 * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
993 * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case,
994 * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE.
995 * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1.
996 */
997static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 };
998
999static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p,
1000 int *ftcfg)
1001{
1002 u32 bytes, i;
1003
1004 /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */
1005 if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1006 bytes = 8;
1007
1008 for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++)
1009 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes)
1010 break;
1011 if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1012 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1013
1014 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p,
1015 stm32h7_usart_fifo_thresh_cfg[i]);
1016
1017 /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */
1018 if (i)
1019 *ftcfg = i - 1;
1020 else
1021 *ftcfg = -EINVAL;
1022}
1023
1024static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1025{
1026 clk_disable_unprepare(stm32port->clk);
1027}
1028
1029static int stm32_usart_init_port(struct stm32_port *stm32port,
1030 struct platform_device *pdev)
1031{
1032 struct uart_port *port = &stm32port->port;
1033 struct resource *res;
1034 int ret, irq;
1035
1036 irq = platform_get_irq(pdev, 0);
1037 if (irq <= 0)
1038 return irq ? : -ENODEV;
1039
1040 port->iotype = UPIO_MEM;
1041 port->flags = UPF_BOOT_AUTOCONF;
1042 port->ops = &stm32_uart_ops;
1043 port->dev = &pdev->dev;
1044 port->fifosize = stm32port->info->cfg.fifosize;
1045 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1046 port->irq = irq;
1047 port->rs485_config = stm32_usart_config_rs485;
1048
1049 ret = stm32_usart_init_rs485(port, pdev);
1050 if (ret)
1051 return ret;
1052
1053 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1054 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1055
1056 stm32port->swap = stm32port->info->cfg.has_swap &&
1057 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1058
1059 stm32port->fifoen = stm32port->info->cfg.has_fifo;
1060 if (stm32port->fifoen) {
1061 stm32_usart_get_ftcfg(pdev, "rx-threshold",
1062 &stm32port->rxftcfg);
1063 stm32_usart_get_ftcfg(pdev, "tx-threshold",
1064 &stm32port->txftcfg);
1065 }
1066
1067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068 port->membase = devm_ioremap_resource(&pdev->dev, res);
1069 if (IS_ERR(port->membase))
1070 return PTR_ERR(port->membase);
1071 port->mapbase = res->start;
1072
1073 spin_lock_init(&port->lock);
1074
1075 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1076 if (IS_ERR(stm32port->clk))
1077 return PTR_ERR(stm32port->clk);
1078
1079 /* Ensure that clk rate is correct by enabling the clk */
1080 ret = clk_prepare_enable(stm32port->clk);
1081 if (ret)
1082 return ret;
1083
1084 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1085 if (!stm32port->port.uartclk) {
1086 ret = -EINVAL;
1087 goto err_clk;
1088 }
1089
1090 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1091 if (IS_ERR(stm32port->gpios)) {
1092 ret = PTR_ERR(stm32port->gpios);
1093 goto err_clk;
1094 }
1095
1096 /*
1097 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1098 * properties should not be specified.
1099 */
1100 if (stm32port->hw_flow_control) {
1101 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1102 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1103 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1104 ret = -EINVAL;
1105 goto err_clk;
1106 }
1107 }
1108
1109 return ret;
1110
1111err_clk:
1112 clk_disable_unprepare(stm32port->clk);
1113
1114 return ret;
1115}
1116
1117static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1118{
1119 struct device_node *np = pdev->dev.of_node;
1120 int id;
1121
1122 if (!np)
1123 return NULL;
1124
1125 id = of_alias_get_id(np, "serial");
1126 if (id < 0) {
1127 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1128 return NULL;
1129 }
1130
1131 if (WARN_ON(id >= STM32_MAX_PORTS))
1132 return NULL;
1133
1134 stm32_ports[id].hw_flow_control =
1135 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1136 of_property_read_bool (np, "uart-has-rtscts");
1137 stm32_ports[id].port.line = id;
1138 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1139 stm32_ports[id].cr3_irq = 0;
1140 stm32_ports[id].last_res = RX_BUF_L;
1141 return &stm32_ports[id];
1142}
1143
1144#ifdef CONFIG_OF
1145static const struct of_device_id stm32_match[] = {
1146 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1147 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1148 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1149 {},
1150};
1151
1152MODULE_DEVICE_TABLE(of, stm32_match);
1153#endif
1154
1155static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1156 struct platform_device *pdev)
1157{
1158 if (stm32port->rx_buf)
1159 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1160 stm32port->rx_dma_buf);
1161}
1162
1163static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1164 struct platform_device *pdev)
1165{
1166 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1167 struct uart_port *port = &stm32port->port;
1168 struct device *dev = &pdev->dev;
1169 struct dma_slave_config config;
1170 struct dma_async_tx_descriptor *desc = NULL;
1171 int ret;
1172
1173 /*
1174 * Using DMA and threaded handler for the console could lead to
1175 * deadlocks.
1176 */
1177 if (uart_console(port))
1178 return -ENODEV;
1179
1180 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1181 &stm32port->rx_dma_buf,
1182 GFP_KERNEL);
1183 if (!stm32port->rx_buf)
1184 return -ENOMEM;
1185
1186 /* Configure DMA channel */
1187 memset(&config, 0, sizeof(config));
1188 config.src_addr = port->mapbase + ofs->rdr;
1189 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1190
1191 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1192 if (ret < 0) {
1193 dev_err(dev, "rx dma channel config failed\n");
1194 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1195 return ret;
1196 }
1197
1198 /* Prepare a DMA cyclic transaction */
1199 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1200 stm32port->rx_dma_buf,
1201 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1202 DMA_PREP_INTERRUPT);
1203 if (!desc) {
1204 dev_err(dev, "rx dma prep cyclic failed\n");
1205 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1206 return -ENODEV;
1207 }
1208
1209 /* No callback as dma buffer is drained on usart interrupt */
1210 desc->callback = NULL;
1211 desc->callback_param = NULL;
1212
1213 /* Push current DMA transaction in the pending queue */
1214 ret = dma_submit_error(dmaengine_submit(desc));
1215 if (ret) {
1216 dmaengine_terminate_sync(stm32port->rx_ch);
1217 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1218 return ret;
1219 }
1220
1221 /* Issue pending DMA requests */
1222 dma_async_issue_pending(stm32port->rx_ch);
1223
1224 return 0;
1225}
1226
1227static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1228 struct platform_device *pdev)
1229{
1230 if (stm32port->tx_buf)
1231 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1232 stm32port->tx_dma_buf);
1233}
1234
1235static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1236 struct platform_device *pdev)
1237{
1238 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1239 struct uart_port *port = &stm32port->port;
1240 struct device *dev = &pdev->dev;
1241 struct dma_slave_config config;
1242 int ret;
1243
1244 stm32port->tx_dma_busy = false;
1245
1246 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1247 &stm32port->tx_dma_buf,
1248 GFP_KERNEL);
1249 if (!stm32port->tx_buf)
1250 return -ENOMEM;
1251
1252 /* Configure DMA channel */
1253 memset(&config, 0, sizeof(config));
1254 config.dst_addr = port->mapbase + ofs->tdr;
1255 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1256
1257 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1258 if (ret < 0) {
1259 dev_err(dev, "tx dma channel config failed\n");
1260 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1261 return ret;
1262 }
1263
1264 return 0;
1265}
1266
1267static int stm32_usart_serial_probe(struct platform_device *pdev)
1268{
1269 struct stm32_port *stm32port;
1270 int ret;
1271
1272 stm32port = stm32_usart_of_get_port(pdev);
1273 if (!stm32port)
1274 return -ENODEV;
1275
1276 stm32port->info = of_device_get_match_data(&pdev->dev);
1277 if (!stm32port->info)
1278 return -EINVAL;
1279
1280 ret = stm32_usart_init_port(stm32port, pdev);
1281 if (ret)
1282 return ret;
1283
1284 if (stm32port->wakeup_src) {
1285 device_set_wakeup_capable(&pdev->dev, true);
1286 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1287 if (ret)
1288 goto err_deinit_port;
1289 }
1290
1291 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1292 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) {
1293 ret = -EPROBE_DEFER;
1294 goto err_wakeirq;
1295 }
1296 /* Fall back in interrupt mode for any non-deferral error */
1297 if (IS_ERR(stm32port->rx_ch))
1298 stm32port->rx_ch = NULL;
1299
1300 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1301 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1302 ret = -EPROBE_DEFER;
1303 goto err_dma_rx;
1304 }
1305 /* Fall back in interrupt mode for any non-deferral error */
1306 if (IS_ERR(stm32port->tx_ch))
1307 stm32port->tx_ch = NULL;
1308
1309 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1310 /* Fall back in interrupt mode */
1311 dma_release_channel(stm32port->rx_ch);
1312 stm32port->rx_ch = NULL;
1313 }
1314
1315 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1316 /* Fall back in interrupt mode */
1317 dma_release_channel(stm32port->tx_ch);
1318 stm32port->tx_ch = NULL;
1319 }
1320
1321 if (!stm32port->rx_ch)
1322 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1323 if (!stm32port->tx_ch)
1324 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1325
1326 platform_set_drvdata(pdev, &stm32port->port);
1327
1328 pm_runtime_get_noresume(&pdev->dev);
1329 pm_runtime_set_active(&pdev->dev);
1330 pm_runtime_enable(&pdev->dev);
1331
1332 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1333 if (ret)
1334 goto err_port;
1335
1336 pm_runtime_put_sync(&pdev->dev);
1337
1338 return 0;
1339
1340err_port:
1341 pm_runtime_disable(&pdev->dev);
1342 pm_runtime_set_suspended(&pdev->dev);
1343 pm_runtime_put_noidle(&pdev->dev);
1344
1345 if (stm32port->tx_ch) {
1346 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1347 dma_release_channel(stm32port->tx_ch);
1348 }
1349
1350 if (stm32port->rx_ch)
1351 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1352
1353err_dma_rx:
1354 if (stm32port->rx_ch)
1355 dma_release_channel(stm32port->rx_ch);
1356
1357err_wakeirq:
1358 if (stm32port->wakeup_src)
1359 dev_pm_clear_wake_irq(&pdev->dev);
1360
1361err_deinit_port:
1362 if (stm32port->wakeup_src)
1363 device_set_wakeup_capable(&pdev->dev, false);
1364
1365 stm32_usart_deinit_port(stm32port);
1366
1367 return ret;
1368}
1369
1370static int stm32_usart_serial_remove(struct platform_device *pdev)
1371{
1372 struct uart_port *port = platform_get_drvdata(pdev);
1373 struct stm32_port *stm32_port = to_stm32_port(port);
1374 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1375 int err;
1376
1377 pm_runtime_get_sync(&pdev->dev);
1378 err = uart_remove_one_port(&stm32_usart_driver, port);
1379 if (err)
1380 return(err);
1381
1382 pm_runtime_disable(&pdev->dev);
1383 pm_runtime_set_suspended(&pdev->dev);
1384 pm_runtime_put_noidle(&pdev->dev);
1385
1386 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1387
1388 if (stm32_port->tx_ch) {
1389 dmaengine_terminate_async(stm32_port->tx_ch);
1390 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1391 dma_release_channel(stm32_port->tx_ch);
1392 }
1393
1394 if (stm32_port->rx_ch) {
1395 dmaengine_terminate_async(stm32_port->rx_ch);
1396 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1397 dma_release_channel(stm32_port->rx_ch);
1398 }
1399
1400 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1401
1402 if (stm32_port->wakeup_src) {
1403 dev_pm_clear_wake_irq(&pdev->dev);
1404 device_init_wakeup(&pdev->dev, false);
1405 }
1406
1407 stm32_usart_deinit_port(stm32_port);
1408
1409 return 0;
1410}
1411
1412#ifdef CONFIG_SERIAL_STM32_CONSOLE
1413static void stm32_usart_console_putchar(struct uart_port *port, int ch)
1414{
1415 struct stm32_port *stm32_port = to_stm32_port(port);
1416 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1417
1418 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1419 cpu_relax();
1420
1421 writel_relaxed(ch, port->membase + ofs->tdr);
1422}
1423
1424static void stm32_usart_console_write(struct console *co, const char *s,
1425 unsigned int cnt)
1426{
1427 struct uart_port *port = &stm32_ports[co->index].port;
1428 struct stm32_port *stm32_port = to_stm32_port(port);
1429 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1430 const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1431 unsigned long flags;
1432 u32 old_cr1, new_cr1;
1433 int locked = 1;
1434
1435 if (oops_in_progress)
1436 locked = spin_trylock_irqsave(&port->lock, flags);
1437 else
1438 spin_lock_irqsave(&port->lock, flags);
1439
1440 /* Save and disable interrupts, enable the transmitter */
1441 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1442 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1443 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1444 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1445
1446 uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1447
1448 /* Restore interrupt state */
1449 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1450
1451 if (locked)
1452 spin_unlock_irqrestore(&port->lock, flags);
1453}
1454
1455static int stm32_usart_console_setup(struct console *co, char *options)
1456{
1457 struct stm32_port *stm32port;
1458 int baud = 9600;
1459 int bits = 8;
1460 int parity = 'n';
1461 int flow = 'n';
1462
1463 if (co->index >= STM32_MAX_PORTS)
1464 return -ENODEV;
1465
1466 stm32port = &stm32_ports[co->index];
1467
1468 /*
1469 * This driver does not support early console initialization
1470 * (use ARM early printk support instead), so we only expect
1471 * this to be called during the uart port registration when the
1472 * driver gets probed and the port should be mapped at that point.
1473 */
1474 if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1475 return -ENXIO;
1476
1477 if (options)
1478 uart_parse_options(options, &baud, &parity, &bits, &flow);
1479
1480 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1481}
1482
1483static struct console stm32_console = {
1484 .name = STM32_SERIAL_NAME,
1485 .device = uart_console_device,
1486 .write = stm32_usart_console_write,
1487 .setup = stm32_usart_console_setup,
1488 .flags = CON_PRINTBUFFER,
1489 .index = -1,
1490 .data = &stm32_usart_driver,
1491};
1492
1493#define STM32_SERIAL_CONSOLE (&stm32_console)
1494
1495#else
1496#define STM32_SERIAL_CONSOLE NULL
1497#endif /* CONFIG_SERIAL_STM32_CONSOLE */
1498
1499static struct uart_driver stm32_usart_driver = {
1500 .driver_name = DRIVER_NAME,
1501 .dev_name = STM32_SERIAL_NAME,
1502 .major = 0,
1503 .minor = 0,
1504 .nr = STM32_MAX_PORTS,
1505 .cons = STM32_SERIAL_CONSOLE,
1506};
1507
1508static void __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
1509 bool enable)
1510{
1511 struct stm32_port *stm32_port = to_stm32_port(port);
1512 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1513
1514 if (!stm32_port->wakeup_src)
1515 return;
1516
1517 /*
1518 * Enable low-power wake-up and wake-up irq if argument is set to
1519 * "enable", disable low-power wake-up and wake-up irq otherwise
1520 */
1521 if (enable) {
1522 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
1523 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
1524 } else {
1525 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1526 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
1527 }
1528}
1529
1530static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
1531{
1532 struct uart_port *port = dev_get_drvdata(dev);
1533
1534 uart_suspend_port(&stm32_usart_driver, port);
1535
1536 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1537 stm32_usart_serial_en_wakeup(port, true);
1538
1539 /*
1540 * When "no_console_suspend" is enabled, keep the pinctrl default state
1541 * and rely on bootloader stage to restore this state upon resume.
1542 * Otherwise, apply the idle or sleep states depending on wakeup
1543 * capabilities.
1544 */
1545 if (console_suspend_enabled || !uart_console(port)) {
1546 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1547 pinctrl_pm_select_idle_state(dev);
1548 else
1549 pinctrl_pm_select_sleep_state(dev);
1550 }
1551
1552 return 0;
1553}
1554
1555static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
1556{
1557 struct uart_port *port = dev_get_drvdata(dev);
1558
1559 pinctrl_pm_select_default_state(dev);
1560
1561 if (device_may_wakeup(dev) || device_wakeup_path(dev))
1562 stm32_usart_serial_en_wakeup(port, false);
1563
1564 return uart_resume_port(&stm32_usart_driver, port);
1565}
1566
1567static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
1568{
1569 struct uart_port *port = dev_get_drvdata(dev);
1570 struct stm32_port *stm32port = container_of(port,
1571 struct stm32_port, port);
1572
1573 clk_disable_unprepare(stm32port->clk);
1574
1575 return 0;
1576}
1577
1578static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
1579{
1580 struct uart_port *port = dev_get_drvdata(dev);
1581 struct stm32_port *stm32port = container_of(port,
1582 struct stm32_port, port);
1583
1584 return clk_prepare_enable(stm32port->clk);
1585}
1586
1587static const struct dev_pm_ops stm32_serial_pm_ops = {
1588 SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
1589 stm32_usart_runtime_resume, NULL)
1590 SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
1591 stm32_usart_serial_resume)
1592};
1593
1594static struct platform_driver stm32_serial_driver = {
1595 .probe = stm32_usart_serial_probe,
1596 .remove = stm32_usart_serial_remove,
1597 .driver = {
1598 .name = DRIVER_NAME,
1599 .pm = &stm32_serial_pm_ops,
1600 .of_match_table = of_match_ptr(stm32_match),
1601 },
1602};
1603
1604static int __init stm32_usart_init(void)
1605{
1606 static char banner[] __initdata = "STM32 USART driver initialized";
1607 int ret;
1608
1609 pr_info("%s\n", banner);
1610
1611 ret = uart_register_driver(&stm32_usart_driver);
1612 if (ret)
1613 return ret;
1614
1615 ret = platform_driver_register(&stm32_serial_driver);
1616 if (ret)
1617 uart_unregister_driver(&stm32_usart_driver);
1618
1619 return ret;
1620}
1621
1622static void __exit stm32_usart_exit(void)
1623{
1624 platform_driver_unregister(&stm32_serial_driver);
1625 uart_unregister_driver(&stm32_usart_driver);
1626}
1627
1628module_init(stm32_usart_init);
1629module_exit(stm32_usart_exit);
1630
1631MODULE_ALIAS("platform:" DRIVER_NAME);
1632MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1633MODULE_LICENSE("GPL v2");