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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)
9 */
10
11#if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/clk.h>
16#include <linux/console.h>
17#include <linux/delay.h>
18#include <linux/dma-direction.h>
19#include <linux/dmaengine.h>
20#include <linux/dma-mapping.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/irq.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/pm_wakeirq.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33#include <linux/spinlock.h>
34#include <linux/sysrq.h>
35#include <linux/tty_flip.h>
36#include <linux/tty.h>
37
38#include "stm32-usart.h"
39
40static void stm32_stop_tx(struct uart_port *port);
41static void stm32_transmit_chars(struct uart_port *port);
42
43static inline struct stm32_port *to_stm32_port(struct uart_port *port)
44{
45 return container_of(port, struct stm32_port, port);
46}
47
48static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
49{
50 u32 val;
51
52 val = readl_relaxed(port->membase + reg);
53 val |= bits;
54 writel_relaxed(val, port->membase + reg);
55}
56
57static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
58{
59 u32 val;
60
61 val = readl_relaxed(port->membase + reg);
62 val &= ~bits;
63 writel_relaxed(val, port->membase + reg);
64}
65
66static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
67 u32 delay_DDE, u32 baud)
68{
69 u32 rs485_deat_dedt;
70 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
71 bool over8;
72
73 *cr3 |= USART_CR3_DEM;
74 over8 = *cr1 & USART_CR1_OVER8;
75
76 if (over8)
77 rs485_deat_dedt = delay_ADE * baud * 8;
78 else
79 rs485_deat_dedt = delay_ADE * baud * 16;
80
81 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
82 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
83 rs485_deat_dedt_max : rs485_deat_dedt;
84 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
85 USART_CR1_DEAT_MASK;
86 *cr1 |= rs485_deat_dedt;
87
88 if (over8)
89 rs485_deat_dedt = delay_DDE * baud * 8;
90 else
91 rs485_deat_dedt = delay_DDE * baud * 16;
92
93 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
94 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
95 rs485_deat_dedt_max : rs485_deat_dedt;
96 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
97 USART_CR1_DEDT_MASK;
98 *cr1 |= rs485_deat_dedt;
99}
100
101static int stm32_config_rs485(struct uart_port *port,
102 struct serial_rs485 *rs485conf)
103{
104 struct stm32_port *stm32_port = to_stm32_port(port);
105 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
106 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
107 u32 usartdiv, baud, cr1, cr3;
108 bool over8;
109
110 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
111
112 port->rs485 = *rs485conf;
113
114 rs485conf->flags |= SER_RS485_RX_DURING_TX;
115
116 if (rs485conf->flags & SER_RS485_ENABLED) {
117 cr1 = readl_relaxed(port->membase + ofs->cr1);
118 cr3 = readl_relaxed(port->membase + ofs->cr3);
119 usartdiv = readl_relaxed(port->membase + ofs->brr);
120 usartdiv = usartdiv & GENMASK(15, 0);
121 over8 = cr1 & USART_CR1_OVER8;
122
123 if (over8)
124 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
125 << USART_BRR_04_R_SHIFT;
126
127 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
128 stm32_config_reg_rs485(&cr1, &cr3,
129 rs485conf->delay_rts_before_send,
130 rs485conf->delay_rts_after_send, baud);
131
132 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
133 cr3 &= ~USART_CR3_DEP;
134 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
135 } else {
136 cr3 |= USART_CR3_DEP;
137 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
138 }
139
140 writel_relaxed(cr3, port->membase + ofs->cr3);
141 writel_relaxed(cr1, port->membase + ofs->cr1);
142 } else {
143 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
144 stm32_clr_bits(port, ofs->cr1,
145 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
146 }
147
148 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
149
150 return 0;
151}
152
153static int stm32_init_rs485(struct uart_port *port,
154 struct platform_device *pdev)
155{
156 struct serial_rs485 *rs485conf = &port->rs485;
157
158 rs485conf->flags = 0;
159 rs485conf->delay_rts_before_send = 0;
160 rs485conf->delay_rts_after_send = 0;
161
162 if (!pdev->dev.of_node)
163 return -ENODEV;
164
165 uart_get_rs485_mode(&pdev->dev, rs485conf);
166
167 return 0;
168}
169
170static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
171 bool threaded)
172{
173 struct stm32_port *stm32_port = to_stm32_port(port);
174 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
175 enum dma_status status;
176 struct dma_tx_state state;
177
178 *sr = readl_relaxed(port->membase + ofs->isr);
179
180 if (threaded && stm32_port->rx_ch) {
181 status = dmaengine_tx_status(stm32_port->rx_ch,
182 stm32_port->rx_ch->cookie,
183 &state);
184 if ((status == DMA_IN_PROGRESS) &&
185 (*last_res != state.residue))
186 return 1;
187 else
188 return 0;
189 } else if (*sr & USART_SR_RXNE) {
190 return 1;
191 }
192 return 0;
193}
194
195static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
196 int *last_res)
197{
198 struct stm32_port *stm32_port = to_stm32_port(port);
199 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
200 unsigned long c;
201
202 if (stm32_port->rx_ch) {
203 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
204 if ((*last_res) == 0)
205 *last_res = RX_BUF_L;
206 } else {
207 c = readl_relaxed(port->membase + ofs->rdr);
208 /* apply RDR data mask */
209 c &= stm32_port->rdr_mask;
210 }
211
212 return c;
213}
214
215static void stm32_receive_chars(struct uart_port *port, bool threaded)
216{
217 struct tty_port *tport = &port->state->port;
218 struct stm32_port *stm32_port = to_stm32_port(port);
219 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
220 unsigned long c;
221 u32 sr;
222 char flag;
223
224 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
225 pm_wakeup_event(tport->tty->dev, 0);
226
227 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
228 sr |= USART_SR_DUMMY_RX;
229 flag = TTY_NORMAL;
230
231 /*
232 * Status bits has to be cleared before reading the RDR:
233 * In FIFO mode, reading the RDR will pop the next data
234 * (if any) along with its status bits into the SR.
235 * Not doing so leads to misalignement between RDR and SR,
236 * and clear status bits of the next rx data.
237 *
238 * Clear errors flags for stm32f7 and stm32h7 compatible
239 * devices. On stm32f4 compatible devices, the error bit is
240 * cleared by the sequence [read SR - read DR].
241 */
242 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
243 stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF |
244 USART_ICR_PECF | USART_ICR_FECF);
245
246 c = stm32_get_char(port, &sr, &stm32_port->last_res);
247 port->icount.rx++;
248 if (sr & USART_SR_ERR_MASK) {
249 if (sr & USART_SR_ORE) {
250 port->icount.overrun++;
251 } else if (sr & USART_SR_PE) {
252 port->icount.parity++;
253 } else if (sr & USART_SR_FE) {
254 /* Break detection if character is null */
255 if (!c) {
256 port->icount.brk++;
257 if (uart_handle_break(port))
258 continue;
259 } else {
260 port->icount.frame++;
261 }
262 }
263
264 sr &= port->read_status_mask;
265
266 if (sr & USART_SR_PE) {
267 flag = TTY_PARITY;
268 } else if (sr & USART_SR_FE) {
269 if (!c)
270 flag = TTY_BREAK;
271 else
272 flag = TTY_FRAME;
273 }
274 }
275
276 if (uart_handle_sysrq_char(port, c))
277 continue;
278 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
279 }
280
281 spin_unlock(&port->lock);
282 tty_flip_buffer_push(tport);
283 spin_lock(&port->lock);
284}
285
286static void stm32_tx_dma_complete(void *arg)
287{
288 struct uart_port *port = arg;
289 struct stm32_port *stm32port = to_stm32_port(port);
290 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
291
292 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
293 stm32port->tx_dma_busy = false;
294
295 /* Let's see if we have pending data to send */
296 stm32_transmit_chars(port);
297}
298
299static void stm32_tx_interrupt_enable(struct uart_port *port)
300{
301 struct stm32_port *stm32_port = to_stm32_port(port);
302 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
303
304 /*
305 * Enables TX FIFO threashold irq when FIFO is enabled,
306 * or TX empty irq when FIFO is disabled
307 */
308 if (stm32_port->fifoen)
309 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
310 else
311 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
312}
313
314static void stm32_tx_interrupt_disable(struct uart_port *port)
315{
316 struct stm32_port *stm32_port = to_stm32_port(port);
317 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
318
319 if (stm32_port->fifoen)
320 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
321 else
322 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
323}
324
325static void stm32_transmit_chars_pio(struct uart_port *port)
326{
327 struct stm32_port *stm32_port = to_stm32_port(port);
328 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
329 struct circ_buf *xmit = &port->state->xmit;
330
331 if (stm32_port->tx_dma_busy) {
332 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
333 stm32_port->tx_dma_busy = false;
334 }
335
336 while (!uart_circ_empty(xmit)) {
337 /* Check that TDR is empty before filling FIFO */
338 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
339 break;
340 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
342 port->icount.tx++;
343 }
344
345 /* rely on TXE irq (mask or unmask) for sending remaining data */
346 if (uart_circ_empty(xmit))
347 stm32_tx_interrupt_disable(port);
348 else
349 stm32_tx_interrupt_enable(port);
350}
351
352static void stm32_transmit_chars_dma(struct uart_port *port)
353{
354 struct stm32_port *stm32port = to_stm32_port(port);
355 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
356 struct circ_buf *xmit = &port->state->xmit;
357 struct dma_async_tx_descriptor *desc = NULL;
358 dma_cookie_t cookie;
359 unsigned int count, i;
360
361 if (stm32port->tx_dma_busy)
362 return;
363
364 stm32port->tx_dma_busy = true;
365
366 count = uart_circ_chars_pending(xmit);
367
368 if (count > TX_BUF_L)
369 count = TX_BUF_L;
370
371 if (xmit->tail < xmit->head) {
372 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
373 } else {
374 size_t one = UART_XMIT_SIZE - xmit->tail;
375 size_t two;
376
377 if (one > count)
378 one = count;
379 two = count - one;
380
381 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
382 if (two)
383 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
384 }
385
386 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
387 stm32port->tx_dma_buf,
388 count,
389 DMA_MEM_TO_DEV,
390 DMA_PREP_INTERRUPT);
391
392 if (!desc) {
393 for (i = count; i > 0; i--)
394 stm32_transmit_chars_pio(port);
395 return;
396 }
397
398 desc->callback = stm32_tx_dma_complete;
399 desc->callback_param = port;
400
401 /* Push current DMA TX transaction in the pending queue */
402 cookie = dmaengine_submit(desc);
403
404 /* Issue pending DMA TX requests */
405 dma_async_issue_pending(stm32port->tx_ch);
406
407 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
408
409 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
410 port->icount.tx += count;
411}
412
413static void stm32_transmit_chars(struct uart_port *port)
414{
415 struct stm32_port *stm32_port = to_stm32_port(port);
416 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
417 struct circ_buf *xmit = &port->state->xmit;
418
419 if (port->x_char) {
420 if (stm32_port->tx_dma_busy)
421 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
422 writel_relaxed(port->x_char, port->membase + ofs->tdr);
423 port->x_char = 0;
424 port->icount.tx++;
425 if (stm32_port->tx_dma_busy)
426 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
427 return;
428 }
429
430 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
431 stm32_tx_interrupt_disable(port);
432 return;
433 }
434
435 if (ofs->icr == UNDEF_REG)
436 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
437 else
438 stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
439
440 if (stm32_port->tx_ch)
441 stm32_transmit_chars_dma(port);
442 else
443 stm32_transmit_chars_pio(port);
444
445 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
446 uart_write_wakeup(port);
447
448 if (uart_circ_empty(xmit))
449 stm32_tx_interrupt_disable(port);
450}
451
452static irqreturn_t stm32_interrupt(int irq, void *ptr)
453{
454 struct uart_port *port = ptr;
455 struct stm32_port *stm32_port = to_stm32_port(port);
456 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
457 u32 sr;
458
459 spin_lock(&port->lock);
460
461 sr = readl_relaxed(port->membase + ofs->isr);
462
463 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
464 writel_relaxed(USART_ICR_RTOCF,
465 port->membase + ofs->icr);
466
467 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
468 writel_relaxed(USART_ICR_WUCF,
469 port->membase + ofs->icr);
470
471 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
472 stm32_receive_chars(port, false);
473
474 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
475 stm32_transmit_chars(port);
476
477 spin_unlock(&port->lock);
478
479 if (stm32_port->rx_ch)
480 return IRQ_WAKE_THREAD;
481 else
482 return IRQ_HANDLED;
483}
484
485static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
486{
487 struct uart_port *port = ptr;
488 struct stm32_port *stm32_port = to_stm32_port(port);
489
490 spin_lock(&port->lock);
491
492 if (stm32_port->rx_ch)
493 stm32_receive_chars(port, true);
494
495 spin_unlock(&port->lock);
496
497 return IRQ_HANDLED;
498}
499
500static unsigned int stm32_tx_empty(struct uart_port *port)
501{
502 struct stm32_port *stm32_port = to_stm32_port(port);
503 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
504
505 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
506}
507
508static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
509{
510 struct stm32_port *stm32_port = to_stm32_port(port);
511 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
512
513 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
514 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
515 else
516 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
517}
518
519static unsigned int stm32_get_mctrl(struct uart_port *port)
520{
521 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
522 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
523}
524
525/* Transmit stop */
526static void stm32_stop_tx(struct uart_port *port)
527{
528 stm32_tx_interrupt_disable(port);
529}
530
531/* There are probably characters waiting to be transmitted. */
532static void stm32_start_tx(struct uart_port *port)
533{
534 struct circ_buf *xmit = &port->state->xmit;
535
536 if (uart_circ_empty(xmit))
537 return;
538
539 stm32_transmit_chars(port);
540}
541
542/* Throttle the remote when input buffer is about to overflow. */
543static void stm32_throttle(struct uart_port *port)
544{
545 struct stm32_port *stm32_port = to_stm32_port(port);
546 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
547 unsigned long flags;
548
549 spin_lock_irqsave(&port->lock, flags);
550 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
551 if (stm32_port->cr3_irq)
552 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
553
554 spin_unlock_irqrestore(&port->lock, flags);
555}
556
557/* Unthrottle the remote, the input buffer can now accept data. */
558static void stm32_unthrottle(struct uart_port *port)
559{
560 struct stm32_port *stm32_port = to_stm32_port(port);
561 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
562 unsigned long flags;
563
564 spin_lock_irqsave(&port->lock, flags);
565 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
566 if (stm32_port->cr3_irq)
567 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
568
569 spin_unlock_irqrestore(&port->lock, flags);
570}
571
572/* Receive stop */
573static void stm32_stop_rx(struct uart_port *port)
574{
575 struct stm32_port *stm32_port = to_stm32_port(port);
576 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
577
578 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
579 if (stm32_port->cr3_irq)
580 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
581
582}
583
584/* Handle breaks - ignored by us */
585static void stm32_break_ctl(struct uart_port *port, int break_state)
586{
587}
588
589static int stm32_startup(struct uart_port *port)
590{
591 struct stm32_port *stm32_port = to_stm32_port(port);
592 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
593 const char *name = to_platform_device(port->dev)->name;
594 u32 val;
595 int ret;
596
597 ret = request_threaded_irq(port->irq, stm32_interrupt,
598 stm32_threaded_interrupt,
599 IRQF_NO_SUSPEND, name, port);
600 if (ret)
601 return ret;
602
603 /* RX FIFO Flush */
604 if (ofs->rqr != UNDEF_REG)
605 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
606
607 /* Tx and RX FIFO configuration */
608 if (stm32_port->fifoen) {
609 val = readl_relaxed(port->membase + ofs->cr3);
610 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
611 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
612 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
613 writel_relaxed(val, port->membase + ofs->cr3);
614 }
615
616 /* RX FIFO enabling */
617 val = stm32_port->cr1_irq | USART_CR1_RE;
618 if (stm32_port->fifoen)
619 val |= USART_CR1_FIFOEN;
620 stm32_set_bits(port, ofs->cr1, val);
621
622 return 0;
623}
624
625static void stm32_shutdown(struct uart_port *port)
626{
627 struct stm32_port *stm32_port = to_stm32_port(port);
628 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
629 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
630 u32 val, isr;
631 int ret;
632
633 val = USART_CR1_TXEIE | USART_CR1_TE;
634 val |= stm32_port->cr1_irq | USART_CR1_RE;
635 val |= BIT(cfg->uart_enable_bit);
636 if (stm32_port->fifoen)
637 val |= USART_CR1_FIFOEN;
638
639 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
640 isr, (isr & USART_SR_TC),
641 10, 100000);
642
643 if (ret)
644 dev_err(port->dev, "transmission complete not set\n");
645
646 stm32_clr_bits(port, ofs->cr1, val);
647
648 free_irq(port->irq, port);
649}
650
651static unsigned int stm32_get_databits(struct ktermios *termios)
652{
653 unsigned int bits;
654
655 tcflag_t cflag = termios->c_cflag;
656
657 switch (cflag & CSIZE) {
658 /*
659 * CSIZE settings are not necessarily supported in hardware.
660 * CSIZE unsupported configurations are handled here to set word length
661 * to 8 bits word as default configuration and to print debug message.
662 */
663 case CS5:
664 bits = 5;
665 break;
666 case CS6:
667 bits = 6;
668 break;
669 case CS7:
670 bits = 7;
671 break;
672 /* default including CS8 */
673 default:
674 bits = 8;
675 break;
676 }
677
678 return bits;
679}
680
681static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
682 struct ktermios *old)
683{
684 struct stm32_port *stm32_port = to_stm32_port(port);
685 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
686 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
687 struct serial_rs485 *rs485conf = &port->rs485;
688 unsigned int baud, bits;
689 u32 usartdiv, mantissa, fraction, oversampling;
690 tcflag_t cflag = termios->c_cflag;
691 u32 cr1, cr2, cr3;
692 unsigned long flags;
693
694 if (!stm32_port->hw_flow_control)
695 cflag &= ~CRTSCTS;
696
697 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
698
699 spin_lock_irqsave(&port->lock, flags);
700
701 /* Stop serial port and reset value */
702 writel_relaxed(0, port->membase + ofs->cr1);
703
704 /* flush RX & TX FIFO */
705 if (ofs->rqr != UNDEF_REG)
706 stm32_set_bits(port, ofs->rqr,
707 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
708
709 cr1 = USART_CR1_TE | USART_CR1_RE;
710 if (stm32_port->fifoen)
711 cr1 |= USART_CR1_FIFOEN;
712 cr2 = 0;
713 cr3 = readl_relaxed(port->membase + ofs->cr3);
714 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
715 | USART_CR3_TXFTCFG_MASK;
716
717 if (cflag & CSTOPB)
718 cr2 |= USART_CR2_STOP_2B;
719
720 bits = stm32_get_databits(termios);
721 stm32_port->rdr_mask = (BIT(bits) - 1);
722
723 if (cflag & PARENB) {
724 bits++;
725 cr1 |= USART_CR1_PCE;
726 }
727
728 /*
729 * Word length configuration:
730 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
731 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
732 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
733 * M0 and M1 already cleared by cr1 initialization.
734 */
735 if (bits == 9)
736 cr1 |= USART_CR1_M0;
737 else if ((bits == 7) && cfg->has_7bits_data)
738 cr1 |= USART_CR1_M1;
739 else if (bits != 8)
740 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
741 , bits);
742
743 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
744 stm32_port->fifoen)) {
745 if (cflag & CSTOPB)
746 bits = bits + 3; /* 1 start bit + 2 stop bits */
747 else
748 bits = bits + 2; /* 1 start bit + 1 stop bit */
749
750 /* RX timeout irq to occur after last stop bit + bits */
751 stm32_port->cr1_irq = USART_CR1_RTOIE;
752 writel_relaxed(bits, port->membase + ofs->rtor);
753 cr2 |= USART_CR2_RTOEN;
754 /* Not using dma, enable fifo threshold irq */
755 if (!stm32_port->rx_ch)
756 stm32_port->cr3_irq = USART_CR3_RXFTIE;
757 }
758
759 cr1 |= stm32_port->cr1_irq;
760 cr3 |= stm32_port->cr3_irq;
761
762 if (cflag & PARODD)
763 cr1 |= USART_CR1_PS;
764
765 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
766 if (cflag & CRTSCTS) {
767 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
768 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
769 }
770
771 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
772
773 /*
774 * The USART supports 16 or 8 times oversampling.
775 * By default we prefer 16 times oversampling, so that the receiver
776 * has a better tolerance to clock deviations.
777 * 8 times oversampling is only used to achieve higher speeds.
778 */
779 if (usartdiv < 16) {
780 oversampling = 8;
781 cr1 |= USART_CR1_OVER8;
782 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
783 } else {
784 oversampling = 16;
785 cr1 &= ~USART_CR1_OVER8;
786 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
787 }
788
789 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
790 fraction = usartdiv % oversampling;
791 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
792
793 uart_update_timeout(port, cflag, baud);
794
795 port->read_status_mask = USART_SR_ORE;
796 if (termios->c_iflag & INPCK)
797 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
798 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
799 port->read_status_mask |= USART_SR_FE;
800
801 /* Characters to ignore */
802 port->ignore_status_mask = 0;
803 if (termios->c_iflag & IGNPAR)
804 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
805 if (termios->c_iflag & IGNBRK) {
806 port->ignore_status_mask |= USART_SR_FE;
807 /*
808 * If we're ignoring parity and break indicators,
809 * ignore overruns too (for real raw support).
810 */
811 if (termios->c_iflag & IGNPAR)
812 port->ignore_status_mask |= USART_SR_ORE;
813 }
814
815 /* Ignore all characters if CREAD is not set */
816 if ((termios->c_cflag & CREAD) == 0)
817 port->ignore_status_mask |= USART_SR_DUMMY_RX;
818
819 if (stm32_port->rx_ch)
820 cr3 |= USART_CR3_DMAR;
821
822 if (rs485conf->flags & SER_RS485_ENABLED) {
823 stm32_config_reg_rs485(&cr1, &cr3,
824 rs485conf->delay_rts_before_send,
825 rs485conf->delay_rts_after_send, baud);
826 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
827 cr3 &= ~USART_CR3_DEP;
828 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
829 } else {
830 cr3 |= USART_CR3_DEP;
831 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
832 }
833
834 } else {
835 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
836 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
837 }
838
839 writel_relaxed(cr3, port->membase + ofs->cr3);
840 writel_relaxed(cr2, port->membase + ofs->cr2);
841 writel_relaxed(cr1, port->membase + ofs->cr1);
842
843 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
844 spin_unlock_irqrestore(&port->lock, flags);
845}
846
847static const char *stm32_type(struct uart_port *port)
848{
849 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
850}
851
852static void stm32_release_port(struct uart_port *port)
853{
854}
855
856static int stm32_request_port(struct uart_port *port)
857{
858 return 0;
859}
860
861static void stm32_config_port(struct uart_port *port, int flags)
862{
863 if (flags & UART_CONFIG_TYPE)
864 port->type = PORT_STM32;
865}
866
867static int
868stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
869{
870 /* No user changeable parameters */
871 return -EINVAL;
872}
873
874static void stm32_pm(struct uart_port *port, unsigned int state,
875 unsigned int oldstate)
876{
877 struct stm32_port *stm32port = container_of(port,
878 struct stm32_port, port);
879 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
880 struct stm32_usart_config *cfg = &stm32port->info->cfg;
881 unsigned long flags = 0;
882
883 switch (state) {
884 case UART_PM_STATE_ON:
885 pm_runtime_get_sync(port->dev);
886 break;
887 case UART_PM_STATE_OFF:
888 spin_lock_irqsave(&port->lock, flags);
889 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
890 spin_unlock_irqrestore(&port->lock, flags);
891 pm_runtime_put_sync(port->dev);
892 break;
893 }
894}
895
896static const struct uart_ops stm32_uart_ops = {
897 .tx_empty = stm32_tx_empty,
898 .set_mctrl = stm32_set_mctrl,
899 .get_mctrl = stm32_get_mctrl,
900 .stop_tx = stm32_stop_tx,
901 .start_tx = stm32_start_tx,
902 .throttle = stm32_throttle,
903 .unthrottle = stm32_unthrottle,
904 .stop_rx = stm32_stop_rx,
905 .break_ctl = stm32_break_ctl,
906 .startup = stm32_startup,
907 .shutdown = stm32_shutdown,
908 .set_termios = stm32_set_termios,
909 .pm = stm32_pm,
910 .type = stm32_type,
911 .release_port = stm32_release_port,
912 .request_port = stm32_request_port,
913 .config_port = stm32_config_port,
914 .verify_port = stm32_verify_port,
915};
916
917static int stm32_init_port(struct stm32_port *stm32port,
918 struct platform_device *pdev)
919{
920 struct uart_port *port = &stm32port->port;
921 struct resource *res;
922 int ret;
923
924 port->iotype = UPIO_MEM;
925 port->flags = UPF_BOOT_AUTOCONF;
926 port->ops = &stm32_uart_ops;
927 port->dev = &pdev->dev;
928 port->fifosize = stm32port->info->cfg.fifosize;
929
930 ret = platform_get_irq(pdev, 0);
931 if (ret <= 0)
932 return ret ? : -ENODEV;
933 port->irq = ret;
934
935 port->rs485_config = stm32_config_rs485;
936
937 stm32_init_rs485(port, pdev);
938
939 if (stm32port->info->cfg.has_wakeup) {
940 stm32port->wakeirq = platform_get_irq(pdev, 1);
941 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
942 return stm32port->wakeirq ? : -ENODEV;
943 }
944
945 stm32port->fifoen = stm32port->info->cfg.has_fifo;
946
947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 port->membase = devm_ioremap_resource(&pdev->dev, res);
949 if (IS_ERR(port->membase))
950 return PTR_ERR(port->membase);
951 port->mapbase = res->start;
952
953 spin_lock_init(&port->lock);
954
955 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
956 if (IS_ERR(stm32port->clk))
957 return PTR_ERR(stm32port->clk);
958
959 /* Ensure that clk rate is correct by enabling the clk */
960 ret = clk_prepare_enable(stm32port->clk);
961 if (ret)
962 return ret;
963
964 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
965 if (!stm32port->port.uartclk) {
966 clk_disable_unprepare(stm32port->clk);
967 ret = -EINVAL;
968 }
969
970 return ret;
971}
972
973static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
974{
975 struct device_node *np = pdev->dev.of_node;
976 int id;
977
978 if (!np)
979 return NULL;
980
981 id = of_alias_get_id(np, "serial");
982 if (id < 0) {
983 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
984 return NULL;
985 }
986
987 if (WARN_ON(id >= STM32_MAX_PORTS))
988 return NULL;
989
990 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
991 "st,hw-flow-ctrl");
992 stm32_ports[id].port.line = id;
993 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
994 stm32_ports[id].cr3_irq = 0;
995 stm32_ports[id].last_res = RX_BUF_L;
996 return &stm32_ports[id];
997}
998
999#ifdef CONFIG_OF
1000static const struct of_device_id stm32_match[] = {
1001 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1002 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1003 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1004 {},
1005};
1006
1007MODULE_DEVICE_TABLE(of, stm32_match);
1008#endif
1009
1010static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
1011 struct platform_device *pdev)
1012{
1013 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1014 struct uart_port *port = &stm32port->port;
1015 struct device *dev = &pdev->dev;
1016 struct dma_slave_config config;
1017 struct dma_async_tx_descriptor *desc = NULL;
1018 dma_cookie_t cookie;
1019 int ret;
1020
1021 /* Request DMA RX channel */
1022 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1023 if (!stm32port->rx_ch) {
1024 dev_info(dev, "rx dma alloc failed\n");
1025 return -ENODEV;
1026 }
1027 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1028 &stm32port->rx_dma_buf,
1029 GFP_KERNEL);
1030 if (!stm32port->rx_buf) {
1031 ret = -ENOMEM;
1032 goto alloc_err;
1033 }
1034
1035 /* Configure DMA channel */
1036 memset(&config, 0, sizeof(config));
1037 config.src_addr = port->mapbase + ofs->rdr;
1038 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1039
1040 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1041 if (ret < 0) {
1042 dev_err(dev, "rx dma channel config failed\n");
1043 ret = -ENODEV;
1044 goto config_err;
1045 }
1046
1047 /* Prepare a DMA cyclic transaction */
1048 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1049 stm32port->rx_dma_buf,
1050 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1051 DMA_PREP_INTERRUPT);
1052 if (!desc) {
1053 dev_err(dev, "rx dma prep cyclic failed\n");
1054 ret = -ENODEV;
1055 goto config_err;
1056 }
1057
1058 /* No callback as dma buffer is drained on usart interrupt */
1059 desc->callback = NULL;
1060 desc->callback_param = NULL;
1061
1062 /* Push current DMA transaction in the pending queue */
1063 cookie = dmaengine_submit(desc);
1064
1065 /* Issue pending DMA requests */
1066 dma_async_issue_pending(stm32port->rx_ch);
1067
1068 return 0;
1069
1070config_err:
1071 dma_free_coherent(&pdev->dev,
1072 RX_BUF_L, stm32port->rx_buf,
1073 stm32port->rx_dma_buf);
1074
1075alloc_err:
1076 dma_release_channel(stm32port->rx_ch);
1077 stm32port->rx_ch = NULL;
1078
1079 return ret;
1080}
1081
1082static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1083 struct platform_device *pdev)
1084{
1085 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1086 struct uart_port *port = &stm32port->port;
1087 struct device *dev = &pdev->dev;
1088 struct dma_slave_config config;
1089 int ret;
1090
1091 stm32port->tx_dma_busy = false;
1092
1093 /* Request DMA TX channel */
1094 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1095 if (!stm32port->tx_ch) {
1096 dev_info(dev, "tx dma alloc failed\n");
1097 return -ENODEV;
1098 }
1099 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1100 &stm32port->tx_dma_buf,
1101 GFP_KERNEL);
1102 if (!stm32port->tx_buf) {
1103 ret = -ENOMEM;
1104 goto alloc_err;
1105 }
1106
1107 /* Configure DMA channel */
1108 memset(&config, 0, sizeof(config));
1109 config.dst_addr = port->mapbase + ofs->tdr;
1110 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1111
1112 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1113 if (ret < 0) {
1114 dev_err(dev, "tx dma channel config failed\n");
1115 ret = -ENODEV;
1116 goto config_err;
1117 }
1118
1119 return 0;
1120
1121config_err:
1122 dma_free_coherent(&pdev->dev,
1123 TX_BUF_L, stm32port->tx_buf,
1124 stm32port->tx_dma_buf);
1125
1126alloc_err:
1127 dma_release_channel(stm32port->tx_ch);
1128 stm32port->tx_ch = NULL;
1129
1130 return ret;
1131}
1132
1133static int stm32_serial_probe(struct platform_device *pdev)
1134{
1135 const struct of_device_id *match;
1136 struct stm32_port *stm32port;
1137 int ret;
1138
1139 stm32port = stm32_of_get_stm32_port(pdev);
1140 if (!stm32port)
1141 return -ENODEV;
1142
1143 match = of_match_device(stm32_match, &pdev->dev);
1144 if (match && match->data)
1145 stm32port->info = (struct stm32_usart_info *)match->data;
1146 else
1147 return -EINVAL;
1148
1149 ret = stm32_init_port(stm32port, pdev);
1150 if (ret)
1151 return ret;
1152
1153 if (stm32port->wakeirq > 0) {
1154 ret = device_init_wakeup(&pdev->dev, true);
1155 if (ret)
1156 goto err_uninit;
1157
1158 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1159 stm32port->wakeirq);
1160 if (ret)
1161 goto err_nowup;
1162
1163 device_set_wakeup_enable(&pdev->dev, false);
1164 }
1165
1166 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1167 if (ret)
1168 goto err_wirq;
1169
1170 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1171 if (ret)
1172 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1173
1174 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1175 if (ret)
1176 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1177
1178 platform_set_drvdata(pdev, &stm32port->port);
1179
1180 pm_runtime_get_noresume(&pdev->dev);
1181 pm_runtime_set_active(&pdev->dev);
1182 pm_runtime_enable(&pdev->dev);
1183 pm_runtime_put_sync(&pdev->dev);
1184
1185 return 0;
1186
1187err_wirq:
1188 if (stm32port->wakeirq > 0)
1189 dev_pm_clear_wake_irq(&pdev->dev);
1190
1191err_nowup:
1192 if (stm32port->wakeirq > 0)
1193 device_init_wakeup(&pdev->dev, false);
1194
1195err_uninit:
1196 clk_disable_unprepare(stm32port->clk);
1197
1198 return ret;
1199}
1200
1201static int stm32_serial_remove(struct platform_device *pdev)
1202{
1203 struct uart_port *port = platform_get_drvdata(pdev);
1204 struct stm32_port *stm32_port = to_stm32_port(port);
1205 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1206 int err;
1207
1208 pm_runtime_get_sync(&pdev->dev);
1209
1210 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1211
1212 if (stm32_port->rx_ch)
1213 dma_release_channel(stm32_port->rx_ch);
1214
1215 if (stm32_port->rx_dma_buf)
1216 dma_free_coherent(&pdev->dev,
1217 RX_BUF_L, stm32_port->rx_buf,
1218 stm32_port->rx_dma_buf);
1219
1220 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1221
1222 if (stm32_port->tx_ch)
1223 dma_release_channel(stm32_port->tx_ch);
1224
1225 if (stm32_port->tx_dma_buf)
1226 dma_free_coherent(&pdev->dev,
1227 TX_BUF_L, stm32_port->tx_buf,
1228 stm32_port->tx_dma_buf);
1229
1230 if (stm32_port->wakeirq > 0) {
1231 dev_pm_clear_wake_irq(&pdev->dev);
1232 device_init_wakeup(&pdev->dev, false);
1233 }
1234
1235 clk_disable_unprepare(stm32_port->clk);
1236
1237 err = uart_remove_one_port(&stm32_usart_driver, port);
1238
1239 pm_runtime_disable(&pdev->dev);
1240 pm_runtime_put_noidle(&pdev->dev);
1241
1242 return err;
1243}
1244
1245
1246#ifdef CONFIG_SERIAL_STM32_CONSOLE
1247static void stm32_console_putchar(struct uart_port *port, int ch)
1248{
1249 struct stm32_port *stm32_port = to_stm32_port(port);
1250 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1251
1252 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1253 cpu_relax();
1254
1255 writel_relaxed(ch, port->membase + ofs->tdr);
1256}
1257
1258static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1259{
1260 struct uart_port *port = &stm32_ports[co->index].port;
1261 struct stm32_port *stm32_port = to_stm32_port(port);
1262 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1263 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1264 unsigned long flags;
1265 u32 old_cr1, new_cr1;
1266 int locked = 1;
1267
1268 local_irq_save(flags);
1269 if (port->sysrq)
1270 locked = 0;
1271 else if (oops_in_progress)
1272 locked = spin_trylock(&port->lock);
1273 else
1274 spin_lock(&port->lock);
1275
1276 /* Save and disable interrupts, enable the transmitter */
1277 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1278 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1279 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1280 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1281
1282 uart_console_write(port, s, cnt, stm32_console_putchar);
1283
1284 /* Restore interrupt state */
1285 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1286
1287 if (locked)
1288 spin_unlock(&port->lock);
1289 local_irq_restore(flags);
1290}
1291
1292static int stm32_console_setup(struct console *co, char *options)
1293{
1294 struct stm32_port *stm32port;
1295 int baud = 9600;
1296 int bits = 8;
1297 int parity = 'n';
1298 int flow = 'n';
1299
1300 if (co->index >= STM32_MAX_PORTS)
1301 return -ENODEV;
1302
1303 stm32port = &stm32_ports[co->index];
1304
1305 /*
1306 * This driver does not support early console initialization
1307 * (use ARM early printk support instead), so we only expect
1308 * this to be called during the uart port registration when the
1309 * driver gets probed and the port should be mapped at that point.
1310 */
1311 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1312 return -ENXIO;
1313
1314 if (options)
1315 uart_parse_options(options, &baud, &parity, &bits, &flow);
1316
1317 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1318}
1319
1320static struct console stm32_console = {
1321 .name = STM32_SERIAL_NAME,
1322 .device = uart_console_device,
1323 .write = stm32_console_write,
1324 .setup = stm32_console_setup,
1325 .flags = CON_PRINTBUFFER,
1326 .index = -1,
1327 .data = &stm32_usart_driver,
1328};
1329
1330#define STM32_SERIAL_CONSOLE (&stm32_console)
1331
1332#else
1333#define STM32_SERIAL_CONSOLE NULL
1334#endif /* CONFIG_SERIAL_STM32_CONSOLE */
1335
1336static struct uart_driver stm32_usart_driver = {
1337 .driver_name = DRIVER_NAME,
1338 .dev_name = STM32_SERIAL_NAME,
1339 .major = 0,
1340 .minor = 0,
1341 .nr = STM32_MAX_PORTS,
1342 .cons = STM32_SERIAL_CONSOLE,
1343};
1344
1345static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port,
1346 bool enable)
1347{
1348 struct stm32_port *stm32_port = to_stm32_port(port);
1349 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1350 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1351 u32 val;
1352
1353 if (stm32_port->wakeirq <= 0)
1354 return;
1355
1356 if (enable) {
1357 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1358 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1359 val = readl_relaxed(port->membase + ofs->cr3);
1360 val &= ~USART_CR3_WUS_MASK;
1361 /* Enable Wake up interrupt from low power on start bit */
1362 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1363 writel_relaxed(val, port->membase + ofs->cr3);
1364 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1365 } else {
1366 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1367 }
1368}
1369
1370static int __maybe_unused stm32_serial_suspend(struct device *dev)
1371{
1372 struct uart_port *port = dev_get_drvdata(dev);
1373
1374 uart_suspend_port(&stm32_usart_driver, port);
1375
1376 if (device_may_wakeup(dev))
1377 stm32_serial_enable_wakeup(port, true);
1378 else
1379 stm32_serial_enable_wakeup(port, false);
1380
1381 pinctrl_pm_select_sleep_state(dev);
1382
1383 return 0;
1384}
1385
1386static int __maybe_unused stm32_serial_resume(struct device *dev)
1387{
1388 struct uart_port *port = dev_get_drvdata(dev);
1389
1390 pinctrl_pm_select_default_state(dev);
1391
1392 if (device_may_wakeup(dev))
1393 stm32_serial_enable_wakeup(port, false);
1394
1395 return uart_resume_port(&stm32_usart_driver, port);
1396}
1397
1398static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev)
1399{
1400 struct uart_port *port = dev_get_drvdata(dev);
1401 struct stm32_port *stm32port = container_of(port,
1402 struct stm32_port, port);
1403
1404 clk_disable_unprepare(stm32port->clk);
1405
1406 return 0;
1407}
1408
1409static int __maybe_unused stm32_serial_runtime_resume(struct device *dev)
1410{
1411 struct uart_port *port = dev_get_drvdata(dev);
1412 struct stm32_port *stm32port = container_of(port,
1413 struct stm32_port, port);
1414
1415 return clk_prepare_enable(stm32port->clk);
1416}
1417
1418static const struct dev_pm_ops stm32_serial_pm_ops = {
1419 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend,
1420 stm32_serial_runtime_resume, NULL)
1421 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1422};
1423
1424static struct platform_driver stm32_serial_driver = {
1425 .probe = stm32_serial_probe,
1426 .remove = stm32_serial_remove,
1427 .driver = {
1428 .name = DRIVER_NAME,
1429 .pm = &stm32_serial_pm_ops,
1430 .of_match_table = of_match_ptr(stm32_match),
1431 },
1432};
1433
1434static int __init usart_init(void)
1435{
1436 static char banner[] __initdata = "STM32 USART driver initialized";
1437 int ret;
1438
1439 pr_info("%s\n", banner);
1440
1441 ret = uart_register_driver(&stm32_usart_driver);
1442 if (ret)
1443 return ret;
1444
1445 ret = platform_driver_register(&stm32_serial_driver);
1446 if (ret)
1447 uart_unregister_driver(&stm32_usart_driver);
1448
1449 return ret;
1450}
1451
1452static void __exit usart_exit(void)
1453{
1454 platform_driver_unregister(&stm32_serial_driver);
1455 uart_unregister_driver(&stm32_usart_driver);
1456}
1457
1458module_init(usart_init);
1459module_exit(usart_exit);
1460
1461MODULE_ALIAS("platform:" DRIVER_NAME);
1462MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1463MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
7 *
8 * Inspired by st-asc.c from STMicroelectronics (c)
9 */
10
11#include <linux/clk.h>
12#include <linux/console.h>
13#include <linux/delay.h>
14#include <linux/dma-direction.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
17#include <linux/io.h>
18#include <linux/iopoll.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/pm_runtime.h>
26#include <linux/pm_wakeirq.h>
27#include <linux/serial_core.h>
28#include <linux/serial.h>
29#include <linux/spinlock.h>
30#include <linux/sysrq.h>
31#include <linux/tty_flip.h>
32#include <linux/tty.h>
33
34#include "serial_mctrl_gpio.h"
35#include "stm32-usart.h"
36
37static void stm32_stop_tx(struct uart_port *port);
38static void stm32_transmit_chars(struct uart_port *port);
39
40static inline struct stm32_port *to_stm32_port(struct uart_port *port)
41{
42 return container_of(port, struct stm32_port, port);
43}
44
45static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
46{
47 u32 val;
48
49 val = readl_relaxed(port->membase + reg);
50 val |= bits;
51 writel_relaxed(val, port->membase + reg);
52}
53
54static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
55{
56 u32 val;
57
58 val = readl_relaxed(port->membase + reg);
59 val &= ~bits;
60 writel_relaxed(val, port->membase + reg);
61}
62
63static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
64 u32 delay_DDE, u32 baud)
65{
66 u32 rs485_deat_dedt;
67 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
68 bool over8;
69
70 *cr3 |= USART_CR3_DEM;
71 over8 = *cr1 & USART_CR1_OVER8;
72
73 if (over8)
74 rs485_deat_dedt = delay_ADE * baud * 8;
75 else
76 rs485_deat_dedt = delay_ADE * baud * 16;
77
78 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
79 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
80 rs485_deat_dedt_max : rs485_deat_dedt;
81 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
82 USART_CR1_DEAT_MASK;
83 *cr1 |= rs485_deat_dedt;
84
85 if (over8)
86 rs485_deat_dedt = delay_DDE * baud * 8;
87 else
88 rs485_deat_dedt = delay_DDE * baud * 16;
89
90 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
91 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
92 rs485_deat_dedt_max : rs485_deat_dedt;
93 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
94 USART_CR1_DEDT_MASK;
95 *cr1 |= rs485_deat_dedt;
96}
97
98static int stm32_config_rs485(struct uart_port *port,
99 struct serial_rs485 *rs485conf)
100{
101 struct stm32_port *stm32_port = to_stm32_port(port);
102 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
103 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
104 u32 usartdiv, baud, cr1, cr3;
105 bool over8;
106
107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
108
109 port->rs485 = *rs485conf;
110
111 rs485conf->flags |= SER_RS485_RX_DURING_TX;
112
113 if (rs485conf->flags & SER_RS485_ENABLED) {
114 cr1 = readl_relaxed(port->membase + ofs->cr1);
115 cr3 = readl_relaxed(port->membase + ofs->cr3);
116 usartdiv = readl_relaxed(port->membase + ofs->brr);
117 usartdiv = usartdiv & GENMASK(15, 0);
118 over8 = cr1 & USART_CR1_OVER8;
119
120 if (over8)
121 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
122 << USART_BRR_04_R_SHIFT;
123
124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
125 stm32_config_reg_rs485(&cr1, &cr3,
126 rs485conf->delay_rts_before_send,
127 rs485conf->delay_rts_after_send, baud);
128
129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
130 cr3 &= ~USART_CR3_DEP;
131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
132 mctrl_gpio_set(stm32_port->gpios,
133 stm32_port->port.mctrl & ~TIOCM_RTS);
134 } else {
135 cr3 |= USART_CR3_DEP;
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
137 mctrl_gpio_set(stm32_port->gpios,
138 stm32_port->port.mctrl | TIOCM_RTS);
139 }
140
141 writel_relaxed(cr3, port->membase + ofs->cr3);
142 writel_relaxed(cr1, port->membase + ofs->cr1);
143 } else {
144 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
145 stm32_clr_bits(port, ofs->cr1,
146 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
147 }
148
149 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
150
151 return 0;
152}
153
154static int stm32_init_rs485(struct uart_port *port,
155 struct platform_device *pdev)
156{
157 struct serial_rs485 *rs485conf = &port->rs485;
158
159 rs485conf->flags = 0;
160 rs485conf->delay_rts_before_send = 0;
161 rs485conf->delay_rts_after_send = 0;
162
163 if (!pdev->dev.of_node)
164 return -ENODEV;
165
166 return uart_get_rs485_mode(port);
167}
168
169static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
170 bool threaded)
171{
172 struct stm32_port *stm32_port = to_stm32_port(port);
173 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
174 enum dma_status status;
175 struct dma_tx_state state;
176
177 *sr = readl_relaxed(port->membase + ofs->isr);
178
179 if (threaded && stm32_port->rx_ch) {
180 status = dmaengine_tx_status(stm32_port->rx_ch,
181 stm32_port->rx_ch->cookie,
182 &state);
183 if ((status == DMA_IN_PROGRESS) &&
184 (*last_res != state.residue))
185 return 1;
186 else
187 return 0;
188 } else if (*sr & USART_SR_RXNE) {
189 return 1;
190 }
191 return 0;
192}
193
194static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
195 int *last_res)
196{
197 struct stm32_port *stm32_port = to_stm32_port(port);
198 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
199 unsigned long c;
200
201 if (stm32_port->rx_ch) {
202 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
203 if ((*last_res) == 0)
204 *last_res = RX_BUF_L;
205 } else {
206 c = readl_relaxed(port->membase + ofs->rdr);
207 /* apply RDR data mask */
208 c &= stm32_port->rdr_mask;
209 }
210
211 return c;
212}
213
214static void stm32_receive_chars(struct uart_port *port, bool threaded)
215{
216 struct tty_port *tport = &port->state->port;
217 struct stm32_port *stm32_port = to_stm32_port(port);
218 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
219 unsigned long c;
220 u32 sr;
221 char flag;
222
223 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
224 pm_wakeup_event(tport->tty->dev, 0);
225
226 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
227 sr |= USART_SR_DUMMY_RX;
228 flag = TTY_NORMAL;
229
230 /*
231 * Status bits has to be cleared before reading the RDR:
232 * In FIFO mode, reading the RDR will pop the next data
233 * (if any) along with its status bits into the SR.
234 * Not doing so leads to misalignement between RDR and SR,
235 * and clear status bits of the next rx data.
236 *
237 * Clear errors flags for stm32f7 and stm32h7 compatible
238 * devices. On stm32f4 compatible devices, the error bit is
239 * cleared by the sequence [read SR - read DR].
240 */
241 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
242 writel_relaxed(sr & USART_SR_ERR_MASK,
243 port->membase + ofs->icr);
244
245 c = stm32_get_char(port, &sr, &stm32_port->last_res);
246 port->icount.rx++;
247 if (sr & USART_SR_ERR_MASK) {
248 if (sr & USART_SR_ORE) {
249 port->icount.overrun++;
250 } else if (sr & USART_SR_PE) {
251 port->icount.parity++;
252 } else if (sr & USART_SR_FE) {
253 /* Break detection if character is null */
254 if (!c) {
255 port->icount.brk++;
256 if (uart_handle_break(port))
257 continue;
258 } else {
259 port->icount.frame++;
260 }
261 }
262
263 sr &= port->read_status_mask;
264
265 if (sr & USART_SR_PE) {
266 flag = TTY_PARITY;
267 } else if (sr & USART_SR_FE) {
268 if (!c)
269 flag = TTY_BREAK;
270 else
271 flag = TTY_FRAME;
272 }
273 }
274
275 if (uart_handle_sysrq_char(port, c))
276 continue;
277 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
278 }
279
280 spin_unlock(&port->lock);
281 tty_flip_buffer_push(tport);
282 spin_lock(&port->lock);
283}
284
285static void stm32_tx_dma_complete(void *arg)
286{
287 struct uart_port *port = arg;
288 struct stm32_port *stm32port = to_stm32_port(port);
289 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
290
291 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292 stm32port->tx_dma_busy = false;
293
294 /* Let's see if we have pending data to send */
295 stm32_transmit_chars(port);
296}
297
298static void stm32_tx_interrupt_enable(struct uart_port *port)
299{
300 struct stm32_port *stm32_port = to_stm32_port(port);
301 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
302
303 /*
304 * Enables TX FIFO threashold irq when FIFO is enabled,
305 * or TX empty irq when FIFO is disabled
306 */
307 if (stm32_port->fifoen)
308 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
309 else
310 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
311}
312
313static void stm32_tx_interrupt_disable(struct uart_port *port)
314{
315 struct stm32_port *stm32_port = to_stm32_port(port);
316 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
317
318 if (stm32_port->fifoen)
319 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
320 else
321 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
322}
323
324static void stm32_transmit_chars_pio(struct uart_port *port)
325{
326 struct stm32_port *stm32_port = to_stm32_port(port);
327 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
328 struct circ_buf *xmit = &port->state->xmit;
329
330 if (stm32_port->tx_dma_busy) {
331 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
332 stm32_port->tx_dma_busy = false;
333 }
334
335 while (!uart_circ_empty(xmit)) {
336 /* Check that TDR is empty before filling FIFO */
337 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
338 break;
339 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
340 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
341 port->icount.tx++;
342 }
343
344 /* rely on TXE irq (mask or unmask) for sending remaining data */
345 if (uart_circ_empty(xmit))
346 stm32_tx_interrupt_disable(port);
347 else
348 stm32_tx_interrupt_enable(port);
349}
350
351static void stm32_transmit_chars_dma(struct uart_port *port)
352{
353 struct stm32_port *stm32port = to_stm32_port(port);
354 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
355 struct circ_buf *xmit = &port->state->xmit;
356 struct dma_async_tx_descriptor *desc = NULL;
357 dma_cookie_t cookie;
358 unsigned int count, i;
359
360 if (stm32port->tx_dma_busy)
361 return;
362
363 stm32port->tx_dma_busy = true;
364
365 count = uart_circ_chars_pending(xmit);
366
367 if (count > TX_BUF_L)
368 count = TX_BUF_L;
369
370 if (xmit->tail < xmit->head) {
371 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
372 } else {
373 size_t one = UART_XMIT_SIZE - xmit->tail;
374 size_t two;
375
376 if (one > count)
377 one = count;
378 two = count - one;
379
380 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
381 if (two)
382 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
383 }
384
385 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
386 stm32port->tx_dma_buf,
387 count,
388 DMA_MEM_TO_DEV,
389 DMA_PREP_INTERRUPT);
390
391 if (!desc) {
392 for (i = count; i > 0; i--)
393 stm32_transmit_chars_pio(port);
394 return;
395 }
396
397 desc->callback = stm32_tx_dma_complete;
398 desc->callback_param = port;
399
400 /* Push current DMA TX transaction in the pending queue */
401 cookie = dmaengine_submit(desc);
402
403 /* Issue pending DMA TX requests */
404 dma_async_issue_pending(stm32port->tx_ch);
405
406 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
407
408 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
409 port->icount.tx += count;
410}
411
412static void stm32_transmit_chars(struct uart_port *port)
413{
414 struct stm32_port *stm32_port = to_stm32_port(port);
415 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
416 struct circ_buf *xmit = &port->state->xmit;
417
418 if (port->x_char) {
419 if (stm32_port->tx_dma_busy)
420 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
421 writel_relaxed(port->x_char, port->membase + ofs->tdr);
422 port->x_char = 0;
423 port->icount.tx++;
424 if (stm32_port->tx_dma_busy)
425 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
426 return;
427 }
428
429 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
430 stm32_tx_interrupt_disable(port);
431 return;
432 }
433
434 if (ofs->icr == UNDEF_REG)
435 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
436 else
437 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
438
439 if (stm32_port->tx_ch)
440 stm32_transmit_chars_dma(port);
441 else
442 stm32_transmit_chars_pio(port);
443
444 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
445 uart_write_wakeup(port);
446
447 if (uart_circ_empty(xmit))
448 stm32_tx_interrupt_disable(port);
449}
450
451static irqreturn_t stm32_interrupt(int irq, void *ptr)
452{
453 struct uart_port *port = ptr;
454 struct stm32_port *stm32_port = to_stm32_port(port);
455 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
456 u32 sr;
457
458 spin_lock(&port->lock);
459
460 sr = readl_relaxed(port->membase + ofs->isr);
461
462 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG)
463 writel_relaxed(USART_ICR_RTOCF,
464 port->membase + ofs->icr);
465
466 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
467 writel_relaxed(USART_ICR_WUCF,
468 port->membase + ofs->icr);
469
470 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
471 stm32_receive_chars(port, false);
472
473 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
474 stm32_transmit_chars(port);
475
476 spin_unlock(&port->lock);
477
478 if (stm32_port->rx_ch)
479 return IRQ_WAKE_THREAD;
480 else
481 return IRQ_HANDLED;
482}
483
484static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
485{
486 struct uart_port *port = ptr;
487 struct stm32_port *stm32_port = to_stm32_port(port);
488
489 spin_lock(&port->lock);
490
491 if (stm32_port->rx_ch)
492 stm32_receive_chars(port, true);
493
494 spin_unlock(&port->lock);
495
496 return IRQ_HANDLED;
497}
498
499static unsigned int stm32_tx_empty(struct uart_port *port)
500{
501 struct stm32_port *stm32_port = to_stm32_port(port);
502 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
503
504 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
505}
506
507static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
508{
509 struct stm32_port *stm32_port = to_stm32_port(port);
510 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
511
512 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
513 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
514 else
515 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
516
517 mctrl_gpio_set(stm32_port->gpios, mctrl);
518}
519
520static unsigned int stm32_get_mctrl(struct uart_port *port)
521{
522 struct stm32_port *stm32_port = to_stm32_port(port);
523 unsigned int ret;
524
525 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
526 ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
527
528 return mctrl_gpio_get(stm32_port->gpios, &ret);
529}
530
531static void stm32_enable_ms(struct uart_port *port)
532{
533 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
534}
535
536static void stm32_disable_ms(struct uart_port *port)
537{
538 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
539}
540
541/* Transmit stop */
542static void stm32_stop_tx(struct uart_port *port)
543{
544 stm32_tx_interrupt_disable(port);
545}
546
547/* There are probably characters waiting to be transmitted. */
548static void stm32_start_tx(struct uart_port *port)
549{
550 struct circ_buf *xmit = &port->state->xmit;
551
552 if (uart_circ_empty(xmit))
553 return;
554
555 stm32_transmit_chars(port);
556}
557
558/* Throttle the remote when input buffer is about to overflow. */
559static void stm32_throttle(struct uart_port *port)
560{
561 struct stm32_port *stm32_port = to_stm32_port(port);
562 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
563 unsigned long flags;
564
565 spin_lock_irqsave(&port->lock, flags);
566 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
567 if (stm32_port->cr3_irq)
568 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
569
570 spin_unlock_irqrestore(&port->lock, flags);
571}
572
573/* Unthrottle the remote, the input buffer can now accept data. */
574static void stm32_unthrottle(struct uart_port *port)
575{
576 struct stm32_port *stm32_port = to_stm32_port(port);
577 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
578 unsigned long flags;
579
580 spin_lock_irqsave(&port->lock, flags);
581 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
582 if (stm32_port->cr3_irq)
583 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
584
585 spin_unlock_irqrestore(&port->lock, flags);
586}
587
588/* Receive stop */
589static void stm32_stop_rx(struct uart_port *port)
590{
591 struct stm32_port *stm32_port = to_stm32_port(port);
592 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
593
594 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
595 if (stm32_port->cr3_irq)
596 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
597
598}
599
600/* Handle breaks - ignored by us */
601static void stm32_break_ctl(struct uart_port *port, int break_state)
602{
603}
604
605static int stm32_startup(struct uart_port *port)
606{
607 struct stm32_port *stm32_port = to_stm32_port(port);
608 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
609 const char *name = to_platform_device(port->dev)->name;
610 u32 val;
611 int ret;
612
613 ret = request_threaded_irq(port->irq, stm32_interrupt,
614 stm32_threaded_interrupt,
615 IRQF_NO_SUSPEND, name, port);
616 if (ret)
617 return ret;
618
619 /* RX FIFO Flush */
620 if (ofs->rqr != UNDEF_REG)
621 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
622
623 /* Tx and RX FIFO configuration */
624 if (stm32_port->fifoen) {
625 val = readl_relaxed(port->membase + ofs->cr3);
626 val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
627 val |= USART_CR3_TXFTCFG_HALF << USART_CR3_TXFTCFG_SHIFT;
628 val |= USART_CR3_RXFTCFG_HALF << USART_CR3_RXFTCFG_SHIFT;
629 writel_relaxed(val, port->membase + ofs->cr3);
630 }
631
632 /* RX FIFO enabling */
633 val = stm32_port->cr1_irq | USART_CR1_RE;
634 if (stm32_port->fifoen)
635 val |= USART_CR1_FIFOEN;
636 stm32_set_bits(port, ofs->cr1, val);
637
638 return 0;
639}
640
641static void stm32_shutdown(struct uart_port *port)
642{
643 struct stm32_port *stm32_port = to_stm32_port(port);
644 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
645 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
646 u32 val, isr;
647 int ret;
648
649 /* Disable modem control interrupts */
650 stm32_disable_ms(port);
651
652 val = USART_CR1_TXEIE | USART_CR1_TE;
653 val |= stm32_port->cr1_irq | USART_CR1_RE;
654 val |= BIT(cfg->uart_enable_bit);
655 if (stm32_port->fifoen)
656 val |= USART_CR1_FIFOEN;
657
658 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
659 isr, (isr & USART_SR_TC),
660 10, 100000);
661
662 if (ret)
663 dev_err(port->dev, "transmission complete not set\n");
664
665 stm32_clr_bits(port, ofs->cr1, val);
666
667 free_irq(port->irq, port);
668}
669
670static unsigned int stm32_get_databits(struct ktermios *termios)
671{
672 unsigned int bits;
673
674 tcflag_t cflag = termios->c_cflag;
675
676 switch (cflag & CSIZE) {
677 /*
678 * CSIZE settings are not necessarily supported in hardware.
679 * CSIZE unsupported configurations are handled here to set word length
680 * to 8 bits word as default configuration and to print debug message.
681 */
682 case CS5:
683 bits = 5;
684 break;
685 case CS6:
686 bits = 6;
687 break;
688 case CS7:
689 bits = 7;
690 break;
691 /* default including CS8 */
692 default:
693 bits = 8;
694 break;
695 }
696
697 return bits;
698}
699
700static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
701 struct ktermios *old)
702{
703 struct stm32_port *stm32_port = to_stm32_port(port);
704 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
705 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
706 struct serial_rs485 *rs485conf = &port->rs485;
707 unsigned int baud, bits;
708 u32 usartdiv, mantissa, fraction, oversampling;
709 tcflag_t cflag = termios->c_cflag;
710 u32 cr1, cr2, cr3;
711 unsigned long flags;
712
713 if (!stm32_port->hw_flow_control)
714 cflag &= ~CRTSCTS;
715
716 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
717
718 spin_lock_irqsave(&port->lock, flags);
719
720 /* Stop serial port and reset value */
721 writel_relaxed(0, port->membase + ofs->cr1);
722
723 /* flush RX & TX FIFO */
724 if (ofs->rqr != UNDEF_REG)
725 stm32_set_bits(port, ofs->rqr,
726 USART_RQR_TXFRQ | USART_RQR_RXFRQ);
727
728 cr1 = USART_CR1_TE | USART_CR1_RE;
729 if (stm32_port->fifoen)
730 cr1 |= USART_CR1_FIFOEN;
731 cr2 = 0;
732 cr3 = readl_relaxed(port->membase + ofs->cr3);
733 cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTCFG_MASK | USART_CR3_RXFTIE
734 | USART_CR3_TXFTCFG_MASK;
735
736 if (cflag & CSTOPB)
737 cr2 |= USART_CR2_STOP_2B;
738
739 bits = stm32_get_databits(termios);
740 stm32_port->rdr_mask = (BIT(bits) - 1);
741
742 if (cflag & PARENB) {
743 bits++;
744 cr1 |= USART_CR1_PCE;
745 }
746
747 /*
748 * Word length configuration:
749 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
750 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
751 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
752 * M0 and M1 already cleared by cr1 initialization.
753 */
754 if (bits == 9)
755 cr1 |= USART_CR1_M0;
756 else if ((bits == 7) && cfg->has_7bits_data)
757 cr1 |= USART_CR1_M1;
758 else if (bits != 8)
759 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
760 , bits);
761
762 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
763 stm32_port->fifoen)) {
764 if (cflag & CSTOPB)
765 bits = bits + 3; /* 1 start bit + 2 stop bits */
766 else
767 bits = bits + 2; /* 1 start bit + 1 stop bit */
768
769 /* RX timeout irq to occur after last stop bit + bits */
770 stm32_port->cr1_irq = USART_CR1_RTOIE;
771 writel_relaxed(bits, port->membase + ofs->rtor);
772 cr2 |= USART_CR2_RTOEN;
773 /* Not using dma, enable fifo threshold irq */
774 if (!stm32_port->rx_ch)
775 stm32_port->cr3_irq = USART_CR3_RXFTIE;
776 }
777
778 cr1 |= stm32_port->cr1_irq;
779 cr3 |= stm32_port->cr3_irq;
780
781 if (cflag & PARODD)
782 cr1 |= USART_CR1_PS;
783
784 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
785 if (cflag & CRTSCTS) {
786 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
787 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
788 }
789
790 /* Handle modem control interrupts */
791 if (UART_ENABLE_MS(port, termios->c_cflag))
792 stm32_enable_ms(port);
793 else
794 stm32_disable_ms(port);
795
796 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
797
798 /*
799 * The USART supports 16 or 8 times oversampling.
800 * By default we prefer 16 times oversampling, so that the receiver
801 * has a better tolerance to clock deviations.
802 * 8 times oversampling is only used to achieve higher speeds.
803 */
804 if (usartdiv < 16) {
805 oversampling = 8;
806 cr1 |= USART_CR1_OVER8;
807 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
808 } else {
809 oversampling = 16;
810 cr1 &= ~USART_CR1_OVER8;
811 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
812 }
813
814 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
815 fraction = usartdiv % oversampling;
816 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
817
818 uart_update_timeout(port, cflag, baud);
819
820 port->read_status_mask = USART_SR_ORE;
821 if (termios->c_iflag & INPCK)
822 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
823 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
824 port->read_status_mask |= USART_SR_FE;
825
826 /* Characters to ignore */
827 port->ignore_status_mask = 0;
828 if (termios->c_iflag & IGNPAR)
829 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
830 if (termios->c_iflag & IGNBRK) {
831 port->ignore_status_mask |= USART_SR_FE;
832 /*
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too (for real raw support).
835 */
836 if (termios->c_iflag & IGNPAR)
837 port->ignore_status_mask |= USART_SR_ORE;
838 }
839
840 /* Ignore all characters if CREAD is not set */
841 if ((termios->c_cflag & CREAD) == 0)
842 port->ignore_status_mask |= USART_SR_DUMMY_RX;
843
844 if (stm32_port->rx_ch)
845 cr3 |= USART_CR3_DMAR;
846
847 if (rs485conf->flags & SER_RS485_ENABLED) {
848 stm32_config_reg_rs485(&cr1, &cr3,
849 rs485conf->delay_rts_before_send,
850 rs485conf->delay_rts_after_send, baud);
851 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
852 cr3 &= ~USART_CR3_DEP;
853 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
854 mctrl_gpio_set(stm32_port->gpios,
855 stm32_port->port.mctrl & ~TIOCM_RTS);
856 } else {
857 cr3 |= USART_CR3_DEP;
858 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
859 mctrl_gpio_set(stm32_port->gpios,
860 stm32_port->port.mctrl | TIOCM_RTS);
861 }
862
863 } else {
864 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
865 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
866 }
867
868 writel_relaxed(cr3, port->membase + ofs->cr3);
869 writel_relaxed(cr2, port->membase + ofs->cr2);
870 writel_relaxed(cr1, port->membase + ofs->cr1);
871
872 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
873 spin_unlock_irqrestore(&port->lock, flags);
874}
875
876static const char *stm32_type(struct uart_port *port)
877{
878 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
879}
880
881static void stm32_release_port(struct uart_port *port)
882{
883}
884
885static int stm32_request_port(struct uart_port *port)
886{
887 return 0;
888}
889
890static void stm32_config_port(struct uart_port *port, int flags)
891{
892 if (flags & UART_CONFIG_TYPE)
893 port->type = PORT_STM32;
894}
895
896static int
897stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
898{
899 /* No user changeable parameters */
900 return -EINVAL;
901}
902
903static void stm32_pm(struct uart_port *port, unsigned int state,
904 unsigned int oldstate)
905{
906 struct stm32_port *stm32port = container_of(port,
907 struct stm32_port, port);
908 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
909 struct stm32_usart_config *cfg = &stm32port->info->cfg;
910 unsigned long flags = 0;
911
912 switch (state) {
913 case UART_PM_STATE_ON:
914 pm_runtime_get_sync(port->dev);
915 break;
916 case UART_PM_STATE_OFF:
917 spin_lock_irqsave(&port->lock, flags);
918 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
919 spin_unlock_irqrestore(&port->lock, flags);
920 pm_runtime_put_sync(port->dev);
921 break;
922 }
923}
924
925static const struct uart_ops stm32_uart_ops = {
926 .tx_empty = stm32_tx_empty,
927 .set_mctrl = stm32_set_mctrl,
928 .get_mctrl = stm32_get_mctrl,
929 .stop_tx = stm32_stop_tx,
930 .start_tx = stm32_start_tx,
931 .throttle = stm32_throttle,
932 .unthrottle = stm32_unthrottle,
933 .stop_rx = stm32_stop_rx,
934 .enable_ms = stm32_enable_ms,
935 .break_ctl = stm32_break_ctl,
936 .startup = stm32_startup,
937 .shutdown = stm32_shutdown,
938 .set_termios = stm32_set_termios,
939 .pm = stm32_pm,
940 .type = stm32_type,
941 .release_port = stm32_release_port,
942 .request_port = stm32_request_port,
943 .config_port = stm32_config_port,
944 .verify_port = stm32_verify_port,
945};
946
947static int stm32_init_port(struct stm32_port *stm32port,
948 struct platform_device *pdev)
949{
950 struct uart_port *port = &stm32port->port;
951 struct resource *res;
952 int ret;
953
954 port->iotype = UPIO_MEM;
955 port->flags = UPF_BOOT_AUTOCONF;
956 port->ops = &stm32_uart_ops;
957 port->dev = &pdev->dev;
958 port->fifosize = stm32port->info->cfg.fifosize;
959 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
960
961 ret = platform_get_irq(pdev, 0);
962 if (ret <= 0)
963 return ret ? : -ENODEV;
964 port->irq = ret;
965
966 port->rs485_config = stm32_config_rs485;
967
968 ret = stm32_init_rs485(port, pdev);
969 if (ret)
970 return ret;
971
972 if (stm32port->info->cfg.has_wakeup) {
973 stm32port->wakeirq = platform_get_irq_optional(pdev, 1);
974 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO)
975 return stm32port->wakeirq ? : -ENODEV;
976 }
977
978 stm32port->fifoen = stm32port->info->cfg.has_fifo;
979
980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
981 port->membase = devm_ioremap_resource(&pdev->dev, res);
982 if (IS_ERR(port->membase))
983 return PTR_ERR(port->membase);
984 port->mapbase = res->start;
985
986 spin_lock_init(&port->lock);
987
988 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
989 if (IS_ERR(stm32port->clk))
990 return PTR_ERR(stm32port->clk);
991
992 /* Ensure that clk rate is correct by enabling the clk */
993 ret = clk_prepare_enable(stm32port->clk);
994 if (ret)
995 return ret;
996
997 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
998 if (!stm32port->port.uartclk) {
999 ret = -EINVAL;
1000 goto err_clk;
1001 }
1002
1003 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1004 if (IS_ERR(stm32port->gpios)) {
1005 ret = PTR_ERR(stm32port->gpios);
1006 goto err_clk;
1007 }
1008
1009 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */
1010 if (stm32port->hw_flow_control) {
1011 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1012 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1013 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1014 ret = -EINVAL;
1015 goto err_clk;
1016 }
1017 }
1018
1019 return ret;
1020
1021err_clk:
1022 clk_disable_unprepare(stm32port->clk);
1023
1024 return ret;
1025}
1026
1027static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
1028{
1029 struct device_node *np = pdev->dev.of_node;
1030 int id;
1031
1032 if (!np)
1033 return NULL;
1034
1035 id = of_alias_get_id(np, "serial");
1036 if (id < 0) {
1037 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1038 return NULL;
1039 }
1040
1041 if (WARN_ON(id >= STM32_MAX_PORTS))
1042 return NULL;
1043
1044 stm32_ports[id].hw_flow_control =
1045 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1046 of_property_read_bool (np, "uart-has-rtscts");
1047 stm32_ports[id].port.line = id;
1048 stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1049 stm32_ports[id].cr3_irq = 0;
1050 stm32_ports[id].last_res = RX_BUF_L;
1051 return &stm32_ports[id];
1052}
1053
1054#ifdef CONFIG_OF
1055static const struct of_device_id stm32_match[] = {
1056 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1057 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1058 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1059 {},
1060};
1061
1062MODULE_DEVICE_TABLE(of, stm32_match);
1063#endif
1064
1065static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
1066 struct platform_device *pdev)
1067{
1068 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1069 struct uart_port *port = &stm32port->port;
1070 struct device *dev = &pdev->dev;
1071 struct dma_slave_config config;
1072 struct dma_async_tx_descriptor *desc = NULL;
1073 dma_cookie_t cookie;
1074 int ret;
1075
1076 /* Request DMA RX channel */
1077 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
1078 if (!stm32port->rx_ch) {
1079 dev_info(dev, "rx dma alloc failed\n");
1080 return -ENODEV;
1081 }
1082 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
1083 &stm32port->rx_dma_buf,
1084 GFP_KERNEL);
1085 if (!stm32port->rx_buf) {
1086 ret = -ENOMEM;
1087 goto alloc_err;
1088 }
1089
1090 /* Configure DMA channel */
1091 memset(&config, 0, sizeof(config));
1092 config.src_addr = port->mapbase + ofs->rdr;
1093 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1094
1095 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1096 if (ret < 0) {
1097 dev_err(dev, "rx dma channel config failed\n");
1098 ret = -ENODEV;
1099 goto config_err;
1100 }
1101
1102 /* Prepare a DMA cyclic transaction */
1103 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
1104 stm32port->rx_dma_buf,
1105 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
1106 DMA_PREP_INTERRUPT);
1107 if (!desc) {
1108 dev_err(dev, "rx dma prep cyclic failed\n");
1109 ret = -ENODEV;
1110 goto config_err;
1111 }
1112
1113 /* No callback as dma buffer is drained on usart interrupt */
1114 desc->callback = NULL;
1115 desc->callback_param = NULL;
1116
1117 /* Push current DMA transaction in the pending queue */
1118 cookie = dmaengine_submit(desc);
1119
1120 /* Issue pending DMA requests */
1121 dma_async_issue_pending(stm32port->rx_ch);
1122
1123 return 0;
1124
1125config_err:
1126 dma_free_coherent(&pdev->dev,
1127 RX_BUF_L, stm32port->rx_buf,
1128 stm32port->rx_dma_buf);
1129
1130alloc_err:
1131 dma_release_channel(stm32port->rx_ch);
1132 stm32port->rx_ch = NULL;
1133
1134 return ret;
1135}
1136
1137static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1138 struct platform_device *pdev)
1139{
1140 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1141 struct uart_port *port = &stm32port->port;
1142 struct device *dev = &pdev->dev;
1143 struct dma_slave_config config;
1144 int ret;
1145
1146 stm32port->tx_dma_busy = false;
1147
1148 /* Request DMA TX channel */
1149 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1150 if (!stm32port->tx_ch) {
1151 dev_info(dev, "tx dma alloc failed\n");
1152 return -ENODEV;
1153 }
1154 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1155 &stm32port->tx_dma_buf,
1156 GFP_KERNEL);
1157 if (!stm32port->tx_buf) {
1158 ret = -ENOMEM;
1159 goto alloc_err;
1160 }
1161
1162 /* Configure DMA channel */
1163 memset(&config, 0, sizeof(config));
1164 config.dst_addr = port->mapbase + ofs->tdr;
1165 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1166
1167 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1168 if (ret < 0) {
1169 dev_err(dev, "tx dma channel config failed\n");
1170 ret = -ENODEV;
1171 goto config_err;
1172 }
1173
1174 return 0;
1175
1176config_err:
1177 dma_free_coherent(&pdev->dev,
1178 TX_BUF_L, stm32port->tx_buf,
1179 stm32port->tx_dma_buf);
1180
1181alloc_err:
1182 dma_release_channel(stm32port->tx_ch);
1183 stm32port->tx_ch = NULL;
1184
1185 return ret;
1186}
1187
1188static int stm32_serial_probe(struct platform_device *pdev)
1189{
1190 const struct of_device_id *match;
1191 struct stm32_port *stm32port;
1192 int ret;
1193
1194 stm32port = stm32_of_get_stm32_port(pdev);
1195 if (!stm32port)
1196 return -ENODEV;
1197
1198 match = of_match_device(stm32_match, &pdev->dev);
1199 if (match && match->data)
1200 stm32port->info = (struct stm32_usart_info *)match->data;
1201 else
1202 return -EINVAL;
1203
1204 ret = stm32_init_port(stm32port, pdev);
1205 if (ret)
1206 return ret;
1207
1208 if (stm32port->wakeirq > 0) {
1209 ret = device_init_wakeup(&pdev->dev, true);
1210 if (ret)
1211 goto err_uninit;
1212
1213 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1214 stm32port->wakeirq);
1215 if (ret)
1216 goto err_nowup;
1217
1218 device_set_wakeup_enable(&pdev->dev, false);
1219 }
1220
1221 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1222 if (ret)
1223 goto err_wirq;
1224
1225 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1226 if (ret)
1227 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1228
1229 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1230 if (ret)
1231 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1232
1233 platform_set_drvdata(pdev, &stm32port->port);
1234
1235 pm_runtime_get_noresume(&pdev->dev);
1236 pm_runtime_set_active(&pdev->dev);
1237 pm_runtime_enable(&pdev->dev);
1238 pm_runtime_put_sync(&pdev->dev);
1239
1240 return 0;
1241
1242err_wirq:
1243 if (stm32port->wakeirq > 0)
1244 dev_pm_clear_wake_irq(&pdev->dev);
1245
1246err_nowup:
1247 if (stm32port->wakeirq > 0)
1248 device_init_wakeup(&pdev->dev, false);
1249
1250err_uninit:
1251 clk_disable_unprepare(stm32port->clk);
1252
1253 return ret;
1254}
1255
1256static int stm32_serial_remove(struct platform_device *pdev)
1257{
1258 struct uart_port *port = platform_get_drvdata(pdev);
1259 struct stm32_port *stm32_port = to_stm32_port(port);
1260 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1261 int err;
1262
1263 pm_runtime_get_sync(&pdev->dev);
1264
1265 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1266
1267 if (stm32_port->rx_ch)
1268 dma_release_channel(stm32_port->rx_ch);
1269
1270 if (stm32_port->rx_dma_buf)
1271 dma_free_coherent(&pdev->dev,
1272 RX_BUF_L, stm32_port->rx_buf,
1273 stm32_port->rx_dma_buf);
1274
1275 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1276
1277 if (stm32_port->tx_ch)
1278 dma_release_channel(stm32_port->tx_ch);
1279
1280 if (stm32_port->tx_dma_buf)
1281 dma_free_coherent(&pdev->dev,
1282 TX_BUF_L, stm32_port->tx_buf,
1283 stm32_port->tx_dma_buf);
1284
1285 if (stm32_port->wakeirq > 0) {
1286 dev_pm_clear_wake_irq(&pdev->dev);
1287 device_init_wakeup(&pdev->dev, false);
1288 }
1289
1290 clk_disable_unprepare(stm32_port->clk);
1291
1292 err = uart_remove_one_port(&stm32_usart_driver, port);
1293
1294 pm_runtime_disable(&pdev->dev);
1295 pm_runtime_put_noidle(&pdev->dev);
1296
1297 return err;
1298}
1299
1300
1301#ifdef CONFIG_SERIAL_STM32_CONSOLE
1302static void stm32_console_putchar(struct uart_port *port, int ch)
1303{
1304 struct stm32_port *stm32_port = to_stm32_port(port);
1305 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1306
1307 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1308 cpu_relax();
1309
1310 writel_relaxed(ch, port->membase + ofs->tdr);
1311}
1312
1313static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1314{
1315 struct uart_port *port = &stm32_ports[co->index].port;
1316 struct stm32_port *stm32_port = to_stm32_port(port);
1317 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1318 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1319 unsigned long flags;
1320 u32 old_cr1, new_cr1;
1321 int locked = 1;
1322
1323 local_irq_save(flags);
1324 if (port->sysrq)
1325 locked = 0;
1326 else if (oops_in_progress)
1327 locked = spin_trylock(&port->lock);
1328 else
1329 spin_lock(&port->lock);
1330
1331 /* Save and disable interrupts, enable the transmitter */
1332 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1333 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1334 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1335 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1336
1337 uart_console_write(port, s, cnt, stm32_console_putchar);
1338
1339 /* Restore interrupt state */
1340 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1341
1342 if (locked)
1343 spin_unlock(&port->lock);
1344 local_irq_restore(flags);
1345}
1346
1347static int stm32_console_setup(struct console *co, char *options)
1348{
1349 struct stm32_port *stm32port;
1350 int baud = 9600;
1351 int bits = 8;
1352 int parity = 'n';
1353 int flow = 'n';
1354
1355 if (co->index >= STM32_MAX_PORTS)
1356 return -ENODEV;
1357
1358 stm32port = &stm32_ports[co->index];
1359
1360 /*
1361 * This driver does not support early console initialization
1362 * (use ARM early printk support instead), so we only expect
1363 * this to be called during the uart port registration when the
1364 * driver gets probed and the port should be mapped at that point.
1365 */
1366 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1367 return -ENXIO;
1368
1369 if (options)
1370 uart_parse_options(options, &baud, &parity, &bits, &flow);
1371
1372 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1373}
1374
1375static struct console stm32_console = {
1376 .name = STM32_SERIAL_NAME,
1377 .device = uart_console_device,
1378 .write = stm32_console_write,
1379 .setup = stm32_console_setup,
1380 .flags = CON_PRINTBUFFER,
1381 .index = -1,
1382 .data = &stm32_usart_driver,
1383};
1384
1385#define STM32_SERIAL_CONSOLE (&stm32_console)
1386
1387#else
1388#define STM32_SERIAL_CONSOLE NULL
1389#endif /* CONFIG_SERIAL_STM32_CONSOLE */
1390
1391static struct uart_driver stm32_usart_driver = {
1392 .driver_name = DRIVER_NAME,
1393 .dev_name = STM32_SERIAL_NAME,
1394 .major = 0,
1395 .minor = 0,
1396 .nr = STM32_MAX_PORTS,
1397 .cons = STM32_SERIAL_CONSOLE,
1398};
1399
1400static void __maybe_unused stm32_serial_enable_wakeup(struct uart_port *port,
1401 bool enable)
1402{
1403 struct stm32_port *stm32_port = to_stm32_port(port);
1404 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1405 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1406 u32 val;
1407
1408 if (stm32_port->wakeirq <= 0)
1409 return;
1410
1411 if (enable) {
1412 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1413 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1414 val = readl_relaxed(port->membase + ofs->cr3);
1415 val &= ~USART_CR3_WUS_MASK;
1416 /* Enable Wake up interrupt from low power on start bit */
1417 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1418 writel_relaxed(val, port->membase + ofs->cr3);
1419 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1420 } else {
1421 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1422 }
1423}
1424
1425static int __maybe_unused stm32_serial_suspend(struct device *dev)
1426{
1427 struct uart_port *port = dev_get_drvdata(dev);
1428
1429 uart_suspend_port(&stm32_usart_driver, port);
1430
1431 if (device_may_wakeup(dev))
1432 stm32_serial_enable_wakeup(port, true);
1433 else
1434 stm32_serial_enable_wakeup(port, false);
1435
1436 /*
1437 * When "no_console_suspend" is enabled, keep the pinctrl default state
1438 * and rely on bootloader stage to restore this state upon resume.
1439 * Otherwise, apply the idle or sleep states depending on wakeup
1440 * capabilities.
1441 */
1442 if (console_suspend_enabled || !uart_console(port)) {
1443 if (device_may_wakeup(dev))
1444 pinctrl_pm_select_idle_state(dev);
1445 else
1446 pinctrl_pm_select_sleep_state(dev);
1447 }
1448
1449 return 0;
1450}
1451
1452static int __maybe_unused stm32_serial_resume(struct device *dev)
1453{
1454 struct uart_port *port = dev_get_drvdata(dev);
1455
1456 pinctrl_pm_select_default_state(dev);
1457
1458 if (device_may_wakeup(dev))
1459 stm32_serial_enable_wakeup(port, false);
1460
1461 return uart_resume_port(&stm32_usart_driver, port);
1462}
1463
1464static int __maybe_unused stm32_serial_runtime_suspend(struct device *dev)
1465{
1466 struct uart_port *port = dev_get_drvdata(dev);
1467 struct stm32_port *stm32port = container_of(port,
1468 struct stm32_port, port);
1469
1470 clk_disable_unprepare(stm32port->clk);
1471
1472 return 0;
1473}
1474
1475static int __maybe_unused stm32_serial_runtime_resume(struct device *dev)
1476{
1477 struct uart_port *port = dev_get_drvdata(dev);
1478 struct stm32_port *stm32port = container_of(port,
1479 struct stm32_port, port);
1480
1481 return clk_prepare_enable(stm32port->clk);
1482}
1483
1484static const struct dev_pm_ops stm32_serial_pm_ops = {
1485 SET_RUNTIME_PM_OPS(stm32_serial_runtime_suspend,
1486 stm32_serial_runtime_resume, NULL)
1487 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1488};
1489
1490static struct platform_driver stm32_serial_driver = {
1491 .probe = stm32_serial_probe,
1492 .remove = stm32_serial_remove,
1493 .driver = {
1494 .name = DRIVER_NAME,
1495 .pm = &stm32_serial_pm_ops,
1496 .of_match_table = of_match_ptr(stm32_match),
1497 },
1498};
1499
1500static int __init usart_init(void)
1501{
1502 static char banner[] __initdata = "STM32 USART driver initialized";
1503 int ret;
1504
1505 pr_info("%s\n", banner);
1506
1507 ret = uart_register_driver(&stm32_usart_driver);
1508 if (ret)
1509 return ret;
1510
1511 ret = platform_driver_register(&stm32_serial_driver);
1512 if (ret)
1513 uart_unregister_driver(&stm32_usart_driver);
1514
1515 return ret;
1516}
1517
1518static void __exit usart_exit(void)
1519{
1520 platform_driver_unregister(&stm32_serial_driver);
1521 uart_unregister_driver(&stm32_usart_driver);
1522}
1523
1524module_init(usart_init);
1525module_exit(usart_exit);
1526
1527MODULE_ALIAS("platform:" DRIVER_NAME);
1528MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1529MODULE_LICENSE("GPL v2");