Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdesc.h>
16#include <linux/irqdomain.h>
17#include <linux/mfd/syscon.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25#include "stm32-adc-core.h"
26
27#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
28
29/* SYSCFG registers */
30#define STM32MP1_SYSCFG_PMCSETR 0x04
31#define STM32MP1_SYSCFG_PMCCLRR 0x44
32
33/* SYSCFG bit fields */
34#define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
35
36/* SYSCFG capability flags */
37#define HAS_VBOOSTER BIT(0)
38#define HAS_ANASWVDD BIT(1)
39
40/**
41 * stm32_adc_common_regs - stm32 common registers, compatible dependent data
42 * @csr: common status register offset
43 * @ccr: common control register offset
44 * @eoc1: adc1 end of conversion flag in @csr
45 * @eoc2: adc2 end of conversion flag in @csr
46 * @eoc3: adc3 end of conversion flag in @csr
47 * @ier: interrupt enable register offset for each adc
48 * @eocie_msk: end of conversion interrupt enable mask in @ier
49 */
50struct stm32_adc_common_regs {
51 u32 csr;
52 u32 ccr;
53 u32 eoc1_msk;
54 u32 eoc2_msk;
55 u32 eoc3_msk;
56 u32 ier;
57 u32 eocie_msk;
58};
59
60struct stm32_adc_priv;
61
62/**
63 * stm32_adc_priv_cfg - stm32 core compatible configuration data
64 * @regs: common registers for all instances
65 * @clk_sel: clock selection routine
66 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
67 * @has_syscfg: SYSCFG capability flags
68 */
69struct stm32_adc_priv_cfg {
70 const struct stm32_adc_common_regs *regs;
71 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
72 u32 max_clk_rate_hz;
73 unsigned int has_syscfg;
74};
75
76/**
77 * struct stm32_adc_priv - stm32 ADC core private data
78 * @irq: irq(s) for ADC block
79 * @domain: irq domain reference
80 * @aclk: clock reference for the analog circuitry
81 * @bclk: bus clock common for all ADCs, depends on part used
82 * @booster: booster supply reference
83 * @vdd: vdd supply reference
84 * @vdda: vdda analog supply reference
85 * @vref: regulator reference
86 * @vdd_uv: vdd supply voltage (microvolts)
87 * @vdda_uv: vdda supply voltage (microvolts)
88 * @cfg: compatible configuration data
89 * @common: common data for all ADC instances
90 * @ccr_bak: backup CCR in low power mode
91 * @syscfg: reference to syscon, system control registers
92 */
93struct stm32_adc_priv {
94 int irq[STM32_ADC_MAX_ADCS];
95 struct irq_domain *domain;
96 struct clk *aclk;
97 struct clk *bclk;
98 struct regulator *booster;
99 struct regulator *vdd;
100 struct regulator *vdda;
101 struct regulator *vref;
102 int vdd_uv;
103 int vdda_uv;
104 const struct stm32_adc_priv_cfg *cfg;
105 struct stm32_adc_common common;
106 u32 ccr_bak;
107 struct regmap *syscfg;
108};
109
110static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
111{
112 return container_of(com, struct stm32_adc_priv, common);
113}
114
115/* STM32F4 ADC internal common clock prescaler division ratios */
116static int stm32f4_pclk_div[] = {2, 4, 6, 8};
117
118/**
119 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
120 * @priv: stm32 ADC core private data
121 * Select clock prescaler used for analog conversions, before using ADC.
122 */
123static int stm32f4_adc_clk_sel(struct platform_device *pdev,
124 struct stm32_adc_priv *priv)
125{
126 unsigned long rate;
127 u32 val;
128 int i;
129
130 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
131 if (!priv->aclk) {
132 dev_err(&pdev->dev, "No 'adc' clock found\n");
133 return -ENOENT;
134 }
135
136 rate = clk_get_rate(priv->aclk);
137 if (!rate) {
138 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
139 return -EINVAL;
140 }
141
142 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
143 if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
144 break;
145 }
146 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
147 dev_err(&pdev->dev, "adc clk selection failed\n");
148 return -EINVAL;
149 }
150
151 priv->common.rate = rate / stm32f4_pclk_div[i];
152 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
153 val &= ~STM32F4_ADC_ADCPRE_MASK;
154 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
155 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
156
157 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
158 priv->common.rate / 1000);
159
160 return 0;
161}
162
163/**
164 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
165 * @ckmode: ADC clock mode, Async or sync with prescaler.
166 * @presc: prescaler bitfield for async clock mode
167 * @div: prescaler division ratio
168 */
169struct stm32h7_adc_ck_spec {
170 u32 ckmode;
171 u32 presc;
172 int div;
173};
174
175static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
176 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
177 { 0, 0, 1 },
178 { 0, 1, 2 },
179 { 0, 2, 4 },
180 { 0, 3, 6 },
181 { 0, 4, 8 },
182 { 0, 5, 10 },
183 { 0, 6, 12 },
184 { 0, 7, 16 },
185 { 0, 8, 32 },
186 { 0, 9, 64 },
187 { 0, 10, 128 },
188 { 0, 11, 256 },
189 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
190 { 1, 0, 1 },
191 { 2, 0, 2 },
192 { 3, 0, 4 },
193};
194
195static int stm32h7_adc_clk_sel(struct platform_device *pdev,
196 struct stm32_adc_priv *priv)
197{
198 u32 ckmode, presc, val;
199 unsigned long rate;
200 int i, div;
201
202 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
203 if (!priv->bclk) {
204 dev_err(&pdev->dev, "No 'bus' clock found\n");
205 return -ENOENT;
206 }
207
208 /*
209 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
210 * So, choice is to have bus clock mandatory and adc clock optional.
211 * If optional 'adc' clock has been found, then try to use it first.
212 */
213 if (priv->aclk) {
214 /*
215 * Asynchronous clock modes (e.g. ckmode == 0)
216 * From spec: PLL output musn't exceed max rate
217 */
218 rate = clk_get_rate(priv->aclk);
219 if (!rate) {
220 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
221 return -EINVAL;
222 }
223
224 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
225 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
226 presc = stm32h7_adc_ckmodes_spec[i].presc;
227 div = stm32h7_adc_ckmodes_spec[i].div;
228
229 if (ckmode)
230 continue;
231
232 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
233 goto out;
234 }
235 }
236
237 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
238 rate = clk_get_rate(priv->bclk);
239 if (!rate) {
240 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
241 return -EINVAL;
242 }
243
244 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
245 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
246 presc = stm32h7_adc_ckmodes_spec[i].presc;
247 div = stm32h7_adc_ckmodes_spec[i].div;
248
249 if (!ckmode)
250 continue;
251
252 if ((rate / div) <= priv->cfg->max_clk_rate_hz)
253 goto out;
254 }
255
256 dev_err(&pdev->dev, "adc clk selection failed\n");
257 return -EINVAL;
258
259out:
260 /* rate used later by each ADC instance to control BOOST mode */
261 priv->common.rate = rate / div;
262
263 /* Set common clock mode and prescaler */
264 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
265 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
266 val |= ckmode << STM32H7_CKMODE_SHIFT;
267 val |= presc << STM32H7_PRESC_SHIFT;
268 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
269
270 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
271 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
272
273 return 0;
274}
275
276/* STM32F4 common registers definitions */
277static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
278 .csr = STM32F4_ADC_CSR,
279 .ccr = STM32F4_ADC_CCR,
280 .eoc1_msk = STM32F4_EOC1,
281 .eoc2_msk = STM32F4_EOC2,
282 .eoc3_msk = STM32F4_EOC3,
283 .ier = STM32F4_ADC_CR1,
284 .eocie_msk = STM32F4_EOCIE,
285};
286
287/* STM32H7 common registers definitions */
288static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
289 .csr = STM32H7_ADC_CSR,
290 .ccr = STM32H7_ADC_CCR,
291 .eoc1_msk = STM32H7_EOC_MST,
292 .eoc2_msk = STM32H7_EOC_SLV,
293 .ier = STM32H7_ADC_IER,
294 .eocie_msk = STM32H7_EOCIE,
295};
296
297static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
298 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
299};
300
301static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
302 unsigned int adc)
303{
304 u32 ier, offset = stm32_adc_offset[adc];
305
306 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
307
308 return ier & priv->cfg->regs->eocie_msk;
309}
310
311/* ADC common interrupt for all instances */
312static void stm32_adc_irq_handler(struct irq_desc *desc)
313{
314 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
315 struct irq_chip *chip = irq_desc_get_chip(desc);
316 u32 status;
317
318 chained_irq_enter(chip, desc);
319 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
320
321 /*
322 * End of conversion may be handled by using IRQ or DMA. There may be a
323 * race here when two conversions complete at the same time on several
324 * ADCs. EOC may be read 'set' for several ADCs, with:
325 * - an ADC configured to use DMA (EOC triggers the DMA request, and
326 * is then automatically cleared by DR read in hardware)
327 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
328 * be called in this case)
329 * So both EOC status bit in CSR and EOCIE control bit must be checked
330 * before invoking the interrupt handler (e.g. call ISR only for
331 * IRQ-enabled ADCs).
332 */
333 if (status & priv->cfg->regs->eoc1_msk &&
334 stm32_adc_eoc_enabled(priv, 0))
335 generic_handle_irq(irq_find_mapping(priv->domain, 0));
336
337 if (status & priv->cfg->regs->eoc2_msk &&
338 stm32_adc_eoc_enabled(priv, 1))
339 generic_handle_irq(irq_find_mapping(priv->domain, 1));
340
341 if (status & priv->cfg->regs->eoc3_msk &&
342 stm32_adc_eoc_enabled(priv, 2))
343 generic_handle_irq(irq_find_mapping(priv->domain, 2));
344
345 chained_irq_exit(chip, desc);
346};
347
348static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
349 irq_hw_number_t hwirq)
350{
351 irq_set_chip_data(irq, d->host_data);
352 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
353
354 return 0;
355}
356
357static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
358{
359 irq_set_chip_and_handler(irq, NULL, NULL);
360 irq_set_chip_data(irq, NULL);
361}
362
363static const struct irq_domain_ops stm32_adc_domain_ops = {
364 .map = stm32_adc_domain_map,
365 .unmap = stm32_adc_domain_unmap,
366 .xlate = irq_domain_xlate_onecell,
367};
368
369static int stm32_adc_irq_probe(struct platform_device *pdev,
370 struct stm32_adc_priv *priv)
371{
372 struct device_node *np = pdev->dev.of_node;
373 unsigned int i;
374
375 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
376 priv->irq[i] = platform_get_irq(pdev, i);
377 if (priv->irq[i] < 0) {
378 /*
379 * At least one interrupt must be provided, make others
380 * optional:
381 * - stm32f4/h7 shares a common interrupt.
382 * - stm32mp1, has one line per ADC (either for ADC1,
383 * ADC2 or both).
384 */
385 if (i && priv->irq[i] == -ENXIO)
386 continue;
387
388 return priv->irq[i];
389 }
390 }
391
392 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
393 &stm32_adc_domain_ops,
394 priv);
395 if (!priv->domain) {
396 dev_err(&pdev->dev, "Failed to add irq domain\n");
397 return -ENOMEM;
398 }
399
400 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
401 if (priv->irq[i] < 0)
402 continue;
403 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
404 irq_set_handler_data(priv->irq[i], priv);
405 }
406
407 return 0;
408}
409
410static void stm32_adc_irq_remove(struct platform_device *pdev,
411 struct stm32_adc_priv *priv)
412{
413 int hwirq;
414 unsigned int i;
415
416 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
417 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
418 irq_domain_remove(priv->domain);
419
420 for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
421 if (priv->irq[i] < 0)
422 continue;
423 irq_set_chained_handler(priv->irq[i], NULL);
424 }
425}
426
427static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
428 struct device *dev)
429{
430 int ret;
431
432 /*
433 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
434 * switches (via PCSEL) which have reduced performances when their
435 * supply is below 2.7V (vdda by default):
436 * - Voltage booster can be used, to get full ADC performances
437 * (increases power consumption).
438 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
439 *
440 * Recommended settings for ANASWVDD and EN_BOOSTER:
441 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
442 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
443 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
444 */
445 if (priv->vdda_uv < 2700000) {
446 if (priv->syscfg && priv->vdd_uv > 2700000) {
447 ret = regulator_enable(priv->vdd);
448 if (ret < 0) {
449 dev_err(dev, "vdd enable failed %d\n", ret);
450 return ret;
451 }
452
453 ret = regmap_write(priv->syscfg,
454 STM32MP1_SYSCFG_PMCSETR,
455 STM32MP1_SYSCFG_ANASWVDD_MASK);
456 if (ret < 0) {
457 regulator_disable(priv->vdd);
458 dev_err(dev, "vdd select failed, %d\n", ret);
459 return ret;
460 }
461 dev_dbg(dev, "analog switches supplied by vdd\n");
462
463 return 0;
464 }
465
466 if (priv->booster) {
467 /*
468 * This is optional, as this is a trade-off between
469 * analog performance and power consumption.
470 */
471 ret = regulator_enable(priv->booster);
472 if (ret < 0) {
473 dev_err(dev, "booster enable failed %d\n", ret);
474 return ret;
475 }
476 dev_dbg(dev, "analog switches supplied by booster\n");
477
478 return 0;
479 }
480 }
481
482 /* Fallback using vdda (default), nothing to do */
483 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
484 priv->vdda_uv);
485
486 return 0;
487}
488
489static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
490{
491 if (priv->vdda_uv < 2700000) {
492 if (priv->syscfg && priv->vdd_uv > 2700000) {
493 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
494 STM32MP1_SYSCFG_ANASWVDD_MASK);
495 regulator_disable(priv->vdd);
496 return;
497 }
498 if (priv->booster)
499 regulator_disable(priv->booster);
500 }
501}
502
503static int stm32_adc_core_hw_start(struct device *dev)
504{
505 struct stm32_adc_common *common = dev_get_drvdata(dev);
506 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
507 int ret;
508
509 ret = regulator_enable(priv->vdda);
510 if (ret < 0) {
511 dev_err(dev, "vdda enable failed %d\n", ret);
512 return ret;
513 }
514
515 ret = regulator_get_voltage(priv->vdda);
516 if (ret < 0) {
517 dev_err(dev, "vdda get voltage failed, %d\n", ret);
518 goto err_vdda_disable;
519 }
520 priv->vdda_uv = ret;
521
522 ret = stm32_adc_core_switches_supply_en(priv, dev);
523 if (ret < 0)
524 goto err_vdda_disable;
525
526 ret = regulator_enable(priv->vref);
527 if (ret < 0) {
528 dev_err(dev, "vref enable failed\n");
529 goto err_switches_dis;
530 }
531
532 if (priv->bclk) {
533 ret = clk_prepare_enable(priv->bclk);
534 if (ret < 0) {
535 dev_err(dev, "bus clk enable failed\n");
536 goto err_regulator_disable;
537 }
538 }
539
540 if (priv->aclk) {
541 ret = clk_prepare_enable(priv->aclk);
542 if (ret < 0) {
543 dev_err(dev, "adc clk enable failed\n");
544 goto err_bclk_disable;
545 }
546 }
547
548 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
549
550 return 0;
551
552err_bclk_disable:
553 if (priv->bclk)
554 clk_disable_unprepare(priv->bclk);
555err_regulator_disable:
556 regulator_disable(priv->vref);
557err_switches_dis:
558 stm32_adc_core_switches_supply_dis(priv);
559err_vdda_disable:
560 regulator_disable(priv->vdda);
561
562 return ret;
563}
564
565static void stm32_adc_core_hw_stop(struct device *dev)
566{
567 struct stm32_adc_common *common = dev_get_drvdata(dev);
568 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
569
570 /* Backup CCR that may be lost (depends on power state to achieve) */
571 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
572 if (priv->aclk)
573 clk_disable_unprepare(priv->aclk);
574 if (priv->bclk)
575 clk_disable_unprepare(priv->bclk);
576 regulator_disable(priv->vref);
577 stm32_adc_core_switches_supply_dis(priv);
578 regulator_disable(priv->vdda);
579}
580
581static int stm32_adc_core_switches_probe(struct device *dev,
582 struct stm32_adc_priv *priv)
583{
584 struct device_node *np = dev->of_node;
585 int ret;
586
587 /* Analog switches supply can be controlled by syscfg (optional) */
588 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
589 if (IS_ERR(priv->syscfg)) {
590 ret = PTR_ERR(priv->syscfg);
591 if (ret != -ENODEV) {
592 if (ret != -EPROBE_DEFER)
593 dev_err(dev, "Can't probe syscfg: %d\n", ret);
594 return ret;
595 }
596 priv->syscfg = NULL;
597 }
598
599 /* Booster can be used to supply analog switches (optional) */
600 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
601 of_property_read_bool(np, "booster-supply")) {
602 priv->booster = devm_regulator_get_optional(dev, "booster");
603 if (IS_ERR(priv->booster)) {
604 ret = PTR_ERR(priv->booster);
605 if (ret != -ENODEV) {
606 if (ret != -EPROBE_DEFER)
607 dev_err(dev, "can't get booster %d\n",
608 ret);
609 return ret;
610 }
611 priv->booster = NULL;
612 }
613 }
614
615 /* Vdd can be used to supply analog switches (optional) */
616 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
617 of_property_read_bool(np, "vdd-supply")) {
618 priv->vdd = devm_regulator_get_optional(dev, "vdd");
619 if (IS_ERR(priv->vdd)) {
620 ret = PTR_ERR(priv->vdd);
621 if (ret != -ENODEV) {
622 if (ret != -EPROBE_DEFER)
623 dev_err(dev, "can't get vdd %d\n", ret);
624 return ret;
625 }
626 priv->vdd = NULL;
627 }
628 }
629
630 if (priv->vdd) {
631 ret = regulator_enable(priv->vdd);
632 if (ret < 0) {
633 dev_err(dev, "vdd enable failed %d\n", ret);
634 return ret;
635 }
636
637 ret = regulator_get_voltage(priv->vdd);
638 if (ret < 0) {
639 dev_err(dev, "vdd get voltage failed %d\n", ret);
640 regulator_disable(priv->vdd);
641 return ret;
642 }
643 priv->vdd_uv = ret;
644
645 regulator_disable(priv->vdd);
646 }
647
648 return 0;
649}
650
651static int stm32_adc_probe(struct platform_device *pdev)
652{
653 struct stm32_adc_priv *priv;
654 struct device *dev = &pdev->dev;
655 struct device_node *np = pdev->dev.of_node;
656 struct resource *res;
657 int ret;
658
659 if (!pdev->dev.of_node)
660 return -ENODEV;
661
662 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
663 if (!priv)
664 return -ENOMEM;
665 platform_set_drvdata(pdev, &priv->common);
666
667 priv->cfg = (const struct stm32_adc_priv_cfg *)
668 of_match_device(dev->driver->of_match_table, dev)->data;
669
670 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
671 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
672 if (IS_ERR(priv->common.base))
673 return PTR_ERR(priv->common.base);
674 priv->common.phys_base = res->start;
675
676 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
677 if (IS_ERR(priv->vdda)) {
678 ret = PTR_ERR(priv->vdda);
679 if (ret != -EPROBE_DEFER)
680 dev_err(&pdev->dev, "vdda get failed, %d\n", ret);
681 return ret;
682 }
683
684 priv->vref = devm_regulator_get(&pdev->dev, "vref");
685 if (IS_ERR(priv->vref)) {
686 ret = PTR_ERR(priv->vref);
687 dev_err(&pdev->dev, "vref get failed, %d\n", ret);
688 return ret;
689 }
690
691 priv->aclk = devm_clk_get(&pdev->dev, "adc");
692 if (IS_ERR(priv->aclk)) {
693 ret = PTR_ERR(priv->aclk);
694 if (ret != -ENOENT) {
695 dev_err(&pdev->dev, "Can't get 'adc' clock\n");
696 return ret;
697 }
698 priv->aclk = NULL;
699 }
700
701 priv->bclk = devm_clk_get(&pdev->dev, "bus");
702 if (IS_ERR(priv->bclk)) {
703 ret = PTR_ERR(priv->bclk);
704 if (ret != -ENOENT) {
705 dev_err(&pdev->dev, "Can't get 'bus' clock\n");
706 return ret;
707 }
708 priv->bclk = NULL;
709 }
710
711 ret = stm32_adc_core_switches_probe(dev, priv);
712 if (ret)
713 return ret;
714
715 pm_runtime_get_noresume(dev);
716 pm_runtime_set_active(dev);
717 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
718 pm_runtime_use_autosuspend(dev);
719 pm_runtime_enable(dev);
720
721 ret = stm32_adc_core_hw_start(dev);
722 if (ret)
723 goto err_pm_stop;
724
725 ret = regulator_get_voltage(priv->vref);
726 if (ret < 0) {
727 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
728 goto err_hw_stop;
729 }
730 priv->common.vref_mv = ret / 1000;
731 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
732
733 ret = priv->cfg->clk_sel(pdev, priv);
734 if (ret < 0)
735 goto err_hw_stop;
736
737 ret = stm32_adc_irq_probe(pdev, priv);
738 if (ret < 0)
739 goto err_hw_stop;
740
741 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
742 if (ret < 0) {
743 dev_err(&pdev->dev, "failed to populate DT children\n");
744 goto err_irq_remove;
745 }
746
747 pm_runtime_mark_last_busy(dev);
748 pm_runtime_put_autosuspend(dev);
749
750 return 0;
751
752err_irq_remove:
753 stm32_adc_irq_remove(pdev, priv);
754err_hw_stop:
755 stm32_adc_core_hw_stop(dev);
756err_pm_stop:
757 pm_runtime_disable(dev);
758 pm_runtime_set_suspended(dev);
759 pm_runtime_put_noidle(dev);
760
761 return ret;
762}
763
764static int stm32_adc_remove(struct platform_device *pdev)
765{
766 struct stm32_adc_common *common = platform_get_drvdata(pdev);
767 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
768
769 pm_runtime_get_sync(&pdev->dev);
770 of_platform_depopulate(&pdev->dev);
771 stm32_adc_irq_remove(pdev, priv);
772 stm32_adc_core_hw_stop(&pdev->dev);
773 pm_runtime_disable(&pdev->dev);
774 pm_runtime_set_suspended(&pdev->dev);
775 pm_runtime_put_noidle(&pdev->dev);
776
777 return 0;
778}
779
780#if defined(CONFIG_PM)
781static int stm32_adc_core_runtime_suspend(struct device *dev)
782{
783 stm32_adc_core_hw_stop(dev);
784
785 return 0;
786}
787
788static int stm32_adc_core_runtime_resume(struct device *dev)
789{
790 return stm32_adc_core_hw_start(dev);
791}
792#endif
793
794static const struct dev_pm_ops stm32_adc_core_pm_ops = {
795 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
796 pm_runtime_force_resume)
797 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
798 stm32_adc_core_runtime_resume,
799 NULL)
800};
801
802static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
803 .regs = &stm32f4_adc_common_regs,
804 .clk_sel = stm32f4_adc_clk_sel,
805 .max_clk_rate_hz = 36000000,
806};
807
808static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
809 .regs = &stm32h7_adc_common_regs,
810 .clk_sel = stm32h7_adc_clk_sel,
811 .max_clk_rate_hz = 36000000,
812 .has_syscfg = HAS_VBOOSTER,
813};
814
815static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
816 .regs = &stm32h7_adc_common_regs,
817 .clk_sel = stm32h7_adc_clk_sel,
818 .max_clk_rate_hz = 40000000,
819 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
820};
821
822static const struct of_device_id stm32_adc_of_match[] = {
823 {
824 .compatible = "st,stm32f4-adc-core",
825 .data = (void *)&stm32f4_adc_priv_cfg
826 }, {
827 .compatible = "st,stm32h7-adc-core",
828 .data = (void *)&stm32h7_adc_priv_cfg
829 }, {
830 .compatible = "st,stm32mp1-adc-core",
831 .data = (void *)&stm32mp1_adc_priv_cfg
832 }, {
833 },
834};
835MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
836
837static struct platform_driver stm32_adc_driver = {
838 .probe = stm32_adc_probe,
839 .remove = stm32_adc_remove,
840 .driver = {
841 .name = "stm32-adc-core",
842 .of_match_table = stm32_adc_of_match,
843 .pm = &stm32_adc_core_pm_ops,
844 },
845};
846module_platform_driver(stm32_adc_driver);
847
848MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
849MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
850MODULE_LICENSE("GPL v2");
851MODULE_ALIAS("platform:stm32-adc-core");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 *
8 * Inspired from: fsl-imx25-tsadc
9 *
10 */
11
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/irqchip/chained_irq.h>
15#include <linux/irqdesc.h>
16#include <linux/irqdomain.h>
17#include <linux/mfd/syscon.h>
18#include <linux/module.h>
19#include <linux/of_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/regmap.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24
25#include "stm32-adc-core.h"
26
27#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
28
29/* SYSCFG registers */
30#define STM32MP1_SYSCFG_PMCSETR 0x04
31#define STM32MP1_SYSCFG_PMCCLRR 0x44
32
33/* SYSCFG bit fields */
34#define STM32MP1_SYSCFG_ANASWVDD_MASK BIT(9)
35
36/* SYSCFG capability flags */
37#define HAS_VBOOSTER BIT(0)
38#define HAS_ANASWVDD BIT(1)
39
40/**
41 * struct stm32_adc_common_regs - stm32 common registers
42 * @csr: common status register offset
43 * @ccr: common control register offset
44 * @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n
45 * @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n
46 * @ier: interrupt enable register offset for each adc
47 * @eocie_msk: end of conversion interrupt enable mask in @ier
48 */
49struct stm32_adc_common_regs {
50 u32 csr;
51 u32 ccr;
52 u32 eoc_msk[STM32_ADC_MAX_ADCS];
53 u32 ovr_msk[STM32_ADC_MAX_ADCS];
54 u32 ier;
55 u32 eocie_msk;
56};
57
58struct stm32_adc_priv;
59
60/**
61 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data
62 * @regs: common registers for all instances
63 * @clk_sel: clock selection routine
64 * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
65 * @has_syscfg: SYSCFG capability flags
66 * @num_irqs: number of interrupt lines
67 */
68struct stm32_adc_priv_cfg {
69 const struct stm32_adc_common_regs *regs;
70 int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
71 u32 max_clk_rate_hz;
72 unsigned int has_syscfg;
73 unsigned int num_irqs;
74};
75
76/**
77 * struct stm32_adc_priv - stm32 ADC core private data
78 * @irq: irq(s) for ADC block
79 * @domain: irq domain reference
80 * @aclk: clock reference for the analog circuitry
81 * @bclk: bus clock common for all ADCs, depends on part used
82 * @max_clk_rate: desired maximum clock rate
83 * @booster: booster supply reference
84 * @vdd: vdd supply reference
85 * @vdda: vdda analog supply reference
86 * @vref: regulator reference
87 * @vdd_uv: vdd supply voltage (microvolts)
88 * @vdda_uv: vdda supply voltage (microvolts)
89 * @cfg: compatible configuration data
90 * @common: common data for all ADC instances
91 * @ccr_bak: backup CCR in low power mode
92 * @syscfg: reference to syscon, system control registers
93 */
94struct stm32_adc_priv {
95 int irq[STM32_ADC_MAX_ADCS];
96 struct irq_domain *domain;
97 struct clk *aclk;
98 struct clk *bclk;
99 u32 max_clk_rate;
100 struct regulator *booster;
101 struct regulator *vdd;
102 struct regulator *vdda;
103 struct regulator *vref;
104 int vdd_uv;
105 int vdda_uv;
106 const struct stm32_adc_priv_cfg *cfg;
107 struct stm32_adc_common common;
108 u32 ccr_bak;
109 struct regmap *syscfg;
110};
111
112static struct stm32_adc_priv *to_stm32_adc_priv(struct stm32_adc_common *com)
113{
114 return container_of(com, struct stm32_adc_priv, common);
115}
116
117/* STM32F4 ADC internal common clock prescaler division ratios */
118static int stm32f4_pclk_div[] = {2, 4, 6, 8};
119
120/**
121 * stm32f4_adc_clk_sel() - Select stm32f4 ADC common clock prescaler
122 * @pdev: platform device
123 * @priv: stm32 ADC core private data
124 * Select clock prescaler used for analog conversions, before using ADC.
125 */
126static int stm32f4_adc_clk_sel(struct platform_device *pdev,
127 struct stm32_adc_priv *priv)
128{
129 unsigned long rate;
130 u32 val;
131 int i;
132
133 /* stm32f4 has one clk input for analog (mandatory), enforce it here */
134 if (!priv->aclk) {
135 dev_err(&pdev->dev, "No 'adc' clock found\n");
136 return -ENOENT;
137 }
138
139 rate = clk_get_rate(priv->aclk);
140 if (!rate) {
141 dev_err(&pdev->dev, "Invalid clock rate: 0\n");
142 return -EINVAL;
143 }
144
145 for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
146 if ((rate / stm32f4_pclk_div[i]) <= priv->max_clk_rate)
147 break;
148 }
149 if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
150 dev_err(&pdev->dev, "adc clk selection failed\n");
151 return -EINVAL;
152 }
153
154 priv->common.rate = rate / stm32f4_pclk_div[i];
155 val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR);
156 val &= ~STM32F4_ADC_ADCPRE_MASK;
157 val |= i << STM32F4_ADC_ADCPRE_SHIFT;
158 writel_relaxed(val, priv->common.base + STM32F4_ADC_CCR);
159
160 dev_dbg(&pdev->dev, "Using analog clock source at %ld kHz\n",
161 priv->common.rate / 1000);
162
163 return 0;
164}
165
166/**
167 * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
168 * @ckmode: ADC clock mode, Async or sync with prescaler.
169 * @presc: prescaler bitfield for async clock mode
170 * @div: prescaler division ratio
171 */
172struct stm32h7_adc_ck_spec {
173 u32 ckmode;
174 u32 presc;
175 int div;
176};
177
178static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
179 /* 00: CK_ADC[1..3]: Asynchronous clock modes */
180 { 0, 0, 1 },
181 { 0, 1, 2 },
182 { 0, 2, 4 },
183 { 0, 3, 6 },
184 { 0, 4, 8 },
185 { 0, 5, 10 },
186 { 0, 6, 12 },
187 { 0, 7, 16 },
188 { 0, 8, 32 },
189 { 0, 9, 64 },
190 { 0, 10, 128 },
191 { 0, 11, 256 },
192 /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
193 { 1, 0, 1 },
194 { 2, 0, 2 },
195 { 3, 0, 4 },
196};
197
198static int stm32h7_adc_clk_sel(struct platform_device *pdev,
199 struct stm32_adc_priv *priv)
200{
201 u32 ckmode, presc, val;
202 unsigned long rate;
203 int i, div, duty;
204
205 /* stm32h7 bus clock is common for all ADC instances (mandatory) */
206 if (!priv->bclk) {
207 dev_err(&pdev->dev, "No 'bus' clock found\n");
208 return -ENOENT;
209 }
210
211 /*
212 * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
213 * So, choice is to have bus clock mandatory and adc clock optional.
214 * If optional 'adc' clock has been found, then try to use it first.
215 */
216 if (priv->aclk) {
217 /*
218 * Asynchronous clock modes (e.g. ckmode == 0)
219 * From spec: PLL output musn't exceed max rate
220 */
221 rate = clk_get_rate(priv->aclk);
222 if (!rate) {
223 dev_err(&pdev->dev, "Invalid adc clock rate: 0\n");
224 return -EINVAL;
225 }
226
227 /* If duty is an error, kindly use at least /2 divider */
228 duty = clk_get_scaled_duty_cycle(priv->aclk, 100);
229 if (duty < 0)
230 dev_warn(&pdev->dev, "adc clock duty: %d\n", duty);
231
232 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
233 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
234 presc = stm32h7_adc_ckmodes_spec[i].presc;
235 div = stm32h7_adc_ckmodes_spec[i].div;
236
237 if (ckmode)
238 continue;
239
240 /*
241 * For proper operation, clock duty cycle range is 49%
242 * to 51%. Apply at least /2 prescaler otherwise.
243 */
244 if (div == 1 && (duty < 49 || duty > 51))
245 continue;
246
247 if ((rate / div) <= priv->max_clk_rate)
248 goto out;
249 }
250 }
251
252 /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
253 rate = clk_get_rate(priv->bclk);
254 if (!rate) {
255 dev_err(&pdev->dev, "Invalid bus clock rate: 0\n");
256 return -EINVAL;
257 }
258
259 duty = clk_get_scaled_duty_cycle(priv->bclk, 100);
260 if (duty < 0)
261 dev_warn(&pdev->dev, "bus clock duty: %d\n", duty);
262
263 for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
264 ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
265 presc = stm32h7_adc_ckmodes_spec[i].presc;
266 div = stm32h7_adc_ckmodes_spec[i].div;
267
268 if (!ckmode)
269 continue;
270
271 if (div == 1 && (duty < 49 || duty > 51))
272 continue;
273
274 if ((rate / div) <= priv->max_clk_rate)
275 goto out;
276 }
277
278 dev_err(&pdev->dev, "adc clk selection failed\n");
279 return -EINVAL;
280
281out:
282 /* rate used later by each ADC instance to control BOOST mode */
283 priv->common.rate = rate / div;
284
285 /* Set common clock mode and prescaler */
286 val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR);
287 val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK);
288 val |= ckmode << STM32H7_CKMODE_SHIFT;
289 val |= presc << STM32H7_PRESC_SHIFT;
290 writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR);
291
292 dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n",
293 ckmode ? "bus" : "adc", div, priv->common.rate / 1000);
294
295 return 0;
296}
297
298/* STM32F4 common registers definitions */
299static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
300 .csr = STM32F4_ADC_CSR,
301 .ccr = STM32F4_ADC_CCR,
302 .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3},
303 .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3},
304 .ier = STM32F4_ADC_CR1,
305 .eocie_msk = STM32F4_EOCIE,
306};
307
308/* STM32H7 common registers definitions */
309static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
310 .csr = STM32H7_ADC_CSR,
311 .ccr = STM32H7_ADC_CCR,
312 .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV},
313 .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV},
314 .ier = STM32H7_ADC_IER,
315 .eocie_msk = STM32H7_EOCIE,
316};
317
318static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
319 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
320};
321
322static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
323 unsigned int adc)
324{
325 u32 ier, offset = stm32_adc_offset[adc];
326
327 ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
328
329 return ier & priv->cfg->regs->eocie_msk;
330}
331
332/* ADC common interrupt for all instances */
333static void stm32_adc_irq_handler(struct irq_desc *desc)
334{
335 struct stm32_adc_priv *priv = irq_desc_get_handler_data(desc);
336 struct irq_chip *chip = irq_desc_get_chip(desc);
337 int i;
338 u32 status;
339
340 chained_irq_enter(chip, desc);
341 status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
342
343 /*
344 * End of conversion may be handled by using IRQ or DMA. There may be a
345 * race here when two conversions complete at the same time on several
346 * ADCs. EOC may be read 'set' for several ADCs, with:
347 * - an ADC configured to use DMA (EOC triggers the DMA request, and
348 * is then automatically cleared by DR read in hardware)
349 * - an ADC configured to use IRQs (EOCIE bit is set. The handler must
350 * be called in this case)
351 * So both EOC status bit in CSR and EOCIE control bit must be checked
352 * before invoking the interrupt handler (e.g. call ISR only for
353 * IRQ-enabled ADCs).
354 */
355 for (i = 0; i < priv->cfg->num_irqs; i++) {
356 if ((status & priv->cfg->regs->eoc_msk[i] &&
357 stm32_adc_eoc_enabled(priv, i)) ||
358 (status & priv->cfg->regs->ovr_msk[i]))
359 generic_handle_irq(irq_find_mapping(priv->domain, i));
360 }
361
362 chained_irq_exit(chip, desc);
363};
364
365static int stm32_adc_domain_map(struct irq_domain *d, unsigned int irq,
366 irq_hw_number_t hwirq)
367{
368 irq_set_chip_data(irq, d->host_data);
369 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_level_irq);
370
371 return 0;
372}
373
374static void stm32_adc_domain_unmap(struct irq_domain *d, unsigned int irq)
375{
376 irq_set_chip_and_handler(irq, NULL, NULL);
377 irq_set_chip_data(irq, NULL);
378}
379
380static const struct irq_domain_ops stm32_adc_domain_ops = {
381 .map = stm32_adc_domain_map,
382 .unmap = stm32_adc_domain_unmap,
383 .xlate = irq_domain_xlate_onecell,
384};
385
386static int stm32_adc_irq_probe(struct platform_device *pdev,
387 struct stm32_adc_priv *priv)
388{
389 struct device_node *np = pdev->dev.of_node;
390 unsigned int i;
391
392 /*
393 * Interrupt(s) must be provided, depending on the compatible:
394 * - stm32f4/h7 shares a common interrupt line.
395 * - stm32mp1, has one line per ADC
396 */
397 for (i = 0; i < priv->cfg->num_irqs; i++) {
398 priv->irq[i] = platform_get_irq(pdev, i);
399 if (priv->irq[i] < 0)
400 return priv->irq[i];
401 }
402
403 priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
404 &stm32_adc_domain_ops,
405 priv);
406 if (!priv->domain) {
407 dev_err(&pdev->dev, "Failed to add irq domain\n");
408 return -ENOMEM;
409 }
410
411 for (i = 0; i < priv->cfg->num_irqs; i++) {
412 irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
413 irq_set_handler_data(priv->irq[i], priv);
414 }
415
416 return 0;
417}
418
419static void stm32_adc_irq_remove(struct platform_device *pdev,
420 struct stm32_adc_priv *priv)
421{
422 int hwirq;
423 unsigned int i;
424
425 for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
426 irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
427 irq_domain_remove(priv->domain);
428
429 for (i = 0; i < priv->cfg->num_irqs; i++)
430 irq_set_chained_handler(priv->irq[i], NULL);
431}
432
433static int stm32_adc_core_switches_supply_en(struct stm32_adc_priv *priv,
434 struct device *dev)
435{
436 int ret;
437
438 /*
439 * On STM32H7 and STM32MP1, the ADC inputs are multiplexed with analog
440 * switches (via PCSEL) which have reduced performances when their
441 * supply is below 2.7V (vdda by default):
442 * - Voltage booster can be used, to get full ADC performances
443 * (increases power consumption).
444 * - Vdd can be used to supply them, if above 2.7V (STM32MP1 only).
445 *
446 * Recommended settings for ANASWVDD and EN_BOOSTER:
447 * - vdda < 2.7V but vdd > 2.7V: ANASWVDD = 1, EN_BOOSTER = 0 (stm32mp1)
448 * - vdda < 2.7V and vdd < 2.7V: ANASWVDD = 0, EN_BOOSTER = 1
449 * - vdda >= 2.7V: ANASWVDD = 0, EN_BOOSTER = 0 (default)
450 */
451 if (priv->vdda_uv < 2700000) {
452 if (priv->syscfg && priv->vdd_uv > 2700000) {
453 ret = regulator_enable(priv->vdd);
454 if (ret < 0) {
455 dev_err(dev, "vdd enable failed %d\n", ret);
456 return ret;
457 }
458
459 ret = regmap_write(priv->syscfg,
460 STM32MP1_SYSCFG_PMCSETR,
461 STM32MP1_SYSCFG_ANASWVDD_MASK);
462 if (ret < 0) {
463 regulator_disable(priv->vdd);
464 dev_err(dev, "vdd select failed, %d\n", ret);
465 return ret;
466 }
467 dev_dbg(dev, "analog switches supplied by vdd\n");
468
469 return 0;
470 }
471
472 if (priv->booster) {
473 /*
474 * This is optional, as this is a trade-off between
475 * analog performance and power consumption.
476 */
477 ret = regulator_enable(priv->booster);
478 if (ret < 0) {
479 dev_err(dev, "booster enable failed %d\n", ret);
480 return ret;
481 }
482 dev_dbg(dev, "analog switches supplied by booster\n");
483
484 return 0;
485 }
486 }
487
488 /* Fallback using vdda (default), nothing to do */
489 dev_dbg(dev, "analog switches supplied by vdda (%d uV)\n",
490 priv->vdda_uv);
491
492 return 0;
493}
494
495static void stm32_adc_core_switches_supply_dis(struct stm32_adc_priv *priv)
496{
497 if (priv->vdda_uv < 2700000) {
498 if (priv->syscfg && priv->vdd_uv > 2700000) {
499 regmap_write(priv->syscfg, STM32MP1_SYSCFG_PMCCLRR,
500 STM32MP1_SYSCFG_ANASWVDD_MASK);
501 regulator_disable(priv->vdd);
502 return;
503 }
504 if (priv->booster)
505 regulator_disable(priv->booster);
506 }
507}
508
509static int stm32_adc_core_hw_start(struct device *dev)
510{
511 struct stm32_adc_common *common = dev_get_drvdata(dev);
512 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
513 int ret;
514
515 ret = regulator_enable(priv->vdda);
516 if (ret < 0) {
517 dev_err(dev, "vdda enable failed %d\n", ret);
518 return ret;
519 }
520
521 ret = regulator_get_voltage(priv->vdda);
522 if (ret < 0) {
523 dev_err(dev, "vdda get voltage failed, %d\n", ret);
524 goto err_vdda_disable;
525 }
526 priv->vdda_uv = ret;
527
528 ret = stm32_adc_core_switches_supply_en(priv, dev);
529 if (ret < 0)
530 goto err_vdda_disable;
531
532 ret = regulator_enable(priv->vref);
533 if (ret < 0) {
534 dev_err(dev, "vref enable failed\n");
535 goto err_switches_dis;
536 }
537
538 ret = clk_prepare_enable(priv->bclk);
539 if (ret < 0) {
540 dev_err(dev, "bus clk enable failed\n");
541 goto err_regulator_disable;
542 }
543
544 ret = clk_prepare_enable(priv->aclk);
545 if (ret < 0) {
546 dev_err(dev, "adc clk enable failed\n");
547 goto err_bclk_disable;
548 }
549
550 writel_relaxed(priv->ccr_bak, priv->common.base + priv->cfg->regs->ccr);
551
552 return 0;
553
554err_bclk_disable:
555 clk_disable_unprepare(priv->bclk);
556err_regulator_disable:
557 regulator_disable(priv->vref);
558err_switches_dis:
559 stm32_adc_core_switches_supply_dis(priv);
560err_vdda_disable:
561 regulator_disable(priv->vdda);
562
563 return ret;
564}
565
566static void stm32_adc_core_hw_stop(struct device *dev)
567{
568 struct stm32_adc_common *common = dev_get_drvdata(dev);
569 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
570
571 /* Backup CCR that may be lost (depends on power state to achieve) */
572 priv->ccr_bak = readl_relaxed(priv->common.base + priv->cfg->regs->ccr);
573 clk_disable_unprepare(priv->aclk);
574 clk_disable_unprepare(priv->bclk);
575 regulator_disable(priv->vref);
576 stm32_adc_core_switches_supply_dis(priv);
577 regulator_disable(priv->vdda);
578}
579
580static int stm32_adc_core_switches_probe(struct device *dev,
581 struct stm32_adc_priv *priv)
582{
583 struct device_node *np = dev->of_node;
584 int ret;
585
586 /* Analog switches supply can be controlled by syscfg (optional) */
587 priv->syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
588 if (IS_ERR(priv->syscfg)) {
589 ret = PTR_ERR(priv->syscfg);
590 if (ret != -ENODEV)
591 return dev_err_probe(dev, ret, "Can't probe syscfg\n");
592
593 priv->syscfg = NULL;
594 }
595
596 /* Booster can be used to supply analog switches (optional) */
597 if (priv->cfg->has_syscfg & HAS_VBOOSTER &&
598 of_property_read_bool(np, "booster-supply")) {
599 priv->booster = devm_regulator_get_optional(dev, "booster");
600 if (IS_ERR(priv->booster)) {
601 ret = PTR_ERR(priv->booster);
602 if (ret != -ENODEV)
603 return dev_err_probe(dev, ret, "can't get booster\n");
604
605 priv->booster = NULL;
606 }
607 }
608
609 /* Vdd can be used to supply analog switches (optional) */
610 if (priv->cfg->has_syscfg & HAS_ANASWVDD &&
611 of_property_read_bool(np, "vdd-supply")) {
612 priv->vdd = devm_regulator_get_optional(dev, "vdd");
613 if (IS_ERR(priv->vdd)) {
614 ret = PTR_ERR(priv->vdd);
615 if (ret != -ENODEV)
616 return dev_err_probe(dev, ret, "can't get vdd\n");
617
618 priv->vdd = NULL;
619 }
620 }
621
622 if (priv->vdd) {
623 ret = regulator_enable(priv->vdd);
624 if (ret < 0) {
625 dev_err(dev, "vdd enable failed %d\n", ret);
626 return ret;
627 }
628
629 ret = regulator_get_voltage(priv->vdd);
630 if (ret < 0) {
631 dev_err(dev, "vdd get voltage failed %d\n", ret);
632 regulator_disable(priv->vdd);
633 return ret;
634 }
635 priv->vdd_uv = ret;
636
637 regulator_disable(priv->vdd);
638 }
639
640 return 0;
641}
642
643static int stm32_adc_probe(struct platform_device *pdev)
644{
645 struct stm32_adc_priv *priv;
646 struct device *dev = &pdev->dev;
647 struct device_node *np = pdev->dev.of_node;
648 struct resource *res;
649 u32 max_rate;
650 int ret;
651
652 if (!pdev->dev.of_node)
653 return -ENODEV;
654
655 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
656 if (!priv)
657 return -ENOMEM;
658 platform_set_drvdata(pdev, &priv->common);
659
660 priv->cfg = (const struct stm32_adc_priv_cfg *)
661 of_match_device(dev->driver->of_match_table, dev)->data;
662
663 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 priv->common.base = devm_ioremap_resource(&pdev->dev, res);
665 if (IS_ERR(priv->common.base))
666 return PTR_ERR(priv->common.base);
667 priv->common.phys_base = res->start;
668
669 priv->vdda = devm_regulator_get(&pdev->dev, "vdda");
670 if (IS_ERR(priv->vdda))
671 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vdda),
672 "vdda get failed\n");
673
674 priv->vref = devm_regulator_get(&pdev->dev, "vref");
675 if (IS_ERR(priv->vref))
676 return dev_err_probe(&pdev->dev, PTR_ERR(priv->vref),
677 "vref get failed\n");
678
679 priv->aclk = devm_clk_get_optional(&pdev->dev, "adc");
680 if (IS_ERR(priv->aclk))
681 return dev_err_probe(&pdev->dev, PTR_ERR(priv->aclk),
682 "Can't get 'adc' clock\n");
683
684 priv->bclk = devm_clk_get_optional(&pdev->dev, "bus");
685 if (IS_ERR(priv->bclk))
686 return dev_err_probe(&pdev->dev, PTR_ERR(priv->bclk),
687 "Can't get 'bus' clock\n");
688
689 ret = stm32_adc_core_switches_probe(dev, priv);
690 if (ret)
691 return ret;
692
693 pm_runtime_get_noresume(dev);
694 pm_runtime_set_active(dev);
695 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_CORE_SLEEP_DELAY_MS);
696 pm_runtime_use_autosuspend(dev);
697 pm_runtime_enable(dev);
698
699 ret = stm32_adc_core_hw_start(dev);
700 if (ret)
701 goto err_pm_stop;
702
703 ret = regulator_get_voltage(priv->vref);
704 if (ret < 0) {
705 dev_err(&pdev->dev, "vref get voltage failed, %d\n", ret);
706 goto err_hw_stop;
707 }
708 priv->common.vref_mv = ret / 1000;
709 dev_dbg(&pdev->dev, "vref+=%dmV\n", priv->common.vref_mv);
710
711 ret = of_property_read_u32(pdev->dev.of_node, "st,max-clk-rate-hz",
712 &max_rate);
713 if (!ret)
714 priv->max_clk_rate = min(max_rate, priv->cfg->max_clk_rate_hz);
715 else
716 priv->max_clk_rate = priv->cfg->max_clk_rate_hz;
717
718 ret = priv->cfg->clk_sel(pdev, priv);
719 if (ret < 0)
720 goto err_hw_stop;
721
722 ret = stm32_adc_irq_probe(pdev, priv);
723 if (ret < 0)
724 goto err_hw_stop;
725
726 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
727 if (ret < 0) {
728 dev_err(&pdev->dev, "failed to populate DT children\n");
729 goto err_irq_remove;
730 }
731
732 pm_runtime_mark_last_busy(dev);
733 pm_runtime_put_autosuspend(dev);
734
735 return 0;
736
737err_irq_remove:
738 stm32_adc_irq_remove(pdev, priv);
739err_hw_stop:
740 stm32_adc_core_hw_stop(dev);
741err_pm_stop:
742 pm_runtime_disable(dev);
743 pm_runtime_set_suspended(dev);
744 pm_runtime_put_noidle(dev);
745
746 return ret;
747}
748
749static int stm32_adc_remove(struct platform_device *pdev)
750{
751 struct stm32_adc_common *common = platform_get_drvdata(pdev);
752 struct stm32_adc_priv *priv = to_stm32_adc_priv(common);
753
754 pm_runtime_get_sync(&pdev->dev);
755 of_platform_depopulate(&pdev->dev);
756 stm32_adc_irq_remove(pdev, priv);
757 stm32_adc_core_hw_stop(&pdev->dev);
758 pm_runtime_disable(&pdev->dev);
759 pm_runtime_set_suspended(&pdev->dev);
760 pm_runtime_put_noidle(&pdev->dev);
761
762 return 0;
763}
764
765#if defined(CONFIG_PM)
766static int stm32_adc_core_runtime_suspend(struct device *dev)
767{
768 stm32_adc_core_hw_stop(dev);
769
770 return 0;
771}
772
773static int stm32_adc_core_runtime_resume(struct device *dev)
774{
775 return stm32_adc_core_hw_start(dev);
776}
777
778static int stm32_adc_core_runtime_idle(struct device *dev)
779{
780 pm_runtime_mark_last_busy(dev);
781
782 return 0;
783}
784#endif
785
786static const struct dev_pm_ops stm32_adc_core_pm_ops = {
787 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
788 pm_runtime_force_resume)
789 SET_RUNTIME_PM_OPS(stm32_adc_core_runtime_suspend,
790 stm32_adc_core_runtime_resume,
791 stm32_adc_core_runtime_idle)
792};
793
794static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
795 .regs = &stm32f4_adc_common_regs,
796 .clk_sel = stm32f4_adc_clk_sel,
797 .max_clk_rate_hz = 36000000,
798 .num_irqs = 1,
799};
800
801static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
802 .regs = &stm32h7_adc_common_regs,
803 .clk_sel = stm32h7_adc_clk_sel,
804 .max_clk_rate_hz = 36000000,
805 .has_syscfg = HAS_VBOOSTER,
806 .num_irqs = 1,
807};
808
809static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
810 .regs = &stm32h7_adc_common_regs,
811 .clk_sel = stm32h7_adc_clk_sel,
812 .max_clk_rate_hz = 40000000,
813 .has_syscfg = HAS_VBOOSTER | HAS_ANASWVDD,
814 .num_irqs = 2,
815};
816
817static const struct of_device_id stm32_adc_of_match[] = {
818 {
819 .compatible = "st,stm32f4-adc-core",
820 .data = (void *)&stm32f4_adc_priv_cfg
821 }, {
822 .compatible = "st,stm32h7-adc-core",
823 .data = (void *)&stm32h7_adc_priv_cfg
824 }, {
825 .compatible = "st,stm32mp1-adc-core",
826 .data = (void *)&stm32mp1_adc_priv_cfg
827 }, {
828 },
829};
830MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
831
832static struct platform_driver stm32_adc_driver = {
833 .probe = stm32_adc_probe,
834 .remove = stm32_adc_remove,
835 .driver = {
836 .name = "stm32-adc-core",
837 .of_match_table = stm32_adc_of_match,
838 .pm = &stm32_adc_core_pm_ops,
839 },
840};
841module_platform_driver(stm32_adc_driver);
842
843MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
844MODULE_DESCRIPTION("STMicroelectronics STM32 ADC core driver");
845MODULE_LICENSE("GPL v2");
846MODULE_ALIAS("platform:stm32-adc-core");