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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6
7#include <linux/arm-smccc.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/hdmi.h>
11#include <linux/i2c.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/mfd/syscon.h>
15#include <linux/of_platform.h>
16#include <linux/of.h>
17#include <linux/of_gpio.h>
18#include <linux/of_graph.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22
23#include <sound/hdmi-codec.h>
24
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc.h>
27#include <drm/drm_edid.h>
28#include <drm/drm_print.h>
29#include <drm/drm_probe_helper.h>
30
31#include "mtk_cec.h"
32#include "mtk_hdmi.h"
33#include "mtk_hdmi_regs.h"
34
35#define NCTS_BYTES 7
36
37enum mtk_hdmi_clk_id {
38 MTK_HDMI_CLK_HDMI_PIXEL,
39 MTK_HDMI_CLK_HDMI_PLL,
40 MTK_HDMI_CLK_AUD_BCLK,
41 MTK_HDMI_CLK_AUD_SPDIF,
42 MTK_HDMI_CLK_COUNT
43};
44
45enum hdmi_aud_input_type {
46 HDMI_AUD_INPUT_I2S = 0,
47 HDMI_AUD_INPUT_SPDIF,
48};
49
50enum hdmi_aud_i2s_fmt {
51 HDMI_I2S_MODE_RJT_24BIT = 0,
52 HDMI_I2S_MODE_RJT_16BIT,
53 HDMI_I2S_MODE_LJT_24BIT,
54 HDMI_I2S_MODE_LJT_16BIT,
55 HDMI_I2S_MODE_I2S_24BIT,
56 HDMI_I2S_MODE_I2S_16BIT
57};
58
59enum hdmi_aud_mclk {
60 HDMI_AUD_MCLK_128FS,
61 HDMI_AUD_MCLK_192FS,
62 HDMI_AUD_MCLK_256FS,
63 HDMI_AUD_MCLK_384FS,
64 HDMI_AUD_MCLK_512FS,
65 HDMI_AUD_MCLK_768FS,
66 HDMI_AUD_MCLK_1152FS,
67};
68
69enum hdmi_aud_channel_type {
70 HDMI_AUD_CHAN_TYPE_1_0 = 0,
71 HDMI_AUD_CHAN_TYPE_1_1,
72 HDMI_AUD_CHAN_TYPE_2_0,
73 HDMI_AUD_CHAN_TYPE_2_1,
74 HDMI_AUD_CHAN_TYPE_3_0,
75 HDMI_AUD_CHAN_TYPE_3_1,
76 HDMI_AUD_CHAN_TYPE_4_0,
77 HDMI_AUD_CHAN_TYPE_4_1,
78 HDMI_AUD_CHAN_TYPE_5_0,
79 HDMI_AUD_CHAN_TYPE_5_1,
80 HDMI_AUD_CHAN_TYPE_6_0,
81 HDMI_AUD_CHAN_TYPE_6_1,
82 HDMI_AUD_CHAN_TYPE_7_0,
83 HDMI_AUD_CHAN_TYPE_7_1,
84 HDMI_AUD_CHAN_TYPE_3_0_LRS,
85 HDMI_AUD_CHAN_TYPE_3_1_LRS,
86 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
87 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
88 HDMI_AUD_CHAN_TYPE_6_1_CS,
89 HDMI_AUD_CHAN_TYPE_6_1_CH,
90 HDMI_AUD_CHAN_TYPE_6_1_OH,
91 HDMI_AUD_CHAN_TYPE_6_1_CHR,
92 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
93 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
94 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
95 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
96 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
97 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
98 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
99 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
100 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
101 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
102 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
103 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
104 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
105 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
106 HDMI_AUD_CHAN_TYPE_6_0_CS,
107 HDMI_AUD_CHAN_TYPE_6_0_CH,
108 HDMI_AUD_CHAN_TYPE_6_0_OH,
109 HDMI_AUD_CHAN_TYPE_6_0_CHR,
110 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
111 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
112 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
113 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
114 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
115 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
116 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
117 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
118 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
119 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
120 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
121 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
122 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
123 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
124 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
125 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
126};
127
128enum hdmi_aud_channel_swap_type {
129 HDMI_AUD_SWAP_LR,
130 HDMI_AUD_SWAP_LFE_CC,
131 HDMI_AUD_SWAP_LSRS,
132 HDMI_AUD_SWAP_RLS_RRS,
133 HDMI_AUD_SWAP_LR_STATUS,
134};
135
136struct hdmi_audio_param {
137 enum hdmi_audio_coding_type aud_codec;
138 enum hdmi_audio_sample_size aud_sampe_size;
139 enum hdmi_aud_input_type aud_input_type;
140 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
141 enum hdmi_aud_mclk aud_mclk;
142 enum hdmi_aud_channel_type aud_input_chan_type;
143 struct hdmi_codec_params codec_params;
144};
145
146struct mtk_hdmi {
147 struct drm_bridge bridge;
148 struct drm_bridge *next_bridge;
149 struct drm_connector conn;
150 struct device *dev;
151 struct phy *phy;
152 struct device *cec_dev;
153 struct i2c_adapter *ddc_adpt;
154 struct clk *clk[MTK_HDMI_CLK_COUNT];
155 struct drm_display_mode mode;
156 bool dvi_mode;
157 u32 min_clock;
158 u32 max_clock;
159 u32 max_hdisplay;
160 u32 max_vdisplay;
161 u32 ibias;
162 u32 ibias_up;
163 struct regmap *sys_regmap;
164 unsigned int sys_offset;
165 void __iomem *regs;
166 enum hdmi_colorspace csp;
167 struct hdmi_audio_param aud_param;
168 bool audio_enable;
169 bool powered;
170 bool enabled;
171};
172
173static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
174{
175 return container_of(b, struct mtk_hdmi, bridge);
176}
177
178static inline struct mtk_hdmi *hdmi_ctx_from_conn(struct drm_connector *c)
179{
180 return container_of(c, struct mtk_hdmi, conn);
181}
182
183static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
184{
185 return readl(hdmi->regs + offset);
186}
187
188static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
189{
190 writel(val, hdmi->regs + offset);
191}
192
193static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
194{
195 void __iomem *reg = hdmi->regs + offset;
196 u32 tmp;
197
198 tmp = readl(reg);
199 tmp &= ~bits;
200 writel(tmp, reg);
201}
202
203static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
204{
205 void __iomem *reg = hdmi->regs + offset;
206 u32 tmp;
207
208 tmp = readl(reg);
209 tmp |= bits;
210 writel(tmp, reg);
211}
212
213static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
214{
215 void __iomem *reg = hdmi->regs + offset;
216 u32 tmp;
217
218 tmp = readl(reg);
219 tmp = (tmp & ~mask) | (val & mask);
220 writel(tmp, reg);
221}
222
223static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
224{
225 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
226 VIDEO_SOURCE_SEL);
227}
228
229static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
230{
231 struct arm_smccc_res res;
232 struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
233
234 /*
235 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
236 * output. This bit can only be controlled in ARM supervisor mode.
237 * The ARM trusted firmware provides an API for the HDMI driver to set
238 * this control bit to enable HDMI output in supervisor mode.
239 */
240 if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
241 regmap_update_bits(hdmi->sys_regmap,
242 hdmi->sys_offset + HDMI_SYS_CFG20,
243 0x80008005, enable ? 0x80000005 : 0x8000);
244 else
245 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
246 0x80000000, 0, 0, 0, 0, 0, &res);
247
248 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
249 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
250 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
251 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
252}
253
254static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
255{
256 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
257 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
258}
259
260static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
261{
262 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
263}
264
265static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
266{
267 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
268}
269
270static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
271{
272 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
273 HDMI_RST, HDMI_RST);
274 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
275 HDMI_RST, 0);
276 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
277 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
278 ANLG_ON, ANLG_ON);
279}
280
281static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
282{
283 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
284 CFG2_NOTICE_EN);
285}
286
287static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
288{
289 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
290}
291
292static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
293{
294 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
295}
296
297static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
298 u8 len)
299{
300 u32 ctrl_reg = GRL_CTRL;
301 int i;
302 u8 *frame_data;
303 enum hdmi_infoframe_type frame_type;
304 u8 frame_ver;
305 u8 frame_len;
306 u8 checksum;
307 int ctrl_frame_en = 0;
308
309 frame_type = *buffer;
310 buffer += 1;
311 frame_ver = *buffer;
312 buffer += 1;
313 frame_len = *buffer;
314 buffer += 1;
315 checksum = *buffer;
316 buffer += 1;
317 frame_data = buffer;
318
319 dev_dbg(hdmi->dev,
320 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
321 frame_type, frame_ver, frame_len, checksum);
322
323 switch (frame_type) {
324 case HDMI_INFOFRAME_TYPE_AVI:
325 ctrl_frame_en = CTRL_AVI_EN;
326 ctrl_reg = GRL_CTRL;
327 break;
328 case HDMI_INFOFRAME_TYPE_SPD:
329 ctrl_frame_en = CTRL_SPD_EN;
330 ctrl_reg = GRL_CTRL;
331 break;
332 case HDMI_INFOFRAME_TYPE_AUDIO:
333 ctrl_frame_en = CTRL_AUDIO_EN;
334 ctrl_reg = GRL_CTRL;
335 break;
336 case HDMI_INFOFRAME_TYPE_VENDOR:
337 ctrl_frame_en = VS_EN;
338 ctrl_reg = GRL_ACP_ISRC_CTRL;
339 break;
340 default:
341 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
342 return;
343 }
344 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
345 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
346 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
347 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
348
349 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
350 for (i = 0; i < frame_len; i++)
351 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
352
353 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
354}
355
356static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
357{
358 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
359 AUDIO_PACKET_OFF);
360}
361
362static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
363{
364 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
365 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
366 usleep_range(2000, 4000);
367 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
368 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
369}
370
371static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
372{
373 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
374 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
375 COLOR_8BIT_MODE);
376}
377
378static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
379{
380 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
381 usleep_range(2000, 4000);
382 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
383}
384
385static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
386{
387 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
388 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
389 usleep_range(2000, 4000);
390 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
391 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
392}
393
394static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
395{
396 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
397 CTS_CTRL_SOFT);
398}
399
400static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
401 bool enable)
402{
403 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
404 NCTS_WRI_ANYTIME);
405}
406
407static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
408 struct drm_display_mode *mode)
409{
410 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
411
412 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
413 mode->clock == 74250 &&
414 mode->vdisplay == 1080)
415 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
416 else
417 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
418}
419
420static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
421 enum hdmi_aud_channel_swap_type swap)
422{
423 u8 swap_bit;
424
425 switch (swap) {
426 case HDMI_AUD_SWAP_LR:
427 swap_bit = LR_SWAP;
428 break;
429 case HDMI_AUD_SWAP_LFE_CC:
430 swap_bit = LFE_CC_SWAP;
431 break;
432 case HDMI_AUD_SWAP_LSRS:
433 swap_bit = LSRS_SWAP;
434 break;
435 case HDMI_AUD_SWAP_RLS_RRS:
436 swap_bit = RLS_RRS_SWAP;
437 break;
438 case HDMI_AUD_SWAP_LR_STATUS:
439 swap_bit = LR_STATUS_SWAP;
440 break;
441 default:
442 swap_bit = LFE_CC_SWAP;
443 break;
444 }
445 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
446}
447
448static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
449 enum hdmi_audio_sample_size bit_num)
450{
451 u32 val;
452
453 switch (bit_num) {
454 case HDMI_AUDIO_SAMPLE_SIZE_16:
455 val = AOUT_16BIT;
456 break;
457 case HDMI_AUDIO_SAMPLE_SIZE_20:
458 val = AOUT_20BIT;
459 break;
460 case HDMI_AUDIO_SAMPLE_SIZE_24:
461 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
462 val = AOUT_24BIT;
463 break;
464 }
465
466 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
467}
468
469static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
470 enum hdmi_aud_i2s_fmt i2s_fmt)
471{
472 u32 val;
473
474 val = mtk_hdmi_read(hdmi, GRL_CFG0);
475 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
476
477 switch (i2s_fmt) {
478 case HDMI_I2S_MODE_RJT_24BIT:
479 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
480 break;
481 case HDMI_I2S_MODE_RJT_16BIT:
482 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
483 break;
484 case HDMI_I2S_MODE_LJT_24BIT:
485 default:
486 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
487 break;
488 case HDMI_I2S_MODE_LJT_16BIT:
489 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
490 break;
491 case HDMI_I2S_MODE_I2S_24BIT:
492 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
493 break;
494 case HDMI_I2S_MODE_I2S_16BIT:
495 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
496 break;
497 }
498 mtk_hdmi_write(hdmi, GRL_CFG0, val);
499}
500
501static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
502{
503 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
504 u8 val;
505
506 /* Disable high bitrate, set DST packet normal/double */
507 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
508
509 if (dst)
510 val = DST_NORMAL_DOUBLE | SACD_DST;
511 else
512 val = 0;
513
514 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
515}
516
517static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
518 enum hdmi_aud_channel_type channel_type,
519 u8 channel_count)
520{
521 unsigned int ch_switch;
522 u8 i2s_uv;
523
524 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
525 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
526 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
527 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
528
529 if (channel_count == 2) {
530 i2s_uv = I2S_UV_CH_EN(0);
531 } else if (channel_count == 3 || channel_count == 4) {
532 if (channel_count == 4 &&
533 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
534 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
535 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
536 else
537 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
538 } else if (channel_count == 6 || channel_count == 5) {
539 if (channel_count == 6 &&
540 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
541 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
542 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
543 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
544 } else {
545 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
546 I2S_UV_CH_EN(0);
547 }
548 } else if (channel_count == 8 || channel_count == 7) {
549 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
550 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
551 } else {
552 i2s_uv = I2S_UV_CH_EN(0);
553 }
554
555 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
556 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
557 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
558 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
559}
560
561static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
562 enum hdmi_aud_input_type input_type)
563{
564 u32 val;
565
566 val = mtk_hdmi_read(hdmi, GRL_CFG1);
567 if (input_type == HDMI_AUD_INPUT_I2S &&
568 (val & CFG1_SPDIF) == CFG1_SPDIF) {
569 val &= ~CFG1_SPDIF;
570 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
571 (val & CFG1_SPDIF) == 0) {
572 val |= CFG1_SPDIF;
573 }
574 mtk_hdmi_write(hdmi, GRL_CFG1, val);
575}
576
577static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
578 u8 *channel_status)
579{
580 int i;
581
582 for (i = 0; i < 5; i++) {
583 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
584 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
585 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
586 }
587 for (; i < 24; i++) {
588 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
589 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
590 }
591}
592
593static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
594{
595 u32 val;
596
597 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
598 if (val & MIX_CTRL_SRC_EN) {
599 val &= ~MIX_CTRL_SRC_EN;
600 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
601 usleep_range(255, 512);
602 val |= MIX_CTRL_SRC_EN;
603 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
604 }
605}
606
607static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
608{
609 u32 val;
610
611 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
612 val &= ~MIX_CTRL_SRC_EN;
613 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
614 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
615}
616
617static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
618 enum hdmi_aud_mclk mclk)
619{
620 u32 val;
621
622 val = mtk_hdmi_read(hdmi, GRL_CFG5);
623 val &= CFG5_CD_RATIO_MASK;
624
625 switch (mclk) {
626 case HDMI_AUD_MCLK_128FS:
627 val |= CFG5_FS128;
628 break;
629 case HDMI_AUD_MCLK_256FS:
630 val |= CFG5_FS256;
631 break;
632 case HDMI_AUD_MCLK_384FS:
633 val |= CFG5_FS384;
634 break;
635 case HDMI_AUD_MCLK_512FS:
636 val |= CFG5_FS512;
637 break;
638 case HDMI_AUD_MCLK_768FS:
639 val |= CFG5_FS768;
640 break;
641 default:
642 val |= CFG5_FS256;
643 break;
644 }
645 mtk_hdmi_write(hdmi, GRL_CFG5, val);
646}
647
648struct hdmi_acr_n {
649 unsigned int clock;
650 unsigned int n[3];
651};
652
653/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
654static const struct hdmi_acr_n hdmi_rec_n_table[] = {
655 /* Clock, N: 32kHz 44.1kHz 48kHz */
656 { 25175, { 4576, 7007, 6864 } },
657 { 74176, { 11648, 17836, 11648 } },
658 { 148352, { 11648, 8918, 5824 } },
659 { 296703, { 5824, 4459, 5824 } },
660 { 297000, { 3072, 4704, 5120 } },
661 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
662};
663
664/**
665 * hdmi_recommended_n() - Return N value recommended by HDMI specification
666 * @freq: audio sample rate in Hz
667 * @clock: rounded TMDS clock in kHz
668 */
669static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
670{
671 const struct hdmi_acr_n *recommended;
672 unsigned int i;
673
674 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
675 if (clock == hdmi_rec_n_table[i].clock)
676 break;
677 }
678 recommended = hdmi_rec_n_table + i;
679
680 switch (freq) {
681 case 32000:
682 return recommended->n[0];
683 case 44100:
684 return recommended->n[1];
685 case 48000:
686 return recommended->n[2];
687 case 88200:
688 return recommended->n[1] * 2;
689 case 96000:
690 return recommended->n[2] * 2;
691 case 176400:
692 return recommended->n[1] * 4;
693 case 192000:
694 return recommended->n[2] * 4;
695 default:
696 return (128 * freq) / 1000;
697 }
698}
699
700static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
701{
702 switch (clock) {
703 case 25175:
704 return 25174825; /* 25.2/1.001 MHz */
705 case 74176:
706 return 74175824; /* 74.25/1.001 MHz */
707 case 148352:
708 return 148351648; /* 148.5/1.001 MHz */
709 case 296703:
710 return 296703297; /* 297/1.001 MHz */
711 default:
712 return clock * 1000;
713 }
714}
715
716static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
717 unsigned int tmds_clock, unsigned int n)
718{
719 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
720 128 * audio_sample_rate);
721}
722
723static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
724 unsigned int cts)
725{
726 unsigned char val[NCTS_BYTES];
727 int i;
728
729 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
730 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
731 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
732 memset(val, 0, sizeof(val));
733
734 val[0] = (cts >> 24) & 0xff;
735 val[1] = (cts >> 16) & 0xff;
736 val[2] = (cts >> 8) & 0xff;
737 val[3] = cts & 0xff;
738
739 val[4] = (n >> 16) & 0xff;
740 val[5] = (n >> 8) & 0xff;
741 val[6] = n & 0xff;
742
743 for (i = 0; i < NCTS_BYTES; i++)
744 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
745}
746
747static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
748 unsigned int sample_rate,
749 unsigned int clock)
750{
751 unsigned int n, cts;
752
753 n = hdmi_recommended_n(sample_rate, clock);
754 cts = hdmi_expected_cts(sample_rate, clock, n);
755
756 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
757 __func__, sample_rate, clock, n, cts);
758
759 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
760 AUDIO_I2S_NCTS_SEL);
761 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
762}
763
764static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
765{
766 switch (channel_type) {
767 case HDMI_AUD_CHAN_TYPE_1_0:
768 case HDMI_AUD_CHAN_TYPE_1_1:
769 case HDMI_AUD_CHAN_TYPE_2_0:
770 return 2;
771 case HDMI_AUD_CHAN_TYPE_2_1:
772 case HDMI_AUD_CHAN_TYPE_3_0:
773 return 3;
774 case HDMI_AUD_CHAN_TYPE_3_1:
775 case HDMI_AUD_CHAN_TYPE_4_0:
776 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
777 return 4;
778 case HDMI_AUD_CHAN_TYPE_4_1:
779 case HDMI_AUD_CHAN_TYPE_5_0:
780 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
781 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
782 return 5;
783 case HDMI_AUD_CHAN_TYPE_5_1:
784 case HDMI_AUD_CHAN_TYPE_6_0:
785 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
786 case HDMI_AUD_CHAN_TYPE_6_0_CS:
787 case HDMI_AUD_CHAN_TYPE_6_0_CH:
788 case HDMI_AUD_CHAN_TYPE_6_0_OH:
789 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
790 return 6;
791 case HDMI_AUD_CHAN_TYPE_6_1:
792 case HDMI_AUD_CHAN_TYPE_6_1_CS:
793 case HDMI_AUD_CHAN_TYPE_6_1_CH:
794 case HDMI_AUD_CHAN_TYPE_6_1_OH:
795 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
796 case HDMI_AUD_CHAN_TYPE_7_0:
797 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
798 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
799 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
800 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
801 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
802 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
803 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
804 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
805 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
806 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
807 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
808 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
809 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
810 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
811 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
812 return 7;
813 case HDMI_AUD_CHAN_TYPE_7_1:
814 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
815 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
816 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
817 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
818 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
819 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
820 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
821 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
822 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
823 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
824 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
825 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
826 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
827 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
828 return 8;
829 default:
830 return 2;
831 }
832}
833
834static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
835{
836 unsigned long rate;
837 int ret;
838
839 /* The DPI driver already should have set TVDPLL to the correct rate */
840 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
841 if (ret) {
842 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
843 ret);
844 return ret;
845 }
846
847 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
848
849 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
850 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
851 rate);
852 else
853 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
854
855 mtk_hdmi_hw_config_sys(hdmi);
856 mtk_hdmi_hw_set_deep_color_mode(hdmi);
857 return 0;
858}
859
860static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
861 struct drm_display_mode *mode)
862{
863 mtk_hdmi_hw_reset(hdmi);
864 mtk_hdmi_hw_enable_notice(hdmi, true);
865 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
866 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
867 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
868
869 mtk_hdmi_hw_msic_setting(hdmi, mode);
870}
871
872static int mtk_hdmi_aud_enable_packet(struct mtk_hdmi *hdmi, bool enable)
873{
874 mtk_hdmi_hw_send_aud_packet(hdmi, enable);
875 return 0;
876}
877
878static int mtk_hdmi_aud_on_off_hw_ncts(struct mtk_hdmi *hdmi, bool on)
879{
880 mtk_hdmi_hw_ncts_enable(hdmi, on);
881 return 0;
882}
883
884static int mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
885{
886 enum hdmi_aud_channel_type chan_type;
887 u8 chan_count;
888 bool dst;
889
890 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
891 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
892
893 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
894 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
895 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
896 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
897 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
898 }
899
900 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
901 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
902
903 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
904 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
905 mtk_hdmi_hw_audio_config(hdmi, dst);
906
907 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
908 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
909 else
910 chan_type = hdmi->aud_param.aud_input_chan_type;
911 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
912 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
913 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
914
915 return 0;
916}
917
918static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
919 struct drm_display_mode *display_mode)
920{
921 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
922
923 mtk_hdmi_aud_on_off_hw_ncts(hdmi, false);
924 mtk_hdmi_hw_aud_src_disable(hdmi);
925 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
926
927 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
928 switch (sample_rate) {
929 case 32000:
930 case 44100:
931 case 48000:
932 case 88200:
933 case 96000:
934 break;
935 default:
936 return -EINVAL;
937 }
938 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
939 } else {
940 switch (sample_rate) {
941 case 32000:
942 case 44100:
943 case 48000:
944 break;
945 default:
946 return -EINVAL;
947 }
948 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
949 }
950
951 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
952
953 mtk_hdmi_hw_aud_src_reenable(hdmi);
954 return 0;
955}
956
957static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
958 struct drm_display_mode *display_mode)
959{
960 mtk_hdmi_hw_aud_mute(hdmi);
961 mtk_hdmi_aud_enable_packet(hdmi, false);
962
963 mtk_hdmi_aud_set_input(hdmi);
964 mtk_hdmi_aud_set_src(hdmi, display_mode);
965 mtk_hdmi_hw_aud_set_channel_status(hdmi,
966 hdmi->aud_param.codec_params.iec.status);
967
968 usleep_range(50, 100);
969
970 mtk_hdmi_aud_on_off_hw_ncts(hdmi, true);
971 mtk_hdmi_aud_enable_packet(hdmi, true);
972 mtk_hdmi_hw_aud_unmute(hdmi);
973 return 0;
974}
975
976static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
977 struct drm_display_mode *mode)
978{
979 struct hdmi_avi_infoframe frame;
980 u8 buffer[17];
981 ssize_t err;
982
983 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
984 &hdmi->conn, mode);
985 if (err < 0) {
986 dev_err(hdmi->dev,
987 "Failed to get AVI infoframe from mode: %zd\n", err);
988 return err;
989 }
990
991 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
992 if (err < 0) {
993 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
994 return err;
995 }
996
997 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
998 return 0;
999}
1000
1001static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
1002 const char *vendor,
1003 const char *product)
1004{
1005 struct hdmi_spd_infoframe frame;
1006 u8 buffer[29];
1007 ssize_t err;
1008
1009 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1010 if (err < 0) {
1011 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1012 err);
1013 return err;
1014 }
1015
1016 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1017 if (err < 0) {
1018 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1019 return err;
1020 }
1021
1022 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1023 return 0;
1024}
1025
1026static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1027{
1028 struct hdmi_audio_infoframe frame;
1029 u8 buffer[14];
1030 ssize_t err;
1031
1032 err = hdmi_audio_infoframe_init(&frame);
1033 if (err < 0) {
1034 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1035 err);
1036 return err;
1037 }
1038
1039 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1040 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1041 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1042 frame.channels = mtk_hdmi_aud_get_chnl_count(
1043 hdmi->aud_param.aud_input_chan_type);
1044
1045 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1046 if (err < 0) {
1047 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1048 err);
1049 return err;
1050 }
1051
1052 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1053 return 0;
1054}
1055
1056static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1057 struct drm_display_mode *mode)
1058{
1059 struct hdmi_vendor_infoframe frame;
1060 u8 buffer[10];
1061 ssize_t err;
1062
1063 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1064 &hdmi->conn, mode);
1065 if (err) {
1066 dev_err(hdmi->dev,
1067 "Failed to get vendor infoframe from mode: %zd\n", err);
1068 return err;
1069 }
1070
1071 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1072 if (err < 0) {
1073 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1074 err);
1075 return err;
1076 }
1077
1078 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1079 return 0;
1080}
1081
1082static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1083{
1084 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1085
1086 hdmi->csp = HDMI_COLORSPACE_RGB;
1087 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1088 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1089 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1090 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1091 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1092 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1093
1094 return 0;
1095}
1096
1097static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1098{
1099 mtk_hdmi_aud_enable_packet(hdmi, true);
1100 hdmi->audio_enable = true;
1101}
1102
1103static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1104{
1105 mtk_hdmi_aud_enable_packet(hdmi, false);
1106 hdmi->audio_enable = false;
1107}
1108
1109static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1110 struct hdmi_audio_param *param)
1111{
1112 if (!hdmi->audio_enable) {
1113 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1114 return -EINVAL;
1115 }
1116 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1117 param->aud_codec, param->aud_input_type,
1118 param->aud_input_chan_type, param->codec_params.sample_rate);
1119 memcpy(&hdmi->aud_param, param, sizeof(*param));
1120 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1121}
1122
1123static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1124 struct drm_display_mode *mode)
1125{
1126 int ret;
1127
1128 mtk_hdmi_hw_vid_black(hdmi, true);
1129 mtk_hdmi_hw_aud_mute(hdmi);
1130 mtk_hdmi_hw_send_av_mute(hdmi);
1131 phy_power_off(hdmi->phy);
1132
1133 ret = mtk_hdmi_video_change_vpll(hdmi,
1134 mode->clock * 1000);
1135 if (ret) {
1136 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1137 return ret;
1138 }
1139 mtk_hdmi_video_set_display_mode(hdmi, mode);
1140
1141 phy_power_on(hdmi->phy);
1142 mtk_hdmi_aud_output_config(hdmi, mode);
1143
1144 mtk_hdmi_hw_vid_black(hdmi, false);
1145 mtk_hdmi_hw_aud_unmute(hdmi);
1146 mtk_hdmi_hw_send_av_unmute(hdmi);
1147
1148 return 0;
1149}
1150
1151static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1152 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1153 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1154 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1155 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1156};
1157
1158static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1159 struct device_node *np)
1160{
1161 int i;
1162
1163 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1164 hdmi->clk[i] = of_clk_get_by_name(np,
1165 mtk_hdmi_clk_names[i]);
1166 if (IS_ERR(hdmi->clk[i]))
1167 return PTR_ERR(hdmi->clk[i]);
1168 }
1169 return 0;
1170}
1171
1172static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1173{
1174 int ret;
1175
1176 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1177 if (ret)
1178 return ret;
1179
1180 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1181 if (ret)
1182 goto err;
1183
1184 return 0;
1185err:
1186 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1187 return ret;
1188}
1189
1190static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1191{
1192 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1193 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1194}
1195
1196static enum drm_connector_status hdmi_conn_detect(struct drm_connector *conn,
1197 bool force)
1198{
1199 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1200
1201 return mtk_cec_hpd_high(hdmi->cec_dev) ?
1202 connector_status_connected : connector_status_disconnected;
1203}
1204
1205static void hdmi_conn_destroy(struct drm_connector *conn)
1206{
1207 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1208
1209 mtk_cec_set_hpd_event(hdmi->cec_dev, NULL, NULL);
1210
1211 drm_connector_cleanup(conn);
1212}
1213
1214static int mtk_hdmi_conn_get_modes(struct drm_connector *conn)
1215{
1216 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1217 struct edid *edid;
1218 int ret;
1219
1220 if (!hdmi->ddc_adpt)
1221 return -ENODEV;
1222
1223 edid = drm_get_edid(conn, hdmi->ddc_adpt);
1224 if (!edid)
1225 return -ENODEV;
1226
1227 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1228
1229 drm_connector_update_edid_property(conn, edid);
1230
1231 ret = drm_add_edid_modes(conn, edid);
1232 kfree(edid);
1233 return ret;
1234}
1235
1236static int mtk_hdmi_conn_mode_valid(struct drm_connector *conn,
1237 struct drm_display_mode *mode)
1238{
1239 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1240
1241 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1242 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1243 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1244
1245 if (hdmi->bridge.next) {
1246 struct drm_display_mode adjusted_mode;
1247
1248 drm_mode_copy(&adjusted_mode, mode);
1249 if (!drm_bridge_mode_fixup(hdmi->bridge.next, mode,
1250 &adjusted_mode))
1251 return MODE_BAD;
1252 }
1253
1254 if (mode->clock < 27000)
1255 return MODE_CLOCK_LOW;
1256 if (mode->clock > 297000)
1257 return MODE_CLOCK_HIGH;
1258
1259 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1260}
1261
1262static struct drm_encoder *mtk_hdmi_conn_best_enc(struct drm_connector *conn)
1263{
1264 struct mtk_hdmi *hdmi = hdmi_ctx_from_conn(conn);
1265
1266 return hdmi->bridge.encoder;
1267}
1268
1269static const struct drm_connector_funcs mtk_hdmi_connector_funcs = {
1270 .detect = hdmi_conn_detect,
1271 .fill_modes = drm_helper_probe_single_connector_modes,
1272 .destroy = hdmi_conn_destroy,
1273 .reset = drm_atomic_helper_connector_reset,
1274 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1275 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1276};
1277
1278static const struct drm_connector_helper_funcs
1279 mtk_hdmi_connector_helper_funcs = {
1280 .get_modes = mtk_hdmi_conn_get_modes,
1281 .mode_valid = mtk_hdmi_conn_mode_valid,
1282 .best_encoder = mtk_hdmi_conn_best_enc,
1283};
1284
1285static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1286{
1287 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1288
1289 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
1290 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1291}
1292
1293/*
1294 * Bridge callbacks
1295 */
1296
1297static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge)
1298{
1299 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1300 int ret;
1301
1302 ret = drm_connector_init(bridge->encoder->dev, &hdmi->conn,
1303 &mtk_hdmi_connector_funcs,
1304 DRM_MODE_CONNECTOR_HDMIA);
1305 if (ret) {
1306 dev_err(hdmi->dev, "Failed to initialize connector: %d\n", ret);
1307 return ret;
1308 }
1309 drm_connector_helper_add(&hdmi->conn, &mtk_hdmi_connector_helper_funcs);
1310
1311 hdmi->conn.polled = DRM_CONNECTOR_POLL_HPD;
1312 hdmi->conn.interlace_allowed = true;
1313 hdmi->conn.doublescan_allowed = false;
1314
1315 ret = drm_connector_attach_encoder(&hdmi->conn,
1316 bridge->encoder);
1317 if (ret) {
1318 dev_err(hdmi->dev,
1319 "Failed to attach connector to encoder: %d\n", ret);
1320 return ret;
1321 }
1322
1323 if (hdmi->next_bridge) {
1324 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1325 bridge);
1326 if (ret) {
1327 dev_err(hdmi->dev,
1328 "Failed to attach external bridge: %d\n", ret);
1329 return ret;
1330 }
1331 }
1332
1333 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1334
1335 return 0;
1336}
1337
1338static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1339 const struct drm_display_mode *mode,
1340 struct drm_display_mode *adjusted_mode)
1341{
1342 return true;
1343}
1344
1345static void mtk_hdmi_bridge_disable(struct drm_bridge *bridge)
1346{
1347 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1348
1349 if (!hdmi->enabled)
1350 return;
1351
1352 phy_power_off(hdmi->phy);
1353 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1354 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1355
1356 hdmi->enabled = false;
1357}
1358
1359static void mtk_hdmi_bridge_post_disable(struct drm_bridge *bridge)
1360{
1361 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1362
1363 if (!hdmi->powered)
1364 return;
1365
1366 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1367 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1368
1369 hdmi->powered = false;
1370}
1371
1372static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1373 const struct drm_display_mode *mode,
1374 const struct drm_display_mode *adjusted_mode)
1375{
1376 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1377
1378 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1379 adjusted_mode->name, adjusted_mode->hdisplay);
1380 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1381 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1382 adjusted_mode->htotal);
1383 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1384 adjusted_mode->hskew, adjusted_mode->vdisplay);
1385 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1386 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1387 adjusted_mode->vtotal);
1388 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1389 adjusted_mode->vscan, adjusted_mode->flags);
1390
1391 drm_mode_copy(&hdmi->mode, adjusted_mode);
1392}
1393
1394static void mtk_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
1395{
1396 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1397
1398 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1399 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1400
1401 hdmi->powered = true;
1402}
1403
1404static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1405 struct drm_display_mode *mode)
1406{
1407 mtk_hdmi_setup_audio_infoframe(hdmi);
1408 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1409 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1410 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1411 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1412}
1413
1414static void mtk_hdmi_bridge_enable(struct drm_bridge *bridge)
1415{
1416 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1417
1418 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1419 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1420 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1421 phy_power_on(hdmi->phy);
1422 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1423
1424 hdmi->enabled = true;
1425}
1426
1427static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1428 .attach = mtk_hdmi_bridge_attach,
1429 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1430 .disable = mtk_hdmi_bridge_disable,
1431 .post_disable = mtk_hdmi_bridge_post_disable,
1432 .mode_set = mtk_hdmi_bridge_mode_set,
1433 .pre_enable = mtk_hdmi_bridge_pre_enable,
1434 .enable = mtk_hdmi_bridge_enable,
1435};
1436
1437static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1438 struct platform_device *pdev)
1439{
1440 struct device *dev = &pdev->dev;
1441 struct device_node *np = dev->of_node;
1442 struct device_node *cec_np, *remote, *i2c_np;
1443 struct platform_device *cec_pdev;
1444 struct regmap *regmap;
1445 struct resource *mem;
1446 int ret;
1447
1448 ret = mtk_hdmi_get_all_clk(hdmi, np);
1449 if (ret) {
1450 dev_err(dev, "Failed to get clocks: %d\n", ret);
1451 return ret;
1452 }
1453
1454 /* The CEC module handles HDMI hotplug detection */
1455 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1456 if (!cec_np) {
1457 dev_err(dev, "Failed to find CEC node\n");
1458 return -EINVAL;
1459 }
1460
1461 cec_pdev = of_find_device_by_node(cec_np);
1462 if (!cec_pdev) {
1463 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1464 cec_np);
1465 of_node_put(cec_np);
1466 return -EPROBE_DEFER;
1467 }
1468 of_node_put(cec_np);
1469 hdmi->cec_dev = &cec_pdev->dev;
1470
1471 /*
1472 * The mediatek,syscon-hdmi property contains a phandle link to the
1473 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1474 * registers it contains.
1475 */
1476 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1477 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1478 &hdmi->sys_offset);
1479 if (IS_ERR(regmap))
1480 ret = PTR_ERR(regmap);
1481 if (ret) {
1482 dev_err(dev,
1483 "Failed to get system configuration registers: %d\n",
1484 ret);
1485 return ret;
1486 }
1487 hdmi->sys_regmap = regmap;
1488
1489 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1490 hdmi->regs = devm_ioremap_resource(dev, mem);
1491 if (IS_ERR(hdmi->regs))
1492 return PTR_ERR(hdmi->regs);
1493
1494 remote = of_graph_get_remote_node(np, 1, 0);
1495 if (!remote)
1496 return -EINVAL;
1497
1498 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1499 hdmi->next_bridge = of_drm_find_bridge(remote);
1500 if (!hdmi->next_bridge) {
1501 dev_err(dev, "Waiting for external bridge\n");
1502 of_node_put(remote);
1503 return -EPROBE_DEFER;
1504 }
1505 }
1506
1507 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1508 if (!i2c_np) {
1509 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1510 remote);
1511 of_node_put(remote);
1512 return -EINVAL;
1513 }
1514 of_node_put(remote);
1515
1516 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1517 of_node_put(i2c_np);
1518 if (!hdmi->ddc_adpt) {
1519 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1520 return -EINVAL;
1521 }
1522
1523 return 0;
1524}
1525
1526/*
1527 * HDMI audio codec callbacks
1528 */
1529
1530static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1531 struct hdmi_codec_daifmt *daifmt,
1532 struct hdmi_codec_params *params)
1533{
1534 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1535 struct hdmi_audio_param hdmi_params;
1536 unsigned int chan = params->cea.channels;
1537
1538 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1539 params->sample_rate, params->sample_width, chan);
1540
1541 if (!hdmi->bridge.encoder)
1542 return -ENODEV;
1543
1544 switch (chan) {
1545 case 2:
1546 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1547 break;
1548 case 4:
1549 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1550 break;
1551 case 6:
1552 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1553 break;
1554 case 8:
1555 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1556 break;
1557 default:
1558 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1559 return -EINVAL;
1560 }
1561
1562 switch (params->sample_rate) {
1563 case 32000:
1564 case 44100:
1565 case 48000:
1566 case 88200:
1567 case 96000:
1568 case 176400:
1569 case 192000:
1570 break;
1571 default:
1572 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1573 params->sample_rate);
1574 return -EINVAL;
1575 }
1576
1577 switch (daifmt->fmt) {
1578 case HDMI_I2S:
1579 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1580 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1581 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1582 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1583 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1584 break;
1585 case HDMI_SPDIF:
1586 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1587 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1588 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1589 break;
1590 default:
1591 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1592 daifmt->fmt);
1593 return -EINVAL;
1594 }
1595
1596 memcpy(&hdmi_params.codec_params, params,
1597 sizeof(hdmi_params.codec_params));
1598
1599 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1600
1601 return 0;
1602}
1603
1604static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1605{
1606 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1607
1608 dev_dbg(dev, "%s\n", __func__);
1609
1610 mtk_hdmi_audio_enable(hdmi);
1611
1612 return 0;
1613}
1614
1615static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1616{
1617 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1618
1619 dev_dbg(dev, "%s\n", __func__);
1620
1621 mtk_hdmi_audio_disable(hdmi);
1622}
1623
1624static int
1625mtk_hdmi_audio_digital_mute(struct device *dev, void *data, bool enable)
1626{
1627 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1628
1629 dev_dbg(dev, "%s(%d)\n", __func__, enable);
1630
1631 if (enable)
1632 mtk_hdmi_hw_aud_mute(hdmi);
1633 else
1634 mtk_hdmi_hw_aud_unmute(hdmi);
1635
1636 return 0;
1637}
1638
1639static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1640{
1641 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1642
1643 dev_dbg(dev, "%s\n", __func__);
1644
1645 memcpy(buf, hdmi->conn.eld, min(sizeof(hdmi->conn.eld), len));
1646
1647 return 0;
1648}
1649
1650static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1651 .hw_params = mtk_hdmi_audio_hw_params,
1652 .audio_startup = mtk_hdmi_audio_startup,
1653 .audio_shutdown = mtk_hdmi_audio_shutdown,
1654 .digital_mute = mtk_hdmi_audio_digital_mute,
1655 .get_eld = mtk_hdmi_audio_get_eld,
1656};
1657
1658static void mtk_hdmi_register_audio_driver(struct device *dev)
1659{
1660 struct hdmi_codec_pdata codec_data = {
1661 .ops = &mtk_hdmi_audio_codec_ops,
1662 .max_i2s_channels = 2,
1663 .i2s = 1,
1664 };
1665 struct platform_device *pdev;
1666
1667 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1668 PLATFORM_DEVID_AUTO, &codec_data,
1669 sizeof(codec_data));
1670 if (IS_ERR(pdev))
1671 return;
1672
1673 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1674}
1675
1676static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1677{
1678 struct mtk_hdmi *hdmi;
1679 struct device *dev = &pdev->dev;
1680 int ret;
1681
1682 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1683 if (!hdmi)
1684 return -ENOMEM;
1685
1686 hdmi->dev = dev;
1687
1688 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1689 if (ret)
1690 return ret;
1691
1692 hdmi->phy = devm_phy_get(dev, "hdmi");
1693 if (IS_ERR(hdmi->phy)) {
1694 ret = PTR_ERR(hdmi->phy);
1695 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1696 return ret;
1697 }
1698
1699 platform_set_drvdata(pdev, hdmi);
1700
1701 ret = mtk_hdmi_output_init(hdmi);
1702 if (ret) {
1703 dev_err(dev, "Failed to initialize hdmi output\n");
1704 return ret;
1705 }
1706
1707 mtk_hdmi_register_audio_driver(dev);
1708
1709 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1710 hdmi->bridge.of_node = pdev->dev.of_node;
1711 drm_bridge_add(&hdmi->bridge);
1712
1713 ret = mtk_hdmi_clk_enable_audio(hdmi);
1714 if (ret) {
1715 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1716 goto err_bridge_remove;
1717 }
1718
1719 dev_dbg(dev, "mediatek hdmi probe success\n");
1720 return 0;
1721
1722err_bridge_remove:
1723 drm_bridge_remove(&hdmi->bridge);
1724 return ret;
1725}
1726
1727static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1728{
1729 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1730
1731 drm_bridge_remove(&hdmi->bridge);
1732 mtk_hdmi_clk_disable_audio(hdmi);
1733 return 0;
1734}
1735
1736#ifdef CONFIG_PM_SLEEP
1737static int mtk_hdmi_suspend(struct device *dev)
1738{
1739 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1740
1741 mtk_hdmi_clk_disable_audio(hdmi);
1742 dev_dbg(dev, "hdmi suspend success!\n");
1743 return 0;
1744}
1745
1746static int mtk_hdmi_resume(struct device *dev)
1747{
1748 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1749 int ret = 0;
1750
1751 ret = mtk_hdmi_clk_enable_audio(hdmi);
1752 if (ret) {
1753 dev_err(dev, "hdmi resume failed!\n");
1754 return ret;
1755 }
1756
1757 dev_dbg(dev, "hdmi resume success!\n");
1758 return 0;
1759}
1760#endif
1761static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1762 mtk_hdmi_suspend, mtk_hdmi_resume);
1763
1764static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1765 { .compatible = "mediatek,mt8173-hdmi", },
1766 {}
1767};
1768
1769static struct platform_driver mtk_hdmi_driver = {
1770 .probe = mtk_drm_hdmi_probe,
1771 .remove = mtk_drm_hdmi_remove,
1772 .driver = {
1773 .name = "mediatek-drm-hdmi",
1774 .of_match_table = mtk_drm_hdmi_of_ids,
1775 .pm = &mtk_hdmi_pm_ops,
1776 },
1777};
1778
1779static struct platform_driver * const mtk_hdmi_drivers[] = {
1780 &mtk_hdmi_phy_driver,
1781 &mtk_hdmi_ddc_driver,
1782 &mtk_cec_driver,
1783 &mtk_hdmi_driver,
1784};
1785
1786static int __init mtk_hdmitx_init(void)
1787{
1788 return platform_register_drivers(mtk_hdmi_drivers,
1789 ARRAY_SIZE(mtk_hdmi_drivers));
1790}
1791
1792static void __exit mtk_hdmitx_exit(void)
1793{
1794 platform_unregister_drivers(mtk_hdmi_drivers,
1795 ARRAY_SIZE(mtk_hdmi_drivers));
1796}
1797
1798module_init(mtk_hdmitx_init);
1799module_exit(mtk_hdmitx_exit);
1800
1801MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1802MODULE_DESCRIPTION("MediaTek HDMI Driver");
1803MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6
7#include <linux/arm-smccc.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/hdmi.h>
11#include <linux/i2c.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/of_platform.h>
18#include <linux/of.h>
19#include <linux/of_gpio.h>
20#include <linux/of_graph.h>
21#include <linux/phy/phy.h>
22#include <linux/platform_device.h>
23#include <linux/regmap.h>
24
25#include <sound/hdmi-codec.h>
26
27#include <drm/drm_atomic_helper.h>
28#include <drm/drm_bridge.h>
29#include <drm/drm_crtc.h>
30#include <drm/drm_edid.h>
31#include <drm/drm_print.h>
32#include <drm/drm_probe_helper.h>
33
34#include "mtk_cec.h"
35#include "mtk_hdmi.h"
36#include "mtk_hdmi_regs.h"
37
38#define NCTS_BYTES 7
39
40enum mtk_hdmi_clk_id {
41 MTK_HDMI_CLK_HDMI_PIXEL,
42 MTK_HDMI_CLK_HDMI_PLL,
43 MTK_HDMI_CLK_AUD_BCLK,
44 MTK_HDMI_CLK_AUD_SPDIF,
45 MTK_HDMI_CLK_COUNT
46};
47
48enum hdmi_aud_input_type {
49 HDMI_AUD_INPUT_I2S = 0,
50 HDMI_AUD_INPUT_SPDIF,
51};
52
53enum hdmi_aud_i2s_fmt {
54 HDMI_I2S_MODE_RJT_24BIT = 0,
55 HDMI_I2S_MODE_RJT_16BIT,
56 HDMI_I2S_MODE_LJT_24BIT,
57 HDMI_I2S_MODE_LJT_16BIT,
58 HDMI_I2S_MODE_I2S_24BIT,
59 HDMI_I2S_MODE_I2S_16BIT
60};
61
62enum hdmi_aud_mclk {
63 HDMI_AUD_MCLK_128FS,
64 HDMI_AUD_MCLK_192FS,
65 HDMI_AUD_MCLK_256FS,
66 HDMI_AUD_MCLK_384FS,
67 HDMI_AUD_MCLK_512FS,
68 HDMI_AUD_MCLK_768FS,
69 HDMI_AUD_MCLK_1152FS,
70};
71
72enum hdmi_aud_channel_type {
73 HDMI_AUD_CHAN_TYPE_1_0 = 0,
74 HDMI_AUD_CHAN_TYPE_1_1,
75 HDMI_AUD_CHAN_TYPE_2_0,
76 HDMI_AUD_CHAN_TYPE_2_1,
77 HDMI_AUD_CHAN_TYPE_3_0,
78 HDMI_AUD_CHAN_TYPE_3_1,
79 HDMI_AUD_CHAN_TYPE_4_0,
80 HDMI_AUD_CHAN_TYPE_4_1,
81 HDMI_AUD_CHAN_TYPE_5_0,
82 HDMI_AUD_CHAN_TYPE_5_1,
83 HDMI_AUD_CHAN_TYPE_6_0,
84 HDMI_AUD_CHAN_TYPE_6_1,
85 HDMI_AUD_CHAN_TYPE_7_0,
86 HDMI_AUD_CHAN_TYPE_7_1,
87 HDMI_AUD_CHAN_TYPE_3_0_LRS,
88 HDMI_AUD_CHAN_TYPE_3_1_LRS,
89 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
90 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
91 HDMI_AUD_CHAN_TYPE_6_1_CS,
92 HDMI_AUD_CHAN_TYPE_6_1_CH,
93 HDMI_AUD_CHAN_TYPE_6_1_OH,
94 HDMI_AUD_CHAN_TYPE_6_1_CHR,
95 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
96 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
97 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
98 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
99 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
100 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
101 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
102 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
104 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
105 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
106 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
107 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
108 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
109 HDMI_AUD_CHAN_TYPE_6_0_CS,
110 HDMI_AUD_CHAN_TYPE_6_0_CH,
111 HDMI_AUD_CHAN_TYPE_6_0_OH,
112 HDMI_AUD_CHAN_TYPE_6_0_CHR,
113 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
114 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
115 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
116 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
117 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
118 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
119 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
120 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
122 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
123 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
124 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
125 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
126 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
127 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
128 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
129};
130
131enum hdmi_aud_channel_swap_type {
132 HDMI_AUD_SWAP_LR,
133 HDMI_AUD_SWAP_LFE_CC,
134 HDMI_AUD_SWAP_LSRS,
135 HDMI_AUD_SWAP_RLS_RRS,
136 HDMI_AUD_SWAP_LR_STATUS,
137};
138
139struct hdmi_audio_param {
140 enum hdmi_audio_coding_type aud_codec;
141 enum hdmi_audio_sample_size aud_sampe_size;
142 enum hdmi_aud_input_type aud_input_type;
143 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
144 enum hdmi_aud_mclk aud_mclk;
145 enum hdmi_aud_channel_type aud_input_chan_type;
146 struct hdmi_codec_params codec_params;
147};
148
149struct mtk_hdmi_conf {
150 bool tz_disabled;
151 bool cea_modes_only;
152 unsigned long max_mode_clock;
153};
154
155struct mtk_hdmi {
156 struct drm_bridge bridge;
157 struct drm_bridge *next_bridge;
158 struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
159 struct device *dev;
160 const struct mtk_hdmi_conf *conf;
161 struct phy *phy;
162 struct device *cec_dev;
163 struct i2c_adapter *ddc_adpt;
164 struct clk *clk[MTK_HDMI_CLK_COUNT];
165 struct drm_display_mode mode;
166 bool dvi_mode;
167 u32 min_clock;
168 u32 max_clock;
169 u32 max_hdisplay;
170 u32 max_vdisplay;
171 u32 ibias;
172 u32 ibias_up;
173 struct regmap *sys_regmap;
174 unsigned int sys_offset;
175 void __iomem *regs;
176 enum hdmi_colorspace csp;
177 struct hdmi_audio_param aud_param;
178 bool audio_enable;
179 bool powered;
180 bool enabled;
181 hdmi_codec_plugged_cb plugged_cb;
182 struct device *codec_dev;
183 struct mutex update_plugged_status_lock;
184};
185
186static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
187{
188 return container_of(b, struct mtk_hdmi, bridge);
189}
190
191static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
192{
193 return readl(hdmi->regs + offset);
194}
195
196static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
197{
198 writel(val, hdmi->regs + offset);
199}
200
201static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
202{
203 void __iomem *reg = hdmi->regs + offset;
204 u32 tmp;
205
206 tmp = readl(reg);
207 tmp &= ~bits;
208 writel(tmp, reg);
209}
210
211static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
212{
213 void __iomem *reg = hdmi->regs + offset;
214 u32 tmp;
215
216 tmp = readl(reg);
217 tmp |= bits;
218 writel(tmp, reg);
219}
220
221static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
222{
223 void __iomem *reg = hdmi->regs + offset;
224 u32 tmp;
225
226 tmp = readl(reg);
227 tmp = (tmp & ~mask) | (val & mask);
228 writel(tmp, reg);
229}
230
231static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
232{
233 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
234 VIDEO_SOURCE_SEL);
235}
236
237static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
238{
239 struct arm_smccc_res res;
240
241 /*
242 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
243 * output. This bit can only be controlled in ARM supervisor mode.
244 * The ARM trusted firmware provides an API for the HDMI driver to set
245 * this control bit to enable HDMI output in supervisor mode.
246 */
247 if (hdmi->conf && hdmi->conf->tz_disabled)
248 regmap_update_bits(hdmi->sys_regmap,
249 hdmi->sys_offset + HDMI_SYS_CFG20,
250 0x80008005, enable ? 0x80000005 : 0x8000);
251 else
252 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
253 0x80000000, 0, 0, 0, 0, 0, &res);
254
255 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
256 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
257 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
258 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
259}
260
261static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
262{
263 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
264 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
265}
266
267static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
268{
269 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
270}
271
272static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
273{
274 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
275}
276
277static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
278{
279 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
280 HDMI_RST, HDMI_RST);
281 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
282 HDMI_RST, 0);
283 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
284 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
285 ANLG_ON, ANLG_ON);
286}
287
288static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
289{
290 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
291 CFG2_NOTICE_EN);
292}
293
294static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
295{
296 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
297}
298
299static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
300{
301 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
302}
303
304static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
305 u8 len)
306{
307 u32 ctrl_reg = GRL_CTRL;
308 int i;
309 u8 *frame_data;
310 enum hdmi_infoframe_type frame_type;
311 u8 frame_ver;
312 u8 frame_len;
313 u8 checksum;
314 int ctrl_frame_en = 0;
315
316 frame_type = *buffer++;
317 frame_ver = *buffer++;
318 frame_len = *buffer++;
319 checksum = *buffer++;
320 frame_data = buffer;
321
322 dev_dbg(hdmi->dev,
323 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
324 frame_type, frame_ver, frame_len, checksum);
325
326 switch (frame_type) {
327 case HDMI_INFOFRAME_TYPE_AVI:
328 ctrl_frame_en = CTRL_AVI_EN;
329 ctrl_reg = GRL_CTRL;
330 break;
331 case HDMI_INFOFRAME_TYPE_SPD:
332 ctrl_frame_en = CTRL_SPD_EN;
333 ctrl_reg = GRL_CTRL;
334 break;
335 case HDMI_INFOFRAME_TYPE_AUDIO:
336 ctrl_frame_en = CTRL_AUDIO_EN;
337 ctrl_reg = GRL_CTRL;
338 break;
339 case HDMI_INFOFRAME_TYPE_VENDOR:
340 ctrl_frame_en = VS_EN;
341 ctrl_reg = GRL_ACP_ISRC_CTRL;
342 break;
343 default:
344 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
345 return;
346 }
347 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
348 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
349 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
350 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
351
352 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
353 for (i = 0; i < frame_len; i++)
354 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
355
356 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
357}
358
359static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
360{
361 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
362 AUDIO_PACKET_OFF);
363}
364
365static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
366{
367 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
368 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
369 usleep_range(2000, 4000);
370 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
371 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
372}
373
374static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
375{
376 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
377 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
378 COLOR_8BIT_MODE);
379}
380
381static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
382{
383 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
384 usleep_range(2000, 4000);
385 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
386}
387
388static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
389{
390 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
391 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
392 usleep_range(2000, 4000);
393 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
394 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
395}
396
397static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
398{
399 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
400 CTS_CTRL_SOFT);
401}
402
403static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
404 bool enable)
405{
406 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
407 NCTS_WRI_ANYTIME);
408}
409
410static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
411 struct drm_display_mode *mode)
412{
413 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
414
415 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
416 mode->clock == 74250 &&
417 mode->vdisplay == 1080)
418 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
419 else
420 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
421}
422
423static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
424 enum hdmi_aud_channel_swap_type swap)
425{
426 u8 swap_bit;
427
428 switch (swap) {
429 case HDMI_AUD_SWAP_LR:
430 swap_bit = LR_SWAP;
431 break;
432 case HDMI_AUD_SWAP_LFE_CC:
433 swap_bit = LFE_CC_SWAP;
434 break;
435 case HDMI_AUD_SWAP_LSRS:
436 swap_bit = LSRS_SWAP;
437 break;
438 case HDMI_AUD_SWAP_RLS_RRS:
439 swap_bit = RLS_RRS_SWAP;
440 break;
441 case HDMI_AUD_SWAP_LR_STATUS:
442 swap_bit = LR_STATUS_SWAP;
443 break;
444 default:
445 swap_bit = LFE_CC_SWAP;
446 break;
447 }
448 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
449}
450
451static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
452 enum hdmi_audio_sample_size bit_num)
453{
454 u32 val;
455
456 switch (bit_num) {
457 case HDMI_AUDIO_SAMPLE_SIZE_16:
458 val = AOUT_16BIT;
459 break;
460 case HDMI_AUDIO_SAMPLE_SIZE_20:
461 val = AOUT_20BIT;
462 break;
463 case HDMI_AUDIO_SAMPLE_SIZE_24:
464 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
465 val = AOUT_24BIT;
466 break;
467 }
468
469 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
470}
471
472static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
473 enum hdmi_aud_i2s_fmt i2s_fmt)
474{
475 u32 val;
476
477 val = mtk_hdmi_read(hdmi, GRL_CFG0);
478 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
479
480 switch (i2s_fmt) {
481 case HDMI_I2S_MODE_RJT_24BIT:
482 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
483 break;
484 case HDMI_I2S_MODE_RJT_16BIT:
485 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
486 break;
487 case HDMI_I2S_MODE_LJT_24BIT:
488 default:
489 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
490 break;
491 case HDMI_I2S_MODE_LJT_16BIT:
492 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
493 break;
494 case HDMI_I2S_MODE_I2S_24BIT:
495 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
496 break;
497 case HDMI_I2S_MODE_I2S_16BIT:
498 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
499 break;
500 }
501 mtk_hdmi_write(hdmi, GRL_CFG0, val);
502}
503
504static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
505{
506 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
507 u8 val;
508
509 /* Disable high bitrate, set DST packet normal/double */
510 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
511
512 if (dst)
513 val = DST_NORMAL_DOUBLE | SACD_DST;
514 else
515 val = 0;
516
517 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
518}
519
520static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
521 enum hdmi_aud_channel_type channel_type,
522 u8 channel_count)
523{
524 unsigned int ch_switch;
525 u8 i2s_uv;
526
527 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
528 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
529 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
530 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
531
532 if (channel_count == 2) {
533 i2s_uv = I2S_UV_CH_EN(0);
534 } else if (channel_count == 3 || channel_count == 4) {
535 if (channel_count == 4 &&
536 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
537 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
538 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
539 else
540 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
541 } else if (channel_count == 6 || channel_count == 5) {
542 if (channel_count == 6 &&
543 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
544 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
545 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
546 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
547 } else {
548 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
549 I2S_UV_CH_EN(0);
550 }
551 } else if (channel_count == 8 || channel_count == 7) {
552 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
553 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
554 } else {
555 i2s_uv = I2S_UV_CH_EN(0);
556 }
557
558 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
559 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
560 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
561 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
562}
563
564static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
565 enum hdmi_aud_input_type input_type)
566{
567 u32 val;
568
569 val = mtk_hdmi_read(hdmi, GRL_CFG1);
570 if (input_type == HDMI_AUD_INPUT_I2S &&
571 (val & CFG1_SPDIF) == CFG1_SPDIF) {
572 val &= ~CFG1_SPDIF;
573 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
574 (val & CFG1_SPDIF) == 0) {
575 val |= CFG1_SPDIF;
576 }
577 mtk_hdmi_write(hdmi, GRL_CFG1, val);
578}
579
580static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
581 u8 *channel_status)
582{
583 int i;
584
585 for (i = 0; i < 5; i++) {
586 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
587 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
588 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
589 }
590 for (; i < 24; i++) {
591 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
592 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
593 }
594}
595
596static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
597{
598 u32 val;
599
600 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
601 if (val & MIX_CTRL_SRC_EN) {
602 val &= ~MIX_CTRL_SRC_EN;
603 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
604 usleep_range(255, 512);
605 val |= MIX_CTRL_SRC_EN;
606 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
607 }
608}
609
610static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
611{
612 u32 val;
613
614 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
615 val &= ~MIX_CTRL_SRC_EN;
616 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
617 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
618}
619
620static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
621 enum hdmi_aud_mclk mclk)
622{
623 u32 val;
624
625 val = mtk_hdmi_read(hdmi, GRL_CFG5);
626 val &= CFG5_CD_RATIO_MASK;
627
628 switch (mclk) {
629 case HDMI_AUD_MCLK_128FS:
630 val |= CFG5_FS128;
631 break;
632 case HDMI_AUD_MCLK_256FS:
633 val |= CFG5_FS256;
634 break;
635 case HDMI_AUD_MCLK_384FS:
636 val |= CFG5_FS384;
637 break;
638 case HDMI_AUD_MCLK_512FS:
639 val |= CFG5_FS512;
640 break;
641 case HDMI_AUD_MCLK_768FS:
642 val |= CFG5_FS768;
643 break;
644 default:
645 val |= CFG5_FS256;
646 break;
647 }
648 mtk_hdmi_write(hdmi, GRL_CFG5, val);
649}
650
651struct hdmi_acr_n {
652 unsigned int clock;
653 unsigned int n[3];
654};
655
656/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
657static const struct hdmi_acr_n hdmi_rec_n_table[] = {
658 /* Clock, N: 32kHz 44.1kHz 48kHz */
659 { 25175, { 4576, 7007, 6864 } },
660 { 74176, { 11648, 17836, 11648 } },
661 { 148352, { 11648, 8918, 5824 } },
662 { 296703, { 5824, 4459, 5824 } },
663 { 297000, { 3072, 4704, 5120 } },
664 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
665};
666
667/**
668 * hdmi_recommended_n() - Return N value recommended by HDMI specification
669 * @freq: audio sample rate in Hz
670 * @clock: rounded TMDS clock in kHz
671 */
672static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
673{
674 const struct hdmi_acr_n *recommended;
675 unsigned int i;
676
677 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
678 if (clock == hdmi_rec_n_table[i].clock)
679 break;
680 }
681 recommended = hdmi_rec_n_table + i;
682
683 switch (freq) {
684 case 32000:
685 return recommended->n[0];
686 case 44100:
687 return recommended->n[1];
688 case 48000:
689 return recommended->n[2];
690 case 88200:
691 return recommended->n[1] * 2;
692 case 96000:
693 return recommended->n[2] * 2;
694 case 176400:
695 return recommended->n[1] * 4;
696 case 192000:
697 return recommended->n[2] * 4;
698 default:
699 return (128 * freq) / 1000;
700 }
701}
702
703static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
704{
705 switch (clock) {
706 case 25175:
707 return 25174825; /* 25.2/1.001 MHz */
708 case 74176:
709 return 74175824; /* 74.25/1.001 MHz */
710 case 148352:
711 return 148351648; /* 148.5/1.001 MHz */
712 case 296703:
713 return 296703297; /* 297/1.001 MHz */
714 default:
715 return clock * 1000;
716 }
717}
718
719static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
720 unsigned int tmds_clock, unsigned int n)
721{
722 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
723 128 * audio_sample_rate);
724}
725
726static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
727 unsigned int cts)
728{
729 unsigned char val[NCTS_BYTES];
730 int i;
731
732 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
733 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
734 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
735 memset(val, 0, sizeof(val));
736
737 val[0] = (cts >> 24) & 0xff;
738 val[1] = (cts >> 16) & 0xff;
739 val[2] = (cts >> 8) & 0xff;
740 val[3] = cts & 0xff;
741
742 val[4] = (n >> 16) & 0xff;
743 val[5] = (n >> 8) & 0xff;
744 val[6] = n & 0xff;
745
746 for (i = 0; i < NCTS_BYTES; i++)
747 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
748}
749
750static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
751 unsigned int sample_rate,
752 unsigned int clock)
753{
754 unsigned int n, cts;
755
756 n = hdmi_recommended_n(sample_rate, clock);
757 cts = hdmi_expected_cts(sample_rate, clock, n);
758
759 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
760 __func__, sample_rate, clock, n, cts);
761
762 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
763 AUDIO_I2S_NCTS_SEL);
764 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
765}
766
767static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
768{
769 switch (channel_type) {
770 case HDMI_AUD_CHAN_TYPE_1_0:
771 case HDMI_AUD_CHAN_TYPE_1_1:
772 case HDMI_AUD_CHAN_TYPE_2_0:
773 return 2;
774 case HDMI_AUD_CHAN_TYPE_2_1:
775 case HDMI_AUD_CHAN_TYPE_3_0:
776 return 3;
777 case HDMI_AUD_CHAN_TYPE_3_1:
778 case HDMI_AUD_CHAN_TYPE_4_0:
779 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
780 return 4;
781 case HDMI_AUD_CHAN_TYPE_4_1:
782 case HDMI_AUD_CHAN_TYPE_5_0:
783 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
784 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
785 return 5;
786 case HDMI_AUD_CHAN_TYPE_5_1:
787 case HDMI_AUD_CHAN_TYPE_6_0:
788 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
789 case HDMI_AUD_CHAN_TYPE_6_0_CS:
790 case HDMI_AUD_CHAN_TYPE_6_0_CH:
791 case HDMI_AUD_CHAN_TYPE_6_0_OH:
792 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
793 return 6;
794 case HDMI_AUD_CHAN_TYPE_6_1:
795 case HDMI_AUD_CHAN_TYPE_6_1_CS:
796 case HDMI_AUD_CHAN_TYPE_6_1_CH:
797 case HDMI_AUD_CHAN_TYPE_6_1_OH:
798 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
799 case HDMI_AUD_CHAN_TYPE_7_0:
800 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
801 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
802 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
803 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
804 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
805 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
806 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
807 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
808 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
809 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
810 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
811 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
812 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
813 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
814 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
815 return 7;
816 case HDMI_AUD_CHAN_TYPE_7_1:
817 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
818 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
819 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
820 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
821 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
822 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
823 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
824 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
825 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
826 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
827 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
828 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
829 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
830 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
831 return 8;
832 default:
833 return 2;
834 }
835}
836
837static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
838{
839 unsigned long rate;
840 int ret;
841
842 /* The DPI driver already should have set TVDPLL to the correct rate */
843 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
844 if (ret) {
845 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
846 ret);
847 return ret;
848 }
849
850 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
851
852 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
853 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
854 rate);
855 else
856 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
857
858 mtk_hdmi_hw_config_sys(hdmi);
859 mtk_hdmi_hw_set_deep_color_mode(hdmi);
860 return 0;
861}
862
863static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
864 struct drm_display_mode *mode)
865{
866 mtk_hdmi_hw_reset(hdmi);
867 mtk_hdmi_hw_enable_notice(hdmi, true);
868 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
869 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
870 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
871
872 mtk_hdmi_hw_msic_setting(hdmi, mode);
873}
874
875
876static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
877{
878 enum hdmi_aud_channel_type chan_type;
879 u8 chan_count;
880 bool dst;
881
882 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
883 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
884
885 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
886 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
887 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
888 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
889 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
890 }
891
892 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
893 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
894
895 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
896 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
897 mtk_hdmi_hw_audio_config(hdmi, dst);
898
899 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
900 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
901 else
902 chan_type = hdmi->aud_param.aud_input_chan_type;
903 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
904 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
905 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
906}
907
908static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
909 struct drm_display_mode *display_mode)
910{
911 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
912
913 mtk_hdmi_hw_ncts_enable(hdmi, false);
914 mtk_hdmi_hw_aud_src_disable(hdmi);
915 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
916
917 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
918 switch (sample_rate) {
919 case 32000:
920 case 44100:
921 case 48000:
922 case 88200:
923 case 96000:
924 break;
925 default:
926 return -EINVAL;
927 }
928 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
929 } else {
930 switch (sample_rate) {
931 case 32000:
932 case 44100:
933 case 48000:
934 break;
935 default:
936 return -EINVAL;
937 }
938 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
939 }
940
941 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
942
943 mtk_hdmi_hw_aud_src_reenable(hdmi);
944 return 0;
945}
946
947static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
948 struct drm_display_mode *display_mode)
949{
950 mtk_hdmi_hw_aud_mute(hdmi);
951 mtk_hdmi_hw_send_aud_packet(hdmi, false);
952
953 mtk_hdmi_aud_set_input(hdmi);
954 mtk_hdmi_aud_set_src(hdmi, display_mode);
955 mtk_hdmi_hw_aud_set_channel_status(hdmi,
956 hdmi->aud_param.codec_params.iec.status);
957
958 usleep_range(50, 100);
959
960 mtk_hdmi_hw_ncts_enable(hdmi, true);
961 mtk_hdmi_hw_send_aud_packet(hdmi, true);
962 mtk_hdmi_hw_aud_unmute(hdmi);
963 return 0;
964}
965
966static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
967 struct drm_display_mode *mode)
968{
969 struct hdmi_avi_infoframe frame;
970 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
971 ssize_t err;
972
973 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
974 hdmi->curr_conn, mode);
975 if (err < 0) {
976 dev_err(hdmi->dev,
977 "Failed to get AVI infoframe from mode: %zd\n", err);
978 return err;
979 }
980
981 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
982 if (err < 0) {
983 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
984 return err;
985 }
986
987 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
988 return 0;
989}
990
991static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
992 const char *vendor,
993 const char *product)
994{
995 struct hdmi_spd_infoframe frame;
996 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
997 ssize_t err;
998
999 err = hdmi_spd_infoframe_init(&frame, vendor, product);
1000 if (err < 0) {
1001 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1002 err);
1003 return err;
1004 }
1005
1006 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1007 if (err < 0) {
1008 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1009 return err;
1010 }
1011
1012 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1013 return 0;
1014}
1015
1016static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1017{
1018 struct hdmi_audio_infoframe frame;
1019 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1020 ssize_t err;
1021
1022 err = hdmi_audio_infoframe_init(&frame);
1023 if (err < 0) {
1024 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1025 err);
1026 return err;
1027 }
1028
1029 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1030 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1031 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1032 frame.channels = mtk_hdmi_aud_get_chnl_count(
1033 hdmi->aud_param.aud_input_chan_type);
1034
1035 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1036 if (err < 0) {
1037 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1038 err);
1039 return err;
1040 }
1041
1042 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1043 return 0;
1044}
1045
1046static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1047 struct drm_display_mode *mode)
1048{
1049 struct hdmi_vendor_infoframe frame;
1050 u8 buffer[10];
1051 ssize_t err;
1052
1053 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1054 hdmi->curr_conn, mode);
1055 if (err) {
1056 dev_err(hdmi->dev,
1057 "Failed to get vendor infoframe from mode: %zd\n", err);
1058 return err;
1059 }
1060
1061 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1062 if (err < 0) {
1063 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1064 err);
1065 return err;
1066 }
1067
1068 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1069 return 0;
1070}
1071
1072static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1073{
1074 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1075
1076 hdmi->csp = HDMI_COLORSPACE_RGB;
1077 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1078 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1079 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1080 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1081 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1082 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1083
1084 return 0;
1085}
1086
1087static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1088{
1089 mtk_hdmi_hw_send_aud_packet(hdmi, true);
1090 hdmi->audio_enable = true;
1091}
1092
1093static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1094{
1095 mtk_hdmi_hw_send_aud_packet(hdmi, false);
1096 hdmi->audio_enable = false;
1097}
1098
1099static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1100 struct hdmi_audio_param *param)
1101{
1102 if (!hdmi->audio_enable) {
1103 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1104 return -EINVAL;
1105 }
1106 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1107 param->aud_codec, param->aud_input_type,
1108 param->aud_input_chan_type, param->codec_params.sample_rate);
1109 memcpy(&hdmi->aud_param, param, sizeof(*param));
1110 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1111}
1112
1113static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1114 struct drm_display_mode *mode)
1115{
1116 int ret;
1117
1118 mtk_hdmi_hw_vid_black(hdmi, true);
1119 mtk_hdmi_hw_aud_mute(hdmi);
1120 mtk_hdmi_hw_send_av_mute(hdmi);
1121 phy_power_off(hdmi->phy);
1122
1123 ret = mtk_hdmi_video_change_vpll(hdmi,
1124 mode->clock * 1000);
1125 if (ret) {
1126 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1127 return ret;
1128 }
1129 mtk_hdmi_video_set_display_mode(hdmi, mode);
1130
1131 phy_power_on(hdmi->phy);
1132 mtk_hdmi_aud_output_config(hdmi, mode);
1133
1134 mtk_hdmi_hw_vid_black(hdmi, false);
1135 mtk_hdmi_hw_aud_unmute(hdmi);
1136 mtk_hdmi_hw_send_av_unmute(hdmi);
1137
1138 return 0;
1139}
1140
1141static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1142 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1143 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1144 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1145 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1146};
1147
1148static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1149 struct device_node *np)
1150{
1151 int i;
1152
1153 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1154 hdmi->clk[i] = of_clk_get_by_name(np,
1155 mtk_hdmi_clk_names[i]);
1156 if (IS_ERR(hdmi->clk[i]))
1157 return PTR_ERR(hdmi->clk[i]);
1158 }
1159 return 0;
1160}
1161
1162static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1163{
1164 int ret;
1165
1166 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1167 if (ret)
1168 return ret;
1169
1170 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1171 if (ret)
1172 goto err;
1173
1174 return 0;
1175err:
1176 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1177 return ret;
1178}
1179
1180static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1181{
1182 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1183 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1184}
1185
1186static enum drm_connector_status
1187mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1188{
1189 bool connected;
1190
1191 mutex_lock(&hdmi->update_plugged_status_lock);
1192 connected = mtk_cec_hpd_high(hdmi->cec_dev);
1193 if (hdmi->plugged_cb && hdmi->codec_dev)
1194 hdmi->plugged_cb(hdmi->codec_dev, connected);
1195 mutex_unlock(&hdmi->update_plugged_status_lock);
1196
1197 return connected ?
1198 connector_status_connected : connector_status_disconnected;
1199}
1200
1201static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi)
1202{
1203 return mtk_hdmi_update_plugged_status(hdmi);
1204}
1205
1206static int mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1207 const struct drm_display_info *info,
1208 const struct drm_display_mode *mode)
1209{
1210 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1211 struct drm_bridge *next_bridge;
1212
1213 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1214 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1215 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1216
1217 next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge);
1218 if (next_bridge) {
1219 struct drm_display_mode adjusted_mode;
1220
1221 drm_mode_copy(&adjusted_mode, mode);
1222 if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
1223 &adjusted_mode))
1224 return MODE_BAD;
1225 }
1226
1227 if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
1228 return MODE_BAD;
1229
1230 if (hdmi->conf->max_mode_clock &&
1231 mode->clock > hdmi->conf->max_mode_clock)
1232 return MODE_CLOCK_HIGH;
1233
1234 if (mode->clock < 27000)
1235 return MODE_CLOCK_LOW;
1236 if (mode->clock > 297000)
1237 return MODE_CLOCK_HIGH;
1238
1239 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1240}
1241
1242static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1243{
1244 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1245
1246 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {
1247 static enum drm_connector_status status;
1248
1249 status = mtk_hdmi_detect(hdmi);
1250 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1251 drm_bridge_hpd_notify(&hdmi->bridge, status);
1252 }
1253}
1254
1255/*
1256 * Bridge callbacks
1257 */
1258
1259static enum drm_connector_status mtk_hdmi_bridge_detect(struct drm_bridge *bridge)
1260{
1261 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1262
1263 return mtk_hdmi_detect(hdmi);
1264}
1265
1266static struct edid *mtk_hdmi_bridge_get_edid(struct drm_bridge *bridge,
1267 struct drm_connector *connector)
1268{
1269 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1270 struct edid *edid;
1271
1272 if (!hdmi->ddc_adpt)
1273 return NULL;
1274 edid = drm_get_edid(connector, hdmi->ddc_adpt);
1275 if (!edid)
1276 return NULL;
1277 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1278 return edid;
1279}
1280
1281static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1282 enum drm_bridge_attach_flags flags)
1283{
1284 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1285 int ret;
1286
1287 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
1288 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n",
1289 __func__);
1290 return -EINVAL;
1291 }
1292
1293 if (hdmi->next_bridge) {
1294 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1295 bridge, flags);
1296 if (ret) {
1297 dev_err(hdmi->dev,
1298 "Failed to attach external bridge: %d\n", ret);
1299 return ret;
1300 }
1301 }
1302
1303 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1304
1305 return 0;
1306}
1307
1308static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1309 const struct drm_display_mode *mode,
1310 struct drm_display_mode *adjusted_mode)
1311{
1312 return true;
1313}
1314
1315static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
1316 struct drm_bridge_state *old_bridge_state)
1317{
1318 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1319
1320 if (!hdmi->enabled)
1321 return;
1322
1323 phy_power_off(hdmi->phy);
1324 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1325 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1326
1327 hdmi->curr_conn = NULL;
1328
1329 hdmi->enabled = false;
1330}
1331
1332static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
1333 struct drm_bridge_state *old_state)
1334{
1335 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1336
1337 if (!hdmi->powered)
1338 return;
1339
1340 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1341 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1342
1343 hdmi->powered = false;
1344}
1345
1346static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1347 const struct drm_display_mode *mode,
1348 const struct drm_display_mode *adjusted_mode)
1349{
1350 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1351
1352 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1353 adjusted_mode->name, adjusted_mode->hdisplay);
1354 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1355 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1356 adjusted_mode->htotal);
1357 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1358 adjusted_mode->hskew, adjusted_mode->vdisplay);
1359 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1360 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1361 adjusted_mode->vtotal);
1362 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1363 adjusted_mode->vscan, adjusted_mode->flags);
1364
1365 drm_mode_copy(&hdmi->mode, adjusted_mode);
1366}
1367
1368static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1369 struct drm_bridge_state *old_state)
1370{
1371 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1372
1373 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1374 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1375
1376 hdmi->powered = true;
1377}
1378
1379static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1380 struct drm_display_mode *mode)
1381{
1382 mtk_hdmi_setup_audio_infoframe(hdmi);
1383 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1384 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1385 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1386 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1387}
1388
1389static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
1390 struct drm_bridge_state *old_state)
1391{
1392 struct drm_atomic_state *state = old_state->base.state;
1393 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1394
1395 /* Retrieve the connector through the atomic state. */
1396 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
1397 bridge->encoder);
1398
1399 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1400 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1401 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1402 phy_power_on(hdmi->phy);
1403 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1404
1405 hdmi->enabled = true;
1406}
1407
1408static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1409 .mode_valid = mtk_hdmi_bridge_mode_valid,
1410 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1411 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1412 .atomic_reset = drm_atomic_helper_bridge_reset,
1413 .attach = mtk_hdmi_bridge_attach,
1414 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1415 .atomic_disable = mtk_hdmi_bridge_atomic_disable,
1416 .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
1417 .mode_set = mtk_hdmi_bridge_mode_set,
1418 .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable,
1419 .atomic_enable = mtk_hdmi_bridge_atomic_enable,
1420 .detect = mtk_hdmi_bridge_detect,
1421 .get_edid = mtk_hdmi_bridge_get_edid,
1422};
1423
1424static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1425 struct platform_device *pdev)
1426{
1427 struct device *dev = &pdev->dev;
1428 struct device_node *np = dev->of_node;
1429 struct device_node *cec_np, *remote, *i2c_np;
1430 struct platform_device *cec_pdev;
1431 struct regmap *regmap;
1432 struct resource *mem;
1433 int ret;
1434
1435 ret = mtk_hdmi_get_all_clk(hdmi, np);
1436 if (ret) {
1437 if (ret != -EPROBE_DEFER)
1438 dev_err(dev, "Failed to get clocks: %d\n", ret);
1439
1440 return ret;
1441 }
1442
1443 /* The CEC module handles HDMI hotplug detection */
1444 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1445 if (!cec_np) {
1446 dev_err(dev, "Failed to find CEC node\n");
1447 return -EINVAL;
1448 }
1449
1450 cec_pdev = of_find_device_by_node(cec_np);
1451 if (!cec_pdev) {
1452 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1453 cec_np);
1454 of_node_put(cec_np);
1455 return -EPROBE_DEFER;
1456 }
1457 of_node_put(cec_np);
1458 hdmi->cec_dev = &cec_pdev->dev;
1459
1460 /*
1461 * The mediatek,syscon-hdmi property contains a phandle link to the
1462 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1463 * registers it contains.
1464 */
1465 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1466 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1467 &hdmi->sys_offset);
1468 if (IS_ERR(regmap))
1469 ret = PTR_ERR(regmap);
1470 if (ret) {
1471 dev_err(dev,
1472 "Failed to get system configuration registers: %d\n",
1473 ret);
1474 goto put_device;
1475 }
1476 hdmi->sys_regmap = regmap;
1477
1478 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1479 hdmi->regs = devm_ioremap_resource(dev, mem);
1480 if (IS_ERR(hdmi->regs)) {
1481 ret = PTR_ERR(hdmi->regs);
1482 goto put_device;
1483 }
1484
1485 remote = of_graph_get_remote_node(np, 1, 0);
1486 if (!remote) {
1487 ret = -EINVAL;
1488 goto put_device;
1489 }
1490
1491 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1492 hdmi->next_bridge = of_drm_find_bridge(remote);
1493 if (!hdmi->next_bridge) {
1494 dev_err(dev, "Waiting for external bridge\n");
1495 of_node_put(remote);
1496 ret = -EPROBE_DEFER;
1497 goto put_device;
1498 }
1499 }
1500
1501 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1502 if (!i2c_np) {
1503 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1504 remote);
1505 of_node_put(remote);
1506 ret = -EINVAL;
1507 goto put_device;
1508 }
1509 of_node_put(remote);
1510
1511 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1512 of_node_put(i2c_np);
1513 if (!hdmi->ddc_adpt) {
1514 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1515 ret = -EINVAL;
1516 goto put_device;
1517 }
1518
1519 return 0;
1520put_device:
1521 put_device(hdmi->cec_dev);
1522 return ret;
1523}
1524
1525/*
1526 * HDMI audio codec callbacks
1527 */
1528
1529static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1530 struct hdmi_codec_daifmt *daifmt,
1531 struct hdmi_codec_params *params)
1532{
1533 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1534 struct hdmi_audio_param hdmi_params;
1535 unsigned int chan = params->cea.channels;
1536
1537 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1538 params->sample_rate, params->sample_width, chan);
1539
1540 if (!hdmi->bridge.encoder)
1541 return -ENODEV;
1542
1543 switch (chan) {
1544 case 2:
1545 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1546 break;
1547 case 4:
1548 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1549 break;
1550 case 6:
1551 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1552 break;
1553 case 8:
1554 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1555 break;
1556 default:
1557 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1558 return -EINVAL;
1559 }
1560
1561 switch (params->sample_rate) {
1562 case 32000:
1563 case 44100:
1564 case 48000:
1565 case 88200:
1566 case 96000:
1567 case 176400:
1568 case 192000:
1569 break;
1570 default:
1571 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1572 params->sample_rate);
1573 return -EINVAL;
1574 }
1575
1576 switch (daifmt->fmt) {
1577 case HDMI_I2S:
1578 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1579 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1580 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1581 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1582 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1583 break;
1584 case HDMI_SPDIF:
1585 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1586 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1587 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1588 break;
1589 default:
1590 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1591 daifmt->fmt);
1592 return -EINVAL;
1593 }
1594
1595 memcpy(&hdmi_params.codec_params, params,
1596 sizeof(hdmi_params.codec_params));
1597
1598 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1599
1600 return 0;
1601}
1602
1603static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1604{
1605 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1606
1607 mtk_hdmi_audio_enable(hdmi);
1608
1609 return 0;
1610}
1611
1612static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1613{
1614 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1615
1616 mtk_hdmi_audio_disable(hdmi);
1617}
1618
1619static int
1620mtk_hdmi_audio_mute(struct device *dev, void *data,
1621 bool enable, int direction)
1622{
1623 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1624
1625 if (enable)
1626 mtk_hdmi_hw_aud_mute(hdmi);
1627 else
1628 mtk_hdmi_hw_aud_unmute(hdmi);
1629
1630 return 0;
1631}
1632
1633static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1634{
1635 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1636
1637 if (hdmi->enabled)
1638 memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
1639 else
1640 memset(buf, 0, len);
1641 return 0;
1642}
1643
1644static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1645 hdmi_codec_plugged_cb fn,
1646 struct device *codec_dev)
1647{
1648 struct mtk_hdmi *hdmi = data;
1649
1650 mutex_lock(&hdmi->update_plugged_status_lock);
1651 hdmi->plugged_cb = fn;
1652 hdmi->codec_dev = codec_dev;
1653 mutex_unlock(&hdmi->update_plugged_status_lock);
1654
1655 mtk_hdmi_update_plugged_status(hdmi);
1656
1657 return 0;
1658}
1659
1660static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1661 .hw_params = mtk_hdmi_audio_hw_params,
1662 .audio_startup = mtk_hdmi_audio_startup,
1663 .audio_shutdown = mtk_hdmi_audio_shutdown,
1664 .mute_stream = mtk_hdmi_audio_mute,
1665 .get_eld = mtk_hdmi_audio_get_eld,
1666 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1667 .no_capture_mute = 1,
1668};
1669
1670static int mtk_hdmi_register_audio_driver(struct device *dev)
1671{
1672 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1673 struct hdmi_codec_pdata codec_data = {
1674 .ops = &mtk_hdmi_audio_codec_ops,
1675 .max_i2s_channels = 2,
1676 .i2s = 1,
1677 .data = hdmi,
1678 };
1679 struct platform_device *pdev;
1680
1681 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1682 PLATFORM_DEVID_AUTO, &codec_data,
1683 sizeof(codec_data));
1684 if (IS_ERR(pdev))
1685 return PTR_ERR(pdev);
1686
1687 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1688 return 0;
1689}
1690
1691static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1692{
1693 struct mtk_hdmi *hdmi;
1694 struct device *dev = &pdev->dev;
1695 int ret;
1696
1697 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1698 if (!hdmi)
1699 return -ENOMEM;
1700
1701 hdmi->dev = dev;
1702 hdmi->conf = of_device_get_match_data(dev);
1703
1704 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1705 if (ret)
1706 return ret;
1707
1708 hdmi->phy = devm_phy_get(dev, "hdmi");
1709 if (IS_ERR(hdmi->phy)) {
1710 ret = PTR_ERR(hdmi->phy);
1711 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1712 return ret;
1713 }
1714
1715 mutex_init(&hdmi->update_plugged_status_lock);
1716 platform_set_drvdata(pdev, hdmi);
1717
1718 ret = mtk_hdmi_output_init(hdmi);
1719 if (ret) {
1720 dev_err(dev, "Failed to initialize hdmi output\n");
1721 return ret;
1722 }
1723
1724 ret = mtk_hdmi_register_audio_driver(dev);
1725 if (ret) {
1726 dev_err(dev, "Failed to register audio driver: %d\n", ret);
1727 return ret;
1728 }
1729
1730 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1731 hdmi->bridge.of_node = pdev->dev.of_node;
1732 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1733 | DRM_BRIDGE_OP_HPD;
1734 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1735 drm_bridge_add(&hdmi->bridge);
1736
1737 ret = mtk_hdmi_clk_enable_audio(hdmi);
1738 if (ret) {
1739 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1740 goto err_bridge_remove;
1741 }
1742
1743 return 0;
1744
1745err_bridge_remove:
1746 drm_bridge_remove(&hdmi->bridge);
1747 return ret;
1748}
1749
1750static int mtk_drm_hdmi_remove(struct platform_device *pdev)
1751{
1752 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1753
1754 drm_bridge_remove(&hdmi->bridge);
1755 mtk_hdmi_clk_disable_audio(hdmi);
1756 return 0;
1757}
1758
1759#ifdef CONFIG_PM_SLEEP
1760static int mtk_hdmi_suspend(struct device *dev)
1761{
1762 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1763
1764 mtk_hdmi_clk_disable_audio(hdmi);
1765
1766 return 0;
1767}
1768
1769static int mtk_hdmi_resume(struct device *dev)
1770{
1771 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1772 int ret = 0;
1773
1774 ret = mtk_hdmi_clk_enable_audio(hdmi);
1775 if (ret) {
1776 dev_err(dev, "hdmi resume failed!\n");
1777 return ret;
1778 }
1779
1780 return 0;
1781}
1782#endif
1783static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1784 mtk_hdmi_suspend, mtk_hdmi_resume);
1785
1786static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1787 .tz_disabled = true,
1788};
1789
1790static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
1791 .max_mode_clock = 148500,
1792 .cea_modes_only = true,
1793};
1794
1795static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1796 { .compatible = "mediatek,mt2701-hdmi",
1797 .data = &mtk_hdmi_conf_mt2701,
1798 },
1799 { .compatible = "mediatek,mt8167-hdmi",
1800 .data = &mtk_hdmi_conf_mt8167,
1801 },
1802 { .compatible = "mediatek,mt8173-hdmi",
1803 },
1804 {}
1805};
1806MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
1807
1808static struct platform_driver mtk_hdmi_driver = {
1809 .probe = mtk_drm_hdmi_probe,
1810 .remove = mtk_drm_hdmi_remove,
1811 .driver = {
1812 .name = "mediatek-drm-hdmi",
1813 .of_match_table = mtk_drm_hdmi_of_ids,
1814 .pm = &mtk_hdmi_pm_ops,
1815 },
1816};
1817
1818static struct platform_driver * const mtk_hdmi_drivers[] = {
1819 &mtk_hdmi_ddc_driver,
1820 &mtk_cec_driver,
1821 &mtk_hdmi_driver,
1822};
1823
1824static int __init mtk_hdmitx_init(void)
1825{
1826 return platform_register_drivers(mtk_hdmi_drivers,
1827 ARRAY_SIZE(mtk_hdmi_drivers));
1828}
1829
1830static void __exit mtk_hdmitx_exit(void)
1831{
1832 platform_unregister_drivers(mtk_hdmi_drivers,
1833 ARRAY_SIZE(mtk_hdmi_drivers));
1834}
1835
1836module_init(mtk_hdmitx_init);
1837module_exit(mtk_hdmitx_exit);
1838
1839MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1840MODULE_DESCRIPTION("MediaTek HDMI Driver");
1841MODULE_LICENSE("GPL v2");