Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Based on drivers/serial/8250.c by Russell King.
4 *
5 * Author: Nicolas Pitre
6 * Created: Feb 20, 2003
7 * Copyright: (C) 2003 Monta Vista Software, Inc.
8 *
9 * Note 1: This driver is made separate from the already too overloaded
10 * 8250.c because it needs some kirks of its own and that'll make it
11 * easier to add DMA support.
12 *
13 * Note 2: I'm too sick of device allocation policies for serial ports.
14 * If someone else wants to request an "official" allocation of major/minor
15 * for this driver please be my guest. And don't forget that new hardware
16 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17 * hope for a better port registration and dynamic device allocation scheme
18 * with the serial core maintainer satisfaction to appear soon.
19 */
20
21
22#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
25
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/sysrq.h>
30#include <linux/serial_reg.h>
31#include <linux/circ_buf.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/of.h>
35#include <linux/platform_device.h>
36#include <linux/tty.h>
37#include <linux/tty_flip.h>
38#include <linux/serial_core.h>
39#include <linux/clk.h>
40#include <linux/io.h>
41#include <linux/slab.h>
42
43#define PXA_NAME_LEN 8
44
45struct uart_pxa_port {
46 struct uart_port port;
47 unsigned char ier;
48 unsigned char lcr;
49 unsigned char mcr;
50 unsigned int lsr_break_flag;
51 struct clk *clk;
52 char name[PXA_NAME_LEN];
53};
54
55static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
56{
57 offset <<= 2;
58 return readl(up->port.membase + offset);
59}
60
61static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
62{
63 offset <<= 2;
64 writel(value, up->port.membase + offset);
65}
66
67static void serial_pxa_enable_ms(struct uart_port *port)
68{
69 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
70
71 up->ier |= UART_IER_MSI;
72 serial_out(up, UART_IER, up->ier);
73}
74
75static void serial_pxa_stop_tx(struct uart_port *port)
76{
77 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
78
79 if (up->ier & UART_IER_THRI) {
80 up->ier &= ~UART_IER_THRI;
81 serial_out(up, UART_IER, up->ier);
82 }
83}
84
85static void serial_pxa_stop_rx(struct uart_port *port)
86{
87 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
88
89 up->ier &= ~UART_IER_RLSI;
90 up->port.read_status_mask &= ~UART_LSR_DR;
91 serial_out(up, UART_IER, up->ier);
92}
93
94static inline void receive_chars(struct uart_pxa_port *up, int *status)
95{
96 unsigned int ch, flag;
97 int max_count = 256;
98
99 do {
100 /* work around Errata #20 according to
101 * Intel(R) PXA27x Processor Family
102 * Specification Update (May 2005)
103 *
104 * Step 2
105 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
106 */
107 up->ier &= ~UART_IER_RTOIE;
108 serial_out(up, UART_IER, up->ier);
109
110 ch = serial_in(up, UART_RX);
111 flag = TTY_NORMAL;
112 up->port.icount.rx++;
113
114 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
115 UART_LSR_FE | UART_LSR_OE))) {
116 /*
117 * For statistics only
118 */
119 if (*status & UART_LSR_BI) {
120 *status &= ~(UART_LSR_FE | UART_LSR_PE);
121 up->port.icount.brk++;
122 /*
123 * We do the SysRQ and SAK checking
124 * here because otherwise the break
125 * may get masked by ignore_status_mask
126 * or read_status_mask.
127 */
128 if (uart_handle_break(&up->port))
129 goto ignore_char;
130 } else if (*status & UART_LSR_PE)
131 up->port.icount.parity++;
132 else if (*status & UART_LSR_FE)
133 up->port.icount.frame++;
134 if (*status & UART_LSR_OE)
135 up->port.icount.overrun++;
136
137 /*
138 * Mask off conditions which should be ignored.
139 */
140 *status &= up->port.read_status_mask;
141
142#ifdef CONFIG_SERIAL_PXA_CONSOLE
143 if (up->port.line == up->port.cons->index) {
144 /* Recover the break flag from console xmit */
145 *status |= up->lsr_break_flag;
146 up->lsr_break_flag = 0;
147 }
148#endif
149 if (*status & UART_LSR_BI) {
150 flag = TTY_BREAK;
151 } else if (*status & UART_LSR_PE)
152 flag = TTY_PARITY;
153 else if (*status & UART_LSR_FE)
154 flag = TTY_FRAME;
155 }
156
157 if (uart_handle_sysrq_char(&up->port, ch))
158 goto ignore_char;
159
160 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
161
162 ignore_char:
163 *status = serial_in(up, UART_LSR);
164 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
165 tty_flip_buffer_push(&up->port.state->port);
166
167 /* work around Errata #20 according to
168 * Intel(R) PXA27x Processor Family
169 * Specification Update (May 2005)
170 *
171 * Step 6:
172 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
173 */
174 up->ier |= UART_IER_RTOIE;
175 serial_out(up, UART_IER, up->ier);
176}
177
178static void transmit_chars(struct uart_pxa_port *up)
179{
180 struct circ_buf *xmit = &up->port.state->xmit;
181 int count;
182
183 if (up->port.x_char) {
184 serial_out(up, UART_TX, up->port.x_char);
185 up->port.icount.tx++;
186 up->port.x_char = 0;
187 return;
188 }
189 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
190 serial_pxa_stop_tx(&up->port);
191 return;
192 }
193
194 count = up->port.fifosize / 2;
195 do {
196 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
197 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
198 up->port.icount.tx++;
199 if (uart_circ_empty(xmit))
200 break;
201 } while (--count > 0);
202
203 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
204 uart_write_wakeup(&up->port);
205
206
207 if (uart_circ_empty(xmit))
208 serial_pxa_stop_tx(&up->port);
209}
210
211static void serial_pxa_start_tx(struct uart_port *port)
212{
213 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
214
215 if (!(up->ier & UART_IER_THRI)) {
216 up->ier |= UART_IER_THRI;
217 serial_out(up, UART_IER, up->ier);
218 }
219}
220
221/* should hold up->port.lock */
222static inline void check_modem_status(struct uart_pxa_port *up)
223{
224 int status;
225
226 status = serial_in(up, UART_MSR);
227
228 if ((status & UART_MSR_ANY_DELTA) == 0)
229 return;
230
231 if (status & UART_MSR_TERI)
232 up->port.icount.rng++;
233 if (status & UART_MSR_DDSR)
234 up->port.icount.dsr++;
235 if (status & UART_MSR_DDCD)
236 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
237 if (status & UART_MSR_DCTS)
238 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
239
240 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
241}
242
243/*
244 * This handles the interrupt from one port.
245 */
246static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
247{
248 struct uart_pxa_port *up = dev_id;
249 unsigned int iir, lsr;
250
251 iir = serial_in(up, UART_IIR);
252 if (iir & UART_IIR_NO_INT)
253 return IRQ_NONE;
254 spin_lock(&up->port.lock);
255 lsr = serial_in(up, UART_LSR);
256 if (lsr & UART_LSR_DR)
257 receive_chars(up, &lsr);
258 check_modem_status(up);
259 if (lsr & UART_LSR_THRE)
260 transmit_chars(up);
261 spin_unlock(&up->port.lock);
262 return IRQ_HANDLED;
263}
264
265static unsigned int serial_pxa_tx_empty(struct uart_port *port)
266{
267 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
268 unsigned long flags;
269 unsigned int ret;
270
271 spin_lock_irqsave(&up->port.lock, flags);
272 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
273 spin_unlock_irqrestore(&up->port.lock, flags);
274
275 return ret;
276}
277
278static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
279{
280 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
281 unsigned char status;
282 unsigned int ret;
283
284 status = serial_in(up, UART_MSR);
285
286 ret = 0;
287 if (status & UART_MSR_DCD)
288 ret |= TIOCM_CAR;
289 if (status & UART_MSR_RI)
290 ret |= TIOCM_RNG;
291 if (status & UART_MSR_DSR)
292 ret |= TIOCM_DSR;
293 if (status & UART_MSR_CTS)
294 ret |= TIOCM_CTS;
295 return ret;
296}
297
298static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
299{
300 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
301 unsigned char mcr = 0;
302
303 if (mctrl & TIOCM_RTS)
304 mcr |= UART_MCR_RTS;
305 if (mctrl & TIOCM_DTR)
306 mcr |= UART_MCR_DTR;
307 if (mctrl & TIOCM_OUT1)
308 mcr |= UART_MCR_OUT1;
309 if (mctrl & TIOCM_OUT2)
310 mcr |= UART_MCR_OUT2;
311 if (mctrl & TIOCM_LOOP)
312 mcr |= UART_MCR_LOOP;
313
314 mcr |= up->mcr;
315
316 serial_out(up, UART_MCR, mcr);
317}
318
319static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
320{
321 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
322 unsigned long flags;
323
324 spin_lock_irqsave(&up->port.lock, flags);
325 if (break_state == -1)
326 up->lcr |= UART_LCR_SBC;
327 else
328 up->lcr &= ~UART_LCR_SBC;
329 serial_out(up, UART_LCR, up->lcr);
330 spin_unlock_irqrestore(&up->port.lock, flags);
331}
332
333static int serial_pxa_startup(struct uart_port *port)
334{
335 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
336 unsigned long flags;
337 int retval;
338
339 if (port->line == 3) /* HWUART */
340 up->mcr |= UART_MCR_AFE;
341 else
342 up->mcr = 0;
343
344 up->port.uartclk = clk_get_rate(up->clk);
345
346 /*
347 * Allocate the IRQ
348 */
349 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
350 if (retval)
351 return retval;
352
353 /*
354 * Clear the FIFO buffers and disable them.
355 * (they will be reenabled in set_termios())
356 */
357 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
358 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
359 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
360 serial_out(up, UART_FCR, 0);
361
362 /*
363 * Clear the interrupt registers.
364 */
365 (void) serial_in(up, UART_LSR);
366 (void) serial_in(up, UART_RX);
367 (void) serial_in(up, UART_IIR);
368 (void) serial_in(up, UART_MSR);
369
370 /*
371 * Now, initialize the UART
372 */
373 serial_out(up, UART_LCR, UART_LCR_WLEN8);
374
375 spin_lock_irqsave(&up->port.lock, flags);
376 up->port.mctrl |= TIOCM_OUT2;
377 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
378 spin_unlock_irqrestore(&up->port.lock, flags);
379
380 /*
381 * Finally, enable interrupts. Note: Modem status interrupts
382 * are set via set_termios(), which will be occurring imminently
383 * anyway, so we don't enable them here.
384 */
385 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
386 serial_out(up, UART_IER, up->ier);
387
388 /*
389 * And clear the interrupt registers again for luck.
390 */
391 (void) serial_in(up, UART_LSR);
392 (void) serial_in(up, UART_RX);
393 (void) serial_in(up, UART_IIR);
394 (void) serial_in(up, UART_MSR);
395
396 return 0;
397}
398
399static void serial_pxa_shutdown(struct uart_port *port)
400{
401 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
402 unsigned long flags;
403
404 free_irq(up->port.irq, up);
405
406 /*
407 * Disable interrupts from this port
408 */
409 up->ier = 0;
410 serial_out(up, UART_IER, 0);
411
412 spin_lock_irqsave(&up->port.lock, flags);
413 up->port.mctrl &= ~TIOCM_OUT2;
414 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
415 spin_unlock_irqrestore(&up->port.lock, flags);
416
417 /*
418 * Disable break condition and FIFOs
419 */
420 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
421 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
422 UART_FCR_CLEAR_RCVR |
423 UART_FCR_CLEAR_XMIT);
424 serial_out(up, UART_FCR, 0);
425}
426
427static void
428serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
429 struct ktermios *old)
430{
431 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
432 unsigned char cval, fcr = 0;
433 unsigned long flags;
434 unsigned int baud, quot;
435 unsigned int dll;
436
437 switch (termios->c_cflag & CSIZE) {
438 case CS5:
439 cval = UART_LCR_WLEN5;
440 break;
441 case CS6:
442 cval = UART_LCR_WLEN6;
443 break;
444 case CS7:
445 cval = UART_LCR_WLEN7;
446 break;
447 default:
448 case CS8:
449 cval = UART_LCR_WLEN8;
450 break;
451 }
452
453 if (termios->c_cflag & CSTOPB)
454 cval |= UART_LCR_STOP;
455 if (termios->c_cflag & PARENB)
456 cval |= UART_LCR_PARITY;
457 if (!(termios->c_cflag & PARODD))
458 cval |= UART_LCR_EPAR;
459
460 /*
461 * Ask the core to calculate the divisor for us.
462 */
463 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
464 quot = uart_get_divisor(port, baud);
465
466 if ((up->port.uartclk / quot) < (2400 * 16))
467 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
468 else if ((up->port.uartclk / quot) < (230400 * 16))
469 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
470 else
471 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
472
473 /*
474 * Ok, we're now changing the port state. Do it with
475 * interrupts disabled.
476 */
477 spin_lock_irqsave(&up->port.lock, flags);
478
479 /*
480 * Ensure the port will be enabled.
481 * This is required especially for serial console.
482 */
483 up->ier |= UART_IER_UUE;
484
485 /*
486 * Update the per-port timeout.
487 */
488 uart_update_timeout(port, termios->c_cflag, baud);
489
490 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
491 if (termios->c_iflag & INPCK)
492 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
493 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
494 up->port.read_status_mask |= UART_LSR_BI;
495
496 /*
497 * Characters to ignore
498 */
499 up->port.ignore_status_mask = 0;
500 if (termios->c_iflag & IGNPAR)
501 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
502 if (termios->c_iflag & IGNBRK) {
503 up->port.ignore_status_mask |= UART_LSR_BI;
504 /*
505 * If we're ignoring parity and break indicators,
506 * ignore overruns too (for real raw support).
507 */
508 if (termios->c_iflag & IGNPAR)
509 up->port.ignore_status_mask |= UART_LSR_OE;
510 }
511
512 /*
513 * ignore all characters if CREAD is not set
514 */
515 if ((termios->c_cflag & CREAD) == 0)
516 up->port.ignore_status_mask |= UART_LSR_DR;
517
518 /*
519 * CTS flow control flag and modem status interrupts
520 */
521 up->ier &= ~UART_IER_MSI;
522 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
523 up->ier |= UART_IER_MSI;
524
525 serial_out(up, UART_IER, up->ier);
526
527 if (termios->c_cflag & CRTSCTS)
528 up->mcr |= UART_MCR_AFE;
529 else
530 up->mcr &= ~UART_MCR_AFE;
531
532 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
533 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
534
535 /*
536 * work around Errata #75 according to Intel(R) PXA27x Processor Family
537 * Specification Update (Nov 2005)
538 */
539 dll = serial_in(up, UART_DLL);
540 WARN_ON(dll != (quot & 0xff));
541
542 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
543 serial_out(up, UART_LCR, cval); /* reset DLAB */
544 up->lcr = cval; /* Save LCR */
545 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
546 serial_out(up, UART_FCR, fcr);
547 spin_unlock_irqrestore(&up->port.lock, flags);
548}
549
550static void
551serial_pxa_pm(struct uart_port *port, unsigned int state,
552 unsigned int oldstate)
553{
554 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
555
556 if (!state)
557 clk_prepare_enable(up->clk);
558 else
559 clk_disable_unprepare(up->clk);
560}
561
562static void serial_pxa_release_port(struct uart_port *port)
563{
564}
565
566static int serial_pxa_request_port(struct uart_port *port)
567{
568 return 0;
569}
570
571static void serial_pxa_config_port(struct uart_port *port, int flags)
572{
573 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
574 up->port.type = PORT_PXA;
575}
576
577static int
578serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
579{
580 /* we don't want the core code to modify any port params */
581 return -EINVAL;
582}
583
584static const char *
585serial_pxa_type(struct uart_port *port)
586{
587 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
588 return up->name;
589}
590
591static struct uart_pxa_port *serial_pxa_ports[4];
592static struct uart_driver serial_pxa_reg;
593
594#ifdef CONFIG_SERIAL_PXA_CONSOLE
595
596#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
597
598/*
599 * Wait for transmitter & holding register to empty
600 */
601static void wait_for_xmitr(struct uart_pxa_port *up)
602{
603 unsigned int status, tmout = 10000;
604
605 /* Wait up to 10ms for the character(s) to be sent. */
606 do {
607 status = serial_in(up, UART_LSR);
608
609 if (status & UART_LSR_BI)
610 up->lsr_break_flag = UART_LSR_BI;
611
612 if (--tmout == 0)
613 break;
614 udelay(1);
615 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
616
617 /* Wait up to 1s for flow control if necessary */
618 if (up->port.flags & UPF_CONS_FLOW) {
619 tmout = 1000000;
620 while (--tmout &&
621 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
622 udelay(1);
623 }
624}
625
626static void serial_pxa_console_putchar(struct uart_port *port, int ch)
627{
628 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
629
630 wait_for_xmitr(up);
631 serial_out(up, UART_TX, ch);
632}
633
634/*
635 * Print a string to the serial port trying not to disturb
636 * any possible real use of the port...
637 *
638 * The console_lock must be held when we get here.
639 */
640static void
641serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
642{
643 struct uart_pxa_port *up = serial_pxa_ports[co->index];
644 unsigned int ier;
645 unsigned long flags;
646 int locked = 1;
647
648 clk_enable(up->clk);
649 local_irq_save(flags);
650 if (up->port.sysrq)
651 locked = 0;
652 else if (oops_in_progress)
653 locked = spin_trylock(&up->port.lock);
654 else
655 spin_lock(&up->port.lock);
656
657 /*
658 * First save the IER then disable the interrupts
659 */
660 ier = serial_in(up, UART_IER);
661 serial_out(up, UART_IER, UART_IER_UUE);
662
663 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
664
665 /*
666 * Finally, wait for transmitter to become empty
667 * and restore the IER
668 */
669 wait_for_xmitr(up);
670 serial_out(up, UART_IER, ier);
671
672 if (locked)
673 spin_unlock(&up->port.lock);
674 local_irq_restore(flags);
675 clk_disable(up->clk);
676
677}
678
679#ifdef CONFIG_CONSOLE_POLL
680/*
681 * Console polling routines for writing and reading from the uart while
682 * in an interrupt or debug context.
683 */
684
685static int serial_pxa_get_poll_char(struct uart_port *port)
686{
687 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
688 unsigned char lsr = serial_in(up, UART_LSR);
689
690 while (!(lsr & UART_LSR_DR))
691 lsr = serial_in(up, UART_LSR);
692
693 return serial_in(up, UART_RX);
694}
695
696
697static void serial_pxa_put_poll_char(struct uart_port *port,
698 unsigned char c)
699{
700 unsigned int ier;
701 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
702
703 /*
704 * First save the IER then disable the interrupts
705 */
706 ier = serial_in(up, UART_IER);
707 serial_out(up, UART_IER, UART_IER_UUE);
708
709 wait_for_xmitr(up);
710 /*
711 * Send the character out.
712 */
713 serial_out(up, UART_TX, c);
714
715 /*
716 * Finally, wait for transmitter to become empty
717 * and restore the IER
718 */
719 wait_for_xmitr(up);
720 serial_out(up, UART_IER, ier);
721}
722
723#endif /* CONFIG_CONSOLE_POLL */
724
725static int __init
726serial_pxa_console_setup(struct console *co, char *options)
727{
728 struct uart_pxa_port *up;
729 int baud = 9600;
730 int bits = 8;
731 int parity = 'n';
732 int flow = 'n';
733
734 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
735 co->index = 0;
736 up = serial_pxa_ports[co->index];
737 if (!up)
738 return -ENODEV;
739
740 if (options)
741 uart_parse_options(options, &baud, &parity, &bits, &flow);
742
743 return uart_set_options(&up->port, co, baud, parity, bits, flow);
744}
745
746static struct console serial_pxa_console = {
747 .name = "ttyS",
748 .write = serial_pxa_console_write,
749 .device = uart_console_device,
750 .setup = serial_pxa_console_setup,
751 .flags = CON_PRINTBUFFER,
752 .index = -1,
753 .data = &serial_pxa_reg,
754};
755
756#define PXA_CONSOLE &serial_pxa_console
757#else
758#define PXA_CONSOLE NULL
759#endif
760
761static const struct uart_ops serial_pxa_pops = {
762 .tx_empty = serial_pxa_tx_empty,
763 .set_mctrl = serial_pxa_set_mctrl,
764 .get_mctrl = serial_pxa_get_mctrl,
765 .stop_tx = serial_pxa_stop_tx,
766 .start_tx = serial_pxa_start_tx,
767 .stop_rx = serial_pxa_stop_rx,
768 .enable_ms = serial_pxa_enable_ms,
769 .break_ctl = serial_pxa_break_ctl,
770 .startup = serial_pxa_startup,
771 .shutdown = serial_pxa_shutdown,
772 .set_termios = serial_pxa_set_termios,
773 .pm = serial_pxa_pm,
774 .type = serial_pxa_type,
775 .release_port = serial_pxa_release_port,
776 .request_port = serial_pxa_request_port,
777 .config_port = serial_pxa_config_port,
778 .verify_port = serial_pxa_verify_port,
779#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
780 .poll_get_char = serial_pxa_get_poll_char,
781 .poll_put_char = serial_pxa_put_poll_char,
782#endif
783};
784
785static struct uart_driver serial_pxa_reg = {
786 .owner = THIS_MODULE,
787 .driver_name = "PXA serial",
788 .dev_name = "ttyS",
789 .major = TTY_MAJOR,
790 .minor = 64,
791 .nr = 4,
792 .cons = PXA_CONSOLE,
793};
794
795#ifdef CONFIG_PM
796static int serial_pxa_suspend(struct device *dev)
797{
798 struct uart_pxa_port *sport = dev_get_drvdata(dev);
799
800 if (sport)
801 uart_suspend_port(&serial_pxa_reg, &sport->port);
802
803 return 0;
804}
805
806static int serial_pxa_resume(struct device *dev)
807{
808 struct uart_pxa_port *sport = dev_get_drvdata(dev);
809
810 if (sport)
811 uart_resume_port(&serial_pxa_reg, &sport->port);
812
813 return 0;
814}
815
816static const struct dev_pm_ops serial_pxa_pm_ops = {
817 .suspend = serial_pxa_suspend,
818 .resume = serial_pxa_resume,
819};
820#endif
821
822static const struct of_device_id serial_pxa_dt_ids[] = {
823 { .compatible = "mrvl,pxa-uart", },
824 { .compatible = "mrvl,mmp-uart", },
825 {}
826};
827
828static int serial_pxa_probe_dt(struct platform_device *pdev,
829 struct uart_pxa_port *sport)
830{
831 struct device_node *np = pdev->dev.of_node;
832 int ret;
833
834 if (!np)
835 return 1;
836
837 ret = of_alias_get_id(np, "serial");
838 if (ret < 0) {
839 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
840 return ret;
841 }
842 sport->port.line = ret;
843 return 0;
844}
845
846static int serial_pxa_probe(struct platform_device *dev)
847{
848 struct uart_pxa_port *sport;
849 struct resource *mmres, *irqres;
850 int ret;
851
852 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
853 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
854 if (!mmres || !irqres)
855 return -ENODEV;
856
857 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
858 if (!sport)
859 return -ENOMEM;
860
861 sport->clk = clk_get(&dev->dev, NULL);
862 if (IS_ERR(sport->clk)) {
863 ret = PTR_ERR(sport->clk);
864 goto err_free;
865 }
866
867 ret = clk_prepare(sport->clk);
868 if (ret) {
869 clk_put(sport->clk);
870 goto err_free;
871 }
872
873 sport->port.type = PORT_PXA;
874 sport->port.iotype = UPIO_MEM;
875 sport->port.mapbase = mmres->start;
876 sport->port.irq = irqres->start;
877 sport->port.fifosize = 64;
878 sport->port.ops = &serial_pxa_pops;
879 sport->port.dev = &dev->dev;
880 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
881 sport->port.uartclk = clk_get_rate(sport->clk);
882
883 ret = serial_pxa_probe_dt(dev, sport);
884 if (ret > 0)
885 sport->port.line = dev->id;
886 else if (ret < 0)
887 goto err_clk;
888 if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
889 dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
890 ret = -EINVAL;
891 goto err_clk;
892 }
893 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
894
895 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
896 if (!sport->port.membase) {
897 ret = -ENOMEM;
898 goto err_clk;
899 }
900
901 serial_pxa_ports[sport->port.line] = sport;
902
903 uart_add_one_port(&serial_pxa_reg, &sport->port);
904 platform_set_drvdata(dev, sport);
905
906 return 0;
907
908 err_clk:
909 clk_unprepare(sport->clk);
910 clk_put(sport->clk);
911 err_free:
912 kfree(sport);
913 return ret;
914}
915
916static struct platform_driver serial_pxa_driver = {
917 .probe = serial_pxa_probe,
918
919 .driver = {
920 .name = "pxa2xx-uart",
921#ifdef CONFIG_PM
922 .pm = &serial_pxa_pm_ops,
923#endif
924 .suppress_bind_attrs = true,
925 .of_match_table = serial_pxa_dt_ids,
926 },
927};
928
929
930/* 8250 driver for PXA serial ports should be used */
931static int __init serial_pxa_init(void)
932{
933 int ret;
934
935 ret = uart_register_driver(&serial_pxa_reg);
936 if (ret != 0)
937 return ret;
938
939 ret = platform_driver_register(&serial_pxa_driver);
940 if (ret != 0)
941 uart_unregister_driver(&serial_pxa_reg);
942
943 return ret;
944}
945device_initcall(serial_pxa_init);
1/*
2 * Based on drivers/serial/8250.c by Russell King.
3 *
4 * Author: Nicolas Pitre
5 * Created: Feb 20, 2003
6 * Copyright: (C) 2003 Monta Vista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * Note 1: This driver is made separate from the already too overloaded
14 * 8250.c because it needs some kirks of its own and that'll make it
15 * easier to add DMA support.
16 *
17 * Note 2: I'm too sick of device allocation policies for serial ports.
18 * If someone else wants to request an "official" allocation of major/minor
19 * for this driver please be my guest. And don't forget that new hardware
20 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
21 * hope for a better port registration and dynamic device allocation scheme
22 * with the serial core maintainer satisfaction to appear soon.
23 */
24
25
26#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27#define SUPPORT_SYSRQ
28#endif
29
30#include <linux/module.h>
31#include <linux/ioport.h>
32#include <linux/init.h>
33#include <linux/console.h>
34#include <linux/sysrq.h>
35#include <linux/serial_reg.h>
36#include <linux/circ_buf.h>
37#include <linux/delay.h>
38#include <linux/interrupt.h>
39#include <linux/of.h>
40#include <linux/platform_device.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/clk.h>
45#include <linux/io.h>
46#include <linux/slab.h>
47
48#define PXA_NAME_LEN 8
49
50struct uart_pxa_port {
51 struct uart_port port;
52 unsigned char ier;
53 unsigned char lcr;
54 unsigned char mcr;
55 unsigned int lsr_break_flag;
56 struct clk *clk;
57 char name[PXA_NAME_LEN];
58};
59
60static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
61{
62 offset <<= 2;
63 return readl(up->port.membase + offset);
64}
65
66static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
67{
68 offset <<= 2;
69 writel(value, up->port.membase + offset);
70}
71
72static void serial_pxa_enable_ms(struct uart_port *port)
73{
74 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
75
76 up->ier |= UART_IER_MSI;
77 serial_out(up, UART_IER, up->ier);
78}
79
80static void serial_pxa_stop_tx(struct uart_port *port)
81{
82 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
83
84 if (up->ier & UART_IER_THRI) {
85 up->ier &= ~UART_IER_THRI;
86 serial_out(up, UART_IER, up->ier);
87 }
88}
89
90static void serial_pxa_stop_rx(struct uart_port *port)
91{
92 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
93
94 up->ier &= ~UART_IER_RLSI;
95 up->port.read_status_mask &= ~UART_LSR_DR;
96 serial_out(up, UART_IER, up->ier);
97}
98
99static inline void receive_chars(struct uart_pxa_port *up, int *status)
100{
101 unsigned int ch, flag;
102 int max_count = 256;
103
104 do {
105 /* work around Errata #20 according to
106 * Intel(R) PXA27x Processor Family
107 * Specification Update (May 2005)
108 *
109 * Step 2
110 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
111 */
112 up->ier &= ~UART_IER_RTOIE;
113 serial_out(up, UART_IER, up->ier);
114
115 ch = serial_in(up, UART_RX);
116 flag = TTY_NORMAL;
117 up->port.icount.rx++;
118
119 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
120 UART_LSR_FE | UART_LSR_OE))) {
121 /*
122 * For statistics only
123 */
124 if (*status & UART_LSR_BI) {
125 *status &= ~(UART_LSR_FE | UART_LSR_PE);
126 up->port.icount.brk++;
127 /*
128 * We do the SysRQ and SAK checking
129 * here because otherwise the break
130 * may get masked by ignore_status_mask
131 * or read_status_mask.
132 */
133 if (uart_handle_break(&up->port))
134 goto ignore_char;
135 } else if (*status & UART_LSR_PE)
136 up->port.icount.parity++;
137 else if (*status & UART_LSR_FE)
138 up->port.icount.frame++;
139 if (*status & UART_LSR_OE)
140 up->port.icount.overrun++;
141
142 /*
143 * Mask off conditions which should be ignored.
144 */
145 *status &= up->port.read_status_mask;
146
147#ifdef CONFIG_SERIAL_PXA_CONSOLE
148 if (up->port.line == up->port.cons->index) {
149 /* Recover the break flag from console xmit */
150 *status |= up->lsr_break_flag;
151 up->lsr_break_flag = 0;
152 }
153#endif
154 if (*status & UART_LSR_BI) {
155 flag = TTY_BREAK;
156 } else if (*status & UART_LSR_PE)
157 flag = TTY_PARITY;
158 else if (*status & UART_LSR_FE)
159 flag = TTY_FRAME;
160 }
161
162 if (uart_handle_sysrq_char(&up->port, ch))
163 goto ignore_char;
164
165 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
166
167 ignore_char:
168 *status = serial_in(up, UART_LSR);
169 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
170 tty_flip_buffer_push(&up->port.state->port);
171
172 /* work around Errata #20 according to
173 * Intel(R) PXA27x Processor Family
174 * Specification Update (May 2005)
175 *
176 * Step 6:
177 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
178 */
179 up->ier |= UART_IER_RTOIE;
180 serial_out(up, UART_IER, up->ier);
181}
182
183static void transmit_chars(struct uart_pxa_port *up)
184{
185 struct circ_buf *xmit = &up->port.state->xmit;
186 int count;
187
188 if (up->port.x_char) {
189 serial_out(up, UART_TX, up->port.x_char);
190 up->port.icount.tx++;
191 up->port.x_char = 0;
192 return;
193 }
194 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
195 serial_pxa_stop_tx(&up->port);
196 return;
197 }
198
199 count = up->port.fifosize / 2;
200 do {
201 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
202 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
203 up->port.icount.tx++;
204 if (uart_circ_empty(xmit))
205 break;
206 } while (--count > 0);
207
208 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
209 uart_write_wakeup(&up->port);
210
211
212 if (uart_circ_empty(xmit))
213 serial_pxa_stop_tx(&up->port);
214}
215
216static void serial_pxa_start_tx(struct uart_port *port)
217{
218 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
219
220 if (!(up->ier & UART_IER_THRI)) {
221 up->ier |= UART_IER_THRI;
222 serial_out(up, UART_IER, up->ier);
223 }
224}
225
226/* should hold up->port.lock */
227static inline void check_modem_status(struct uart_pxa_port *up)
228{
229 int status;
230
231 status = serial_in(up, UART_MSR);
232
233 if ((status & UART_MSR_ANY_DELTA) == 0)
234 return;
235
236 if (status & UART_MSR_TERI)
237 up->port.icount.rng++;
238 if (status & UART_MSR_DDSR)
239 up->port.icount.dsr++;
240 if (status & UART_MSR_DDCD)
241 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
242 if (status & UART_MSR_DCTS)
243 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
244
245 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
246}
247
248/*
249 * This handles the interrupt from one port.
250 */
251static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
252{
253 struct uart_pxa_port *up = dev_id;
254 unsigned int iir, lsr;
255
256 iir = serial_in(up, UART_IIR);
257 if (iir & UART_IIR_NO_INT)
258 return IRQ_NONE;
259 spin_lock(&up->port.lock);
260 lsr = serial_in(up, UART_LSR);
261 if (lsr & UART_LSR_DR)
262 receive_chars(up, &lsr);
263 check_modem_status(up);
264 if (lsr & UART_LSR_THRE)
265 transmit_chars(up);
266 spin_unlock(&up->port.lock);
267 return IRQ_HANDLED;
268}
269
270static unsigned int serial_pxa_tx_empty(struct uart_port *port)
271{
272 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
273 unsigned long flags;
274 unsigned int ret;
275
276 spin_lock_irqsave(&up->port.lock, flags);
277 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
278 spin_unlock_irqrestore(&up->port.lock, flags);
279
280 return ret;
281}
282
283static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
284{
285 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
286 unsigned char status;
287 unsigned int ret;
288
289 status = serial_in(up, UART_MSR);
290
291 ret = 0;
292 if (status & UART_MSR_DCD)
293 ret |= TIOCM_CAR;
294 if (status & UART_MSR_RI)
295 ret |= TIOCM_RNG;
296 if (status & UART_MSR_DSR)
297 ret |= TIOCM_DSR;
298 if (status & UART_MSR_CTS)
299 ret |= TIOCM_CTS;
300 return ret;
301}
302
303static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
304{
305 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
306 unsigned char mcr = 0;
307
308 if (mctrl & TIOCM_RTS)
309 mcr |= UART_MCR_RTS;
310 if (mctrl & TIOCM_DTR)
311 mcr |= UART_MCR_DTR;
312 if (mctrl & TIOCM_OUT1)
313 mcr |= UART_MCR_OUT1;
314 if (mctrl & TIOCM_OUT2)
315 mcr |= UART_MCR_OUT2;
316 if (mctrl & TIOCM_LOOP)
317 mcr |= UART_MCR_LOOP;
318
319 mcr |= up->mcr;
320
321 serial_out(up, UART_MCR, mcr);
322}
323
324static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
325{
326 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
327 unsigned long flags;
328
329 spin_lock_irqsave(&up->port.lock, flags);
330 if (break_state == -1)
331 up->lcr |= UART_LCR_SBC;
332 else
333 up->lcr &= ~UART_LCR_SBC;
334 serial_out(up, UART_LCR, up->lcr);
335 spin_unlock_irqrestore(&up->port.lock, flags);
336}
337
338static int serial_pxa_startup(struct uart_port *port)
339{
340 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
341 unsigned long flags;
342 int retval;
343
344 if (port->line == 3) /* HWUART */
345 up->mcr |= UART_MCR_AFE;
346 else
347 up->mcr = 0;
348
349 up->port.uartclk = clk_get_rate(up->clk);
350
351 /*
352 * Allocate the IRQ
353 */
354 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
355 if (retval)
356 return retval;
357
358 /*
359 * Clear the FIFO buffers and disable them.
360 * (they will be reenabled in set_termios())
361 */
362 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
363 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
364 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
365 serial_out(up, UART_FCR, 0);
366
367 /*
368 * Clear the interrupt registers.
369 */
370 (void) serial_in(up, UART_LSR);
371 (void) serial_in(up, UART_RX);
372 (void) serial_in(up, UART_IIR);
373 (void) serial_in(up, UART_MSR);
374
375 /*
376 * Now, initialize the UART
377 */
378 serial_out(up, UART_LCR, UART_LCR_WLEN8);
379
380 spin_lock_irqsave(&up->port.lock, flags);
381 up->port.mctrl |= TIOCM_OUT2;
382 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
383 spin_unlock_irqrestore(&up->port.lock, flags);
384
385 /*
386 * Finally, enable interrupts. Note: Modem status interrupts
387 * are set via set_termios(), which will be occurring imminently
388 * anyway, so we don't enable them here.
389 */
390 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
391 serial_out(up, UART_IER, up->ier);
392
393 /*
394 * And clear the interrupt registers again for luck.
395 */
396 (void) serial_in(up, UART_LSR);
397 (void) serial_in(up, UART_RX);
398 (void) serial_in(up, UART_IIR);
399 (void) serial_in(up, UART_MSR);
400
401 return 0;
402}
403
404static void serial_pxa_shutdown(struct uart_port *port)
405{
406 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
407 unsigned long flags;
408
409 free_irq(up->port.irq, up);
410
411 /*
412 * Disable interrupts from this port
413 */
414 up->ier = 0;
415 serial_out(up, UART_IER, 0);
416
417 spin_lock_irqsave(&up->port.lock, flags);
418 up->port.mctrl &= ~TIOCM_OUT2;
419 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
420 spin_unlock_irqrestore(&up->port.lock, flags);
421
422 /*
423 * Disable break condition and FIFOs
424 */
425 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
426 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
427 UART_FCR_CLEAR_RCVR |
428 UART_FCR_CLEAR_XMIT);
429 serial_out(up, UART_FCR, 0);
430}
431
432static void
433serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
434 struct ktermios *old)
435{
436 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
437 unsigned char cval, fcr = 0;
438 unsigned long flags;
439 unsigned int baud, quot;
440 unsigned int dll;
441
442 switch (termios->c_cflag & CSIZE) {
443 case CS5:
444 cval = UART_LCR_WLEN5;
445 break;
446 case CS6:
447 cval = UART_LCR_WLEN6;
448 break;
449 case CS7:
450 cval = UART_LCR_WLEN7;
451 break;
452 default:
453 case CS8:
454 cval = UART_LCR_WLEN8;
455 break;
456 }
457
458 if (termios->c_cflag & CSTOPB)
459 cval |= UART_LCR_STOP;
460 if (termios->c_cflag & PARENB)
461 cval |= UART_LCR_PARITY;
462 if (!(termios->c_cflag & PARODD))
463 cval |= UART_LCR_EPAR;
464
465 /*
466 * Ask the core to calculate the divisor for us.
467 */
468 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
469 quot = uart_get_divisor(port, baud);
470
471 if ((up->port.uartclk / quot) < (2400 * 16))
472 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
473 else if ((up->port.uartclk / quot) < (230400 * 16))
474 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
475 else
476 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
477
478 /*
479 * Ok, we're now changing the port state. Do it with
480 * interrupts disabled.
481 */
482 spin_lock_irqsave(&up->port.lock, flags);
483
484 /*
485 * Ensure the port will be enabled.
486 * This is required especially for serial console.
487 */
488 up->ier |= UART_IER_UUE;
489
490 /*
491 * Update the per-port timeout.
492 */
493 uart_update_timeout(port, termios->c_cflag, baud);
494
495 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
496 if (termios->c_iflag & INPCK)
497 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
498 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
499 up->port.read_status_mask |= UART_LSR_BI;
500
501 /*
502 * Characters to ignore
503 */
504 up->port.ignore_status_mask = 0;
505 if (termios->c_iflag & IGNPAR)
506 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
507 if (termios->c_iflag & IGNBRK) {
508 up->port.ignore_status_mask |= UART_LSR_BI;
509 /*
510 * If we're ignoring parity and break indicators,
511 * ignore overruns too (for real raw support).
512 */
513 if (termios->c_iflag & IGNPAR)
514 up->port.ignore_status_mask |= UART_LSR_OE;
515 }
516
517 /*
518 * ignore all characters if CREAD is not set
519 */
520 if ((termios->c_cflag & CREAD) == 0)
521 up->port.ignore_status_mask |= UART_LSR_DR;
522
523 /*
524 * CTS flow control flag and modem status interrupts
525 */
526 up->ier &= ~UART_IER_MSI;
527 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
528 up->ier |= UART_IER_MSI;
529
530 serial_out(up, UART_IER, up->ier);
531
532 if (termios->c_cflag & CRTSCTS)
533 up->mcr |= UART_MCR_AFE;
534 else
535 up->mcr &= ~UART_MCR_AFE;
536
537 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
538 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
539
540 /*
541 * work around Errata #75 according to Intel(R) PXA27x Processor Family
542 * Specification Update (Nov 2005)
543 */
544 dll = serial_in(up, UART_DLL);
545 WARN_ON(dll != (quot & 0xff));
546
547 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
548 serial_out(up, UART_LCR, cval); /* reset DLAB */
549 up->lcr = cval; /* Save LCR */
550 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
551 serial_out(up, UART_FCR, fcr);
552 spin_unlock_irqrestore(&up->port.lock, flags);
553}
554
555static void
556serial_pxa_pm(struct uart_port *port, unsigned int state,
557 unsigned int oldstate)
558{
559 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
560
561 if (!state)
562 clk_prepare_enable(up->clk);
563 else
564 clk_disable_unprepare(up->clk);
565}
566
567static void serial_pxa_release_port(struct uart_port *port)
568{
569}
570
571static int serial_pxa_request_port(struct uart_port *port)
572{
573 return 0;
574}
575
576static void serial_pxa_config_port(struct uart_port *port, int flags)
577{
578 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
579 up->port.type = PORT_PXA;
580}
581
582static int
583serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
584{
585 /* we don't want the core code to modify any port params */
586 return -EINVAL;
587}
588
589static const char *
590serial_pxa_type(struct uart_port *port)
591{
592 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
593 return up->name;
594}
595
596static struct uart_pxa_port *serial_pxa_ports[4];
597static struct uart_driver serial_pxa_reg;
598
599#ifdef CONFIG_SERIAL_PXA_CONSOLE
600
601#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
602
603/*
604 * Wait for transmitter & holding register to empty
605 */
606static void wait_for_xmitr(struct uart_pxa_port *up)
607{
608 unsigned int status, tmout = 10000;
609
610 /* Wait up to 10ms for the character(s) to be sent. */
611 do {
612 status = serial_in(up, UART_LSR);
613
614 if (status & UART_LSR_BI)
615 up->lsr_break_flag = UART_LSR_BI;
616
617 if (--tmout == 0)
618 break;
619 udelay(1);
620 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
621
622 /* Wait up to 1s for flow control if necessary */
623 if (up->port.flags & UPF_CONS_FLOW) {
624 tmout = 1000000;
625 while (--tmout &&
626 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
627 udelay(1);
628 }
629}
630
631static void serial_pxa_console_putchar(struct uart_port *port, int ch)
632{
633 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
634
635 wait_for_xmitr(up);
636 serial_out(up, UART_TX, ch);
637}
638
639/*
640 * Print a string to the serial port trying not to disturb
641 * any possible real use of the port...
642 *
643 * The console_lock must be held when we get here.
644 */
645static void
646serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
647{
648 struct uart_pxa_port *up = serial_pxa_ports[co->index];
649 unsigned int ier;
650 unsigned long flags;
651 int locked = 1;
652
653 clk_enable(up->clk);
654 local_irq_save(flags);
655 if (up->port.sysrq)
656 locked = 0;
657 else if (oops_in_progress)
658 locked = spin_trylock(&up->port.lock);
659 else
660 spin_lock(&up->port.lock);
661
662 /*
663 * First save the IER then disable the interrupts
664 */
665 ier = serial_in(up, UART_IER);
666 serial_out(up, UART_IER, UART_IER_UUE);
667
668 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
669
670 /*
671 * Finally, wait for transmitter to become empty
672 * and restore the IER
673 */
674 wait_for_xmitr(up);
675 serial_out(up, UART_IER, ier);
676
677 if (locked)
678 spin_unlock(&up->port.lock);
679 local_irq_restore(flags);
680 clk_disable(up->clk);
681
682}
683
684#ifdef CONFIG_CONSOLE_POLL
685/*
686 * Console polling routines for writing and reading from the uart while
687 * in an interrupt or debug context.
688 */
689
690static int serial_pxa_get_poll_char(struct uart_port *port)
691{
692 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
693 unsigned char lsr = serial_in(up, UART_LSR);
694
695 while (!(lsr & UART_LSR_DR))
696 lsr = serial_in(up, UART_LSR);
697
698 return serial_in(up, UART_RX);
699}
700
701
702static void serial_pxa_put_poll_char(struct uart_port *port,
703 unsigned char c)
704{
705 unsigned int ier;
706 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
707
708 /*
709 * First save the IER then disable the interrupts
710 */
711 ier = serial_in(up, UART_IER);
712 serial_out(up, UART_IER, UART_IER_UUE);
713
714 wait_for_xmitr(up);
715 /*
716 * Send the character out.
717 */
718 serial_out(up, UART_TX, c);
719
720 /*
721 * Finally, wait for transmitter to become empty
722 * and restore the IER
723 */
724 wait_for_xmitr(up);
725 serial_out(up, UART_IER, ier);
726}
727
728#endif /* CONFIG_CONSOLE_POLL */
729
730static int __init
731serial_pxa_console_setup(struct console *co, char *options)
732{
733 struct uart_pxa_port *up;
734 int baud = 9600;
735 int bits = 8;
736 int parity = 'n';
737 int flow = 'n';
738
739 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
740 co->index = 0;
741 up = serial_pxa_ports[co->index];
742 if (!up)
743 return -ENODEV;
744
745 if (options)
746 uart_parse_options(options, &baud, &parity, &bits, &flow);
747
748 return uart_set_options(&up->port, co, baud, parity, bits, flow);
749}
750
751static struct console serial_pxa_console = {
752 .name = "ttyS",
753 .write = serial_pxa_console_write,
754 .device = uart_console_device,
755 .setup = serial_pxa_console_setup,
756 .flags = CON_PRINTBUFFER,
757 .index = -1,
758 .data = &serial_pxa_reg,
759};
760
761#define PXA_CONSOLE &serial_pxa_console
762#else
763#define PXA_CONSOLE NULL
764#endif
765
766static struct uart_ops serial_pxa_pops = {
767 .tx_empty = serial_pxa_tx_empty,
768 .set_mctrl = serial_pxa_set_mctrl,
769 .get_mctrl = serial_pxa_get_mctrl,
770 .stop_tx = serial_pxa_stop_tx,
771 .start_tx = serial_pxa_start_tx,
772 .stop_rx = serial_pxa_stop_rx,
773 .enable_ms = serial_pxa_enable_ms,
774 .break_ctl = serial_pxa_break_ctl,
775 .startup = serial_pxa_startup,
776 .shutdown = serial_pxa_shutdown,
777 .set_termios = serial_pxa_set_termios,
778 .pm = serial_pxa_pm,
779 .type = serial_pxa_type,
780 .release_port = serial_pxa_release_port,
781 .request_port = serial_pxa_request_port,
782 .config_port = serial_pxa_config_port,
783 .verify_port = serial_pxa_verify_port,
784#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
785 .poll_get_char = serial_pxa_get_poll_char,
786 .poll_put_char = serial_pxa_put_poll_char,
787#endif
788};
789
790static struct uart_driver serial_pxa_reg = {
791 .owner = THIS_MODULE,
792 .driver_name = "PXA serial",
793 .dev_name = "ttyS",
794 .major = TTY_MAJOR,
795 .minor = 64,
796 .nr = 4,
797 .cons = PXA_CONSOLE,
798};
799
800#ifdef CONFIG_PM
801static int serial_pxa_suspend(struct device *dev)
802{
803 struct uart_pxa_port *sport = dev_get_drvdata(dev);
804
805 if (sport)
806 uart_suspend_port(&serial_pxa_reg, &sport->port);
807
808 return 0;
809}
810
811static int serial_pxa_resume(struct device *dev)
812{
813 struct uart_pxa_port *sport = dev_get_drvdata(dev);
814
815 if (sport)
816 uart_resume_port(&serial_pxa_reg, &sport->port);
817
818 return 0;
819}
820
821static const struct dev_pm_ops serial_pxa_pm_ops = {
822 .suspend = serial_pxa_suspend,
823 .resume = serial_pxa_resume,
824};
825#endif
826
827static const struct of_device_id serial_pxa_dt_ids[] = {
828 { .compatible = "mrvl,pxa-uart", },
829 { .compatible = "mrvl,mmp-uart", },
830 {}
831};
832MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids);
833
834static int serial_pxa_probe_dt(struct platform_device *pdev,
835 struct uart_pxa_port *sport)
836{
837 struct device_node *np = pdev->dev.of_node;
838 int ret;
839
840 if (!np)
841 return 1;
842
843 ret = of_alias_get_id(np, "serial");
844 if (ret < 0) {
845 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
846 return ret;
847 }
848 sport->port.line = ret;
849 return 0;
850}
851
852static int serial_pxa_probe(struct platform_device *dev)
853{
854 struct uart_pxa_port *sport;
855 struct resource *mmres, *irqres;
856 int ret;
857
858 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
859 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
860 if (!mmres || !irqres)
861 return -ENODEV;
862
863 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
864 if (!sport)
865 return -ENOMEM;
866
867 sport->clk = clk_get(&dev->dev, NULL);
868 if (IS_ERR(sport->clk)) {
869 ret = PTR_ERR(sport->clk);
870 goto err_free;
871 }
872
873 ret = clk_prepare(sport->clk);
874 if (ret) {
875 clk_put(sport->clk);
876 goto err_free;
877 }
878
879 sport->port.type = PORT_PXA;
880 sport->port.iotype = UPIO_MEM;
881 sport->port.mapbase = mmres->start;
882 sport->port.irq = irqres->start;
883 sport->port.fifosize = 64;
884 sport->port.ops = &serial_pxa_pops;
885 sport->port.dev = &dev->dev;
886 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
887 sport->port.uartclk = clk_get_rate(sport->clk);
888
889 ret = serial_pxa_probe_dt(dev, sport);
890 if (ret > 0)
891 sport->port.line = dev->id;
892 else if (ret < 0)
893 goto err_clk;
894 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
895
896 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
897 if (!sport->port.membase) {
898 ret = -ENOMEM;
899 goto err_clk;
900 }
901
902 serial_pxa_ports[sport->port.line] = sport;
903
904 uart_add_one_port(&serial_pxa_reg, &sport->port);
905 platform_set_drvdata(dev, sport);
906
907 return 0;
908
909 err_clk:
910 clk_unprepare(sport->clk);
911 clk_put(sport->clk);
912 err_free:
913 kfree(sport);
914 return ret;
915}
916
917static int serial_pxa_remove(struct platform_device *dev)
918{
919 struct uart_pxa_port *sport = platform_get_drvdata(dev);
920
921 uart_remove_one_port(&serial_pxa_reg, &sport->port);
922
923 clk_unprepare(sport->clk);
924 clk_put(sport->clk);
925 kfree(sport);
926
927 return 0;
928}
929
930static struct platform_driver serial_pxa_driver = {
931 .probe = serial_pxa_probe,
932 .remove = serial_pxa_remove,
933
934 .driver = {
935 .name = "pxa2xx-uart",
936#ifdef CONFIG_PM
937 .pm = &serial_pxa_pm_ops,
938#endif
939 .of_match_table = serial_pxa_dt_ids,
940 },
941};
942
943static int __init serial_pxa_init(void)
944{
945 int ret;
946
947 ret = uart_register_driver(&serial_pxa_reg);
948 if (ret != 0)
949 return ret;
950
951 ret = platform_driver_register(&serial_pxa_driver);
952 if (ret != 0)
953 uart_unregister_driver(&serial_pxa_reg);
954
955 return ret;
956}
957
958static void __exit serial_pxa_exit(void)
959{
960 platform_driver_unregister(&serial_pxa_driver);
961 uart_unregister_driver(&serial_pxa_reg);
962}
963
964module_init(serial_pxa_init);
965module_exit(serial_pxa_exit);
966
967MODULE_LICENSE("GPL");
968MODULE_ALIAS("platform:pxa2xx-uart");