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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Based on drivers/serial/8250.c by Russell King.
4 *
5 * Author: Nicolas Pitre
6 * Created: Feb 20, 2003
7 * Copyright: (C) 2003 Monta Vista Software, Inc.
8 *
9 * Note 1: This driver is made separate from the already too overloaded
10 * 8250.c because it needs some kirks of its own and that'll make it
11 * easier to add DMA support.
12 *
13 * Note 2: I'm too sick of device allocation policies for serial ports.
14 * If someone else wants to request an "official" allocation of major/minor
15 * for this driver please be my guest. And don't forget that new hardware
16 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17 * hope for a better port registration and dynamic device allocation scheme
18 * with the serial core maintainer satisfaction to appear soon.
19 */
20
21
22#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
25
26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/sysrq.h>
30#include <linux/serial_reg.h>
31#include <linux/circ_buf.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/of.h>
35#include <linux/platform_device.h>
36#include <linux/tty.h>
37#include <linux/tty_flip.h>
38#include <linux/serial_core.h>
39#include <linux/clk.h>
40#include <linux/io.h>
41#include <linux/slab.h>
42
43#define PXA_NAME_LEN 8
44
45struct uart_pxa_port {
46 struct uart_port port;
47 unsigned char ier;
48 unsigned char lcr;
49 unsigned char mcr;
50 unsigned int lsr_break_flag;
51 struct clk *clk;
52 char name[PXA_NAME_LEN];
53};
54
55static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
56{
57 offset <<= 2;
58 return readl(up->port.membase + offset);
59}
60
61static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
62{
63 offset <<= 2;
64 writel(value, up->port.membase + offset);
65}
66
67static void serial_pxa_enable_ms(struct uart_port *port)
68{
69 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
70
71 up->ier |= UART_IER_MSI;
72 serial_out(up, UART_IER, up->ier);
73}
74
75static void serial_pxa_stop_tx(struct uart_port *port)
76{
77 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
78
79 if (up->ier & UART_IER_THRI) {
80 up->ier &= ~UART_IER_THRI;
81 serial_out(up, UART_IER, up->ier);
82 }
83}
84
85static void serial_pxa_stop_rx(struct uart_port *port)
86{
87 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
88
89 up->ier &= ~UART_IER_RLSI;
90 up->port.read_status_mask &= ~UART_LSR_DR;
91 serial_out(up, UART_IER, up->ier);
92}
93
94static inline void receive_chars(struct uart_pxa_port *up, int *status)
95{
96 unsigned int ch, flag;
97 int max_count = 256;
98
99 do {
100 /* work around Errata #20 according to
101 * Intel(R) PXA27x Processor Family
102 * Specification Update (May 2005)
103 *
104 * Step 2
105 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
106 */
107 up->ier &= ~UART_IER_RTOIE;
108 serial_out(up, UART_IER, up->ier);
109
110 ch = serial_in(up, UART_RX);
111 flag = TTY_NORMAL;
112 up->port.icount.rx++;
113
114 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
115 UART_LSR_FE | UART_LSR_OE))) {
116 /*
117 * For statistics only
118 */
119 if (*status & UART_LSR_BI) {
120 *status &= ~(UART_LSR_FE | UART_LSR_PE);
121 up->port.icount.brk++;
122 /*
123 * We do the SysRQ and SAK checking
124 * here because otherwise the break
125 * may get masked by ignore_status_mask
126 * or read_status_mask.
127 */
128 if (uart_handle_break(&up->port))
129 goto ignore_char;
130 } else if (*status & UART_LSR_PE)
131 up->port.icount.parity++;
132 else if (*status & UART_LSR_FE)
133 up->port.icount.frame++;
134 if (*status & UART_LSR_OE)
135 up->port.icount.overrun++;
136
137 /*
138 * Mask off conditions which should be ignored.
139 */
140 *status &= up->port.read_status_mask;
141
142#ifdef CONFIG_SERIAL_PXA_CONSOLE
143 if (up->port.line == up->port.cons->index) {
144 /* Recover the break flag from console xmit */
145 *status |= up->lsr_break_flag;
146 up->lsr_break_flag = 0;
147 }
148#endif
149 if (*status & UART_LSR_BI) {
150 flag = TTY_BREAK;
151 } else if (*status & UART_LSR_PE)
152 flag = TTY_PARITY;
153 else if (*status & UART_LSR_FE)
154 flag = TTY_FRAME;
155 }
156
157 if (uart_handle_sysrq_char(&up->port, ch))
158 goto ignore_char;
159
160 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
161
162 ignore_char:
163 *status = serial_in(up, UART_LSR);
164 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
165 tty_flip_buffer_push(&up->port.state->port);
166
167 /* work around Errata #20 according to
168 * Intel(R) PXA27x Processor Family
169 * Specification Update (May 2005)
170 *
171 * Step 6:
172 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
173 */
174 up->ier |= UART_IER_RTOIE;
175 serial_out(up, UART_IER, up->ier);
176}
177
178static void transmit_chars(struct uart_pxa_port *up)
179{
180 struct circ_buf *xmit = &up->port.state->xmit;
181 int count;
182
183 if (up->port.x_char) {
184 serial_out(up, UART_TX, up->port.x_char);
185 up->port.icount.tx++;
186 up->port.x_char = 0;
187 return;
188 }
189 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
190 serial_pxa_stop_tx(&up->port);
191 return;
192 }
193
194 count = up->port.fifosize / 2;
195 do {
196 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
197 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
198 up->port.icount.tx++;
199 if (uart_circ_empty(xmit))
200 break;
201 } while (--count > 0);
202
203 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
204 uart_write_wakeup(&up->port);
205
206
207 if (uart_circ_empty(xmit))
208 serial_pxa_stop_tx(&up->port);
209}
210
211static void serial_pxa_start_tx(struct uart_port *port)
212{
213 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
214
215 if (!(up->ier & UART_IER_THRI)) {
216 up->ier |= UART_IER_THRI;
217 serial_out(up, UART_IER, up->ier);
218 }
219}
220
221/* should hold up->port.lock */
222static inline void check_modem_status(struct uart_pxa_port *up)
223{
224 int status;
225
226 status = serial_in(up, UART_MSR);
227
228 if ((status & UART_MSR_ANY_DELTA) == 0)
229 return;
230
231 if (status & UART_MSR_TERI)
232 up->port.icount.rng++;
233 if (status & UART_MSR_DDSR)
234 up->port.icount.dsr++;
235 if (status & UART_MSR_DDCD)
236 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
237 if (status & UART_MSR_DCTS)
238 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
239
240 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
241}
242
243/*
244 * This handles the interrupt from one port.
245 */
246static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
247{
248 struct uart_pxa_port *up = dev_id;
249 unsigned int iir, lsr;
250
251 iir = serial_in(up, UART_IIR);
252 if (iir & UART_IIR_NO_INT)
253 return IRQ_NONE;
254 spin_lock(&up->port.lock);
255 lsr = serial_in(up, UART_LSR);
256 if (lsr & UART_LSR_DR)
257 receive_chars(up, &lsr);
258 check_modem_status(up);
259 if (lsr & UART_LSR_THRE)
260 transmit_chars(up);
261 spin_unlock(&up->port.lock);
262 return IRQ_HANDLED;
263}
264
265static unsigned int serial_pxa_tx_empty(struct uart_port *port)
266{
267 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
268 unsigned long flags;
269 unsigned int ret;
270
271 spin_lock_irqsave(&up->port.lock, flags);
272 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
273 spin_unlock_irqrestore(&up->port.lock, flags);
274
275 return ret;
276}
277
278static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
279{
280 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
281 unsigned char status;
282 unsigned int ret;
283
284 status = serial_in(up, UART_MSR);
285
286 ret = 0;
287 if (status & UART_MSR_DCD)
288 ret |= TIOCM_CAR;
289 if (status & UART_MSR_RI)
290 ret |= TIOCM_RNG;
291 if (status & UART_MSR_DSR)
292 ret |= TIOCM_DSR;
293 if (status & UART_MSR_CTS)
294 ret |= TIOCM_CTS;
295 return ret;
296}
297
298static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
299{
300 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
301 unsigned char mcr = 0;
302
303 if (mctrl & TIOCM_RTS)
304 mcr |= UART_MCR_RTS;
305 if (mctrl & TIOCM_DTR)
306 mcr |= UART_MCR_DTR;
307 if (mctrl & TIOCM_OUT1)
308 mcr |= UART_MCR_OUT1;
309 if (mctrl & TIOCM_OUT2)
310 mcr |= UART_MCR_OUT2;
311 if (mctrl & TIOCM_LOOP)
312 mcr |= UART_MCR_LOOP;
313
314 mcr |= up->mcr;
315
316 serial_out(up, UART_MCR, mcr);
317}
318
319static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
320{
321 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
322 unsigned long flags;
323
324 spin_lock_irqsave(&up->port.lock, flags);
325 if (break_state == -1)
326 up->lcr |= UART_LCR_SBC;
327 else
328 up->lcr &= ~UART_LCR_SBC;
329 serial_out(up, UART_LCR, up->lcr);
330 spin_unlock_irqrestore(&up->port.lock, flags);
331}
332
333static int serial_pxa_startup(struct uart_port *port)
334{
335 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
336 unsigned long flags;
337 int retval;
338
339 if (port->line == 3) /* HWUART */
340 up->mcr |= UART_MCR_AFE;
341 else
342 up->mcr = 0;
343
344 up->port.uartclk = clk_get_rate(up->clk);
345
346 /*
347 * Allocate the IRQ
348 */
349 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
350 if (retval)
351 return retval;
352
353 /*
354 * Clear the FIFO buffers and disable them.
355 * (they will be reenabled in set_termios())
356 */
357 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
358 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
359 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
360 serial_out(up, UART_FCR, 0);
361
362 /*
363 * Clear the interrupt registers.
364 */
365 (void) serial_in(up, UART_LSR);
366 (void) serial_in(up, UART_RX);
367 (void) serial_in(up, UART_IIR);
368 (void) serial_in(up, UART_MSR);
369
370 /*
371 * Now, initialize the UART
372 */
373 serial_out(up, UART_LCR, UART_LCR_WLEN8);
374
375 spin_lock_irqsave(&up->port.lock, flags);
376 up->port.mctrl |= TIOCM_OUT2;
377 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
378 spin_unlock_irqrestore(&up->port.lock, flags);
379
380 /*
381 * Finally, enable interrupts. Note: Modem status interrupts
382 * are set via set_termios(), which will be occurring imminently
383 * anyway, so we don't enable them here.
384 */
385 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
386 serial_out(up, UART_IER, up->ier);
387
388 /*
389 * And clear the interrupt registers again for luck.
390 */
391 (void) serial_in(up, UART_LSR);
392 (void) serial_in(up, UART_RX);
393 (void) serial_in(up, UART_IIR);
394 (void) serial_in(up, UART_MSR);
395
396 return 0;
397}
398
399static void serial_pxa_shutdown(struct uart_port *port)
400{
401 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
402 unsigned long flags;
403
404 free_irq(up->port.irq, up);
405
406 /*
407 * Disable interrupts from this port
408 */
409 up->ier = 0;
410 serial_out(up, UART_IER, 0);
411
412 spin_lock_irqsave(&up->port.lock, flags);
413 up->port.mctrl &= ~TIOCM_OUT2;
414 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
415 spin_unlock_irqrestore(&up->port.lock, flags);
416
417 /*
418 * Disable break condition and FIFOs
419 */
420 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
421 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
422 UART_FCR_CLEAR_RCVR |
423 UART_FCR_CLEAR_XMIT);
424 serial_out(up, UART_FCR, 0);
425}
426
427static void
428serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
429 struct ktermios *old)
430{
431 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
432 unsigned char cval, fcr = 0;
433 unsigned long flags;
434 unsigned int baud, quot;
435 unsigned int dll;
436
437 switch (termios->c_cflag & CSIZE) {
438 case CS5:
439 cval = UART_LCR_WLEN5;
440 break;
441 case CS6:
442 cval = UART_LCR_WLEN6;
443 break;
444 case CS7:
445 cval = UART_LCR_WLEN7;
446 break;
447 default:
448 case CS8:
449 cval = UART_LCR_WLEN8;
450 break;
451 }
452
453 if (termios->c_cflag & CSTOPB)
454 cval |= UART_LCR_STOP;
455 if (termios->c_cflag & PARENB)
456 cval |= UART_LCR_PARITY;
457 if (!(termios->c_cflag & PARODD))
458 cval |= UART_LCR_EPAR;
459
460 /*
461 * Ask the core to calculate the divisor for us.
462 */
463 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
464 quot = uart_get_divisor(port, baud);
465
466 if ((up->port.uartclk / quot) < (2400 * 16))
467 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
468 else if ((up->port.uartclk / quot) < (230400 * 16))
469 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
470 else
471 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
472
473 /*
474 * Ok, we're now changing the port state. Do it with
475 * interrupts disabled.
476 */
477 spin_lock_irqsave(&up->port.lock, flags);
478
479 /*
480 * Ensure the port will be enabled.
481 * This is required especially for serial console.
482 */
483 up->ier |= UART_IER_UUE;
484
485 /*
486 * Update the per-port timeout.
487 */
488 uart_update_timeout(port, termios->c_cflag, baud);
489
490 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
491 if (termios->c_iflag & INPCK)
492 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
493 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
494 up->port.read_status_mask |= UART_LSR_BI;
495
496 /*
497 * Characters to ignore
498 */
499 up->port.ignore_status_mask = 0;
500 if (termios->c_iflag & IGNPAR)
501 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
502 if (termios->c_iflag & IGNBRK) {
503 up->port.ignore_status_mask |= UART_LSR_BI;
504 /*
505 * If we're ignoring parity and break indicators,
506 * ignore overruns too (for real raw support).
507 */
508 if (termios->c_iflag & IGNPAR)
509 up->port.ignore_status_mask |= UART_LSR_OE;
510 }
511
512 /*
513 * ignore all characters if CREAD is not set
514 */
515 if ((termios->c_cflag & CREAD) == 0)
516 up->port.ignore_status_mask |= UART_LSR_DR;
517
518 /*
519 * CTS flow control flag and modem status interrupts
520 */
521 up->ier &= ~UART_IER_MSI;
522 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
523 up->ier |= UART_IER_MSI;
524
525 serial_out(up, UART_IER, up->ier);
526
527 if (termios->c_cflag & CRTSCTS)
528 up->mcr |= UART_MCR_AFE;
529 else
530 up->mcr &= ~UART_MCR_AFE;
531
532 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
533 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
534
535 /*
536 * work around Errata #75 according to Intel(R) PXA27x Processor Family
537 * Specification Update (Nov 2005)
538 */
539 dll = serial_in(up, UART_DLL);
540 WARN_ON(dll != (quot & 0xff));
541
542 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
543 serial_out(up, UART_LCR, cval); /* reset DLAB */
544 up->lcr = cval; /* Save LCR */
545 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
546 serial_out(up, UART_FCR, fcr);
547 spin_unlock_irqrestore(&up->port.lock, flags);
548}
549
550static void
551serial_pxa_pm(struct uart_port *port, unsigned int state,
552 unsigned int oldstate)
553{
554 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
555
556 if (!state)
557 clk_prepare_enable(up->clk);
558 else
559 clk_disable_unprepare(up->clk);
560}
561
562static void serial_pxa_release_port(struct uart_port *port)
563{
564}
565
566static int serial_pxa_request_port(struct uart_port *port)
567{
568 return 0;
569}
570
571static void serial_pxa_config_port(struct uart_port *port, int flags)
572{
573 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
574 up->port.type = PORT_PXA;
575}
576
577static int
578serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
579{
580 /* we don't want the core code to modify any port params */
581 return -EINVAL;
582}
583
584static const char *
585serial_pxa_type(struct uart_port *port)
586{
587 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
588 return up->name;
589}
590
591static struct uart_pxa_port *serial_pxa_ports[4];
592static struct uart_driver serial_pxa_reg;
593
594#ifdef CONFIG_SERIAL_PXA_CONSOLE
595
596#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
597
598/*
599 * Wait for transmitter & holding register to empty
600 */
601static void wait_for_xmitr(struct uart_pxa_port *up)
602{
603 unsigned int status, tmout = 10000;
604
605 /* Wait up to 10ms for the character(s) to be sent. */
606 do {
607 status = serial_in(up, UART_LSR);
608
609 if (status & UART_LSR_BI)
610 up->lsr_break_flag = UART_LSR_BI;
611
612 if (--tmout == 0)
613 break;
614 udelay(1);
615 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
616
617 /* Wait up to 1s for flow control if necessary */
618 if (up->port.flags & UPF_CONS_FLOW) {
619 tmout = 1000000;
620 while (--tmout &&
621 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
622 udelay(1);
623 }
624}
625
626static void serial_pxa_console_putchar(struct uart_port *port, int ch)
627{
628 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
629
630 wait_for_xmitr(up);
631 serial_out(up, UART_TX, ch);
632}
633
634/*
635 * Print a string to the serial port trying not to disturb
636 * any possible real use of the port...
637 *
638 * The console_lock must be held when we get here.
639 */
640static void
641serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
642{
643 struct uart_pxa_port *up = serial_pxa_ports[co->index];
644 unsigned int ier;
645 unsigned long flags;
646 int locked = 1;
647
648 clk_enable(up->clk);
649 local_irq_save(flags);
650 if (up->port.sysrq)
651 locked = 0;
652 else if (oops_in_progress)
653 locked = spin_trylock(&up->port.lock);
654 else
655 spin_lock(&up->port.lock);
656
657 /*
658 * First save the IER then disable the interrupts
659 */
660 ier = serial_in(up, UART_IER);
661 serial_out(up, UART_IER, UART_IER_UUE);
662
663 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
664
665 /*
666 * Finally, wait for transmitter to become empty
667 * and restore the IER
668 */
669 wait_for_xmitr(up);
670 serial_out(up, UART_IER, ier);
671
672 if (locked)
673 spin_unlock(&up->port.lock);
674 local_irq_restore(flags);
675 clk_disable(up->clk);
676
677}
678
679#ifdef CONFIG_CONSOLE_POLL
680/*
681 * Console polling routines for writing and reading from the uart while
682 * in an interrupt or debug context.
683 */
684
685static int serial_pxa_get_poll_char(struct uart_port *port)
686{
687 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
688 unsigned char lsr = serial_in(up, UART_LSR);
689
690 while (!(lsr & UART_LSR_DR))
691 lsr = serial_in(up, UART_LSR);
692
693 return serial_in(up, UART_RX);
694}
695
696
697static void serial_pxa_put_poll_char(struct uart_port *port,
698 unsigned char c)
699{
700 unsigned int ier;
701 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
702
703 /*
704 * First save the IER then disable the interrupts
705 */
706 ier = serial_in(up, UART_IER);
707 serial_out(up, UART_IER, UART_IER_UUE);
708
709 wait_for_xmitr(up);
710 /*
711 * Send the character out.
712 */
713 serial_out(up, UART_TX, c);
714
715 /*
716 * Finally, wait for transmitter to become empty
717 * and restore the IER
718 */
719 wait_for_xmitr(up);
720 serial_out(up, UART_IER, ier);
721}
722
723#endif /* CONFIG_CONSOLE_POLL */
724
725static int __init
726serial_pxa_console_setup(struct console *co, char *options)
727{
728 struct uart_pxa_port *up;
729 int baud = 9600;
730 int bits = 8;
731 int parity = 'n';
732 int flow = 'n';
733
734 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
735 co->index = 0;
736 up = serial_pxa_ports[co->index];
737 if (!up)
738 return -ENODEV;
739
740 if (options)
741 uart_parse_options(options, &baud, &parity, &bits, &flow);
742
743 return uart_set_options(&up->port, co, baud, parity, bits, flow);
744}
745
746static struct console serial_pxa_console = {
747 .name = "ttyS",
748 .write = serial_pxa_console_write,
749 .device = uart_console_device,
750 .setup = serial_pxa_console_setup,
751 .flags = CON_PRINTBUFFER,
752 .index = -1,
753 .data = &serial_pxa_reg,
754};
755
756#define PXA_CONSOLE &serial_pxa_console
757#else
758#define PXA_CONSOLE NULL
759#endif
760
761static const struct uart_ops serial_pxa_pops = {
762 .tx_empty = serial_pxa_tx_empty,
763 .set_mctrl = serial_pxa_set_mctrl,
764 .get_mctrl = serial_pxa_get_mctrl,
765 .stop_tx = serial_pxa_stop_tx,
766 .start_tx = serial_pxa_start_tx,
767 .stop_rx = serial_pxa_stop_rx,
768 .enable_ms = serial_pxa_enable_ms,
769 .break_ctl = serial_pxa_break_ctl,
770 .startup = serial_pxa_startup,
771 .shutdown = serial_pxa_shutdown,
772 .set_termios = serial_pxa_set_termios,
773 .pm = serial_pxa_pm,
774 .type = serial_pxa_type,
775 .release_port = serial_pxa_release_port,
776 .request_port = serial_pxa_request_port,
777 .config_port = serial_pxa_config_port,
778 .verify_port = serial_pxa_verify_port,
779#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
780 .poll_get_char = serial_pxa_get_poll_char,
781 .poll_put_char = serial_pxa_put_poll_char,
782#endif
783};
784
785static struct uart_driver serial_pxa_reg = {
786 .owner = THIS_MODULE,
787 .driver_name = "PXA serial",
788 .dev_name = "ttyS",
789 .major = TTY_MAJOR,
790 .minor = 64,
791 .nr = 4,
792 .cons = PXA_CONSOLE,
793};
794
795#ifdef CONFIG_PM
796static int serial_pxa_suspend(struct device *dev)
797{
798 struct uart_pxa_port *sport = dev_get_drvdata(dev);
799
800 if (sport)
801 uart_suspend_port(&serial_pxa_reg, &sport->port);
802
803 return 0;
804}
805
806static int serial_pxa_resume(struct device *dev)
807{
808 struct uart_pxa_port *sport = dev_get_drvdata(dev);
809
810 if (sport)
811 uart_resume_port(&serial_pxa_reg, &sport->port);
812
813 return 0;
814}
815
816static const struct dev_pm_ops serial_pxa_pm_ops = {
817 .suspend = serial_pxa_suspend,
818 .resume = serial_pxa_resume,
819};
820#endif
821
822static const struct of_device_id serial_pxa_dt_ids[] = {
823 { .compatible = "mrvl,pxa-uart", },
824 { .compatible = "mrvl,mmp-uart", },
825 {}
826};
827
828static int serial_pxa_probe_dt(struct platform_device *pdev,
829 struct uart_pxa_port *sport)
830{
831 struct device_node *np = pdev->dev.of_node;
832 int ret;
833
834 if (!np)
835 return 1;
836
837 ret = of_alias_get_id(np, "serial");
838 if (ret < 0) {
839 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
840 return ret;
841 }
842 sport->port.line = ret;
843 return 0;
844}
845
846static int serial_pxa_probe(struct platform_device *dev)
847{
848 struct uart_pxa_port *sport;
849 struct resource *mmres, *irqres;
850 int ret;
851
852 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
853 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
854 if (!mmres || !irqres)
855 return -ENODEV;
856
857 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
858 if (!sport)
859 return -ENOMEM;
860
861 sport->clk = clk_get(&dev->dev, NULL);
862 if (IS_ERR(sport->clk)) {
863 ret = PTR_ERR(sport->clk);
864 goto err_free;
865 }
866
867 ret = clk_prepare(sport->clk);
868 if (ret) {
869 clk_put(sport->clk);
870 goto err_free;
871 }
872
873 sport->port.type = PORT_PXA;
874 sport->port.iotype = UPIO_MEM;
875 sport->port.mapbase = mmres->start;
876 sport->port.irq = irqres->start;
877 sport->port.fifosize = 64;
878 sport->port.ops = &serial_pxa_pops;
879 sport->port.dev = &dev->dev;
880 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
881 sport->port.uartclk = clk_get_rate(sport->clk);
882
883 ret = serial_pxa_probe_dt(dev, sport);
884 if (ret > 0)
885 sport->port.line = dev->id;
886 else if (ret < 0)
887 goto err_clk;
888 if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
889 dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
890 ret = -EINVAL;
891 goto err_clk;
892 }
893 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
894
895 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
896 if (!sport->port.membase) {
897 ret = -ENOMEM;
898 goto err_clk;
899 }
900
901 serial_pxa_ports[sport->port.line] = sport;
902
903 uart_add_one_port(&serial_pxa_reg, &sport->port);
904 platform_set_drvdata(dev, sport);
905
906 return 0;
907
908 err_clk:
909 clk_unprepare(sport->clk);
910 clk_put(sport->clk);
911 err_free:
912 kfree(sport);
913 return ret;
914}
915
916static struct platform_driver serial_pxa_driver = {
917 .probe = serial_pxa_probe,
918
919 .driver = {
920 .name = "pxa2xx-uart",
921#ifdef CONFIG_PM
922 .pm = &serial_pxa_pm_ops,
923#endif
924 .suppress_bind_attrs = true,
925 .of_match_table = serial_pxa_dt_ids,
926 },
927};
928
929
930/* 8250 driver for PXA serial ports should be used */
931static int __init serial_pxa_init(void)
932{
933 int ret;
934
935 ret = uart_register_driver(&serial_pxa_reg);
936 if (ret != 0)
937 return ret;
938
939 ret = platform_driver_register(&serial_pxa_driver);
940 if (ret != 0)
941 uart_unregister_driver(&serial_pxa_reg);
942
943 return ret;
944}
945device_initcall(serial_pxa_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Based on drivers/serial/8250.c by Russell King.
4 *
5 * Author: Nicolas Pitre
6 * Created: Feb 20, 2003
7 * Copyright: (C) 2003 Monta Vista Software, Inc.
8 *
9 * Note 1: This driver is made separate from the already too overloaded
10 * 8250.c because it needs some kirks of its own and that'll make it
11 * easier to add DMA support.
12 *
13 * Note 2: I'm too sick of device allocation policies for serial ports.
14 * If someone else wants to request an "official" allocation of major/minor
15 * for this driver please be my guest. And don't forget that new hardware
16 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17 * hope for a better port registration and dynamic device allocation scheme
18 * with the serial core maintainer satisfaction to appear soon.
19 */
20
21
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/sysrq.h>
26#include <linux/serial_reg.h>
27#include <linux/circ_buf.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/of.h>
31#include <linux/platform_device.h>
32#include <linux/tty.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_core.h>
35#include <linux/clk.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38
39#define PXA_NAME_LEN 8
40
41struct uart_pxa_port {
42 struct uart_port port;
43 unsigned char ier;
44 unsigned char lcr;
45 unsigned char mcr;
46 unsigned int lsr_break_flag;
47 struct clk *clk;
48 char name[PXA_NAME_LEN];
49};
50
51static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
52{
53 offset <<= 2;
54 return readl(up->port.membase + offset);
55}
56
57static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
58{
59 offset <<= 2;
60 writel(value, up->port.membase + offset);
61}
62
63static void serial_pxa_enable_ms(struct uart_port *port)
64{
65 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
66
67 up->ier |= UART_IER_MSI;
68 serial_out(up, UART_IER, up->ier);
69}
70
71static void serial_pxa_stop_tx(struct uart_port *port)
72{
73 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
74
75 if (up->ier & UART_IER_THRI) {
76 up->ier &= ~UART_IER_THRI;
77 serial_out(up, UART_IER, up->ier);
78 }
79}
80
81static void serial_pxa_stop_rx(struct uart_port *port)
82{
83 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
84
85 up->ier &= ~UART_IER_RLSI;
86 up->port.read_status_mask &= ~UART_LSR_DR;
87 serial_out(up, UART_IER, up->ier);
88}
89
90static inline void receive_chars(struct uart_pxa_port *up, int *status)
91{
92 unsigned int ch, flag;
93 int max_count = 256;
94
95 do {
96 /* work around Errata #20 according to
97 * Intel(R) PXA27x Processor Family
98 * Specification Update (May 2005)
99 *
100 * Step 2
101 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
102 */
103 up->ier &= ~UART_IER_RTOIE;
104 serial_out(up, UART_IER, up->ier);
105
106 ch = serial_in(up, UART_RX);
107 flag = TTY_NORMAL;
108 up->port.icount.rx++;
109
110 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
111 UART_LSR_FE | UART_LSR_OE))) {
112 /*
113 * For statistics only
114 */
115 if (*status & UART_LSR_BI) {
116 *status &= ~(UART_LSR_FE | UART_LSR_PE);
117 up->port.icount.brk++;
118 /*
119 * We do the SysRQ and SAK checking
120 * here because otherwise the break
121 * may get masked by ignore_status_mask
122 * or read_status_mask.
123 */
124 if (uart_handle_break(&up->port))
125 goto ignore_char;
126 } else if (*status & UART_LSR_PE)
127 up->port.icount.parity++;
128 else if (*status & UART_LSR_FE)
129 up->port.icount.frame++;
130 if (*status & UART_LSR_OE)
131 up->port.icount.overrun++;
132
133 /*
134 * Mask off conditions which should be ignored.
135 */
136 *status &= up->port.read_status_mask;
137
138#ifdef CONFIG_SERIAL_PXA_CONSOLE
139 if (up->port.line == up->port.cons->index) {
140 /* Recover the break flag from console xmit */
141 *status |= up->lsr_break_flag;
142 up->lsr_break_flag = 0;
143 }
144#endif
145 if (*status & UART_LSR_BI) {
146 flag = TTY_BREAK;
147 } else if (*status & UART_LSR_PE)
148 flag = TTY_PARITY;
149 else if (*status & UART_LSR_FE)
150 flag = TTY_FRAME;
151 }
152
153 if (uart_handle_sysrq_char(&up->port, ch))
154 goto ignore_char;
155
156 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
157
158 ignore_char:
159 *status = serial_in(up, UART_LSR);
160 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
161 tty_flip_buffer_push(&up->port.state->port);
162
163 /* work around Errata #20 according to
164 * Intel(R) PXA27x Processor Family
165 * Specification Update (May 2005)
166 *
167 * Step 6:
168 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
169 */
170 up->ier |= UART_IER_RTOIE;
171 serial_out(up, UART_IER, up->ier);
172}
173
174static void transmit_chars(struct uart_pxa_port *up)
175{
176 struct circ_buf *xmit = &up->port.state->xmit;
177 int count;
178
179 if (up->port.x_char) {
180 serial_out(up, UART_TX, up->port.x_char);
181 up->port.icount.tx++;
182 up->port.x_char = 0;
183 return;
184 }
185 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
186 serial_pxa_stop_tx(&up->port);
187 return;
188 }
189
190 count = up->port.fifosize / 2;
191 do {
192 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
194 up->port.icount.tx++;
195 if (uart_circ_empty(xmit))
196 break;
197 } while (--count > 0);
198
199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
200 uart_write_wakeup(&up->port);
201
202
203 if (uart_circ_empty(xmit))
204 serial_pxa_stop_tx(&up->port);
205}
206
207static void serial_pxa_start_tx(struct uart_port *port)
208{
209 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
210
211 if (!(up->ier & UART_IER_THRI)) {
212 up->ier |= UART_IER_THRI;
213 serial_out(up, UART_IER, up->ier);
214 }
215}
216
217/* should hold up->port.lock */
218static inline void check_modem_status(struct uart_pxa_port *up)
219{
220 int status;
221
222 status = serial_in(up, UART_MSR);
223
224 if ((status & UART_MSR_ANY_DELTA) == 0)
225 return;
226
227 if (status & UART_MSR_TERI)
228 up->port.icount.rng++;
229 if (status & UART_MSR_DDSR)
230 up->port.icount.dsr++;
231 if (status & UART_MSR_DDCD)
232 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
233 if (status & UART_MSR_DCTS)
234 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
235
236 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
237}
238
239/*
240 * This handles the interrupt from one port.
241 */
242static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
243{
244 struct uart_pxa_port *up = dev_id;
245 unsigned int iir, lsr;
246
247 iir = serial_in(up, UART_IIR);
248 if (iir & UART_IIR_NO_INT)
249 return IRQ_NONE;
250 spin_lock(&up->port.lock);
251 lsr = serial_in(up, UART_LSR);
252 if (lsr & UART_LSR_DR)
253 receive_chars(up, &lsr);
254 check_modem_status(up);
255 if (lsr & UART_LSR_THRE)
256 transmit_chars(up);
257 spin_unlock(&up->port.lock);
258 return IRQ_HANDLED;
259}
260
261static unsigned int serial_pxa_tx_empty(struct uart_port *port)
262{
263 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
264 unsigned long flags;
265 unsigned int ret;
266
267 spin_lock_irqsave(&up->port.lock, flags);
268 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
269 spin_unlock_irqrestore(&up->port.lock, flags);
270
271 return ret;
272}
273
274static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
275{
276 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
277 unsigned char status;
278 unsigned int ret;
279
280 status = serial_in(up, UART_MSR);
281
282 ret = 0;
283 if (status & UART_MSR_DCD)
284 ret |= TIOCM_CAR;
285 if (status & UART_MSR_RI)
286 ret |= TIOCM_RNG;
287 if (status & UART_MSR_DSR)
288 ret |= TIOCM_DSR;
289 if (status & UART_MSR_CTS)
290 ret |= TIOCM_CTS;
291 return ret;
292}
293
294static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
295{
296 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
297 unsigned char mcr = 0;
298
299 if (mctrl & TIOCM_RTS)
300 mcr |= UART_MCR_RTS;
301 if (mctrl & TIOCM_DTR)
302 mcr |= UART_MCR_DTR;
303 if (mctrl & TIOCM_OUT1)
304 mcr |= UART_MCR_OUT1;
305 if (mctrl & TIOCM_OUT2)
306 mcr |= UART_MCR_OUT2;
307 if (mctrl & TIOCM_LOOP)
308 mcr |= UART_MCR_LOOP;
309
310 mcr |= up->mcr;
311
312 serial_out(up, UART_MCR, mcr);
313}
314
315static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
316{
317 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
318 unsigned long flags;
319
320 spin_lock_irqsave(&up->port.lock, flags);
321 if (break_state == -1)
322 up->lcr |= UART_LCR_SBC;
323 else
324 up->lcr &= ~UART_LCR_SBC;
325 serial_out(up, UART_LCR, up->lcr);
326 spin_unlock_irqrestore(&up->port.lock, flags);
327}
328
329static int serial_pxa_startup(struct uart_port *port)
330{
331 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
332 unsigned long flags;
333 int retval;
334
335 if (port->line == 3) /* HWUART */
336 up->mcr |= UART_MCR_AFE;
337 else
338 up->mcr = 0;
339
340 up->port.uartclk = clk_get_rate(up->clk);
341
342 /*
343 * Allocate the IRQ
344 */
345 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
346 if (retval)
347 return retval;
348
349 /*
350 * Clear the FIFO buffers and disable them.
351 * (they will be reenabled in set_termios())
352 */
353 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
354 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
355 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
356 serial_out(up, UART_FCR, 0);
357
358 /*
359 * Clear the interrupt registers.
360 */
361 (void) serial_in(up, UART_LSR);
362 (void) serial_in(up, UART_RX);
363 (void) serial_in(up, UART_IIR);
364 (void) serial_in(up, UART_MSR);
365
366 /*
367 * Now, initialize the UART
368 */
369 serial_out(up, UART_LCR, UART_LCR_WLEN8);
370
371 spin_lock_irqsave(&up->port.lock, flags);
372 up->port.mctrl |= TIOCM_OUT2;
373 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
374 spin_unlock_irqrestore(&up->port.lock, flags);
375
376 /*
377 * Finally, enable interrupts. Note: Modem status interrupts
378 * are set via set_termios(), which will be occurring imminently
379 * anyway, so we don't enable them here.
380 */
381 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
382 serial_out(up, UART_IER, up->ier);
383
384 /*
385 * And clear the interrupt registers again for luck.
386 */
387 (void) serial_in(up, UART_LSR);
388 (void) serial_in(up, UART_RX);
389 (void) serial_in(up, UART_IIR);
390 (void) serial_in(up, UART_MSR);
391
392 return 0;
393}
394
395static void serial_pxa_shutdown(struct uart_port *port)
396{
397 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
398 unsigned long flags;
399
400 free_irq(up->port.irq, up);
401
402 /*
403 * Disable interrupts from this port
404 */
405 up->ier = 0;
406 serial_out(up, UART_IER, 0);
407
408 spin_lock_irqsave(&up->port.lock, flags);
409 up->port.mctrl &= ~TIOCM_OUT2;
410 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
411 spin_unlock_irqrestore(&up->port.lock, flags);
412
413 /*
414 * Disable break condition and FIFOs
415 */
416 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
417 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
418 UART_FCR_CLEAR_RCVR |
419 UART_FCR_CLEAR_XMIT);
420 serial_out(up, UART_FCR, 0);
421}
422
423static void
424serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
425 struct ktermios *old)
426{
427 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
428 unsigned char cval, fcr = 0;
429 unsigned long flags;
430 unsigned int baud, quot;
431 unsigned int dll;
432
433 switch (termios->c_cflag & CSIZE) {
434 case CS5:
435 cval = UART_LCR_WLEN5;
436 break;
437 case CS6:
438 cval = UART_LCR_WLEN6;
439 break;
440 case CS7:
441 cval = UART_LCR_WLEN7;
442 break;
443 default:
444 case CS8:
445 cval = UART_LCR_WLEN8;
446 break;
447 }
448
449 if (termios->c_cflag & CSTOPB)
450 cval |= UART_LCR_STOP;
451 if (termios->c_cflag & PARENB)
452 cval |= UART_LCR_PARITY;
453 if (!(termios->c_cflag & PARODD))
454 cval |= UART_LCR_EPAR;
455
456 /*
457 * Ask the core to calculate the divisor for us.
458 */
459 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
460 quot = uart_get_divisor(port, baud);
461
462 if ((up->port.uartclk / quot) < (2400 * 16))
463 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
464 else if ((up->port.uartclk / quot) < (230400 * 16))
465 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
466 else
467 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
468
469 /*
470 * Ok, we're now changing the port state. Do it with
471 * interrupts disabled.
472 */
473 spin_lock_irqsave(&up->port.lock, flags);
474
475 /*
476 * Ensure the port will be enabled.
477 * This is required especially for serial console.
478 */
479 up->ier |= UART_IER_UUE;
480
481 /*
482 * Update the per-port timeout.
483 */
484 uart_update_timeout(port, termios->c_cflag, baud);
485
486 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
487 if (termios->c_iflag & INPCK)
488 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
489 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
490 up->port.read_status_mask |= UART_LSR_BI;
491
492 /*
493 * Characters to ignore
494 */
495 up->port.ignore_status_mask = 0;
496 if (termios->c_iflag & IGNPAR)
497 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
498 if (termios->c_iflag & IGNBRK) {
499 up->port.ignore_status_mask |= UART_LSR_BI;
500 /*
501 * If we're ignoring parity and break indicators,
502 * ignore overruns too (for real raw support).
503 */
504 if (termios->c_iflag & IGNPAR)
505 up->port.ignore_status_mask |= UART_LSR_OE;
506 }
507
508 /*
509 * ignore all characters if CREAD is not set
510 */
511 if ((termios->c_cflag & CREAD) == 0)
512 up->port.ignore_status_mask |= UART_LSR_DR;
513
514 /*
515 * CTS flow control flag and modem status interrupts
516 */
517 up->ier &= ~UART_IER_MSI;
518 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
519 up->ier |= UART_IER_MSI;
520
521 serial_out(up, UART_IER, up->ier);
522
523 if (termios->c_cflag & CRTSCTS)
524 up->mcr |= UART_MCR_AFE;
525 else
526 up->mcr &= ~UART_MCR_AFE;
527
528 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
529 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
530
531 /*
532 * work around Errata #75 according to Intel(R) PXA27x Processor Family
533 * Specification Update (Nov 2005)
534 */
535 dll = serial_in(up, UART_DLL);
536 WARN_ON(dll != (quot & 0xff));
537
538 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
539 serial_out(up, UART_LCR, cval); /* reset DLAB */
540 up->lcr = cval; /* Save LCR */
541 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
542 serial_out(up, UART_FCR, fcr);
543 spin_unlock_irqrestore(&up->port.lock, flags);
544}
545
546static void
547serial_pxa_pm(struct uart_port *port, unsigned int state,
548 unsigned int oldstate)
549{
550 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
551
552 if (!state)
553 clk_prepare_enable(up->clk);
554 else
555 clk_disable_unprepare(up->clk);
556}
557
558static void serial_pxa_release_port(struct uart_port *port)
559{
560}
561
562static int serial_pxa_request_port(struct uart_port *port)
563{
564 return 0;
565}
566
567static void serial_pxa_config_port(struct uart_port *port, int flags)
568{
569 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
570 up->port.type = PORT_PXA;
571}
572
573static int
574serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
575{
576 /* we don't want the core code to modify any port params */
577 return -EINVAL;
578}
579
580static const char *
581serial_pxa_type(struct uart_port *port)
582{
583 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
584 return up->name;
585}
586
587static struct uart_pxa_port *serial_pxa_ports[4];
588static struct uart_driver serial_pxa_reg;
589
590#ifdef CONFIG_SERIAL_PXA_CONSOLE
591
592#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
593
594/*
595 * Wait for transmitter & holding register to empty
596 */
597static void wait_for_xmitr(struct uart_pxa_port *up)
598{
599 unsigned int status, tmout = 10000;
600
601 /* Wait up to 10ms for the character(s) to be sent. */
602 do {
603 status = serial_in(up, UART_LSR);
604
605 if (status & UART_LSR_BI)
606 up->lsr_break_flag = UART_LSR_BI;
607
608 if (--tmout == 0)
609 break;
610 udelay(1);
611 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
612
613 /* Wait up to 1s for flow control if necessary */
614 if (up->port.flags & UPF_CONS_FLOW) {
615 tmout = 1000000;
616 while (--tmout &&
617 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
618 udelay(1);
619 }
620}
621
622static void serial_pxa_console_putchar(struct uart_port *port, int ch)
623{
624 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
625
626 wait_for_xmitr(up);
627 serial_out(up, UART_TX, ch);
628}
629
630/*
631 * Print a string to the serial port trying not to disturb
632 * any possible real use of the port...
633 *
634 * The console_lock must be held when we get here.
635 */
636static void
637serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
638{
639 struct uart_pxa_port *up = serial_pxa_ports[co->index];
640 unsigned int ier;
641 unsigned long flags;
642 int locked = 1;
643
644 clk_enable(up->clk);
645 local_irq_save(flags);
646 if (up->port.sysrq)
647 locked = 0;
648 else if (oops_in_progress)
649 locked = spin_trylock(&up->port.lock);
650 else
651 spin_lock(&up->port.lock);
652
653 /*
654 * First save the IER then disable the interrupts
655 */
656 ier = serial_in(up, UART_IER);
657 serial_out(up, UART_IER, UART_IER_UUE);
658
659 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
660
661 /*
662 * Finally, wait for transmitter to become empty
663 * and restore the IER
664 */
665 wait_for_xmitr(up);
666 serial_out(up, UART_IER, ier);
667
668 if (locked)
669 spin_unlock(&up->port.lock);
670 local_irq_restore(flags);
671 clk_disable(up->clk);
672
673}
674
675#ifdef CONFIG_CONSOLE_POLL
676/*
677 * Console polling routines for writing and reading from the uart while
678 * in an interrupt or debug context.
679 */
680
681static int serial_pxa_get_poll_char(struct uart_port *port)
682{
683 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
684 unsigned char lsr = serial_in(up, UART_LSR);
685
686 while (!(lsr & UART_LSR_DR))
687 lsr = serial_in(up, UART_LSR);
688
689 return serial_in(up, UART_RX);
690}
691
692
693static void serial_pxa_put_poll_char(struct uart_port *port,
694 unsigned char c)
695{
696 unsigned int ier;
697 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
698
699 /*
700 * First save the IER then disable the interrupts
701 */
702 ier = serial_in(up, UART_IER);
703 serial_out(up, UART_IER, UART_IER_UUE);
704
705 wait_for_xmitr(up);
706 /*
707 * Send the character out.
708 */
709 serial_out(up, UART_TX, c);
710
711 /*
712 * Finally, wait for transmitter to become empty
713 * and restore the IER
714 */
715 wait_for_xmitr(up);
716 serial_out(up, UART_IER, ier);
717}
718
719#endif /* CONFIG_CONSOLE_POLL */
720
721static int __init
722serial_pxa_console_setup(struct console *co, char *options)
723{
724 struct uart_pxa_port *up;
725 int baud = 9600;
726 int bits = 8;
727 int parity = 'n';
728 int flow = 'n';
729
730 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
731 co->index = 0;
732 up = serial_pxa_ports[co->index];
733 if (!up)
734 return -ENODEV;
735
736 if (options)
737 uart_parse_options(options, &baud, &parity, &bits, &flow);
738
739 return uart_set_options(&up->port, co, baud, parity, bits, flow);
740}
741
742static struct console serial_pxa_console = {
743 .name = "ttyS",
744 .write = serial_pxa_console_write,
745 .device = uart_console_device,
746 .setup = serial_pxa_console_setup,
747 .flags = CON_PRINTBUFFER,
748 .index = -1,
749 .data = &serial_pxa_reg,
750};
751
752#define PXA_CONSOLE &serial_pxa_console
753#else
754#define PXA_CONSOLE NULL
755#endif
756
757static const struct uart_ops serial_pxa_pops = {
758 .tx_empty = serial_pxa_tx_empty,
759 .set_mctrl = serial_pxa_set_mctrl,
760 .get_mctrl = serial_pxa_get_mctrl,
761 .stop_tx = serial_pxa_stop_tx,
762 .start_tx = serial_pxa_start_tx,
763 .stop_rx = serial_pxa_stop_rx,
764 .enable_ms = serial_pxa_enable_ms,
765 .break_ctl = serial_pxa_break_ctl,
766 .startup = serial_pxa_startup,
767 .shutdown = serial_pxa_shutdown,
768 .set_termios = serial_pxa_set_termios,
769 .pm = serial_pxa_pm,
770 .type = serial_pxa_type,
771 .release_port = serial_pxa_release_port,
772 .request_port = serial_pxa_request_port,
773 .config_port = serial_pxa_config_port,
774 .verify_port = serial_pxa_verify_port,
775#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
776 .poll_get_char = serial_pxa_get_poll_char,
777 .poll_put_char = serial_pxa_put_poll_char,
778#endif
779};
780
781static struct uart_driver serial_pxa_reg = {
782 .owner = THIS_MODULE,
783 .driver_name = "PXA serial",
784 .dev_name = "ttyS",
785 .major = TTY_MAJOR,
786 .minor = 64,
787 .nr = 4,
788 .cons = PXA_CONSOLE,
789};
790
791#ifdef CONFIG_PM
792static int serial_pxa_suspend(struct device *dev)
793{
794 struct uart_pxa_port *sport = dev_get_drvdata(dev);
795
796 if (sport)
797 uart_suspend_port(&serial_pxa_reg, &sport->port);
798
799 return 0;
800}
801
802static int serial_pxa_resume(struct device *dev)
803{
804 struct uart_pxa_port *sport = dev_get_drvdata(dev);
805
806 if (sport)
807 uart_resume_port(&serial_pxa_reg, &sport->port);
808
809 return 0;
810}
811
812static const struct dev_pm_ops serial_pxa_pm_ops = {
813 .suspend = serial_pxa_suspend,
814 .resume = serial_pxa_resume,
815};
816#endif
817
818static const struct of_device_id serial_pxa_dt_ids[] = {
819 { .compatible = "mrvl,pxa-uart", },
820 { .compatible = "mrvl,mmp-uart", },
821 {}
822};
823
824static int serial_pxa_probe_dt(struct platform_device *pdev,
825 struct uart_pxa_port *sport)
826{
827 struct device_node *np = pdev->dev.of_node;
828 int ret;
829
830 if (!np)
831 return 1;
832
833 ret = of_alias_get_id(np, "serial");
834 if (ret < 0) {
835 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
836 return ret;
837 }
838 sport->port.line = ret;
839 return 0;
840}
841
842static int serial_pxa_probe(struct platform_device *dev)
843{
844 struct uart_pxa_port *sport;
845 struct resource *mmres, *irqres;
846 int ret;
847
848 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
849 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
850 if (!mmres || !irqres)
851 return -ENODEV;
852
853 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
854 if (!sport)
855 return -ENOMEM;
856
857 sport->clk = clk_get(&dev->dev, NULL);
858 if (IS_ERR(sport->clk)) {
859 ret = PTR_ERR(sport->clk);
860 goto err_free;
861 }
862
863 ret = clk_prepare(sport->clk);
864 if (ret) {
865 clk_put(sport->clk);
866 goto err_free;
867 }
868
869 sport->port.type = PORT_PXA;
870 sport->port.iotype = UPIO_MEM;
871 sport->port.mapbase = mmres->start;
872 sport->port.irq = irqres->start;
873 sport->port.fifosize = 64;
874 sport->port.ops = &serial_pxa_pops;
875 sport->port.dev = &dev->dev;
876 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
877 sport->port.uartclk = clk_get_rate(sport->clk);
878 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE);
879
880 ret = serial_pxa_probe_dt(dev, sport);
881 if (ret > 0)
882 sport->port.line = dev->id;
883 else if (ret < 0)
884 goto err_clk;
885 if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
886 dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
887 ret = -EINVAL;
888 goto err_clk;
889 }
890 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
891
892 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
893 if (!sport->port.membase) {
894 ret = -ENOMEM;
895 goto err_clk;
896 }
897
898 serial_pxa_ports[sport->port.line] = sport;
899
900 uart_add_one_port(&serial_pxa_reg, &sport->port);
901 platform_set_drvdata(dev, sport);
902
903 return 0;
904
905 err_clk:
906 clk_unprepare(sport->clk);
907 clk_put(sport->clk);
908 err_free:
909 kfree(sport);
910 return ret;
911}
912
913static struct platform_driver serial_pxa_driver = {
914 .probe = serial_pxa_probe,
915
916 .driver = {
917 .name = "pxa2xx-uart",
918#ifdef CONFIG_PM
919 .pm = &serial_pxa_pm_ops,
920#endif
921 .suppress_bind_attrs = true,
922 .of_match_table = serial_pxa_dt_ids,
923 },
924};
925
926
927/* 8250 driver for PXA serial ports should be used */
928static int __init serial_pxa_init(void)
929{
930 int ret;
931
932 ret = uart_register_driver(&serial_pxa_reg);
933 if (ret != 0)
934 return ret;
935
936 ret = platform_driver_register(&serial_pxa_driver);
937 if (ret != 0)
938 uart_unregister_driver(&serial_pxa_reg);
939
940 return ret;
941}
942device_initcall(serial_pxa_init);