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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/omap.h>
12#include <dt-bindings/clock/omap5.h>
13
14/ {
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
21
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <0x0>;
44
45 operating-points = <
46 /* kHz uV */
47 1000000 1060000
48 1500000 1250000
49 >;
50
51 clocks = <&dpll_mpu_ck>;
52 clock-names = "cpu";
53
54 clock-latency = <300000>; /* From omap-cpufreq driver */
55
56 /* cooling options */
57 #cooling-cells = <2>; /* min followed by max */
58 };
59 cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a15";
62 reg = <0x1>;
63
64 operating-points = <
65 /* kHz uV */
66 1000000 1060000
67 1500000 1250000
68 >;
69
70 clocks = <&dpll_mpu_ck>;
71 clock-names = "cpu";
72
73 clock-latency = <300000>; /* From omap-cpufreq driver */
74
75 /* cooling options */
76 #cooling-cells = <2>; /* min followed by max */
77 };
78 };
79
80 thermal-zones {
81 #include "omap4-cpu-thermal.dtsi"
82 #include "omap5-gpu-thermal.dtsi"
83 #include "omap5-core-thermal.dtsi"
84 };
85
86 timer {
87 compatible = "arm,armv7-timer";
88 /* PPI secure/nonsecure IRQ */
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
93 interrupt-parent = <&gic>;
94 };
95
96 pmu {
97 compatible = "arm,cortex-a15-pmu";
98 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 gic: interrupt-controller@48211000 {
103 compatible = "arm,cortex-a15-gic";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0 0x48211000 0 0x1000>,
107 <0 0x48212000 0 0x2000>,
108 <0 0x48214000 0 0x2000>,
109 <0 0x48216000 0 0x2000>;
110 interrupt-parent = <&gic>;
111 };
112
113 wakeupgen: interrupt-controller@48281000 {
114 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 reg = <0 0x48281000 0 0x1000>;
118 interrupt-parent = <&gic>;
119 };
120
121 /*
122 * The soc node represents the soc top level view. It is used for IPs
123 * that are not memory mapped in the MPU view or for the MPU itself.
124 */
125 soc {
126 compatible = "ti,omap-infra";
127 mpu {
128 compatible = "ti,omap4-mpu";
129 ti,hwmods = "mpu";
130 sram = <&ocmcram>;
131 };
132 };
133
134 /*
135 * XXX: Use a flat representation of the OMAP3 interconnect.
136 * The real OMAP interconnect network is quite complex.
137 * Since it will not bring real advantage to represent that in DT for
138 * the moment, just use a fake OCP bus entry to represent the whole bus
139 * hierarchy.
140 */
141 ocp {
142 compatible = "ti,omap5-l3-noc", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 ranges = <0 0 0 0xc0000000>;
146 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
147 reg = <0 0x44000000 0 0x2000>,
148 <0 0x44800000 0 0x3000>,
149 <0 0x45000000 0 0x4000>;
150 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
152
153 l4_wkup: interconnect@4ae00000 {
154 };
155
156 l4_cfg: interconnect@4a000000 {
157 };
158
159 l4_per: interconnect@48000000 {
160 };
161
162 l4_abe: interconnect@40100000 {
163 };
164
165 ocmcram: ocmcram@40300000 {
166 compatible = "mmio-sram";
167 reg = <0x40300000 0x20000>; /* 128k */
168 };
169
170 gpmc: gpmc@50000000 {
171 compatible = "ti,omap4430-gpmc";
172 reg = <0x50000000 0x1000>;
173 #address-cells = <2>;
174 #size-cells = <1>;
175 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
176 dmas = <&sdma 4>;
177 dma-names = "rxtx";
178 gpmc,num-cs = <8>;
179 gpmc,num-waitpins = <4>;
180 ti,hwmods = "gpmc";
181 clocks = <&l3_iclk_div>;
182 clock-names = "fck";
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 gpio-controller;
186 #gpio-cells = <2>;
187 };
188
189 mmu_dsp: mmu@4a066000 {
190 compatible = "ti,omap4-iommu";
191 reg = <0x4a066000 0x100>;
192 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "mmu_dsp";
194 #iommu-cells = <0>;
195 };
196
197 mmu_ipu: mmu@55082000 {
198 compatible = "ti,omap4-iommu";
199 reg = <0x55082000 0x100>;
200 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
201 ti,hwmods = "mmu_ipu";
202 #iommu-cells = <0>;
203 ti,iommu-bus-err-back;
204 };
205
206 dmm@4e000000 {
207 compatible = "ti,omap5-dmm";
208 reg = <0x4e000000 0x800>;
209 interrupts = <0 113 0x4>;
210 ti,hwmods = "dmm";
211 };
212
213 emif1: emif@4c000000 {
214 compatible = "ti,emif-4d5";
215 ti,hwmods = "emif1";
216 ti,no-idle-on-init;
217 phy-type = <2>; /* DDR PHY type: Intelli PHY */
218 reg = <0x4c000000 0x400>;
219 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
220 hw-caps-read-idle-ctrl;
221 hw-caps-ll-interface;
222 hw-caps-temp-alert;
223 };
224
225 emif2: emif@4d000000 {
226 compatible = "ti,emif-4d5";
227 ti,hwmods = "emif2";
228 ti,no-idle-on-init;
229 phy-type = <2>; /* DDR PHY type: Intelli PHY */
230 reg = <0x4d000000 0x400>;
231 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
232 hw-caps-read-idle-ctrl;
233 hw-caps-ll-interface;
234 hw-caps-temp-alert;
235 };
236
237 bandgap: bandgap@4a0021e0 {
238 reg = <0x4a0021e0 0xc
239 0x4a00232c 0xc
240 0x4a002380 0x2c
241 0x4a0023C0 0x3c>;
242 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
243 compatible = "ti,omap5430-bandgap";
244
245 #thermal-sensor-cells = <1>;
246 };
247
248 /* OCP2SCP3 */
249 sata: sata@4a141100 {
250 compatible = "snps,dwc-ahci";
251 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
252 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
253 phys = <&sata_phy>;
254 phy-names = "sata-phy";
255 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
256 ti,hwmods = "sata";
257 ports-implemented = <0x1>;
258 };
259
260 target-module@56000000 {
261 compatible = "ti,sysc-omap4", "ti,sysc";
262 reg = <0x5600fe00 0x4>,
263 <0x5600fe10 0x4>;
264 reg-names = "rev", "sysc";
265 ti,sysc-midle = <SYSC_IDLE_FORCE>,
266 <SYSC_IDLE_NO>,
267 <SYSC_IDLE_SMART>;
268 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
269 <SYSC_IDLE_NO>,
270 <SYSC_IDLE_SMART>;
271 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
272 clock-names = "fck";
273 #address-cells = <1>;
274 #size-cells = <1>;
275 ranges = <0 0x56000000 0x2000000>;
276
277 /*
278 * Closed source PowerVR driver, no child device
279 * binding or driver in mainline
280 */
281 };
282
283 dss: dss@58000000 {
284 compatible = "ti,omap5-dss";
285 reg = <0x58000000 0x80>;
286 status = "disabled";
287 ti,hwmods = "dss_core";
288 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
289 clock-names = "fck";
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges;
293
294 dispc@58001000 {
295 compatible = "ti,omap5-dispc";
296 reg = <0x58001000 0x1000>;
297 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
298 ti,hwmods = "dss_dispc";
299 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
300 clock-names = "fck";
301 };
302
303 rfbi: encoder@58002000 {
304 compatible = "ti,omap5-rfbi";
305 reg = <0x58002000 0x100>;
306 status = "disabled";
307 ti,hwmods = "dss_rfbi";
308 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
309 clock-names = "fck", "ick";
310 };
311
312 dsi1: encoder@58004000 {
313 compatible = "ti,omap5-dsi";
314 reg = <0x58004000 0x200>,
315 <0x58004200 0x40>,
316 <0x58004300 0x40>;
317 reg-names = "proto", "phy", "pll";
318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
319 status = "disabled";
320 ti,hwmods = "dss_dsi1";
321 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
322 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
323 clock-names = "fck", "sys_clk";
324 };
325
326 dsi2: encoder@58005000 {
327 compatible = "ti,omap5-dsi";
328 reg = <0x58009000 0x200>,
329 <0x58009200 0x40>,
330 <0x58009300 0x40>;
331 reg-names = "proto", "phy", "pll";
332 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
333 status = "disabled";
334 ti,hwmods = "dss_dsi2";
335 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
336 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
337 clock-names = "fck", "sys_clk";
338 };
339
340 hdmi: encoder@58060000 {
341 compatible = "ti,omap5-hdmi";
342 reg = <0x58040000 0x200>,
343 <0x58040200 0x80>,
344 <0x58040300 0x80>,
345 <0x58060000 0x19000>;
346 reg-names = "wp", "pll", "phy", "core";
347 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
348 status = "disabled";
349 ti,hwmods = "dss_hdmi";
350 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
351 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
352 clock-names = "fck", "sys_clk";
353 dmas = <&sdma 76>;
354 dma-names = "audio_tx";
355 };
356 };
357
358 abb_mpu: regulator-abb-mpu {
359 compatible = "ti,abb-v2";
360 regulator-name = "abb_mpu";
361 #address-cells = <0>;
362 #size-cells = <0>;
363 clocks = <&sys_clkin>;
364 ti,settling-time = <50>;
365 ti,clock-cycles = <16>;
366
367 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
368 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
369 reg-names = "base-address", "int-address",
370 "efuse-address", "ldo-address";
371 ti,tranxdone-status-mask = <0x80>;
372 /* LDOVBBMPU_MUX_CTRL */
373 ti,ldovbb-override-mask = <0x400>;
374 /* LDOVBBMPU_VSET_OUT */
375 ti,ldovbb-vset-mask = <0x1F>;
376
377 /*
378 * NOTE: only FBB mode used but actual vset will
379 * determine final biasing
380 */
381 ti,abb_info = <
382 /*uV ABB efuse rbb_m fbb_m vset_m*/
383 1060000 0 0x0 0 0x02000000 0x01F00000
384 1250000 0 0x4 0 0x02000000 0x01F00000
385 >;
386 };
387
388 abb_mm: regulator-abb-mm {
389 compatible = "ti,abb-v2";
390 regulator-name = "abb_mm";
391 #address-cells = <0>;
392 #size-cells = <0>;
393 clocks = <&sys_clkin>;
394 ti,settling-time = <50>;
395 ti,clock-cycles = <16>;
396
397 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
398 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
399 reg-names = "base-address", "int-address",
400 "efuse-address", "ldo-address";
401 ti,tranxdone-status-mask = <0x80000000>;
402 /* LDOVBBMM_MUX_CTRL */
403 ti,ldovbb-override-mask = <0x400>;
404 /* LDOVBBMM_VSET_OUT */
405 ti,ldovbb-vset-mask = <0x1F>;
406
407 /*
408 * NOTE: only FBB mode used but actual vset will
409 * determine final biasing
410 */
411 ti,abb_info = <
412 /*uV ABB efuse rbb_m fbb_m vset_m*/
413 1025000 0 0x0 0 0x02000000 0x01F00000
414 1120000 0 0x4 0 0x02000000 0x01F00000
415 >;
416 };
417 };
418};
419
420&cpu_thermal {
421 polling-delay = <500>; /* milliseconds */
422 coefficients = <65 (-1791)>;
423};
424
425#include "omap5-l4.dtsi"
426#include "omap54xx-clocks.dtsi"
427
428&gpu_thermal {
429 coefficients = <117 (-2992)>;
430};
431
432&core_thermal {
433 coefficients = <0 2000>;
434};
435
436#include "omap5-l4-abe.dtsi"
437#include "omap54xx-clocks.dtsi"
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/pinctrl/omap.h>
13
14#include "skeleton.dtsi"
15
16/ {
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 compatible = "ti,omap5";
21 interrupt-parent = <&wakeupgen>;
22
23 aliases {
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a15";
44 reg = <0x0>;
45
46 operating-points = <
47 /* kHz uV */
48 1000000 1060000
49 1500000 1250000
50 >;
51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
61 };
62 cpu@1 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a15";
65 reg = <0x1>;
66 };
67 };
68
69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
75 timer {
76 compatible = "arm,armv7-timer";
77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
82 interrupt-parent = <&gic>;
83 };
84
85 pmu {
86 compatible = "arm,cortex-a15-pmu";
87 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91 gic: interrupt-controller@48211000 {
92 compatible = "arm,cortex-a15-gic";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 reg = <0x48211000 0x1000>,
96 <0x48212000 0x1000>,
97 <0x48214000 0x2000>,
98 <0x48216000 0x2000>;
99 interrupt-parent = <&gic>;
100 };
101
102 wakeupgen: interrupt-controller@48281000 {
103 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 reg = <0x48281000 0x1000>;
107 interrupt-parent = <&gic>;
108 };
109
110 /*
111 * The soc node represents the soc top level view. It is used for IPs
112 * that are not memory mapped in the MPU view or for the MPU itself.
113 */
114 soc {
115 compatible = "ti,omap-infra";
116 mpu {
117 compatible = "ti,omap4-mpu";
118 ti,hwmods = "mpu";
119 sram = <&ocmcram>;
120 };
121 };
122
123 /*
124 * XXX: Use a flat representation of the OMAP3 interconnect.
125 * The real OMAP interconnect network is quite complex.
126 * Since it will not bring real advantage to represent that in DT for
127 * the moment, just use a fake OCP bus entry to represent the whole bus
128 * hierarchy.
129 */
130 ocp {
131 compatible = "ti,omap5-l3-noc", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 ranges;
135 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
136 reg = <0x44000000 0x2000>,
137 <0x44800000 0x3000>,
138 <0x45000000 0x4000>;
139 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
141
142 l4_cfg: l4@4a000000 {
143 compatible = "ti,omap5-l4-cfg", "simple-bus";
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0x4a000000 0x22a000>;
147
148 scm_core: scm@2000 {
149 compatible = "ti,omap5-scm-core", "simple-bus";
150 reg = <0x2000 0x1000>;
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges = <0 0x2000 0x800>;
154
155 scm_conf: scm_conf@0 {
156 compatible = "syscon";
157 reg = <0x0 0x800>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 };
161 };
162
163 scm_padconf_core: scm@2800 {
164 compatible = "ti,omap5-scm-padconf-core",
165 "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0 0x2800 0x800>;
169
170 omap5_pmx_core: pinmux@40 {
171 compatible = "ti,omap5-padconf",
172 "pinctrl-single";
173 reg = <0x40 0x01b6>;
174 #address-cells = <1>;
175 #size-cells = <0>;
176 #interrupt-cells = <1>;
177 interrupt-controller;
178 pinctrl-single,register-width = <16>;
179 pinctrl-single,function-mask = <0x7fff>;
180 };
181
182 omap5_padconf_global: omap5_padconf_global@5a0 {
183 compatible = "syscon",
184 "simple-bus";
185 reg = <0x5a0 0xec>;
186 #address-cells = <1>;
187 #size-cells = <1>;
188 ranges = <0 0x5a0 0xec>;
189
190 pbias_regulator: pbias_regulator {
191 compatible = "ti,pbias-omap5", "ti,pbias-omap";
192 reg = <0x60 0x4>;
193 syscon = <&omap5_padconf_global>;
194 pbias_mmc_reg: pbias_mmc_omap5 {
195 regulator-name = "pbias_mmc_omap5";
196 regulator-min-microvolt = <1800000>;
197 regulator-max-microvolt = <3000000>;
198 };
199 };
200 };
201 };
202
203 cm_core_aon: cm_core_aon@4000 {
204 compatible = "ti,omap5-cm-core-aon";
205 reg = <0x4000 0x2000>;
206
207 cm_core_aon_clocks: clocks {
208 #address-cells = <1>;
209 #size-cells = <0>;
210 };
211
212 cm_core_aon_clockdomains: clockdomains {
213 };
214 };
215
216 cm_core: cm_core@8000 {
217 compatible = "ti,omap5-cm-core";
218 reg = <0x8000 0x3000>;
219
220 cm_core_clocks: clocks {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 };
224
225 cm_core_clockdomains: clockdomains {
226 };
227 };
228 };
229
230 l4_wkup: l4@4ae00000 {
231 compatible = "ti,omap5-l4-wkup", "simple-bus";
232 #address-cells = <1>;
233 #size-cells = <1>;
234 ranges = <0 0x4ae00000 0x2b000>;
235
236 counter32k: counter@4000 {
237 compatible = "ti,omap-counter32k";
238 reg = <0x4000 0x40>;
239 ti,hwmods = "counter_32k";
240 };
241
242 prm: prm@6000 {
243 compatible = "ti,omap5-prm";
244 reg = <0x6000 0x3000>;
245 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
246
247 prm_clocks: clocks {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 };
251
252 prm_clockdomains: clockdomains {
253 };
254 };
255
256 scrm: scrm@a000 {
257 compatible = "ti,omap5-scrm";
258 reg = <0xa000 0x2000>;
259
260 scrm_clocks: clocks {
261 #address-cells = <1>;
262 #size-cells = <0>;
263 };
264
265 scrm_clockdomains: clockdomains {
266 };
267 };
268
269 omap5_pmx_wkup: pinmux@c840 {
270 compatible = "ti,omap5-padconf",
271 "pinctrl-single";
272 reg = <0xc840 0x003c>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 #interrupt-cells = <1>;
276 interrupt-controller;
277 pinctrl-single,register-width = <16>;
278 pinctrl-single,function-mask = <0x7fff>;
279 };
280 };
281
282 ocmcram: ocmcram@40300000 {
283 compatible = "mmio-sram";
284 reg = <0x40300000 0x20000>; /* 128k */
285 };
286
287 sdma: dma-controller@4a056000 {
288 compatible = "ti,omap4430-sdma";
289 reg = <0x4a056000 0x1000>;
290 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
294 #dma-cells = <1>;
295 dma-channels = <32>;
296 dma-requests = <127>;
297 };
298
299 gpio1: gpio@4ae10000 {
300 compatible = "ti,omap4-gpio";
301 reg = <0x4ae10000 0x200>;
302 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
303 ti,hwmods = "gpio1";
304 ti,gpio-always-on;
305 gpio-controller;
306 #gpio-cells = <2>;
307 interrupt-controller;
308 #interrupt-cells = <2>;
309 };
310
311 gpio2: gpio@48055000 {
312 compatible = "ti,omap4-gpio";
313 reg = <0x48055000 0x200>;
314 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
315 ti,hwmods = "gpio2";
316 gpio-controller;
317 #gpio-cells = <2>;
318 interrupt-controller;
319 #interrupt-cells = <2>;
320 };
321
322 gpio3: gpio@48057000 {
323 compatible = "ti,omap4-gpio";
324 reg = <0x48057000 0x200>;
325 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
326 ti,hwmods = "gpio3";
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 };
332
333 gpio4: gpio@48059000 {
334 compatible = "ti,omap4-gpio";
335 reg = <0x48059000 0x200>;
336 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
337 ti,hwmods = "gpio4";
338 gpio-controller;
339 #gpio-cells = <2>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342 };
343
344 gpio5: gpio@4805b000 {
345 compatible = "ti,omap4-gpio";
346 reg = <0x4805b000 0x200>;
347 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
348 ti,hwmods = "gpio5";
349 gpio-controller;
350 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
353 };
354
355 gpio6: gpio@4805d000 {
356 compatible = "ti,omap4-gpio";
357 reg = <0x4805d000 0x200>;
358 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
359 ti,hwmods = "gpio6";
360 gpio-controller;
361 #gpio-cells = <2>;
362 interrupt-controller;
363 #interrupt-cells = <2>;
364 };
365
366 gpio7: gpio@48051000 {
367 compatible = "ti,omap4-gpio";
368 reg = <0x48051000 0x200>;
369 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
370 ti,hwmods = "gpio7";
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
374 #interrupt-cells = <2>;
375 };
376
377 gpio8: gpio@48053000 {
378 compatible = "ti,omap4-gpio";
379 reg = <0x48053000 0x200>;
380 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
381 ti,hwmods = "gpio8";
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 };
387
388 gpmc: gpmc@50000000 {
389 compatible = "ti,omap4430-gpmc";
390 reg = <0x50000000 0x1000>;
391 #address-cells = <2>;
392 #size-cells = <1>;
393 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
394 dmas = <&sdma 4>;
395 dma-names = "rxtx";
396 gpmc,num-cs = <8>;
397 gpmc,num-waitpins = <4>;
398 ti,hwmods = "gpmc";
399 clocks = <&l3_iclk_div>;
400 clock-names = "fck";
401 };
402
403 i2c1: i2c@48070000 {
404 compatible = "ti,omap4-i2c";
405 reg = <0x48070000 0x100>;
406 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 ti,hwmods = "i2c1";
410 };
411
412 i2c2: i2c@48072000 {
413 compatible = "ti,omap4-i2c";
414 reg = <0x48072000 0x100>;
415 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
416 #address-cells = <1>;
417 #size-cells = <0>;
418 ti,hwmods = "i2c2";
419 };
420
421 i2c3: i2c@48060000 {
422 compatible = "ti,omap4-i2c";
423 reg = <0x48060000 0x100>;
424 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
426 #size-cells = <0>;
427 ti,hwmods = "i2c3";
428 };
429
430 i2c4: i2c@4807a000 {
431 compatible = "ti,omap4-i2c";
432 reg = <0x4807a000 0x100>;
433 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
434 #address-cells = <1>;
435 #size-cells = <0>;
436 ti,hwmods = "i2c4";
437 };
438
439 i2c5: i2c@4807c000 {
440 compatible = "ti,omap4-i2c";
441 reg = <0x4807c000 0x100>;
442 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 ti,hwmods = "i2c5";
446 };
447
448 hwspinlock: spinlock@4a0f6000 {
449 compatible = "ti,omap4-hwspinlock";
450 reg = <0x4a0f6000 0x1000>;
451 ti,hwmods = "spinlock";
452 #hwlock-cells = <1>;
453 };
454
455 mcspi1: spi@48098000 {
456 compatible = "ti,omap4-mcspi";
457 reg = <0x48098000 0x200>;
458 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 ti,hwmods = "mcspi1";
462 ti,spi-num-cs = <4>;
463 dmas = <&sdma 35>,
464 <&sdma 36>,
465 <&sdma 37>,
466 <&sdma 38>,
467 <&sdma 39>,
468 <&sdma 40>,
469 <&sdma 41>,
470 <&sdma 42>;
471 dma-names = "tx0", "rx0", "tx1", "rx1",
472 "tx2", "rx2", "tx3", "rx3";
473 };
474
475 mcspi2: spi@4809a000 {
476 compatible = "ti,omap4-mcspi";
477 reg = <0x4809a000 0x200>;
478 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 ti,hwmods = "mcspi2";
482 ti,spi-num-cs = <2>;
483 dmas = <&sdma 43>,
484 <&sdma 44>,
485 <&sdma 45>,
486 <&sdma 46>;
487 dma-names = "tx0", "rx0", "tx1", "rx1";
488 };
489
490 mcspi3: spi@480b8000 {
491 compatible = "ti,omap4-mcspi";
492 reg = <0x480b8000 0x200>;
493 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
495 #size-cells = <0>;
496 ti,hwmods = "mcspi3";
497 ti,spi-num-cs = <2>;
498 dmas = <&sdma 15>, <&sdma 16>;
499 dma-names = "tx0", "rx0";
500 };
501
502 mcspi4: spi@480ba000 {
503 compatible = "ti,omap4-mcspi";
504 reg = <0x480ba000 0x200>;
505 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 ti,hwmods = "mcspi4";
509 ti,spi-num-cs = <1>;
510 dmas = <&sdma 70>, <&sdma 71>;
511 dma-names = "tx0", "rx0";
512 };
513
514 uart1: serial@4806a000 {
515 compatible = "ti,omap4-uart";
516 reg = <0x4806a000 0x100>;
517 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
518 ti,hwmods = "uart1";
519 clock-frequency = <48000000>;
520 };
521
522 uart2: serial@4806c000 {
523 compatible = "ti,omap4-uart";
524 reg = <0x4806c000 0x100>;
525 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
526 ti,hwmods = "uart2";
527 clock-frequency = <48000000>;
528 };
529
530 uart3: serial@48020000 {
531 compatible = "ti,omap4-uart";
532 reg = <0x48020000 0x100>;
533 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
534 ti,hwmods = "uart3";
535 clock-frequency = <48000000>;
536 };
537
538 uart4: serial@4806e000 {
539 compatible = "ti,omap4-uart";
540 reg = <0x4806e000 0x100>;
541 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
542 ti,hwmods = "uart4";
543 clock-frequency = <48000000>;
544 };
545
546 uart5: serial@48066000 {
547 compatible = "ti,omap4-uart";
548 reg = <0x48066000 0x100>;
549 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
550 ti,hwmods = "uart5";
551 clock-frequency = <48000000>;
552 };
553
554 uart6: serial@48068000 {
555 compatible = "ti,omap4-uart";
556 reg = <0x48068000 0x100>;
557 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
558 ti,hwmods = "uart6";
559 clock-frequency = <48000000>;
560 };
561
562 mmc1: mmc@4809c000 {
563 compatible = "ti,omap4-hsmmc";
564 reg = <0x4809c000 0x400>;
565 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
566 ti,hwmods = "mmc1";
567 ti,dual-volt;
568 ti,needs-special-reset;
569 dmas = <&sdma 61>, <&sdma 62>;
570 dma-names = "tx", "rx";
571 pbias-supply = <&pbias_mmc_reg>;
572 };
573
574 mmc2: mmc@480b4000 {
575 compatible = "ti,omap4-hsmmc";
576 reg = <0x480b4000 0x400>;
577 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
578 ti,hwmods = "mmc2";
579 ti,needs-special-reset;
580 dmas = <&sdma 47>, <&sdma 48>;
581 dma-names = "tx", "rx";
582 };
583
584 mmc3: mmc@480ad000 {
585 compatible = "ti,omap4-hsmmc";
586 reg = <0x480ad000 0x400>;
587 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
588 ti,hwmods = "mmc3";
589 ti,needs-special-reset;
590 dmas = <&sdma 77>, <&sdma 78>;
591 dma-names = "tx", "rx";
592 };
593
594 mmc4: mmc@480d1000 {
595 compatible = "ti,omap4-hsmmc";
596 reg = <0x480d1000 0x400>;
597 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
598 ti,hwmods = "mmc4";
599 ti,needs-special-reset;
600 dmas = <&sdma 57>, <&sdma 58>;
601 dma-names = "tx", "rx";
602 };
603
604 mmc5: mmc@480d5000 {
605 compatible = "ti,omap4-hsmmc";
606 reg = <0x480d5000 0x400>;
607 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
608 ti,hwmods = "mmc5";
609 ti,needs-special-reset;
610 dmas = <&sdma 59>, <&sdma 60>;
611 dma-names = "tx", "rx";
612 };
613
614 mmu_dsp: mmu@4a066000 {
615 compatible = "ti,omap4-iommu";
616 reg = <0x4a066000 0x100>;
617 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
618 ti,hwmods = "mmu_dsp";
619 #iommu-cells = <0>;
620 };
621
622 mmu_ipu: mmu@55082000 {
623 compatible = "ti,omap4-iommu";
624 reg = <0x55082000 0x100>;
625 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
626 ti,hwmods = "mmu_ipu";
627 #iommu-cells = <0>;
628 ti,iommu-bus-err-back;
629 };
630
631 keypad: keypad@4ae1c000 {
632 compatible = "ti,omap4-keypad";
633 reg = <0x4ae1c000 0x400>;
634 ti,hwmods = "kbd";
635 };
636
637 mcpdm: mcpdm@40132000 {
638 compatible = "ti,omap4-mcpdm";
639 reg = <0x40132000 0x7f>, /* MPU private access */
640 <0x49032000 0x7f>; /* L3 Interconnect */
641 reg-names = "mpu", "dma";
642 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
643 ti,hwmods = "mcpdm";
644 dmas = <&sdma 65>,
645 <&sdma 66>;
646 dma-names = "up_link", "dn_link";
647 status = "disabled";
648 };
649
650 dmic: dmic@4012e000 {
651 compatible = "ti,omap4-dmic";
652 reg = <0x4012e000 0x7f>, /* MPU private access */
653 <0x4902e000 0x7f>; /* L3 Interconnect */
654 reg-names = "mpu", "dma";
655 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
656 ti,hwmods = "dmic";
657 dmas = <&sdma 67>;
658 dma-names = "up_link";
659 status = "disabled";
660 };
661
662 mcbsp1: mcbsp@40122000 {
663 compatible = "ti,omap4-mcbsp";
664 reg = <0x40122000 0xff>, /* MPU private access */
665 <0x49022000 0xff>; /* L3 Interconnect */
666 reg-names = "mpu", "dma";
667 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
668 interrupt-names = "common";
669 ti,buffer-size = <128>;
670 ti,hwmods = "mcbsp1";
671 dmas = <&sdma 33>,
672 <&sdma 34>;
673 dma-names = "tx", "rx";
674 status = "disabled";
675 };
676
677 mcbsp2: mcbsp@40124000 {
678 compatible = "ti,omap4-mcbsp";
679 reg = <0x40124000 0xff>, /* MPU private access */
680 <0x49024000 0xff>; /* L3 Interconnect */
681 reg-names = "mpu", "dma";
682 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
683 interrupt-names = "common";
684 ti,buffer-size = <128>;
685 ti,hwmods = "mcbsp2";
686 dmas = <&sdma 17>,
687 <&sdma 18>;
688 dma-names = "tx", "rx";
689 status = "disabled";
690 };
691
692 mcbsp3: mcbsp@40126000 {
693 compatible = "ti,omap4-mcbsp";
694 reg = <0x40126000 0xff>, /* MPU private access */
695 <0x49026000 0xff>; /* L3 Interconnect */
696 reg-names = "mpu", "dma";
697 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
698 interrupt-names = "common";
699 ti,buffer-size = <128>;
700 ti,hwmods = "mcbsp3";
701 dmas = <&sdma 19>,
702 <&sdma 20>;
703 dma-names = "tx", "rx";
704 status = "disabled";
705 };
706
707 mailbox: mailbox@4a0f4000 {
708 compatible = "ti,omap4-mailbox";
709 reg = <0x4a0f4000 0x200>;
710 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
711 ti,hwmods = "mailbox";
712 #mbox-cells = <1>;
713 ti,mbox-num-users = <3>;
714 ti,mbox-num-fifos = <8>;
715 mbox_ipu: mbox_ipu {
716 ti,mbox-tx = <0 0 0>;
717 ti,mbox-rx = <1 0 0>;
718 };
719 mbox_dsp: mbox_dsp {
720 ti,mbox-tx = <3 0 0>;
721 ti,mbox-rx = <2 0 0>;
722 };
723 };
724
725 timer1: timer@4ae18000 {
726 compatible = "ti,omap5430-timer";
727 reg = <0x4ae18000 0x80>;
728 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
729 ti,hwmods = "timer1";
730 ti,timer-alwon;
731 };
732
733 timer2: timer@48032000 {
734 compatible = "ti,omap5430-timer";
735 reg = <0x48032000 0x80>;
736 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
737 ti,hwmods = "timer2";
738 };
739
740 timer3: timer@48034000 {
741 compatible = "ti,omap5430-timer";
742 reg = <0x48034000 0x80>;
743 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
744 ti,hwmods = "timer3";
745 };
746
747 timer4: timer@48036000 {
748 compatible = "ti,omap5430-timer";
749 reg = <0x48036000 0x80>;
750 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
751 ti,hwmods = "timer4";
752 };
753
754 timer5: timer@40138000 {
755 compatible = "ti,omap5430-timer";
756 reg = <0x40138000 0x80>,
757 <0x49038000 0x80>;
758 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
759 ti,hwmods = "timer5";
760 ti,timer-dsp;
761 ti,timer-pwm;
762 };
763
764 timer6: timer@4013a000 {
765 compatible = "ti,omap5430-timer";
766 reg = <0x4013a000 0x80>,
767 <0x4903a000 0x80>;
768 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
769 ti,hwmods = "timer6";
770 ti,timer-dsp;
771 ti,timer-pwm;
772 };
773
774 timer7: timer@4013c000 {
775 compatible = "ti,omap5430-timer";
776 reg = <0x4013c000 0x80>,
777 <0x4903c000 0x80>;
778 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
779 ti,hwmods = "timer7";
780 ti,timer-dsp;
781 };
782
783 timer8: timer@4013e000 {
784 compatible = "ti,omap5430-timer";
785 reg = <0x4013e000 0x80>,
786 <0x4903e000 0x80>;
787 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
788 ti,hwmods = "timer8";
789 ti,timer-dsp;
790 ti,timer-pwm;
791 };
792
793 timer9: timer@4803e000 {
794 compatible = "ti,omap5430-timer";
795 reg = <0x4803e000 0x80>;
796 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
797 ti,hwmods = "timer9";
798 ti,timer-pwm;
799 };
800
801 timer10: timer@48086000 {
802 compatible = "ti,omap5430-timer";
803 reg = <0x48086000 0x80>;
804 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
805 ti,hwmods = "timer10";
806 ti,timer-pwm;
807 };
808
809 timer11: timer@48088000 {
810 compatible = "ti,omap5430-timer";
811 reg = <0x48088000 0x80>;
812 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
813 ti,hwmods = "timer11";
814 ti,timer-pwm;
815 };
816
817 wdt2: wdt@4ae14000 {
818 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
819 reg = <0x4ae14000 0x80>;
820 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
821 ti,hwmods = "wd_timer2";
822 };
823
824 dmm@4e000000 {
825 compatible = "ti,omap5-dmm";
826 reg = <0x4e000000 0x800>;
827 interrupts = <0 113 0x4>;
828 ti,hwmods = "dmm";
829 };
830
831 emif1: emif@4c000000 {
832 compatible = "ti,emif-4d5";
833 ti,hwmods = "emif1";
834 ti,no-idle-on-init;
835 phy-type = <2>; /* DDR PHY type: Intelli PHY */
836 reg = <0x4c000000 0x400>;
837 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
838 hw-caps-read-idle-ctrl;
839 hw-caps-ll-interface;
840 hw-caps-temp-alert;
841 };
842
843 emif2: emif@4d000000 {
844 compatible = "ti,emif-4d5";
845 ti,hwmods = "emif2";
846 ti,no-idle-on-init;
847 phy-type = <2>; /* DDR PHY type: Intelli PHY */
848 reg = <0x4d000000 0x400>;
849 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
850 hw-caps-read-idle-ctrl;
851 hw-caps-ll-interface;
852 hw-caps-temp-alert;
853 };
854
855 usb3: omap_dwc3@4a020000 {
856 compatible = "ti,dwc3";
857 ti,hwmods = "usb_otg_ss";
858 reg = <0x4a020000 0x10000>;
859 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
860 #address-cells = <1>;
861 #size-cells = <1>;
862 utmi-mode = <2>;
863 ranges;
864 dwc3@4a030000 {
865 compatible = "snps,dwc3";
866 reg = <0x4a030000 0x10000>;
867 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
868 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
870 interrupt-names = "peripheral",
871 "host",
872 "otg";
873 phys = <&usb2_phy>, <&usb3_phy>;
874 phy-names = "usb2-phy", "usb3-phy";
875 dr_mode = "peripheral";
876 };
877 };
878
879 ocp2scp@4a080000 {
880 compatible = "ti,omap-ocp2scp";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 reg = <0x4a080000 0x20>;
884 ranges;
885 ti,hwmods = "ocp2scp1";
886 usb2_phy: usb2phy@4a084000 {
887 compatible = "ti,omap-usb2";
888 reg = <0x4a084000 0x7c>;
889 syscon-phy-power = <&scm_conf 0x300>;
890 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
891 clock-names = "wkupclk", "refclk";
892 #phy-cells = <0>;
893 };
894
895 usb3_phy: usb3phy@4a084400 {
896 compatible = "ti,omap-usb3";
897 reg = <0x4a084400 0x80>,
898 <0x4a084800 0x64>,
899 <0x4a084c00 0x40>;
900 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
901 syscon-phy-power = <&scm_conf 0x370>;
902 clocks = <&usb_phy_cm_clk32k>,
903 <&sys_clkin>,
904 <&usb_otg_ss_refclk960m>;
905 clock-names = "wkupclk",
906 "sysclk",
907 "refclk";
908 #phy-cells = <0>;
909 };
910 };
911
912 usbhstll: usbhstll@4a062000 {
913 compatible = "ti,usbhs-tll";
914 reg = <0x4a062000 0x1000>;
915 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
916 ti,hwmods = "usb_tll_hs";
917 };
918
919 usbhshost: usbhshost@4a064000 {
920 compatible = "ti,usbhs-host";
921 reg = <0x4a064000 0x800>;
922 ti,hwmods = "usb_host_hs";
923 #address-cells = <1>;
924 #size-cells = <1>;
925 ranges;
926 clocks = <&l3init_60m_fclk>,
927 <&xclk60mhsp1_ck>,
928 <&xclk60mhsp2_ck>;
929 clock-names = "refclk_60m_int",
930 "refclk_60m_ext_p1",
931 "refclk_60m_ext_p2";
932
933 usbhsohci: ohci@4a064800 {
934 compatible = "ti,ohci-omap3";
935 reg = <0x4a064800 0x400>;
936 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
937 };
938
939 usbhsehci: ehci@4a064c00 {
940 compatible = "ti,ehci-omap";
941 reg = <0x4a064c00 0x400>;
942 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
943 };
944 };
945
946 bandgap: bandgap@4a0021e0 {
947 reg = <0x4a0021e0 0xc
948 0x4a00232c 0xc
949 0x4a002380 0x2c
950 0x4a0023C0 0x3c>;
951 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
952 compatible = "ti,omap5430-bandgap";
953
954 #thermal-sensor-cells = <1>;
955 };
956
957 /* OCP2SCP3 */
958 ocp2scp@4a090000 {
959 compatible = "ti,omap-ocp2scp";
960 #address-cells = <1>;
961 #size-cells = <1>;
962 reg = <0x4a090000 0x20>;
963 ranges;
964 ti,hwmods = "ocp2scp3";
965 sata_phy: phy@4a096000 {
966 compatible = "ti,phy-pipe3-sata";
967 reg = <0x4A096000 0x80>, /* phy_rx */
968 <0x4A096400 0x64>, /* phy_tx */
969 <0x4A096800 0x40>; /* pll_ctrl */
970 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
971 syscon-phy-power = <&scm_conf 0x374>;
972 clocks = <&sys_clkin>, <&sata_ref_clk>;
973 clock-names = "sysclk", "refclk";
974 #phy-cells = <0>;
975 };
976 };
977
978 sata: sata@4a141100 {
979 compatible = "snps,dwc-ahci";
980 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
981 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
982 phys = <&sata_phy>;
983 phy-names = "sata-phy";
984 clocks = <&sata_ref_clk>;
985 ti,hwmods = "sata";
986 };
987
988 dss: dss@58000000 {
989 compatible = "ti,omap5-dss";
990 reg = <0x58000000 0x80>;
991 status = "disabled";
992 ti,hwmods = "dss_core";
993 clocks = <&dss_dss_clk>;
994 clock-names = "fck";
995 #address-cells = <1>;
996 #size-cells = <1>;
997 ranges;
998
999 dispc@58001000 {
1000 compatible = "ti,omap5-dispc";
1001 reg = <0x58001000 0x1000>;
1002 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1003 ti,hwmods = "dss_dispc";
1004 clocks = <&dss_dss_clk>;
1005 clock-names = "fck";
1006 };
1007
1008 rfbi: encoder@58002000 {
1009 compatible = "ti,omap5-rfbi";
1010 reg = <0x58002000 0x100>;
1011 status = "disabled";
1012 ti,hwmods = "dss_rfbi";
1013 clocks = <&dss_dss_clk>, <&l3_iclk_div>;
1014 clock-names = "fck", "ick";
1015 };
1016
1017 dsi1: encoder@58004000 {
1018 compatible = "ti,omap5-dsi";
1019 reg = <0x58004000 0x200>,
1020 <0x58004200 0x40>,
1021 <0x58004300 0x40>;
1022 reg-names = "proto", "phy", "pll";
1023 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1024 status = "disabled";
1025 ti,hwmods = "dss_dsi1";
1026 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1027 clock-names = "fck", "sys_clk";
1028 };
1029
1030 dsi2: encoder@58005000 {
1031 compatible = "ti,omap5-dsi";
1032 reg = <0x58009000 0x200>,
1033 <0x58009200 0x40>,
1034 <0x58009300 0x40>;
1035 reg-names = "proto", "phy", "pll";
1036 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1037 status = "disabled";
1038 ti,hwmods = "dss_dsi2";
1039 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
1040 clock-names = "fck", "sys_clk";
1041 };
1042
1043 hdmi: encoder@58060000 {
1044 compatible = "ti,omap5-hdmi";
1045 reg = <0x58040000 0x200>,
1046 <0x58040200 0x80>,
1047 <0x58040300 0x80>,
1048 <0x58060000 0x19000>;
1049 reg-names = "wp", "pll", "phy", "core";
1050 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1051 status = "disabled";
1052 ti,hwmods = "dss_hdmi";
1053 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
1054 clock-names = "fck", "sys_clk";
1055 dmas = <&sdma 76>;
1056 dma-names = "audio_tx";
1057 };
1058 };
1059
1060 abb_mpu: regulator-abb-mpu {
1061 compatible = "ti,abb-v2";
1062 regulator-name = "abb_mpu";
1063 #address-cells = <0>;
1064 #size-cells = <0>;
1065 clocks = <&sys_clkin>;
1066 ti,settling-time = <50>;
1067 ti,clock-cycles = <16>;
1068
1069 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1070 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1071 reg-names = "base-address", "int-address",
1072 "efuse-address", "ldo-address";
1073 ti,tranxdone-status-mask = <0x80>;
1074 /* LDOVBBMPU_MUX_CTRL */
1075 ti,ldovbb-override-mask = <0x400>;
1076 /* LDOVBBMPU_VSET_OUT */
1077 ti,ldovbb-vset-mask = <0x1F>;
1078
1079 /*
1080 * NOTE: only FBB mode used but actual vset will
1081 * determine final biasing
1082 */
1083 ti,abb_info = <
1084 /*uV ABB efuse rbb_m fbb_m vset_m*/
1085 1060000 0 0x0 0 0x02000000 0x01F00000
1086 1250000 0 0x4 0 0x02000000 0x01F00000
1087 >;
1088 };
1089
1090 abb_mm: regulator-abb-mm {
1091 compatible = "ti,abb-v2";
1092 regulator-name = "abb_mm";
1093 #address-cells = <0>;
1094 #size-cells = <0>;
1095 clocks = <&sys_clkin>;
1096 ti,settling-time = <50>;
1097 ti,clock-cycles = <16>;
1098
1099 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1100 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1101 reg-names = "base-address", "int-address",
1102 "efuse-address", "ldo-address";
1103 ti,tranxdone-status-mask = <0x80000000>;
1104 /* LDOVBBMM_MUX_CTRL */
1105 ti,ldovbb-override-mask = <0x400>;
1106 /* LDOVBBMM_VSET_OUT */
1107 ti,ldovbb-vset-mask = <0x1F>;
1108
1109 /*
1110 * NOTE: only FBB mode used but actual vset will
1111 * determine final biasing
1112 */
1113 ti,abb_info = <
1114 /*uV ABB efuse rbb_m fbb_m vset_m*/
1115 1025000 0 0x0 0 0x02000000 0x01F00000
1116 1120000 0 0x4 0 0x02000000 0x01F00000
1117 >;
1118 };
1119 };
1120};
1121
1122&cpu_thermal {
1123 polling-delay = <500>; /* milliseconds */
1124};
1125
1126/include/ "omap54xx-clocks.dtsi"