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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case TEST_J:
50 case TEST_K:
51 case TEST_SE0_NAK:
52 case TEST_PACKET:
53 case TEST_FORCE_EN:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (dwc->revision >= DWC3_REVISION_194A) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117
118 /*
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
121 */
122 if (dwc->revision >= DWC3_REVISION_194A)
123 return 0;
124
125 /* wait for a change in DSTS */
126 retries = 10000;
127 while (--retries) {
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129
130 if (DWC3_DSTS_USBLNKST(reg) == state)
131 return 0;
132
133 udelay(5);
134 }
135
136 return -ETIMEDOUT;
137}
138
139/**
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
142 *
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
146 */
147static void dwc3_ep_inc_trb(u8 *index)
148{
149 (*index)++;
150 if (*index == (DWC3_TRB_NUM - 1))
151 *index = 0;
152}
153
154/**
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
157 */
158static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
159{
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
161}
162
163/**
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
166 */
167static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
168{
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
170}
171
172static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
174{
175 struct dwc3 *dwc = dep->dwc;
176
177 list_del(&req->list);
178 req->remaining = 0;
179 req->needs_extra_trb = false;
180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
184 if (req->trb)
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
187
188 req->trb = NULL;
189 trace_dwc3_gadget_giveback(req);
190
191 if (dep->number > 1)
192 pm_runtime_put(dwc->dev);
193}
194
195/**
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
200 *
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
204 */
205void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
206 int status)
207{
208 struct dwc3 *dwc = dep->dwc;
209
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
211 req->status = DWC3_REQUEST_STATUS_COMPLETED;
212
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
216}
217
218/**
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
223 *
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
226 */
227int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
228{
229 u32 timeout = 500;
230 int status = 0;
231 int ret = 0;
232 u32 reg;
233
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
236
237 do {
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
241 if (status)
242 ret = -EINVAL;
243 break;
244 }
245 } while (--timeout);
246
247 if (!timeout) {
248 ret = -ETIMEDOUT;
249 status = -ETIMEDOUT;
250 }
251
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
253
254 return ret;
255}
256
257static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
258
259/**
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
264 *
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
267 */
268int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
270{
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
273 u32 timeout = 1000;
274 u32 saved_config = 0;
275 u32 reg;
276
277 int cmd_status = 0;
278 int ret = -EINVAL;
279
280 /*
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
283 * endpoint command.
284 *
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
287 *
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 */
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
295 }
296
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
300 }
301
302 if (saved_config)
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
304 }
305
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
307 int needs_wakeup;
308
309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 dwc->link_state == DWC3_LINK_STATE_U2 ||
311 dwc->link_state == DWC3_LINK_STATE_U3);
312
313 if (unlikely(needs_wakeup)) {
314 ret = __dwc3_gadget_wakeup(dwc);
315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
316 ret);
317 }
318 }
319
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
323
324 /*
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
328 * and CmdIOC bits.
329 *
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
332 *
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
338 */
339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 !usb_endpoint_xfer_isoc(desc))
341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 else
343 cmd |= DWC3_DEPCMD_CMDACT;
344
345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 do {
347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 cmd_status = DWC3_DEPCMD_STATUS(reg);
350
351 switch (cmd_status) {
352 case 0:
353 ret = 0;
354 break;
355 case DEPEVT_TRANSFER_NO_RESOURCE:
356 ret = -EINVAL;
357 break;
358 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 /*
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
365 *
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
369 */
370 ret = -EAGAIN;
371 break;
372 default:
373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
374 }
375
376 break;
377 }
378 } while (--timeout);
379
380 if (timeout == 0) {
381 ret = -ETIMEDOUT;
382 cmd_status = -ETIMEDOUT;
383 }
384
385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386
387 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
388 dep->flags |= DWC3_EP_TRANSFER_STARTED;
389 dwc3_gadget_ep_get_transfer_index(dep);
390 }
391
392 if (saved_config) {
393 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 reg |= saved_config;
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 }
397
398 return ret;
399}
400
401static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402{
403 struct dwc3 *dwc = dep->dwc;
404 struct dwc3_gadget_ep_cmd_params params;
405 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
406
407 /*
408 * As of core revision 2.60a the recommended programming model
409 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 * command for IN endpoints. This is to prevent an issue where
411 * some (non-compliant) hosts may not send ACK TPs for pending
412 * IN transfers due to a mishandled error condition. Synopsys
413 * STAR 9000614252.
414 */
415 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
416 (dwc->gadget.speed >= USB_SPEED_SUPER))
417 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418
419 memset(¶ms, 0, sizeof(params));
420
421 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
422}
423
424static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
425 struct dwc3_trb *trb)
426{
427 u32 offset = (char *) trb - (char *) dep->trb_pool;
428
429 return dep->trb_pool_dma + offset;
430}
431
432static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433{
434 struct dwc3 *dwc = dep->dwc;
435
436 if (dep->trb_pool)
437 return 0;
438
439 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
440 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
441 &dep->trb_pool_dma, GFP_KERNEL);
442 if (!dep->trb_pool) {
443 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
444 dep->name);
445 return -ENOMEM;
446 }
447
448 return 0;
449}
450
451static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452{
453 struct dwc3 *dwc = dep->dwc;
454
455 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 dep->trb_pool, dep->trb_pool_dma);
457
458 dep->trb_pool = NULL;
459 dep->trb_pool_dma = 0;
460}
461
462static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463{
464 struct dwc3_gadget_ep_cmd_params params;
465
466 memset(¶ms, 0x00, sizeof(params));
467
468 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469
470 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 ¶ms);
472}
473
474/**
475 * dwc3_gadget_start_config - configure ep resources
476 * @dep: endpoint that is being enabled
477 *
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
480 *
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
487 *
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
491 *
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
494 *
495 * The following simplified method is used instead:
496 *
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
502 *
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
506 */
507static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508{
509 struct dwc3_gadget_ep_cmd_params params;
510 struct dwc3 *dwc;
511 u32 cmd;
512 int i;
513 int ret;
514
515 if (dep->number)
516 return 0;
517
518 memset(¶ms, 0x00, sizeof(params));
519 cmd = DWC3_DEPCMD_DEPSTARTCFG;
520 dwc = dep->dwc;
521
522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
523 if (ret)
524 return ret;
525
526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 struct dwc3_ep *dep = dwc->eps[i];
528
529 if (!dep)
530 continue;
531
532 ret = dwc3_gadget_set_xfer_resource(dep);
533 if (ret)
534 return ret;
535 }
536
537 return 0;
538}
539
540static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541{
542 const struct usb_ss_ep_comp_descriptor *comp_desc;
543 const struct usb_endpoint_descriptor *desc;
544 struct dwc3_gadget_ep_cmd_params params;
545 struct dwc3 *dwc = dep->dwc;
546
547 comp_desc = dep->endpoint.comp_desc;
548 desc = dep->endpoint.desc;
549
550 memset(¶ms, 0x00, sizeof(params));
551
552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 u32 burst = dep->endpoint.maxburst;
558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
559 }
560
561 params.param0 |= action;
562 if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 params.param2 |= dep->saved_state;
564
565 if (usb_endpoint_xfer_control(desc))
566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567
568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570
571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN;
574 dep->stream_capable = true;
575 }
576
577 if (!usb_endpoint_xfer_control(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
579
580 /*
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
585 */
586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
587
588 /*
589 * We must use the lower 16 TX FIFOs even though
590 * HW might have more
591 */
592 if (dep->direction)
593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594
595 if (desc->bInterval) {
596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 dep->interval = 1 << (desc->bInterval - 1);
598 }
599
600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
601}
602
603/**
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
607 *
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
610 */
611static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
612{
613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 struct dwc3 *dwc = dep->dwc;
615
616 u32 reg;
617 int ret;
618
619 if (!(dep->flags & DWC3_EP_ENABLED)) {
620 ret = dwc3_gadget_start_config(dep);
621 if (ret)
622 return ret;
623 }
624
625 ret = dwc3_gadget_set_ep_config(dep, action);
626 if (ret)
627 return ret;
628
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 struct dwc3_trb *trb_st_hw;
631 struct dwc3_trb *trb_link;
632
633 dep->type = usb_endpoint_type(desc);
634 dep->flags |= DWC3_EP_ENABLED;
635
636 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
637 reg |= DWC3_DALEPENA_EP(dep->number);
638 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
639
640 if (usb_endpoint_xfer_control(desc))
641 goto out;
642
643 /* Initialize the TRB ring */
644 dep->trb_dequeue = 0;
645 dep->trb_enqueue = 0;
646 memset(dep->trb_pool, 0,
647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
648
649 /* Link TRB. The HWO bit is never reset */
650 trb_st_hw = &dep->trb_pool[0];
651
652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
657 }
658
659 /*
660 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 * Response Update Transfer command.
662 */
663 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
664 usb_endpoint_xfer_int(desc)) {
665 struct dwc3_gadget_ep_cmd_params params;
666 struct dwc3_trb *trb;
667 dma_addr_t trb_dma;
668 u32 cmd;
669
670 memset(¶ms, 0, sizeof(params));
671 trb = &dep->trb_pool[0];
672 trb_dma = dwc3_trb_dma_offset(dep, trb);
673
674 params.param0 = upper_32_bits(trb_dma);
675 params.param1 = lower_32_bits(trb_dma);
676
677 cmd = DWC3_DEPCMD_STARTTRANSFER;
678
679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
680 if (ret < 0)
681 return ret;
682 }
683
684out:
685 trace_dwc3_gadget_ep_enable(dep);
686
687 return 0;
688}
689
690static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
691 bool interrupt);
692static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
693{
694 struct dwc3_request *req;
695
696 dwc3_stop_active_transfer(dep, true, false);
697
698 /* - giveback all requests to gadget driver */
699 while (!list_empty(&dep->started_list)) {
700 req = next_request(&dep->started_list);
701
702 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
703 }
704
705 while (!list_empty(&dep->pending_list)) {
706 req = next_request(&dep->pending_list);
707
708 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 }
710
711 while (!list_empty(&dep->cancelled_list)) {
712 req = next_request(&dep->cancelled_list);
713
714 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 }
716}
717
718/**
719 * __dwc3_gadget_ep_disable - disables a hw endpoint
720 * @dep: the endpoint to disable
721 *
722 * This function undoes what __dwc3_gadget_ep_enable did and also removes
723 * requests which are currently being processed by the hardware and those which
724 * are not yet scheduled.
725 *
726 * Caller should take care of locking.
727 */
728static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
729{
730 struct dwc3 *dwc = dep->dwc;
731 u32 reg;
732
733 trace_dwc3_gadget_ep_disable(dep);
734
735 dwc3_remove_requests(dwc, dep);
736
737 /* make sure HW endpoint isn't stalled */
738 if (dep->flags & DWC3_EP_STALL)
739 __dwc3_gadget_ep_set_halt(dep, 0, false);
740
741 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
742 reg &= ~DWC3_DALEPENA_EP(dep->number);
743 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
744
745 dep->stream_capable = false;
746 dep->type = 0;
747 dep->flags = 0;
748
749 /* Clear out the ep descriptors for non-ep0 */
750 if (dep->number > 1) {
751 dep->endpoint.comp_desc = NULL;
752 dep->endpoint.desc = NULL;
753 }
754
755 return 0;
756}
757
758/* -------------------------------------------------------------------------- */
759
760static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
761 const struct usb_endpoint_descriptor *desc)
762{
763 return -EINVAL;
764}
765
766static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767{
768 return -EINVAL;
769}
770
771/* -------------------------------------------------------------------------- */
772
773static int dwc3_gadget_ep_enable(struct usb_ep *ep,
774 const struct usb_endpoint_descriptor *desc)
775{
776 struct dwc3_ep *dep;
777 struct dwc3 *dwc;
778 unsigned long flags;
779 int ret;
780
781 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
782 pr_debug("dwc3: invalid parameters\n");
783 return -EINVAL;
784 }
785
786 if (!desc->wMaxPacketSize) {
787 pr_debug("dwc3: missing wMaxPacketSize\n");
788 return -EINVAL;
789 }
790
791 dep = to_dwc3_ep(ep);
792 dwc = dep->dwc;
793
794 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
795 "%s is already enabled\n",
796 dep->name))
797 return 0;
798
799 spin_lock_irqsave(&dwc->lock, flags);
800 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
801 spin_unlock_irqrestore(&dwc->lock, flags);
802
803 return ret;
804}
805
806static int dwc3_gadget_ep_disable(struct usb_ep *ep)
807{
808 struct dwc3_ep *dep;
809 struct dwc3 *dwc;
810 unsigned long flags;
811 int ret;
812
813 if (!ep) {
814 pr_debug("dwc3: invalid parameters\n");
815 return -EINVAL;
816 }
817
818 dep = to_dwc3_ep(ep);
819 dwc = dep->dwc;
820
821 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
822 "%s is already disabled\n",
823 dep->name))
824 return 0;
825
826 spin_lock_irqsave(&dwc->lock, flags);
827 ret = __dwc3_gadget_ep_disable(dep);
828 spin_unlock_irqrestore(&dwc->lock, flags);
829
830 return ret;
831}
832
833static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 gfp_t gfp_flags)
835{
836 struct dwc3_request *req;
837 struct dwc3_ep *dep = to_dwc3_ep(ep);
838
839 req = kzalloc(sizeof(*req), gfp_flags);
840 if (!req)
841 return NULL;
842
843 req->direction = dep->direction;
844 req->epnum = dep->number;
845 req->dep = dep;
846 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
847
848 trace_dwc3_alloc_request(req);
849
850 return &req->request;
851}
852
853static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
854 struct usb_request *request)
855{
856 struct dwc3_request *req = to_dwc3_request(request);
857
858 trace_dwc3_free_request(req);
859 kfree(req);
860}
861
862/**
863 * dwc3_ep_prev_trb - returns the previous TRB in the ring
864 * @dep: The endpoint with the TRB ring
865 * @index: The index of the current TRB in the ring
866 *
867 * Returns the TRB prior to the one pointed to by the index. If the
868 * index is 0, we will wrap backwards, skip the link TRB, and return
869 * the one just before that.
870 */
871static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872{
873 u8 tmp = index;
874
875 if (!tmp)
876 tmp = DWC3_TRB_NUM - 1;
877
878 return &dep->trb_pool[tmp - 1];
879}
880
881static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
882{
883 struct dwc3_trb *tmp;
884 u8 trbs_left;
885
886 /*
887 * If enqueue & dequeue are equal than it is either full or empty.
888 *
889 * One way to know for sure is if the TRB right before us has HWO bit
890 * set or not. If it has, then we're definitely full and can't fit any
891 * more transfers in our ring.
892 */
893 if (dep->trb_enqueue == dep->trb_dequeue) {
894 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
895 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
896 return 0;
897
898 return DWC3_TRB_NUM - 1;
899 }
900
901 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
902 trbs_left &= (DWC3_TRB_NUM - 1);
903
904 if (dep->trb_dequeue < dep->trb_enqueue)
905 trbs_left--;
906
907 return trbs_left;
908}
909
910static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
911 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
912 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
913{
914 struct dwc3 *dwc = dep->dwc;
915 struct usb_gadget *gadget = &dwc->gadget;
916 enum usb_device_speed speed = gadget->speed;
917
918 trb->size = DWC3_TRB_SIZE_LENGTH(length);
919 trb->bpl = lower_32_bits(dma);
920 trb->bph = upper_32_bits(dma);
921
922 switch (usb_endpoint_type(dep->endpoint.desc)) {
923 case USB_ENDPOINT_XFER_CONTROL:
924 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 break;
926
927 case USB_ENDPOINT_XFER_ISOC:
928 if (!node) {
929 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930
931 /*
932 * USB Specification 2.0 Section 5.9.2 states that: "If
933 * there is only a single transaction in the microframe,
934 * only a DATA0 data packet PID is used. If there are
935 * two transactions per microframe, DATA1 is used for
936 * the first transaction data packet and DATA0 is used
937 * for the second transaction data packet. If there are
938 * three transactions per microframe, DATA2 is used for
939 * the first transaction data packet, DATA1 is used for
940 * the second, and DATA0 is used for the third."
941 *
942 * IOW, we should satisfy the following cases:
943 *
944 * 1) length <= maxpacket
945 * - DATA0
946 *
947 * 2) maxpacket < length <= (2 * maxpacket)
948 * - DATA1, DATA0
949 *
950 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
951 * - DATA2, DATA1, DATA0
952 */
953 if (speed == USB_SPEED_HIGH) {
954 struct usb_ep *ep = &dep->endpoint;
955 unsigned int mult = 2;
956 unsigned int maxp = usb_endpoint_maxp(ep->desc);
957
958 if (length <= (2 * maxp))
959 mult--;
960
961 if (length <= maxp)
962 mult--;
963
964 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 }
966 } else {
967 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 }
969
970 /* always enable Interrupt on Missed ISOC */
971 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 break;
973
974 case USB_ENDPOINT_XFER_BULK:
975 case USB_ENDPOINT_XFER_INT:
976 trb->ctrl = DWC3_TRBCTL_NORMAL;
977 break;
978 default:
979 /*
980 * This is only possible with faulty memory because we
981 * checked it already :)
982 */
983 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
984 usb_endpoint_type(dep->endpoint.desc));
985 }
986
987 /*
988 * Enable Continue on Short Packet
989 * when endpoint is not a stream capable
990 */
991 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
992 if (!dep->stream_capable)
993 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994
995 if (short_not_ok)
996 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 }
998
999 if ((!no_interrupt && !chain) ||
1000 (dwc3_calc_trbs_left(dep) == 1))
1001 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002
1003 if (chain)
1004 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1005
1006 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1007 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008
1009 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1010
1011 dwc3_ep_inc_enq(dep);
1012
1013 trace_dwc3_prepare_trb(dep, trb);
1014}
1015
1016/**
1017 * dwc3_prepare_one_trb - setup one TRB from one request
1018 * @dep: endpoint for which this request is prepared
1019 * @req: dwc3_request pointer
1020 * @chain: should this TRB be chained to the next?
1021 * @node: only for isochronous endpoints. First TRB needs different type.
1022 */
1023static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 struct dwc3_request *req, unsigned chain, unsigned node)
1025{
1026 struct dwc3_trb *trb;
1027 unsigned int length;
1028 dma_addr_t dma;
1029 unsigned stream_id = req->request.stream_id;
1030 unsigned short_not_ok = req->request.short_not_ok;
1031 unsigned no_interrupt = req->request.no_interrupt;
1032
1033 if (req->request.num_sgs > 0) {
1034 length = sg_dma_len(req->start_sg);
1035 dma = sg_dma_address(req->start_sg);
1036 } else {
1037 length = req->request.length;
1038 dma = req->request.dma;
1039 }
1040
1041 trb = &dep->trb_pool[dep->trb_enqueue];
1042
1043 if (!req->trb) {
1044 dwc3_gadget_move_started_request(req);
1045 req->trb = trb;
1046 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047 }
1048
1049 req->num_trbs++;
1050
1051 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 stream_id, short_not_ok, no_interrupt);
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->start_sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 unsigned int remaining = req->request.num_mapped_sgs
1063 - req->num_queued_sgs;
1064
1065 for_each_sg(sg, s, remaining, i) {
1066 unsigned int length = req->request.length;
1067 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 unsigned int rem = length % maxp;
1069 unsigned chain = true;
1070
1071 if (sg_is_last(s))
1072 chain = false;
1073
1074 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 struct dwc3 *dwc = dep->dwc;
1076 struct dwc3_trb *trb;
1077
1078 req->needs_extra_trb = true;
1079
1080 /* prepare normal TRB */
1081 dwc3_prepare_one_trb(dep, req, true, i);
1082
1083 /* Now prepare one extra TRB to align transfer size */
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1085 req->num_trbs++;
1086 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 maxp - rem, false, 1,
1088 req->request.stream_id,
1089 req->request.short_not_ok,
1090 req->request.no_interrupt);
1091 } else {
1092 dwc3_prepare_one_trb(dep, req, chain, i);
1093 }
1094
1095 /*
1096 * There can be a situation where all sgs in sglist are not
1097 * queued because of insufficient trb number. To handle this
1098 * case, update start_sg to next sg to be queued, so that
1099 * we have free trbs we can continue queuing from where we
1100 * previously stopped
1101 */
1102 if (chain)
1103 req->start_sg = sg_next(s);
1104
1105 req->num_queued_sgs++;
1106
1107 if (!dwc3_calc_trbs_left(dep))
1108 break;
1109 }
1110}
1111
1112static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 struct dwc3_request *req)
1114{
1115 unsigned int length = req->request.length;
1116 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 unsigned int rem = length % maxp;
1118
1119 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->needs_extra_trb = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 req->num_trbs++;
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 false, 1, req->request.stream_id,
1133 req->request.short_not_ok,
1134 req->request.no_interrupt);
1135 } else if (req->request.zero && req->request.length &&
1136 (IS_ALIGNED(req->request.length, maxp))) {
1137 struct dwc3 *dwc = dep->dwc;
1138 struct dwc3_trb *trb;
1139
1140 req->needs_extra_trb = true;
1141
1142 /* prepare normal TRB */
1143 dwc3_prepare_one_trb(dep, req, true, 0);
1144
1145 /* Now prepare one extra TRB to handle ZLP */
1146 trb = &dep->trb_pool[dep->trb_enqueue];
1147 req->num_trbs++;
1148 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 false, 1, req->request.stream_id,
1150 req->request.short_not_ok,
1151 req->request.no_interrupt);
1152 } else {
1153 dwc3_prepare_one_trb(dep, req, false, 0);
1154 }
1155}
1156
1157/*
1158 * dwc3_prepare_trbs - setup TRBs from requests
1159 * @dep: endpoint for which requests are being prepared
1160 *
1161 * The function goes through the requests list and sets up TRBs for the
1162 * transfers. The function returns once there are no more TRBs available or
1163 * it runs out of requests.
1164 */
1165static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1166{
1167 struct dwc3_request *req, *n;
1168
1169 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1170
1171 /*
1172 * We can get in a situation where there's a request in the started list
1173 * but there weren't enough TRBs to fully kick it in the first time
1174 * around, so it has been waiting for more TRBs to be freed up.
1175 *
1176 * In that case, we should check if we have a request with pending_sgs
1177 * in the started list and prepare TRBs for that request first,
1178 * otherwise we will prepare TRBs completely out of order and that will
1179 * break things.
1180 */
1181 list_for_each_entry(req, &dep->started_list, list) {
1182 if (req->num_pending_sgs > 0)
1183 dwc3_prepare_one_trb_sg(dep, req);
1184
1185 if (!dwc3_calc_trbs_left(dep))
1186 return;
1187 }
1188
1189 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 struct dwc3 *dwc = dep->dwc;
1191 int ret;
1192
1193 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1194 dep->direction);
1195 if (ret)
1196 return;
1197
1198 req->sg = req->request.sg;
1199 req->start_sg = req->sg;
1200 req->num_queued_sgs = 0;
1201 req->num_pending_sgs = req->request.num_mapped_sgs;
1202
1203 if (req->num_pending_sgs > 0)
1204 dwc3_prepare_one_trb_sg(dep, req);
1205 else
1206 dwc3_prepare_one_trb_linear(dep, req);
1207
1208 if (!dwc3_calc_trbs_left(dep))
1209 return;
1210 }
1211}
1212
1213static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1214{
1215 struct dwc3_gadget_ep_cmd_params params;
1216 struct dwc3_request *req;
1217 int starting;
1218 int ret;
1219 u32 cmd;
1220
1221 if (!dwc3_calc_trbs_left(dep))
1222 return 0;
1223
1224 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1225
1226 dwc3_prepare_trbs(dep);
1227 req = next_request(&dep->started_list);
1228 if (!req) {
1229 dep->flags |= DWC3_EP_PENDING_REQUEST;
1230 return 0;
1231 }
1232
1233 memset(¶ms, 0, sizeof(params));
1234
1235 if (starting) {
1236 params.param0 = upper_32_bits(req->trb_dma);
1237 params.param1 = lower_32_bits(req->trb_dma);
1238 cmd = DWC3_DEPCMD_STARTTRANSFER;
1239
1240 if (dep->stream_capable)
1241 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1242
1243 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1244 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1245 } else {
1246 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1247 DWC3_DEPCMD_PARAM(dep->resource_index);
1248 }
1249
1250 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1251 if (ret < 0) {
1252 /*
1253 * FIXME we need to iterate over the list of requests
1254 * here and stop, unmap, free and del each of the linked
1255 * requests instead of what we do now.
1256 */
1257 if (req->trb)
1258 memset(req->trb, 0, sizeof(struct dwc3_trb));
1259 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1260 return ret;
1261 }
1262
1263 return 0;
1264}
1265
1266static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267{
1268 u32 reg;
1269
1270 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1271 return DWC3_DSTS_SOFFN(reg);
1272}
1273
1274/**
1275 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1276 * @dep: isoc endpoint
1277 *
1278 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1279 * microframe number reported by the XferNotReady event for the future frame
1280 * number to start the isoc transfer.
1281 *
1282 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1283 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1284 * XferNotReady event are invalid. The driver uses this number to schedule the
1285 * isochronous transfer and passes it to the START TRANSFER command. Because
1286 * this number is invalid, the command may fail. If BIT[15:14] matches the
1287 * internal 16-bit microframe, the START TRANSFER command will pass and the
1288 * transfer will start at the scheduled time, if it is off by 1, the command
1289 * will still pass, but the transfer will start 2 seconds in the future. For all
1290 * other conditions, the START TRANSFER command will fail with bus-expiry.
1291 *
1292 * In order to workaround this issue, we can test for the correct combination of
1293 * BIT[15:14] by sending START TRANSFER commands with different values of
1294 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1295 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1296 * As the result, within the 4 possible combinations for BIT[15:14], there will
1297 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1298 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1299 * value is the correct combination.
1300 *
1301 * Since there are only 4 outcomes and the results are ordered, we can simply
1302 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1303 * deduce the smaller successful combination.
1304 *
1305 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1306 * of BIT[15:14]. The correct combination is as follow:
1307 *
1308 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1309 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1310 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1311 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1312 *
1313 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1314 * endpoints.
1315 */
1316static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1317{
1318 int cmd_status = 0;
1319 bool test0;
1320 bool test1;
1321
1322 while (dep->combo_num < 2) {
1323 struct dwc3_gadget_ep_cmd_params params;
1324 u32 test_frame_number;
1325 u32 cmd;
1326
1327 /*
1328 * Check if we can start isoc transfer on the next interval or
1329 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1330 */
1331 test_frame_number = dep->frame_number & 0x3fff;
1332 test_frame_number |= dep->combo_num << 14;
1333 test_frame_number += max_t(u32, 4, dep->interval);
1334
1335 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1336 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1337
1338 cmd = DWC3_DEPCMD_STARTTRANSFER;
1339 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1340 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1341
1342 /* Redo if some other failure beside bus-expiry is received */
1343 if (cmd_status && cmd_status != -EAGAIN) {
1344 dep->start_cmd_status = 0;
1345 dep->combo_num = 0;
1346 return 0;
1347 }
1348
1349 /* Store the first test status */
1350 if (dep->combo_num == 0)
1351 dep->start_cmd_status = cmd_status;
1352
1353 dep->combo_num++;
1354
1355 /*
1356 * End the transfer if the START_TRANSFER command is successful
1357 * to wait for the next XferNotReady to test the command again
1358 */
1359 if (cmd_status == 0) {
1360 dwc3_stop_active_transfer(dep, true, true);
1361 return 0;
1362 }
1363 }
1364
1365 /* test0 and test1 are both completed at this point */
1366 test0 = (dep->start_cmd_status == 0);
1367 test1 = (cmd_status == 0);
1368
1369 if (!test0 && test1)
1370 dep->combo_num = 1;
1371 else if (!test0 && !test1)
1372 dep->combo_num = 2;
1373 else if (test0 && !test1)
1374 dep->combo_num = 3;
1375 else if (test0 && test1)
1376 dep->combo_num = 0;
1377
1378 dep->frame_number &= 0x3fff;
1379 dep->frame_number |= dep->combo_num << 14;
1380 dep->frame_number += max_t(u32, 4, dep->interval);
1381
1382 /* Reinitialize test variables */
1383 dep->start_cmd_status = 0;
1384 dep->combo_num = 0;
1385
1386 return __dwc3_gadget_kick_transfer(dep);
1387}
1388
1389static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1390{
1391 struct dwc3 *dwc = dep->dwc;
1392 int ret;
1393 int i;
1394
1395 if (list_empty(&dep->pending_list)) {
1396 dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 return -EAGAIN;
1398 }
1399
1400 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1401 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1402 (dwc->revision == DWC3_USB31_REVISION_170A &&
1403 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1404 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1405
1406 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1407 return dwc3_gadget_start_isoc_quirk(dep);
1408 }
1409
1410 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1411 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1412
1413 ret = __dwc3_gadget_kick_transfer(dep);
1414 if (ret != -EAGAIN)
1415 break;
1416 }
1417
1418 return ret;
1419}
1420
1421static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1422{
1423 struct dwc3 *dwc = dep->dwc;
1424
1425 if (!dep->endpoint.desc) {
1426 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1427 dep->name);
1428 return -ESHUTDOWN;
1429 }
1430
1431 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1432 &req->request, req->dep->name))
1433 return -EINVAL;
1434
1435 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1436 "%s: request %pK already in flight\n",
1437 dep->name, &req->request))
1438 return -EINVAL;
1439
1440 pm_runtime_get(dwc->dev);
1441
1442 req->request.actual = 0;
1443 req->request.status = -EINPROGRESS;
1444
1445 trace_dwc3_ep_queue(req);
1446
1447 list_add_tail(&req->list, &dep->pending_list);
1448 req->status = DWC3_REQUEST_STATUS_QUEUED;
1449
1450 /*
1451 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 * wait for a XferNotReady event so we will know what's the current
1453 * (micro-)frame number.
1454 *
1455 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 * errors which will force us issue EndTransfer command.
1457 */
1458 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1461 return 0;
1462
1463 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 return __dwc3_gadget_start_isoc(dep);
1466 }
1467 }
1468 }
1469
1470 return __dwc3_gadget_kick_transfer(dep);
1471}
1472
1473static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1474 gfp_t gfp_flags)
1475{
1476 struct dwc3_request *req = to_dwc3_request(request);
1477 struct dwc3_ep *dep = to_dwc3_ep(ep);
1478 struct dwc3 *dwc = dep->dwc;
1479
1480 unsigned long flags;
1481
1482 int ret;
1483
1484 spin_lock_irqsave(&dwc->lock, flags);
1485 ret = __dwc3_gadget_ep_queue(dep, req);
1486 spin_unlock_irqrestore(&dwc->lock, flags);
1487
1488 return ret;
1489}
1490
1491static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492{
1493 int i;
1494
1495 /*
1496 * If request was already started, this means we had to
1497 * stop the transfer. With that we also need to ignore
1498 * all TRBs used by the request, however TRBs can only
1499 * be modified after completion of END_TRANSFER
1500 * command. So what we do here is that we wait for
1501 * END_TRANSFER completion and only after that, we jump
1502 * over TRBs by clearing HWO and incrementing dequeue
1503 * pointer.
1504 */
1505 for (i = 0; i < req->num_trbs; i++) {
1506 struct dwc3_trb *trb;
1507
1508 trb = req->trb + i;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1511 }
1512
1513 req->num_trbs = 0;
1514}
1515
1516static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1517{
1518 struct dwc3_request *req;
1519 struct dwc3_request *tmp;
1520
1521 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1522 dwc3_gadget_ep_skip_trbs(dep, req);
1523 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1524 }
1525}
1526
1527static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1528 struct usb_request *request)
1529{
1530 struct dwc3_request *req = to_dwc3_request(request);
1531 struct dwc3_request *r = NULL;
1532
1533 struct dwc3_ep *dep = to_dwc3_ep(ep);
1534 struct dwc3 *dwc = dep->dwc;
1535
1536 unsigned long flags;
1537 int ret = 0;
1538
1539 trace_dwc3_ep_dequeue(req);
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542
1543 list_for_each_entry(r, &dep->pending_list, list) {
1544 if (r == req)
1545 break;
1546 }
1547
1548 if (r != req) {
1549 list_for_each_entry(r, &dep->started_list, list) {
1550 if (r == req)
1551 break;
1552 }
1553 if (r == req) {
1554 /* wait until it is processed */
1555 dwc3_stop_active_transfer(dep, true, true);
1556
1557 if (!r->trb)
1558 goto out0;
1559
1560 dwc3_gadget_move_cancelled_request(req);
1561 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1562 goto out0;
1563 else
1564 goto out1;
1565 }
1566 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 request, ep->name);
1568 ret = -EINVAL;
1569 goto out0;
1570 }
1571
1572out1:
1573 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1574
1575out0:
1576 spin_unlock_irqrestore(&dwc->lock, flags);
1577
1578 return ret;
1579}
1580
1581int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1582{
1583 struct dwc3_gadget_ep_cmd_params params;
1584 struct dwc3 *dwc = dep->dwc;
1585 int ret;
1586
1587 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1588 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1589 return -EINVAL;
1590 }
1591
1592 memset(¶ms, 0x00, sizeof(params));
1593
1594 if (value) {
1595 struct dwc3_trb *trb;
1596
1597 unsigned transfer_in_flight;
1598 unsigned started;
1599
1600 if (dep->number > 1)
1601 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1602 else
1603 trb = &dwc->ep0_trb[dep->trb_enqueue];
1604
1605 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1606 started = !list_empty(&dep->started_list);
1607
1608 if (!protocol && ((dep->direction && transfer_in_flight) ||
1609 (!dep->direction && started))) {
1610 return -EAGAIN;
1611 }
1612
1613 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1614 ¶ms);
1615 if (ret)
1616 dev_err(dwc->dev, "failed to set STALL on %s\n",
1617 dep->name);
1618 else
1619 dep->flags |= DWC3_EP_STALL;
1620 } else {
1621
1622 ret = dwc3_send_clear_stall_ep_cmd(dep);
1623 if (ret)
1624 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1625 dep->name);
1626 else
1627 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1628 }
1629
1630 return ret;
1631}
1632
1633static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1634{
1635 struct dwc3_ep *dep = to_dwc3_ep(ep);
1636 struct dwc3 *dwc = dep->dwc;
1637
1638 unsigned long flags;
1639
1640 int ret;
1641
1642 spin_lock_irqsave(&dwc->lock, flags);
1643 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1644 spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1650{
1651 struct dwc3_ep *dep = to_dwc3_ep(ep);
1652 struct dwc3 *dwc = dep->dwc;
1653 unsigned long flags;
1654 int ret;
1655
1656 spin_lock_irqsave(&dwc->lock, flags);
1657 dep->flags |= DWC3_EP_WEDGE;
1658
1659 if (dep->number == 0 || dep->number == 1)
1660 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1661 else
1662 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1663 spin_unlock_irqrestore(&dwc->lock, flags);
1664
1665 return ret;
1666}
1667
1668/* -------------------------------------------------------------------------- */
1669
1670static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1671 .bLength = USB_DT_ENDPOINT_SIZE,
1672 .bDescriptorType = USB_DT_ENDPOINT,
1673 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1674};
1675
1676static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1677 .enable = dwc3_gadget_ep0_enable,
1678 .disable = dwc3_gadget_ep0_disable,
1679 .alloc_request = dwc3_gadget_ep_alloc_request,
1680 .free_request = dwc3_gadget_ep_free_request,
1681 .queue = dwc3_gadget_ep0_queue,
1682 .dequeue = dwc3_gadget_ep_dequeue,
1683 .set_halt = dwc3_gadget_ep0_set_halt,
1684 .set_wedge = dwc3_gadget_ep_set_wedge,
1685};
1686
1687static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1688 .enable = dwc3_gadget_ep_enable,
1689 .disable = dwc3_gadget_ep_disable,
1690 .alloc_request = dwc3_gadget_ep_alloc_request,
1691 .free_request = dwc3_gadget_ep_free_request,
1692 .queue = dwc3_gadget_ep_queue,
1693 .dequeue = dwc3_gadget_ep_dequeue,
1694 .set_halt = dwc3_gadget_ep_set_halt,
1695 .set_wedge = dwc3_gadget_ep_set_wedge,
1696};
1697
1698/* -------------------------------------------------------------------------- */
1699
1700static int dwc3_gadget_get_frame(struct usb_gadget *g)
1701{
1702 struct dwc3 *dwc = gadget_to_dwc(g);
1703
1704 return __dwc3_gadget_get_frame(dwc);
1705}
1706
1707static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708{
1709 int retries;
1710
1711 int ret;
1712 u32 reg;
1713
1714 u8 link_state;
1715 u8 speed;
1716
1717 /*
1718 * According to the Databook Remote wakeup request should
1719 * be issued only when the device is in early suspend state.
1720 *
1721 * We can check that via USB Link State bits in DSTS register.
1722 */
1723 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724
1725 speed = reg & DWC3_DSTS_CONNECTSPD;
1726 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1727 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1728 return 0;
1729
1730 link_state = DWC3_DSTS_USBLNKST(reg);
1731
1732 switch (link_state) {
1733 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1734 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
1740 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1741 if (ret < 0) {
1742 dev_err(dwc->dev, "failed to put link in Recovery\n");
1743 return ret;
1744 }
1745
1746 /* Recent versions do this automatically */
1747 if (dwc->revision < DWC3_REVISION_194A) {
1748 /* write zeroes to Link Change Request */
1749 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1751 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1752 }
1753
1754 /* poll until Link State changes to ON */
1755 retries = 20000;
1756
1757 while (retries--) {
1758 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1759
1760 /* in HS, means ON */
1761 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1762 break;
1763 }
1764
1765 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1766 dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773static int dwc3_gadget_wakeup(struct usb_gadget *g)
1774{
1775 struct dwc3 *dwc = gadget_to_dwc(g);
1776 unsigned long flags;
1777 int ret;
1778
1779 spin_lock_irqsave(&dwc->lock, flags);
1780 ret = __dwc3_gadget_wakeup(dwc);
1781 spin_unlock_irqrestore(&dwc->lock, flags);
1782
1783 return ret;
1784}
1785
1786static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1787 int is_selfpowered)
1788{
1789 struct dwc3 *dwc = gadget_to_dwc(g);
1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dwc->lock, flags);
1793 g->is_selfpowered = !!is_selfpowered;
1794 spin_unlock_irqrestore(&dwc->lock, flags);
1795
1796 return 0;
1797}
1798
1799static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1800{
1801 u32 reg;
1802 u32 timeout = 500;
1803
1804 if (pm_runtime_suspended(dwc->dev))
1805 return 0;
1806
1807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1808 if (is_on) {
1809 if (dwc->revision <= DWC3_REVISION_187A) {
1810 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1811 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1812 }
1813
1814 if (dwc->revision >= DWC3_REVISION_194A)
1815 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1816 reg |= DWC3_DCTL_RUN_STOP;
1817
1818 if (dwc->has_hibernation)
1819 reg |= DWC3_DCTL_KEEP_CONNECT;
1820
1821 dwc->pullups_connected = true;
1822 } else {
1823 reg &= ~DWC3_DCTL_RUN_STOP;
1824
1825 if (dwc->has_hibernation && !suspend)
1826 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1827
1828 dwc->pullups_connected = false;
1829 }
1830
1831 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832
1833 do {
1834 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1835 reg &= DWC3_DSTS_DEVCTRLHLT;
1836 } while (--timeout && !(!is_on ^ !reg));
1837
1838 if (!timeout)
1839 return -ETIMEDOUT;
1840
1841 return 0;
1842}
1843
1844static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1845{
1846 struct dwc3 *dwc = gadget_to_dwc(g);
1847 unsigned long flags;
1848 int ret;
1849
1850 is_on = !!is_on;
1851
1852 /*
1853 * Per databook, when we want to stop the gadget, if a control transfer
1854 * is still in process, complete it and get the core into setup phase.
1855 */
1856 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1857 reinit_completion(&dwc->ep0_in_setup);
1858
1859 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1860 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1861 if (ret == 0) {
1862 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1863 return -ETIMEDOUT;
1864 }
1865 }
1866
1867 spin_lock_irqsave(&dwc->lock, flags);
1868 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1869 spin_unlock_irqrestore(&dwc->lock, flags);
1870
1871 return ret;
1872}
1873
1874static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1875{
1876 u32 reg;
1877
1878 /* Enable all but Start and End of Frame IRQs */
1879 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1880 DWC3_DEVTEN_EVNTOVERFLOWEN |
1881 DWC3_DEVTEN_CMDCMPLTEN |
1882 DWC3_DEVTEN_ERRTICERREN |
1883 DWC3_DEVTEN_WKUPEVTEN |
1884 DWC3_DEVTEN_CONNECTDONEEN |
1885 DWC3_DEVTEN_USBRSTEN |
1886 DWC3_DEVTEN_DISCONNEVTEN);
1887
1888 if (dwc->revision < DWC3_REVISION_250A)
1889 reg |= DWC3_DEVTEN_ULSTCNGEN;
1890
1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1892}
1893
1894static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1895{
1896 /* mask all interrupts */
1897 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1898}
1899
1900static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1901static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1902
1903/**
1904 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1905 * @dwc: pointer to our context structure
1906 *
1907 * The following looks like complex but it's actually very simple. In order to
1908 * calculate the number of packets we can burst at once on OUT transfers, we're
1909 * gonna use RxFIFO size.
1910 *
1911 * To calculate RxFIFO size we need two numbers:
1912 * MDWIDTH = size, in bits, of the internal memory bus
1913 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1914 *
1915 * Given these two numbers, the formula is simple:
1916 *
1917 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1918 *
1919 * 24 bytes is for 3x SETUP packets
1920 * 16 bytes is a clock domain crossing tolerance
1921 *
1922 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1923 */
1924static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925{
1926 u32 ram2_depth;
1927 u32 mdwidth;
1928 u32 nump;
1929 u32 reg;
1930
1931 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1932 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1933
1934 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1935 nump = min_t(u32, nump, 16);
1936
1937 /* update NumP */
1938 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1939 reg &= ~DWC3_DCFG_NUMP_MASK;
1940 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1941 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1942}
1943
1944static int __dwc3_gadget_start(struct dwc3 *dwc)
1945{
1946 struct dwc3_ep *dep;
1947 int ret = 0;
1948 u32 reg;
1949
1950 /*
1951 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1952 * the core supports IMOD, disable it.
1953 */
1954 if (dwc->imod_interval) {
1955 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1956 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1957 } else if (dwc3_has_imod(dwc)) {
1958 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1959 }
1960
1961 /*
1962 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1963 * field instead of letting dwc3 itself calculate that automatically.
1964 *
1965 * This way, we maximize the chances that we'll be able to get several
1966 * bursts of data without going through any sort of endpoint throttling.
1967 */
1968 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1969 if (dwc3_is_usb31(dwc))
1970 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1971 else
1972 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1973
1974 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1975
1976 dwc3_gadget_setup_nump(dwc);
1977
1978 /* Start with SuperSpeed Default */
1979 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1980
1981 dep = dwc->eps[0];
1982 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1983 if (ret) {
1984 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 goto err0;
1986 }
1987
1988 dep = dwc->eps[1];
1989 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1990 if (ret) {
1991 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1992 goto err1;
1993 }
1994
1995 /* begin to receive SETUP packets */
1996 dwc->ep0state = EP0_SETUP_PHASE;
1997 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1998 dwc3_ep0_out_start(dwc);
1999
2000 dwc3_gadget_enable_irq(dwc);
2001
2002 return 0;
2003
2004err1:
2005 __dwc3_gadget_ep_disable(dwc->eps[0]);
2006
2007err0:
2008 return ret;
2009}
2010
2011static int dwc3_gadget_start(struct usb_gadget *g,
2012 struct usb_gadget_driver *driver)
2013{
2014 struct dwc3 *dwc = gadget_to_dwc(g);
2015 unsigned long flags;
2016 int ret = 0;
2017 int irq;
2018
2019 irq = dwc->irq_gadget;
2020 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2021 IRQF_SHARED, "dwc3", dwc->ev_buf);
2022 if (ret) {
2023 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2024 irq, ret);
2025 goto err0;
2026 }
2027
2028 spin_lock_irqsave(&dwc->lock, flags);
2029 if (dwc->gadget_driver) {
2030 dev_err(dwc->dev, "%s is already bound to %s\n",
2031 dwc->gadget.name,
2032 dwc->gadget_driver->driver.name);
2033 ret = -EBUSY;
2034 goto err1;
2035 }
2036
2037 dwc->gadget_driver = driver;
2038
2039 if (pm_runtime_active(dwc->dev))
2040 __dwc3_gadget_start(dwc);
2041
2042 spin_unlock_irqrestore(&dwc->lock, flags);
2043
2044 return 0;
2045
2046err1:
2047 spin_unlock_irqrestore(&dwc->lock, flags);
2048 free_irq(irq, dwc);
2049
2050err0:
2051 return ret;
2052}
2053
2054static void __dwc3_gadget_stop(struct dwc3 *dwc)
2055{
2056 dwc3_gadget_disable_irq(dwc);
2057 __dwc3_gadget_ep_disable(dwc->eps[0]);
2058 __dwc3_gadget_ep_disable(dwc->eps[1]);
2059}
2060
2061static int dwc3_gadget_stop(struct usb_gadget *g)
2062{
2063 struct dwc3 *dwc = gadget_to_dwc(g);
2064 unsigned long flags;
2065
2066 spin_lock_irqsave(&dwc->lock, flags);
2067
2068 if (pm_runtime_suspended(dwc->dev))
2069 goto out;
2070
2071 __dwc3_gadget_stop(dwc);
2072
2073out:
2074 dwc->gadget_driver = NULL;
2075 spin_unlock_irqrestore(&dwc->lock, flags);
2076
2077 free_irq(dwc->irq_gadget, dwc->ev_buf);
2078
2079 return 0;
2080}
2081
2082static void dwc3_gadget_config_params(struct usb_gadget *g,
2083 struct usb_dcd_config_params *params)
2084{
2085 struct dwc3 *dwc = gadget_to_dwc(g);
2086
2087 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2088 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2089
2090 /* Recommended BESL */
2091 if (!dwc->dis_enblslpm_quirk) {
2092 /*
2093 * If the recommended BESL baseline is 0 or if the BESL deep is
2094 * less than 2, Microsoft's Windows 10 host usb stack will issue
2095 * a usb reset immediately after it receives the extended BOS
2096 * descriptor and the enumeration will fail. To maintain
2097 * compatibility with the Windows' usb stack, let's set the
2098 * recommended BESL baseline to 1 and clamp the BESL deep to be
2099 * within 2 to 15.
2100 */
2101 params->besl_baseline = 1;
2102 if (dwc->is_utmi_l1_suspend)
2103 params->besl_deep =
2104 clamp_t(u8, dwc->hird_threshold, 2, 15);
2105 }
2106
2107 /* U1 Device exit Latency */
2108 if (dwc->dis_u1_entry_quirk)
2109 params->bU1devExitLat = 0;
2110 else
2111 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2112
2113 /* U2 Device exit Latency */
2114 if (dwc->dis_u2_entry_quirk)
2115 params->bU2DevExitLat = 0;
2116 else
2117 params->bU2DevExitLat =
2118 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2119}
2120
2121static void dwc3_gadget_set_speed(struct usb_gadget *g,
2122 enum usb_device_speed speed)
2123{
2124 struct dwc3 *dwc = gadget_to_dwc(g);
2125 unsigned long flags;
2126 u32 reg;
2127
2128 spin_lock_irqsave(&dwc->lock, flags);
2129 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2130 reg &= ~(DWC3_DCFG_SPEED_MASK);
2131
2132 /*
2133 * WORKAROUND: DWC3 revision < 2.20a have an issue
2134 * which would cause metastability state on Run/Stop
2135 * bit if we try to force the IP to USB2-only mode.
2136 *
2137 * Because of that, we cannot configure the IP to any
2138 * speed other than the SuperSpeed
2139 *
2140 * Refers to:
2141 *
2142 * STAR#9000525659: Clock Domain Crossing on DCTL in
2143 * USB 2.0 Mode
2144 */
2145 if (dwc->revision < DWC3_REVISION_220A &&
2146 !dwc->dis_metastability_quirk) {
2147 reg |= DWC3_DCFG_SUPERSPEED;
2148 } else {
2149 switch (speed) {
2150 case USB_SPEED_LOW:
2151 reg |= DWC3_DCFG_LOWSPEED;
2152 break;
2153 case USB_SPEED_FULL:
2154 reg |= DWC3_DCFG_FULLSPEED;
2155 break;
2156 case USB_SPEED_HIGH:
2157 reg |= DWC3_DCFG_HIGHSPEED;
2158 break;
2159 case USB_SPEED_SUPER:
2160 reg |= DWC3_DCFG_SUPERSPEED;
2161 break;
2162 case USB_SPEED_SUPER_PLUS:
2163 if (dwc3_is_usb31(dwc))
2164 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2165 else
2166 reg |= DWC3_DCFG_SUPERSPEED;
2167 break;
2168 default:
2169 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2170
2171 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2172 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2173 else
2174 reg |= DWC3_DCFG_SUPERSPEED;
2175 }
2176 }
2177 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2178
2179 spin_unlock_irqrestore(&dwc->lock, flags);
2180}
2181
2182static const struct usb_gadget_ops dwc3_gadget_ops = {
2183 .get_frame = dwc3_gadget_get_frame,
2184 .wakeup = dwc3_gadget_wakeup,
2185 .set_selfpowered = dwc3_gadget_set_selfpowered,
2186 .pullup = dwc3_gadget_pullup,
2187 .udc_start = dwc3_gadget_start,
2188 .udc_stop = dwc3_gadget_stop,
2189 .udc_set_speed = dwc3_gadget_set_speed,
2190 .get_config_params = dwc3_gadget_config_params,
2191};
2192
2193/* -------------------------------------------------------------------------- */
2194
2195static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2196{
2197 struct dwc3 *dwc = dep->dwc;
2198
2199 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2200 dep->endpoint.maxburst = 1;
2201 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2202 if (!dep->direction)
2203 dwc->gadget.ep0 = &dep->endpoint;
2204
2205 dep->endpoint.caps.type_control = true;
2206
2207 return 0;
2208}
2209
2210static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2211{
2212 struct dwc3 *dwc = dep->dwc;
2213 int mdwidth;
2214 int kbytes;
2215 int size;
2216
2217 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2218 /* MDWIDTH is represented in bits, we need it in bytes */
2219 mdwidth /= 8;
2220
2221 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2222 if (dwc3_is_usb31(dwc))
2223 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2224 else
2225 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2226
2227 /* FIFO Depth is in MDWDITH bytes. Multiply */
2228 size *= mdwidth;
2229
2230 kbytes = size / 1024;
2231 if (kbytes == 0)
2232 kbytes = 1;
2233
2234 /*
2235 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2236 * internal overhead. We don't really know how these are used,
2237 * but documentation say it exists.
2238 */
2239 size -= mdwidth * (kbytes + 1);
2240 size /= kbytes;
2241
2242 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2243
2244 dep->endpoint.max_streams = 15;
2245 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2246 list_add_tail(&dep->endpoint.ep_list,
2247 &dwc->gadget.ep_list);
2248 dep->endpoint.caps.type_iso = true;
2249 dep->endpoint.caps.type_bulk = true;
2250 dep->endpoint.caps.type_int = true;
2251
2252 return dwc3_alloc_trb_pool(dep);
2253}
2254
2255static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2256{
2257 struct dwc3 *dwc = dep->dwc;
2258
2259 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2260 dep->endpoint.max_streams = 15;
2261 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2262 list_add_tail(&dep->endpoint.ep_list,
2263 &dwc->gadget.ep_list);
2264 dep->endpoint.caps.type_iso = true;
2265 dep->endpoint.caps.type_bulk = true;
2266 dep->endpoint.caps.type_int = true;
2267
2268 return dwc3_alloc_trb_pool(dep);
2269}
2270
2271static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2272{
2273 struct dwc3_ep *dep;
2274 bool direction = epnum & 1;
2275 int ret;
2276 u8 num = epnum >> 1;
2277
2278 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2279 if (!dep)
2280 return -ENOMEM;
2281
2282 dep->dwc = dwc;
2283 dep->number = epnum;
2284 dep->direction = direction;
2285 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2286 dwc->eps[epnum] = dep;
2287 dep->combo_num = 0;
2288 dep->start_cmd_status = 0;
2289
2290 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2291 direction ? "in" : "out");
2292
2293 dep->endpoint.name = dep->name;
2294
2295 if (!(dep->number > 1)) {
2296 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2297 dep->endpoint.comp_desc = NULL;
2298 }
2299
2300 if (num == 0)
2301 ret = dwc3_gadget_init_control_endpoint(dep);
2302 else if (direction)
2303 ret = dwc3_gadget_init_in_endpoint(dep);
2304 else
2305 ret = dwc3_gadget_init_out_endpoint(dep);
2306
2307 if (ret)
2308 return ret;
2309
2310 dep->endpoint.caps.dir_in = direction;
2311 dep->endpoint.caps.dir_out = !direction;
2312
2313 INIT_LIST_HEAD(&dep->pending_list);
2314 INIT_LIST_HEAD(&dep->started_list);
2315 INIT_LIST_HEAD(&dep->cancelled_list);
2316
2317 return 0;
2318}
2319
2320static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2321{
2322 u8 epnum;
2323
2324 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2325
2326 for (epnum = 0; epnum < total; epnum++) {
2327 int ret;
2328
2329 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2330 if (ret)
2331 return ret;
2332 }
2333
2334 return 0;
2335}
2336
2337static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2338{
2339 struct dwc3_ep *dep;
2340 u8 epnum;
2341
2342 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343 dep = dwc->eps[epnum];
2344 if (!dep)
2345 continue;
2346 /*
2347 * Physical endpoints 0 and 1 are special; they form the
2348 * bi-directional USB endpoint 0.
2349 *
2350 * For those two physical endpoints, we don't allocate a TRB
2351 * pool nor do we add them the endpoints list. Due to that, we
2352 * shouldn't do these two operations otherwise we would end up
2353 * with all sorts of bugs when removing dwc3.ko.
2354 */
2355 if (epnum != 0 && epnum != 1) {
2356 dwc3_free_trb_pool(dep);
2357 list_del(&dep->endpoint.ep_list);
2358 }
2359
2360 kfree(dep);
2361 }
2362}
2363
2364/* -------------------------------------------------------------------------- */
2365
2366static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2367 struct dwc3_request *req, struct dwc3_trb *trb,
2368 const struct dwc3_event_depevt *event, int status, int chain)
2369{
2370 unsigned int count;
2371
2372 dwc3_ep_inc_deq(dep);
2373
2374 trace_dwc3_complete_trb(dep, trb);
2375 req->num_trbs--;
2376
2377 /*
2378 * If we're in the middle of series of chained TRBs and we
2379 * receive a short transfer along the way, DWC3 will skip
2380 * through all TRBs including the last TRB in the chain (the
2381 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2382 * bit and SW has to do it manually.
2383 *
2384 * We're going to do that here to avoid problems of HW trying
2385 * to use bogus TRBs for transfers.
2386 */
2387 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2388 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2389
2390 /*
2391 * For isochronous transfers, the first TRB in a service interval must
2392 * have the Isoc-First type. Track and report its interval frame number.
2393 */
2394 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2395 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2396 unsigned int frame_number;
2397
2398 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2399 frame_number &= ~(dep->interval - 1);
2400 req->request.frame_number = frame_number;
2401 }
2402
2403 /*
2404 * If we're dealing with unaligned size OUT transfer, we will be left
2405 * with one TRB pending in the ring. We need to manually clear HWO bit
2406 * from that TRB.
2407 */
2408
2409 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2410 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2411 return 1;
2412 }
2413
2414 count = trb->size & DWC3_TRB_SIZE_MASK;
2415 req->remaining += count;
2416
2417 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2418 return 1;
2419
2420 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2421 return 1;
2422
2423 if (event->status & DEPEVT_STATUS_IOC)
2424 return 1;
2425
2426 return 0;
2427}
2428
2429static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2430 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2431 int status)
2432{
2433 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2434 struct scatterlist *sg = req->sg;
2435 struct scatterlist *s;
2436 unsigned int pending = req->num_pending_sgs;
2437 unsigned int i;
2438 int ret = 0;
2439
2440 for_each_sg(sg, s, pending, i) {
2441 trb = &dep->trb_pool[dep->trb_dequeue];
2442
2443 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2444 break;
2445
2446 req->sg = sg_next(s);
2447 req->num_pending_sgs--;
2448
2449 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2450 trb, event, status, true);
2451 if (ret)
2452 break;
2453 }
2454
2455 return ret;
2456}
2457
2458static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2459 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2460 int status)
2461{
2462 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2463
2464 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2465 event, status, false);
2466}
2467
2468static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2469{
2470 return req->request.actual == req->request.length;
2471}
2472
2473static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2474 const struct dwc3_event_depevt *event,
2475 struct dwc3_request *req, int status)
2476{
2477 int ret;
2478
2479 if (req->num_pending_sgs)
2480 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2481 status);
2482 else
2483 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2484 status);
2485
2486 if (req->needs_extra_trb) {
2487 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2488 status);
2489 req->needs_extra_trb = false;
2490 }
2491
2492 req->request.actual = req->request.length - req->remaining;
2493
2494 if (!dwc3_gadget_ep_request_completed(req) &&
2495 req->num_pending_sgs) {
2496 __dwc3_gadget_kick_transfer(dep);
2497 goto out;
2498 }
2499
2500 dwc3_gadget_giveback(dep, req, status);
2501
2502out:
2503 return ret;
2504}
2505
2506static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2507 const struct dwc3_event_depevt *event, int status)
2508{
2509 struct dwc3_request *req;
2510 struct dwc3_request *tmp;
2511
2512 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2513 int ret;
2514
2515 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2516 req, status);
2517 if (ret)
2518 break;
2519 }
2520}
2521
2522static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2523 const struct dwc3_event_depevt *event)
2524{
2525 dep->frame_number = event->parameters;
2526}
2527
2528static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2529 const struct dwc3_event_depevt *event)
2530{
2531 struct dwc3 *dwc = dep->dwc;
2532 unsigned status = 0;
2533 bool stop = false;
2534
2535 dwc3_gadget_endpoint_frame_from_event(dep, event);
2536
2537 if (event->status & DEPEVT_STATUS_BUSERR)
2538 status = -ECONNRESET;
2539
2540 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2541 status = -EXDEV;
2542
2543 if (list_empty(&dep->started_list))
2544 stop = true;
2545 }
2546
2547 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2548
2549 if (stop) {
2550 dwc3_stop_active_transfer(dep, true, true);
2551 dep->flags = DWC3_EP_ENABLED;
2552 }
2553
2554 /*
2555 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2556 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2557 */
2558 if (dwc->revision < DWC3_REVISION_183A) {
2559 u32 reg;
2560 int i;
2561
2562 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2563 dep = dwc->eps[i];
2564
2565 if (!(dep->flags & DWC3_EP_ENABLED))
2566 continue;
2567
2568 if (!list_empty(&dep->started_list))
2569 return;
2570 }
2571
2572 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2573 reg |= dwc->u1u2;
2574 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2575
2576 dwc->u1u2 = 0;
2577 }
2578}
2579
2580static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2581 const struct dwc3_event_depevt *event)
2582{
2583 dwc3_gadget_endpoint_frame_from_event(dep, event);
2584 (void) __dwc3_gadget_start_isoc(dep);
2585}
2586
2587static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2588 const struct dwc3_event_depevt *event)
2589{
2590 struct dwc3_ep *dep;
2591 u8 epnum = event->endpoint_number;
2592 u8 cmd;
2593
2594 dep = dwc->eps[epnum];
2595
2596 if (!(dep->flags & DWC3_EP_ENABLED)) {
2597 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2598 return;
2599
2600 /* Handle only EPCMDCMPLT when EP disabled */
2601 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2602 return;
2603 }
2604
2605 if (epnum == 0 || epnum == 1) {
2606 dwc3_ep0_interrupt(dwc, event);
2607 return;
2608 }
2609
2610 switch (event->endpoint_event) {
2611 case DWC3_DEPEVT_XFERINPROGRESS:
2612 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2613 break;
2614 case DWC3_DEPEVT_XFERNOTREADY:
2615 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2616 break;
2617 case DWC3_DEPEVT_EPCMDCMPLT:
2618 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2619
2620 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2621 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2622 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2623 }
2624 break;
2625 case DWC3_DEPEVT_STREAMEVT:
2626 case DWC3_DEPEVT_XFERCOMPLETE:
2627 case DWC3_DEPEVT_RXTXFIFOEVT:
2628 break;
2629 }
2630}
2631
2632static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2633{
2634 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2635 spin_unlock(&dwc->lock);
2636 dwc->gadget_driver->disconnect(&dwc->gadget);
2637 spin_lock(&dwc->lock);
2638 }
2639}
2640
2641static void dwc3_suspend_gadget(struct dwc3 *dwc)
2642{
2643 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2644 spin_unlock(&dwc->lock);
2645 dwc->gadget_driver->suspend(&dwc->gadget);
2646 spin_lock(&dwc->lock);
2647 }
2648}
2649
2650static void dwc3_resume_gadget(struct dwc3 *dwc)
2651{
2652 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2653 spin_unlock(&dwc->lock);
2654 dwc->gadget_driver->resume(&dwc->gadget);
2655 spin_lock(&dwc->lock);
2656 }
2657}
2658
2659static void dwc3_reset_gadget(struct dwc3 *dwc)
2660{
2661 if (!dwc->gadget_driver)
2662 return;
2663
2664 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2665 spin_unlock(&dwc->lock);
2666 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2667 spin_lock(&dwc->lock);
2668 }
2669}
2670
2671static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2672 bool interrupt)
2673{
2674 struct dwc3 *dwc = dep->dwc;
2675 struct dwc3_gadget_ep_cmd_params params;
2676 u32 cmd;
2677 int ret;
2678
2679 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2680 return;
2681
2682 /*
2683 * NOTICE: We are violating what the Databook says about the
2684 * EndTransfer command. Ideally we would _always_ wait for the
2685 * EndTransfer Command Completion IRQ, but that's causing too
2686 * much trouble synchronizing between us and gadget driver.
2687 *
2688 * We have discussed this with the IP Provider and it was
2689 * suggested to giveback all requests here, but give HW some
2690 * extra time to synchronize with the interconnect. We're using
2691 * an arbitrary 100us delay for that.
2692 *
2693 * Note also that a similar handling was tested by Synopsys
2694 * (thanks a lot Paul) and nothing bad has come out of it.
2695 * In short, what we're doing is:
2696 *
2697 * - Issue EndTransfer WITH CMDIOC bit set
2698 * - Wait 100us
2699 *
2700 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2701 * supports a mode to work around the above limitation. The
2702 * software can poll the CMDACT bit in the DEPCMD register
2703 * after issuing a EndTransfer command. This mode is enabled
2704 * by writing GUCTL2[14]. This polling is already done in the
2705 * dwc3_send_gadget_ep_cmd() function so if the mode is
2706 * enabled, the EndTransfer command will have completed upon
2707 * returning from this function and we don't need to delay for
2708 * 100us.
2709 *
2710 * This mode is NOT available on the DWC_usb31 IP.
2711 */
2712
2713 cmd = DWC3_DEPCMD_ENDTRANSFER;
2714 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2715 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2716 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2717 memset(¶ms, 0, sizeof(params));
2718 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2719 WARN_ON_ONCE(ret);
2720 dep->resource_index = 0;
2721
2722 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2723 udelay(100);
2724}
2725
2726static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2727{
2728 u32 epnum;
2729
2730 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2731 struct dwc3_ep *dep;
2732 int ret;
2733
2734 dep = dwc->eps[epnum];
2735 if (!dep)
2736 continue;
2737
2738 if (!(dep->flags & DWC3_EP_STALL))
2739 continue;
2740
2741 dep->flags &= ~DWC3_EP_STALL;
2742
2743 ret = dwc3_send_clear_stall_ep_cmd(dep);
2744 WARN_ON_ONCE(ret);
2745 }
2746}
2747
2748static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2749{
2750 int reg;
2751
2752 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2753 reg &= ~DWC3_DCTL_INITU1ENA;
2754 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2755
2756 reg &= ~DWC3_DCTL_INITU2ENA;
2757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2758
2759 dwc3_disconnect_gadget(dwc);
2760
2761 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2762 dwc->setup_packet_pending = false;
2763 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2764
2765 dwc->connected = false;
2766}
2767
2768static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2769{
2770 u32 reg;
2771
2772 dwc->connected = true;
2773
2774 /*
2775 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2776 * would cause a missing Disconnect Event if there's a
2777 * pending Setup Packet in the FIFO.
2778 *
2779 * There's no suggested workaround on the official Bug
2780 * report, which states that "unless the driver/application
2781 * is doing any special handling of a disconnect event,
2782 * there is no functional issue".
2783 *
2784 * Unfortunately, it turns out that we _do_ some special
2785 * handling of a disconnect event, namely complete all
2786 * pending transfers, notify gadget driver of the
2787 * disconnection, and so on.
2788 *
2789 * Our suggested workaround is to follow the Disconnect
2790 * Event steps here, instead, based on a setup_packet_pending
2791 * flag. Such flag gets set whenever we have a SETUP_PENDING
2792 * status for EP0 TRBs and gets cleared on XferComplete for the
2793 * same endpoint.
2794 *
2795 * Refers to:
2796 *
2797 * STAR#9000466709: RTL: Device : Disconnect event not
2798 * generated if setup packet pending in FIFO
2799 */
2800 if (dwc->revision < DWC3_REVISION_188A) {
2801 if (dwc->setup_packet_pending)
2802 dwc3_gadget_disconnect_interrupt(dwc);
2803 }
2804
2805 dwc3_reset_gadget(dwc);
2806
2807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2808 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2809 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2810 dwc->test_mode = false;
2811 dwc3_clear_stall_all_ep(dwc);
2812
2813 /* Reset device address to zero */
2814 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2815 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2816 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2817}
2818
2819static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2820{
2821 struct dwc3_ep *dep;
2822 int ret;
2823 u32 reg;
2824 u8 speed;
2825
2826 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2827 speed = reg & DWC3_DSTS_CONNECTSPD;
2828 dwc->speed = speed;
2829
2830 /*
2831 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2832 * each time on Connect Done.
2833 *
2834 * Currently we always use the reset value. If any platform
2835 * wants to set this to a different value, we need to add a
2836 * setting and update GCTL.RAMCLKSEL here.
2837 */
2838
2839 switch (speed) {
2840 case DWC3_DSTS_SUPERSPEED_PLUS:
2841 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2842 dwc->gadget.ep0->maxpacket = 512;
2843 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2844 break;
2845 case DWC3_DSTS_SUPERSPEED:
2846 /*
2847 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2848 * would cause a missing USB3 Reset event.
2849 *
2850 * In such situations, we should force a USB3 Reset
2851 * event by calling our dwc3_gadget_reset_interrupt()
2852 * routine.
2853 *
2854 * Refers to:
2855 *
2856 * STAR#9000483510: RTL: SS : USB3 reset event may
2857 * not be generated always when the link enters poll
2858 */
2859 if (dwc->revision < DWC3_REVISION_190A)
2860 dwc3_gadget_reset_interrupt(dwc);
2861
2862 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2863 dwc->gadget.ep0->maxpacket = 512;
2864 dwc->gadget.speed = USB_SPEED_SUPER;
2865 break;
2866 case DWC3_DSTS_HIGHSPEED:
2867 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2868 dwc->gadget.ep0->maxpacket = 64;
2869 dwc->gadget.speed = USB_SPEED_HIGH;
2870 break;
2871 case DWC3_DSTS_FULLSPEED:
2872 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2873 dwc->gadget.ep0->maxpacket = 64;
2874 dwc->gadget.speed = USB_SPEED_FULL;
2875 break;
2876 case DWC3_DSTS_LOWSPEED:
2877 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2878 dwc->gadget.ep0->maxpacket = 8;
2879 dwc->gadget.speed = USB_SPEED_LOW;
2880 break;
2881 }
2882
2883 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2884
2885 /* Enable USB2 LPM Capability */
2886
2887 if ((dwc->revision > DWC3_REVISION_194A) &&
2888 (speed != DWC3_DSTS_SUPERSPEED) &&
2889 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2890 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2891 reg |= DWC3_DCFG_LPM_CAP;
2892 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2893
2894 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2895 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2896
2897 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2898 (dwc->is_utmi_l1_suspend << 4));
2899
2900 /*
2901 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2902 * DCFG.LPMCap is set, core responses with an ACK and the
2903 * BESL value in the LPM token is less than or equal to LPM
2904 * NYET threshold.
2905 */
2906 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2907 && dwc->has_lpm_erratum,
2908 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2909
2910 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2911 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
2912
2913 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2914 } else {
2915 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2916 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2917 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2918 }
2919
2920 dep = dwc->eps[0];
2921 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2922 if (ret) {
2923 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2924 return;
2925 }
2926
2927 dep = dwc->eps[1];
2928 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2929 if (ret) {
2930 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2931 return;
2932 }
2933
2934 /*
2935 * Configure PHY via GUSB3PIPECTLn if required.
2936 *
2937 * Update GTXFIFOSIZn
2938 *
2939 * In both cases reset values should be sufficient.
2940 */
2941}
2942
2943static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2944{
2945 /*
2946 * TODO take core out of low power mode when that's
2947 * implemented.
2948 */
2949
2950 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2951 spin_unlock(&dwc->lock);
2952 dwc->gadget_driver->resume(&dwc->gadget);
2953 spin_lock(&dwc->lock);
2954 }
2955}
2956
2957static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2958 unsigned int evtinfo)
2959{
2960 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2961 unsigned int pwropt;
2962
2963 /*
2964 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2965 * Hibernation mode enabled which would show up when device detects
2966 * host-initiated U3 exit.
2967 *
2968 * In that case, device will generate a Link State Change Interrupt
2969 * from U3 to RESUME which is only necessary if Hibernation is
2970 * configured in.
2971 *
2972 * There are no functional changes due to such spurious event and we
2973 * just need to ignore it.
2974 *
2975 * Refers to:
2976 *
2977 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2978 * operational mode
2979 */
2980 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2981 if ((dwc->revision < DWC3_REVISION_250A) &&
2982 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2983 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2984 (next == DWC3_LINK_STATE_RESUME)) {
2985 return;
2986 }
2987 }
2988
2989 /*
2990 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2991 * on the link partner, the USB session might do multiple entry/exit
2992 * of low power states before a transfer takes place.
2993 *
2994 * Due to this problem, we might experience lower throughput. The
2995 * suggested workaround is to disable DCTL[12:9] bits if we're
2996 * transitioning from U1/U2 to U0 and enable those bits again
2997 * after a transfer completes and there are no pending transfers
2998 * on any of the enabled endpoints.
2999 *
3000 * This is the first half of that workaround.
3001 *
3002 * Refers to:
3003 *
3004 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3005 * core send LGO_Ux entering U0
3006 */
3007 if (dwc->revision < DWC3_REVISION_183A) {
3008 if (next == DWC3_LINK_STATE_U0) {
3009 u32 u1u2;
3010 u32 reg;
3011
3012 switch (dwc->link_state) {
3013 case DWC3_LINK_STATE_U1:
3014 case DWC3_LINK_STATE_U2:
3015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3016 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3017 | DWC3_DCTL_ACCEPTU2ENA
3018 | DWC3_DCTL_INITU1ENA
3019 | DWC3_DCTL_ACCEPTU1ENA);
3020
3021 if (!dwc->u1u2)
3022 dwc->u1u2 = reg & u1u2;
3023
3024 reg &= ~u1u2;
3025
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3027 break;
3028 default:
3029 /* do nothing */
3030 break;
3031 }
3032 }
3033 }
3034
3035 switch (next) {
3036 case DWC3_LINK_STATE_U1:
3037 if (dwc->speed == USB_SPEED_SUPER)
3038 dwc3_suspend_gadget(dwc);
3039 break;
3040 case DWC3_LINK_STATE_U2:
3041 case DWC3_LINK_STATE_U3:
3042 dwc3_suspend_gadget(dwc);
3043 break;
3044 case DWC3_LINK_STATE_RESUME:
3045 dwc3_resume_gadget(dwc);
3046 break;
3047 default:
3048 /* do nothing */
3049 break;
3050 }
3051
3052 dwc->link_state = next;
3053}
3054
3055static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3056 unsigned int evtinfo)
3057{
3058 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3059
3060 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3061 dwc3_suspend_gadget(dwc);
3062
3063 dwc->link_state = next;
3064}
3065
3066static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3067 unsigned int evtinfo)
3068{
3069 unsigned int is_ss = evtinfo & BIT(4);
3070
3071 /*
3072 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3073 * have a known issue which can cause USB CV TD.9.23 to fail
3074 * randomly.
3075 *
3076 * Because of this issue, core could generate bogus hibernation
3077 * events which SW needs to ignore.
3078 *
3079 * Refers to:
3080 *
3081 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3082 * Device Fallback from SuperSpeed
3083 */
3084 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3085 return;
3086
3087 /* enter hibernation here */
3088}
3089
3090static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3091 const struct dwc3_event_devt *event)
3092{
3093 switch (event->type) {
3094 case DWC3_DEVICE_EVENT_DISCONNECT:
3095 dwc3_gadget_disconnect_interrupt(dwc);
3096 break;
3097 case DWC3_DEVICE_EVENT_RESET:
3098 dwc3_gadget_reset_interrupt(dwc);
3099 break;
3100 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3101 dwc3_gadget_conndone_interrupt(dwc);
3102 break;
3103 case DWC3_DEVICE_EVENT_WAKEUP:
3104 dwc3_gadget_wakeup_interrupt(dwc);
3105 break;
3106 case DWC3_DEVICE_EVENT_HIBER_REQ:
3107 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3108 "unexpected hibernation event\n"))
3109 break;
3110
3111 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3112 break;
3113 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3114 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3115 break;
3116 case DWC3_DEVICE_EVENT_EOPF:
3117 /* It changed to be suspend event for version 2.30a and above */
3118 if (dwc->revision >= DWC3_REVISION_230A) {
3119 /*
3120 * Ignore suspend event until the gadget enters into
3121 * USB_STATE_CONFIGURED state.
3122 */
3123 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3124 dwc3_gadget_suspend_interrupt(dwc,
3125 event->event_info);
3126 }
3127 break;
3128 case DWC3_DEVICE_EVENT_SOF:
3129 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3130 case DWC3_DEVICE_EVENT_CMD_CMPL:
3131 case DWC3_DEVICE_EVENT_OVERFLOW:
3132 break;
3133 default:
3134 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3135 }
3136}
3137
3138static void dwc3_process_event_entry(struct dwc3 *dwc,
3139 const union dwc3_event *event)
3140{
3141 trace_dwc3_event(event->raw, dwc);
3142
3143 if (!event->type.is_devspec)
3144 dwc3_endpoint_interrupt(dwc, &event->depevt);
3145 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3146 dwc3_gadget_interrupt(dwc, &event->devt);
3147 else
3148 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3149}
3150
3151static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3152{
3153 struct dwc3 *dwc = evt->dwc;
3154 irqreturn_t ret = IRQ_NONE;
3155 int left;
3156 u32 reg;
3157
3158 left = evt->count;
3159
3160 if (!(evt->flags & DWC3_EVENT_PENDING))
3161 return IRQ_NONE;
3162
3163 while (left > 0) {
3164 union dwc3_event event;
3165
3166 event.raw = *(u32 *) (evt->cache + evt->lpos);
3167
3168 dwc3_process_event_entry(dwc, &event);
3169
3170 /*
3171 * FIXME we wrap around correctly to the next entry as
3172 * almost all entries are 4 bytes in size. There is one
3173 * entry which has 12 bytes which is a regular entry
3174 * followed by 8 bytes data. ATM I don't know how
3175 * things are organized if we get next to the a
3176 * boundary so I worry about that once we try to handle
3177 * that.
3178 */
3179 evt->lpos = (evt->lpos + 4) % evt->length;
3180 left -= 4;
3181 }
3182
3183 evt->count = 0;
3184 evt->flags &= ~DWC3_EVENT_PENDING;
3185 ret = IRQ_HANDLED;
3186
3187 /* Unmask interrupt */
3188 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3189 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3190 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3191
3192 if (dwc->imod_interval) {
3193 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3194 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3195 }
3196
3197 return ret;
3198}
3199
3200static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3201{
3202 struct dwc3_event_buffer *evt = _evt;
3203 struct dwc3 *dwc = evt->dwc;
3204 unsigned long flags;
3205 irqreturn_t ret = IRQ_NONE;
3206
3207 spin_lock_irqsave(&dwc->lock, flags);
3208 ret = dwc3_process_event_buf(evt);
3209 spin_unlock_irqrestore(&dwc->lock, flags);
3210
3211 return ret;
3212}
3213
3214static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3215{
3216 struct dwc3 *dwc = evt->dwc;
3217 u32 amount;
3218 u32 count;
3219 u32 reg;
3220
3221 if (pm_runtime_suspended(dwc->dev)) {
3222 pm_runtime_get(dwc->dev);
3223 disable_irq_nosync(dwc->irq_gadget);
3224 dwc->pending_events = true;
3225 return IRQ_HANDLED;
3226 }
3227
3228 /*
3229 * With PCIe legacy interrupt, test shows that top-half irq handler can
3230 * be called again after HW interrupt deassertion. Check if bottom-half
3231 * irq event handler completes before caching new event to prevent
3232 * losing events.
3233 */
3234 if (evt->flags & DWC3_EVENT_PENDING)
3235 return IRQ_HANDLED;
3236
3237 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3238 count &= DWC3_GEVNTCOUNT_MASK;
3239 if (!count)
3240 return IRQ_NONE;
3241
3242 evt->count = count;
3243 evt->flags |= DWC3_EVENT_PENDING;
3244
3245 /* Mask interrupt */
3246 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3247 reg |= DWC3_GEVNTSIZ_INTMASK;
3248 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3249
3250 amount = min(count, evt->length - evt->lpos);
3251 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3252
3253 if (amount < count)
3254 memcpy(evt->cache, evt->buf, count - amount);
3255
3256 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3257
3258 return IRQ_WAKE_THREAD;
3259}
3260
3261static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3262{
3263 struct dwc3_event_buffer *evt = _evt;
3264
3265 return dwc3_check_event_buf(evt);
3266}
3267
3268static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3269{
3270 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3271 int irq;
3272
3273 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3274 if (irq > 0)
3275 goto out;
3276
3277 if (irq == -EPROBE_DEFER)
3278 goto out;
3279
3280 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3281 if (irq > 0)
3282 goto out;
3283
3284 if (irq == -EPROBE_DEFER)
3285 goto out;
3286
3287 irq = platform_get_irq(dwc3_pdev, 0);
3288 if (irq > 0)
3289 goto out;
3290
3291 if (!irq)
3292 irq = -EINVAL;
3293
3294out:
3295 return irq;
3296}
3297
3298/**
3299 * dwc3_gadget_init - initializes gadget related registers
3300 * @dwc: pointer to our controller context structure
3301 *
3302 * Returns 0 on success otherwise negative errno.
3303 */
3304int dwc3_gadget_init(struct dwc3 *dwc)
3305{
3306 int ret;
3307 int irq;
3308
3309 irq = dwc3_gadget_get_irq(dwc);
3310 if (irq < 0) {
3311 ret = irq;
3312 goto err0;
3313 }
3314
3315 dwc->irq_gadget = irq;
3316
3317 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3318 sizeof(*dwc->ep0_trb) * 2,
3319 &dwc->ep0_trb_addr, GFP_KERNEL);
3320 if (!dwc->ep0_trb) {
3321 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3322 ret = -ENOMEM;
3323 goto err0;
3324 }
3325
3326 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3327 if (!dwc->setup_buf) {
3328 ret = -ENOMEM;
3329 goto err1;
3330 }
3331
3332 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3333 &dwc->bounce_addr, GFP_KERNEL);
3334 if (!dwc->bounce) {
3335 ret = -ENOMEM;
3336 goto err2;
3337 }
3338
3339 init_completion(&dwc->ep0_in_setup);
3340
3341 dwc->gadget.ops = &dwc3_gadget_ops;
3342 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3343 dwc->gadget.sg_supported = true;
3344 dwc->gadget.name = "dwc3-gadget";
3345 dwc->gadget.lpm_capable = true;
3346
3347 /*
3348 * FIXME We might be setting max_speed to <SUPER, however versions
3349 * <2.20a of dwc3 have an issue with metastability (documented
3350 * elsewhere in this driver) which tells us we can't set max speed to
3351 * anything lower than SUPER.
3352 *
3353 * Because gadget.max_speed is only used by composite.c and function
3354 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3355 * to happen so we avoid sending SuperSpeed Capability descriptor
3356 * together with our BOS descriptor as that could confuse host into
3357 * thinking we can handle super speed.
3358 *
3359 * Note that, in fact, we won't even support GetBOS requests when speed
3360 * is less than super speed because we don't have means, yet, to tell
3361 * composite.c that we are USB 2.0 + LPM ECN.
3362 */
3363 if (dwc->revision < DWC3_REVISION_220A &&
3364 !dwc->dis_metastability_quirk)
3365 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3366 dwc->revision);
3367
3368 dwc->gadget.max_speed = dwc->maximum_speed;
3369
3370 /*
3371 * REVISIT: Here we should clear all pending IRQs to be
3372 * sure we're starting from a well known location.
3373 */
3374
3375 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3376 if (ret)
3377 goto err3;
3378
3379 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3380 if (ret) {
3381 dev_err(dwc->dev, "failed to register udc\n");
3382 goto err4;
3383 }
3384
3385 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3386
3387 return 0;
3388
3389err4:
3390 dwc3_gadget_free_endpoints(dwc);
3391
3392err3:
3393 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3394 dwc->bounce_addr);
3395
3396err2:
3397 kfree(dwc->setup_buf);
3398
3399err1:
3400 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3401 dwc->ep0_trb, dwc->ep0_trb_addr);
3402
3403err0:
3404 return ret;
3405}
3406
3407/* -------------------------------------------------------------------------- */
3408
3409void dwc3_gadget_exit(struct dwc3 *dwc)
3410{
3411 usb_del_gadget_udc(&dwc->gadget);
3412 dwc3_gadget_free_endpoints(dwc);
3413 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3414 dwc->bounce_addr);
3415 kfree(dwc->setup_buf);
3416 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3417 dwc->ep0_trb, dwc->ep0_trb_addr);
3418}
3419
3420int dwc3_gadget_suspend(struct dwc3 *dwc)
3421{
3422 if (!dwc->gadget_driver)
3423 return 0;
3424
3425 dwc3_gadget_run_stop(dwc, false, false);
3426 dwc3_disconnect_gadget(dwc);
3427 __dwc3_gadget_stop(dwc);
3428
3429 return 0;
3430}
3431
3432int dwc3_gadget_resume(struct dwc3 *dwc)
3433{
3434 int ret;
3435
3436 if (!dwc->gadget_driver)
3437 return 0;
3438
3439 ret = __dwc3_gadget_start(dwc);
3440 if (ret < 0)
3441 goto err0;
3442
3443 ret = dwc3_gadget_run_stop(dwc, true, false);
3444 if (ret < 0)
3445 goto err1;
3446
3447 return 0;
3448
3449err1:
3450 __dwc3_gadget_stop(dwc);
3451
3452err0:
3453 return ret;
3454}
3455
3456void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3457{
3458 if (dwc->pending_events) {
3459 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3460 dwc->pending_events = false;
3461 enable_irq(dwc->irq_gadget);
3462 }
3463}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30/**
31 * dwc3_gadget_set_test_mode - enables usb2 test modes
32 * @dwc: pointer to our context structure
33 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
34 *
35 * Caller should take care of locking. This function will return 0 on
36 * success or -EINVAL if wrong Test Selector is passed.
37 */
38int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
39{
40 u32 reg;
41
42 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
43 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
44
45 switch (mode) {
46 case TEST_J:
47 case TEST_K:
48 case TEST_SE0_NAK:
49 case TEST_PACKET:
50 case TEST_FORCE_EN:
51 reg |= mode << 1;
52 break;
53 default:
54 return -EINVAL;
55 }
56
57 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
58
59 return 0;
60}
61
62/**
63 * dwc3_gadget_get_link_state - gets current state of usb link
64 * @dwc: pointer to our context structure
65 *
66 * Caller should take care of locking. This function will
67 * return the link state on success (>= 0) or -ETIMEDOUT.
68 */
69int dwc3_gadget_get_link_state(struct dwc3 *dwc)
70{
71 u32 reg;
72
73 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
74
75 return DWC3_DSTS_USBLNKST(reg);
76}
77
78/**
79 * dwc3_gadget_set_link_state - sets usb link to a particular state
80 * @dwc: pointer to our context structure
81 * @state: the state to put link into
82 *
83 * Caller should take care of locking. This function will
84 * return 0 on success or -ETIMEDOUT.
85 */
86int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
87{
88 int retries = 10000;
89 u32 reg;
90
91 /*
92 * Wait until device controller is ready. Only applies to 1.94a and
93 * later RTL.
94 */
95 if (dwc->revision >= DWC3_REVISION_194A) {
96 while (--retries) {
97 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
98 if (reg & DWC3_DSTS_DCNRD)
99 udelay(5);
100 else
101 break;
102 }
103
104 if (retries <= 0)
105 return -ETIMEDOUT;
106 }
107
108 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
109 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
110
111 /* set requested state */
112 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
113 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
114
115 /*
116 * The following code is racy when called from dwc3_gadget_wakeup,
117 * and is not needed, at least on newer versions
118 */
119 if (dwc->revision >= DWC3_REVISION_194A)
120 return 0;
121
122 /* wait for a change in DSTS */
123 retries = 10000;
124 while (--retries) {
125 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
126
127 if (DWC3_DSTS_USBLNKST(reg) == state)
128 return 0;
129
130 udelay(5);
131 }
132
133 return -ETIMEDOUT;
134}
135
136/**
137 * dwc3_ep_inc_trb - increment a trb index.
138 * @index: Pointer to the TRB index to increment.
139 *
140 * The index should never point to the link TRB. After incrementing,
141 * if it is point to the link TRB, wrap around to the beginning. The
142 * link TRB is always at the last TRB entry.
143 */
144static void dwc3_ep_inc_trb(u8 *index)
145{
146 (*index)++;
147 if (*index == (DWC3_TRB_NUM - 1))
148 *index = 0;
149}
150
151/**
152 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
153 * @dep: The endpoint whose enqueue pointer we're incrementing
154 */
155static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
156{
157 dwc3_ep_inc_trb(&dep->trb_enqueue);
158}
159
160/**
161 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
162 * @dep: The endpoint whose enqueue pointer we're incrementing
163 */
164static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
165{
166 dwc3_ep_inc_trb(&dep->trb_dequeue);
167}
168
169static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
170 struct dwc3_request *req, int status)
171{
172 struct dwc3 *dwc = dep->dwc;
173
174 req->started = false;
175 list_del(&req->list);
176 req->remaining = 0;
177
178 if (req->request.status == -EINPROGRESS)
179 req->request.status = status;
180
181 if (req->trb)
182 usb_gadget_unmap_request_by_dev(dwc->sysdev,
183 &req->request, req->direction);
184
185 req->trb = NULL;
186 trace_dwc3_gadget_giveback(req);
187
188 if (dep->number > 1)
189 pm_runtime_put(dwc->dev);
190}
191
192/**
193 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
194 * @dep: The endpoint to whom the request belongs to
195 * @req: The request we're giving back
196 * @status: completion code for the request
197 *
198 * Must be called with controller's lock held and interrupts disabled. This
199 * function will unmap @req and call its ->complete() callback to notify upper
200 * layers that it has completed.
201 */
202void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
203 int status)
204{
205 struct dwc3 *dwc = dep->dwc;
206
207 dwc3_gadget_del_and_unmap_request(dep, req, status);
208
209 spin_unlock(&dwc->lock);
210 usb_gadget_giveback_request(&dep->endpoint, &req->request);
211 spin_lock(&dwc->lock);
212}
213
214/**
215 * dwc3_send_gadget_generic_command - issue a generic command for the controller
216 * @dwc: pointer to the controller context
217 * @cmd: the command to be issued
218 * @param: command parameter
219 *
220 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
221 * and wait for its completion.
222 */
223int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
224{
225 u32 timeout = 500;
226 int status = 0;
227 int ret = 0;
228 u32 reg;
229
230 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
231 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
232
233 do {
234 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
235 if (!(reg & DWC3_DGCMD_CMDACT)) {
236 status = DWC3_DGCMD_STATUS(reg);
237 if (status)
238 ret = -EINVAL;
239 break;
240 }
241 } while (--timeout);
242
243 if (!timeout) {
244 ret = -ETIMEDOUT;
245 status = -ETIMEDOUT;
246 }
247
248 trace_dwc3_gadget_generic_cmd(cmd, param, status);
249
250 return ret;
251}
252
253static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
254
255/**
256 * dwc3_send_gadget_ep_cmd - issue an endpoint command
257 * @dep: the endpoint to which the command is going to be issued
258 * @cmd: the command to be issued
259 * @params: parameters to the command
260 *
261 * Caller should handle locking. This function will issue @cmd with given
262 * @params to @dep and wait for its completion.
263 */
264int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
265 struct dwc3_gadget_ep_cmd_params *params)
266{
267 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
268 struct dwc3 *dwc = dep->dwc;
269 u32 timeout = 1000;
270 u32 reg;
271
272 int cmd_status = 0;
273 int susphy = false;
274 int ret = -EINVAL;
275
276 /*
277 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
278 * we're issuing an endpoint command, we must check if
279 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
280 *
281 * We will also set SUSPHY bit to what it was before returning as stated
282 * by the same section on Synopsys databook.
283 */
284 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
285 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
286 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
287 susphy = true;
288 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
289 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
290 }
291 }
292
293 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
294 int needs_wakeup;
295
296 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
297 dwc->link_state == DWC3_LINK_STATE_U2 ||
298 dwc->link_state == DWC3_LINK_STATE_U3);
299
300 if (unlikely(needs_wakeup)) {
301 ret = __dwc3_gadget_wakeup(dwc);
302 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
303 ret);
304 }
305 }
306
307 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
308 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
309 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
310
311 /*
312 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
313 * not relying on XferNotReady, we can make use of a special "No
314 * Response Update Transfer" command where we should clear both CmdAct
315 * and CmdIOC bits.
316 *
317 * With this, we don't need to wait for command completion and can
318 * straight away issue further commands to the endpoint.
319 *
320 * NOTICE: We're making an assumption that control endpoints will never
321 * make use of Update Transfer command. This is a safe assumption
322 * because we can never have more than one request at a time with
323 * Control Endpoints. If anybody changes that assumption, this chunk
324 * needs to be updated accordingly.
325 */
326 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
327 !usb_endpoint_xfer_isoc(desc))
328 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
329 else
330 cmd |= DWC3_DEPCMD_CMDACT;
331
332 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
333 do {
334 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
335 if (!(reg & DWC3_DEPCMD_CMDACT)) {
336 cmd_status = DWC3_DEPCMD_STATUS(reg);
337
338 switch (cmd_status) {
339 case 0:
340 ret = 0;
341 break;
342 case DEPEVT_TRANSFER_NO_RESOURCE:
343 ret = -EINVAL;
344 break;
345 case DEPEVT_TRANSFER_BUS_EXPIRY:
346 /*
347 * SW issues START TRANSFER command to
348 * isochronous ep with future frame interval. If
349 * future interval time has already passed when
350 * core receives the command, it will respond
351 * with an error status of 'Bus Expiry'.
352 *
353 * Instead of always returning -EINVAL, let's
354 * give a hint to the gadget driver that this is
355 * the case by returning -EAGAIN.
356 */
357 ret = -EAGAIN;
358 break;
359 default:
360 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
361 }
362
363 break;
364 }
365 } while (--timeout);
366
367 if (timeout == 0) {
368 ret = -ETIMEDOUT;
369 cmd_status = -ETIMEDOUT;
370 }
371
372 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
373
374 if (ret == 0) {
375 switch (DWC3_DEPCMD_CMD(cmd)) {
376 case DWC3_DEPCMD_STARTTRANSFER:
377 dep->flags |= DWC3_EP_TRANSFER_STARTED;
378 break;
379 case DWC3_DEPCMD_ENDTRANSFER:
380 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
381 break;
382 default:
383 /* nothing */
384 break;
385 }
386 }
387
388 if (unlikely(susphy)) {
389 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
390 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
391 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
392 }
393
394 return ret;
395}
396
397static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
398{
399 struct dwc3 *dwc = dep->dwc;
400 struct dwc3_gadget_ep_cmd_params params;
401 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
402
403 /*
404 * As of core revision 2.60a the recommended programming model
405 * is to set the ClearPendIN bit when issuing a Clear Stall EP
406 * command for IN endpoints. This is to prevent an issue where
407 * some (non-compliant) hosts may not send ACK TPs for pending
408 * IN transfers due to a mishandled error condition. Synopsys
409 * STAR 9000614252.
410 */
411 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
412 (dwc->gadget.speed >= USB_SPEED_SUPER))
413 cmd |= DWC3_DEPCMD_CLEARPENDIN;
414
415 memset(¶ms, 0, sizeof(params));
416
417 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
418}
419
420static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
421 struct dwc3_trb *trb)
422{
423 u32 offset = (char *) trb - (char *) dep->trb_pool;
424
425 return dep->trb_pool_dma + offset;
426}
427
428static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
429{
430 struct dwc3 *dwc = dep->dwc;
431
432 if (dep->trb_pool)
433 return 0;
434
435 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
436 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
437 &dep->trb_pool_dma, GFP_KERNEL);
438 if (!dep->trb_pool) {
439 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
440 dep->name);
441 return -ENOMEM;
442 }
443
444 return 0;
445}
446
447static void dwc3_free_trb_pool(struct dwc3_ep *dep)
448{
449 struct dwc3 *dwc = dep->dwc;
450
451 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
452 dep->trb_pool, dep->trb_pool_dma);
453
454 dep->trb_pool = NULL;
455 dep->trb_pool_dma = 0;
456}
457
458static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
459
460/**
461 * dwc3_gadget_start_config - configure ep resources
462 * @dwc: pointer to our controller context structure
463 * @dep: endpoint that is being enabled
464 *
465 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
466 * completion, it will set Transfer Resource for all available endpoints.
467 *
468 * The assignment of transfer resources cannot perfectly follow the data book
469 * due to the fact that the controller driver does not have all knowledge of the
470 * configuration in advance. It is given this information piecemeal by the
471 * composite gadget framework after every SET_CONFIGURATION and
472 * SET_INTERFACE. Trying to follow the databook programming model in this
473 * scenario can cause errors. For two reasons:
474 *
475 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
476 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
477 * incorrect in the scenario of multiple interfaces.
478 *
479 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
480 * endpoint on alt setting (8.1.6).
481 *
482 * The following simplified method is used instead:
483 *
484 * All hardware endpoints can be assigned a transfer resource and this setting
485 * will stay persistent until either a core reset or hibernation. So whenever we
486 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
487 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
488 * guaranteed that there are as many transfer resources as endpoints.
489 *
490 * This function is called for each endpoint when it is being enabled but is
491 * triggered only when called for EP0-out, which always happens first, and which
492 * should only happen in one of the above conditions.
493 */
494static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
495{
496 struct dwc3_gadget_ep_cmd_params params;
497 u32 cmd;
498 int i;
499 int ret;
500
501 if (dep->number)
502 return 0;
503
504 memset(¶ms, 0x00, sizeof(params));
505 cmd = DWC3_DEPCMD_DEPSTARTCFG;
506
507 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
508 if (ret)
509 return ret;
510
511 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
512 struct dwc3_ep *dep = dwc->eps[i];
513
514 if (!dep)
515 continue;
516
517 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
518 if (ret)
519 return ret;
520 }
521
522 return 0;
523}
524
525static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
526 bool modify, bool restore)
527{
528 const struct usb_ss_ep_comp_descriptor *comp_desc;
529 const struct usb_endpoint_descriptor *desc;
530 struct dwc3_gadget_ep_cmd_params params;
531
532 if (dev_WARN_ONCE(dwc->dev, modify && restore,
533 "Can't modify and restore\n"))
534 return -EINVAL;
535
536 comp_desc = dep->endpoint.comp_desc;
537 desc = dep->endpoint.desc;
538
539 memset(¶ms, 0x00, sizeof(params));
540
541 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
542 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
543
544 /* Burst size is only needed in SuperSpeed mode */
545 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
546 u32 burst = dep->endpoint.maxburst;
547 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
548 }
549
550 if (modify) {
551 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
552 } else if (restore) {
553 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
554 params.param2 |= dep->saved_state;
555 } else {
556 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
557 }
558
559 if (usb_endpoint_xfer_control(desc))
560 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
561
562 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
563 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
564
565 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
566 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
567 | DWC3_DEPCFG_STREAM_EVENT_EN;
568 dep->stream_capable = true;
569 }
570
571 if (!usb_endpoint_xfer_control(desc))
572 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
573
574 /*
575 * We are doing 1:1 mapping for endpoints, meaning
576 * Physical Endpoints 2 maps to Logical Endpoint 2 and
577 * so on. We consider the direction bit as part of the physical
578 * endpoint number. So USB endpoint 0x81 is 0x03.
579 */
580 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
581
582 /*
583 * We must use the lower 16 TX FIFOs even though
584 * HW might have more
585 */
586 if (dep->direction)
587 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
588
589 if (desc->bInterval) {
590 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
591 dep->interval = 1 << (desc->bInterval - 1);
592 }
593
594 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
595}
596
597static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
598{
599 struct dwc3_gadget_ep_cmd_params params;
600
601 memset(¶ms, 0x00, sizeof(params));
602
603 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
604
605 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
606 ¶ms);
607}
608
609/**
610 * __dwc3_gadget_ep_enable - initializes a hw endpoint
611 * @dep: endpoint to be initialized
612 * @modify: if true, modify existing endpoint configuration
613 * @restore: if true, restore endpoint configuration from scratch buffer
614 *
615 * Caller should take care of locking. Execute all necessary commands to
616 * initialize a HW endpoint so it can be used by a gadget driver.
617 */
618static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
619 bool modify, bool restore)
620{
621 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
622 struct dwc3 *dwc = dep->dwc;
623
624 u32 reg;
625 int ret;
626
627 if (!(dep->flags & DWC3_EP_ENABLED)) {
628 ret = dwc3_gadget_start_config(dwc, dep);
629 if (ret)
630 return ret;
631 }
632
633 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
634 if (ret)
635 return ret;
636
637 if (!(dep->flags & DWC3_EP_ENABLED)) {
638 struct dwc3_trb *trb_st_hw;
639 struct dwc3_trb *trb_link;
640
641 dep->type = usb_endpoint_type(desc);
642 dep->flags |= DWC3_EP_ENABLED;
643 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
644
645 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
646 reg |= DWC3_DALEPENA_EP(dep->number);
647 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
648
649 init_waitqueue_head(&dep->wait_end_transfer);
650
651 if (usb_endpoint_xfer_control(desc))
652 goto out;
653
654 /* Initialize the TRB ring */
655 dep->trb_dequeue = 0;
656 dep->trb_enqueue = 0;
657 memset(dep->trb_pool, 0,
658 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
659
660 /* Link TRB. The HWO bit is never reset */
661 trb_st_hw = &dep->trb_pool[0];
662
663 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
664 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
665 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
667 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
668 }
669
670 /*
671 * Issue StartTransfer here with no-op TRB so we can always rely on No
672 * Response Update Transfer command.
673 */
674 if (usb_endpoint_xfer_bulk(desc)) {
675 struct dwc3_gadget_ep_cmd_params params;
676 struct dwc3_trb *trb;
677 dma_addr_t trb_dma;
678 u32 cmd;
679
680 memset(¶ms, 0, sizeof(params));
681 trb = &dep->trb_pool[0];
682 trb_dma = dwc3_trb_dma_offset(dep, trb);
683
684 params.param0 = upper_32_bits(trb_dma);
685 params.param1 = lower_32_bits(trb_dma);
686
687 cmd = DWC3_DEPCMD_STARTTRANSFER;
688
689 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
690 if (ret < 0)
691 return ret;
692
693 dep->flags |= DWC3_EP_BUSY;
694
695 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
696 WARN_ON_ONCE(!dep->resource_index);
697 }
698
699
700out:
701 trace_dwc3_gadget_ep_enable(dep);
702
703 return 0;
704}
705
706static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
707static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
708{
709 struct dwc3_request *req;
710
711 dwc3_stop_active_transfer(dwc, dep->number, true);
712
713 /* - giveback all requests to gadget driver */
714 while (!list_empty(&dep->started_list)) {
715 req = next_request(&dep->started_list);
716
717 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
718 }
719
720 while (!list_empty(&dep->pending_list)) {
721 req = next_request(&dep->pending_list);
722
723 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
724 }
725}
726
727/**
728 * __dwc3_gadget_ep_disable - disables a hw endpoint
729 * @dep: the endpoint to disable
730 *
731 * This function undoes what __dwc3_gadget_ep_enable did and also removes
732 * requests which are currently being processed by the hardware and those which
733 * are not yet scheduled.
734 *
735 * Caller should take care of locking.
736 */
737static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
738{
739 struct dwc3 *dwc = dep->dwc;
740 u32 reg;
741
742 trace_dwc3_gadget_ep_disable(dep);
743
744 dwc3_remove_requests(dwc, dep);
745
746 /* make sure HW endpoint isn't stalled */
747 if (dep->flags & DWC3_EP_STALL)
748 __dwc3_gadget_ep_set_halt(dep, 0, false);
749
750 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
751 reg &= ~DWC3_DALEPENA_EP(dep->number);
752 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
753
754 dep->stream_capable = false;
755 dep->type = 0;
756 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
757
758 /* Clear out the ep descriptors for non-ep0 */
759 if (dep->number > 1) {
760 dep->endpoint.comp_desc = NULL;
761 dep->endpoint.desc = NULL;
762 }
763
764 return 0;
765}
766
767/* -------------------------------------------------------------------------- */
768
769static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
770 const struct usb_endpoint_descriptor *desc)
771{
772 return -EINVAL;
773}
774
775static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
776{
777 return -EINVAL;
778}
779
780/* -------------------------------------------------------------------------- */
781
782static int dwc3_gadget_ep_enable(struct usb_ep *ep,
783 const struct usb_endpoint_descriptor *desc)
784{
785 struct dwc3_ep *dep;
786 struct dwc3 *dwc;
787 unsigned long flags;
788 int ret;
789
790 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
791 pr_debug("dwc3: invalid parameters\n");
792 return -EINVAL;
793 }
794
795 if (!desc->wMaxPacketSize) {
796 pr_debug("dwc3: missing wMaxPacketSize\n");
797 return -EINVAL;
798 }
799
800 dep = to_dwc3_ep(ep);
801 dwc = dep->dwc;
802
803 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
804 "%s is already enabled\n",
805 dep->name))
806 return 0;
807
808 spin_lock_irqsave(&dwc->lock, flags);
809 ret = __dwc3_gadget_ep_enable(dep, false, false);
810 spin_unlock_irqrestore(&dwc->lock, flags);
811
812 return ret;
813}
814
815static int dwc3_gadget_ep_disable(struct usb_ep *ep)
816{
817 struct dwc3_ep *dep;
818 struct dwc3 *dwc;
819 unsigned long flags;
820 int ret;
821
822 if (!ep) {
823 pr_debug("dwc3: invalid parameters\n");
824 return -EINVAL;
825 }
826
827 dep = to_dwc3_ep(ep);
828 dwc = dep->dwc;
829
830 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
831 "%s is already disabled\n",
832 dep->name))
833 return 0;
834
835 spin_lock_irqsave(&dwc->lock, flags);
836 ret = __dwc3_gadget_ep_disable(dep);
837 spin_unlock_irqrestore(&dwc->lock, flags);
838
839 return ret;
840}
841
842static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
843 gfp_t gfp_flags)
844{
845 struct dwc3_request *req;
846 struct dwc3_ep *dep = to_dwc3_ep(ep);
847
848 req = kzalloc(sizeof(*req), gfp_flags);
849 if (!req)
850 return NULL;
851
852 req->epnum = dep->number;
853 req->dep = dep;
854
855 dep->allocated_requests++;
856
857 trace_dwc3_alloc_request(req);
858
859 return &req->request;
860}
861
862static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
863 struct usb_request *request)
864{
865 struct dwc3_request *req = to_dwc3_request(request);
866 struct dwc3_ep *dep = to_dwc3_ep(ep);
867
868 dep->allocated_requests--;
869 trace_dwc3_free_request(req);
870 kfree(req);
871}
872
873static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
874
875static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
876 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
877 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
878{
879 struct dwc3 *dwc = dep->dwc;
880 struct usb_gadget *gadget = &dwc->gadget;
881 enum usb_device_speed speed = gadget->speed;
882
883 dwc3_ep_inc_enq(dep);
884
885 trb->size = DWC3_TRB_SIZE_LENGTH(length);
886 trb->bpl = lower_32_bits(dma);
887 trb->bph = upper_32_bits(dma);
888
889 switch (usb_endpoint_type(dep->endpoint.desc)) {
890 case USB_ENDPOINT_XFER_CONTROL:
891 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
892 break;
893
894 case USB_ENDPOINT_XFER_ISOC:
895 if (!node) {
896 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
897
898 /*
899 * USB Specification 2.0 Section 5.9.2 states that: "If
900 * there is only a single transaction in the microframe,
901 * only a DATA0 data packet PID is used. If there are
902 * two transactions per microframe, DATA1 is used for
903 * the first transaction data packet and DATA0 is used
904 * for the second transaction data packet. If there are
905 * three transactions per microframe, DATA2 is used for
906 * the first transaction data packet, DATA1 is used for
907 * the second, and DATA0 is used for the third."
908 *
909 * IOW, we should satisfy the following cases:
910 *
911 * 1) length <= maxpacket
912 * - DATA0
913 *
914 * 2) maxpacket < length <= (2 * maxpacket)
915 * - DATA1, DATA0
916 *
917 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
918 * - DATA2, DATA1, DATA0
919 */
920 if (speed == USB_SPEED_HIGH) {
921 struct usb_ep *ep = &dep->endpoint;
922 unsigned int mult = 2;
923 unsigned int maxp = usb_endpoint_maxp(ep->desc);
924
925 if (length <= (2 * maxp))
926 mult--;
927
928 if (length <= maxp)
929 mult--;
930
931 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
932 }
933 } else {
934 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
935 }
936
937 /* always enable Interrupt on Missed ISOC */
938 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
939 break;
940
941 case USB_ENDPOINT_XFER_BULK:
942 case USB_ENDPOINT_XFER_INT:
943 trb->ctrl = DWC3_TRBCTL_NORMAL;
944 break;
945 default:
946 /*
947 * This is only possible with faulty memory because we
948 * checked it already :)
949 */
950 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
951 usb_endpoint_type(dep->endpoint.desc));
952 }
953
954 /* always enable Continue on Short Packet */
955 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
956 trb->ctrl |= DWC3_TRB_CTRL_CSP;
957
958 if (short_not_ok)
959 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
960 }
961
962 if ((!no_interrupt && !chain) ||
963 (dwc3_calc_trbs_left(dep) == 0))
964 trb->ctrl |= DWC3_TRB_CTRL_IOC;
965
966 if (chain)
967 trb->ctrl |= DWC3_TRB_CTRL_CHN;
968
969 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
970 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
971
972 trb->ctrl |= DWC3_TRB_CTRL_HWO;
973
974 trace_dwc3_prepare_trb(dep, trb);
975}
976
977/**
978 * dwc3_prepare_one_trb - setup one TRB from one request
979 * @dep: endpoint for which this request is prepared
980 * @req: dwc3_request pointer
981 * @chain: should this TRB be chained to the next?
982 * @node: only for isochronous endpoints. First TRB needs different type.
983 */
984static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
985 struct dwc3_request *req, unsigned chain, unsigned node)
986{
987 struct dwc3_trb *trb;
988 unsigned length = req->request.length;
989 unsigned stream_id = req->request.stream_id;
990 unsigned short_not_ok = req->request.short_not_ok;
991 unsigned no_interrupt = req->request.no_interrupt;
992 dma_addr_t dma = req->request.dma;
993
994 trb = &dep->trb_pool[dep->trb_enqueue];
995
996 if (!req->trb) {
997 dwc3_gadget_move_started_request(req);
998 req->trb = trb;
999 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1000 dep->queued_requests++;
1001 }
1002
1003 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1004 stream_id, short_not_ok, no_interrupt);
1005}
1006
1007/**
1008 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1009 * @dep: The endpoint with the TRB ring
1010 * @index: The index of the current TRB in the ring
1011 *
1012 * Returns the TRB prior to the one pointed to by the index. If the
1013 * index is 0, we will wrap backwards, skip the link TRB, and return
1014 * the one just before that.
1015 */
1016static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1017{
1018 u8 tmp = index;
1019
1020 if (!tmp)
1021 tmp = DWC3_TRB_NUM - 1;
1022
1023 return &dep->trb_pool[tmp - 1];
1024}
1025
1026static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1027{
1028 struct dwc3_trb *tmp;
1029 u8 trbs_left;
1030
1031 /*
1032 * If enqueue & dequeue are equal than it is either full or empty.
1033 *
1034 * One way to know for sure is if the TRB right before us has HWO bit
1035 * set or not. If it has, then we're definitely full and can't fit any
1036 * more transfers in our ring.
1037 */
1038 if (dep->trb_enqueue == dep->trb_dequeue) {
1039 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1040 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1041 return 0;
1042
1043 return DWC3_TRB_NUM - 1;
1044 }
1045
1046 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1047 trbs_left &= (DWC3_TRB_NUM - 1);
1048
1049 if (dep->trb_dequeue < dep->trb_enqueue)
1050 trbs_left--;
1051
1052 return trbs_left;
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 for_each_sg(sg, s, req->num_pending_sgs, i) {
1063 unsigned int length = req->request.length;
1064 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1065 unsigned int rem = length % maxp;
1066 unsigned chain = true;
1067
1068 if (sg_is_last(s))
1069 chain = false;
1070
1071 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1072 struct dwc3 *dwc = dep->dwc;
1073 struct dwc3_trb *trb;
1074
1075 req->unaligned = true;
1076
1077 /* prepare normal TRB */
1078 dwc3_prepare_one_trb(dep, req, true, i);
1079
1080 /* Now prepare one extra TRB to align transfer size */
1081 trb = &dep->trb_pool[dep->trb_enqueue];
1082 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1083 maxp - rem, false, 0,
1084 req->request.stream_id,
1085 req->request.short_not_ok,
1086 req->request.no_interrupt);
1087 } else {
1088 dwc3_prepare_one_trb(dep, req, chain, i);
1089 }
1090
1091 if (!dwc3_calc_trbs_left(dep))
1092 break;
1093 }
1094}
1095
1096static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1097 struct dwc3_request *req)
1098{
1099 unsigned int length = req->request.length;
1100 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1101 unsigned int rem = length % maxp;
1102
1103 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1104 struct dwc3 *dwc = dep->dwc;
1105 struct dwc3_trb *trb;
1106
1107 req->unaligned = true;
1108
1109 /* prepare normal TRB */
1110 dwc3_prepare_one_trb(dep, req, true, 0);
1111
1112 /* Now prepare one extra TRB to align transfer size */
1113 trb = &dep->trb_pool[dep->trb_enqueue];
1114 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1115 false, 0, req->request.stream_id,
1116 req->request.short_not_ok,
1117 req->request.no_interrupt);
1118 } else if (req->request.zero && req->request.length &&
1119 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->zero = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to handle ZLP */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1131 false, 0, req->request.stream_id,
1132 req->request.short_not_ok,
1133 req->request.no_interrupt);
1134 } else {
1135 dwc3_prepare_one_trb(dep, req, false, 0);
1136 }
1137}
1138
1139/*
1140 * dwc3_prepare_trbs - setup TRBs from requests
1141 * @dep: endpoint for which requests are being prepared
1142 *
1143 * The function goes through the requests list and sets up TRBs for the
1144 * transfers. The function returns once there are no more TRBs available or
1145 * it runs out of requests.
1146 */
1147static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1148{
1149 struct dwc3_request *req, *n;
1150
1151 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1152
1153 /*
1154 * We can get in a situation where there's a request in the started list
1155 * but there weren't enough TRBs to fully kick it in the first time
1156 * around, so it has been waiting for more TRBs to be freed up.
1157 *
1158 * In that case, we should check if we have a request with pending_sgs
1159 * in the started list and prepare TRBs for that request first,
1160 * otherwise we will prepare TRBs completely out of order and that will
1161 * break things.
1162 */
1163 list_for_each_entry(req, &dep->started_list, list) {
1164 if (req->num_pending_sgs > 0)
1165 dwc3_prepare_one_trb_sg(dep, req);
1166
1167 if (!dwc3_calc_trbs_left(dep))
1168 return;
1169 }
1170
1171 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1172 struct dwc3 *dwc = dep->dwc;
1173 int ret;
1174
1175 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1176 dep->direction);
1177 if (ret)
1178 return;
1179
1180 req->sg = req->request.sg;
1181 req->num_pending_sgs = req->request.num_mapped_sgs;
1182
1183 if (req->num_pending_sgs > 0)
1184 dwc3_prepare_one_trb_sg(dep, req);
1185 else
1186 dwc3_prepare_one_trb_linear(dep, req);
1187
1188 if (!dwc3_calc_trbs_left(dep))
1189 return;
1190 }
1191}
1192
1193static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1194{
1195 struct dwc3_gadget_ep_cmd_params params;
1196 struct dwc3_request *req;
1197 int starting;
1198 int ret;
1199 u32 cmd;
1200
1201 if (!dwc3_calc_trbs_left(dep))
1202 return 0;
1203
1204 starting = !(dep->flags & DWC3_EP_BUSY);
1205
1206 dwc3_prepare_trbs(dep);
1207 req = next_request(&dep->started_list);
1208 if (!req) {
1209 dep->flags |= DWC3_EP_PENDING_REQUEST;
1210 return 0;
1211 }
1212
1213 memset(¶ms, 0, sizeof(params));
1214
1215 if (starting) {
1216 params.param0 = upper_32_bits(req->trb_dma);
1217 params.param1 = lower_32_bits(req->trb_dma);
1218 cmd = DWC3_DEPCMD_STARTTRANSFER;
1219
1220 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1221 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1222 } else {
1223 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1224 DWC3_DEPCMD_PARAM(dep->resource_index);
1225 }
1226
1227 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1228 if (ret < 0) {
1229 /*
1230 * FIXME we need to iterate over the list of requests
1231 * here and stop, unmap, free and del each of the linked
1232 * requests instead of what we do now.
1233 */
1234 if (req->trb)
1235 memset(req->trb, 0, sizeof(struct dwc3_trb));
1236 dep->queued_requests--;
1237 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1238 return ret;
1239 }
1240
1241 dep->flags |= DWC3_EP_BUSY;
1242
1243 if (starting) {
1244 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1245 WARN_ON_ONCE(!dep->resource_index);
1246 }
1247
1248 return 0;
1249}
1250
1251static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1252{
1253 u32 reg;
1254
1255 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1256 return DWC3_DSTS_SOFFN(reg);
1257}
1258
1259static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1260 struct dwc3_ep *dep, u32 cur_uf)
1261{
1262 if (list_empty(&dep->pending_list)) {
1263 dev_info(dwc->dev, "%s: ran out of requests\n",
1264 dep->name);
1265 dep->flags |= DWC3_EP_PENDING_REQUEST;
1266 return;
1267 }
1268
1269 /*
1270 * Schedule the first trb for one interval in the future or at
1271 * least 4 microframes.
1272 */
1273 dep->frame_number = cur_uf + max_t(u32, 4, dep->interval);
1274 __dwc3_gadget_kick_transfer(dep);
1275}
1276
1277static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1278 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1279{
1280 u32 cur_uf, mask;
1281
1282 mask = ~(dep->interval - 1);
1283 cur_uf = event->parameters & mask;
1284
1285 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1286}
1287
1288static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1289{
1290 struct dwc3 *dwc = dep->dwc;
1291
1292 if (!dep->endpoint.desc) {
1293 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1294 dep->name);
1295 return -ESHUTDOWN;
1296 }
1297
1298 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1299 &req->request, req->dep->name))
1300 return -EINVAL;
1301
1302 pm_runtime_get(dwc->dev);
1303
1304 req->request.actual = 0;
1305 req->request.status = -EINPROGRESS;
1306 req->direction = dep->direction;
1307 req->epnum = dep->number;
1308
1309 trace_dwc3_ep_queue(req);
1310
1311 list_add_tail(&req->list, &dep->pending_list);
1312
1313 /*
1314 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1315 * wait for a XferNotReady event so we will know what's the current
1316 * (micro-)frame number.
1317 *
1318 * Without this trick, we are very, very likely gonna get Bus Expiry
1319 * errors which will force us issue EndTransfer command.
1320 */
1321 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1322 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1323 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1324 dwc3_stop_active_transfer(dwc, dep->number, true);
1325 dep->flags = DWC3_EP_ENABLED;
1326 } else {
1327 u32 cur_uf;
1328
1329 cur_uf = __dwc3_gadget_get_frame(dwc);
1330 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1331 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1332 }
1333 return 0;
1334 }
1335
1336 if ((dep->flags & DWC3_EP_BUSY) &&
1337 !(dep->flags & DWC3_EP_MISSED_ISOC))
1338 goto out;
1339
1340 return 0;
1341 }
1342
1343out:
1344 return __dwc3_gadget_kick_transfer(dep);
1345}
1346
1347static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1348 gfp_t gfp_flags)
1349{
1350 struct dwc3_request *req = to_dwc3_request(request);
1351 struct dwc3_ep *dep = to_dwc3_ep(ep);
1352 struct dwc3 *dwc = dep->dwc;
1353
1354 unsigned long flags;
1355
1356 int ret;
1357
1358 spin_lock_irqsave(&dwc->lock, flags);
1359 ret = __dwc3_gadget_ep_queue(dep, req);
1360 spin_unlock_irqrestore(&dwc->lock, flags);
1361
1362 return ret;
1363}
1364
1365static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1366 struct usb_request *request)
1367{
1368 struct dwc3_request *req = to_dwc3_request(request);
1369 struct dwc3_request *r = NULL;
1370
1371 struct dwc3_ep *dep = to_dwc3_ep(ep);
1372 struct dwc3 *dwc = dep->dwc;
1373
1374 unsigned long flags;
1375 int ret = 0;
1376
1377 trace_dwc3_ep_dequeue(req);
1378
1379 spin_lock_irqsave(&dwc->lock, flags);
1380
1381 list_for_each_entry(r, &dep->pending_list, list) {
1382 if (r == req)
1383 break;
1384 }
1385
1386 if (r != req) {
1387 list_for_each_entry(r, &dep->started_list, list) {
1388 if (r == req)
1389 break;
1390 }
1391 if (r == req) {
1392 /* wait until it is processed */
1393 dwc3_stop_active_transfer(dwc, dep->number, true);
1394
1395 /*
1396 * If request was already started, this means we had to
1397 * stop the transfer. With that we also need to ignore
1398 * all TRBs used by the request, however TRBs can only
1399 * be modified after completion of END_TRANSFER
1400 * command. So what we do here is that we wait for
1401 * END_TRANSFER completion and only after that, we jump
1402 * over TRBs by clearing HWO and incrementing dequeue
1403 * pointer.
1404 *
1405 * Note that we have 2 possible types of transfers here:
1406 *
1407 * i) Linear buffer request
1408 * ii) SG-list based request
1409 *
1410 * SG-list based requests will have r->num_pending_sgs
1411 * set to a valid number (> 0). Linear requests,
1412 * normally use a single TRB.
1413 *
1414 * For each of these two cases, if r->unaligned flag is
1415 * set, one extra TRB has been used to align transfer
1416 * size to wMaxPacketSize.
1417 *
1418 * All of these cases need to be taken into
1419 * consideration so we don't mess up our TRB ring
1420 * pointers.
1421 */
1422 wait_event_lock_irq(dep->wait_end_transfer,
1423 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1424 dwc->lock);
1425
1426 if (!r->trb)
1427 goto out0;
1428
1429 if (r->num_pending_sgs) {
1430 struct dwc3_trb *trb;
1431 int i = 0;
1432
1433 for (i = 0; i < r->num_pending_sgs; i++) {
1434 trb = r->trb + i;
1435 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1436 dwc3_ep_inc_deq(dep);
1437 }
1438
1439 if (r->unaligned || r->zero) {
1440 trb = r->trb + r->num_pending_sgs + 1;
1441 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1442 dwc3_ep_inc_deq(dep);
1443 }
1444 } else {
1445 struct dwc3_trb *trb = r->trb;
1446
1447 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1448 dwc3_ep_inc_deq(dep);
1449
1450 if (r->unaligned || r->zero) {
1451 trb = r->trb + 1;
1452 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1453 dwc3_ep_inc_deq(dep);
1454 }
1455 }
1456 goto out1;
1457 }
1458 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1459 request, ep->name);
1460 ret = -EINVAL;
1461 goto out0;
1462 }
1463
1464out1:
1465 /* giveback the request */
1466 dep->queued_requests--;
1467 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1468
1469out0:
1470 spin_unlock_irqrestore(&dwc->lock, flags);
1471
1472 return ret;
1473}
1474
1475int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1476{
1477 struct dwc3_gadget_ep_cmd_params params;
1478 struct dwc3 *dwc = dep->dwc;
1479 int ret;
1480
1481 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1482 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1483 return -EINVAL;
1484 }
1485
1486 memset(¶ms, 0x00, sizeof(params));
1487
1488 if (value) {
1489 struct dwc3_trb *trb;
1490
1491 unsigned transfer_in_flight;
1492 unsigned started;
1493
1494 if (dep->flags & DWC3_EP_STALL)
1495 return 0;
1496
1497 if (dep->number > 1)
1498 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1499 else
1500 trb = &dwc->ep0_trb[dep->trb_enqueue];
1501
1502 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1503 started = !list_empty(&dep->started_list);
1504
1505 if (!protocol && ((dep->direction && transfer_in_flight) ||
1506 (!dep->direction && started))) {
1507 return -EAGAIN;
1508 }
1509
1510 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1511 ¶ms);
1512 if (ret)
1513 dev_err(dwc->dev, "failed to set STALL on %s\n",
1514 dep->name);
1515 else
1516 dep->flags |= DWC3_EP_STALL;
1517 } else {
1518 if (!(dep->flags & DWC3_EP_STALL))
1519 return 0;
1520
1521 ret = dwc3_send_clear_stall_ep_cmd(dep);
1522 if (ret)
1523 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1524 dep->name);
1525 else
1526 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1527 }
1528
1529 return ret;
1530}
1531
1532static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1533{
1534 struct dwc3_ep *dep = to_dwc3_ep(ep);
1535 struct dwc3 *dwc = dep->dwc;
1536
1537 unsigned long flags;
1538
1539 int ret;
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1543 spin_unlock_irqrestore(&dwc->lock, flags);
1544
1545 return ret;
1546}
1547
1548static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1549{
1550 struct dwc3_ep *dep = to_dwc3_ep(ep);
1551 struct dwc3 *dwc = dep->dwc;
1552 unsigned long flags;
1553 int ret;
1554
1555 spin_lock_irqsave(&dwc->lock, flags);
1556 dep->flags |= DWC3_EP_WEDGE;
1557
1558 if (dep->number == 0 || dep->number == 1)
1559 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1560 else
1561 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1562 spin_unlock_irqrestore(&dwc->lock, flags);
1563
1564 return ret;
1565}
1566
1567/* -------------------------------------------------------------------------- */
1568
1569static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1570 .bLength = USB_DT_ENDPOINT_SIZE,
1571 .bDescriptorType = USB_DT_ENDPOINT,
1572 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1573};
1574
1575static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1576 .enable = dwc3_gadget_ep0_enable,
1577 .disable = dwc3_gadget_ep0_disable,
1578 .alloc_request = dwc3_gadget_ep_alloc_request,
1579 .free_request = dwc3_gadget_ep_free_request,
1580 .queue = dwc3_gadget_ep0_queue,
1581 .dequeue = dwc3_gadget_ep_dequeue,
1582 .set_halt = dwc3_gadget_ep0_set_halt,
1583 .set_wedge = dwc3_gadget_ep_set_wedge,
1584};
1585
1586static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1587 .enable = dwc3_gadget_ep_enable,
1588 .disable = dwc3_gadget_ep_disable,
1589 .alloc_request = dwc3_gadget_ep_alloc_request,
1590 .free_request = dwc3_gadget_ep_free_request,
1591 .queue = dwc3_gadget_ep_queue,
1592 .dequeue = dwc3_gadget_ep_dequeue,
1593 .set_halt = dwc3_gadget_ep_set_halt,
1594 .set_wedge = dwc3_gadget_ep_set_wedge,
1595};
1596
1597/* -------------------------------------------------------------------------- */
1598
1599static int dwc3_gadget_get_frame(struct usb_gadget *g)
1600{
1601 struct dwc3 *dwc = gadget_to_dwc(g);
1602
1603 return __dwc3_gadget_get_frame(dwc);
1604}
1605
1606static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1607{
1608 int retries;
1609
1610 int ret;
1611 u32 reg;
1612
1613 u8 link_state;
1614 u8 speed;
1615
1616 /*
1617 * According to the Databook Remote wakeup request should
1618 * be issued only when the device is in early suspend state.
1619 *
1620 * We can check that via USB Link State bits in DSTS register.
1621 */
1622 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1623
1624 speed = reg & DWC3_DSTS_CONNECTSPD;
1625 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1626 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1627 return 0;
1628
1629 link_state = DWC3_DSTS_USBLNKST(reg);
1630
1631 switch (link_state) {
1632 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1633 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1634 break;
1635 default:
1636 return -EINVAL;
1637 }
1638
1639 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1640 if (ret < 0) {
1641 dev_err(dwc->dev, "failed to put link in Recovery\n");
1642 return ret;
1643 }
1644
1645 /* Recent versions do this automatically */
1646 if (dwc->revision < DWC3_REVISION_194A) {
1647 /* write zeroes to Link Change Request */
1648 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1649 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1650 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1651 }
1652
1653 /* poll until Link State changes to ON */
1654 retries = 20000;
1655
1656 while (retries--) {
1657 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1658
1659 /* in HS, means ON */
1660 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1661 break;
1662 }
1663
1664 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1665 dev_err(dwc->dev, "failed to send remote wakeup\n");
1666 return -EINVAL;
1667 }
1668
1669 return 0;
1670}
1671
1672static int dwc3_gadget_wakeup(struct usb_gadget *g)
1673{
1674 struct dwc3 *dwc = gadget_to_dwc(g);
1675 unsigned long flags;
1676 int ret;
1677
1678 spin_lock_irqsave(&dwc->lock, flags);
1679 ret = __dwc3_gadget_wakeup(dwc);
1680 spin_unlock_irqrestore(&dwc->lock, flags);
1681
1682 return ret;
1683}
1684
1685static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1686 int is_selfpowered)
1687{
1688 struct dwc3 *dwc = gadget_to_dwc(g);
1689 unsigned long flags;
1690
1691 spin_lock_irqsave(&dwc->lock, flags);
1692 g->is_selfpowered = !!is_selfpowered;
1693 spin_unlock_irqrestore(&dwc->lock, flags);
1694
1695 return 0;
1696}
1697
1698static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1699{
1700 u32 reg;
1701 u32 timeout = 500;
1702
1703 if (pm_runtime_suspended(dwc->dev))
1704 return 0;
1705
1706 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1707 if (is_on) {
1708 if (dwc->revision <= DWC3_REVISION_187A) {
1709 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1710 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1711 }
1712
1713 if (dwc->revision >= DWC3_REVISION_194A)
1714 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1715 reg |= DWC3_DCTL_RUN_STOP;
1716
1717 if (dwc->has_hibernation)
1718 reg |= DWC3_DCTL_KEEP_CONNECT;
1719
1720 dwc->pullups_connected = true;
1721 } else {
1722 reg &= ~DWC3_DCTL_RUN_STOP;
1723
1724 if (dwc->has_hibernation && !suspend)
1725 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1726
1727 dwc->pullups_connected = false;
1728 }
1729
1730 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1731
1732 do {
1733 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1734 reg &= DWC3_DSTS_DEVCTRLHLT;
1735 } while (--timeout && !(!is_on ^ !reg));
1736
1737 if (!timeout)
1738 return -ETIMEDOUT;
1739
1740 return 0;
1741}
1742
1743static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1744{
1745 struct dwc3 *dwc = gadget_to_dwc(g);
1746 unsigned long flags;
1747 int ret;
1748
1749 is_on = !!is_on;
1750
1751 /*
1752 * Per databook, when we want to stop the gadget, if a control transfer
1753 * is still in process, complete it and get the core into setup phase.
1754 */
1755 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1756 reinit_completion(&dwc->ep0_in_setup);
1757
1758 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1759 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1760 if (ret == 0) {
1761 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1762 return -ETIMEDOUT;
1763 }
1764 }
1765
1766 spin_lock_irqsave(&dwc->lock, flags);
1767 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1768 spin_unlock_irqrestore(&dwc->lock, flags);
1769
1770 return ret;
1771}
1772
1773static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1774{
1775 u32 reg;
1776
1777 /* Enable all but Start and End of Frame IRQs */
1778 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1779 DWC3_DEVTEN_EVNTOVERFLOWEN |
1780 DWC3_DEVTEN_CMDCMPLTEN |
1781 DWC3_DEVTEN_ERRTICERREN |
1782 DWC3_DEVTEN_WKUPEVTEN |
1783 DWC3_DEVTEN_CONNECTDONEEN |
1784 DWC3_DEVTEN_USBRSTEN |
1785 DWC3_DEVTEN_DISCONNEVTEN);
1786
1787 if (dwc->revision < DWC3_REVISION_250A)
1788 reg |= DWC3_DEVTEN_ULSTCNGEN;
1789
1790 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1791}
1792
1793static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1794{
1795 /* mask all interrupts */
1796 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1797}
1798
1799static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1800static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1801
1802/**
1803 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1804 * @dwc: pointer to our context structure
1805 *
1806 * The following looks like complex but it's actually very simple. In order to
1807 * calculate the number of packets we can burst at once on OUT transfers, we're
1808 * gonna use RxFIFO size.
1809 *
1810 * To calculate RxFIFO size we need two numbers:
1811 * MDWIDTH = size, in bits, of the internal memory bus
1812 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1813 *
1814 * Given these two numbers, the formula is simple:
1815 *
1816 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1817 *
1818 * 24 bytes is for 3x SETUP packets
1819 * 16 bytes is a clock domain crossing tolerance
1820 *
1821 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1822 */
1823static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1824{
1825 u32 ram2_depth;
1826 u32 mdwidth;
1827 u32 nump;
1828 u32 reg;
1829
1830 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1831 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1832
1833 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1834 nump = min_t(u32, nump, 16);
1835
1836 /* update NumP */
1837 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1838 reg &= ~DWC3_DCFG_NUMP_MASK;
1839 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1840 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1841}
1842
1843static int __dwc3_gadget_start(struct dwc3 *dwc)
1844{
1845 struct dwc3_ep *dep;
1846 int ret = 0;
1847 u32 reg;
1848
1849 /*
1850 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1851 * the core supports IMOD, disable it.
1852 */
1853 if (dwc->imod_interval) {
1854 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1855 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1856 } else if (dwc3_has_imod(dwc)) {
1857 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1858 }
1859
1860 /*
1861 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1862 * field instead of letting dwc3 itself calculate that automatically.
1863 *
1864 * This way, we maximize the chances that we'll be able to get several
1865 * bursts of data without going through any sort of endpoint throttling.
1866 */
1867 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1868 if (dwc3_is_usb31(dwc))
1869 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1870 else
1871 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1872
1873 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1874
1875 dwc3_gadget_setup_nump(dwc);
1876
1877 /* Start with SuperSpeed Default */
1878 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1879
1880 dep = dwc->eps[0];
1881 ret = __dwc3_gadget_ep_enable(dep, false, false);
1882 if (ret) {
1883 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1884 goto err0;
1885 }
1886
1887 dep = dwc->eps[1];
1888 ret = __dwc3_gadget_ep_enable(dep, false, false);
1889 if (ret) {
1890 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1891 goto err1;
1892 }
1893
1894 /* begin to receive SETUP packets */
1895 dwc->ep0state = EP0_SETUP_PHASE;
1896 dwc3_ep0_out_start(dwc);
1897
1898 dwc3_gadget_enable_irq(dwc);
1899
1900 return 0;
1901
1902err1:
1903 __dwc3_gadget_ep_disable(dwc->eps[0]);
1904
1905err0:
1906 return ret;
1907}
1908
1909static int dwc3_gadget_start(struct usb_gadget *g,
1910 struct usb_gadget_driver *driver)
1911{
1912 struct dwc3 *dwc = gadget_to_dwc(g);
1913 unsigned long flags;
1914 int ret = 0;
1915 int irq;
1916
1917 irq = dwc->irq_gadget;
1918 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1919 IRQF_SHARED, "dwc3", dwc->ev_buf);
1920 if (ret) {
1921 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1922 irq, ret);
1923 goto err0;
1924 }
1925
1926 spin_lock_irqsave(&dwc->lock, flags);
1927 if (dwc->gadget_driver) {
1928 dev_err(dwc->dev, "%s is already bound to %s\n",
1929 dwc->gadget.name,
1930 dwc->gadget_driver->driver.name);
1931 ret = -EBUSY;
1932 goto err1;
1933 }
1934
1935 dwc->gadget_driver = driver;
1936
1937 if (pm_runtime_active(dwc->dev))
1938 __dwc3_gadget_start(dwc);
1939
1940 spin_unlock_irqrestore(&dwc->lock, flags);
1941
1942 return 0;
1943
1944err1:
1945 spin_unlock_irqrestore(&dwc->lock, flags);
1946 free_irq(irq, dwc);
1947
1948err0:
1949 return ret;
1950}
1951
1952static void __dwc3_gadget_stop(struct dwc3 *dwc)
1953{
1954 dwc3_gadget_disable_irq(dwc);
1955 __dwc3_gadget_ep_disable(dwc->eps[0]);
1956 __dwc3_gadget_ep_disable(dwc->eps[1]);
1957}
1958
1959static int dwc3_gadget_stop(struct usb_gadget *g)
1960{
1961 struct dwc3 *dwc = gadget_to_dwc(g);
1962 unsigned long flags;
1963 int epnum;
1964 u32 tmo_eps = 0;
1965
1966 spin_lock_irqsave(&dwc->lock, flags);
1967
1968 if (pm_runtime_suspended(dwc->dev))
1969 goto out;
1970
1971 __dwc3_gadget_stop(dwc);
1972
1973 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1974 struct dwc3_ep *dep = dwc->eps[epnum];
1975 int ret;
1976
1977 if (!dep)
1978 continue;
1979
1980 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1981 continue;
1982
1983 ret = wait_event_interruptible_lock_irq_timeout(dep->wait_end_transfer,
1984 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1985 dwc->lock, msecs_to_jiffies(5));
1986
1987 if (ret <= 0) {
1988 /* Timed out or interrupted! There's nothing much
1989 * we can do so we just log here and print which
1990 * endpoints timed out at the end.
1991 */
1992 tmo_eps |= 1 << epnum;
1993 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
1994 }
1995 }
1996
1997 if (tmo_eps) {
1998 dev_err(dwc->dev,
1999 "end transfer timed out on endpoints 0x%x [bitmap]\n",
2000 tmo_eps);
2001 }
2002
2003out:
2004 dwc->gadget_driver = NULL;
2005 spin_unlock_irqrestore(&dwc->lock, flags);
2006
2007 free_irq(dwc->irq_gadget, dwc->ev_buf);
2008
2009 return 0;
2010}
2011
2012static void dwc3_gadget_set_speed(struct usb_gadget *g,
2013 enum usb_device_speed speed)
2014{
2015 struct dwc3 *dwc = gadget_to_dwc(g);
2016 unsigned long flags;
2017 u32 reg;
2018
2019 spin_lock_irqsave(&dwc->lock, flags);
2020 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2021 reg &= ~(DWC3_DCFG_SPEED_MASK);
2022
2023 /*
2024 * WORKAROUND: DWC3 revision < 2.20a have an issue
2025 * which would cause metastability state on Run/Stop
2026 * bit if we try to force the IP to USB2-only mode.
2027 *
2028 * Because of that, we cannot configure the IP to any
2029 * speed other than the SuperSpeed
2030 *
2031 * Refers to:
2032 *
2033 * STAR#9000525659: Clock Domain Crossing on DCTL in
2034 * USB 2.0 Mode
2035 */
2036 if (dwc->revision < DWC3_REVISION_220A &&
2037 !dwc->dis_metastability_quirk) {
2038 reg |= DWC3_DCFG_SUPERSPEED;
2039 } else {
2040 switch (speed) {
2041 case USB_SPEED_LOW:
2042 reg |= DWC3_DCFG_LOWSPEED;
2043 break;
2044 case USB_SPEED_FULL:
2045 reg |= DWC3_DCFG_FULLSPEED;
2046 break;
2047 case USB_SPEED_HIGH:
2048 reg |= DWC3_DCFG_HIGHSPEED;
2049 break;
2050 case USB_SPEED_SUPER:
2051 reg |= DWC3_DCFG_SUPERSPEED;
2052 break;
2053 case USB_SPEED_SUPER_PLUS:
2054 if (dwc3_is_usb31(dwc))
2055 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2056 else
2057 reg |= DWC3_DCFG_SUPERSPEED;
2058 break;
2059 default:
2060 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2061
2062 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2063 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2064 else
2065 reg |= DWC3_DCFG_SUPERSPEED;
2066 }
2067 }
2068 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2069
2070 spin_unlock_irqrestore(&dwc->lock, flags);
2071}
2072
2073static const struct usb_gadget_ops dwc3_gadget_ops = {
2074 .get_frame = dwc3_gadget_get_frame,
2075 .wakeup = dwc3_gadget_wakeup,
2076 .set_selfpowered = dwc3_gadget_set_selfpowered,
2077 .pullup = dwc3_gadget_pullup,
2078 .udc_start = dwc3_gadget_start,
2079 .udc_stop = dwc3_gadget_stop,
2080 .udc_set_speed = dwc3_gadget_set_speed,
2081};
2082
2083/* -------------------------------------------------------------------------- */
2084
2085static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2086{
2087 struct dwc3_ep *dep;
2088 u8 epnum;
2089
2090 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2091
2092 for (epnum = 0; epnum < total; epnum++) {
2093 bool direction = epnum & 1;
2094 u8 num = epnum >> 1;
2095
2096 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2097 if (!dep)
2098 return -ENOMEM;
2099
2100 dep->dwc = dwc;
2101 dep->number = epnum;
2102 dep->direction = direction;
2103 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2104 dwc->eps[epnum] = dep;
2105
2106 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2107 direction ? "in" : "out");
2108
2109 dep->endpoint.name = dep->name;
2110
2111 if (!(dep->number > 1)) {
2112 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2113 dep->endpoint.comp_desc = NULL;
2114 }
2115
2116 spin_lock_init(&dep->lock);
2117
2118 if (num == 0) {
2119 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2120 dep->endpoint.maxburst = 1;
2121 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2122 if (!direction)
2123 dwc->gadget.ep0 = &dep->endpoint;
2124 } else if (direction) {
2125 int mdwidth;
2126 int kbytes;
2127 int size;
2128 int ret;
2129
2130 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2131 /* MDWIDTH is represented in bits, we need it in bytes */
2132 mdwidth /= 8;
2133
2134 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2135 if (dwc3_is_usb31(dwc))
2136 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2137 else
2138 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2139
2140 /* FIFO Depth is in MDWDITH bytes. Multiply */
2141 size *= mdwidth;
2142
2143 kbytes = size / 1024;
2144 if (kbytes == 0)
2145 kbytes = 1;
2146
2147 /*
2148 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2149 * internal overhead. We don't really know how these are used,
2150 * but documentation say it exists.
2151 */
2152 size -= mdwidth * (kbytes + 1);
2153 size /= kbytes;
2154
2155 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2156
2157 dep->endpoint.max_streams = 15;
2158 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2159 list_add_tail(&dep->endpoint.ep_list,
2160 &dwc->gadget.ep_list);
2161
2162 ret = dwc3_alloc_trb_pool(dep);
2163 if (ret)
2164 return ret;
2165 } else {
2166 int ret;
2167
2168 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2169 dep->endpoint.max_streams = 15;
2170 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2171 list_add_tail(&dep->endpoint.ep_list,
2172 &dwc->gadget.ep_list);
2173
2174 ret = dwc3_alloc_trb_pool(dep);
2175 if (ret)
2176 return ret;
2177 }
2178
2179 if (num == 0) {
2180 dep->endpoint.caps.type_control = true;
2181 } else {
2182 dep->endpoint.caps.type_iso = true;
2183 dep->endpoint.caps.type_bulk = true;
2184 dep->endpoint.caps.type_int = true;
2185 }
2186
2187 dep->endpoint.caps.dir_in = direction;
2188 dep->endpoint.caps.dir_out = !direction;
2189
2190 INIT_LIST_HEAD(&dep->pending_list);
2191 INIT_LIST_HEAD(&dep->started_list);
2192 }
2193
2194 return 0;
2195}
2196
2197static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2198{
2199 struct dwc3_ep *dep;
2200 u8 epnum;
2201
2202 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2203 dep = dwc->eps[epnum];
2204 if (!dep)
2205 continue;
2206 /*
2207 * Physical endpoints 0 and 1 are special; they form the
2208 * bi-directional USB endpoint 0.
2209 *
2210 * For those two physical endpoints, we don't allocate a TRB
2211 * pool nor do we add them the endpoints list. Due to that, we
2212 * shouldn't do these two operations otherwise we would end up
2213 * with all sorts of bugs when removing dwc3.ko.
2214 */
2215 if (epnum != 0 && epnum != 1) {
2216 dwc3_free_trb_pool(dep);
2217 list_del(&dep->endpoint.ep_list);
2218 }
2219
2220 kfree(dep);
2221 }
2222}
2223
2224/* -------------------------------------------------------------------------- */
2225
2226static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2227 struct dwc3_request *req, struct dwc3_trb *trb,
2228 const struct dwc3_event_depevt *event, int status,
2229 int chain)
2230{
2231 unsigned int count;
2232 unsigned int s_pkt = 0;
2233 unsigned int trb_status;
2234
2235 dwc3_ep_inc_deq(dep);
2236
2237 if (req->trb == trb)
2238 dep->queued_requests--;
2239
2240 trace_dwc3_complete_trb(dep, trb);
2241
2242 /*
2243 * If we're in the middle of series of chained TRBs and we
2244 * receive a short transfer along the way, DWC3 will skip
2245 * through all TRBs including the last TRB in the chain (the
2246 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2247 * bit and SW has to do it manually.
2248 *
2249 * We're going to do that here to avoid problems of HW trying
2250 * to use bogus TRBs for transfers.
2251 */
2252 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2253 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2254
2255 /*
2256 * If we're dealing with unaligned size OUT transfer, we will be left
2257 * with one TRB pending in the ring. We need to manually clear HWO bit
2258 * from that TRB.
2259 */
2260 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2261 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2262 return 1;
2263 }
2264
2265 count = trb->size & DWC3_TRB_SIZE_MASK;
2266 req->remaining += count;
2267
2268 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2269 return 1;
2270
2271 if (dep->direction) {
2272 if (count) {
2273 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2274 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2275 /*
2276 * If missed isoc occurred and there is
2277 * no request queued then issue END
2278 * TRANSFER, so that core generates
2279 * next xfernotready and we will issue
2280 * a fresh START TRANSFER.
2281 * If there are still queued request
2282 * then wait, do not issue either END
2283 * or UPDATE TRANSFER, just attach next
2284 * request in pending_list during
2285 * giveback.If any future queued request
2286 * is successfully transferred then we
2287 * will issue UPDATE TRANSFER for all
2288 * request in the pending_list.
2289 */
2290 dep->flags |= DWC3_EP_MISSED_ISOC;
2291 } else {
2292 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2293 dep->name);
2294 status = -ECONNRESET;
2295 }
2296 } else {
2297 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2298 }
2299 } else {
2300 if (count && (event->status & DEPEVT_STATUS_SHORT))
2301 s_pkt = 1;
2302 }
2303
2304 if (s_pkt && !chain)
2305 return 1;
2306
2307 if ((event->status & DEPEVT_STATUS_IOC) &&
2308 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2309 return 1;
2310
2311 return 0;
2312}
2313
2314static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2315 const struct dwc3_event_depevt *event, int status)
2316{
2317 struct dwc3_request *req, *n;
2318 struct dwc3_trb *trb;
2319 bool ioc = false;
2320 int ret = 0;
2321
2322 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2323 unsigned length;
2324 int chain;
2325
2326 length = req->request.length;
2327 chain = req->num_pending_sgs > 0;
2328 if (chain) {
2329 struct scatterlist *sg = req->sg;
2330 struct scatterlist *s;
2331 unsigned int pending = req->num_pending_sgs;
2332 unsigned int i;
2333
2334 for_each_sg(sg, s, pending, i) {
2335 trb = &dep->trb_pool[dep->trb_dequeue];
2336
2337 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2338 break;
2339
2340 req->sg = sg_next(s);
2341 req->num_pending_sgs--;
2342
2343 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2344 event, status, chain);
2345 if (ret)
2346 break;
2347 }
2348 } else {
2349 trb = &dep->trb_pool[dep->trb_dequeue];
2350 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2351 event, status, chain);
2352 }
2353
2354 if (req->unaligned || req->zero) {
2355 trb = &dep->trb_pool[dep->trb_dequeue];
2356 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2357 event, status, false);
2358 req->unaligned = false;
2359 req->zero = false;
2360 }
2361
2362 req->request.actual = length - req->remaining;
2363
2364 if ((req->request.actual < length) && req->num_pending_sgs)
2365 return __dwc3_gadget_kick_transfer(dep);
2366
2367 dwc3_gadget_giveback(dep, req, status);
2368
2369 if (ret) {
2370 if ((event->status & DEPEVT_STATUS_IOC) &&
2371 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2372 ioc = true;
2373 break;
2374 }
2375 }
2376
2377 /*
2378 * Our endpoint might get disabled by another thread during
2379 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2380 * early on so DWC3_EP_BUSY flag gets cleared
2381 */
2382 if (!dep->endpoint.desc)
2383 return 1;
2384
2385 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2386 list_empty(&dep->started_list)) {
2387 if (list_empty(&dep->pending_list)) {
2388 /*
2389 * If there is no entry in request list then do
2390 * not issue END TRANSFER now. Just set PENDING
2391 * flag, so that END TRANSFER is issued when an
2392 * entry is added into request list.
2393 */
2394 dep->flags = DWC3_EP_PENDING_REQUEST;
2395 } else {
2396 dwc3_stop_active_transfer(dwc, dep->number, true);
2397 dep->flags = DWC3_EP_ENABLED;
2398 }
2399 return 1;
2400 }
2401
2402 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2403 return 0;
2404
2405 return 1;
2406}
2407
2408static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2409 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2410{
2411 unsigned status = 0;
2412 int clean_busy;
2413 u32 is_xfer_complete;
2414
2415 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2416
2417 if (event->status & DEPEVT_STATUS_BUSERR)
2418 status = -ECONNRESET;
2419
2420 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2421 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2422 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2423 dep->flags &= ~DWC3_EP_BUSY;
2424
2425 /*
2426 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2427 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2428 */
2429 if (dwc->revision < DWC3_REVISION_183A) {
2430 u32 reg;
2431 int i;
2432
2433 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2434 dep = dwc->eps[i];
2435
2436 if (!(dep->flags & DWC3_EP_ENABLED))
2437 continue;
2438
2439 if (!list_empty(&dep->started_list))
2440 return;
2441 }
2442
2443 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2444 reg |= dwc->u1u2;
2445 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2446
2447 dwc->u1u2 = 0;
2448 }
2449
2450 /*
2451 * Our endpoint might get disabled by another thread during
2452 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2453 * early on so DWC3_EP_BUSY flag gets cleared
2454 */
2455 if (!dep->endpoint.desc)
2456 return;
2457
2458 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc))
2459 __dwc3_gadget_kick_transfer(dep);
2460}
2461
2462static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2463 const struct dwc3_event_depevt *event)
2464{
2465 struct dwc3_ep *dep;
2466 u8 epnum = event->endpoint_number;
2467 u8 cmd;
2468
2469 dep = dwc->eps[epnum];
2470
2471 if (!(dep->flags & DWC3_EP_ENABLED)) {
2472 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2473 return;
2474
2475 /* Handle only EPCMDCMPLT when EP disabled */
2476 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2477 return;
2478 }
2479
2480 if (epnum == 0 || epnum == 1) {
2481 dwc3_ep0_interrupt(dwc, event);
2482 return;
2483 }
2484
2485 switch (event->endpoint_event) {
2486 case DWC3_DEPEVT_XFERCOMPLETE:
2487 dep->resource_index = 0;
2488
2489 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2490 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2491 return;
2492 }
2493
2494 dwc3_endpoint_transfer_complete(dwc, dep, event);
2495 break;
2496 case DWC3_DEPEVT_XFERINPROGRESS:
2497 dwc3_endpoint_transfer_complete(dwc, dep, event);
2498 break;
2499 case DWC3_DEPEVT_XFERNOTREADY:
2500 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2501 dwc3_gadget_start_isoc(dwc, dep, event);
2502 else
2503 __dwc3_gadget_kick_transfer(dep);
2504
2505 break;
2506 case DWC3_DEPEVT_STREAMEVT:
2507 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2508 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2509 dep->name);
2510 return;
2511 }
2512 break;
2513 case DWC3_DEPEVT_EPCMDCMPLT:
2514 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2515
2516 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2517 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2518 wake_up(&dep->wait_end_transfer);
2519 }
2520 break;
2521 case DWC3_DEPEVT_RXTXFIFOEVT:
2522 break;
2523 }
2524}
2525
2526static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2527{
2528 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2529 spin_unlock(&dwc->lock);
2530 dwc->gadget_driver->disconnect(&dwc->gadget);
2531 spin_lock(&dwc->lock);
2532 }
2533}
2534
2535static void dwc3_suspend_gadget(struct dwc3 *dwc)
2536{
2537 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2538 spin_unlock(&dwc->lock);
2539 dwc->gadget_driver->suspend(&dwc->gadget);
2540 spin_lock(&dwc->lock);
2541 }
2542}
2543
2544static void dwc3_resume_gadget(struct dwc3 *dwc)
2545{
2546 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2547 spin_unlock(&dwc->lock);
2548 dwc->gadget_driver->resume(&dwc->gadget);
2549 spin_lock(&dwc->lock);
2550 }
2551}
2552
2553static void dwc3_reset_gadget(struct dwc3 *dwc)
2554{
2555 if (!dwc->gadget_driver)
2556 return;
2557
2558 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2559 spin_unlock(&dwc->lock);
2560 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2561 spin_lock(&dwc->lock);
2562 }
2563}
2564
2565static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2566{
2567 struct dwc3_ep *dep;
2568 struct dwc3_gadget_ep_cmd_params params;
2569 u32 cmd;
2570 int ret;
2571
2572 dep = dwc->eps[epnum];
2573
2574 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2575 !dep->resource_index)
2576 return;
2577
2578 /*
2579 * NOTICE: We are violating what the Databook says about the
2580 * EndTransfer command. Ideally we would _always_ wait for the
2581 * EndTransfer Command Completion IRQ, but that's causing too
2582 * much trouble synchronizing between us and gadget driver.
2583 *
2584 * We have discussed this with the IP Provider and it was
2585 * suggested to giveback all requests here, but give HW some
2586 * extra time to synchronize with the interconnect. We're using
2587 * an arbitrary 100us delay for that.
2588 *
2589 * Note also that a similar handling was tested by Synopsys
2590 * (thanks a lot Paul) and nothing bad has come out of it.
2591 * In short, what we're doing is:
2592 *
2593 * - Issue EndTransfer WITH CMDIOC bit set
2594 * - Wait 100us
2595 *
2596 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2597 * supports a mode to work around the above limitation. The
2598 * software can poll the CMDACT bit in the DEPCMD register
2599 * after issuing a EndTransfer command. This mode is enabled
2600 * by writing GUCTL2[14]. This polling is already done in the
2601 * dwc3_send_gadget_ep_cmd() function so if the mode is
2602 * enabled, the EndTransfer command will have completed upon
2603 * returning from this function and we don't need to delay for
2604 * 100us.
2605 *
2606 * This mode is NOT available on the DWC_usb31 IP.
2607 */
2608
2609 cmd = DWC3_DEPCMD_ENDTRANSFER;
2610 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2611 cmd |= DWC3_DEPCMD_CMDIOC;
2612 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2613 memset(¶ms, 0, sizeof(params));
2614 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2615 WARN_ON_ONCE(ret);
2616 dep->resource_index = 0;
2617 dep->flags &= ~DWC3_EP_BUSY;
2618
2619 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2620 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2621 udelay(100);
2622 }
2623}
2624
2625static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2626{
2627 u32 epnum;
2628
2629 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2630 struct dwc3_ep *dep;
2631 int ret;
2632
2633 dep = dwc->eps[epnum];
2634 if (!dep)
2635 continue;
2636
2637 if (!(dep->flags & DWC3_EP_STALL))
2638 continue;
2639
2640 dep->flags &= ~DWC3_EP_STALL;
2641
2642 ret = dwc3_send_clear_stall_ep_cmd(dep);
2643 WARN_ON_ONCE(ret);
2644 }
2645}
2646
2647static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2648{
2649 int reg;
2650
2651 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2652 reg &= ~DWC3_DCTL_INITU1ENA;
2653 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2654
2655 reg &= ~DWC3_DCTL_INITU2ENA;
2656 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2657
2658 dwc3_disconnect_gadget(dwc);
2659
2660 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2661 dwc->setup_packet_pending = false;
2662 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2663
2664 dwc->connected = false;
2665}
2666
2667static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2668{
2669 u32 reg;
2670
2671 dwc->connected = true;
2672
2673 /*
2674 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2675 * would cause a missing Disconnect Event if there's a
2676 * pending Setup Packet in the FIFO.
2677 *
2678 * There's no suggested workaround on the official Bug
2679 * report, which states that "unless the driver/application
2680 * is doing any special handling of a disconnect event,
2681 * there is no functional issue".
2682 *
2683 * Unfortunately, it turns out that we _do_ some special
2684 * handling of a disconnect event, namely complete all
2685 * pending transfers, notify gadget driver of the
2686 * disconnection, and so on.
2687 *
2688 * Our suggested workaround is to follow the Disconnect
2689 * Event steps here, instead, based on a setup_packet_pending
2690 * flag. Such flag gets set whenever we have a SETUP_PENDING
2691 * status for EP0 TRBs and gets cleared on XferComplete for the
2692 * same endpoint.
2693 *
2694 * Refers to:
2695 *
2696 * STAR#9000466709: RTL: Device : Disconnect event not
2697 * generated if setup packet pending in FIFO
2698 */
2699 if (dwc->revision < DWC3_REVISION_188A) {
2700 if (dwc->setup_packet_pending)
2701 dwc3_gadget_disconnect_interrupt(dwc);
2702 }
2703
2704 dwc3_reset_gadget(dwc);
2705
2706 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2707 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2708 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2709 dwc->test_mode = false;
2710 dwc3_clear_stall_all_ep(dwc);
2711
2712 /* Reset device address to zero */
2713 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2714 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2715 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2716}
2717
2718static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2719{
2720 struct dwc3_ep *dep;
2721 int ret;
2722 u32 reg;
2723 u8 speed;
2724
2725 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2726 speed = reg & DWC3_DSTS_CONNECTSPD;
2727 dwc->speed = speed;
2728
2729 /*
2730 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2731 * each time on Connect Done.
2732 *
2733 * Currently we always use the reset value. If any platform
2734 * wants to set this to a different value, we need to add a
2735 * setting and update GCTL.RAMCLKSEL here.
2736 */
2737
2738 switch (speed) {
2739 case DWC3_DSTS_SUPERSPEED_PLUS:
2740 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2741 dwc->gadget.ep0->maxpacket = 512;
2742 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2743 break;
2744 case DWC3_DSTS_SUPERSPEED:
2745 /*
2746 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2747 * would cause a missing USB3 Reset event.
2748 *
2749 * In such situations, we should force a USB3 Reset
2750 * event by calling our dwc3_gadget_reset_interrupt()
2751 * routine.
2752 *
2753 * Refers to:
2754 *
2755 * STAR#9000483510: RTL: SS : USB3 reset event may
2756 * not be generated always when the link enters poll
2757 */
2758 if (dwc->revision < DWC3_REVISION_190A)
2759 dwc3_gadget_reset_interrupt(dwc);
2760
2761 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2762 dwc->gadget.ep0->maxpacket = 512;
2763 dwc->gadget.speed = USB_SPEED_SUPER;
2764 break;
2765 case DWC3_DSTS_HIGHSPEED:
2766 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2767 dwc->gadget.ep0->maxpacket = 64;
2768 dwc->gadget.speed = USB_SPEED_HIGH;
2769 break;
2770 case DWC3_DSTS_FULLSPEED:
2771 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2772 dwc->gadget.ep0->maxpacket = 64;
2773 dwc->gadget.speed = USB_SPEED_FULL;
2774 break;
2775 case DWC3_DSTS_LOWSPEED:
2776 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2777 dwc->gadget.ep0->maxpacket = 8;
2778 dwc->gadget.speed = USB_SPEED_LOW;
2779 break;
2780 }
2781
2782 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2783
2784 /* Enable USB2 LPM Capability */
2785
2786 if ((dwc->revision > DWC3_REVISION_194A) &&
2787 (speed != DWC3_DSTS_SUPERSPEED) &&
2788 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2789 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2790 reg |= DWC3_DCFG_LPM_CAP;
2791 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2792
2793 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2794 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2795
2796 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2797
2798 /*
2799 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2800 * DCFG.LPMCap is set, core responses with an ACK and the
2801 * BESL value in the LPM token is less than or equal to LPM
2802 * NYET threshold.
2803 */
2804 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2805 && dwc->has_lpm_erratum,
2806 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2807
2808 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2809 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2810
2811 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2812 } else {
2813 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2814 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2815 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2816 }
2817
2818 dep = dwc->eps[0];
2819 ret = __dwc3_gadget_ep_enable(dep, true, false);
2820 if (ret) {
2821 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2822 return;
2823 }
2824
2825 dep = dwc->eps[1];
2826 ret = __dwc3_gadget_ep_enable(dep, true, false);
2827 if (ret) {
2828 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2829 return;
2830 }
2831
2832 /*
2833 * Configure PHY via GUSB3PIPECTLn if required.
2834 *
2835 * Update GTXFIFOSIZn
2836 *
2837 * In both cases reset values should be sufficient.
2838 */
2839}
2840
2841static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2842{
2843 /*
2844 * TODO take core out of low power mode when that's
2845 * implemented.
2846 */
2847
2848 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2849 spin_unlock(&dwc->lock);
2850 dwc->gadget_driver->resume(&dwc->gadget);
2851 spin_lock(&dwc->lock);
2852 }
2853}
2854
2855static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2856 unsigned int evtinfo)
2857{
2858 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2859 unsigned int pwropt;
2860
2861 /*
2862 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2863 * Hibernation mode enabled which would show up when device detects
2864 * host-initiated U3 exit.
2865 *
2866 * In that case, device will generate a Link State Change Interrupt
2867 * from U3 to RESUME which is only necessary if Hibernation is
2868 * configured in.
2869 *
2870 * There are no functional changes due to such spurious event and we
2871 * just need to ignore it.
2872 *
2873 * Refers to:
2874 *
2875 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2876 * operational mode
2877 */
2878 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2879 if ((dwc->revision < DWC3_REVISION_250A) &&
2880 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2881 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2882 (next == DWC3_LINK_STATE_RESUME)) {
2883 return;
2884 }
2885 }
2886
2887 /*
2888 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2889 * on the link partner, the USB session might do multiple entry/exit
2890 * of low power states before a transfer takes place.
2891 *
2892 * Due to this problem, we might experience lower throughput. The
2893 * suggested workaround is to disable DCTL[12:9] bits if we're
2894 * transitioning from U1/U2 to U0 and enable those bits again
2895 * after a transfer completes and there are no pending transfers
2896 * on any of the enabled endpoints.
2897 *
2898 * This is the first half of that workaround.
2899 *
2900 * Refers to:
2901 *
2902 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2903 * core send LGO_Ux entering U0
2904 */
2905 if (dwc->revision < DWC3_REVISION_183A) {
2906 if (next == DWC3_LINK_STATE_U0) {
2907 u32 u1u2;
2908 u32 reg;
2909
2910 switch (dwc->link_state) {
2911 case DWC3_LINK_STATE_U1:
2912 case DWC3_LINK_STATE_U2:
2913 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2914 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2915 | DWC3_DCTL_ACCEPTU2ENA
2916 | DWC3_DCTL_INITU1ENA
2917 | DWC3_DCTL_ACCEPTU1ENA);
2918
2919 if (!dwc->u1u2)
2920 dwc->u1u2 = reg & u1u2;
2921
2922 reg &= ~u1u2;
2923
2924 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2925 break;
2926 default:
2927 /* do nothing */
2928 break;
2929 }
2930 }
2931 }
2932
2933 switch (next) {
2934 case DWC3_LINK_STATE_U1:
2935 if (dwc->speed == USB_SPEED_SUPER)
2936 dwc3_suspend_gadget(dwc);
2937 break;
2938 case DWC3_LINK_STATE_U2:
2939 case DWC3_LINK_STATE_U3:
2940 dwc3_suspend_gadget(dwc);
2941 break;
2942 case DWC3_LINK_STATE_RESUME:
2943 dwc3_resume_gadget(dwc);
2944 break;
2945 default:
2946 /* do nothing */
2947 break;
2948 }
2949
2950 dwc->link_state = next;
2951}
2952
2953static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2954 unsigned int evtinfo)
2955{
2956 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2957
2958 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2959 dwc3_suspend_gadget(dwc);
2960
2961 dwc->link_state = next;
2962}
2963
2964static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2965 unsigned int evtinfo)
2966{
2967 unsigned int is_ss = evtinfo & BIT(4);
2968
2969 /*
2970 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2971 * have a known issue which can cause USB CV TD.9.23 to fail
2972 * randomly.
2973 *
2974 * Because of this issue, core could generate bogus hibernation
2975 * events which SW needs to ignore.
2976 *
2977 * Refers to:
2978 *
2979 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2980 * Device Fallback from SuperSpeed
2981 */
2982 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2983 return;
2984
2985 /* enter hibernation here */
2986}
2987
2988static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2989 const struct dwc3_event_devt *event)
2990{
2991 switch (event->type) {
2992 case DWC3_DEVICE_EVENT_DISCONNECT:
2993 dwc3_gadget_disconnect_interrupt(dwc);
2994 break;
2995 case DWC3_DEVICE_EVENT_RESET:
2996 dwc3_gadget_reset_interrupt(dwc);
2997 break;
2998 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2999 dwc3_gadget_conndone_interrupt(dwc);
3000 break;
3001 case DWC3_DEVICE_EVENT_WAKEUP:
3002 dwc3_gadget_wakeup_interrupt(dwc);
3003 break;
3004 case DWC3_DEVICE_EVENT_HIBER_REQ:
3005 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3006 "unexpected hibernation event\n"))
3007 break;
3008
3009 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3010 break;
3011 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3012 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3013 break;
3014 case DWC3_DEVICE_EVENT_EOPF:
3015 /* It changed to be suspend event for version 2.30a and above */
3016 if (dwc->revision >= DWC3_REVISION_230A) {
3017 /*
3018 * Ignore suspend event until the gadget enters into
3019 * USB_STATE_CONFIGURED state.
3020 */
3021 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3022 dwc3_gadget_suspend_interrupt(dwc,
3023 event->event_info);
3024 }
3025 break;
3026 case DWC3_DEVICE_EVENT_SOF:
3027 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3028 case DWC3_DEVICE_EVENT_CMD_CMPL:
3029 case DWC3_DEVICE_EVENT_OVERFLOW:
3030 break;
3031 default:
3032 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3033 }
3034}
3035
3036static void dwc3_process_event_entry(struct dwc3 *dwc,
3037 const union dwc3_event *event)
3038{
3039 trace_dwc3_event(event->raw, dwc);
3040
3041 if (!event->type.is_devspec)
3042 dwc3_endpoint_interrupt(dwc, &event->depevt);
3043 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3044 dwc3_gadget_interrupt(dwc, &event->devt);
3045 else
3046 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3047}
3048
3049static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3050{
3051 struct dwc3 *dwc = evt->dwc;
3052 irqreturn_t ret = IRQ_NONE;
3053 int left;
3054 u32 reg;
3055
3056 left = evt->count;
3057
3058 if (!(evt->flags & DWC3_EVENT_PENDING))
3059 return IRQ_NONE;
3060
3061 while (left > 0) {
3062 union dwc3_event event;
3063
3064 event.raw = *(u32 *) (evt->cache + evt->lpos);
3065
3066 dwc3_process_event_entry(dwc, &event);
3067
3068 /*
3069 * FIXME we wrap around correctly to the next entry as
3070 * almost all entries are 4 bytes in size. There is one
3071 * entry which has 12 bytes which is a regular entry
3072 * followed by 8 bytes data. ATM I don't know how
3073 * things are organized if we get next to the a
3074 * boundary so I worry about that once we try to handle
3075 * that.
3076 */
3077 evt->lpos = (evt->lpos + 4) % evt->length;
3078 left -= 4;
3079 }
3080
3081 evt->count = 0;
3082 evt->flags &= ~DWC3_EVENT_PENDING;
3083 ret = IRQ_HANDLED;
3084
3085 /* Unmask interrupt */
3086 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3087 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3088 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3089
3090 if (dwc->imod_interval) {
3091 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3092 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3093 }
3094
3095 return ret;
3096}
3097
3098static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3099{
3100 struct dwc3_event_buffer *evt = _evt;
3101 struct dwc3 *dwc = evt->dwc;
3102 unsigned long flags;
3103 irqreturn_t ret = IRQ_NONE;
3104
3105 spin_lock_irqsave(&dwc->lock, flags);
3106 ret = dwc3_process_event_buf(evt);
3107 spin_unlock_irqrestore(&dwc->lock, flags);
3108
3109 return ret;
3110}
3111
3112static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3113{
3114 struct dwc3 *dwc = evt->dwc;
3115 u32 amount;
3116 u32 count;
3117 u32 reg;
3118
3119 if (pm_runtime_suspended(dwc->dev)) {
3120 pm_runtime_get(dwc->dev);
3121 disable_irq_nosync(dwc->irq_gadget);
3122 dwc->pending_events = true;
3123 return IRQ_HANDLED;
3124 }
3125
3126 /*
3127 * With PCIe legacy interrupt, test shows that top-half irq handler can
3128 * be called again after HW interrupt deassertion. Check if bottom-half
3129 * irq event handler completes before caching new event to prevent
3130 * losing events.
3131 */
3132 if (evt->flags & DWC3_EVENT_PENDING)
3133 return IRQ_HANDLED;
3134
3135 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3136 count &= DWC3_GEVNTCOUNT_MASK;
3137 if (!count)
3138 return IRQ_NONE;
3139
3140 evt->count = count;
3141 evt->flags |= DWC3_EVENT_PENDING;
3142
3143 /* Mask interrupt */
3144 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3145 reg |= DWC3_GEVNTSIZ_INTMASK;
3146 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3147
3148 amount = min(count, evt->length - evt->lpos);
3149 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3150
3151 if (amount < count)
3152 memcpy(evt->cache, evt->buf, count - amount);
3153
3154 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3155
3156 return IRQ_WAKE_THREAD;
3157}
3158
3159static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3160{
3161 struct dwc3_event_buffer *evt = _evt;
3162
3163 return dwc3_check_event_buf(evt);
3164}
3165
3166static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3167{
3168 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3169 int irq;
3170
3171 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3172 if (irq > 0)
3173 goto out;
3174
3175 if (irq == -EPROBE_DEFER)
3176 goto out;
3177
3178 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3179 if (irq > 0)
3180 goto out;
3181
3182 if (irq == -EPROBE_DEFER)
3183 goto out;
3184
3185 irq = platform_get_irq(dwc3_pdev, 0);
3186 if (irq > 0)
3187 goto out;
3188
3189 if (irq != -EPROBE_DEFER)
3190 dev_err(dwc->dev, "missing peripheral IRQ\n");
3191
3192 if (!irq)
3193 irq = -EINVAL;
3194
3195out:
3196 return irq;
3197}
3198
3199/**
3200 * dwc3_gadget_init - initializes gadget related registers
3201 * @dwc: pointer to our controller context structure
3202 *
3203 * Returns 0 on success otherwise negative errno.
3204 */
3205int dwc3_gadget_init(struct dwc3 *dwc)
3206{
3207 int ret;
3208 int irq;
3209
3210 irq = dwc3_gadget_get_irq(dwc);
3211 if (irq < 0) {
3212 ret = irq;
3213 goto err0;
3214 }
3215
3216 dwc->irq_gadget = irq;
3217
3218 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3219 sizeof(*dwc->ep0_trb) * 2,
3220 &dwc->ep0_trb_addr, GFP_KERNEL);
3221 if (!dwc->ep0_trb) {
3222 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3223 ret = -ENOMEM;
3224 goto err0;
3225 }
3226
3227 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3228 if (!dwc->setup_buf) {
3229 ret = -ENOMEM;
3230 goto err1;
3231 }
3232
3233 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3234 &dwc->bounce_addr, GFP_KERNEL);
3235 if (!dwc->bounce) {
3236 ret = -ENOMEM;
3237 goto err2;
3238 }
3239
3240 init_completion(&dwc->ep0_in_setup);
3241
3242 dwc->gadget.ops = &dwc3_gadget_ops;
3243 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3244 dwc->gadget.sg_supported = true;
3245 dwc->gadget.name = "dwc3-gadget";
3246 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3247
3248 /*
3249 * FIXME We might be setting max_speed to <SUPER, however versions
3250 * <2.20a of dwc3 have an issue with metastability (documented
3251 * elsewhere in this driver) which tells us we can't set max speed to
3252 * anything lower than SUPER.
3253 *
3254 * Because gadget.max_speed is only used by composite.c and function
3255 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3256 * to happen so we avoid sending SuperSpeed Capability descriptor
3257 * together with our BOS descriptor as that could confuse host into
3258 * thinking we can handle super speed.
3259 *
3260 * Note that, in fact, we won't even support GetBOS requests when speed
3261 * is less than super speed because we don't have means, yet, to tell
3262 * composite.c that we are USB 2.0 + LPM ECN.
3263 */
3264 if (dwc->revision < DWC3_REVISION_220A &&
3265 !dwc->dis_metastability_quirk)
3266 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3267 dwc->revision);
3268
3269 dwc->gadget.max_speed = dwc->maximum_speed;
3270
3271 /*
3272 * REVISIT: Here we should clear all pending IRQs to be
3273 * sure we're starting from a well known location.
3274 */
3275
3276 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3277 if (ret)
3278 goto err3;
3279
3280 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3281 if (ret) {
3282 dev_err(dwc->dev, "failed to register udc\n");
3283 goto err4;
3284 }
3285
3286 return 0;
3287
3288err4:
3289 dwc3_gadget_free_endpoints(dwc);
3290
3291err3:
3292 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3293 dwc->bounce_addr);
3294
3295err2:
3296 kfree(dwc->setup_buf);
3297
3298err1:
3299 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3300 dwc->ep0_trb, dwc->ep0_trb_addr);
3301
3302err0:
3303 return ret;
3304}
3305
3306/* -------------------------------------------------------------------------- */
3307
3308void dwc3_gadget_exit(struct dwc3 *dwc)
3309{
3310 usb_del_gadget_udc(&dwc->gadget);
3311 dwc3_gadget_free_endpoints(dwc);
3312 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3313 dwc->bounce_addr);
3314 kfree(dwc->setup_buf);
3315 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3316 dwc->ep0_trb, dwc->ep0_trb_addr);
3317}
3318
3319int dwc3_gadget_suspend(struct dwc3 *dwc)
3320{
3321 if (!dwc->gadget_driver)
3322 return 0;
3323
3324 dwc3_gadget_run_stop(dwc, false, false);
3325 dwc3_disconnect_gadget(dwc);
3326 __dwc3_gadget_stop(dwc);
3327
3328 return 0;
3329}
3330
3331int dwc3_gadget_resume(struct dwc3 *dwc)
3332{
3333 int ret;
3334
3335 if (!dwc->gadget_driver)
3336 return 0;
3337
3338 ret = __dwc3_gadget_start(dwc);
3339 if (ret < 0)
3340 goto err0;
3341
3342 ret = dwc3_gadget_run_stop(dwc, true, false);
3343 if (ret < 0)
3344 goto err1;
3345
3346 return 0;
3347
3348err1:
3349 __dwc3_gadget_stop(dwc);
3350
3351err0:
3352 return ret;
3353}
3354
3355void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3356{
3357 if (dwc->pending_events) {
3358 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3359 dwc->pending_events = false;
3360 enable_irq(dwc->irq_gadget);
3361 }
3362}