Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case TEST_J:
50 case TEST_K:
51 case TEST_SE0_NAK:
52 case TEST_PACKET:
53 case TEST_FORCE_EN:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (dwc->revision >= DWC3_REVISION_194A) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117
118 /*
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
121 */
122 if (dwc->revision >= DWC3_REVISION_194A)
123 return 0;
124
125 /* wait for a change in DSTS */
126 retries = 10000;
127 while (--retries) {
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129
130 if (DWC3_DSTS_USBLNKST(reg) == state)
131 return 0;
132
133 udelay(5);
134 }
135
136 return -ETIMEDOUT;
137}
138
139/**
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
142 *
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
146 */
147static void dwc3_ep_inc_trb(u8 *index)
148{
149 (*index)++;
150 if (*index == (DWC3_TRB_NUM - 1))
151 *index = 0;
152}
153
154/**
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
157 */
158static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
159{
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
161}
162
163/**
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
166 */
167static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
168{
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
170}
171
172static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
174{
175 struct dwc3 *dwc = dep->dwc;
176
177 list_del(&req->list);
178 req->remaining = 0;
179 req->needs_extra_trb = false;
180
181 if (req->request.status == -EINPROGRESS)
182 req->request.status = status;
183
184 if (req->trb)
185 usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 &req->request, req->direction);
187
188 req->trb = NULL;
189 trace_dwc3_gadget_giveback(req);
190
191 if (dep->number > 1)
192 pm_runtime_put(dwc->dev);
193}
194
195/**
196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197 * @dep: The endpoint to whom the request belongs to
198 * @req: The request we're giving back
199 * @status: completion code for the request
200 *
201 * Must be called with controller's lock held and interrupts disabled. This
202 * function will unmap @req and call its ->complete() callback to notify upper
203 * layers that it has completed.
204 */
205void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
206 int status)
207{
208 struct dwc3 *dwc = dep->dwc;
209
210 dwc3_gadget_del_and_unmap_request(dep, req, status);
211 req->status = DWC3_REQUEST_STATUS_COMPLETED;
212
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
216}
217
218/**
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
223 *
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
226 */
227int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
228{
229 u32 timeout = 500;
230 int status = 0;
231 int ret = 0;
232 u32 reg;
233
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
236
237 do {
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
241 if (status)
242 ret = -EINVAL;
243 break;
244 }
245 } while (--timeout);
246
247 if (!timeout) {
248 ret = -ETIMEDOUT;
249 status = -ETIMEDOUT;
250 }
251
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
253
254 return ret;
255}
256
257static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
258
259/**
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
264 *
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
267 */
268int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
270{
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
273 u32 timeout = 1000;
274 u32 saved_config = 0;
275 u32 reg;
276
277 int cmd_status = 0;
278 int ret = -EINVAL;
279
280 /*
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
283 * endpoint command.
284 *
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
287 *
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 */
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
295 }
296
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
300 }
301
302 if (saved_config)
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
304 }
305
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
307 int needs_wakeup;
308
309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 dwc->link_state == DWC3_LINK_STATE_U2 ||
311 dwc->link_state == DWC3_LINK_STATE_U3);
312
313 if (unlikely(needs_wakeup)) {
314 ret = __dwc3_gadget_wakeup(dwc);
315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
316 ret);
317 }
318 }
319
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
323
324 /*
325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 * not relying on XferNotReady, we can make use of a special "No
327 * Response Update Transfer" command where we should clear both CmdAct
328 * and CmdIOC bits.
329 *
330 * With this, we don't need to wait for command completion and can
331 * straight away issue further commands to the endpoint.
332 *
333 * NOTICE: We're making an assumption that control endpoints will never
334 * make use of Update Transfer command. This is a safe assumption
335 * because we can never have more than one request at a time with
336 * Control Endpoints. If anybody changes that assumption, this chunk
337 * needs to be updated accordingly.
338 */
339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 !usb_endpoint_xfer_isoc(desc))
341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 else
343 cmd |= DWC3_DEPCMD_CMDACT;
344
345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 do {
347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 cmd_status = DWC3_DEPCMD_STATUS(reg);
350
351 switch (cmd_status) {
352 case 0:
353 ret = 0;
354 break;
355 case DEPEVT_TRANSFER_NO_RESOURCE:
356 ret = -EINVAL;
357 break;
358 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 /*
360 * SW issues START TRANSFER command to
361 * isochronous ep with future frame interval. If
362 * future interval time has already passed when
363 * core receives the command, it will respond
364 * with an error status of 'Bus Expiry'.
365 *
366 * Instead of always returning -EINVAL, let's
367 * give a hint to the gadget driver that this is
368 * the case by returning -EAGAIN.
369 */
370 ret = -EAGAIN;
371 break;
372 default:
373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
374 }
375
376 break;
377 }
378 } while (--timeout);
379
380 if (timeout == 0) {
381 ret = -ETIMEDOUT;
382 cmd_status = -ETIMEDOUT;
383 }
384
385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386
387 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
388 dep->flags |= DWC3_EP_TRANSFER_STARTED;
389 dwc3_gadget_ep_get_transfer_index(dep);
390 }
391
392 if (saved_config) {
393 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 reg |= saved_config;
395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 }
397
398 return ret;
399}
400
401static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402{
403 struct dwc3 *dwc = dep->dwc;
404 struct dwc3_gadget_ep_cmd_params params;
405 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
406
407 /*
408 * As of core revision 2.60a the recommended programming model
409 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 * command for IN endpoints. This is to prevent an issue where
411 * some (non-compliant) hosts may not send ACK TPs for pending
412 * IN transfers due to a mishandled error condition. Synopsys
413 * STAR 9000614252.
414 */
415 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
416 (dwc->gadget.speed >= USB_SPEED_SUPER))
417 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418
419 memset(¶ms, 0, sizeof(params));
420
421 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
422}
423
424static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
425 struct dwc3_trb *trb)
426{
427 u32 offset = (char *) trb - (char *) dep->trb_pool;
428
429 return dep->trb_pool_dma + offset;
430}
431
432static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433{
434 struct dwc3 *dwc = dep->dwc;
435
436 if (dep->trb_pool)
437 return 0;
438
439 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
440 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
441 &dep->trb_pool_dma, GFP_KERNEL);
442 if (!dep->trb_pool) {
443 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
444 dep->name);
445 return -ENOMEM;
446 }
447
448 return 0;
449}
450
451static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452{
453 struct dwc3 *dwc = dep->dwc;
454
455 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 dep->trb_pool, dep->trb_pool_dma);
457
458 dep->trb_pool = NULL;
459 dep->trb_pool_dma = 0;
460}
461
462static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463{
464 struct dwc3_gadget_ep_cmd_params params;
465
466 memset(¶ms, 0x00, sizeof(params));
467
468 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469
470 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 ¶ms);
472}
473
474/**
475 * dwc3_gadget_start_config - configure ep resources
476 * @dep: endpoint that is being enabled
477 *
478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479 * completion, it will set Transfer Resource for all available endpoints.
480 *
481 * The assignment of transfer resources cannot perfectly follow the data book
482 * due to the fact that the controller driver does not have all knowledge of the
483 * configuration in advance. It is given this information piecemeal by the
484 * composite gadget framework after every SET_CONFIGURATION and
485 * SET_INTERFACE. Trying to follow the databook programming model in this
486 * scenario can cause errors. For two reasons:
487 *
488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490 * incorrect in the scenario of multiple interfaces.
491 *
492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493 * endpoint on alt setting (8.1.6).
494 *
495 * The following simplified method is used instead:
496 *
497 * All hardware endpoints can be assigned a transfer resource and this setting
498 * will stay persistent until either a core reset or hibernation. So whenever we
499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501 * guaranteed that there are as many transfer resources as endpoints.
502 *
503 * This function is called for each endpoint when it is being enabled but is
504 * triggered only when called for EP0-out, which always happens first, and which
505 * should only happen in one of the above conditions.
506 */
507static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508{
509 struct dwc3_gadget_ep_cmd_params params;
510 struct dwc3 *dwc;
511 u32 cmd;
512 int i;
513 int ret;
514
515 if (dep->number)
516 return 0;
517
518 memset(¶ms, 0x00, sizeof(params));
519 cmd = DWC3_DEPCMD_DEPSTARTCFG;
520 dwc = dep->dwc;
521
522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
523 if (ret)
524 return ret;
525
526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 struct dwc3_ep *dep = dwc->eps[i];
528
529 if (!dep)
530 continue;
531
532 ret = dwc3_gadget_set_xfer_resource(dep);
533 if (ret)
534 return ret;
535 }
536
537 return 0;
538}
539
540static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541{
542 const struct usb_ss_ep_comp_descriptor *comp_desc;
543 const struct usb_endpoint_descriptor *desc;
544 struct dwc3_gadget_ep_cmd_params params;
545 struct dwc3 *dwc = dep->dwc;
546
547 comp_desc = dep->endpoint.comp_desc;
548 desc = dep->endpoint.desc;
549
550 memset(¶ms, 0x00, sizeof(params));
551
552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554
555 /* Burst size is only needed in SuperSpeed mode */
556 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 u32 burst = dep->endpoint.maxburst;
558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
559 }
560
561 params.param0 |= action;
562 if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 params.param2 |= dep->saved_state;
564
565 if (usb_endpoint_xfer_control(desc))
566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567
568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570
571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 | DWC3_DEPCFG_STREAM_EVENT_EN;
574 dep->stream_capable = true;
575 }
576
577 if (!usb_endpoint_xfer_control(desc))
578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
579
580 /*
581 * We are doing 1:1 mapping for endpoints, meaning
582 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 * so on. We consider the direction bit as part of the physical
584 * endpoint number. So USB endpoint 0x81 is 0x03.
585 */
586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
587
588 /*
589 * We must use the lower 16 TX FIFOs even though
590 * HW might have more
591 */
592 if (dep->direction)
593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594
595 if (desc->bInterval) {
596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 dep->interval = 1 << (desc->bInterval - 1);
598 }
599
600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
601}
602
603/**
604 * __dwc3_gadget_ep_enable - initializes a hw endpoint
605 * @dep: endpoint to be initialized
606 * @action: one of INIT, MODIFY or RESTORE
607 *
608 * Caller should take care of locking. Execute all necessary commands to
609 * initialize a HW endpoint so it can be used by a gadget driver.
610 */
611static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
612{
613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 struct dwc3 *dwc = dep->dwc;
615
616 u32 reg;
617 int ret;
618
619 if (!(dep->flags & DWC3_EP_ENABLED)) {
620 ret = dwc3_gadget_start_config(dep);
621 if (ret)
622 return ret;
623 }
624
625 ret = dwc3_gadget_set_ep_config(dep, action);
626 if (ret)
627 return ret;
628
629 if (!(dep->flags & DWC3_EP_ENABLED)) {
630 struct dwc3_trb *trb_st_hw;
631 struct dwc3_trb *trb_link;
632
633 dep->type = usb_endpoint_type(desc);
634 dep->flags |= DWC3_EP_ENABLED;
635
636 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
637 reg |= DWC3_DALEPENA_EP(dep->number);
638 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
639
640 if (usb_endpoint_xfer_control(desc))
641 goto out;
642
643 /* Initialize the TRB ring */
644 dep->trb_dequeue = 0;
645 dep->trb_enqueue = 0;
646 memset(dep->trb_pool, 0,
647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
648
649 /* Link TRB. The HWO bit is never reset */
650 trb_st_hw = &dep->trb_pool[0];
651
652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
657 }
658
659 /*
660 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 * Response Update Transfer command.
662 */
663 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
664 usb_endpoint_xfer_int(desc)) {
665 struct dwc3_gadget_ep_cmd_params params;
666 struct dwc3_trb *trb;
667 dma_addr_t trb_dma;
668 u32 cmd;
669
670 memset(¶ms, 0, sizeof(params));
671 trb = &dep->trb_pool[0];
672 trb_dma = dwc3_trb_dma_offset(dep, trb);
673
674 params.param0 = upper_32_bits(trb_dma);
675 params.param1 = lower_32_bits(trb_dma);
676
677 cmd = DWC3_DEPCMD_STARTTRANSFER;
678
679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
680 if (ret < 0)
681 return ret;
682 }
683
684out:
685 trace_dwc3_gadget_ep_enable(dep);
686
687 return 0;
688}
689
690static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
691 bool interrupt);
692static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
693{
694 struct dwc3_request *req;
695
696 dwc3_stop_active_transfer(dep, true, false);
697
698 /* - giveback all requests to gadget driver */
699 while (!list_empty(&dep->started_list)) {
700 req = next_request(&dep->started_list);
701
702 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
703 }
704
705 while (!list_empty(&dep->pending_list)) {
706 req = next_request(&dep->pending_list);
707
708 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 }
710
711 while (!list_empty(&dep->cancelled_list)) {
712 req = next_request(&dep->cancelled_list);
713
714 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 }
716}
717
718/**
719 * __dwc3_gadget_ep_disable - disables a hw endpoint
720 * @dep: the endpoint to disable
721 *
722 * This function undoes what __dwc3_gadget_ep_enable did and also removes
723 * requests which are currently being processed by the hardware and those which
724 * are not yet scheduled.
725 *
726 * Caller should take care of locking.
727 */
728static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
729{
730 struct dwc3 *dwc = dep->dwc;
731 u32 reg;
732
733 trace_dwc3_gadget_ep_disable(dep);
734
735 dwc3_remove_requests(dwc, dep);
736
737 /* make sure HW endpoint isn't stalled */
738 if (dep->flags & DWC3_EP_STALL)
739 __dwc3_gadget_ep_set_halt(dep, 0, false);
740
741 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
742 reg &= ~DWC3_DALEPENA_EP(dep->number);
743 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
744
745 dep->stream_capable = false;
746 dep->type = 0;
747 dep->flags = 0;
748
749 /* Clear out the ep descriptors for non-ep0 */
750 if (dep->number > 1) {
751 dep->endpoint.comp_desc = NULL;
752 dep->endpoint.desc = NULL;
753 }
754
755 return 0;
756}
757
758/* -------------------------------------------------------------------------- */
759
760static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
761 const struct usb_endpoint_descriptor *desc)
762{
763 return -EINVAL;
764}
765
766static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767{
768 return -EINVAL;
769}
770
771/* -------------------------------------------------------------------------- */
772
773static int dwc3_gadget_ep_enable(struct usb_ep *ep,
774 const struct usb_endpoint_descriptor *desc)
775{
776 struct dwc3_ep *dep;
777 struct dwc3 *dwc;
778 unsigned long flags;
779 int ret;
780
781 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
782 pr_debug("dwc3: invalid parameters\n");
783 return -EINVAL;
784 }
785
786 if (!desc->wMaxPacketSize) {
787 pr_debug("dwc3: missing wMaxPacketSize\n");
788 return -EINVAL;
789 }
790
791 dep = to_dwc3_ep(ep);
792 dwc = dep->dwc;
793
794 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
795 "%s is already enabled\n",
796 dep->name))
797 return 0;
798
799 spin_lock_irqsave(&dwc->lock, flags);
800 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
801 spin_unlock_irqrestore(&dwc->lock, flags);
802
803 return ret;
804}
805
806static int dwc3_gadget_ep_disable(struct usb_ep *ep)
807{
808 struct dwc3_ep *dep;
809 struct dwc3 *dwc;
810 unsigned long flags;
811 int ret;
812
813 if (!ep) {
814 pr_debug("dwc3: invalid parameters\n");
815 return -EINVAL;
816 }
817
818 dep = to_dwc3_ep(ep);
819 dwc = dep->dwc;
820
821 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
822 "%s is already disabled\n",
823 dep->name))
824 return 0;
825
826 spin_lock_irqsave(&dwc->lock, flags);
827 ret = __dwc3_gadget_ep_disable(dep);
828 spin_unlock_irqrestore(&dwc->lock, flags);
829
830 return ret;
831}
832
833static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 gfp_t gfp_flags)
835{
836 struct dwc3_request *req;
837 struct dwc3_ep *dep = to_dwc3_ep(ep);
838
839 req = kzalloc(sizeof(*req), gfp_flags);
840 if (!req)
841 return NULL;
842
843 req->direction = dep->direction;
844 req->epnum = dep->number;
845 req->dep = dep;
846 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
847
848 trace_dwc3_alloc_request(req);
849
850 return &req->request;
851}
852
853static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
854 struct usb_request *request)
855{
856 struct dwc3_request *req = to_dwc3_request(request);
857
858 trace_dwc3_free_request(req);
859 kfree(req);
860}
861
862/**
863 * dwc3_ep_prev_trb - returns the previous TRB in the ring
864 * @dep: The endpoint with the TRB ring
865 * @index: The index of the current TRB in the ring
866 *
867 * Returns the TRB prior to the one pointed to by the index. If the
868 * index is 0, we will wrap backwards, skip the link TRB, and return
869 * the one just before that.
870 */
871static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872{
873 u8 tmp = index;
874
875 if (!tmp)
876 tmp = DWC3_TRB_NUM - 1;
877
878 return &dep->trb_pool[tmp - 1];
879}
880
881static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
882{
883 struct dwc3_trb *tmp;
884 u8 trbs_left;
885
886 /*
887 * If enqueue & dequeue are equal than it is either full or empty.
888 *
889 * One way to know for sure is if the TRB right before us has HWO bit
890 * set or not. If it has, then we're definitely full and can't fit any
891 * more transfers in our ring.
892 */
893 if (dep->trb_enqueue == dep->trb_dequeue) {
894 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
895 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
896 return 0;
897
898 return DWC3_TRB_NUM - 1;
899 }
900
901 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
902 trbs_left &= (DWC3_TRB_NUM - 1);
903
904 if (dep->trb_dequeue < dep->trb_enqueue)
905 trbs_left--;
906
907 return trbs_left;
908}
909
910static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
911 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
912 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
913{
914 struct dwc3 *dwc = dep->dwc;
915 struct usb_gadget *gadget = &dwc->gadget;
916 enum usb_device_speed speed = gadget->speed;
917
918 trb->size = DWC3_TRB_SIZE_LENGTH(length);
919 trb->bpl = lower_32_bits(dma);
920 trb->bph = upper_32_bits(dma);
921
922 switch (usb_endpoint_type(dep->endpoint.desc)) {
923 case USB_ENDPOINT_XFER_CONTROL:
924 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 break;
926
927 case USB_ENDPOINT_XFER_ISOC:
928 if (!node) {
929 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930
931 /*
932 * USB Specification 2.0 Section 5.9.2 states that: "If
933 * there is only a single transaction in the microframe,
934 * only a DATA0 data packet PID is used. If there are
935 * two transactions per microframe, DATA1 is used for
936 * the first transaction data packet and DATA0 is used
937 * for the second transaction data packet. If there are
938 * three transactions per microframe, DATA2 is used for
939 * the first transaction data packet, DATA1 is used for
940 * the second, and DATA0 is used for the third."
941 *
942 * IOW, we should satisfy the following cases:
943 *
944 * 1) length <= maxpacket
945 * - DATA0
946 *
947 * 2) maxpacket < length <= (2 * maxpacket)
948 * - DATA1, DATA0
949 *
950 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
951 * - DATA2, DATA1, DATA0
952 */
953 if (speed == USB_SPEED_HIGH) {
954 struct usb_ep *ep = &dep->endpoint;
955 unsigned int mult = 2;
956 unsigned int maxp = usb_endpoint_maxp(ep->desc);
957
958 if (length <= (2 * maxp))
959 mult--;
960
961 if (length <= maxp)
962 mult--;
963
964 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 }
966 } else {
967 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 }
969
970 /* always enable Interrupt on Missed ISOC */
971 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 break;
973
974 case USB_ENDPOINT_XFER_BULK:
975 case USB_ENDPOINT_XFER_INT:
976 trb->ctrl = DWC3_TRBCTL_NORMAL;
977 break;
978 default:
979 /*
980 * This is only possible with faulty memory because we
981 * checked it already :)
982 */
983 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
984 usb_endpoint_type(dep->endpoint.desc));
985 }
986
987 /*
988 * Enable Continue on Short Packet
989 * when endpoint is not a stream capable
990 */
991 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
992 if (!dep->stream_capable)
993 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994
995 if (short_not_ok)
996 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 }
998
999 if ((!no_interrupt && !chain) ||
1000 (dwc3_calc_trbs_left(dep) == 1))
1001 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002
1003 if (chain)
1004 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1005
1006 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1007 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008
1009 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1010
1011 dwc3_ep_inc_enq(dep);
1012
1013 trace_dwc3_prepare_trb(dep, trb);
1014}
1015
1016/**
1017 * dwc3_prepare_one_trb - setup one TRB from one request
1018 * @dep: endpoint for which this request is prepared
1019 * @req: dwc3_request pointer
1020 * @chain: should this TRB be chained to the next?
1021 * @node: only for isochronous endpoints. First TRB needs different type.
1022 */
1023static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 struct dwc3_request *req, unsigned chain, unsigned node)
1025{
1026 struct dwc3_trb *trb;
1027 unsigned int length;
1028 dma_addr_t dma;
1029 unsigned stream_id = req->request.stream_id;
1030 unsigned short_not_ok = req->request.short_not_ok;
1031 unsigned no_interrupt = req->request.no_interrupt;
1032
1033 if (req->request.num_sgs > 0) {
1034 length = sg_dma_len(req->start_sg);
1035 dma = sg_dma_address(req->start_sg);
1036 } else {
1037 length = req->request.length;
1038 dma = req->request.dma;
1039 }
1040
1041 trb = &dep->trb_pool[dep->trb_enqueue];
1042
1043 if (!req->trb) {
1044 dwc3_gadget_move_started_request(req);
1045 req->trb = trb;
1046 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047 }
1048
1049 req->num_trbs++;
1050
1051 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 stream_id, short_not_ok, no_interrupt);
1053}
1054
1055static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 struct dwc3_request *req)
1057{
1058 struct scatterlist *sg = req->start_sg;
1059 struct scatterlist *s;
1060 int i;
1061
1062 unsigned int remaining = req->request.num_mapped_sgs
1063 - req->num_queued_sgs;
1064
1065 for_each_sg(sg, s, remaining, i) {
1066 unsigned int length = req->request.length;
1067 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 unsigned int rem = length % maxp;
1069 unsigned chain = true;
1070
1071 if (sg_is_last(s))
1072 chain = false;
1073
1074 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 struct dwc3 *dwc = dep->dwc;
1076 struct dwc3_trb *trb;
1077
1078 req->needs_extra_trb = true;
1079
1080 /* prepare normal TRB */
1081 dwc3_prepare_one_trb(dep, req, true, i);
1082
1083 /* Now prepare one extra TRB to align transfer size */
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1085 req->num_trbs++;
1086 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 maxp - rem, false, 1,
1088 req->request.stream_id,
1089 req->request.short_not_ok,
1090 req->request.no_interrupt);
1091 } else {
1092 dwc3_prepare_one_trb(dep, req, chain, i);
1093 }
1094
1095 /*
1096 * There can be a situation where all sgs in sglist are not
1097 * queued because of insufficient trb number. To handle this
1098 * case, update start_sg to next sg to be queued, so that
1099 * we have free trbs we can continue queuing from where we
1100 * previously stopped
1101 */
1102 if (chain)
1103 req->start_sg = sg_next(s);
1104
1105 req->num_queued_sgs++;
1106
1107 if (!dwc3_calc_trbs_left(dep))
1108 break;
1109 }
1110}
1111
1112static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 struct dwc3_request *req)
1114{
1115 unsigned int length = req->request.length;
1116 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 unsigned int rem = length % maxp;
1118
1119 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 struct dwc3 *dwc = dep->dwc;
1121 struct dwc3_trb *trb;
1122
1123 req->needs_extra_trb = true;
1124
1125 /* prepare normal TRB */
1126 dwc3_prepare_one_trb(dep, req, true, 0);
1127
1128 /* Now prepare one extra TRB to align transfer size */
1129 trb = &dep->trb_pool[dep->trb_enqueue];
1130 req->num_trbs++;
1131 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 false, 1, req->request.stream_id,
1133 req->request.short_not_ok,
1134 req->request.no_interrupt);
1135 } else if (req->request.zero && req->request.length &&
1136 (IS_ALIGNED(req->request.length, maxp))) {
1137 struct dwc3 *dwc = dep->dwc;
1138 struct dwc3_trb *trb;
1139
1140 req->needs_extra_trb = true;
1141
1142 /* prepare normal TRB */
1143 dwc3_prepare_one_trb(dep, req, true, 0);
1144
1145 /* Now prepare one extra TRB to handle ZLP */
1146 trb = &dep->trb_pool[dep->trb_enqueue];
1147 req->num_trbs++;
1148 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 false, 1, req->request.stream_id,
1150 req->request.short_not_ok,
1151 req->request.no_interrupt);
1152 } else {
1153 dwc3_prepare_one_trb(dep, req, false, 0);
1154 }
1155}
1156
1157/*
1158 * dwc3_prepare_trbs - setup TRBs from requests
1159 * @dep: endpoint for which requests are being prepared
1160 *
1161 * The function goes through the requests list and sets up TRBs for the
1162 * transfers. The function returns once there are no more TRBs available or
1163 * it runs out of requests.
1164 */
1165static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1166{
1167 struct dwc3_request *req, *n;
1168
1169 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1170
1171 /*
1172 * We can get in a situation where there's a request in the started list
1173 * but there weren't enough TRBs to fully kick it in the first time
1174 * around, so it has been waiting for more TRBs to be freed up.
1175 *
1176 * In that case, we should check if we have a request with pending_sgs
1177 * in the started list and prepare TRBs for that request first,
1178 * otherwise we will prepare TRBs completely out of order and that will
1179 * break things.
1180 */
1181 list_for_each_entry(req, &dep->started_list, list) {
1182 if (req->num_pending_sgs > 0)
1183 dwc3_prepare_one_trb_sg(dep, req);
1184
1185 if (!dwc3_calc_trbs_left(dep))
1186 return;
1187 }
1188
1189 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 struct dwc3 *dwc = dep->dwc;
1191 int ret;
1192
1193 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1194 dep->direction);
1195 if (ret)
1196 return;
1197
1198 req->sg = req->request.sg;
1199 req->start_sg = req->sg;
1200 req->num_queued_sgs = 0;
1201 req->num_pending_sgs = req->request.num_mapped_sgs;
1202
1203 if (req->num_pending_sgs > 0)
1204 dwc3_prepare_one_trb_sg(dep, req);
1205 else
1206 dwc3_prepare_one_trb_linear(dep, req);
1207
1208 if (!dwc3_calc_trbs_left(dep))
1209 return;
1210 }
1211}
1212
1213static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1214{
1215 struct dwc3_gadget_ep_cmd_params params;
1216 struct dwc3_request *req;
1217 int starting;
1218 int ret;
1219 u32 cmd;
1220
1221 if (!dwc3_calc_trbs_left(dep))
1222 return 0;
1223
1224 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1225
1226 dwc3_prepare_trbs(dep);
1227 req = next_request(&dep->started_list);
1228 if (!req) {
1229 dep->flags |= DWC3_EP_PENDING_REQUEST;
1230 return 0;
1231 }
1232
1233 memset(¶ms, 0, sizeof(params));
1234
1235 if (starting) {
1236 params.param0 = upper_32_bits(req->trb_dma);
1237 params.param1 = lower_32_bits(req->trb_dma);
1238 cmd = DWC3_DEPCMD_STARTTRANSFER;
1239
1240 if (dep->stream_capable)
1241 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1242
1243 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1244 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1245 } else {
1246 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1247 DWC3_DEPCMD_PARAM(dep->resource_index);
1248 }
1249
1250 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1251 if (ret < 0) {
1252 /*
1253 * FIXME we need to iterate over the list of requests
1254 * here and stop, unmap, free and del each of the linked
1255 * requests instead of what we do now.
1256 */
1257 if (req->trb)
1258 memset(req->trb, 0, sizeof(struct dwc3_trb));
1259 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1260 return ret;
1261 }
1262
1263 return 0;
1264}
1265
1266static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267{
1268 u32 reg;
1269
1270 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1271 return DWC3_DSTS_SOFFN(reg);
1272}
1273
1274/**
1275 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1276 * @dep: isoc endpoint
1277 *
1278 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1279 * microframe number reported by the XferNotReady event for the future frame
1280 * number to start the isoc transfer.
1281 *
1282 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1283 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1284 * XferNotReady event are invalid. The driver uses this number to schedule the
1285 * isochronous transfer and passes it to the START TRANSFER command. Because
1286 * this number is invalid, the command may fail. If BIT[15:14] matches the
1287 * internal 16-bit microframe, the START TRANSFER command will pass and the
1288 * transfer will start at the scheduled time, if it is off by 1, the command
1289 * will still pass, but the transfer will start 2 seconds in the future. For all
1290 * other conditions, the START TRANSFER command will fail with bus-expiry.
1291 *
1292 * In order to workaround this issue, we can test for the correct combination of
1293 * BIT[15:14] by sending START TRANSFER commands with different values of
1294 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1295 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1296 * As the result, within the 4 possible combinations for BIT[15:14], there will
1297 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1298 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1299 * value is the correct combination.
1300 *
1301 * Since there are only 4 outcomes and the results are ordered, we can simply
1302 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1303 * deduce the smaller successful combination.
1304 *
1305 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1306 * of BIT[15:14]. The correct combination is as follow:
1307 *
1308 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1309 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1310 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1311 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1312 *
1313 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1314 * endpoints.
1315 */
1316static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1317{
1318 int cmd_status = 0;
1319 bool test0;
1320 bool test1;
1321
1322 while (dep->combo_num < 2) {
1323 struct dwc3_gadget_ep_cmd_params params;
1324 u32 test_frame_number;
1325 u32 cmd;
1326
1327 /*
1328 * Check if we can start isoc transfer on the next interval or
1329 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1330 */
1331 test_frame_number = dep->frame_number & 0x3fff;
1332 test_frame_number |= dep->combo_num << 14;
1333 test_frame_number += max_t(u32, 4, dep->interval);
1334
1335 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1336 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1337
1338 cmd = DWC3_DEPCMD_STARTTRANSFER;
1339 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1340 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1341
1342 /* Redo if some other failure beside bus-expiry is received */
1343 if (cmd_status && cmd_status != -EAGAIN) {
1344 dep->start_cmd_status = 0;
1345 dep->combo_num = 0;
1346 return 0;
1347 }
1348
1349 /* Store the first test status */
1350 if (dep->combo_num == 0)
1351 dep->start_cmd_status = cmd_status;
1352
1353 dep->combo_num++;
1354
1355 /*
1356 * End the transfer if the START_TRANSFER command is successful
1357 * to wait for the next XferNotReady to test the command again
1358 */
1359 if (cmd_status == 0) {
1360 dwc3_stop_active_transfer(dep, true, true);
1361 return 0;
1362 }
1363 }
1364
1365 /* test0 and test1 are both completed at this point */
1366 test0 = (dep->start_cmd_status == 0);
1367 test1 = (cmd_status == 0);
1368
1369 if (!test0 && test1)
1370 dep->combo_num = 1;
1371 else if (!test0 && !test1)
1372 dep->combo_num = 2;
1373 else if (test0 && !test1)
1374 dep->combo_num = 3;
1375 else if (test0 && test1)
1376 dep->combo_num = 0;
1377
1378 dep->frame_number &= 0x3fff;
1379 dep->frame_number |= dep->combo_num << 14;
1380 dep->frame_number += max_t(u32, 4, dep->interval);
1381
1382 /* Reinitialize test variables */
1383 dep->start_cmd_status = 0;
1384 dep->combo_num = 0;
1385
1386 return __dwc3_gadget_kick_transfer(dep);
1387}
1388
1389static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1390{
1391 struct dwc3 *dwc = dep->dwc;
1392 int ret;
1393 int i;
1394
1395 if (list_empty(&dep->pending_list)) {
1396 dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 return -EAGAIN;
1398 }
1399
1400 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1401 (dwc->revision <= DWC3_USB31_REVISION_160A ||
1402 (dwc->revision == DWC3_USB31_REVISION_170A &&
1403 dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1404 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1405
1406 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1407 return dwc3_gadget_start_isoc_quirk(dep);
1408 }
1409
1410 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1411 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1412
1413 ret = __dwc3_gadget_kick_transfer(dep);
1414 if (ret != -EAGAIN)
1415 break;
1416 }
1417
1418 return ret;
1419}
1420
1421static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1422{
1423 struct dwc3 *dwc = dep->dwc;
1424
1425 if (!dep->endpoint.desc) {
1426 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1427 dep->name);
1428 return -ESHUTDOWN;
1429 }
1430
1431 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1432 &req->request, req->dep->name))
1433 return -EINVAL;
1434
1435 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1436 "%s: request %pK already in flight\n",
1437 dep->name, &req->request))
1438 return -EINVAL;
1439
1440 pm_runtime_get(dwc->dev);
1441
1442 req->request.actual = 0;
1443 req->request.status = -EINPROGRESS;
1444
1445 trace_dwc3_ep_queue(req);
1446
1447 list_add_tail(&req->list, &dep->pending_list);
1448 req->status = DWC3_REQUEST_STATUS_QUEUED;
1449
1450 /*
1451 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 * wait for a XferNotReady event so we will know what's the current
1453 * (micro-)frame number.
1454 *
1455 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 * errors which will force us issue EndTransfer command.
1457 */
1458 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1461 return 0;
1462
1463 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 return __dwc3_gadget_start_isoc(dep);
1466 }
1467 }
1468 }
1469
1470 return __dwc3_gadget_kick_transfer(dep);
1471}
1472
1473static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1474 gfp_t gfp_flags)
1475{
1476 struct dwc3_request *req = to_dwc3_request(request);
1477 struct dwc3_ep *dep = to_dwc3_ep(ep);
1478 struct dwc3 *dwc = dep->dwc;
1479
1480 unsigned long flags;
1481
1482 int ret;
1483
1484 spin_lock_irqsave(&dwc->lock, flags);
1485 ret = __dwc3_gadget_ep_queue(dep, req);
1486 spin_unlock_irqrestore(&dwc->lock, flags);
1487
1488 return ret;
1489}
1490
1491static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492{
1493 int i;
1494
1495 /*
1496 * If request was already started, this means we had to
1497 * stop the transfer. With that we also need to ignore
1498 * all TRBs used by the request, however TRBs can only
1499 * be modified after completion of END_TRANSFER
1500 * command. So what we do here is that we wait for
1501 * END_TRANSFER completion and only after that, we jump
1502 * over TRBs by clearing HWO and incrementing dequeue
1503 * pointer.
1504 */
1505 for (i = 0; i < req->num_trbs; i++) {
1506 struct dwc3_trb *trb;
1507
1508 trb = req->trb + i;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1511 }
1512
1513 req->num_trbs = 0;
1514}
1515
1516static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1517{
1518 struct dwc3_request *req;
1519 struct dwc3_request *tmp;
1520
1521 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1522 dwc3_gadget_ep_skip_trbs(dep, req);
1523 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1524 }
1525}
1526
1527static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1528 struct usb_request *request)
1529{
1530 struct dwc3_request *req = to_dwc3_request(request);
1531 struct dwc3_request *r = NULL;
1532
1533 struct dwc3_ep *dep = to_dwc3_ep(ep);
1534 struct dwc3 *dwc = dep->dwc;
1535
1536 unsigned long flags;
1537 int ret = 0;
1538
1539 trace_dwc3_ep_dequeue(req);
1540
1541 spin_lock_irqsave(&dwc->lock, flags);
1542
1543 list_for_each_entry(r, &dep->pending_list, list) {
1544 if (r == req)
1545 break;
1546 }
1547
1548 if (r != req) {
1549 list_for_each_entry(r, &dep->started_list, list) {
1550 if (r == req)
1551 break;
1552 }
1553 if (r == req) {
1554 /* wait until it is processed */
1555 dwc3_stop_active_transfer(dep, true, true);
1556
1557 if (!r->trb)
1558 goto out0;
1559
1560 dwc3_gadget_move_cancelled_request(req);
1561 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1562 goto out0;
1563 else
1564 goto out1;
1565 }
1566 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 request, ep->name);
1568 ret = -EINVAL;
1569 goto out0;
1570 }
1571
1572out1:
1573 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1574
1575out0:
1576 spin_unlock_irqrestore(&dwc->lock, flags);
1577
1578 return ret;
1579}
1580
1581int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1582{
1583 struct dwc3_gadget_ep_cmd_params params;
1584 struct dwc3 *dwc = dep->dwc;
1585 int ret;
1586
1587 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1588 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1589 return -EINVAL;
1590 }
1591
1592 memset(¶ms, 0x00, sizeof(params));
1593
1594 if (value) {
1595 struct dwc3_trb *trb;
1596
1597 unsigned transfer_in_flight;
1598 unsigned started;
1599
1600 if (dep->number > 1)
1601 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1602 else
1603 trb = &dwc->ep0_trb[dep->trb_enqueue];
1604
1605 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1606 started = !list_empty(&dep->started_list);
1607
1608 if (!protocol && ((dep->direction && transfer_in_flight) ||
1609 (!dep->direction && started))) {
1610 return -EAGAIN;
1611 }
1612
1613 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1614 ¶ms);
1615 if (ret)
1616 dev_err(dwc->dev, "failed to set STALL on %s\n",
1617 dep->name);
1618 else
1619 dep->flags |= DWC3_EP_STALL;
1620 } else {
1621
1622 ret = dwc3_send_clear_stall_ep_cmd(dep);
1623 if (ret)
1624 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1625 dep->name);
1626 else
1627 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1628 }
1629
1630 return ret;
1631}
1632
1633static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1634{
1635 struct dwc3_ep *dep = to_dwc3_ep(ep);
1636 struct dwc3 *dwc = dep->dwc;
1637
1638 unsigned long flags;
1639
1640 int ret;
1641
1642 spin_lock_irqsave(&dwc->lock, flags);
1643 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1644 spin_unlock_irqrestore(&dwc->lock, flags);
1645
1646 return ret;
1647}
1648
1649static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1650{
1651 struct dwc3_ep *dep = to_dwc3_ep(ep);
1652 struct dwc3 *dwc = dep->dwc;
1653 unsigned long flags;
1654 int ret;
1655
1656 spin_lock_irqsave(&dwc->lock, flags);
1657 dep->flags |= DWC3_EP_WEDGE;
1658
1659 if (dep->number == 0 || dep->number == 1)
1660 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1661 else
1662 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1663 spin_unlock_irqrestore(&dwc->lock, flags);
1664
1665 return ret;
1666}
1667
1668/* -------------------------------------------------------------------------- */
1669
1670static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1671 .bLength = USB_DT_ENDPOINT_SIZE,
1672 .bDescriptorType = USB_DT_ENDPOINT,
1673 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1674};
1675
1676static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1677 .enable = dwc3_gadget_ep0_enable,
1678 .disable = dwc3_gadget_ep0_disable,
1679 .alloc_request = dwc3_gadget_ep_alloc_request,
1680 .free_request = dwc3_gadget_ep_free_request,
1681 .queue = dwc3_gadget_ep0_queue,
1682 .dequeue = dwc3_gadget_ep_dequeue,
1683 .set_halt = dwc3_gadget_ep0_set_halt,
1684 .set_wedge = dwc3_gadget_ep_set_wedge,
1685};
1686
1687static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1688 .enable = dwc3_gadget_ep_enable,
1689 .disable = dwc3_gadget_ep_disable,
1690 .alloc_request = dwc3_gadget_ep_alloc_request,
1691 .free_request = dwc3_gadget_ep_free_request,
1692 .queue = dwc3_gadget_ep_queue,
1693 .dequeue = dwc3_gadget_ep_dequeue,
1694 .set_halt = dwc3_gadget_ep_set_halt,
1695 .set_wedge = dwc3_gadget_ep_set_wedge,
1696};
1697
1698/* -------------------------------------------------------------------------- */
1699
1700static int dwc3_gadget_get_frame(struct usb_gadget *g)
1701{
1702 struct dwc3 *dwc = gadget_to_dwc(g);
1703
1704 return __dwc3_gadget_get_frame(dwc);
1705}
1706
1707static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708{
1709 int retries;
1710
1711 int ret;
1712 u32 reg;
1713
1714 u8 link_state;
1715 u8 speed;
1716
1717 /*
1718 * According to the Databook Remote wakeup request should
1719 * be issued only when the device is in early suspend state.
1720 *
1721 * We can check that via USB Link State bits in DSTS register.
1722 */
1723 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724
1725 speed = reg & DWC3_DSTS_CONNECTSPD;
1726 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1727 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1728 return 0;
1729
1730 link_state = DWC3_DSTS_USBLNKST(reg);
1731
1732 switch (link_state) {
1733 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1734 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
1740 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1741 if (ret < 0) {
1742 dev_err(dwc->dev, "failed to put link in Recovery\n");
1743 return ret;
1744 }
1745
1746 /* Recent versions do this automatically */
1747 if (dwc->revision < DWC3_REVISION_194A) {
1748 /* write zeroes to Link Change Request */
1749 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1751 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1752 }
1753
1754 /* poll until Link State changes to ON */
1755 retries = 20000;
1756
1757 while (retries--) {
1758 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1759
1760 /* in HS, means ON */
1761 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1762 break;
1763 }
1764
1765 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1766 dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 return -EINVAL;
1768 }
1769
1770 return 0;
1771}
1772
1773static int dwc3_gadget_wakeup(struct usb_gadget *g)
1774{
1775 struct dwc3 *dwc = gadget_to_dwc(g);
1776 unsigned long flags;
1777 int ret;
1778
1779 spin_lock_irqsave(&dwc->lock, flags);
1780 ret = __dwc3_gadget_wakeup(dwc);
1781 spin_unlock_irqrestore(&dwc->lock, flags);
1782
1783 return ret;
1784}
1785
1786static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1787 int is_selfpowered)
1788{
1789 struct dwc3 *dwc = gadget_to_dwc(g);
1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dwc->lock, flags);
1793 g->is_selfpowered = !!is_selfpowered;
1794 spin_unlock_irqrestore(&dwc->lock, flags);
1795
1796 return 0;
1797}
1798
1799static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1800{
1801 u32 reg;
1802 u32 timeout = 500;
1803
1804 if (pm_runtime_suspended(dwc->dev))
1805 return 0;
1806
1807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1808 if (is_on) {
1809 if (dwc->revision <= DWC3_REVISION_187A) {
1810 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1811 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1812 }
1813
1814 if (dwc->revision >= DWC3_REVISION_194A)
1815 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1816 reg |= DWC3_DCTL_RUN_STOP;
1817
1818 if (dwc->has_hibernation)
1819 reg |= DWC3_DCTL_KEEP_CONNECT;
1820
1821 dwc->pullups_connected = true;
1822 } else {
1823 reg &= ~DWC3_DCTL_RUN_STOP;
1824
1825 if (dwc->has_hibernation && !suspend)
1826 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1827
1828 dwc->pullups_connected = false;
1829 }
1830
1831 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832
1833 do {
1834 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1835 reg &= DWC3_DSTS_DEVCTRLHLT;
1836 } while (--timeout && !(!is_on ^ !reg));
1837
1838 if (!timeout)
1839 return -ETIMEDOUT;
1840
1841 return 0;
1842}
1843
1844static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1845{
1846 struct dwc3 *dwc = gadget_to_dwc(g);
1847 unsigned long flags;
1848 int ret;
1849
1850 is_on = !!is_on;
1851
1852 /*
1853 * Per databook, when we want to stop the gadget, if a control transfer
1854 * is still in process, complete it and get the core into setup phase.
1855 */
1856 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1857 reinit_completion(&dwc->ep0_in_setup);
1858
1859 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1860 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1861 if (ret == 0) {
1862 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1863 return -ETIMEDOUT;
1864 }
1865 }
1866
1867 spin_lock_irqsave(&dwc->lock, flags);
1868 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1869 spin_unlock_irqrestore(&dwc->lock, flags);
1870
1871 return ret;
1872}
1873
1874static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1875{
1876 u32 reg;
1877
1878 /* Enable all but Start and End of Frame IRQs */
1879 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1880 DWC3_DEVTEN_EVNTOVERFLOWEN |
1881 DWC3_DEVTEN_CMDCMPLTEN |
1882 DWC3_DEVTEN_ERRTICERREN |
1883 DWC3_DEVTEN_WKUPEVTEN |
1884 DWC3_DEVTEN_CONNECTDONEEN |
1885 DWC3_DEVTEN_USBRSTEN |
1886 DWC3_DEVTEN_DISCONNEVTEN);
1887
1888 if (dwc->revision < DWC3_REVISION_250A)
1889 reg |= DWC3_DEVTEN_ULSTCNGEN;
1890
1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1892}
1893
1894static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1895{
1896 /* mask all interrupts */
1897 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1898}
1899
1900static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1901static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1902
1903/**
1904 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1905 * @dwc: pointer to our context structure
1906 *
1907 * The following looks like complex but it's actually very simple. In order to
1908 * calculate the number of packets we can burst at once on OUT transfers, we're
1909 * gonna use RxFIFO size.
1910 *
1911 * To calculate RxFIFO size we need two numbers:
1912 * MDWIDTH = size, in bits, of the internal memory bus
1913 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1914 *
1915 * Given these two numbers, the formula is simple:
1916 *
1917 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1918 *
1919 * 24 bytes is for 3x SETUP packets
1920 * 16 bytes is a clock domain crossing tolerance
1921 *
1922 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1923 */
1924static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925{
1926 u32 ram2_depth;
1927 u32 mdwidth;
1928 u32 nump;
1929 u32 reg;
1930
1931 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1932 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1933
1934 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1935 nump = min_t(u32, nump, 16);
1936
1937 /* update NumP */
1938 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1939 reg &= ~DWC3_DCFG_NUMP_MASK;
1940 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1941 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1942}
1943
1944static int __dwc3_gadget_start(struct dwc3 *dwc)
1945{
1946 struct dwc3_ep *dep;
1947 int ret = 0;
1948 u32 reg;
1949
1950 /*
1951 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1952 * the core supports IMOD, disable it.
1953 */
1954 if (dwc->imod_interval) {
1955 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1956 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1957 } else if (dwc3_has_imod(dwc)) {
1958 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1959 }
1960
1961 /*
1962 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1963 * field instead of letting dwc3 itself calculate that automatically.
1964 *
1965 * This way, we maximize the chances that we'll be able to get several
1966 * bursts of data without going through any sort of endpoint throttling.
1967 */
1968 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1969 if (dwc3_is_usb31(dwc))
1970 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1971 else
1972 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1973
1974 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1975
1976 dwc3_gadget_setup_nump(dwc);
1977
1978 /* Start with SuperSpeed Default */
1979 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1980
1981 dep = dwc->eps[0];
1982 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1983 if (ret) {
1984 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 goto err0;
1986 }
1987
1988 dep = dwc->eps[1];
1989 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1990 if (ret) {
1991 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1992 goto err1;
1993 }
1994
1995 /* begin to receive SETUP packets */
1996 dwc->ep0state = EP0_SETUP_PHASE;
1997 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1998 dwc3_ep0_out_start(dwc);
1999
2000 dwc3_gadget_enable_irq(dwc);
2001
2002 return 0;
2003
2004err1:
2005 __dwc3_gadget_ep_disable(dwc->eps[0]);
2006
2007err0:
2008 return ret;
2009}
2010
2011static int dwc3_gadget_start(struct usb_gadget *g,
2012 struct usb_gadget_driver *driver)
2013{
2014 struct dwc3 *dwc = gadget_to_dwc(g);
2015 unsigned long flags;
2016 int ret = 0;
2017 int irq;
2018
2019 irq = dwc->irq_gadget;
2020 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2021 IRQF_SHARED, "dwc3", dwc->ev_buf);
2022 if (ret) {
2023 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2024 irq, ret);
2025 goto err0;
2026 }
2027
2028 spin_lock_irqsave(&dwc->lock, flags);
2029 if (dwc->gadget_driver) {
2030 dev_err(dwc->dev, "%s is already bound to %s\n",
2031 dwc->gadget.name,
2032 dwc->gadget_driver->driver.name);
2033 ret = -EBUSY;
2034 goto err1;
2035 }
2036
2037 dwc->gadget_driver = driver;
2038
2039 if (pm_runtime_active(dwc->dev))
2040 __dwc3_gadget_start(dwc);
2041
2042 spin_unlock_irqrestore(&dwc->lock, flags);
2043
2044 return 0;
2045
2046err1:
2047 spin_unlock_irqrestore(&dwc->lock, flags);
2048 free_irq(irq, dwc);
2049
2050err0:
2051 return ret;
2052}
2053
2054static void __dwc3_gadget_stop(struct dwc3 *dwc)
2055{
2056 dwc3_gadget_disable_irq(dwc);
2057 __dwc3_gadget_ep_disable(dwc->eps[0]);
2058 __dwc3_gadget_ep_disable(dwc->eps[1]);
2059}
2060
2061static int dwc3_gadget_stop(struct usb_gadget *g)
2062{
2063 struct dwc3 *dwc = gadget_to_dwc(g);
2064 unsigned long flags;
2065
2066 spin_lock_irqsave(&dwc->lock, flags);
2067
2068 if (pm_runtime_suspended(dwc->dev))
2069 goto out;
2070
2071 __dwc3_gadget_stop(dwc);
2072
2073out:
2074 dwc->gadget_driver = NULL;
2075 spin_unlock_irqrestore(&dwc->lock, flags);
2076
2077 free_irq(dwc->irq_gadget, dwc->ev_buf);
2078
2079 return 0;
2080}
2081
2082static void dwc3_gadget_config_params(struct usb_gadget *g,
2083 struct usb_dcd_config_params *params)
2084{
2085 struct dwc3 *dwc = gadget_to_dwc(g);
2086
2087 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2088 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2089
2090 /* Recommended BESL */
2091 if (!dwc->dis_enblslpm_quirk) {
2092 /*
2093 * If the recommended BESL baseline is 0 or if the BESL deep is
2094 * less than 2, Microsoft's Windows 10 host usb stack will issue
2095 * a usb reset immediately after it receives the extended BOS
2096 * descriptor and the enumeration will fail. To maintain
2097 * compatibility with the Windows' usb stack, let's set the
2098 * recommended BESL baseline to 1 and clamp the BESL deep to be
2099 * within 2 to 15.
2100 */
2101 params->besl_baseline = 1;
2102 if (dwc->is_utmi_l1_suspend)
2103 params->besl_deep =
2104 clamp_t(u8, dwc->hird_threshold, 2, 15);
2105 }
2106
2107 /* U1 Device exit Latency */
2108 if (dwc->dis_u1_entry_quirk)
2109 params->bU1devExitLat = 0;
2110 else
2111 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2112
2113 /* U2 Device exit Latency */
2114 if (dwc->dis_u2_entry_quirk)
2115 params->bU2DevExitLat = 0;
2116 else
2117 params->bU2DevExitLat =
2118 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2119}
2120
2121static void dwc3_gadget_set_speed(struct usb_gadget *g,
2122 enum usb_device_speed speed)
2123{
2124 struct dwc3 *dwc = gadget_to_dwc(g);
2125 unsigned long flags;
2126 u32 reg;
2127
2128 spin_lock_irqsave(&dwc->lock, flags);
2129 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2130 reg &= ~(DWC3_DCFG_SPEED_MASK);
2131
2132 /*
2133 * WORKAROUND: DWC3 revision < 2.20a have an issue
2134 * which would cause metastability state on Run/Stop
2135 * bit if we try to force the IP to USB2-only mode.
2136 *
2137 * Because of that, we cannot configure the IP to any
2138 * speed other than the SuperSpeed
2139 *
2140 * Refers to:
2141 *
2142 * STAR#9000525659: Clock Domain Crossing on DCTL in
2143 * USB 2.0 Mode
2144 */
2145 if (dwc->revision < DWC3_REVISION_220A &&
2146 !dwc->dis_metastability_quirk) {
2147 reg |= DWC3_DCFG_SUPERSPEED;
2148 } else {
2149 switch (speed) {
2150 case USB_SPEED_LOW:
2151 reg |= DWC3_DCFG_LOWSPEED;
2152 break;
2153 case USB_SPEED_FULL:
2154 reg |= DWC3_DCFG_FULLSPEED;
2155 break;
2156 case USB_SPEED_HIGH:
2157 reg |= DWC3_DCFG_HIGHSPEED;
2158 break;
2159 case USB_SPEED_SUPER:
2160 reg |= DWC3_DCFG_SUPERSPEED;
2161 break;
2162 case USB_SPEED_SUPER_PLUS:
2163 if (dwc3_is_usb31(dwc))
2164 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2165 else
2166 reg |= DWC3_DCFG_SUPERSPEED;
2167 break;
2168 default:
2169 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2170
2171 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2172 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2173 else
2174 reg |= DWC3_DCFG_SUPERSPEED;
2175 }
2176 }
2177 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2178
2179 spin_unlock_irqrestore(&dwc->lock, flags);
2180}
2181
2182static const struct usb_gadget_ops dwc3_gadget_ops = {
2183 .get_frame = dwc3_gadget_get_frame,
2184 .wakeup = dwc3_gadget_wakeup,
2185 .set_selfpowered = dwc3_gadget_set_selfpowered,
2186 .pullup = dwc3_gadget_pullup,
2187 .udc_start = dwc3_gadget_start,
2188 .udc_stop = dwc3_gadget_stop,
2189 .udc_set_speed = dwc3_gadget_set_speed,
2190 .get_config_params = dwc3_gadget_config_params,
2191};
2192
2193/* -------------------------------------------------------------------------- */
2194
2195static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2196{
2197 struct dwc3 *dwc = dep->dwc;
2198
2199 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2200 dep->endpoint.maxburst = 1;
2201 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2202 if (!dep->direction)
2203 dwc->gadget.ep0 = &dep->endpoint;
2204
2205 dep->endpoint.caps.type_control = true;
2206
2207 return 0;
2208}
2209
2210static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2211{
2212 struct dwc3 *dwc = dep->dwc;
2213 int mdwidth;
2214 int kbytes;
2215 int size;
2216
2217 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2218 /* MDWIDTH is represented in bits, we need it in bytes */
2219 mdwidth /= 8;
2220
2221 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2222 if (dwc3_is_usb31(dwc))
2223 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2224 else
2225 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2226
2227 /* FIFO Depth is in MDWDITH bytes. Multiply */
2228 size *= mdwidth;
2229
2230 kbytes = size / 1024;
2231 if (kbytes == 0)
2232 kbytes = 1;
2233
2234 /*
2235 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2236 * internal overhead. We don't really know how these are used,
2237 * but documentation say it exists.
2238 */
2239 size -= mdwidth * (kbytes + 1);
2240 size /= kbytes;
2241
2242 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2243
2244 dep->endpoint.max_streams = 15;
2245 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2246 list_add_tail(&dep->endpoint.ep_list,
2247 &dwc->gadget.ep_list);
2248 dep->endpoint.caps.type_iso = true;
2249 dep->endpoint.caps.type_bulk = true;
2250 dep->endpoint.caps.type_int = true;
2251
2252 return dwc3_alloc_trb_pool(dep);
2253}
2254
2255static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2256{
2257 struct dwc3 *dwc = dep->dwc;
2258
2259 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2260 dep->endpoint.max_streams = 15;
2261 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2262 list_add_tail(&dep->endpoint.ep_list,
2263 &dwc->gadget.ep_list);
2264 dep->endpoint.caps.type_iso = true;
2265 dep->endpoint.caps.type_bulk = true;
2266 dep->endpoint.caps.type_int = true;
2267
2268 return dwc3_alloc_trb_pool(dep);
2269}
2270
2271static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2272{
2273 struct dwc3_ep *dep;
2274 bool direction = epnum & 1;
2275 int ret;
2276 u8 num = epnum >> 1;
2277
2278 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2279 if (!dep)
2280 return -ENOMEM;
2281
2282 dep->dwc = dwc;
2283 dep->number = epnum;
2284 dep->direction = direction;
2285 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2286 dwc->eps[epnum] = dep;
2287 dep->combo_num = 0;
2288 dep->start_cmd_status = 0;
2289
2290 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2291 direction ? "in" : "out");
2292
2293 dep->endpoint.name = dep->name;
2294
2295 if (!(dep->number > 1)) {
2296 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2297 dep->endpoint.comp_desc = NULL;
2298 }
2299
2300 if (num == 0)
2301 ret = dwc3_gadget_init_control_endpoint(dep);
2302 else if (direction)
2303 ret = dwc3_gadget_init_in_endpoint(dep);
2304 else
2305 ret = dwc3_gadget_init_out_endpoint(dep);
2306
2307 if (ret)
2308 return ret;
2309
2310 dep->endpoint.caps.dir_in = direction;
2311 dep->endpoint.caps.dir_out = !direction;
2312
2313 INIT_LIST_HEAD(&dep->pending_list);
2314 INIT_LIST_HEAD(&dep->started_list);
2315 INIT_LIST_HEAD(&dep->cancelled_list);
2316
2317 return 0;
2318}
2319
2320static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2321{
2322 u8 epnum;
2323
2324 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2325
2326 for (epnum = 0; epnum < total; epnum++) {
2327 int ret;
2328
2329 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2330 if (ret)
2331 return ret;
2332 }
2333
2334 return 0;
2335}
2336
2337static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2338{
2339 struct dwc3_ep *dep;
2340 u8 epnum;
2341
2342 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343 dep = dwc->eps[epnum];
2344 if (!dep)
2345 continue;
2346 /*
2347 * Physical endpoints 0 and 1 are special; they form the
2348 * bi-directional USB endpoint 0.
2349 *
2350 * For those two physical endpoints, we don't allocate a TRB
2351 * pool nor do we add them the endpoints list. Due to that, we
2352 * shouldn't do these two operations otherwise we would end up
2353 * with all sorts of bugs when removing dwc3.ko.
2354 */
2355 if (epnum != 0 && epnum != 1) {
2356 dwc3_free_trb_pool(dep);
2357 list_del(&dep->endpoint.ep_list);
2358 }
2359
2360 kfree(dep);
2361 }
2362}
2363
2364/* -------------------------------------------------------------------------- */
2365
2366static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2367 struct dwc3_request *req, struct dwc3_trb *trb,
2368 const struct dwc3_event_depevt *event, int status, int chain)
2369{
2370 unsigned int count;
2371
2372 dwc3_ep_inc_deq(dep);
2373
2374 trace_dwc3_complete_trb(dep, trb);
2375 req->num_trbs--;
2376
2377 /*
2378 * If we're in the middle of series of chained TRBs and we
2379 * receive a short transfer along the way, DWC3 will skip
2380 * through all TRBs including the last TRB in the chain (the
2381 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2382 * bit and SW has to do it manually.
2383 *
2384 * We're going to do that here to avoid problems of HW trying
2385 * to use bogus TRBs for transfers.
2386 */
2387 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2388 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2389
2390 /*
2391 * For isochronous transfers, the first TRB in a service interval must
2392 * have the Isoc-First type. Track and report its interval frame number.
2393 */
2394 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2395 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2396 unsigned int frame_number;
2397
2398 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2399 frame_number &= ~(dep->interval - 1);
2400 req->request.frame_number = frame_number;
2401 }
2402
2403 /*
2404 * If we're dealing with unaligned size OUT transfer, we will be left
2405 * with one TRB pending in the ring. We need to manually clear HWO bit
2406 * from that TRB.
2407 */
2408
2409 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2410 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2411 return 1;
2412 }
2413
2414 count = trb->size & DWC3_TRB_SIZE_MASK;
2415 req->remaining += count;
2416
2417 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2418 return 1;
2419
2420 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2421 return 1;
2422
2423 if (event->status & DEPEVT_STATUS_IOC)
2424 return 1;
2425
2426 return 0;
2427}
2428
2429static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2430 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2431 int status)
2432{
2433 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2434 struct scatterlist *sg = req->sg;
2435 struct scatterlist *s;
2436 unsigned int pending = req->num_pending_sgs;
2437 unsigned int i;
2438 int ret = 0;
2439
2440 for_each_sg(sg, s, pending, i) {
2441 trb = &dep->trb_pool[dep->trb_dequeue];
2442
2443 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2444 break;
2445
2446 req->sg = sg_next(s);
2447 req->num_pending_sgs--;
2448
2449 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2450 trb, event, status, true);
2451 if (ret)
2452 break;
2453 }
2454
2455 return ret;
2456}
2457
2458static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2459 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2460 int status)
2461{
2462 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2463
2464 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2465 event, status, false);
2466}
2467
2468static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2469{
2470 return req->request.actual == req->request.length;
2471}
2472
2473static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2474 const struct dwc3_event_depevt *event,
2475 struct dwc3_request *req, int status)
2476{
2477 int ret;
2478
2479 if (req->num_pending_sgs)
2480 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2481 status);
2482 else
2483 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2484 status);
2485
2486 if (req->needs_extra_trb) {
2487 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2488 status);
2489 req->needs_extra_trb = false;
2490 }
2491
2492 req->request.actual = req->request.length - req->remaining;
2493
2494 if (!dwc3_gadget_ep_request_completed(req) &&
2495 req->num_pending_sgs) {
2496 __dwc3_gadget_kick_transfer(dep);
2497 goto out;
2498 }
2499
2500 dwc3_gadget_giveback(dep, req, status);
2501
2502out:
2503 return ret;
2504}
2505
2506static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2507 const struct dwc3_event_depevt *event, int status)
2508{
2509 struct dwc3_request *req;
2510 struct dwc3_request *tmp;
2511
2512 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2513 int ret;
2514
2515 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2516 req, status);
2517 if (ret)
2518 break;
2519 }
2520}
2521
2522static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2523 const struct dwc3_event_depevt *event)
2524{
2525 dep->frame_number = event->parameters;
2526}
2527
2528static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2529 const struct dwc3_event_depevt *event)
2530{
2531 struct dwc3 *dwc = dep->dwc;
2532 unsigned status = 0;
2533 bool stop = false;
2534
2535 dwc3_gadget_endpoint_frame_from_event(dep, event);
2536
2537 if (event->status & DEPEVT_STATUS_BUSERR)
2538 status = -ECONNRESET;
2539
2540 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2541 status = -EXDEV;
2542
2543 if (list_empty(&dep->started_list))
2544 stop = true;
2545 }
2546
2547 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2548
2549 if (stop) {
2550 dwc3_stop_active_transfer(dep, true, true);
2551 dep->flags = DWC3_EP_ENABLED;
2552 }
2553
2554 /*
2555 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2556 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2557 */
2558 if (dwc->revision < DWC3_REVISION_183A) {
2559 u32 reg;
2560 int i;
2561
2562 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2563 dep = dwc->eps[i];
2564
2565 if (!(dep->flags & DWC3_EP_ENABLED))
2566 continue;
2567
2568 if (!list_empty(&dep->started_list))
2569 return;
2570 }
2571
2572 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2573 reg |= dwc->u1u2;
2574 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2575
2576 dwc->u1u2 = 0;
2577 }
2578}
2579
2580static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2581 const struct dwc3_event_depevt *event)
2582{
2583 dwc3_gadget_endpoint_frame_from_event(dep, event);
2584 (void) __dwc3_gadget_start_isoc(dep);
2585}
2586
2587static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2588 const struct dwc3_event_depevt *event)
2589{
2590 struct dwc3_ep *dep;
2591 u8 epnum = event->endpoint_number;
2592 u8 cmd;
2593
2594 dep = dwc->eps[epnum];
2595
2596 if (!(dep->flags & DWC3_EP_ENABLED)) {
2597 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2598 return;
2599
2600 /* Handle only EPCMDCMPLT when EP disabled */
2601 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2602 return;
2603 }
2604
2605 if (epnum == 0 || epnum == 1) {
2606 dwc3_ep0_interrupt(dwc, event);
2607 return;
2608 }
2609
2610 switch (event->endpoint_event) {
2611 case DWC3_DEPEVT_XFERINPROGRESS:
2612 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2613 break;
2614 case DWC3_DEPEVT_XFERNOTREADY:
2615 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2616 break;
2617 case DWC3_DEPEVT_EPCMDCMPLT:
2618 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2619
2620 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2621 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2622 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2623 }
2624 break;
2625 case DWC3_DEPEVT_STREAMEVT:
2626 case DWC3_DEPEVT_XFERCOMPLETE:
2627 case DWC3_DEPEVT_RXTXFIFOEVT:
2628 break;
2629 }
2630}
2631
2632static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2633{
2634 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2635 spin_unlock(&dwc->lock);
2636 dwc->gadget_driver->disconnect(&dwc->gadget);
2637 spin_lock(&dwc->lock);
2638 }
2639}
2640
2641static void dwc3_suspend_gadget(struct dwc3 *dwc)
2642{
2643 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2644 spin_unlock(&dwc->lock);
2645 dwc->gadget_driver->suspend(&dwc->gadget);
2646 spin_lock(&dwc->lock);
2647 }
2648}
2649
2650static void dwc3_resume_gadget(struct dwc3 *dwc)
2651{
2652 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2653 spin_unlock(&dwc->lock);
2654 dwc->gadget_driver->resume(&dwc->gadget);
2655 spin_lock(&dwc->lock);
2656 }
2657}
2658
2659static void dwc3_reset_gadget(struct dwc3 *dwc)
2660{
2661 if (!dwc->gadget_driver)
2662 return;
2663
2664 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2665 spin_unlock(&dwc->lock);
2666 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2667 spin_lock(&dwc->lock);
2668 }
2669}
2670
2671static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2672 bool interrupt)
2673{
2674 struct dwc3 *dwc = dep->dwc;
2675 struct dwc3_gadget_ep_cmd_params params;
2676 u32 cmd;
2677 int ret;
2678
2679 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2680 return;
2681
2682 /*
2683 * NOTICE: We are violating what the Databook says about the
2684 * EndTransfer command. Ideally we would _always_ wait for the
2685 * EndTransfer Command Completion IRQ, but that's causing too
2686 * much trouble synchronizing between us and gadget driver.
2687 *
2688 * We have discussed this with the IP Provider and it was
2689 * suggested to giveback all requests here, but give HW some
2690 * extra time to synchronize with the interconnect. We're using
2691 * an arbitrary 100us delay for that.
2692 *
2693 * Note also that a similar handling was tested by Synopsys
2694 * (thanks a lot Paul) and nothing bad has come out of it.
2695 * In short, what we're doing is:
2696 *
2697 * - Issue EndTransfer WITH CMDIOC bit set
2698 * - Wait 100us
2699 *
2700 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2701 * supports a mode to work around the above limitation. The
2702 * software can poll the CMDACT bit in the DEPCMD register
2703 * after issuing a EndTransfer command. This mode is enabled
2704 * by writing GUCTL2[14]. This polling is already done in the
2705 * dwc3_send_gadget_ep_cmd() function so if the mode is
2706 * enabled, the EndTransfer command will have completed upon
2707 * returning from this function and we don't need to delay for
2708 * 100us.
2709 *
2710 * This mode is NOT available on the DWC_usb31 IP.
2711 */
2712
2713 cmd = DWC3_DEPCMD_ENDTRANSFER;
2714 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2715 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2716 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2717 memset(¶ms, 0, sizeof(params));
2718 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2719 WARN_ON_ONCE(ret);
2720 dep->resource_index = 0;
2721
2722 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2723 udelay(100);
2724}
2725
2726static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2727{
2728 u32 epnum;
2729
2730 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2731 struct dwc3_ep *dep;
2732 int ret;
2733
2734 dep = dwc->eps[epnum];
2735 if (!dep)
2736 continue;
2737
2738 if (!(dep->flags & DWC3_EP_STALL))
2739 continue;
2740
2741 dep->flags &= ~DWC3_EP_STALL;
2742
2743 ret = dwc3_send_clear_stall_ep_cmd(dep);
2744 WARN_ON_ONCE(ret);
2745 }
2746}
2747
2748static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2749{
2750 int reg;
2751
2752 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2753 reg &= ~DWC3_DCTL_INITU1ENA;
2754 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2755
2756 reg &= ~DWC3_DCTL_INITU2ENA;
2757 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2758
2759 dwc3_disconnect_gadget(dwc);
2760
2761 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2762 dwc->setup_packet_pending = false;
2763 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2764
2765 dwc->connected = false;
2766}
2767
2768static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2769{
2770 u32 reg;
2771
2772 dwc->connected = true;
2773
2774 /*
2775 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2776 * would cause a missing Disconnect Event if there's a
2777 * pending Setup Packet in the FIFO.
2778 *
2779 * There's no suggested workaround on the official Bug
2780 * report, which states that "unless the driver/application
2781 * is doing any special handling of a disconnect event,
2782 * there is no functional issue".
2783 *
2784 * Unfortunately, it turns out that we _do_ some special
2785 * handling of a disconnect event, namely complete all
2786 * pending transfers, notify gadget driver of the
2787 * disconnection, and so on.
2788 *
2789 * Our suggested workaround is to follow the Disconnect
2790 * Event steps here, instead, based on a setup_packet_pending
2791 * flag. Such flag gets set whenever we have a SETUP_PENDING
2792 * status for EP0 TRBs and gets cleared on XferComplete for the
2793 * same endpoint.
2794 *
2795 * Refers to:
2796 *
2797 * STAR#9000466709: RTL: Device : Disconnect event not
2798 * generated if setup packet pending in FIFO
2799 */
2800 if (dwc->revision < DWC3_REVISION_188A) {
2801 if (dwc->setup_packet_pending)
2802 dwc3_gadget_disconnect_interrupt(dwc);
2803 }
2804
2805 dwc3_reset_gadget(dwc);
2806
2807 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2808 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2809 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2810 dwc->test_mode = false;
2811 dwc3_clear_stall_all_ep(dwc);
2812
2813 /* Reset device address to zero */
2814 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2815 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2816 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2817}
2818
2819static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2820{
2821 struct dwc3_ep *dep;
2822 int ret;
2823 u32 reg;
2824 u8 speed;
2825
2826 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2827 speed = reg & DWC3_DSTS_CONNECTSPD;
2828 dwc->speed = speed;
2829
2830 /*
2831 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2832 * each time on Connect Done.
2833 *
2834 * Currently we always use the reset value. If any platform
2835 * wants to set this to a different value, we need to add a
2836 * setting and update GCTL.RAMCLKSEL here.
2837 */
2838
2839 switch (speed) {
2840 case DWC3_DSTS_SUPERSPEED_PLUS:
2841 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2842 dwc->gadget.ep0->maxpacket = 512;
2843 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2844 break;
2845 case DWC3_DSTS_SUPERSPEED:
2846 /*
2847 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2848 * would cause a missing USB3 Reset event.
2849 *
2850 * In such situations, we should force a USB3 Reset
2851 * event by calling our dwc3_gadget_reset_interrupt()
2852 * routine.
2853 *
2854 * Refers to:
2855 *
2856 * STAR#9000483510: RTL: SS : USB3 reset event may
2857 * not be generated always when the link enters poll
2858 */
2859 if (dwc->revision < DWC3_REVISION_190A)
2860 dwc3_gadget_reset_interrupt(dwc);
2861
2862 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2863 dwc->gadget.ep0->maxpacket = 512;
2864 dwc->gadget.speed = USB_SPEED_SUPER;
2865 break;
2866 case DWC3_DSTS_HIGHSPEED:
2867 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2868 dwc->gadget.ep0->maxpacket = 64;
2869 dwc->gadget.speed = USB_SPEED_HIGH;
2870 break;
2871 case DWC3_DSTS_FULLSPEED:
2872 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2873 dwc->gadget.ep0->maxpacket = 64;
2874 dwc->gadget.speed = USB_SPEED_FULL;
2875 break;
2876 case DWC3_DSTS_LOWSPEED:
2877 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2878 dwc->gadget.ep0->maxpacket = 8;
2879 dwc->gadget.speed = USB_SPEED_LOW;
2880 break;
2881 }
2882
2883 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2884
2885 /* Enable USB2 LPM Capability */
2886
2887 if ((dwc->revision > DWC3_REVISION_194A) &&
2888 (speed != DWC3_DSTS_SUPERSPEED) &&
2889 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2890 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2891 reg |= DWC3_DCFG_LPM_CAP;
2892 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2893
2894 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2895 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2896
2897 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2898 (dwc->is_utmi_l1_suspend << 4));
2899
2900 /*
2901 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2902 * DCFG.LPMCap is set, core responses with an ACK and the
2903 * BESL value in the LPM token is less than or equal to LPM
2904 * NYET threshold.
2905 */
2906 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2907 && dwc->has_lpm_erratum,
2908 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2909
2910 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2911 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
2912
2913 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2914 } else {
2915 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2916 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2917 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2918 }
2919
2920 dep = dwc->eps[0];
2921 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2922 if (ret) {
2923 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2924 return;
2925 }
2926
2927 dep = dwc->eps[1];
2928 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2929 if (ret) {
2930 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2931 return;
2932 }
2933
2934 /*
2935 * Configure PHY via GUSB3PIPECTLn if required.
2936 *
2937 * Update GTXFIFOSIZn
2938 *
2939 * In both cases reset values should be sufficient.
2940 */
2941}
2942
2943static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2944{
2945 /*
2946 * TODO take core out of low power mode when that's
2947 * implemented.
2948 */
2949
2950 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2951 spin_unlock(&dwc->lock);
2952 dwc->gadget_driver->resume(&dwc->gadget);
2953 spin_lock(&dwc->lock);
2954 }
2955}
2956
2957static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2958 unsigned int evtinfo)
2959{
2960 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2961 unsigned int pwropt;
2962
2963 /*
2964 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2965 * Hibernation mode enabled which would show up when device detects
2966 * host-initiated U3 exit.
2967 *
2968 * In that case, device will generate a Link State Change Interrupt
2969 * from U3 to RESUME which is only necessary if Hibernation is
2970 * configured in.
2971 *
2972 * There are no functional changes due to such spurious event and we
2973 * just need to ignore it.
2974 *
2975 * Refers to:
2976 *
2977 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2978 * operational mode
2979 */
2980 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2981 if ((dwc->revision < DWC3_REVISION_250A) &&
2982 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2983 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2984 (next == DWC3_LINK_STATE_RESUME)) {
2985 return;
2986 }
2987 }
2988
2989 /*
2990 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2991 * on the link partner, the USB session might do multiple entry/exit
2992 * of low power states before a transfer takes place.
2993 *
2994 * Due to this problem, we might experience lower throughput. The
2995 * suggested workaround is to disable DCTL[12:9] bits if we're
2996 * transitioning from U1/U2 to U0 and enable those bits again
2997 * after a transfer completes and there are no pending transfers
2998 * on any of the enabled endpoints.
2999 *
3000 * This is the first half of that workaround.
3001 *
3002 * Refers to:
3003 *
3004 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3005 * core send LGO_Ux entering U0
3006 */
3007 if (dwc->revision < DWC3_REVISION_183A) {
3008 if (next == DWC3_LINK_STATE_U0) {
3009 u32 u1u2;
3010 u32 reg;
3011
3012 switch (dwc->link_state) {
3013 case DWC3_LINK_STATE_U1:
3014 case DWC3_LINK_STATE_U2:
3015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3016 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3017 | DWC3_DCTL_ACCEPTU2ENA
3018 | DWC3_DCTL_INITU1ENA
3019 | DWC3_DCTL_ACCEPTU1ENA);
3020
3021 if (!dwc->u1u2)
3022 dwc->u1u2 = reg & u1u2;
3023
3024 reg &= ~u1u2;
3025
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3027 break;
3028 default:
3029 /* do nothing */
3030 break;
3031 }
3032 }
3033 }
3034
3035 switch (next) {
3036 case DWC3_LINK_STATE_U1:
3037 if (dwc->speed == USB_SPEED_SUPER)
3038 dwc3_suspend_gadget(dwc);
3039 break;
3040 case DWC3_LINK_STATE_U2:
3041 case DWC3_LINK_STATE_U3:
3042 dwc3_suspend_gadget(dwc);
3043 break;
3044 case DWC3_LINK_STATE_RESUME:
3045 dwc3_resume_gadget(dwc);
3046 break;
3047 default:
3048 /* do nothing */
3049 break;
3050 }
3051
3052 dwc->link_state = next;
3053}
3054
3055static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3056 unsigned int evtinfo)
3057{
3058 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3059
3060 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3061 dwc3_suspend_gadget(dwc);
3062
3063 dwc->link_state = next;
3064}
3065
3066static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3067 unsigned int evtinfo)
3068{
3069 unsigned int is_ss = evtinfo & BIT(4);
3070
3071 /*
3072 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3073 * have a known issue which can cause USB CV TD.9.23 to fail
3074 * randomly.
3075 *
3076 * Because of this issue, core could generate bogus hibernation
3077 * events which SW needs to ignore.
3078 *
3079 * Refers to:
3080 *
3081 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3082 * Device Fallback from SuperSpeed
3083 */
3084 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3085 return;
3086
3087 /* enter hibernation here */
3088}
3089
3090static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3091 const struct dwc3_event_devt *event)
3092{
3093 switch (event->type) {
3094 case DWC3_DEVICE_EVENT_DISCONNECT:
3095 dwc3_gadget_disconnect_interrupt(dwc);
3096 break;
3097 case DWC3_DEVICE_EVENT_RESET:
3098 dwc3_gadget_reset_interrupt(dwc);
3099 break;
3100 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3101 dwc3_gadget_conndone_interrupt(dwc);
3102 break;
3103 case DWC3_DEVICE_EVENT_WAKEUP:
3104 dwc3_gadget_wakeup_interrupt(dwc);
3105 break;
3106 case DWC3_DEVICE_EVENT_HIBER_REQ:
3107 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3108 "unexpected hibernation event\n"))
3109 break;
3110
3111 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3112 break;
3113 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3114 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3115 break;
3116 case DWC3_DEVICE_EVENT_EOPF:
3117 /* It changed to be suspend event for version 2.30a and above */
3118 if (dwc->revision >= DWC3_REVISION_230A) {
3119 /*
3120 * Ignore suspend event until the gadget enters into
3121 * USB_STATE_CONFIGURED state.
3122 */
3123 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3124 dwc3_gadget_suspend_interrupt(dwc,
3125 event->event_info);
3126 }
3127 break;
3128 case DWC3_DEVICE_EVENT_SOF:
3129 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3130 case DWC3_DEVICE_EVENT_CMD_CMPL:
3131 case DWC3_DEVICE_EVENT_OVERFLOW:
3132 break;
3133 default:
3134 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3135 }
3136}
3137
3138static void dwc3_process_event_entry(struct dwc3 *dwc,
3139 const union dwc3_event *event)
3140{
3141 trace_dwc3_event(event->raw, dwc);
3142
3143 if (!event->type.is_devspec)
3144 dwc3_endpoint_interrupt(dwc, &event->depevt);
3145 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3146 dwc3_gadget_interrupt(dwc, &event->devt);
3147 else
3148 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3149}
3150
3151static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3152{
3153 struct dwc3 *dwc = evt->dwc;
3154 irqreturn_t ret = IRQ_NONE;
3155 int left;
3156 u32 reg;
3157
3158 left = evt->count;
3159
3160 if (!(evt->flags & DWC3_EVENT_PENDING))
3161 return IRQ_NONE;
3162
3163 while (left > 0) {
3164 union dwc3_event event;
3165
3166 event.raw = *(u32 *) (evt->cache + evt->lpos);
3167
3168 dwc3_process_event_entry(dwc, &event);
3169
3170 /*
3171 * FIXME we wrap around correctly to the next entry as
3172 * almost all entries are 4 bytes in size. There is one
3173 * entry which has 12 bytes which is a regular entry
3174 * followed by 8 bytes data. ATM I don't know how
3175 * things are organized if we get next to the a
3176 * boundary so I worry about that once we try to handle
3177 * that.
3178 */
3179 evt->lpos = (evt->lpos + 4) % evt->length;
3180 left -= 4;
3181 }
3182
3183 evt->count = 0;
3184 evt->flags &= ~DWC3_EVENT_PENDING;
3185 ret = IRQ_HANDLED;
3186
3187 /* Unmask interrupt */
3188 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3189 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3190 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3191
3192 if (dwc->imod_interval) {
3193 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3194 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3195 }
3196
3197 return ret;
3198}
3199
3200static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3201{
3202 struct dwc3_event_buffer *evt = _evt;
3203 struct dwc3 *dwc = evt->dwc;
3204 unsigned long flags;
3205 irqreturn_t ret = IRQ_NONE;
3206
3207 spin_lock_irqsave(&dwc->lock, flags);
3208 ret = dwc3_process_event_buf(evt);
3209 spin_unlock_irqrestore(&dwc->lock, flags);
3210
3211 return ret;
3212}
3213
3214static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3215{
3216 struct dwc3 *dwc = evt->dwc;
3217 u32 amount;
3218 u32 count;
3219 u32 reg;
3220
3221 if (pm_runtime_suspended(dwc->dev)) {
3222 pm_runtime_get(dwc->dev);
3223 disable_irq_nosync(dwc->irq_gadget);
3224 dwc->pending_events = true;
3225 return IRQ_HANDLED;
3226 }
3227
3228 /*
3229 * With PCIe legacy interrupt, test shows that top-half irq handler can
3230 * be called again after HW interrupt deassertion. Check if bottom-half
3231 * irq event handler completes before caching new event to prevent
3232 * losing events.
3233 */
3234 if (evt->flags & DWC3_EVENT_PENDING)
3235 return IRQ_HANDLED;
3236
3237 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3238 count &= DWC3_GEVNTCOUNT_MASK;
3239 if (!count)
3240 return IRQ_NONE;
3241
3242 evt->count = count;
3243 evt->flags |= DWC3_EVENT_PENDING;
3244
3245 /* Mask interrupt */
3246 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3247 reg |= DWC3_GEVNTSIZ_INTMASK;
3248 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3249
3250 amount = min(count, evt->length - evt->lpos);
3251 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3252
3253 if (amount < count)
3254 memcpy(evt->cache, evt->buf, count - amount);
3255
3256 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3257
3258 return IRQ_WAKE_THREAD;
3259}
3260
3261static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3262{
3263 struct dwc3_event_buffer *evt = _evt;
3264
3265 return dwc3_check_event_buf(evt);
3266}
3267
3268static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3269{
3270 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3271 int irq;
3272
3273 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3274 if (irq > 0)
3275 goto out;
3276
3277 if (irq == -EPROBE_DEFER)
3278 goto out;
3279
3280 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3281 if (irq > 0)
3282 goto out;
3283
3284 if (irq == -EPROBE_DEFER)
3285 goto out;
3286
3287 irq = platform_get_irq(dwc3_pdev, 0);
3288 if (irq > 0)
3289 goto out;
3290
3291 if (!irq)
3292 irq = -EINVAL;
3293
3294out:
3295 return irq;
3296}
3297
3298/**
3299 * dwc3_gadget_init - initializes gadget related registers
3300 * @dwc: pointer to our controller context structure
3301 *
3302 * Returns 0 on success otherwise negative errno.
3303 */
3304int dwc3_gadget_init(struct dwc3 *dwc)
3305{
3306 int ret;
3307 int irq;
3308
3309 irq = dwc3_gadget_get_irq(dwc);
3310 if (irq < 0) {
3311 ret = irq;
3312 goto err0;
3313 }
3314
3315 dwc->irq_gadget = irq;
3316
3317 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3318 sizeof(*dwc->ep0_trb) * 2,
3319 &dwc->ep0_trb_addr, GFP_KERNEL);
3320 if (!dwc->ep0_trb) {
3321 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3322 ret = -ENOMEM;
3323 goto err0;
3324 }
3325
3326 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3327 if (!dwc->setup_buf) {
3328 ret = -ENOMEM;
3329 goto err1;
3330 }
3331
3332 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3333 &dwc->bounce_addr, GFP_KERNEL);
3334 if (!dwc->bounce) {
3335 ret = -ENOMEM;
3336 goto err2;
3337 }
3338
3339 init_completion(&dwc->ep0_in_setup);
3340
3341 dwc->gadget.ops = &dwc3_gadget_ops;
3342 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3343 dwc->gadget.sg_supported = true;
3344 dwc->gadget.name = "dwc3-gadget";
3345 dwc->gadget.lpm_capable = true;
3346
3347 /*
3348 * FIXME We might be setting max_speed to <SUPER, however versions
3349 * <2.20a of dwc3 have an issue with metastability (documented
3350 * elsewhere in this driver) which tells us we can't set max speed to
3351 * anything lower than SUPER.
3352 *
3353 * Because gadget.max_speed is only used by composite.c and function
3354 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3355 * to happen so we avoid sending SuperSpeed Capability descriptor
3356 * together with our BOS descriptor as that could confuse host into
3357 * thinking we can handle super speed.
3358 *
3359 * Note that, in fact, we won't even support GetBOS requests when speed
3360 * is less than super speed because we don't have means, yet, to tell
3361 * composite.c that we are USB 2.0 + LPM ECN.
3362 */
3363 if (dwc->revision < DWC3_REVISION_220A &&
3364 !dwc->dis_metastability_quirk)
3365 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3366 dwc->revision);
3367
3368 dwc->gadget.max_speed = dwc->maximum_speed;
3369
3370 /*
3371 * REVISIT: Here we should clear all pending IRQs to be
3372 * sure we're starting from a well known location.
3373 */
3374
3375 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3376 if (ret)
3377 goto err3;
3378
3379 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3380 if (ret) {
3381 dev_err(dwc->dev, "failed to register udc\n");
3382 goto err4;
3383 }
3384
3385 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3386
3387 return 0;
3388
3389err4:
3390 dwc3_gadget_free_endpoints(dwc);
3391
3392err3:
3393 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3394 dwc->bounce_addr);
3395
3396err2:
3397 kfree(dwc->setup_buf);
3398
3399err1:
3400 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3401 dwc->ep0_trb, dwc->ep0_trb_addr);
3402
3403err0:
3404 return ret;
3405}
3406
3407/* -------------------------------------------------------------------------- */
3408
3409void dwc3_gadget_exit(struct dwc3 *dwc)
3410{
3411 usb_del_gadget_udc(&dwc->gadget);
3412 dwc3_gadget_free_endpoints(dwc);
3413 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3414 dwc->bounce_addr);
3415 kfree(dwc->setup_buf);
3416 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3417 dwc->ep0_trb, dwc->ep0_trb_addr);
3418}
3419
3420int dwc3_gadget_suspend(struct dwc3 *dwc)
3421{
3422 if (!dwc->gadget_driver)
3423 return 0;
3424
3425 dwc3_gadget_run_stop(dwc, false, false);
3426 dwc3_disconnect_gadget(dwc);
3427 __dwc3_gadget_stop(dwc);
3428
3429 return 0;
3430}
3431
3432int dwc3_gadget_resume(struct dwc3 *dwc)
3433{
3434 int ret;
3435
3436 if (!dwc->gadget_driver)
3437 return 0;
3438
3439 ret = __dwc3_gadget_start(dwc);
3440 if (ret < 0)
3441 goto err0;
3442
3443 ret = dwc3_gadget_run_stop(dwc, true, false);
3444 if (ret < 0)
3445 goto err1;
3446
3447 return 0;
3448
3449err1:
3450 __dwc3_gadget_stop(dwc);
3451
3452err0:
3453 return ret;
3454}
3455
3456void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3457{
3458 if (dwc->pending_events) {
3459 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3460 dwc->pending_events = false;
3461 enable_irq(dwc->irq_gadget);
3462 }
3463}
1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "core.h"
34#include "gadget.h"
35#include "io.h"
36
37/**
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
41 *
42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector
44 * is passed
45 */
46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47{
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52
53 switch (mode) {
54 case TEST_J:
55 case TEST_K:
56 case TEST_SE0_NAK:
57 case TEST_PACKET:
58 case TEST_FORCE_EN:
59 reg |= mode << 1;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66
67 return 0;
68}
69
70/**
71 * dwc3_gadget_get_link_state - Gets current state of USB Link
72 * @dwc: pointer to our context structure
73 *
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
76 */
77int dwc3_gadget_get_link_state(struct dwc3 *dwc)
78{
79 u32 reg;
80
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
82
83 return DWC3_DSTS_USBLNKST(reg);
84}
85
86/**
87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
90 *
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
93 */
94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95{
96 int retries = 10000;
97 u32 reg;
98
99 /*
100 * Wait until device controller is ready. Only applies to 1.94a and
101 * later RTL.
102 */
103 if (dwc->revision >= DWC3_REVISION_194A) {
104 while (--retries) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
107 udelay(5);
108 else
109 break;
110 }
111
112 if (retries <= 0)
113 return -ETIMEDOUT;
114 }
115
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
118
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122
123 /*
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
126 */
127 if (dwc->revision >= DWC3_REVISION_194A)
128 return 0;
129
130 /* wait for a change in DSTS */
131 retries = 10000;
132 while (--retries) {
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
134
135 if (DWC3_DSTS_USBLNKST(reg) == state)
136 return 0;
137
138 udelay(5);
139 }
140
141 dev_vdbg(dwc->dev, "link state change request timed out\n");
142
143 return -ETIMEDOUT;
144}
145
146/**
147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
148 * @dwc: pointer to our context structure
149 *
150 * This function will a best effort FIFO allocation in order
151 * to improve FIFO usage and throughput, while still allowing
152 * us to enable as many endpoints as possible.
153 *
154 * Keep in mind that this operation will be highly dependent
155 * on the configured size for RAM1 - which contains TxFifo -,
156 * the amount of endpoints enabled on coreConsultant tool, and
157 * the width of the Master Bus.
158 *
159 * In the ideal world, we would always be able to satisfy the
160 * following equation:
161 *
162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
164 *
165 * Unfortunately, due to many variables that's not always the case.
166 */
167int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
168{
169 int last_fifo_depth = 0;
170 int ram1_depth;
171 int fifo_size;
172 int mdwidth;
173 int num;
174
175 if (!dwc->needs_fifo_resize)
176 return 0;
177
178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
180
181 /* MDWIDTH is represented in bits, we need it in bytes */
182 mdwidth >>= 3;
183
184 /*
185 * FIXME For now we will only allocate 1 wMaxPacketSize space
186 * for each enabled endpoint, later patches will come to
187 * improve this algorithm so that we better use the internal
188 * FIFO space
189 */
190 for (num = 0; num < dwc->num_in_eps; num++) {
191 /* bit0 indicates direction; 1 means IN ep */
192 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
193 int mult = 1;
194 int tmp;
195
196 if (!(dep->flags & DWC3_EP_ENABLED))
197 continue;
198
199 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
200 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
201 mult = 3;
202
203 /*
204 * REVISIT: the following assumes we will always have enough
205 * space available on the FIFO RAM for all possible use cases.
206 * Make sure that's true somehow and change FIFO allocation
207 * accordingly.
208 *
209 * If we have Bulk or Isochronous endpoints, we want
210 * them to be able to be very, very fast. So we're giving
211 * those endpoints a fifo_size which is enough for 3 full
212 * packets
213 */
214 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
215 tmp += mdwidth;
216
217 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
218
219 fifo_size |= (last_fifo_depth << 16);
220
221 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
222 dep->name, last_fifo_depth, fifo_size & 0xffff);
223
224 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
225
226 last_fifo_depth += (fifo_size & 0xffff);
227 }
228
229 return 0;
230}
231
232void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
233 int status)
234{
235 struct dwc3 *dwc = dep->dwc;
236 int i;
237
238 if (req->queued) {
239 i = 0;
240 do {
241 dep->busy_slot++;
242 /*
243 * Skip LINK TRB. We can't use req->trb and check for
244 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
245 * just completed (not the LINK TRB).
246 */
247 if (((dep->busy_slot & DWC3_TRB_MASK) ==
248 DWC3_TRB_NUM- 1) &&
249 usb_endpoint_xfer_isoc(dep->endpoint.desc))
250 dep->busy_slot++;
251 } while(++i < req->request.num_mapped_sgs);
252 req->queued = false;
253 }
254 list_del(&req->list);
255 req->trb = NULL;
256
257 if (req->request.status == -EINPROGRESS)
258 req->request.status = status;
259
260 if (dwc->ep0_bounced && dep->number == 0)
261 dwc->ep0_bounced = false;
262 else
263 usb_gadget_unmap_request(&dwc->gadget, &req->request,
264 req->direction);
265
266 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
267 req, dep->name, req->request.actual,
268 req->request.length, status);
269
270 spin_unlock(&dwc->lock);
271 req->request.complete(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
273}
274
275static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
276{
277 switch (cmd) {
278 case DWC3_DEPCMD_DEPSTARTCFG:
279 return "Start New Configuration";
280 case DWC3_DEPCMD_ENDTRANSFER:
281 return "End Transfer";
282 case DWC3_DEPCMD_UPDATETRANSFER:
283 return "Update Transfer";
284 case DWC3_DEPCMD_STARTTRANSFER:
285 return "Start Transfer";
286 case DWC3_DEPCMD_CLEARSTALL:
287 return "Clear Stall";
288 case DWC3_DEPCMD_SETSTALL:
289 return "Set Stall";
290 case DWC3_DEPCMD_GETEPSTATE:
291 return "Get Endpoint State";
292 case DWC3_DEPCMD_SETTRANSFRESOURCE:
293 return "Set Endpoint Transfer Resource";
294 case DWC3_DEPCMD_SETEPCONFIG:
295 return "Set Endpoint Configuration";
296 default:
297 return "UNKNOWN command";
298 }
299}
300
301int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
302{
303 u32 timeout = 500;
304 u32 reg;
305
306 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
307 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
308
309 do {
310 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
311 if (!(reg & DWC3_DGCMD_CMDACT)) {
312 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
313 DWC3_DGCMD_STATUS(reg));
314 return 0;
315 }
316
317 /*
318 * We can't sleep here, because it's also called from
319 * interrupt context.
320 */
321 timeout--;
322 if (!timeout)
323 return -ETIMEDOUT;
324 udelay(1);
325 } while (1);
326}
327
328int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
329 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
330{
331 struct dwc3_ep *dep = dwc->eps[ep];
332 u32 timeout = 500;
333 u32 reg;
334
335 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
336 dep->name,
337 dwc3_gadget_ep_cmd_string(cmd), params->param0,
338 params->param1, params->param2);
339
340 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
341 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
342 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
343
344 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
345 do {
346 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
347 if (!(reg & DWC3_DEPCMD_CMDACT)) {
348 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
349 DWC3_DEPCMD_STATUS(reg));
350 return 0;
351 }
352
353 /*
354 * We can't sleep here, because it is also called from
355 * interrupt context.
356 */
357 timeout--;
358 if (!timeout)
359 return -ETIMEDOUT;
360
361 udelay(1);
362 } while (1);
363}
364
365static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
366 struct dwc3_trb *trb)
367{
368 u32 offset = (char *) trb - (char *) dep->trb_pool;
369
370 return dep->trb_pool_dma + offset;
371}
372
373static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
374{
375 struct dwc3 *dwc = dep->dwc;
376
377 if (dep->trb_pool)
378 return 0;
379
380 if (dep->number == 0 || dep->number == 1)
381 return 0;
382
383 dep->trb_pool = dma_alloc_coherent(dwc->dev,
384 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
385 &dep->trb_pool_dma, GFP_KERNEL);
386 if (!dep->trb_pool) {
387 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
388 dep->name);
389 return -ENOMEM;
390 }
391
392 return 0;
393}
394
395static void dwc3_free_trb_pool(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398
399 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
400 dep->trb_pool, dep->trb_pool_dma);
401
402 dep->trb_pool = NULL;
403 dep->trb_pool_dma = 0;
404}
405
406static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
407{
408 struct dwc3_gadget_ep_cmd_params params;
409 u32 cmd;
410
411 memset(¶ms, 0x00, sizeof(params));
412
413 if (dep->number != 1) {
414 cmd = DWC3_DEPCMD_DEPSTARTCFG;
415 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
416 if (dep->number > 1) {
417 if (dwc->start_config_issued)
418 return 0;
419 dwc->start_config_issued = true;
420 cmd |= DWC3_DEPCMD_PARAM(2);
421 }
422
423 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
424 }
425
426 return 0;
427}
428
429static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
430 const struct usb_endpoint_descriptor *desc,
431 const struct usb_ss_ep_comp_descriptor *comp_desc,
432 bool ignore, bool restore)
433{
434 struct dwc3_gadget_ep_cmd_params params;
435
436 memset(¶ms, 0x00, sizeof(params));
437
438 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
439 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
440
441 /* Burst size is only needed in SuperSpeed mode */
442 if (dwc->gadget.speed == USB_SPEED_SUPER) {
443 u32 burst = dep->endpoint.maxburst - 1;
444
445 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
446 }
447
448 if (ignore)
449 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
450
451 if (restore) {
452 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
453 params.param2 |= dep->saved_state;
454 }
455
456 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
457 | DWC3_DEPCFG_XFER_NOT_READY_EN;
458
459 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
460 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
461 | DWC3_DEPCFG_STREAM_EVENT_EN;
462 dep->stream_capable = true;
463 }
464
465 if (usb_endpoint_xfer_isoc(desc))
466 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
467
468 /*
469 * We are doing 1:1 mapping for endpoints, meaning
470 * Physical Endpoints 2 maps to Logical Endpoint 2 and
471 * so on. We consider the direction bit as part of the physical
472 * endpoint number. So USB endpoint 0x81 is 0x03.
473 */
474 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
475
476 /*
477 * We must use the lower 16 TX FIFOs even though
478 * HW might have more
479 */
480 if (dep->direction)
481 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
482
483 if (desc->bInterval) {
484 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
485 dep->interval = 1 << (desc->bInterval - 1);
486 }
487
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
490}
491
492static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
493{
494 struct dwc3_gadget_ep_cmd_params params;
495
496 memset(¶ms, 0x00, sizeof(params));
497
498 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
499
500 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
501 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
502}
503
504/**
505 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
506 * @dep: endpoint to be initialized
507 * @desc: USB Endpoint Descriptor
508 *
509 * Caller should take care of locking
510 */
511static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
512 const struct usb_endpoint_descriptor *desc,
513 const struct usb_ss_ep_comp_descriptor *comp_desc,
514 bool ignore, bool restore)
515{
516 struct dwc3 *dwc = dep->dwc;
517 u32 reg;
518 int ret = -ENOMEM;
519
520 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
521
522 if (!(dep->flags & DWC3_EP_ENABLED)) {
523 ret = dwc3_gadget_start_config(dwc, dep);
524 if (ret)
525 return ret;
526 }
527
528 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
529 restore);
530 if (ret)
531 return ret;
532
533 if (!(dep->flags & DWC3_EP_ENABLED)) {
534 struct dwc3_trb *trb_st_hw;
535 struct dwc3_trb *trb_link;
536
537 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
538 if (ret)
539 return ret;
540
541 dep->endpoint.desc = desc;
542 dep->comp_desc = comp_desc;
543 dep->type = usb_endpoint_type(desc);
544 dep->flags |= DWC3_EP_ENABLED;
545
546 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
547 reg |= DWC3_DALEPENA_EP(dep->number);
548 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
549
550 if (!usb_endpoint_xfer_isoc(desc))
551 return 0;
552
553 memset(&trb_link, 0, sizeof(trb_link));
554
555 /* Link TRB for ISOC. The HWO bit is never reset */
556 trb_st_hw = &dep->trb_pool[0];
557
558 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
559
560 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
561 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
562 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
563 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
564 }
565
566 return 0;
567}
568
569static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
570static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
571{
572 struct dwc3_request *req;
573
574 if (!list_empty(&dep->req_queued)) {
575 dwc3_stop_active_transfer(dwc, dep->number, true);
576
577 /* - giveback all requests to gadget driver */
578 while (!list_empty(&dep->req_queued)) {
579 req = next_request(&dep->req_queued);
580
581 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
582 }
583 }
584
585 while (!list_empty(&dep->request_list)) {
586 req = next_request(&dep->request_list);
587
588 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
589 }
590}
591
592/**
593 * __dwc3_gadget_ep_disable - Disables a HW endpoint
594 * @dep: the endpoint to disable
595 *
596 * This function also removes requests which are currently processed ny the
597 * hardware and those which are not yet scheduled.
598 * Caller should take care of locking.
599 */
600static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
601{
602 struct dwc3 *dwc = dep->dwc;
603 u32 reg;
604
605 dwc3_remove_requests(dwc, dep);
606
607 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
608 reg &= ~DWC3_DALEPENA_EP(dep->number);
609 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
610
611 dep->stream_capable = false;
612 dep->endpoint.desc = NULL;
613 dep->comp_desc = NULL;
614 dep->type = 0;
615 dep->flags = 0;
616
617 return 0;
618}
619
620/* -------------------------------------------------------------------------- */
621
622static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
623 const struct usb_endpoint_descriptor *desc)
624{
625 return -EINVAL;
626}
627
628static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
629{
630 return -EINVAL;
631}
632
633/* -------------------------------------------------------------------------- */
634
635static int dwc3_gadget_ep_enable(struct usb_ep *ep,
636 const struct usb_endpoint_descriptor *desc)
637{
638 struct dwc3_ep *dep;
639 struct dwc3 *dwc;
640 unsigned long flags;
641 int ret;
642
643 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
644 pr_debug("dwc3: invalid parameters\n");
645 return -EINVAL;
646 }
647
648 if (!desc->wMaxPacketSize) {
649 pr_debug("dwc3: missing wMaxPacketSize\n");
650 return -EINVAL;
651 }
652
653 dep = to_dwc3_ep(ep);
654 dwc = dep->dwc;
655
656 if (dep->flags & DWC3_EP_ENABLED) {
657 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
658 dep->name);
659 return 0;
660 }
661
662 switch (usb_endpoint_type(desc)) {
663 case USB_ENDPOINT_XFER_CONTROL:
664 strlcat(dep->name, "-control", sizeof(dep->name));
665 break;
666 case USB_ENDPOINT_XFER_ISOC:
667 strlcat(dep->name, "-isoc", sizeof(dep->name));
668 break;
669 case USB_ENDPOINT_XFER_BULK:
670 strlcat(dep->name, "-bulk", sizeof(dep->name));
671 break;
672 case USB_ENDPOINT_XFER_INT:
673 strlcat(dep->name, "-int", sizeof(dep->name));
674 break;
675 default:
676 dev_err(dwc->dev, "invalid endpoint transfer type\n");
677 }
678
679 spin_lock_irqsave(&dwc->lock, flags);
680 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
681 spin_unlock_irqrestore(&dwc->lock, flags);
682
683 return ret;
684}
685
686static int dwc3_gadget_ep_disable(struct usb_ep *ep)
687{
688 struct dwc3_ep *dep;
689 struct dwc3 *dwc;
690 unsigned long flags;
691 int ret;
692
693 if (!ep) {
694 pr_debug("dwc3: invalid parameters\n");
695 return -EINVAL;
696 }
697
698 dep = to_dwc3_ep(ep);
699 dwc = dep->dwc;
700
701 if (!(dep->flags & DWC3_EP_ENABLED)) {
702 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
703 dep->name);
704 return 0;
705 }
706
707 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
708 dep->number >> 1,
709 (dep->number & 1) ? "in" : "out");
710
711 spin_lock_irqsave(&dwc->lock, flags);
712 ret = __dwc3_gadget_ep_disable(dep);
713 spin_unlock_irqrestore(&dwc->lock, flags);
714
715 return ret;
716}
717
718static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
719 gfp_t gfp_flags)
720{
721 struct dwc3_request *req;
722 struct dwc3_ep *dep = to_dwc3_ep(ep);
723 struct dwc3 *dwc = dep->dwc;
724
725 req = kzalloc(sizeof(*req), gfp_flags);
726 if (!req) {
727 dev_err(dwc->dev, "not enough memory\n");
728 return NULL;
729 }
730
731 req->epnum = dep->number;
732 req->dep = dep;
733
734 return &req->request;
735}
736
737static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
738 struct usb_request *request)
739{
740 struct dwc3_request *req = to_dwc3_request(request);
741
742 kfree(req);
743}
744
745/**
746 * dwc3_prepare_one_trb - setup one TRB from one request
747 * @dep: endpoint for which this request is prepared
748 * @req: dwc3_request pointer
749 */
750static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
751 struct dwc3_request *req, dma_addr_t dma,
752 unsigned length, unsigned last, unsigned chain, unsigned node)
753{
754 struct dwc3 *dwc = dep->dwc;
755 struct dwc3_trb *trb;
756
757 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
758 dep->name, req, (unsigned long long) dma,
759 length, last ? " last" : "",
760 chain ? " chain" : "");
761
762 /* Skip the LINK-TRB on ISOC */
763 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
764 usb_endpoint_xfer_isoc(dep->endpoint.desc))
765 dep->free_slot++;
766
767 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
768
769 if (!req->trb) {
770 dwc3_gadget_move_request_queued(req);
771 req->trb = trb;
772 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
773 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
774 }
775
776 dep->free_slot++;
777
778 trb->size = DWC3_TRB_SIZE_LENGTH(length);
779 trb->bpl = lower_32_bits(dma);
780 trb->bph = upper_32_bits(dma);
781
782 switch (usb_endpoint_type(dep->endpoint.desc)) {
783 case USB_ENDPOINT_XFER_CONTROL:
784 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
785 break;
786
787 case USB_ENDPOINT_XFER_ISOC:
788 if (!node)
789 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
790 else
791 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
792 break;
793
794 case USB_ENDPOINT_XFER_BULK:
795 case USB_ENDPOINT_XFER_INT:
796 trb->ctrl = DWC3_TRBCTL_NORMAL;
797 break;
798 default:
799 /*
800 * This is only possible with faulty memory because we
801 * checked it already :)
802 */
803 BUG();
804 }
805
806 if (!req->request.no_interrupt && !chain)
807 trb->ctrl |= DWC3_TRB_CTRL_IOC;
808
809 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
810 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
811 trb->ctrl |= DWC3_TRB_CTRL_CSP;
812 } else if (last) {
813 trb->ctrl |= DWC3_TRB_CTRL_LST;
814 }
815
816 if (chain)
817 trb->ctrl |= DWC3_TRB_CTRL_CHN;
818
819 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
820 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
821
822 trb->ctrl |= DWC3_TRB_CTRL_HWO;
823}
824
825/*
826 * dwc3_prepare_trbs - setup TRBs from requests
827 * @dep: endpoint for which requests are being prepared
828 * @starting: true if the endpoint is idle and no requests are queued.
829 *
830 * The function goes through the requests list and sets up TRBs for the
831 * transfers. The function returns once there are no more TRBs available or
832 * it runs out of requests.
833 */
834static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
835{
836 struct dwc3_request *req, *n;
837 u32 trbs_left;
838 u32 max;
839 unsigned int last_one = 0;
840
841 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
842
843 /* the first request must not be queued */
844 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
845
846 /* Can't wrap around on a non-isoc EP since there's no link TRB */
847 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
848 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
849 if (trbs_left > max)
850 trbs_left = max;
851 }
852
853 /*
854 * If busy & slot are equal than it is either full or empty. If we are
855 * starting to process requests then we are empty. Otherwise we are
856 * full and don't do anything
857 */
858 if (!trbs_left) {
859 if (!starting)
860 return;
861 trbs_left = DWC3_TRB_NUM;
862 /*
863 * In case we start from scratch, we queue the ISOC requests
864 * starting from slot 1. This is done because we use ring
865 * buffer and have no LST bit to stop us. Instead, we place
866 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
867 * after the first request so we start at slot 1 and have
868 * 7 requests proceed before we hit the first IOC.
869 * Other transfer types don't use the ring buffer and are
870 * processed from the first TRB until the last one. Since we
871 * don't wrap around we have to start at the beginning.
872 */
873 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
874 dep->busy_slot = 1;
875 dep->free_slot = 1;
876 } else {
877 dep->busy_slot = 0;
878 dep->free_slot = 0;
879 }
880 }
881
882 /* The last TRB is a link TRB, not used for xfer */
883 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
884 return;
885
886 list_for_each_entry_safe(req, n, &dep->request_list, list) {
887 unsigned length;
888 dma_addr_t dma;
889 last_one = false;
890
891 if (req->request.num_mapped_sgs > 0) {
892 struct usb_request *request = &req->request;
893 struct scatterlist *sg = request->sg;
894 struct scatterlist *s;
895 int i;
896
897 for_each_sg(sg, s, request->num_mapped_sgs, i) {
898 unsigned chain = true;
899
900 length = sg_dma_len(s);
901 dma = sg_dma_address(s);
902
903 if (i == (request->num_mapped_sgs - 1) ||
904 sg_is_last(s)) {
905 if (list_is_last(&req->list,
906 &dep->request_list))
907 last_one = true;
908 chain = false;
909 }
910
911 trbs_left--;
912 if (!trbs_left)
913 last_one = true;
914
915 if (last_one)
916 chain = false;
917
918 dwc3_prepare_one_trb(dep, req, dma, length,
919 last_one, chain, i);
920
921 if (last_one)
922 break;
923 }
924 } else {
925 dma = req->request.dma;
926 length = req->request.length;
927 trbs_left--;
928
929 if (!trbs_left)
930 last_one = 1;
931
932 /* Is this the last request? */
933 if (list_is_last(&req->list, &dep->request_list))
934 last_one = 1;
935
936 dwc3_prepare_one_trb(dep, req, dma, length,
937 last_one, false, 0);
938
939 if (last_one)
940 break;
941 }
942 }
943}
944
945static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
946 int start_new)
947{
948 struct dwc3_gadget_ep_cmd_params params;
949 struct dwc3_request *req;
950 struct dwc3 *dwc = dep->dwc;
951 int ret;
952 u32 cmd;
953
954 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
955 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
956 return -EBUSY;
957 }
958 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
959
960 /*
961 * If we are getting here after a short-out-packet we don't enqueue any
962 * new requests as we try to set the IOC bit only on the last request.
963 */
964 if (start_new) {
965 if (list_empty(&dep->req_queued))
966 dwc3_prepare_trbs(dep, start_new);
967
968 /* req points to the first request which will be sent */
969 req = next_request(&dep->req_queued);
970 } else {
971 dwc3_prepare_trbs(dep, start_new);
972
973 /*
974 * req points to the first request where HWO changed from 0 to 1
975 */
976 req = next_request(&dep->req_queued);
977 }
978 if (!req) {
979 dep->flags |= DWC3_EP_PENDING_REQUEST;
980 return 0;
981 }
982
983 memset(¶ms, 0, sizeof(params));
984
985 if (start_new) {
986 params.param0 = upper_32_bits(req->trb_dma);
987 params.param1 = lower_32_bits(req->trb_dma);
988 cmd = DWC3_DEPCMD_STARTTRANSFER;
989 } else {
990 cmd = DWC3_DEPCMD_UPDATETRANSFER;
991 }
992
993 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
994 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
995 if (ret < 0) {
996 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
997
998 /*
999 * FIXME we need to iterate over the list of requests
1000 * here and stop, unmap, free and del each of the linked
1001 * requests instead of what we do now.
1002 */
1003 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1004 req->direction);
1005 list_del(&req->list);
1006 return ret;
1007 }
1008
1009 dep->flags |= DWC3_EP_BUSY;
1010
1011 if (start_new) {
1012 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1013 dep->number);
1014 WARN_ON_ONCE(!dep->resource_index);
1015 }
1016
1017 return 0;
1018}
1019
1020static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1021 struct dwc3_ep *dep, u32 cur_uf)
1022{
1023 u32 uf;
1024
1025 if (list_empty(&dep->request_list)) {
1026 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1027 dep->name);
1028 dep->flags |= DWC3_EP_PENDING_REQUEST;
1029 return;
1030 }
1031
1032 /* 4 micro frames in the future */
1033 uf = cur_uf + dep->interval * 4;
1034
1035 __dwc3_gadget_kick_transfer(dep, uf, 1);
1036}
1037
1038static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1039 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1040{
1041 u32 cur_uf, mask;
1042
1043 mask = ~(dep->interval - 1);
1044 cur_uf = event->parameters & mask;
1045
1046 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1047}
1048
1049static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1050{
1051 struct dwc3 *dwc = dep->dwc;
1052 int ret;
1053
1054 req->request.actual = 0;
1055 req->request.status = -EINPROGRESS;
1056 req->direction = dep->direction;
1057 req->epnum = dep->number;
1058
1059 /*
1060 * We only add to our list of requests now and
1061 * start consuming the list once we get XferNotReady
1062 * IRQ.
1063 *
1064 * That way, we avoid doing anything that we don't need
1065 * to do now and defer it until the point we receive a
1066 * particular token from the Host side.
1067 *
1068 * This will also avoid Host cancelling URBs due to too
1069 * many NAKs.
1070 */
1071 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1072 dep->direction);
1073 if (ret)
1074 return ret;
1075
1076 list_add_tail(&req->list, &dep->request_list);
1077
1078 /*
1079 * There are a few special cases:
1080 *
1081 * 1. XferNotReady with empty list of requests. We need to kick the
1082 * transfer here in that situation, otherwise we will be NAKing
1083 * forever. If we get XferNotReady before gadget driver has a
1084 * chance to queue a request, we will ACK the IRQ but won't be
1085 * able to receive the data until the next request is queued.
1086 * The following code is handling exactly that.
1087 *
1088 */
1089 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1090 /*
1091 * If xfernotready is already elapsed and it is a case
1092 * of isoc transfer, then issue END TRANSFER, so that
1093 * you can receive xfernotready again and can have
1094 * notion of current microframe.
1095 */
1096 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1097 if (list_empty(&dep->req_queued)) {
1098 dwc3_stop_active_transfer(dwc, dep->number, true);
1099 dep->flags = DWC3_EP_ENABLED;
1100 }
1101 return 0;
1102 }
1103
1104 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1105 if (ret && ret != -EBUSY)
1106 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1107 dep->name);
1108 return ret;
1109 }
1110
1111 /*
1112 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1113 * kick the transfer here after queuing a request, otherwise the
1114 * core may not see the modified TRB(s).
1115 */
1116 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1117 (dep->flags & DWC3_EP_BUSY) &&
1118 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1119 WARN_ON_ONCE(!dep->resource_index);
1120 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1121 false);
1122 if (ret && ret != -EBUSY)
1123 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1124 dep->name);
1125 return ret;
1126 }
1127
1128 /*
1129 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1130 * right away, otherwise host will not know we have streams to be
1131 * handled.
1132 */
1133 if (dep->stream_capable) {
1134 int ret;
1135
1136 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1137 if (ret && ret != -EBUSY) {
1138 struct dwc3 *dwc = dep->dwc;
1139
1140 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1141 dep->name);
1142 }
1143 }
1144
1145 return 0;
1146}
1147
1148static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1149 gfp_t gfp_flags)
1150{
1151 struct dwc3_request *req = to_dwc3_request(request);
1152 struct dwc3_ep *dep = to_dwc3_ep(ep);
1153 struct dwc3 *dwc = dep->dwc;
1154
1155 unsigned long flags;
1156
1157 int ret;
1158
1159 if (!dep->endpoint.desc) {
1160 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1161 request, ep->name);
1162 return -ESHUTDOWN;
1163 }
1164
1165 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1166 request, ep->name, request->length);
1167
1168 spin_lock_irqsave(&dwc->lock, flags);
1169 ret = __dwc3_gadget_ep_queue(dep, req);
1170 spin_unlock_irqrestore(&dwc->lock, flags);
1171
1172 return ret;
1173}
1174
1175static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1176 struct usb_request *request)
1177{
1178 struct dwc3_request *req = to_dwc3_request(request);
1179 struct dwc3_request *r = NULL;
1180
1181 struct dwc3_ep *dep = to_dwc3_ep(ep);
1182 struct dwc3 *dwc = dep->dwc;
1183
1184 unsigned long flags;
1185 int ret = 0;
1186
1187 spin_lock_irqsave(&dwc->lock, flags);
1188
1189 list_for_each_entry(r, &dep->request_list, list) {
1190 if (r == req)
1191 break;
1192 }
1193
1194 if (r != req) {
1195 list_for_each_entry(r, &dep->req_queued, list) {
1196 if (r == req)
1197 break;
1198 }
1199 if (r == req) {
1200 /* wait until it is processed */
1201 dwc3_stop_active_transfer(dwc, dep->number, true);
1202 goto out1;
1203 }
1204 dev_err(dwc->dev, "request %p was not queued to %s\n",
1205 request, ep->name);
1206 ret = -EINVAL;
1207 goto out0;
1208 }
1209
1210out1:
1211 /* giveback the request */
1212 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1213
1214out0:
1215 spin_unlock_irqrestore(&dwc->lock, flags);
1216
1217 return ret;
1218}
1219
1220int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1221{
1222 struct dwc3_gadget_ep_cmd_params params;
1223 struct dwc3 *dwc = dep->dwc;
1224 int ret;
1225
1226 memset(¶ms, 0x00, sizeof(params));
1227
1228 if (value) {
1229 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1230 DWC3_DEPCMD_SETSTALL, ¶ms);
1231 if (ret)
1232 dev_err(dwc->dev, "failed to set STALL on %s\n",
1233 dep->name);
1234 else
1235 dep->flags |= DWC3_EP_STALL;
1236 } else {
1237 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1238 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1239 if (ret)
1240 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1241 dep->name);
1242 else
1243 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1244 }
1245
1246 return ret;
1247}
1248
1249static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1250{
1251 struct dwc3_ep *dep = to_dwc3_ep(ep);
1252 struct dwc3 *dwc = dep->dwc;
1253
1254 unsigned long flags;
1255
1256 int ret;
1257
1258 spin_lock_irqsave(&dwc->lock, flags);
1259
1260 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1261 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1262 ret = -EINVAL;
1263 goto out;
1264 }
1265
1266 ret = __dwc3_gadget_ep_set_halt(dep, value);
1267out:
1268 spin_unlock_irqrestore(&dwc->lock, flags);
1269
1270 return ret;
1271}
1272
1273static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1274{
1275 struct dwc3_ep *dep = to_dwc3_ep(ep);
1276 struct dwc3 *dwc = dep->dwc;
1277 unsigned long flags;
1278
1279 spin_lock_irqsave(&dwc->lock, flags);
1280 dep->flags |= DWC3_EP_WEDGE;
1281 spin_unlock_irqrestore(&dwc->lock, flags);
1282
1283 if (dep->number == 0 || dep->number == 1)
1284 return dwc3_gadget_ep0_set_halt(ep, 1);
1285 else
1286 return dwc3_gadget_ep_set_halt(ep, 1);
1287}
1288
1289/* -------------------------------------------------------------------------- */
1290
1291static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1292 .bLength = USB_DT_ENDPOINT_SIZE,
1293 .bDescriptorType = USB_DT_ENDPOINT,
1294 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1295};
1296
1297static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1298 .enable = dwc3_gadget_ep0_enable,
1299 .disable = dwc3_gadget_ep0_disable,
1300 .alloc_request = dwc3_gadget_ep_alloc_request,
1301 .free_request = dwc3_gadget_ep_free_request,
1302 .queue = dwc3_gadget_ep0_queue,
1303 .dequeue = dwc3_gadget_ep_dequeue,
1304 .set_halt = dwc3_gadget_ep0_set_halt,
1305 .set_wedge = dwc3_gadget_ep_set_wedge,
1306};
1307
1308static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1309 .enable = dwc3_gadget_ep_enable,
1310 .disable = dwc3_gadget_ep_disable,
1311 .alloc_request = dwc3_gadget_ep_alloc_request,
1312 .free_request = dwc3_gadget_ep_free_request,
1313 .queue = dwc3_gadget_ep_queue,
1314 .dequeue = dwc3_gadget_ep_dequeue,
1315 .set_halt = dwc3_gadget_ep_set_halt,
1316 .set_wedge = dwc3_gadget_ep_set_wedge,
1317};
1318
1319/* -------------------------------------------------------------------------- */
1320
1321static int dwc3_gadget_get_frame(struct usb_gadget *g)
1322{
1323 struct dwc3 *dwc = gadget_to_dwc(g);
1324 u32 reg;
1325
1326 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1327 return DWC3_DSTS_SOFFN(reg);
1328}
1329
1330static int dwc3_gadget_wakeup(struct usb_gadget *g)
1331{
1332 struct dwc3 *dwc = gadget_to_dwc(g);
1333
1334 unsigned long timeout;
1335 unsigned long flags;
1336
1337 u32 reg;
1338
1339 int ret = 0;
1340
1341 u8 link_state;
1342 u8 speed;
1343
1344 spin_lock_irqsave(&dwc->lock, flags);
1345
1346 /*
1347 * According to the Databook Remote wakeup request should
1348 * be issued only when the device is in early suspend state.
1349 *
1350 * We can check that via USB Link State bits in DSTS register.
1351 */
1352 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1353
1354 speed = reg & DWC3_DSTS_CONNECTSPD;
1355 if (speed == DWC3_DSTS_SUPERSPEED) {
1356 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1357 ret = -EINVAL;
1358 goto out;
1359 }
1360
1361 link_state = DWC3_DSTS_USBLNKST(reg);
1362
1363 switch (link_state) {
1364 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1365 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1366 break;
1367 default:
1368 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1369 link_state);
1370 ret = -EINVAL;
1371 goto out;
1372 }
1373
1374 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1375 if (ret < 0) {
1376 dev_err(dwc->dev, "failed to put link in Recovery\n");
1377 goto out;
1378 }
1379
1380 /* Recent versions do this automatically */
1381 if (dwc->revision < DWC3_REVISION_194A) {
1382 /* write zeroes to Link Change Request */
1383 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1384 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1385 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386 }
1387
1388 /* poll until Link State changes to ON */
1389 timeout = jiffies + msecs_to_jiffies(100);
1390
1391 while (!time_after(jiffies, timeout)) {
1392 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1393
1394 /* in HS, means ON */
1395 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1396 break;
1397 }
1398
1399 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1400 dev_err(dwc->dev, "failed to send remote wakeup\n");
1401 ret = -EINVAL;
1402 }
1403
1404out:
1405 spin_unlock_irqrestore(&dwc->lock, flags);
1406
1407 return ret;
1408}
1409
1410static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1411 int is_selfpowered)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 unsigned long flags;
1415
1416 spin_lock_irqsave(&dwc->lock, flags);
1417 dwc->is_selfpowered = !!is_selfpowered;
1418 spin_unlock_irqrestore(&dwc->lock, flags);
1419
1420 return 0;
1421}
1422
1423static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1424{
1425 u32 reg;
1426 u32 timeout = 500;
1427
1428 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1429 if (is_on) {
1430 if (dwc->revision <= DWC3_REVISION_187A) {
1431 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1432 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1433 }
1434
1435 if (dwc->revision >= DWC3_REVISION_194A)
1436 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1437 reg |= DWC3_DCTL_RUN_STOP;
1438
1439 if (dwc->has_hibernation)
1440 reg |= DWC3_DCTL_KEEP_CONNECT;
1441
1442 dwc->pullups_connected = true;
1443 } else {
1444 reg &= ~DWC3_DCTL_RUN_STOP;
1445
1446 if (dwc->has_hibernation && !suspend)
1447 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1448
1449 dwc->pullups_connected = false;
1450 }
1451
1452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1453
1454 do {
1455 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1456 if (is_on) {
1457 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1458 break;
1459 } else {
1460 if (reg & DWC3_DSTS_DEVCTRLHLT)
1461 break;
1462 }
1463 timeout--;
1464 if (!timeout)
1465 return -ETIMEDOUT;
1466 udelay(1);
1467 } while (1);
1468
1469 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1470 dwc->gadget_driver
1471 ? dwc->gadget_driver->function : "no-function",
1472 is_on ? "connect" : "disconnect");
1473
1474 return 0;
1475}
1476
1477static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1478{
1479 struct dwc3 *dwc = gadget_to_dwc(g);
1480 unsigned long flags;
1481 int ret;
1482
1483 is_on = !!is_on;
1484
1485 spin_lock_irqsave(&dwc->lock, flags);
1486 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1487 spin_unlock_irqrestore(&dwc->lock, flags);
1488
1489 return ret;
1490}
1491
1492static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1493{
1494 u32 reg;
1495
1496 /* Enable all but Start and End of Frame IRQs */
1497 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1498 DWC3_DEVTEN_EVNTOVERFLOWEN |
1499 DWC3_DEVTEN_CMDCMPLTEN |
1500 DWC3_DEVTEN_ERRTICERREN |
1501 DWC3_DEVTEN_WKUPEVTEN |
1502 DWC3_DEVTEN_ULSTCNGEN |
1503 DWC3_DEVTEN_CONNECTDONEEN |
1504 DWC3_DEVTEN_USBRSTEN |
1505 DWC3_DEVTEN_DISCONNEVTEN);
1506
1507 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1508}
1509
1510static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1511{
1512 /* mask all interrupts */
1513 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1514}
1515
1516static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1517static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1518
1519static int dwc3_gadget_start(struct usb_gadget *g,
1520 struct usb_gadget_driver *driver)
1521{
1522 struct dwc3 *dwc = gadget_to_dwc(g);
1523 struct dwc3_ep *dep;
1524 unsigned long flags;
1525 int ret = 0;
1526 int irq;
1527 u32 reg;
1528
1529 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1530 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1531 IRQF_SHARED, "dwc3", dwc);
1532 if (ret) {
1533 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1534 irq, ret);
1535 goto err0;
1536 }
1537
1538 spin_lock_irqsave(&dwc->lock, flags);
1539
1540 if (dwc->gadget_driver) {
1541 dev_err(dwc->dev, "%s is already bound to %s\n",
1542 dwc->gadget.name,
1543 dwc->gadget_driver->driver.name);
1544 ret = -EBUSY;
1545 goto err1;
1546 }
1547
1548 dwc->gadget_driver = driver;
1549
1550 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1551 reg &= ~(DWC3_DCFG_SPEED_MASK);
1552
1553 /**
1554 * WORKAROUND: DWC3 revision < 2.20a have an issue
1555 * which would cause metastability state on Run/Stop
1556 * bit if we try to force the IP to USB2-only mode.
1557 *
1558 * Because of that, we cannot configure the IP to any
1559 * speed other than the SuperSpeed
1560 *
1561 * Refers to:
1562 *
1563 * STAR#9000525659: Clock Domain Crossing on DCTL in
1564 * USB 2.0 Mode
1565 */
1566 if (dwc->revision < DWC3_REVISION_220A) {
1567 reg |= DWC3_DCFG_SUPERSPEED;
1568 } else {
1569 switch (dwc->maximum_speed) {
1570 case USB_SPEED_LOW:
1571 reg |= DWC3_DSTS_LOWSPEED;
1572 break;
1573 case USB_SPEED_FULL:
1574 reg |= DWC3_DSTS_FULLSPEED1;
1575 break;
1576 case USB_SPEED_HIGH:
1577 reg |= DWC3_DSTS_HIGHSPEED;
1578 break;
1579 case USB_SPEED_SUPER: /* FALLTHROUGH */
1580 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1581 default:
1582 reg |= DWC3_DSTS_SUPERSPEED;
1583 }
1584 }
1585 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1586
1587 dwc->start_config_issued = false;
1588
1589 /* Start with SuperSpeed Default */
1590 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1591
1592 dep = dwc->eps[0];
1593 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1594 false);
1595 if (ret) {
1596 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1597 goto err2;
1598 }
1599
1600 dep = dwc->eps[1];
1601 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1602 false);
1603 if (ret) {
1604 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1605 goto err3;
1606 }
1607
1608 /* begin to receive SETUP packets */
1609 dwc->ep0state = EP0_SETUP_PHASE;
1610 dwc3_ep0_out_start(dwc);
1611
1612 dwc3_gadget_enable_irq(dwc);
1613
1614 spin_unlock_irqrestore(&dwc->lock, flags);
1615
1616 return 0;
1617
1618err3:
1619 __dwc3_gadget_ep_disable(dwc->eps[0]);
1620
1621err2:
1622 dwc->gadget_driver = NULL;
1623
1624err1:
1625 spin_unlock_irqrestore(&dwc->lock, flags);
1626
1627 free_irq(irq, dwc);
1628
1629err0:
1630 return ret;
1631}
1632
1633static int dwc3_gadget_stop(struct usb_gadget *g,
1634 struct usb_gadget_driver *driver)
1635{
1636 struct dwc3 *dwc = gadget_to_dwc(g);
1637 unsigned long flags;
1638 int irq;
1639
1640 spin_lock_irqsave(&dwc->lock, flags);
1641
1642 dwc3_gadget_disable_irq(dwc);
1643 __dwc3_gadget_ep_disable(dwc->eps[0]);
1644 __dwc3_gadget_ep_disable(dwc->eps[1]);
1645
1646 dwc->gadget_driver = NULL;
1647
1648 spin_unlock_irqrestore(&dwc->lock, flags);
1649
1650 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1651 free_irq(irq, dwc);
1652
1653 return 0;
1654}
1655
1656static const struct usb_gadget_ops dwc3_gadget_ops = {
1657 .get_frame = dwc3_gadget_get_frame,
1658 .wakeup = dwc3_gadget_wakeup,
1659 .set_selfpowered = dwc3_gadget_set_selfpowered,
1660 .pullup = dwc3_gadget_pullup,
1661 .udc_start = dwc3_gadget_start,
1662 .udc_stop = dwc3_gadget_stop,
1663};
1664
1665/* -------------------------------------------------------------------------- */
1666
1667static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1668 u8 num, u32 direction)
1669{
1670 struct dwc3_ep *dep;
1671 u8 i;
1672
1673 for (i = 0; i < num; i++) {
1674 u8 epnum = (i << 1) | (!!direction);
1675
1676 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1677 if (!dep) {
1678 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1679 epnum);
1680 return -ENOMEM;
1681 }
1682
1683 dep->dwc = dwc;
1684 dep->number = epnum;
1685 dep->direction = !!direction;
1686 dwc->eps[epnum] = dep;
1687
1688 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1689 (epnum & 1) ? "in" : "out");
1690
1691 dep->endpoint.name = dep->name;
1692
1693 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1694
1695 if (epnum == 0 || epnum == 1) {
1696 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1697 dep->endpoint.maxburst = 1;
1698 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1699 if (!epnum)
1700 dwc->gadget.ep0 = &dep->endpoint;
1701 } else {
1702 int ret;
1703
1704 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1705 dep->endpoint.max_streams = 15;
1706 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1707 list_add_tail(&dep->endpoint.ep_list,
1708 &dwc->gadget.ep_list);
1709
1710 ret = dwc3_alloc_trb_pool(dep);
1711 if (ret)
1712 return ret;
1713 }
1714
1715 INIT_LIST_HEAD(&dep->request_list);
1716 INIT_LIST_HEAD(&dep->req_queued);
1717 }
1718
1719 return 0;
1720}
1721
1722static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1723{
1724 int ret;
1725
1726 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1727
1728 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1729 if (ret < 0) {
1730 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1731 return ret;
1732 }
1733
1734 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1735 if (ret < 0) {
1736 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1737 return ret;
1738 }
1739
1740 return 0;
1741}
1742
1743static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1744{
1745 struct dwc3_ep *dep;
1746 u8 epnum;
1747
1748 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1749 dep = dwc->eps[epnum];
1750 if (!dep)
1751 continue;
1752 /*
1753 * Physical endpoints 0 and 1 are special; they form the
1754 * bi-directional USB endpoint 0.
1755 *
1756 * For those two physical endpoints, we don't allocate a TRB
1757 * pool nor do we add them the endpoints list. Due to that, we
1758 * shouldn't do these two operations otherwise we would end up
1759 * with all sorts of bugs when removing dwc3.ko.
1760 */
1761 if (epnum != 0 && epnum != 1) {
1762 dwc3_free_trb_pool(dep);
1763 list_del(&dep->endpoint.ep_list);
1764 }
1765
1766 kfree(dep);
1767 }
1768}
1769
1770/* -------------------------------------------------------------------------- */
1771
1772static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1773 struct dwc3_request *req, struct dwc3_trb *trb,
1774 const struct dwc3_event_depevt *event, int status)
1775{
1776 unsigned int count;
1777 unsigned int s_pkt = 0;
1778 unsigned int trb_status;
1779
1780 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1781 /*
1782 * We continue despite the error. There is not much we
1783 * can do. If we don't clean it up we loop forever. If
1784 * we skip the TRB then it gets overwritten after a
1785 * while since we use them in a ring buffer. A BUG()
1786 * would help. Lets hope that if this occurs, someone
1787 * fixes the root cause instead of looking away :)
1788 */
1789 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1790 dep->name, trb);
1791 count = trb->size & DWC3_TRB_SIZE_MASK;
1792
1793 if (dep->direction) {
1794 if (count) {
1795 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1796 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1797 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1798 dep->name);
1799 /*
1800 * If missed isoc occurred and there is
1801 * no request queued then issue END
1802 * TRANSFER, so that core generates
1803 * next xfernotready and we will issue
1804 * a fresh START TRANSFER.
1805 * If there are still queued request
1806 * then wait, do not issue either END
1807 * or UPDATE TRANSFER, just attach next
1808 * request in request_list during
1809 * giveback.If any future queued request
1810 * is successfully transferred then we
1811 * will issue UPDATE TRANSFER for all
1812 * request in the request_list.
1813 */
1814 dep->flags |= DWC3_EP_MISSED_ISOC;
1815 } else {
1816 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1817 dep->name);
1818 status = -ECONNRESET;
1819 }
1820 } else {
1821 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1822 }
1823 } else {
1824 if (count && (event->status & DEPEVT_STATUS_SHORT))
1825 s_pkt = 1;
1826 }
1827
1828 /*
1829 * We assume here we will always receive the entire data block
1830 * which we should receive. Meaning, if we program RX to
1831 * receive 4K but we receive only 2K, we assume that's all we
1832 * should receive and we simply bounce the request back to the
1833 * gadget driver for further processing.
1834 */
1835 req->request.actual += req->request.length - count;
1836 if (s_pkt)
1837 return 1;
1838 if ((event->status & DEPEVT_STATUS_LST) &&
1839 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1840 DWC3_TRB_CTRL_HWO)))
1841 return 1;
1842 if ((event->status & DEPEVT_STATUS_IOC) &&
1843 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1844 return 1;
1845 return 0;
1846}
1847
1848static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1849 const struct dwc3_event_depevt *event, int status)
1850{
1851 struct dwc3_request *req;
1852 struct dwc3_trb *trb;
1853 unsigned int slot;
1854 unsigned int i;
1855 int ret;
1856
1857 do {
1858 req = next_request(&dep->req_queued);
1859 if (!req) {
1860 WARN_ON_ONCE(1);
1861 return 1;
1862 }
1863 i = 0;
1864 do {
1865 slot = req->start_slot + i;
1866 if ((slot == DWC3_TRB_NUM - 1) &&
1867 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1868 slot++;
1869 slot %= DWC3_TRB_NUM;
1870 trb = &dep->trb_pool[slot];
1871
1872 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1873 event, status);
1874 if (ret)
1875 break;
1876 }while (++i < req->request.num_mapped_sgs);
1877
1878 dwc3_gadget_giveback(dep, req, status);
1879
1880 if (ret)
1881 break;
1882 } while (1);
1883
1884 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1885 list_empty(&dep->req_queued)) {
1886 if (list_empty(&dep->request_list)) {
1887 /*
1888 * If there is no entry in request list then do
1889 * not issue END TRANSFER now. Just set PENDING
1890 * flag, so that END TRANSFER is issued when an
1891 * entry is added into request list.
1892 */
1893 dep->flags = DWC3_EP_PENDING_REQUEST;
1894 } else {
1895 dwc3_stop_active_transfer(dwc, dep->number, true);
1896 dep->flags = DWC3_EP_ENABLED;
1897 }
1898 return 1;
1899 }
1900
1901 return 1;
1902}
1903
1904static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1905 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1906 int start_new)
1907{
1908 unsigned status = 0;
1909 int clean_busy;
1910
1911 if (event->status & DEPEVT_STATUS_BUSERR)
1912 status = -ECONNRESET;
1913
1914 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1915 if (clean_busy)
1916 dep->flags &= ~DWC3_EP_BUSY;
1917
1918 /*
1919 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1920 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1921 */
1922 if (dwc->revision < DWC3_REVISION_183A) {
1923 u32 reg;
1924 int i;
1925
1926 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1927 dep = dwc->eps[i];
1928
1929 if (!(dep->flags & DWC3_EP_ENABLED))
1930 continue;
1931
1932 if (!list_empty(&dep->req_queued))
1933 return;
1934 }
1935
1936 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1937 reg |= dwc->u1u2;
1938 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1939
1940 dwc->u1u2 = 0;
1941 }
1942}
1943
1944static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1945 const struct dwc3_event_depevt *event)
1946{
1947 struct dwc3_ep *dep;
1948 u8 epnum = event->endpoint_number;
1949
1950 dep = dwc->eps[epnum];
1951
1952 if (!(dep->flags & DWC3_EP_ENABLED))
1953 return;
1954
1955 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1956 dwc3_ep_event_string(event->endpoint_event));
1957
1958 if (epnum == 0 || epnum == 1) {
1959 dwc3_ep0_interrupt(dwc, event);
1960 return;
1961 }
1962
1963 switch (event->endpoint_event) {
1964 case DWC3_DEPEVT_XFERCOMPLETE:
1965 dep->resource_index = 0;
1966
1967 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1968 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1969 dep->name);
1970 return;
1971 }
1972
1973 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1974 break;
1975 case DWC3_DEPEVT_XFERINPROGRESS:
1976 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1977 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1978 dep->name);
1979 return;
1980 }
1981
1982 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1983 break;
1984 case DWC3_DEPEVT_XFERNOTREADY:
1985 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1986 dwc3_gadget_start_isoc(dwc, dep, event);
1987 } else {
1988 int ret;
1989
1990 dev_vdbg(dwc->dev, "%s: reason %s\n",
1991 dep->name, event->status &
1992 DEPEVT_STATUS_TRANSFER_ACTIVE
1993 ? "Transfer Active"
1994 : "Transfer Not Active");
1995
1996 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1997 if (!ret || ret == -EBUSY)
1998 return;
1999
2000 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2001 dep->name);
2002 }
2003
2004 break;
2005 case DWC3_DEPEVT_STREAMEVT:
2006 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2007 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2008 dep->name);
2009 return;
2010 }
2011
2012 switch (event->status) {
2013 case DEPEVT_STREAMEVT_FOUND:
2014 dev_vdbg(dwc->dev, "Stream %d found and started\n",
2015 event->parameters);
2016
2017 break;
2018 case DEPEVT_STREAMEVT_NOTFOUND:
2019 /* FALLTHROUGH */
2020 default:
2021 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2022 }
2023 break;
2024 case DWC3_DEPEVT_RXTXFIFOEVT:
2025 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2026 break;
2027 case DWC3_DEPEVT_EPCMDCMPLT:
2028 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2029 break;
2030 }
2031}
2032
2033static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2034{
2035 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2036 spin_unlock(&dwc->lock);
2037 dwc->gadget_driver->disconnect(&dwc->gadget);
2038 spin_lock(&dwc->lock);
2039 }
2040}
2041
2042static void dwc3_suspend_gadget(struct dwc3 *dwc)
2043{
2044 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2045 spin_unlock(&dwc->lock);
2046 dwc->gadget_driver->suspend(&dwc->gadget);
2047 spin_lock(&dwc->lock);
2048 }
2049}
2050
2051static void dwc3_resume_gadget(struct dwc3 *dwc)
2052{
2053 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2054 spin_unlock(&dwc->lock);
2055 dwc->gadget_driver->resume(&dwc->gadget);
2056 spin_lock(&dwc->lock);
2057 }
2058}
2059
2060static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2061{
2062 struct dwc3_ep *dep;
2063 struct dwc3_gadget_ep_cmd_params params;
2064 u32 cmd;
2065 int ret;
2066
2067 dep = dwc->eps[epnum];
2068
2069 if (!dep->resource_index)
2070 return;
2071
2072 /*
2073 * NOTICE: We are violating what the Databook says about the
2074 * EndTransfer command. Ideally we would _always_ wait for the
2075 * EndTransfer Command Completion IRQ, but that's causing too
2076 * much trouble synchronizing between us and gadget driver.
2077 *
2078 * We have discussed this with the IP Provider and it was
2079 * suggested to giveback all requests here, but give HW some
2080 * extra time to synchronize with the interconnect. We're using
2081 * an arbitraty 100us delay for that.
2082 *
2083 * Note also that a similar handling was tested by Synopsys
2084 * (thanks a lot Paul) and nothing bad has come out of it.
2085 * In short, what we're doing is:
2086 *
2087 * - Issue EndTransfer WITH CMDIOC bit set
2088 * - Wait 100us
2089 */
2090
2091 cmd = DWC3_DEPCMD_ENDTRANSFER;
2092 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2093 cmd |= DWC3_DEPCMD_CMDIOC;
2094 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2095 memset(¶ms, 0, sizeof(params));
2096 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2097 WARN_ON_ONCE(ret);
2098 dep->resource_index = 0;
2099 dep->flags &= ~DWC3_EP_BUSY;
2100 udelay(100);
2101}
2102
2103static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2104{
2105 u32 epnum;
2106
2107 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2108 struct dwc3_ep *dep;
2109
2110 dep = dwc->eps[epnum];
2111 if (!dep)
2112 continue;
2113
2114 if (!(dep->flags & DWC3_EP_ENABLED))
2115 continue;
2116
2117 dwc3_remove_requests(dwc, dep);
2118 }
2119}
2120
2121static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2122{
2123 u32 epnum;
2124
2125 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2126 struct dwc3_ep *dep;
2127 struct dwc3_gadget_ep_cmd_params params;
2128 int ret;
2129
2130 dep = dwc->eps[epnum];
2131 if (!dep)
2132 continue;
2133
2134 if (!(dep->flags & DWC3_EP_STALL))
2135 continue;
2136
2137 dep->flags &= ~DWC3_EP_STALL;
2138
2139 memset(¶ms, 0, sizeof(params));
2140 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2141 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2142 WARN_ON_ONCE(ret);
2143 }
2144}
2145
2146static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2147{
2148 int reg;
2149
2150 dev_vdbg(dwc->dev, "%s\n", __func__);
2151
2152 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2153 reg &= ~DWC3_DCTL_INITU1ENA;
2154 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2155
2156 reg &= ~DWC3_DCTL_INITU2ENA;
2157 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2158
2159 dwc3_disconnect_gadget(dwc);
2160 dwc->start_config_issued = false;
2161
2162 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2163 dwc->setup_packet_pending = false;
2164}
2165
2166static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2167{
2168 u32 reg;
2169
2170 dev_vdbg(dwc->dev, "%s\n", __func__);
2171
2172 /*
2173 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2174 * would cause a missing Disconnect Event if there's a
2175 * pending Setup Packet in the FIFO.
2176 *
2177 * There's no suggested workaround on the official Bug
2178 * report, which states that "unless the driver/application
2179 * is doing any special handling of a disconnect event,
2180 * there is no functional issue".
2181 *
2182 * Unfortunately, it turns out that we _do_ some special
2183 * handling of a disconnect event, namely complete all
2184 * pending transfers, notify gadget driver of the
2185 * disconnection, and so on.
2186 *
2187 * Our suggested workaround is to follow the Disconnect
2188 * Event steps here, instead, based on a setup_packet_pending
2189 * flag. Such flag gets set whenever we have a XferNotReady
2190 * event on EP0 and gets cleared on XferComplete for the
2191 * same endpoint.
2192 *
2193 * Refers to:
2194 *
2195 * STAR#9000466709: RTL: Device : Disconnect event not
2196 * generated if setup packet pending in FIFO
2197 */
2198 if (dwc->revision < DWC3_REVISION_188A) {
2199 if (dwc->setup_packet_pending)
2200 dwc3_gadget_disconnect_interrupt(dwc);
2201 }
2202
2203 /* after reset -> Default State */
2204 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2205
2206 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2207 dwc3_disconnect_gadget(dwc);
2208
2209 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2210 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2211 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2212 dwc->test_mode = false;
2213
2214 dwc3_stop_active_transfers(dwc);
2215 dwc3_clear_stall_all_ep(dwc);
2216 dwc->start_config_issued = false;
2217
2218 /* Reset device address to zero */
2219 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2220 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2221 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2222}
2223
2224static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2225{
2226 u32 reg;
2227 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2228
2229 /*
2230 * We change the clock only at SS but I dunno why I would want to do
2231 * this. Maybe it becomes part of the power saving plan.
2232 */
2233
2234 if (speed != DWC3_DSTS_SUPERSPEED)
2235 return;
2236
2237 /*
2238 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2239 * each time on Connect Done.
2240 */
2241 if (!usb30_clock)
2242 return;
2243
2244 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2245 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2246 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2247}
2248
2249static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2250{
2251 struct dwc3_ep *dep;
2252 int ret;
2253 u32 reg;
2254 u8 speed;
2255
2256 dev_vdbg(dwc->dev, "%s\n", __func__);
2257
2258 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2259 speed = reg & DWC3_DSTS_CONNECTSPD;
2260 dwc->speed = speed;
2261
2262 dwc3_update_ram_clk_sel(dwc, speed);
2263
2264 switch (speed) {
2265 case DWC3_DCFG_SUPERSPEED:
2266 /*
2267 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2268 * would cause a missing USB3 Reset event.
2269 *
2270 * In such situations, we should force a USB3 Reset
2271 * event by calling our dwc3_gadget_reset_interrupt()
2272 * routine.
2273 *
2274 * Refers to:
2275 *
2276 * STAR#9000483510: RTL: SS : USB3 reset event may
2277 * not be generated always when the link enters poll
2278 */
2279 if (dwc->revision < DWC3_REVISION_190A)
2280 dwc3_gadget_reset_interrupt(dwc);
2281
2282 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2283 dwc->gadget.ep0->maxpacket = 512;
2284 dwc->gadget.speed = USB_SPEED_SUPER;
2285 break;
2286 case DWC3_DCFG_HIGHSPEED:
2287 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2288 dwc->gadget.ep0->maxpacket = 64;
2289 dwc->gadget.speed = USB_SPEED_HIGH;
2290 break;
2291 case DWC3_DCFG_FULLSPEED2:
2292 case DWC3_DCFG_FULLSPEED1:
2293 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2294 dwc->gadget.ep0->maxpacket = 64;
2295 dwc->gadget.speed = USB_SPEED_FULL;
2296 break;
2297 case DWC3_DCFG_LOWSPEED:
2298 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2299 dwc->gadget.ep0->maxpacket = 8;
2300 dwc->gadget.speed = USB_SPEED_LOW;
2301 break;
2302 }
2303
2304 /* Enable USB2 LPM Capability */
2305
2306 if ((dwc->revision > DWC3_REVISION_194A)
2307 && (speed != DWC3_DCFG_SUPERSPEED)) {
2308 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2309 reg |= DWC3_DCFG_LPM_CAP;
2310 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2311
2312 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2313 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2314
2315 /*
2316 * TODO: This should be configurable. For now using
2317 * maximum allowed HIRD threshold value of 0b1100
2318 */
2319 reg |= DWC3_DCTL_HIRD_THRES(12);
2320
2321 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2322 } else {
2323 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2324 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2325 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2326 }
2327
2328 dep = dwc->eps[0];
2329 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2330 false);
2331 if (ret) {
2332 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2333 return;
2334 }
2335
2336 dep = dwc->eps[1];
2337 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2338 false);
2339 if (ret) {
2340 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2341 return;
2342 }
2343
2344 /*
2345 * Configure PHY via GUSB3PIPECTLn if required.
2346 *
2347 * Update GTXFIFOSIZn
2348 *
2349 * In both cases reset values should be sufficient.
2350 */
2351}
2352
2353static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2354{
2355 dev_vdbg(dwc->dev, "%s\n", __func__);
2356
2357 /*
2358 * TODO take core out of low power mode when that's
2359 * implemented.
2360 */
2361
2362 dwc->gadget_driver->resume(&dwc->gadget);
2363}
2364
2365static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2366 unsigned int evtinfo)
2367{
2368 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2369 unsigned int pwropt;
2370
2371 /*
2372 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2373 * Hibernation mode enabled which would show up when device detects
2374 * host-initiated U3 exit.
2375 *
2376 * In that case, device will generate a Link State Change Interrupt
2377 * from U3 to RESUME which is only necessary if Hibernation is
2378 * configured in.
2379 *
2380 * There are no functional changes due to such spurious event and we
2381 * just need to ignore it.
2382 *
2383 * Refers to:
2384 *
2385 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2386 * operational mode
2387 */
2388 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2389 if ((dwc->revision < DWC3_REVISION_250A) &&
2390 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2391 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2392 (next == DWC3_LINK_STATE_RESUME)) {
2393 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2394 return;
2395 }
2396 }
2397
2398 /*
2399 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2400 * on the link partner, the USB session might do multiple entry/exit
2401 * of low power states before a transfer takes place.
2402 *
2403 * Due to this problem, we might experience lower throughput. The
2404 * suggested workaround is to disable DCTL[12:9] bits if we're
2405 * transitioning from U1/U2 to U0 and enable those bits again
2406 * after a transfer completes and there are no pending transfers
2407 * on any of the enabled endpoints.
2408 *
2409 * This is the first half of that workaround.
2410 *
2411 * Refers to:
2412 *
2413 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2414 * core send LGO_Ux entering U0
2415 */
2416 if (dwc->revision < DWC3_REVISION_183A) {
2417 if (next == DWC3_LINK_STATE_U0) {
2418 u32 u1u2;
2419 u32 reg;
2420
2421 switch (dwc->link_state) {
2422 case DWC3_LINK_STATE_U1:
2423 case DWC3_LINK_STATE_U2:
2424 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2425 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2426 | DWC3_DCTL_ACCEPTU2ENA
2427 | DWC3_DCTL_INITU1ENA
2428 | DWC3_DCTL_ACCEPTU1ENA);
2429
2430 if (!dwc->u1u2)
2431 dwc->u1u2 = reg & u1u2;
2432
2433 reg &= ~u1u2;
2434
2435 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2436 break;
2437 default:
2438 /* do nothing */
2439 break;
2440 }
2441 }
2442 }
2443
2444 dwc->link_state = next;
2445
2446 switch (next) {
2447 case DWC3_LINK_STATE_U1:
2448 if (dwc->speed == USB_SPEED_SUPER)
2449 dwc3_suspend_gadget(dwc);
2450 break;
2451 case DWC3_LINK_STATE_U2:
2452 case DWC3_LINK_STATE_U3:
2453 dwc3_suspend_gadget(dwc);
2454 break;
2455 case DWC3_LINK_STATE_RESUME:
2456 dwc3_resume_gadget(dwc);
2457 break;
2458 default:
2459 /* do nothing */
2460 break;
2461 }
2462
2463 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2464}
2465
2466static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2467 unsigned int evtinfo)
2468{
2469 unsigned int is_ss = evtinfo & BIT(4);
2470
2471 /**
2472 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2473 * have a known issue which can cause USB CV TD.9.23 to fail
2474 * randomly.
2475 *
2476 * Because of this issue, core could generate bogus hibernation
2477 * events which SW needs to ignore.
2478 *
2479 * Refers to:
2480 *
2481 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2482 * Device Fallback from SuperSpeed
2483 */
2484 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2485 return;
2486
2487 /* enter hibernation here */
2488}
2489
2490static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2491 const struct dwc3_event_devt *event)
2492{
2493 switch (event->type) {
2494 case DWC3_DEVICE_EVENT_DISCONNECT:
2495 dwc3_gadget_disconnect_interrupt(dwc);
2496 break;
2497 case DWC3_DEVICE_EVENT_RESET:
2498 dwc3_gadget_reset_interrupt(dwc);
2499 break;
2500 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2501 dwc3_gadget_conndone_interrupt(dwc);
2502 break;
2503 case DWC3_DEVICE_EVENT_WAKEUP:
2504 dwc3_gadget_wakeup_interrupt(dwc);
2505 break;
2506 case DWC3_DEVICE_EVENT_HIBER_REQ:
2507 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2508 "unexpected hibernation event\n"))
2509 break;
2510
2511 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2512 break;
2513 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2514 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2515 break;
2516 case DWC3_DEVICE_EVENT_EOPF:
2517 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2518 break;
2519 case DWC3_DEVICE_EVENT_SOF:
2520 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2521 break;
2522 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2523 dev_vdbg(dwc->dev, "Erratic Error\n");
2524 break;
2525 case DWC3_DEVICE_EVENT_CMD_CMPL:
2526 dev_vdbg(dwc->dev, "Command Complete\n");
2527 break;
2528 case DWC3_DEVICE_EVENT_OVERFLOW:
2529 dev_vdbg(dwc->dev, "Overflow\n");
2530 break;
2531 default:
2532 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2533 }
2534}
2535
2536static void dwc3_process_event_entry(struct dwc3 *dwc,
2537 const union dwc3_event *event)
2538{
2539 /* Endpoint IRQ, handle it and return early */
2540 if (event->type.is_devspec == 0) {
2541 /* depevt */
2542 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2543 }
2544
2545 switch (event->type.type) {
2546 case DWC3_EVENT_TYPE_DEV:
2547 dwc3_gadget_interrupt(dwc, &event->devt);
2548 break;
2549 /* REVISIT what to do with Carkit and I2C events ? */
2550 default:
2551 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2552 }
2553}
2554
2555static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2556{
2557 struct dwc3_event_buffer *evt;
2558 irqreturn_t ret = IRQ_NONE;
2559 int left;
2560 u32 reg;
2561
2562 evt = dwc->ev_buffs[buf];
2563 left = evt->count;
2564
2565 if (!(evt->flags & DWC3_EVENT_PENDING))
2566 return IRQ_NONE;
2567
2568 while (left > 0) {
2569 union dwc3_event event;
2570
2571 event.raw = *(u32 *) (evt->buf + evt->lpos);
2572
2573 dwc3_process_event_entry(dwc, &event);
2574
2575 /*
2576 * FIXME we wrap around correctly to the next entry as
2577 * almost all entries are 4 bytes in size. There is one
2578 * entry which has 12 bytes which is a regular entry
2579 * followed by 8 bytes data. ATM I don't know how
2580 * things are organized if we get next to the a
2581 * boundary so I worry about that once we try to handle
2582 * that.
2583 */
2584 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2585 left -= 4;
2586
2587 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2588 }
2589
2590 evt->count = 0;
2591 evt->flags &= ~DWC3_EVENT_PENDING;
2592 ret = IRQ_HANDLED;
2593
2594 /* Unmask interrupt */
2595 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2596 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2597 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2598
2599 return ret;
2600}
2601
2602static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2603{
2604 struct dwc3 *dwc = _dwc;
2605 unsigned long flags;
2606 irqreturn_t ret = IRQ_NONE;
2607 int i;
2608
2609 spin_lock_irqsave(&dwc->lock, flags);
2610
2611 for (i = 0; i < dwc->num_event_buffers; i++)
2612 ret |= dwc3_process_event_buf(dwc, i);
2613
2614 spin_unlock_irqrestore(&dwc->lock, flags);
2615
2616 return ret;
2617}
2618
2619static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2620{
2621 struct dwc3_event_buffer *evt;
2622 u32 count;
2623 u32 reg;
2624
2625 evt = dwc->ev_buffs[buf];
2626
2627 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2628 count &= DWC3_GEVNTCOUNT_MASK;
2629 if (!count)
2630 return IRQ_NONE;
2631
2632 evt->count = count;
2633 evt->flags |= DWC3_EVENT_PENDING;
2634
2635 /* Mask interrupt */
2636 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2637 reg |= DWC3_GEVNTSIZ_INTMASK;
2638 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2639
2640 return IRQ_WAKE_THREAD;
2641}
2642
2643static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2644{
2645 struct dwc3 *dwc = _dwc;
2646 int i;
2647 irqreturn_t ret = IRQ_NONE;
2648
2649 spin_lock(&dwc->lock);
2650
2651 for (i = 0; i < dwc->num_event_buffers; i++) {
2652 irqreturn_t status;
2653
2654 status = dwc3_check_event_buf(dwc, i);
2655 if (status == IRQ_WAKE_THREAD)
2656 ret = status;
2657 }
2658
2659 spin_unlock(&dwc->lock);
2660
2661 return ret;
2662}
2663
2664/**
2665 * dwc3_gadget_init - Initializes gadget related registers
2666 * @dwc: pointer to our controller context structure
2667 *
2668 * Returns 0 on success otherwise negative errno.
2669 */
2670int dwc3_gadget_init(struct dwc3 *dwc)
2671{
2672 int ret;
2673
2674 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2675 &dwc->ctrl_req_addr, GFP_KERNEL);
2676 if (!dwc->ctrl_req) {
2677 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2678 ret = -ENOMEM;
2679 goto err0;
2680 }
2681
2682 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2683 &dwc->ep0_trb_addr, GFP_KERNEL);
2684 if (!dwc->ep0_trb) {
2685 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2686 ret = -ENOMEM;
2687 goto err1;
2688 }
2689
2690 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2691 if (!dwc->setup_buf) {
2692 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2693 ret = -ENOMEM;
2694 goto err2;
2695 }
2696
2697 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2698 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2699 GFP_KERNEL);
2700 if (!dwc->ep0_bounce) {
2701 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2702 ret = -ENOMEM;
2703 goto err3;
2704 }
2705
2706 dwc->gadget.ops = &dwc3_gadget_ops;
2707 dwc->gadget.max_speed = USB_SPEED_SUPER;
2708 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2709 dwc->gadget.sg_supported = true;
2710 dwc->gadget.name = "dwc3-gadget";
2711
2712 /*
2713 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2714 * on ep out.
2715 */
2716 dwc->gadget.quirk_ep_out_aligned_size = true;
2717
2718 /*
2719 * REVISIT: Here we should clear all pending IRQs to be
2720 * sure we're starting from a well known location.
2721 */
2722
2723 ret = dwc3_gadget_init_endpoints(dwc);
2724 if (ret)
2725 goto err4;
2726
2727 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2728 if (ret) {
2729 dev_err(dwc->dev, "failed to register udc\n");
2730 goto err4;
2731 }
2732
2733 return 0;
2734
2735err4:
2736 dwc3_gadget_free_endpoints(dwc);
2737 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2738 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2739
2740err3:
2741 kfree(dwc->setup_buf);
2742
2743err2:
2744 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2745 dwc->ep0_trb, dwc->ep0_trb_addr);
2746
2747err1:
2748 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2749 dwc->ctrl_req, dwc->ctrl_req_addr);
2750
2751err0:
2752 return ret;
2753}
2754
2755/* -------------------------------------------------------------------------- */
2756
2757void dwc3_gadget_exit(struct dwc3 *dwc)
2758{
2759 usb_del_gadget_udc(&dwc->gadget);
2760
2761 dwc3_gadget_free_endpoints(dwc);
2762
2763 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2764 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2765
2766 kfree(dwc->setup_buf);
2767
2768 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2769 dwc->ep0_trb, dwc->ep0_trb_addr);
2770
2771 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2772 dwc->ctrl_req, dwc->ctrl_req_addr);
2773}
2774
2775int dwc3_gadget_prepare(struct dwc3 *dwc)
2776{
2777 if (dwc->pullups_connected) {
2778 dwc3_gadget_disable_irq(dwc);
2779 dwc3_gadget_run_stop(dwc, true, true);
2780 }
2781
2782 return 0;
2783}
2784
2785void dwc3_gadget_complete(struct dwc3 *dwc)
2786{
2787 if (dwc->pullups_connected) {
2788 dwc3_gadget_enable_irq(dwc);
2789 dwc3_gadget_run_stop(dwc, true, false);
2790 }
2791}
2792
2793int dwc3_gadget_suspend(struct dwc3 *dwc)
2794{
2795 __dwc3_gadget_ep_disable(dwc->eps[0]);
2796 __dwc3_gadget_ep_disable(dwc->eps[1]);
2797
2798 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2799
2800 return 0;
2801}
2802
2803int dwc3_gadget_resume(struct dwc3 *dwc)
2804{
2805 struct dwc3_ep *dep;
2806 int ret;
2807
2808 /* Start with SuperSpeed Default */
2809 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2810
2811 dep = dwc->eps[0];
2812 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2813 false);
2814 if (ret)
2815 goto err0;
2816
2817 dep = dwc->eps[1];
2818 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2819 false);
2820 if (ret)
2821 goto err1;
2822
2823 /* begin to receive SETUP packets */
2824 dwc->ep0state = EP0_SETUP_PHASE;
2825 dwc3_ep0_out_start(dwc);
2826
2827 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2828
2829 return 0;
2830
2831err1:
2832 __dwc3_gadget_ep_disable(dwc->eps[0]);
2833
2834err0:
2835 return ret;
2836}