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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Enable PCIe link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/jiffies.h>
20#include <linux/delay.h>
21#include "../pci.h"
22
23#ifdef MODULE_PARAM_PREFIX
24#undef MODULE_PARAM_PREFIX
25#endif
26#define MODULE_PARAM_PREFIX "pcie_aspm."
27
28/* Note: those are not register definitions */
29#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
31#define ASPM_STATE_L1 (4) /* L1 state */
32#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
36#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
37#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
38#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
39 ASPM_STATE_L1_2_MASK)
40#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
41#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
42 ASPM_STATE_L1SS)
43
44struct aspm_latency {
45 u32 l0s; /* L0s latency (nsec) */
46 u32 l1; /* L1 latency (nsec) */
47};
48
49struct pcie_link_state {
50 struct pci_dev *pdev; /* Upstream component of the Link */
51 struct pci_dev *downstream; /* Downstream component, function 0 */
52 struct pcie_link_state *root; /* pointer to the root port link */
53 struct pcie_link_state *parent; /* pointer to the parent Link state */
54 struct list_head sibling; /* node in link_list */
55
56 /* ASPM state */
57 u32 aspm_support:7; /* Supported ASPM state */
58 u32 aspm_enabled:7; /* Enabled ASPM state */
59 u32 aspm_capable:7; /* Capable ASPM state with latency */
60 u32 aspm_default:7; /* Default ASPM state by BIOS */
61 u32 aspm_disable:7; /* Disabled ASPM state */
62
63 /* Clock PM state */
64 u32 clkpm_capable:1; /* Clock PM capable? */
65 u32 clkpm_enabled:1; /* Current Clock PM state */
66 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
67
68 /* Exit latencies */
69 struct aspm_latency latency_up; /* Upstream direction exit latency */
70 struct aspm_latency latency_dw; /* Downstream direction exit latency */
71 /*
72 * Endpoint acceptable latencies. A pcie downstream port only
73 * has one slot under it, so at most there are 8 functions.
74 */
75 struct aspm_latency acceptable[8];
76
77 /* L1 PM Substate info */
78 struct {
79 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
80 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
81 u32 ctl1; /* value to be programmed in ctl1 */
82 u32 ctl2; /* value to be programmed in ctl2 */
83 } l1ss;
84};
85
86static int aspm_disabled, aspm_force;
87static bool aspm_support_enabled = true;
88static DEFINE_MUTEX(aspm_lock);
89static LIST_HEAD(link_list);
90
91#define POLICY_DEFAULT 0 /* BIOS default setting */
92#define POLICY_PERFORMANCE 1 /* high performance */
93#define POLICY_POWERSAVE 2 /* high power saving */
94#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
95
96#ifdef CONFIG_PCIEASPM_PERFORMANCE
97static int aspm_policy = POLICY_PERFORMANCE;
98#elif defined CONFIG_PCIEASPM_POWERSAVE
99static int aspm_policy = POLICY_POWERSAVE;
100#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
101static int aspm_policy = POLICY_POWER_SUPERSAVE;
102#else
103static int aspm_policy;
104#endif
105
106static const char *policy_str[] = {
107 [POLICY_DEFAULT] = "default",
108 [POLICY_PERFORMANCE] = "performance",
109 [POLICY_POWERSAVE] = "powersave",
110 [POLICY_POWER_SUPERSAVE] = "powersupersave"
111};
112
113#define LINK_RETRAIN_TIMEOUT HZ
114
115static int policy_to_aspm_state(struct pcie_link_state *link)
116{
117 switch (aspm_policy) {
118 case POLICY_PERFORMANCE:
119 /* Disable ASPM and Clock PM */
120 return 0;
121 case POLICY_POWERSAVE:
122 /* Enable ASPM L0s/L1 */
123 return (ASPM_STATE_L0S | ASPM_STATE_L1);
124 case POLICY_POWER_SUPERSAVE:
125 /* Enable Everything */
126 return ASPM_STATE_ALL;
127 case POLICY_DEFAULT:
128 return link->aspm_default;
129 }
130 return 0;
131}
132
133static int policy_to_clkpm_state(struct pcie_link_state *link)
134{
135 switch (aspm_policy) {
136 case POLICY_PERFORMANCE:
137 /* Disable ASPM and Clock PM */
138 return 0;
139 case POLICY_POWERSAVE:
140 case POLICY_POWER_SUPERSAVE:
141 /* Enable Clock PM */
142 return 1;
143 case POLICY_DEFAULT:
144 return link->clkpm_default;
145 }
146 return 0;
147}
148
149static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
150{
151 struct pci_dev *child;
152 struct pci_bus *linkbus = link->pdev->subordinate;
153 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
154
155 list_for_each_entry(child, &linkbus->devices, bus_list)
156 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
157 PCI_EXP_LNKCTL_CLKREQ_EN,
158 val);
159 link->clkpm_enabled = !!enable;
160}
161
162static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
163{
164 /* Don't enable Clock PM if the link is not Clock PM capable */
165 if (!link->clkpm_capable)
166 enable = 0;
167 /* Need nothing if the specified equals to current state */
168 if (link->clkpm_enabled == enable)
169 return;
170 pcie_set_clkpm_nocheck(link, enable);
171}
172
173static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
174{
175 int capable = 1, enabled = 1;
176 u32 reg32;
177 u16 reg16;
178 struct pci_dev *child;
179 struct pci_bus *linkbus = link->pdev->subordinate;
180
181 /* All functions should have the same cap and state, take the worst */
182 list_for_each_entry(child, &linkbus->devices, bus_list) {
183 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
184 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
185 capable = 0;
186 enabled = 0;
187 break;
188 }
189 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
190 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
191 enabled = 0;
192 }
193 link->clkpm_enabled = enabled;
194 link->clkpm_default = enabled;
195 link->clkpm_capable = (blacklist) ? 0 : capable;
196}
197
198static bool pcie_retrain_link(struct pcie_link_state *link)
199{
200 struct pci_dev *parent = link->pdev;
201 unsigned long end_jiffies;
202 u16 reg16;
203
204 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
205 reg16 |= PCI_EXP_LNKCTL_RL;
206 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
207 if (parent->clear_retrain_link) {
208 /*
209 * Due to an erratum in some devices the Retrain Link bit
210 * needs to be cleared again manually to allow the link
211 * training to succeed.
212 */
213 reg16 &= ~PCI_EXP_LNKCTL_RL;
214 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
215 }
216
217 /* Wait for link training end. Break out after waiting for timeout */
218 end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
219 do {
220 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
221 if (!(reg16 & PCI_EXP_LNKSTA_LT))
222 break;
223 msleep(1);
224 } while (time_before(jiffies, end_jiffies));
225 return !(reg16 & PCI_EXP_LNKSTA_LT);
226}
227
228/*
229 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
230 * could use common clock. If they are, configure them to use the
231 * common clock. That will reduce the ASPM state exit latency.
232 */
233static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
234{
235 int same_clock = 1;
236 u16 reg16, parent_reg, child_reg[8];
237 struct pci_dev *child, *parent = link->pdev;
238 struct pci_bus *linkbus = parent->subordinate;
239 /*
240 * All functions of a slot should have the same Slot Clock
241 * Configuration, so just check one function
242 */
243 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
244 BUG_ON(!pci_is_pcie(child));
245
246 /* Check downstream component if bit Slot Clock Configuration is 1 */
247 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
248 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
249 same_clock = 0;
250
251 /* Check upstream component if bit Slot Clock Configuration is 1 */
252 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
253 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
254 same_clock = 0;
255
256 /* Port might be already in common clock mode */
257 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
258 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
259 bool consistent = true;
260
261 list_for_each_entry(child, &linkbus->devices, bus_list) {
262 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
263 ®16);
264 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
265 consistent = false;
266 break;
267 }
268 }
269 if (consistent)
270 return;
271 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
272 }
273
274 /* Configure downstream component, all functions */
275 list_for_each_entry(child, &linkbus->devices, bus_list) {
276 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
277 child_reg[PCI_FUNC(child->devfn)] = reg16;
278 if (same_clock)
279 reg16 |= PCI_EXP_LNKCTL_CCC;
280 else
281 reg16 &= ~PCI_EXP_LNKCTL_CCC;
282 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
283 }
284
285 /* Configure upstream component */
286 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
287 parent_reg = reg16;
288 if (same_clock)
289 reg16 |= PCI_EXP_LNKCTL_CCC;
290 else
291 reg16 &= ~PCI_EXP_LNKCTL_CCC;
292 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
293
294 if (pcie_retrain_link(link))
295 return;
296
297 /* Training failed. Restore common clock configurations */
298 pci_err(parent, "ASPM: Could not configure common clock\n");
299 list_for_each_entry(child, &linkbus->devices, bus_list)
300 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
301 child_reg[PCI_FUNC(child->devfn)]);
302 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
303}
304
305/* Convert L0s latency encoding to ns */
306static u32 calc_l0s_latency(u32 encoding)
307{
308 if (encoding == 0x7)
309 return (5 * 1000); /* > 4us */
310 return (64 << encoding);
311}
312
313/* Convert L0s acceptable latency encoding to ns */
314static u32 calc_l0s_acceptable(u32 encoding)
315{
316 if (encoding == 0x7)
317 return -1U;
318 return (64 << encoding);
319}
320
321/* Convert L1 latency encoding to ns */
322static u32 calc_l1_latency(u32 encoding)
323{
324 if (encoding == 0x7)
325 return (65 * 1000); /* > 64us */
326 return (1000 << encoding);
327}
328
329/* Convert L1 acceptable latency encoding to ns */
330static u32 calc_l1_acceptable(u32 encoding)
331{
332 if (encoding == 0x7)
333 return -1U;
334 return (1000 << encoding);
335}
336
337/* Convert L1SS T_pwr encoding to usec */
338static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
339{
340 switch (scale) {
341 case 0:
342 return val * 2;
343 case 1:
344 return val * 10;
345 case 2:
346 return val * 100;
347 }
348 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
349 return 0;
350}
351
352static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
353{
354 u32 threshold_ns = threshold_us * 1000;
355
356 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
357 if (threshold_ns < 32) {
358 *scale = 0;
359 *value = threshold_ns;
360 } else if (threshold_ns < 1024) {
361 *scale = 1;
362 *value = threshold_ns >> 5;
363 } else if (threshold_ns < 32768) {
364 *scale = 2;
365 *value = threshold_ns >> 10;
366 } else if (threshold_ns < 1048576) {
367 *scale = 3;
368 *value = threshold_ns >> 15;
369 } else if (threshold_ns < 33554432) {
370 *scale = 4;
371 *value = threshold_ns >> 20;
372 } else {
373 *scale = 5;
374 *value = threshold_ns >> 25;
375 }
376}
377
378struct aspm_register_info {
379 u32 support:2;
380 u32 enabled:2;
381 u32 latency_encoding_l0s;
382 u32 latency_encoding_l1;
383
384 /* L1 substates */
385 u32 l1ss_cap_ptr;
386 u32 l1ss_cap;
387 u32 l1ss_ctl1;
388 u32 l1ss_ctl2;
389};
390
391static void pcie_get_aspm_reg(struct pci_dev *pdev,
392 struct aspm_register_info *info)
393{
394 u16 reg16;
395 u32 reg32;
396
397 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
398 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
399 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
400 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
401 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
402 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
403
404 /* Read L1 PM substate capabilities */
405 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
406 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
407 if (!info->l1ss_cap_ptr)
408 return;
409 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
410 &info->l1ss_cap);
411 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
412 info->l1ss_cap = 0;
413 return;
414 }
415
416 /*
417 * If we don't have LTR for the entire path from the Root Complex
418 * to this device, we can't use ASPM L1.2 because it relies on the
419 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
420 */
421 if (!pdev->ltr_path)
422 info->l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
423
424 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
425 &info->l1ss_ctl1);
426 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
427 &info->l1ss_ctl2);
428}
429
430static void pcie_aspm_check_latency(struct pci_dev *endpoint)
431{
432 u32 latency, l1_switch_latency = 0;
433 struct aspm_latency *acceptable;
434 struct pcie_link_state *link;
435
436 /* Device not in D0 doesn't need latency check */
437 if ((endpoint->current_state != PCI_D0) &&
438 (endpoint->current_state != PCI_UNKNOWN))
439 return;
440
441 link = endpoint->bus->self->link_state;
442 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
443
444 while (link) {
445 /* Check upstream direction L0s latency */
446 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
447 (link->latency_up.l0s > acceptable->l0s))
448 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
449
450 /* Check downstream direction L0s latency */
451 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
452 (link->latency_dw.l0s > acceptable->l0s))
453 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
454 /*
455 * Check L1 latency.
456 * Every switch on the path to root complex need 1
457 * more microsecond for L1. Spec doesn't mention L0s.
458 *
459 * The exit latencies for L1 substates are not advertised
460 * by a device. Since the spec also doesn't mention a way
461 * to determine max latencies introduced by enabling L1
462 * substates on the components, it is not clear how to do
463 * a L1 substate exit latency check. We assume that the
464 * L1 exit latencies advertised by a device include L1
465 * substate latencies (and hence do not do any check).
466 */
467 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
468 if ((link->aspm_capable & ASPM_STATE_L1) &&
469 (latency + l1_switch_latency > acceptable->l1))
470 link->aspm_capable &= ~ASPM_STATE_L1;
471 l1_switch_latency += 1000;
472
473 link = link->parent;
474 }
475}
476
477/*
478 * The L1 PM substate capability is only implemented in function 0 in a
479 * multi function device.
480 */
481static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
482{
483 struct pci_dev *child;
484
485 list_for_each_entry(child, &linkbus->devices, bus_list)
486 if (PCI_FUNC(child->devfn) == 0)
487 return child;
488 return NULL;
489}
490
491/* Calculate L1.2 PM substate timing parameters */
492static void aspm_calc_l1ss_info(struct pcie_link_state *link,
493 struct aspm_register_info *upreg,
494 struct aspm_register_info *dwreg)
495{
496 u32 val1, val2, scale1, scale2;
497 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
498
499 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
500 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
501 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
502
503 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
504 return;
505
506 /* Choose the greater of the two Port Common_Mode_Restore_Times */
507 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
508 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
509 t_common_mode = max(val1, val2);
510
511 /* Choose the greater of the two Port T_POWER_ON times */
512 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
513 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
514 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
515 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
516
517 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
518 calc_l1ss_pwron(link->downstream, scale2, val2)) {
519 link->l1ss.ctl2 |= scale1 | (val1 << 3);
520 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
521 } else {
522 link->l1ss.ctl2 |= scale2 | (val2 << 3);
523 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
524 }
525
526 /*
527 * Set LTR_L1.2_THRESHOLD to the time required to transition the
528 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
529 * downstream devices report (via LTR) that they can tolerate at
530 * least that much latency.
531 *
532 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
533 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
534 * least 4us.
535 */
536 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
537 encode_l12_threshold(l1_2_threshold, &scale, &value);
538 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
539}
540
541static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
542{
543 struct pci_dev *child = link->downstream, *parent = link->pdev;
544 struct pci_bus *linkbus = parent->subordinate;
545 struct aspm_register_info upreg, dwreg;
546
547 if (blacklist) {
548 /* Set enabled/disable so that we will disable ASPM later */
549 link->aspm_enabled = ASPM_STATE_ALL;
550 link->aspm_disable = ASPM_STATE_ALL;
551 return;
552 }
553
554 /* Get upstream/downstream components' register state */
555 pcie_get_aspm_reg(parent, &upreg);
556 pcie_get_aspm_reg(child, &dwreg);
557
558 /*
559 * If ASPM not supported, don't mess with the clocks and link,
560 * bail out now.
561 */
562 if (!(upreg.support & dwreg.support))
563 return;
564
565 /* Configure common clock before checking latencies */
566 pcie_aspm_configure_common_clock(link);
567
568 /*
569 * Re-read upstream/downstream components' register state
570 * after clock configuration
571 */
572 pcie_get_aspm_reg(parent, &upreg);
573 pcie_get_aspm_reg(child, &dwreg);
574
575 /*
576 * Setup L0s state
577 *
578 * Note that we must not enable L0s in either direction on a
579 * given link unless components on both sides of the link each
580 * support L0s.
581 */
582 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
583 link->aspm_support |= ASPM_STATE_L0S;
584 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
585 link->aspm_enabled |= ASPM_STATE_L0S_UP;
586 if (upreg.enabled & PCIE_LINK_STATE_L0S)
587 link->aspm_enabled |= ASPM_STATE_L0S_DW;
588 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
589 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
590
591 /* Setup L1 state */
592 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
593 link->aspm_support |= ASPM_STATE_L1;
594 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
595 link->aspm_enabled |= ASPM_STATE_L1;
596 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
597 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
598
599 /* Setup L1 substate */
600 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
601 link->aspm_support |= ASPM_STATE_L1_1;
602 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
603 link->aspm_support |= ASPM_STATE_L1_2;
604 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
605 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
606 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
607 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
608
609 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
610 link->aspm_enabled |= ASPM_STATE_L1_1;
611 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
612 link->aspm_enabled |= ASPM_STATE_L1_2;
613 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
614 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
615 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
616 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
617
618 if (link->aspm_support & ASPM_STATE_L1SS)
619 aspm_calc_l1ss_info(link, &upreg, &dwreg);
620
621 /* Save default state */
622 link->aspm_default = link->aspm_enabled;
623
624 /* Setup initial capable state. Will be updated later */
625 link->aspm_capable = link->aspm_support;
626 /*
627 * If the downstream component has pci bridge function, don't
628 * do ASPM for now.
629 */
630 list_for_each_entry(child, &linkbus->devices, bus_list) {
631 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
632 link->aspm_disable = ASPM_STATE_ALL;
633 break;
634 }
635 }
636
637 /* Get and check endpoint acceptable latencies */
638 list_for_each_entry(child, &linkbus->devices, bus_list) {
639 u32 reg32, encoding;
640 struct aspm_latency *acceptable =
641 &link->acceptable[PCI_FUNC(child->devfn)];
642
643 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
644 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
645 continue;
646
647 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
648 /* Calculate endpoint L0s acceptable latency */
649 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
650 acceptable->l0s = calc_l0s_acceptable(encoding);
651 /* Calculate endpoint L1 acceptable latency */
652 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
653 acceptable->l1 = calc_l1_acceptable(encoding);
654
655 pcie_aspm_check_latency(child);
656 }
657}
658
659static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
660 u32 clear, u32 set)
661{
662 u32 val;
663
664 pci_read_config_dword(pdev, pos, &val);
665 val &= ~clear;
666 val |= set;
667 pci_write_config_dword(pdev, pos, val);
668}
669
670/* Configure the ASPM L1 substates */
671static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
672{
673 u32 val, enable_req;
674 struct pci_dev *child = link->downstream, *parent = link->pdev;
675 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
676 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
677
678 enable_req = (link->aspm_enabled ^ state) & state;
679
680 /*
681 * Here are the rules specified in the PCIe spec for enabling L1SS:
682 * - When enabling L1.x, enable bit at parent first, then at child
683 * - When disabling L1.x, disable bit at child first, then at parent
684 * - When enabling ASPM L1.x, need to disable L1
685 * (at child followed by parent).
686 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
687 * parameters
688 *
689 * To keep it simple, disable all L1SS bits first, and later enable
690 * what is needed.
691 */
692
693 /* Disable all L1 substates */
694 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
695 PCI_L1SS_CTL1_L1SS_MASK, 0);
696 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
697 PCI_L1SS_CTL1_L1SS_MASK, 0);
698 /*
699 * If needed, disable L1, and it gets enabled later
700 * in pcie_config_aspm_link().
701 */
702 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
703 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
704 PCI_EXP_LNKCTL_ASPM_L1, 0);
705 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
706 PCI_EXP_LNKCTL_ASPM_L1, 0);
707 }
708
709 if (enable_req & ASPM_STATE_L1_2_MASK) {
710
711 /* Program T_POWER_ON times in both ports */
712 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
713 link->l1ss.ctl2);
714 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
715 link->l1ss.ctl2);
716
717 /* Program Common_Mode_Restore_Time in upstream device */
718 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
719 PCI_L1SS_CTL1_CM_RESTORE_TIME,
720 link->l1ss.ctl1);
721
722 /* Program LTR_L1.2_THRESHOLD time in both ports */
723 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
724 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
725 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
726 link->l1ss.ctl1);
727 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
728 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
729 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
730 link->l1ss.ctl1);
731 }
732
733 val = 0;
734 if (state & ASPM_STATE_L1_1)
735 val |= PCI_L1SS_CTL1_ASPM_L1_1;
736 if (state & ASPM_STATE_L1_2)
737 val |= PCI_L1SS_CTL1_ASPM_L1_2;
738 if (state & ASPM_STATE_L1_1_PCIPM)
739 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
740 if (state & ASPM_STATE_L1_2_PCIPM)
741 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
742
743 /* Enable what we need to enable */
744 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
745 PCI_L1SS_CAP_L1_PM_SS, val);
746 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
747 PCI_L1SS_CAP_L1_PM_SS, val);
748}
749
750static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
751{
752 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
753 PCI_EXP_LNKCTL_ASPMC, val);
754}
755
756static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
757{
758 u32 upstream = 0, dwstream = 0;
759 struct pci_dev *child = link->downstream, *parent = link->pdev;
760 struct pci_bus *linkbus = parent->subordinate;
761
762 /* Enable only the states that were not explicitly disabled */
763 state &= (link->aspm_capable & ~link->aspm_disable);
764
765 /* Can't enable any substates if L1 is not enabled */
766 if (!(state & ASPM_STATE_L1))
767 state &= ~ASPM_STATE_L1SS;
768
769 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
770 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
771 state &= ~ASPM_STATE_L1_SS_PCIPM;
772 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
773 }
774
775 /* Nothing to do if the link is already in the requested state */
776 if (link->aspm_enabled == state)
777 return;
778 /* Convert ASPM state to upstream/downstream ASPM register state */
779 if (state & ASPM_STATE_L0S_UP)
780 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
781 if (state & ASPM_STATE_L0S_DW)
782 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
783 if (state & ASPM_STATE_L1) {
784 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
785 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
786 }
787
788 if (link->aspm_capable & ASPM_STATE_L1SS)
789 pcie_config_aspm_l1ss(link, state);
790
791 /*
792 * Spec 2.0 suggests all functions should be configured the
793 * same setting for ASPM. Enabling ASPM L1 should be done in
794 * upstream component first and then downstream, and vice
795 * versa for disabling ASPM L1. Spec doesn't mention L0S.
796 */
797 if (state & ASPM_STATE_L1)
798 pcie_config_aspm_dev(parent, upstream);
799 list_for_each_entry(child, &linkbus->devices, bus_list)
800 pcie_config_aspm_dev(child, dwstream);
801 if (!(state & ASPM_STATE_L1))
802 pcie_config_aspm_dev(parent, upstream);
803
804 link->aspm_enabled = state;
805}
806
807static void pcie_config_aspm_path(struct pcie_link_state *link)
808{
809 while (link) {
810 pcie_config_aspm_link(link, policy_to_aspm_state(link));
811 link = link->parent;
812 }
813}
814
815static void free_link_state(struct pcie_link_state *link)
816{
817 link->pdev->link_state = NULL;
818 kfree(link);
819}
820
821static int pcie_aspm_sanity_check(struct pci_dev *pdev)
822{
823 struct pci_dev *child;
824 u32 reg32;
825
826 /*
827 * Some functions in a slot might not all be PCIe functions,
828 * very strange. Disable ASPM for the whole slot
829 */
830 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
831 if (!pci_is_pcie(child))
832 return -EINVAL;
833
834 /*
835 * If ASPM is disabled then we're not going to change
836 * the BIOS state. It's safe to continue even if it's a
837 * pre-1.1 device
838 */
839
840 if (aspm_disabled)
841 continue;
842
843 /*
844 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
845 * RBER bit to determine if a function is 1.1 version device
846 */
847 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
848 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
849 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
850 return -EINVAL;
851 }
852 }
853 return 0;
854}
855
856static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
857{
858 struct pcie_link_state *link;
859
860 link = kzalloc(sizeof(*link), GFP_KERNEL);
861 if (!link)
862 return NULL;
863
864 INIT_LIST_HEAD(&link->sibling);
865 link->pdev = pdev;
866 link->downstream = pci_function_0(pdev->subordinate);
867
868 /*
869 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
870 * hierarchies. Note that some PCIe host implementations omit
871 * the root ports entirely, in which case a downstream port on
872 * a switch may become the root of the link state chain for all
873 * its subordinate endpoints.
874 */
875 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
876 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
877 !pdev->bus->parent->self) {
878 link->root = link;
879 } else {
880 struct pcie_link_state *parent;
881
882 parent = pdev->bus->parent->self->link_state;
883 if (!parent) {
884 kfree(link);
885 return NULL;
886 }
887
888 link->parent = parent;
889 link->root = link->parent->root;
890 }
891
892 list_add(&link->sibling, &link_list);
893 pdev->link_state = link;
894 return link;
895}
896
897/*
898 * pcie_aspm_init_link_state: Initiate PCI express link state.
899 * It is called after the pcie and its children devices are scanned.
900 * @pdev: the root port or switch downstream port
901 */
902void pcie_aspm_init_link_state(struct pci_dev *pdev)
903{
904 struct pcie_link_state *link;
905 int blacklist = !!pcie_aspm_sanity_check(pdev);
906
907 if (!aspm_support_enabled)
908 return;
909
910 if (pdev->link_state)
911 return;
912
913 /*
914 * We allocate pcie_link_state for the component on the upstream
915 * end of a Link, so there's nothing to do unless this device is
916 * downstream port.
917 */
918 if (!pcie_downstream_port(pdev))
919 return;
920
921 /* VIA has a strange chipset, root port is under a bridge */
922 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
923 pdev->bus->self)
924 return;
925
926 down_read(&pci_bus_sem);
927 if (list_empty(&pdev->subordinate->devices))
928 goto out;
929
930 mutex_lock(&aspm_lock);
931 link = alloc_pcie_link_state(pdev);
932 if (!link)
933 goto unlock;
934 /*
935 * Setup initial ASPM state. Note that we need to configure
936 * upstream links also because capable state of them can be
937 * update through pcie_aspm_cap_init().
938 */
939 pcie_aspm_cap_init(link, blacklist);
940
941 /* Setup initial Clock PM state */
942 pcie_clkpm_cap_init(link, blacklist);
943
944 /*
945 * At this stage drivers haven't had an opportunity to change the
946 * link policy setting. Enabling ASPM on broken hardware can cripple
947 * it even before the driver has had a chance to disable ASPM, so
948 * default to a safe level right now. If we're enabling ASPM beyond
949 * the BIOS's expectation, we'll do so once pci_enable_device() is
950 * called.
951 */
952 if (aspm_policy != POLICY_POWERSAVE &&
953 aspm_policy != POLICY_POWER_SUPERSAVE) {
954 pcie_config_aspm_path(link);
955 pcie_set_clkpm(link, policy_to_clkpm_state(link));
956 }
957
958unlock:
959 mutex_unlock(&aspm_lock);
960out:
961 up_read(&pci_bus_sem);
962}
963
964/* Recheck latencies and update aspm_capable for links under the root */
965static void pcie_update_aspm_capable(struct pcie_link_state *root)
966{
967 struct pcie_link_state *link;
968 BUG_ON(root->parent);
969 list_for_each_entry(link, &link_list, sibling) {
970 if (link->root != root)
971 continue;
972 link->aspm_capable = link->aspm_support;
973 }
974 list_for_each_entry(link, &link_list, sibling) {
975 struct pci_dev *child;
976 struct pci_bus *linkbus = link->pdev->subordinate;
977 if (link->root != root)
978 continue;
979 list_for_each_entry(child, &linkbus->devices, bus_list) {
980 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
981 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
982 continue;
983 pcie_aspm_check_latency(child);
984 }
985 }
986}
987
988/* @pdev: the endpoint device */
989void pcie_aspm_exit_link_state(struct pci_dev *pdev)
990{
991 struct pci_dev *parent = pdev->bus->self;
992 struct pcie_link_state *link, *root, *parent_link;
993
994 if (!parent || !parent->link_state)
995 return;
996
997 down_read(&pci_bus_sem);
998 mutex_lock(&aspm_lock);
999 /*
1000 * All PCIe functions are in one slot, remove one function will remove
1001 * the whole slot, so just wait until we are the last function left.
1002 */
1003 if (!list_empty(&parent->subordinate->devices))
1004 goto out;
1005
1006 link = parent->link_state;
1007 root = link->root;
1008 parent_link = link->parent;
1009
1010 /* All functions are removed, so just disable ASPM for the link */
1011 pcie_config_aspm_link(link, 0);
1012 list_del(&link->sibling);
1013 /* Clock PM is for endpoint device */
1014 free_link_state(link);
1015
1016 /* Recheck latencies and configure upstream links */
1017 if (parent_link) {
1018 pcie_update_aspm_capable(root);
1019 pcie_config_aspm_path(parent_link);
1020 }
1021out:
1022 mutex_unlock(&aspm_lock);
1023 up_read(&pci_bus_sem);
1024}
1025
1026/* @pdev: the root port or switch downstream port */
1027void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1028{
1029 struct pcie_link_state *link = pdev->link_state;
1030
1031 if (aspm_disabled || !link)
1032 return;
1033 /*
1034 * Devices changed PM state, we should recheck if latency
1035 * meets all functions' requirement
1036 */
1037 down_read(&pci_bus_sem);
1038 mutex_lock(&aspm_lock);
1039 pcie_update_aspm_capable(link->root);
1040 pcie_config_aspm_path(link);
1041 mutex_unlock(&aspm_lock);
1042 up_read(&pci_bus_sem);
1043}
1044
1045void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1046{
1047 struct pcie_link_state *link = pdev->link_state;
1048
1049 if (aspm_disabled || !link)
1050 return;
1051
1052 if (aspm_policy != POLICY_POWERSAVE &&
1053 aspm_policy != POLICY_POWER_SUPERSAVE)
1054 return;
1055
1056 down_read(&pci_bus_sem);
1057 mutex_lock(&aspm_lock);
1058 pcie_config_aspm_path(link);
1059 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1060 mutex_unlock(&aspm_lock);
1061 up_read(&pci_bus_sem);
1062}
1063
1064static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1065{
1066 struct pci_dev *parent = pdev->bus->self;
1067 struct pcie_link_state *link;
1068
1069 if (!pci_is_pcie(pdev))
1070 return 0;
1071
1072 if (pcie_downstream_port(pdev))
1073 parent = pdev;
1074 if (!parent || !parent->link_state)
1075 return -EINVAL;
1076
1077 /*
1078 * A driver requested that ASPM be disabled on this device, but
1079 * if we don't have permission to manage ASPM (e.g., on ACPI
1080 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1081 * the _OSC method), we can't honor that request. Windows has
1082 * a similar mechanism using "PciASPMOptOut", which is also
1083 * ignored in this situation.
1084 */
1085 if (aspm_disabled) {
1086 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1087 return -EPERM;
1088 }
1089
1090 if (sem)
1091 down_read(&pci_bus_sem);
1092 mutex_lock(&aspm_lock);
1093 link = parent->link_state;
1094 if (state & PCIE_LINK_STATE_L0S)
1095 link->aspm_disable |= ASPM_STATE_L0S;
1096 if (state & PCIE_LINK_STATE_L1)
1097 link->aspm_disable |= ASPM_STATE_L1;
1098 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1099
1100 if (state & PCIE_LINK_STATE_CLKPM) {
1101 link->clkpm_capable = 0;
1102 pcie_set_clkpm(link, 0);
1103 }
1104 mutex_unlock(&aspm_lock);
1105 if (sem)
1106 up_read(&pci_bus_sem);
1107
1108 return 0;
1109}
1110
1111int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1112{
1113 return __pci_disable_link_state(pdev, state, false);
1114}
1115EXPORT_SYMBOL(pci_disable_link_state_locked);
1116
1117/**
1118 * pci_disable_link_state - Disable device's link state, so the link will
1119 * never enter specific states. Note that if the BIOS didn't grant ASPM
1120 * control to the OS, this does nothing because we can't touch the LNKCTL
1121 * register. Returns 0 or a negative errno.
1122 *
1123 * @pdev: PCI device
1124 * @state: ASPM link state to disable
1125 */
1126int pci_disable_link_state(struct pci_dev *pdev, int state)
1127{
1128 return __pci_disable_link_state(pdev, state, true);
1129}
1130EXPORT_SYMBOL(pci_disable_link_state);
1131
1132static int pcie_aspm_set_policy(const char *val,
1133 const struct kernel_param *kp)
1134{
1135 int i;
1136 struct pcie_link_state *link;
1137
1138 if (aspm_disabled)
1139 return -EPERM;
1140 i = sysfs_match_string(policy_str, val);
1141 if (i < 0)
1142 return i;
1143 if (i == aspm_policy)
1144 return 0;
1145
1146 down_read(&pci_bus_sem);
1147 mutex_lock(&aspm_lock);
1148 aspm_policy = i;
1149 list_for_each_entry(link, &link_list, sibling) {
1150 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1151 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1152 }
1153 mutex_unlock(&aspm_lock);
1154 up_read(&pci_bus_sem);
1155 return 0;
1156}
1157
1158static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1159{
1160 int i, cnt = 0;
1161 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1162 if (i == aspm_policy)
1163 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1164 else
1165 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1166 return cnt;
1167}
1168
1169module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1170 NULL, 0644);
1171
1172/**
1173 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1174 * @pdev: Target device.
1175 */
1176bool pcie_aspm_enabled(struct pci_dev *pdev)
1177{
1178 struct pci_dev *bridge = pci_upstream_bridge(pdev);
1179 bool ret;
1180
1181 if (!bridge)
1182 return false;
1183
1184 mutex_lock(&aspm_lock);
1185 ret = bridge->link_state ? !!bridge->link_state->aspm_enabled : false;
1186 mutex_unlock(&aspm_lock);
1187
1188 return ret;
1189}
1190EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1191
1192#ifdef CONFIG_PCIEASPM_DEBUG
1193static ssize_t link_state_show(struct device *dev,
1194 struct device_attribute *attr,
1195 char *buf)
1196{
1197 struct pci_dev *pci_device = to_pci_dev(dev);
1198 struct pcie_link_state *link_state = pci_device->link_state;
1199
1200 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1201}
1202
1203static ssize_t link_state_store(struct device *dev,
1204 struct device_attribute *attr,
1205 const char *buf,
1206 size_t n)
1207{
1208 struct pci_dev *pdev = to_pci_dev(dev);
1209 struct pcie_link_state *link, *root = pdev->link_state->root;
1210 u32 state;
1211
1212 if (aspm_disabled)
1213 return -EPERM;
1214
1215 if (kstrtouint(buf, 10, &state))
1216 return -EINVAL;
1217 if ((state & ~ASPM_STATE_ALL) != 0)
1218 return -EINVAL;
1219
1220 down_read(&pci_bus_sem);
1221 mutex_lock(&aspm_lock);
1222 list_for_each_entry(link, &link_list, sibling) {
1223 if (link->root != root)
1224 continue;
1225 pcie_config_aspm_link(link, state);
1226 }
1227 mutex_unlock(&aspm_lock);
1228 up_read(&pci_bus_sem);
1229 return n;
1230}
1231
1232static ssize_t clk_ctl_show(struct device *dev,
1233 struct device_attribute *attr,
1234 char *buf)
1235{
1236 struct pci_dev *pci_device = to_pci_dev(dev);
1237 struct pcie_link_state *link_state = pci_device->link_state;
1238
1239 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1240}
1241
1242static ssize_t clk_ctl_store(struct device *dev,
1243 struct device_attribute *attr,
1244 const char *buf,
1245 size_t n)
1246{
1247 struct pci_dev *pdev = to_pci_dev(dev);
1248 bool state;
1249
1250 if (strtobool(buf, &state))
1251 return -EINVAL;
1252
1253 down_read(&pci_bus_sem);
1254 mutex_lock(&aspm_lock);
1255 pcie_set_clkpm_nocheck(pdev->link_state, state);
1256 mutex_unlock(&aspm_lock);
1257 up_read(&pci_bus_sem);
1258
1259 return n;
1260}
1261
1262static DEVICE_ATTR_RW(link_state);
1263static DEVICE_ATTR_RW(clk_ctl);
1264
1265static char power_group[] = "power";
1266void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1267{
1268 struct pcie_link_state *link_state = pdev->link_state;
1269
1270 if (!link_state)
1271 return;
1272
1273 if (link_state->aspm_support)
1274 sysfs_add_file_to_group(&pdev->dev.kobj,
1275 &dev_attr_link_state.attr, power_group);
1276 if (link_state->clkpm_capable)
1277 sysfs_add_file_to_group(&pdev->dev.kobj,
1278 &dev_attr_clk_ctl.attr, power_group);
1279}
1280
1281void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1282{
1283 struct pcie_link_state *link_state = pdev->link_state;
1284
1285 if (!link_state)
1286 return;
1287
1288 if (link_state->aspm_support)
1289 sysfs_remove_file_from_group(&pdev->dev.kobj,
1290 &dev_attr_link_state.attr, power_group);
1291 if (link_state->clkpm_capable)
1292 sysfs_remove_file_from_group(&pdev->dev.kobj,
1293 &dev_attr_clk_ctl.attr, power_group);
1294}
1295#endif
1296
1297static int __init pcie_aspm_disable(char *str)
1298{
1299 if (!strcmp(str, "off")) {
1300 aspm_policy = POLICY_DEFAULT;
1301 aspm_disabled = 1;
1302 aspm_support_enabled = false;
1303 printk(KERN_INFO "PCIe ASPM is disabled\n");
1304 } else if (!strcmp(str, "force")) {
1305 aspm_force = 1;
1306 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1307 }
1308 return 1;
1309}
1310
1311__setup("pcie_aspm=", pcie_aspm_disable);
1312
1313void pcie_no_aspm(void)
1314{
1315 /*
1316 * Disabling ASPM is intended to prevent the kernel from modifying
1317 * existing hardware state, not to clear existing state. To that end:
1318 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1319 * (b) prevent userspace from changing policy
1320 */
1321 if (!aspm_force) {
1322 aspm_policy = POLICY_DEFAULT;
1323 aspm_disabled = 1;
1324 }
1325}
1326
1327bool pcie_aspm_support_enabled(void)
1328{
1329 return aspm_support_enabled;
1330}
1331EXPORT_SYMBOL(pcie_aspm_support_enabled);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Enable PCIe link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/jiffies.h>
20#include <linux/delay.h>
21#include <linux/pci-aspm.h>
22#include "../pci.h"
23
24#ifdef MODULE_PARAM_PREFIX
25#undef MODULE_PARAM_PREFIX
26#endif
27#define MODULE_PARAM_PREFIX "pcie_aspm."
28
29/* Note: those are not register definitions */
30#define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31#define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32#define ASPM_STATE_L1 (4) /* L1 state */
33#define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34#define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35#define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36#define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
37#define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
38#define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
39#define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
40 ASPM_STATE_L1_2_MASK)
41#define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
42#define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
43 ASPM_STATE_L1SS)
44
45struct aspm_latency {
46 u32 l0s; /* L0s latency (nsec) */
47 u32 l1; /* L1 latency (nsec) */
48};
49
50struct pcie_link_state {
51 struct pci_dev *pdev; /* Upstream component of the Link */
52 struct pci_dev *downstream; /* Downstream component, function 0 */
53 struct pcie_link_state *root; /* pointer to the root port link */
54 struct pcie_link_state *parent; /* pointer to the parent Link state */
55 struct list_head sibling; /* node in link_list */
56 struct list_head children; /* list of child link states */
57 struct list_head link; /* node in parent's children list */
58
59 /* ASPM state */
60 u32 aspm_support:7; /* Supported ASPM state */
61 u32 aspm_enabled:7; /* Enabled ASPM state */
62 u32 aspm_capable:7; /* Capable ASPM state with latency */
63 u32 aspm_default:7; /* Default ASPM state by BIOS */
64 u32 aspm_disable:7; /* Disabled ASPM state */
65
66 /* Clock PM state */
67 u32 clkpm_capable:1; /* Clock PM capable? */
68 u32 clkpm_enabled:1; /* Current Clock PM state */
69 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
70
71 /* Exit latencies */
72 struct aspm_latency latency_up; /* Upstream direction exit latency */
73 struct aspm_latency latency_dw; /* Downstream direction exit latency */
74 /*
75 * Endpoint acceptable latencies. A pcie downstream port only
76 * has one slot under it, so at most there are 8 functions.
77 */
78 struct aspm_latency acceptable[8];
79
80 /* L1 PM Substate info */
81 struct {
82 u32 up_cap_ptr; /* L1SS cap ptr in upstream dev */
83 u32 dw_cap_ptr; /* L1SS cap ptr in downstream dev */
84 u32 ctl1; /* value to be programmed in ctl1 */
85 u32 ctl2; /* value to be programmed in ctl2 */
86 } l1ss;
87};
88
89static int aspm_disabled, aspm_force;
90static bool aspm_support_enabled = true;
91static DEFINE_MUTEX(aspm_lock);
92static LIST_HEAD(link_list);
93
94#define POLICY_DEFAULT 0 /* BIOS default setting */
95#define POLICY_PERFORMANCE 1 /* high performance */
96#define POLICY_POWERSAVE 2 /* high power saving */
97#define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
98
99#ifdef CONFIG_PCIEASPM_PERFORMANCE
100static int aspm_policy = POLICY_PERFORMANCE;
101#elif defined CONFIG_PCIEASPM_POWERSAVE
102static int aspm_policy = POLICY_POWERSAVE;
103#elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
104static int aspm_policy = POLICY_POWER_SUPERSAVE;
105#else
106static int aspm_policy;
107#endif
108
109static const char *policy_str[] = {
110 [POLICY_DEFAULT] = "default",
111 [POLICY_PERFORMANCE] = "performance",
112 [POLICY_POWERSAVE] = "powersave",
113 [POLICY_POWER_SUPERSAVE] = "powersupersave"
114};
115
116#define LINK_RETRAIN_TIMEOUT HZ
117
118static int policy_to_aspm_state(struct pcie_link_state *link)
119{
120 switch (aspm_policy) {
121 case POLICY_PERFORMANCE:
122 /* Disable ASPM and Clock PM */
123 return 0;
124 case POLICY_POWERSAVE:
125 /* Enable ASPM L0s/L1 */
126 return (ASPM_STATE_L0S | ASPM_STATE_L1);
127 case POLICY_POWER_SUPERSAVE:
128 /* Enable Everything */
129 return ASPM_STATE_ALL;
130 case POLICY_DEFAULT:
131 return link->aspm_default;
132 }
133 return 0;
134}
135
136static int policy_to_clkpm_state(struct pcie_link_state *link)
137{
138 switch (aspm_policy) {
139 case POLICY_PERFORMANCE:
140 /* Disable ASPM and Clock PM */
141 return 0;
142 case POLICY_POWERSAVE:
143 case POLICY_POWER_SUPERSAVE:
144 /* Enable Clock PM */
145 return 1;
146 case POLICY_DEFAULT:
147 return link->clkpm_default;
148 }
149 return 0;
150}
151
152static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
153{
154 struct pci_dev *child;
155 struct pci_bus *linkbus = link->pdev->subordinate;
156 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
157
158 list_for_each_entry(child, &linkbus->devices, bus_list)
159 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
160 PCI_EXP_LNKCTL_CLKREQ_EN,
161 val);
162 link->clkpm_enabled = !!enable;
163}
164
165static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
166{
167 /* Don't enable Clock PM if the link is not Clock PM capable */
168 if (!link->clkpm_capable)
169 enable = 0;
170 /* Need nothing if the specified equals to current state */
171 if (link->clkpm_enabled == enable)
172 return;
173 pcie_set_clkpm_nocheck(link, enable);
174}
175
176static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
177{
178 int capable = 1, enabled = 1;
179 u32 reg32;
180 u16 reg16;
181 struct pci_dev *child;
182 struct pci_bus *linkbus = link->pdev->subordinate;
183
184 /* All functions should have the same cap and state, take the worst */
185 list_for_each_entry(child, &linkbus->devices, bus_list) {
186 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
187 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
188 capable = 0;
189 enabled = 0;
190 break;
191 }
192 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
193 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
194 enabled = 0;
195 }
196 link->clkpm_enabled = enabled;
197 link->clkpm_default = enabled;
198 link->clkpm_capable = (blacklist) ? 0 : capable;
199}
200
201/*
202 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
203 * could use common clock. If they are, configure them to use the
204 * common clock. That will reduce the ASPM state exit latency.
205 */
206static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
207{
208 int same_clock = 1;
209 u16 reg16, parent_reg, child_reg[8];
210 unsigned long start_jiffies;
211 struct pci_dev *child, *parent = link->pdev;
212 struct pci_bus *linkbus = parent->subordinate;
213 /*
214 * All functions of a slot should have the same Slot Clock
215 * Configuration, so just check one function
216 */
217 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
218 BUG_ON(!pci_is_pcie(child));
219
220 /* Check downstream component if bit Slot Clock Configuration is 1 */
221 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
222 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
223 same_clock = 0;
224
225 /* Check upstream component if bit Slot Clock Configuration is 1 */
226 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
227 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
228 same_clock = 0;
229
230 /* Port might be already in common clock mode */
231 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
232 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
233 bool consistent = true;
234
235 list_for_each_entry(child, &linkbus->devices, bus_list) {
236 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
237 ®16);
238 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
239 consistent = false;
240 break;
241 }
242 }
243 if (consistent)
244 return;
245 pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n");
246 }
247
248 /* Configure downstream component, all functions */
249 list_for_each_entry(child, &linkbus->devices, bus_list) {
250 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
251 child_reg[PCI_FUNC(child->devfn)] = reg16;
252 if (same_clock)
253 reg16 |= PCI_EXP_LNKCTL_CCC;
254 else
255 reg16 &= ~PCI_EXP_LNKCTL_CCC;
256 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
257 }
258
259 /* Configure upstream component */
260 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
261 parent_reg = reg16;
262 if (same_clock)
263 reg16 |= PCI_EXP_LNKCTL_CCC;
264 else
265 reg16 &= ~PCI_EXP_LNKCTL_CCC;
266 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
267
268 /* Retrain link */
269 reg16 |= PCI_EXP_LNKCTL_RL;
270 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
271
272 /* Wait for link training end. Break out after waiting for timeout */
273 start_jiffies = jiffies;
274 for (;;) {
275 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
276 if (!(reg16 & PCI_EXP_LNKSTA_LT))
277 break;
278 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT))
279 break;
280 msleep(1);
281 }
282 if (!(reg16 & PCI_EXP_LNKSTA_LT))
283 return;
284
285 /* Training failed. Restore common clock configurations */
286 pci_err(parent, "ASPM: Could not configure common clock\n");
287 list_for_each_entry(child, &linkbus->devices, bus_list)
288 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
289 child_reg[PCI_FUNC(child->devfn)]);
290 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
291}
292
293/* Convert L0s latency encoding to ns */
294static u32 calc_l0s_latency(u32 encoding)
295{
296 if (encoding == 0x7)
297 return (5 * 1000); /* > 4us */
298 return (64 << encoding);
299}
300
301/* Convert L0s acceptable latency encoding to ns */
302static u32 calc_l0s_acceptable(u32 encoding)
303{
304 if (encoding == 0x7)
305 return -1U;
306 return (64 << encoding);
307}
308
309/* Convert L1 latency encoding to ns */
310static u32 calc_l1_latency(u32 encoding)
311{
312 if (encoding == 0x7)
313 return (65 * 1000); /* > 64us */
314 return (1000 << encoding);
315}
316
317/* Convert L1 acceptable latency encoding to ns */
318static u32 calc_l1_acceptable(u32 encoding)
319{
320 if (encoding == 0x7)
321 return -1U;
322 return (1000 << encoding);
323}
324
325/* Convert L1SS T_pwr encoding to usec */
326static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
327{
328 switch (scale) {
329 case 0:
330 return val * 2;
331 case 1:
332 return val * 10;
333 case 2:
334 return val * 100;
335 }
336 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
337 return 0;
338}
339
340static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
341{
342 u32 threshold_ns = threshold_us * 1000;
343
344 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
345 if (threshold_ns < 32) {
346 *scale = 0;
347 *value = threshold_ns;
348 } else if (threshold_ns < 1024) {
349 *scale = 1;
350 *value = threshold_ns >> 5;
351 } else if (threshold_ns < 32768) {
352 *scale = 2;
353 *value = threshold_ns >> 10;
354 } else if (threshold_ns < 1048576) {
355 *scale = 3;
356 *value = threshold_ns >> 15;
357 } else if (threshold_ns < 33554432) {
358 *scale = 4;
359 *value = threshold_ns >> 20;
360 } else {
361 *scale = 5;
362 *value = threshold_ns >> 25;
363 }
364}
365
366struct aspm_register_info {
367 u32 support:2;
368 u32 enabled:2;
369 u32 latency_encoding_l0s;
370 u32 latency_encoding_l1;
371
372 /* L1 substates */
373 u32 l1ss_cap_ptr;
374 u32 l1ss_cap;
375 u32 l1ss_ctl1;
376 u32 l1ss_ctl2;
377};
378
379static void pcie_get_aspm_reg(struct pci_dev *pdev,
380 struct aspm_register_info *info)
381{
382 u16 reg16;
383 u32 reg32;
384
385 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
386 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
387 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
388 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
389 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, ®16);
390 info->enabled = reg16 & PCI_EXP_LNKCTL_ASPMC;
391
392 /* Read L1 PM substate capabilities */
393 info->l1ss_cap = info->l1ss_ctl1 = info->l1ss_ctl2 = 0;
394 info->l1ss_cap_ptr = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
395 if (!info->l1ss_cap_ptr)
396 return;
397 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CAP,
398 &info->l1ss_cap);
399 if (!(info->l1ss_cap & PCI_L1SS_CAP_L1_PM_SS)) {
400 info->l1ss_cap = 0;
401 return;
402 }
403 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL1,
404 &info->l1ss_ctl1);
405 pci_read_config_dword(pdev, info->l1ss_cap_ptr + PCI_L1SS_CTL2,
406 &info->l1ss_ctl2);
407}
408
409static void pcie_aspm_check_latency(struct pci_dev *endpoint)
410{
411 u32 latency, l1_switch_latency = 0;
412 struct aspm_latency *acceptable;
413 struct pcie_link_state *link;
414
415 /* Device not in D0 doesn't need latency check */
416 if ((endpoint->current_state != PCI_D0) &&
417 (endpoint->current_state != PCI_UNKNOWN))
418 return;
419
420 link = endpoint->bus->self->link_state;
421 acceptable = &link->acceptable[PCI_FUNC(endpoint->devfn)];
422
423 while (link) {
424 /* Check upstream direction L0s latency */
425 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
426 (link->latency_up.l0s > acceptable->l0s))
427 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
428
429 /* Check downstream direction L0s latency */
430 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
431 (link->latency_dw.l0s > acceptable->l0s))
432 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
433 /*
434 * Check L1 latency.
435 * Every switch on the path to root complex need 1
436 * more microsecond for L1. Spec doesn't mention L0s.
437 *
438 * The exit latencies for L1 substates are not advertised
439 * by a device. Since the spec also doesn't mention a way
440 * to determine max latencies introduced by enabling L1
441 * substates on the components, it is not clear how to do
442 * a L1 substate exit latency check. We assume that the
443 * L1 exit latencies advertised by a device include L1
444 * substate latencies (and hence do not do any check).
445 */
446 latency = max_t(u32, link->latency_up.l1, link->latency_dw.l1);
447 if ((link->aspm_capable & ASPM_STATE_L1) &&
448 (latency + l1_switch_latency > acceptable->l1))
449 link->aspm_capable &= ~ASPM_STATE_L1;
450 l1_switch_latency += 1000;
451
452 link = link->parent;
453 }
454}
455
456/*
457 * The L1 PM substate capability is only implemented in function 0 in a
458 * multi function device.
459 */
460static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
461{
462 struct pci_dev *child;
463
464 list_for_each_entry(child, &linkbus->devices, bus_list)
465 if (PCI_FUNC(child->devfn) == 0)
466 return child;
467 return NULL;
468}
469
470/* Calculate L1.2 PM substate timing parameters */
471static void aspm_calc_l1ss_info(struct pcie_link_state *link,
472 struct aspm_register_info *upreg,
473 struct aspm_register_info *dwreg)
474{
475 u32 val1, val2, scale1, scale2;
476 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
477
478 link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
479 link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
480 link->l1ss.ctl1 = link->l1ss.ctl2 = 0;
481
482 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
483 return;
484
485 /* Choose the greater of the two Port Common_Mode_Restore_Times */
486 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
487 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
488 t_common_mode = max(val1, val2);
489
490 /* Choose the greater of the two Port T_POWER_ON times */
491 val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
492 scale1 = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
493 val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
494 scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
495
496 if (calc_l1ss_pwron(link->pdev, scale1, val1) >
497 calc_l1ss_pwron(link->downstream, scale2, val2)) {
498 link->l1ss.ctl2 |= scale1 | (val1 << 3);
499 t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
500 } else {
501 link->l1ss.ctl2 |= scale2 | (val2 << 3);
502 t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
503 }
504
505 /*
506 * Set LTR_L1.2_THRESHOLD to the time required to transition the
507 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
508 * downstream devices report (via LTR) that they can tolerate at
509 * least that much latency.
510 *
511 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
512 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
513 * least 4us.
514 */
515 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
516 encode_l12_threshold(l1_2_threshold, &scale, &value);
517 link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
518}
519
520static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
521{
522 struct pci_dev *child = link->downstream, *parent = link->pdev;
523 struct pci_bus *linkbus = parent->subordinate;
524 struct aspm_register_info upreg, dwreg;
525
526 if (blacklist) {
527 /* Set enabled/disable so that we will disable ASPM later */
528 link->aspm_enabled = ASPM_STATE_ALL;
529 link->aspm_disable = ASPM_STATE_ALL;
530 return;
531 }
532
533 /* Get upstream/downstream components' register state */
534 pcie_get_aspm_reg(parent, &upreg);
535 pcie_get_aspm_reg(child, &dwreg);
536
537 /*
538 * If ASPM not supported, don't mess with the clocks and link,
539 * bail out now.
540 */
541 if (!(upreg.support & dwreg.support))
542 return;
543
544 /* Configure common clock before checking latencies */
545 pcie_aspm_configure_common_clock(link);
546
547 /*
548 * Re-read upstream/downstream components' register state
549 * after clock configuration
550 */
551 pcie_get_aspm_reg(parent, &upreg);
552 pcie_get_aspm_reg(child, &dwreg);
553
554 /*
555 * Setup L0s state
556 *
557 * Note that we must not enable L0s in either direction on a
558 * given link unless components on both sides of the link each
559 * support L0s.
560 */
561 if (dwreg.support & upreg.support & PCIE_LINK_STATE_L0S)
562 link->aspm_support |= ASPM_STATE_L0S;
563 if (dwreg.enabled & PCIE_LINK_STATE_L0S)
564 link->aspm_enabled |= ASPM_STATE_L0S_UP;
565 if (upreg.enabled & PCIE_LINK_STATE_L0S)
566 link->aspm_enabled |= ASPM_STATE_L0S_DW;
567 link->latency_up.l0s = calc_l0s_latency(upreg.latency_encoding_l0s);
568 link->latency_dw.l0s = calc_l0s_latency(dwreg.latency_encoding_l0s);
569
570 /* Setup L1 state */
571 if (upreg.support & dwreg.support & PCIE_LINK_STATE_L1)
572 link->aspm_support |= ASPM_STATE_L1;
573 if (upreg.enabled & dwreg.enabled & PCIE_LINK_STATE_L1)
574 link->aspm_enabled |= ASPM_STATE_L1;
575 link->latency_up.l1 = calc_l1_latency(upreg.latency_encoding_l1);
576 link->latency_dw.l1 = calc_l1_latency(dwreg.latency_encoding_l1);
577
578 /* Setup L1 substate */
579 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
580 link->aspm_support |= ASPM_STATE_L1_1;
581 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
582 link->aspm_support |= ASPM_STATE_L1_2;
583 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
584 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
585 if (upreg.l1ss_cap & dwreg.l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
586 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
587
588 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
589 link->aspm_enabled |= ASPM_STATE_L1_1;
590 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
591 link->aspm_enabled |= ASPM_STATE_L1_2;
592 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
593 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
594 if (upreg.l1ss_ctl1 & dwreg.l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
595 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
596
597 if (link->aspm_support & ASPM_STATE_L1SS)
598 aspm_calc_l1ss_info(link, &upreg, &dwreg);
599
600 /* Save default state */
601 link->aspm_default = link->aspm_enabled;
602
603 /* Setup initial capable state. Will be updated later */
604 link->aspm_capable = link->aspm_support;
605 /*
606 * If the downstream component has pci bridge function, don't
607 * do ASPM for now.
608 */
609 list_for_each_entry(child, &linkbus->devices, bus_list) {
610 if (pci_pcie_type(child) == PCI_EXP_TYPE_PCI_BRIDGE) {
611 link->aspm_disable = ASPM_STATE_ALL;
612 break;
613 }
614 }
615
616 /* Get and check endpoint acceptable latencies */
617 list_for_each_entry(child, &linkbus->devices, bus_list) {
618 u32 reg32, encoding;
619 struct aspm_latency *acceptable =
620 &link->acceptable[PCI_FUNC(child->devfn)];
621
622 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
623 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
624 continue;
625
626 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
627 /* Calculate endpoint L0s acceptable latency */
628 encoding = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
629 acceptable->l0s = calc_l0s_acceptable(encoding);
630 /* Calculate endpoint L1 acceptable latency */
631 encoding = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
632 acceptable->l1 = calc_l1_acceptable(encoding);
633
634 pcie_aspm_check_latency(child);
635 }
636}
637
638static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
639 u32 clear, u32 set)
640{
641 u32 val;
642
643 pci_read_config_dword(pdev, pos, &val);
644 val &= ~clear;
645 val |= set;
646 pci_write_config_dword(pdev, pos, val);
647}
648
649/* Configure the ASPM L1 substates */
650static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
651{
652 u32 val, enable_req;
653 struct pci_dev *child = link->downstream, *parent = link->pdev;
654 u32 up_cap_ptr = link->l1ss.up_cap_ptr;
655 u32 dw_cap_ptr = link->l1ss.dw_cap_ptr;
656
657 enable_req = (link->aspm_enabled ^ state) & state;
658
659 /*
660 * Here are the rules specified in the PCIe spec for enabling L1SS:
661 * - When enabling L1.x, enable bit at parent first, then at child
662 * - When disabling L1.x, disable bit at child first, then at parent
663 * - When enabling ASPM L1.x, need to disable L1
664 * (at child followed by parent).
665 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
666 * parameters
667 *
668 * To keep it simple, disable all L1SS bits first, and later enable
669 * what is needed.
670 */
671
672 /* Disable all L1 substates */
673 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
674 PCI_L1SS_CTL1_L1SS_MASK, 0);
675 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
676 PCI_L1SS_CTL1_L1SS_MASK, 0);
677 /*
678 * If needed, disable L1, and it gets enabled later
679 * in pcie_config_aspm_link().
680 */
681 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
682 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
683 PCI_EXP_LNKCTL_ASPM_L1, 0);
684 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
685 PCI_EXP_LNKCTL_ASPM_L1, 0);
686 }
687
688 if (enable_req & ASPM_STATE_L1_2_MASK) {
689
690 /* Program T_POWER_ON times in both ports */
691 pci_write_config_dword(parent, up_cap_ptr + PCI_L1SS_CTL2,
692 link->l1ss.ctl2);
693 pci_write_config_dword(child, dw_cap_ptr + PCI_L1SS_CTL2,
694 link->l1ss.ctl2);
695
696 /* Program Common_Mode_Restore_Time in upstream device */
697 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
698 PCI_L1SS_CTL1_CM_RESTORE_TIME,
699 link->l1ss.ctl1);
700
701 /* Program LTR_L1.2_THRESHOLD time in both ports */
702 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
703 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
704 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
705 link->l1ss.ctl1);
706 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
707 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
708 PCI_L1SS_CTL1_LTR_L12_TH_SCALE,
709 link->l1ss.ctl1);
710 }
711
712 val = 0;
713 if (state & ASPM_STATE_L1_1)
714 val |= PCI_L1SS_CTL1_ASPM_L1_1;
715 if (state & ASPM_STATE_L1_2)
716 val |= PCI_L1SS_CTL1_ASPM_L1_2;
717 if (state & ASPM_STATE_L1_1_PCIPM)
718 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
719 if (state & ASPM_STATE_L1_2_PCIPM)
720 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
721
722 /* Enable what we need to enable */
723 pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
724 PCI_L1SS_CAP_L1_PM_SS, val);
725 pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
726 PCI_L1SS_CAP_L1_PM_SS, val);
727}
728
729static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
730{
731 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
732 PCI_EXP_LNKCTL_ASPMC, val);
733}
734
735static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
736{
737 u32 upstream = 0, dwstream = 0;
738 struct pci_dev *child = link->downstream, *parent = link->pdev;
739 struct pci_bus *linkbus = parent->subordinate;
740
741 /* Enable only the states that were not explicitly disabled */
742 state &= (link->aspm_capable & ~link->aspm_disable);
743
744 /* Can't enable any substates if L1 is not enabled */
745 if (!(state & ASPM_STATE_L1))
746 state &= ~ASPM_STATE_L1SS;
747
748 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
749 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
750 state &= ~ASPM_STATE_L1_SS_PCIPM;
751 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
752 }
753
754 /* Nothing to do if the link is already in the requested state */
755 if (link->aspm_enabled == state)
756 return;
757 /* Convert ASPM state to upstream/downstream ASPM register state */
758 if (state & ASPM_STATE_L0S_UP)
759 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
760 if (state & ASPM_STATE_L0S_DW)
761 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
762 if (state & ASPM_STATE_L1) {
763 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
764 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
765 }
766
767 if (link->aspm_capable & ASPM_STATE_L1SS)
768 pcie_config_aspm_l1ss(link, state);
769
770 /*
771 * Spec 2.0 suggests all functions should be configured the
772 * same setting for ASPM. Enabling ASPM L1 should be done in
773 * upstream component first and then downstream, and vice
774 * versa for disabling ASPM L1. Spec doesn't mention L0S.
775 */
776 if (state & ASPM_STATE_L1)
777 pcie_config_aspm_dev(parent, upstream);
778 list_for_each_entry(child, &linkbus->devices, bus_list)
779 pcie_config_aspm_dev(child, dwstream);
780 if (!(state & ASPM_STATE_L1))
781 pcie_config_aspm_dev(parent, upstream);
782
783 link->aspm_enabled = state;
784}
785
786static void pcie_config_aspm_path(struct pcie_link_state *link)
787{
788 while (link) {
789 pcie_config_aspm_link(link, policy_to_aspm_state(link));
790 link = link->parent;
791 }
792}
793
794static void free_link_state(struct pcie_link_state *link)
795{
796 link->pdev->link_state = NULL;
797 kfree(link);
798}
799
800static int pcie_aspm_sanity_check(struct pci_dev *pdev)
801{
802 struct pci_dev *child;
803 u32 reg32;
804
805 /*
806 * Some functions in a slot might not all be PCIe functions,
807 * very strange. Disable ASPM for the whole slot
808 */
809 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
810 if (!pci_is_pcie(child))
811 return -EINVAL;
812
813 /*
814 * If ASPM is disabled then we're not going to change
815 * the BIOS state. It's safe to continue even if it's a
816 * pre-1.1 device
817 */
818
819 if (aspm_disabled)
820 continue;
821
822 /*
823 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
824 * RBER bit to determine if a function is 1.1 version device
825 */
826 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
827 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
828 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
829 return -EINVAL;
830 }
831 }
832 return 0;
833}
834
835static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
836{
837 struct pcie_link_state *link;
838
839 link = kzalloc(sizeof(*link), GFP_KERNEL);
840 if (!link)
841 return NULL;
842
843 INIT_LIST_HEAD(&link->sibling);
844 INIT_LIST_HEAD(&link->children);
845 INIT_LIST_HEAD(&link->link);
846 link->pdev = pdev;
847 link->downstream = pci_function_0(pdev->subordinate);
848
849 /*
850 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
851 * hierarchies. Note that some PCIe host implementations omit
852 * the root ports entirely, in which case a downstream port on
853 * a switch may become the root of the link state chain for all
854 * its subordinate endpoints.
855 */
856 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
857 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
858 !pdev->bus->parent->self) {
859 link->root = link;
860 } else {
861 struct pcie_link_state *parent;
862
863 parent = pdev->bus->parent->self->link_state;
864 if (!parent) {
865 kfree(link);
866 return NULL;
867 }
868
869 link->parent = parent;
870 link->root = link->parent->root;
871 list_add(&link->link, &parent->children);
872 }
873
874 list_add(&link->sibling, &link_list);
875 pdev->link_state = link;
876 return link;
877}
878
879/*
880 * pcie_aspm_init_link_state: Initiate PCI express link state.
881 * It is called after the pcie and its children devices are scanned.
882 * @pdev: the root port or switch downstream port
883 */
884void pcie_aspm_init_link_state(struct pci_dev *pdev)
885{
886 struct pcie_link_state *link;
887 int blacklist = !!pcie_aspm_sanity_check(pdev);
888
889 if (!aspm_support_enabled)
890 return;
891
892 if (pdev->link_state)
893 return;
894
895 /*
896 * We allocate pcie_link_state for the component on the upstream
897 * end of a Link, so there's nothing to do unless this device has a
898 * Link on its secondary side.
899 */
900 if (!pdev->has_secondary_link)
901 return;
902
903 /* VIA has a strange chipset, root port is under a bridge */
904 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
905 pdev->bus->self)
906 return;
907
908 down_read(&pci_bus_sem);
909 if (list_empty(&pdev->subordinate->devices))
910 goto out;
911
912 mutex_lock(&aspm_lock);
913 link = alloc_pcie_link_state(pdev);
914 if (!link)
915 goto unlock;
916 /*
917 * Setup initial ASPM state. Note that we need to configure
918 * upstream links also because capable state of them can be
919 * update through pcie_aspm_cap_init().
920 */
921 pcie_aspm_cap_init(link, blacklist);
922
923 /* Setup initial Clock PM state */
924 pcie_clkpm_cap_init(link, blacklist);
925
926 /*
927 * At this stage drivers haven't had an opportunity to change the
928 * link policy setting. Enabling ASPM on broken hardware can cripple
929 * it even before the driver has had a chance to disable ASPM, so
930 * default to a safe level right now. If we're enabling ASPM beyond
931 * the BIOS's expectation, we'll do so once pci_enable_device() is
932 * called.
933 */
934 if (aspm_policy != POLICY_POWERSAVE &&
935 aspm_policy != POLICY_POWER_SUPERSAVE) {
936 pcie_config_aspm_path(link);
937 pcie_set_clkpm(link, policy_to_clkpm_state(link));
938 }
939
940unlock:
941 mutex_unlock(&aspm_lock);
942out:
943 up_read(&pci_bus_sem);
944}
945
946/* Recheck latencies and update aspm_capable for links under the root */
947static void pcie_update_aspm_capable(struct pcie_link_state *root)
948{
949 struct pcie_link_state *link;
950 BUG_ON(root->parent);
951 list_for_each_entry(link, &link_list, sibling) {
952 if (link->root != root)
953 continue;
954 link->aspm_capable = link->aspm_support;
955 }
956 list_for_each_entry(link, &link_list, sibling) {
957 struct pci_dev *child;
958 struct pci_bus *linkbus = link->pdev->subordinate;
959 if (link->root != root)
960 continue;
961 list_for_each_entry(child, &linkbus->devices, bus_list) {
962 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
963 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
964 continue;
965 pcie_aspm_check_latency(child);
966 }
967 }
968}
969
970/* @pdev: the endpoint device */
971void pcie_aspm_exit_link_state(struct pci_dev *pdev)
972{
973 struct pci_dev *parent = pdev->bus->self;
974 struct pcie_link_state *link, *root, *parent_link;
975
976 if (!parent || !parent->link_state)
977 return;
978
979 down_read(&pci_bus_sem);
980 mutex_lock(&aspm_lock);
981 /*
982 * All PCIe functions are in one slot, remove one function will remove
983 * the whole slot, so just wait until we are the last function left.
984 */
985 if (!list_is_last(&pdev->bus_list, &parent->subordinate->devices))
986 goto out;
987
988 link = parent->link_state;
989 root = link->root;
990 parent_link = link->parent;
991
992 /* All functions are removed, so just disable ASPM for the link */
993 pcie_config_aspm_link(link, 0);
994 list_del(&link->sibling);
995 list_del(&link->link);
996 /* Clock PM is for endpoint device */
997 free_link_state(link);
998
999 /* Recheck latencies and configure upstream links */
1000 if (parent_link) {
1001 pcie_update_aspm_capable(root);
1002 pcie_config_aspm_path(parent_link);
1003 }
1004out:
1005 mutex_unlock(&aspm_lock);
1006 up_read(&pci_bus_sem);
1007}
1008
1009/* @pdev: the root port or switch downstream port */
1010void pcie_aspm_pm_state_change(struct pci_dev *pdev)
1011{
1012 struct pcie_link_state *link = pdev->link_state;
1013
1014 if (aspm_disabled || !link)
1015 return;
1016 /*
1017 * Devices changed PM state, we should recheck if latency
1018 * meets all functions' requirement
1019 */
1020 down_read(&pci_bus_sem);
1021 mutex_lock(&aspm_lock);
1022 pcie_update_aspm_capable(link->root);
1023 pcie_config_aspm_path(link);
1024 mutex_unlock(&aspm_lock);
1025 up_read(&pci_bus_sem);
1026}
1027
1028void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1029{
1030 struct pcie_link_state *link = pdev->link_state;
1031
1032 if (aspm_disabled || !link)
1033 return;
1034
1035 if (aspm_policy != POLICY_POWERSAVE &&
1036 aspm_policy != POLICY_POWER_SUPERSAVE)
1037 return;
1038
1039 down_read(&pci_bus_sem);
1040 mutex_lock(&aspm_lock);
1041 pcie_config_aspm_path(link);
1042 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1043 mutex_unlock(&aspm_lock);
1044 up_read(&pci_bus_sem);
1045}
1046
1047static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1048{
1049 struct pci_dev *parent = pdev->bus->self;
1050 struct pcie_link_state *link;
1051
1052 if (!pci_is_pcie(pdev))
1053 return;
1054
1055 if (pdev->has_secondary_link)
1056 parent = pdev;
1057 if (!parent || !parent->link_state)
1058 return;
1059
1060 /*
1061 * A driver requested that ASPM be disabled on this device, but
1062 * if we don't have permission to manage ASPM (e.g., on ACPI
1063 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1064 * the _OSC method), we can't honor that request. Windows has
1065 * a similar mechanism using "PciASPMOptOut", which is also
1066 * ignored in this situation.
1067 */
1068 if (aspm_disabled) {
1069 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1070 return;
1071 }
1072
1073 if (sem)
1074 down_read(&pci_bus_sem);
1075 mutex_lock(&aspm_lock);
1076 link = parent->link_state;
1077 if (state & PCIE_LINK_STATE_L0S)
1078 link->aspm_disable |= ASPM_STATE_L0S;
1079 if (state & PCIE_LINK_STATE_L1)
1080 link->aspm_disable |= ASPM_STATE_L1;
1081 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1082
1083 if (state & PCIE_LINK_STATE_CLKPM) {
1084 link->clkpm_capable = 0;
1085 pcie_set_clkpm(link, 0);
1086 }
1087 mutex_unlock(&aspm_lock);
1088 if (sem)
1089 up_read(&pci_bus_sem);
1090}
1091
1092void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1093{
1094 __pci_disable_link_state(pdev, state, false);
1095}
1096EXPORT_SYMBOL(pci_disable_link_state_locked);
1097
1098/**
1099 * pci_disable_link_state - Disable device's link state, so the link will
1100 * never enter specific states. Note that if the BIOS didn't grant ASPM
1101 * control to the OS, this does nothing because we can't touch the LNKCTL
1102 * register.
1103 *
1104 * @pdev: PCI device
1105 * @state: ASPM link state to disable
1106 */
1107void pci_disable_link_state(struct pci_dev *pdev, int state)
1108{
1109 __pci_disable_link_state(pdev, state, true);
1110}
1111EXPORT_SYMBOL(pci_disable_link_state);
1112
1113static int pcie_aspm_set_policy(const char *val,
1114 const struct kernel_param *kp)
1115{
1116 int i;
1117 struct pcie_link_state *link;
1118
1119 if (aspm_disabled)
1120 return -EPERM;
1121 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1122 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
1123 break;
1124 if (i >= ARRAY_SIZE(policy_str))
1125 return -EINVAL;
1126 if (i == aspm_policy)
1127 return 0;
1128
1129 down_read(&pci_bus_sem);
1130 mutex_lock(&aspm_lock);
1131 aspm_policy = i;
1132 list_for_each_entry(link, &link_list, sibling) {
1133 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1134 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1135 }
1136 mutex_unlock(&aspm_lock);
1137 up_read(&pci_bus_sem);
1138 return 0;
1139}
1140
1141static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1142{
1143 int i, cnt = 0;
1144 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1145 if (i == aspm_policy)
1146 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1147 else
1148 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1149 return cnt;
1150}
1151
1152module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1153 NULL, 0644);
1154
1155#ifdef CONFIG_PCIEASPM_DEBUG
1156static ssize_t link_state_show(struct device *dev,
1157 struct device_attribute *attr,
1158 char *buf)
1159{
1160 struct pci_dev *pci_device = to_pci_dev(dev);
1161 struct pcie_link_state *link_state = pci_device->link_state;
1162
1163 return sprintf(buf, "%d\n", link_state->aspm_enabled);
1164}
1165
1166static ssize_t link_state_store(struct device *dev,
1167 struct device_attribute *attr,
1168 const char *buf,
1169 size_t n)
1170{
1171 struct pci_dev *pdev = to_pci_dev(dev);
1172 struct pcie_link_state *link, *root = pdev->link_state->root;
1173 u32 state;
1174
1175 if (aspm_disabled)
1176 return -EPERM;
1177
1178 if (kstrtouint(buf, 10, &state))
1179 return -EINVAL;
1180 if ((state & ~ASPM_STATE_ALL) != 0)
1181 return -EINVAL;
1182
1183 down_read(&pci_bus_sem);
1184 mutex_lock(&aspm_lock);
1185 list_for_each_entry(link, &link_list, sibling) {
1186 if (link->root != root)
1187 continue;
1188 pcie_config_aspm_link(link, state);
1189 }
1190 mutex_unlock(&aspm_lock);
1191 up_read(&pci_bus_sem);
1192 return n;
1193}
1194
1195static ssize_t clk_ctl_show(struct device *dev,
1196 struct device_attribute *attr,
1197 char *buf)
1198{
1199 struct pci_dev *pci_device = to_pci_dev(dev);
1200 struct pcie_link_state *link_state = pci_device->link_state;
1201
1202 return sprintf(buf, "%d\n", link_state->clkpm_enabled);
1203}
1204
1205static ssize_t clk_ctl_store(struct device *dev,
1206 struct device_attribute *attr,
1207 const char *buf,
1208 size_t n)
1209{
1210 struct pci_dev *pdev = to_pci_dev(dev);
1211 bool state;
1212
1213 if (strtobool(buf, &state))
1214 return -EINVAL;
1215
1216 down_read(&pci_bus_sem);
1217 mutex_lock(&aspm_lock);
1218 pcie_set_clkpm_nocheck(pdev->link_state, state);
1219 mutex_unlock(&aspm_lock);
1220 up_read(&pci_bus_sem);
1221
1222 return n;
1223}
1224
1225static DEVICE_ATTR_RW(link_state);
1226static DEVICE_ATTR_RW(clk_ctl);
1227
1228static char power_group[] = "power";
1229void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
1230{
1231 struct pcie_link_state *link_state = pdev->link_state;
1232
1233 if (!link_state)
1234 return;
1235
1236 if (link_state->aspm_support)
1237 sysfs_add_file_to_group(&pdev->dev.kobj,
1238 &dev_attr_link_state.attr, power_group);
1239 if (link_state->clkpm_capable)
1240 sysfs_add_file_to_group(&pdev->dev.kobj,
1241 &dev_attr_clk_ctl.attr, power_group);
1242}
1243
1244void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
1245{
1246 struct pcie_link_state *link_state = pdev->link_state;
1247
1248 if (!link_state)
1249 return;
1250
1251 if (link_state->aspm_support)
1252 sysfs_remove_file_from_group(&pdev->dev.kobj,
1253 &dev_attr_link_state.attr, power_group);
1254 if (link_state->clkpm_capable)
1255 sysfs_remove_file_from_group(&pdev->dev.kobj,
1256 &dev_attr_clk_ctl.attr, power_group);
1257}
1258#endif
1259
1260static int __init pcie_aspm_disable(char *str)
1261{
1262 if (!strcmp(str, "off")) {
1263 aspm_policy = POLICY_DEFAULT;
1264 aspm_disabled = 1;
1265 aspm_support_enabled = false;
1266 printk(KERN_INFO "PCIe ASPM is disabled\n");
1267 } else if (!strcmp(str, "force")) {
1268 aspm_force = 1;
1269 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1270 }
1271 return 1;
1272}
1273
1274__setup("pcie_aspm=", pcie_aspm_disable);
1275
1276void pcie_no_aspm(void)
1277{
1278 /*
1279 * Disabling ASPM is intended to prevent the kernel from modifying
1280 * existing hardware state, not to clear existing state. To that end:
1281 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1282 * (b) prevent userspace from changing policy
1283 */
1284 if (!aspm_force) {
1285 aspm_policy = POLICY_DEFAULT;
1286 aspm_disabled = 1;
1287 }
1288}
1289
1290bool pcie_aspm_support_enabled(void)
1291{
1292 return aspm_support_enabled;
1293}
1294EXPORT_SYMBOL(pcie_aspm_support_enabled);