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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ARC PGU DRM driver.
4 *
5 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
6 */
7
8#include <drm/drm_atomic_helper.h>
9#include <drm/drm_device.h>
10#include <drm/drm_fb_cma_helper.h>
11#include <drm/drm_gem_cma_helper.h>
12#include <drm/drm_vblank.h>
13#include <drm/drm_plane_helper.h>
14#include <drm/drm_probe_helper.h>
15#include <linux/clk.h>
16#include <linux/platform_data/simplefb.h>
17
18#include "arcpgu.h"
19#include "arcpgu_regs.h"
20
21#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
22
23static struct simplefb_format supported_formats[] = {
24 { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
25 { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
26};
27
28static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
29{
30 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
31 const struct drm_framebuffer *fb = crtc->primary->state->fb;
32 uint32_t pixel_format = fb->format->format;
33 struct simplefb_format *format = NULL;
34 int i;
35
36 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
37 if (supported_formats[i].fourcc == pixel_format)
38 format = &supported_formats[i];
39 }
40
41 if (WARN_ON(!format))
42 return;
43
44 if (format->fourcc == DRM_FORMAT_RGB888)
45 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
46 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
47 ARCPGU_MODE_RGB888_MASK);
48
49}
50
51static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
52 .destroy = drm_crtc_cleanup,
53 .set_config = drm_atomic_helper_set_config,
54 .page_flip = drm_atomic_helper_page_flip,
55 .reset = drm_atomic_helper_crtc_reset,
56 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
57 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
58};
59
60static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
61 const struct drm_display_mode *mode)
62{
63 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
64 long rate, clk_rate = mode->clock * 1000;
65 long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
66
67 rate = clk_round_rate(arcpgu->clk, clk_rate);
68 if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
69 return MODE_OK;
70
71 return MODE_NOCLOCK;
72}
73
74static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
75{
76 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
77 struct drm_display_mode *m = &crtc->state->adjusted_mode;
78 u32 val;
79
80 arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
81 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
82
83 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
84 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
85 m->crtc_hsync_end - m->crtc_hdisplay));
86
87 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
88 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
89 m->crtc_vsync_end - m->crtc_vdisplay));
90
91 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
92 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
93 m->crtc_vblank_end - m->crtc_vblank_start));
94
95 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
96
97 if (m->flags & DRM_MODE_FLAG_PVSYNC)
98 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
99 else
100 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
101
102 if (m->flags & DRM_MODE_FLAG_PHSYNC)
103 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
104 else
105 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
106
107 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
108 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
109 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
110
111 arc_pgu_set_pxl_fmt(crtc);
112
113 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
114}
115
116static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
117 struct drm_crtc_state *old_state)
118{
119 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
120
121 clk_prepare_enable(arcpgu->clk);
122 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
123 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
124 ARCPGU_CTRL_ENABLE_MASK);
125}
126
127static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
128 struct drm_crtc_state *old_state)
129{
130 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
131
132 clk_disable_unprepare(arcpgu->clk);
133 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
134 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
135 ~ARCPGU_CTRL_ENABLE_MASK);
136}
137
138static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
139 struct drm_crtc_state *state)
140{
141 struct drm_pending_vblank_event *event = crtc->state->event;
142
143 if (event) {
144 crtc->state->event = NULL;
145
146 spin_lock_irq(&crtc->dev->event_lock);
147 drm_crtc_send_vblank_event(crtc, event);
148 spin_unlock_irq(&crtc->dev->event_lock);
149 }
150}
151
152static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
153 .mode_valid = arc_pgu_crtc_mode_valid,
154 .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
155 .atomic_begin = arc_pgu_crtc_atomic_begin,
156 .atomic_enable = arc_pgu_crtc_atomic_enable,
157 .atomic_disable = arc_pgu_crtc_atomic_disable,
158};
159
160static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
161 struct drm_plane_state *state)
162{
163 struct arcpgu_drm_private *arcpgu;
164 struct drm_gem_cma_object *gem;
165
166 if (!plane->state->crtc || !plane->state->fb)
167 return;
168
169 arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
170 gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
171 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
172}
173
174static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
175 .atomic_update = arc_pgu_plane_atomic_update,
176};
177
178static void arc_pgu_plane_destroy(struct drm_plane *plane)
179{
180 drm_plane_cleanup(plane);
181}
182
183static const struct drm_plane_funcs arc_pgu_plane_funcs = {
184 .update_plane = drm_atomic_helper_update_plane,
185 .disable_plane = drm_atomic_helper_disable_plane,
186 .destroy = arc_pgu_plane_destroy,
187 .reset = drm_atomic_helper_plane_reset,
188 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
189 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
190};
191
192static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
193{
194 struct arcpgu_drm_private *arcpgu = drm->dev_private;
195 struct drm_plane *plane = NULL;
196 u32 formats[ARRAY_SIZE(supported_formats)], i;
197 int ret;
198
199 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
200 if (!plane)
201 return ERR_PTR(-ENOMEM);
202
203 for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
204 formats[i] = supported_formats[i].fourcc;
205
206 ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
207 formats, ARRAY_SIZE(formats),
208 NULL,
209 DRM_PLANE_TYPE_PRIMARY, NULL);
210 if (ret)
211 return ERR_PTR(ret);
212
213 drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
214 arcpgu->plane = plane;
215
216 return plane;
217}
218
219int arc_pgu_setup_crtc(struct drm_device *drm)
220{
221 struct arcpgu_drm_private *arcpgu = drm->dev_private;
222 struct drm_plane *primary;
223 int ret;
224
225 primary = arc_pgu_plane_init(drm);
226 if (IS_ERR(primary))
227 return PTR_ERR(primary);
228
229 ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
230 &arc_pgu_crtc_funcs, NULL);
231 if (ret) {
232 arc_pgu_plane_destroy(primary);
233 return ret;
234 }
235
236 drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
237 return 0;
238}
1/*
2 * ARC PGU DRM driver.
3 *
4 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_fb_cma_helper.h>
20#include <drm/drm_gem_cma_helper.h>
21#include <drm/drm_plane_helper.h>
22#include <linux/clk.h>
23#include <linux/platform_data/simplefb.h>
24
25#include "arcpgu.h"
26#include "arcpgu_regs.h"
27
28#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
29
30static struct simplefb_format supported_formats[] = {
31 { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
32 { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
33};
34
35static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
36{
37 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
38 const struct drm_framebuffer *fb = crtc->primary->state->fb;
39 uint32_t pixel_format = fb->format->format;
40 struct simplefb_format *format = NULL;
41 int i;
42
43 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
44 if (supported_formats[i].fourcc == pixel_format)
45 format = &supported_formats[i];
46 }
47
48 if (WARN_ON(!format))
49 return;
50
51 if (format->fourcc == DRM_FORMAT_RGB888)
52 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
53 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
54 ARCPGU_MODE_RGB888_MASK);
55
56}
57
58static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
59 .destroy = drm_crtc_cleanup,
60 .set_config = drm_atomic_helper_set_config,
61 .page_flip = drm_atomic_helper_page_flip,
62 .reset = drm_atomic_helper_crtc_reset,
63 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
64 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
65};
66
67static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
68 const struct drm_display_mode *mode)
69{
70 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
71 long rate, clk_rate = mode->clock * 1000;
72 long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
73
74 rate = clk_round_rate(arcpgu->clk, clk_rate);
75 if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
76 return MODE_OK;
77
78 return MODE_NOCLOCK;
79}
80
81static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
82{
83 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
84 struct drm_display_mode *m = &crtc->state->adjusted_mode;
85 u32 val;
86
87 arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
88 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
89
90 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
91 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
92 m->crtc_hsync_end - m->crtc_hdisplay));
93
94 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
95 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
96 m->crtc_vsync_end - m->crtc_vdisplay));
97
98 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
99 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
100 m->crtc_vblank_end - m->crtc_vblank_start));
101
102 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
103
104 if (m->flags & DRM_MODE_FLAG_PVSYNC)
105 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
106 else
107 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
108
109 if (m->flags & DRM_MODE_FLAG_PHSYNC)
110 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
111 else
112 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
113
114 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
115 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
116 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
117
118 arc_pgu_set_pxl_fmt(crtc);
119
120 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
121}
122
123static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
124 struct drm_crtc_state *old_state)
125{
126 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
127
128 clk_prepare_enable(arcpgu->clk);
129 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
130 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
131 ARCPGU_CTRL_ENABLE_MASK);
132}
133
134static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
135 struct drm_crtc_state *old_state)
136{
137 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
138
139 if (!crtc->primary->fb)
140 return;
141
142 clk_disable_unprepare(arcpgu->clk);
143 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
144 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
145 ~ARCPGU_CTRL_ENABLE_MASK);
146}
147
148static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
149 struct drm_crtc_state *state)
150{
151 struct drm_pending_vblank_event *event = crtc->state->event;
152
153 if (event) {
154 crtc->state->event = NULL;
155
156 spin_lock_irq(&crtc->dev->event_lock);
157 drm_crtc_send_vblank_event(crtc, event);
158 spin_unlock_irq(&crtc->dev->event_lock);
159 }
160}
161
162static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
163 .mode_valid = arc_pgu_crtc_mode_valid,
164 .mode_set = drm_helper_crtc_mode_set,
165 .mode_set_base = drm_helper_crtc_mode_set_base,
166 .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
167 .atomic_begin = arc_pgu_crtc_atomic_begin,
168 .atomic_enable = arc_pgu_crtc_atomic_enable,
169 .atomic_disable = arc_pgu_crtc_atomic_disable,
170};
171
172static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
173 struct drm_plane_state *state)
174{
175 struct arcpgu_drm_private *arcpgu;
176 struct drm_gem_cma_object *gem;
177
178 if (!plane->state->crtc || !plane->state->fb)
179 return;
180
181 arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
182 gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
183 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
184}
185
186static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
187 .atomic_update = arc_pgu_plane_atomic_update,
188};
189
190static void arc_pgu_plane_destroy(struct drm_plane *plane)
191{
192 drm_plane_helper_disable(plane);
193 drm_plane_cleanup(plane);
194}
195
196static const struct drm_plane_funcs arc_pgu_plane_funcs = {
197 .update_plane = drm_atomic_helper_update_plane,
198 .disable_plane = drm_atomic_helper_disable_plane,
199 .destroy = arc_pgu_plane_destroy,
200 .reset = drm_atomic_helper_plane_reset,
201 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
202 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
203};
204
205static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
206{
207 struct arcpgu_drm_private *arcpgu = drm->dev_private;
208 struct drm_plane *plane = NULL;
209 u32 formats[ARRAY_SIZE(supported_formats)], i;
210 int ret;
211
212 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
213 if (!plane)
214 return ERR_PTR(-ENOMEM);
215
216 for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
217 formats[i] = supported_formats[i].fourcc;
218
219 ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
220 formats, ARRAY_SIZE(formats),
221 NULL,
222 DRM_PLANE_TYPE_PRIMARY, NULL);
223 if (ret)
224 return ERR_PTR(ret);
225
226 drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
227 arcpgu->plane = plane;
228
229 return plane;
230}
231
232int arc_pgu_setup_crtc(struct drm_device *drm)
233{
234 struct arcpgu_drm_private *arcpgu = drm->dev_private;
235 struct drm_plane *primary;
236 int ret;
237
238 primary = arc_pgu_plane_init(drm);
239 if (IS_ERR(primary))
240 return PTR_ERR(primary);
241
242 ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
243 &arc_pgu_crtc_funcs, NULL);
244 if (ret) {
245 arc_pgu_plane_destroy(primary);
246 return ret;
247 }
248
249 drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
250 return 0;
251}