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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ARC PGU DRM driver.
4 *
5 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
6 */
7
8#include <drm/drm_atomic_helper.h>
9#include <drm/drm_device.h>
10#include <drm/drm_fb_cma_helper.h>
11#include <drm/drm_gem_cma_helper.h>
12#include <drm/drm_vblank.h>
13#include <drm/drm_plane_helper.h>
14#include <drm/drm_probe_helper.h>
15#include <linux/clk.h>
16#include <linux/platform_data/simplefb.h>
17
18#include "arcpgu.h"
19#include "arcpgu_regs.h"
20
21#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
22
23static struct simplefb_format supported_formats[] = {
24 { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
25 { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
26};
27
28static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
29{
30 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
31 const struct drm_framebuffer *fb = crtc->primary->state->fb;
32 uint32_t pixel_format = fb->format->format;
33 struct simplefb_format *format = NULL;
34 int i;
35
36 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
37 if (supported_formats[i].fourcc == pixel_format)
38 format = &supported_formats[i];
39 }
40
41 if (WARN_ON(!format))
42 return;
43
44 if (format->fourcc == DRM_FORMAT_RGB888)
45 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
46 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
47 ARCPGU_MODE_RGB888_MASK);
48
49}
50
51static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
52 .destroy = drm_crtc_cleanup,
53 .set_config = drm_atomic_helper_set_config,
54 .page_flip = drm_atomic_helper_page_flip,
55 .reset = drm_atomic_helper_crtc_reset,
56 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
57 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
58};
59
60static enum drm_mode_status arc_pgu_crtc_mode_valid(struct drm_crtc *crtc,
61 const struct drm_display_mode *mode)
62{
63 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
64 long rate, clk_rate = mode->clock * 1000;
65 long diff = clk_rate / 200; /* +-0.5% allowed by HDMI spec */
66
67 rate = clk_round_rate(arcpgu->clk, clk_rate);
68 if ((max(rate, clk_rate) - min(rate, clk_rate) < diff) && (rate > 0))
69 return MODE_OK;
70
71 return MODE_NOCLOCK;
72}
73
74static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
75{
76 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
77 struct drm_display_mode *m = &crtc->state->adjusted_mode;
78 u32 val;
79
80 arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
81 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
82
83 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
84 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
85 m->crtc_hsync_end - m->crtc_hdisplay));
86
87 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
88 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
89 m->crtc_vsync_end - m->crtc_vdisplay));
90
91 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
92 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
93 m->crtc_vblank_end - m->crtc_vblank_start));
94
95 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
96
97 if (m->flags & DRM_MODE_FLAG_PVSYNC)
98 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
99 else
100 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
101
102 if (m->flags & DRM_MODE_FLAG_PHSYNC)
103 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
104 else
105 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
106
107 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
108 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
109 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
110
111 arc_pgu_set_pxl_fmt(crtc);
112
113 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
114}
115
116static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc,
117 struct drm_crtc_state *old_state)
118{
119 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
120
121 clk_prepare_enable(arcpgu->clk);
122 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
123 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
124 ARCPGU_CTRL_ENABLE_MASK);
125}
126
127static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc,
128 struct drm_crtc_state *old_state)
129{
130 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
131
132 clk_disable_unprepare(arcpgu->clk);
133 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
134 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
135 ~ARCPGU_CTRL_ENABLE_MASK);
136}
137
138static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
139 struct drm_crtc_state *state)
140{
141 struct drm_pending_vblank_event *event = crtc->state->event;
142
143 if (event) {
144 crtc->state->event = NULL;
145
146 spin_lock_irq(&crtc->dev->event_lock);
147 drm_crtc_send_vblank_event(crtc, event);
148 spin_unlock_irq(&crtc->dev->event_lock);
149 }
150}
151
152static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
153 .mode_valid = arc_pgu_crtc_mode_valid,
154 .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
155 .atomic_begin = arc_pgu_crtc_atomic_begin,
156 .atomic_enable = arc_pgu_crtc_atomic_enable,
157 .atomic_disable = arc_pgu_crtc_atomic_disable,
158};
159
160static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
161 struct drm_plane_state *state)
162{
163 struct arcpgu_drm_private *arcpgu;
164 struct drm_gem_cma_object *gem;
165
166 if (!plane->state->crtc || !plane->state->fb)
167 return;
168
169 arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
170 gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
171 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
172}
173
174static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
175 .atomic_update = arc_pgu_plane_atomic_update,
176};
177
178static void arc_pgu_plane_destroy(struct drm_plane *plane)
179{
180 drm_plane_cleanup(plane);
181}
182
183static const struct drm_plane_funcs arc_pgu_plane_funcs = {
184 .update_plane = drm_atomic_helper_update_plane,
185 .disable_plane = drm_atomic_helper_disable_plane,
186 .destroy = arc_pgu_plane_destroy,
187 .reset = drm_atomic_helper_plane_reset,
188 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
189 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
190};
191
192static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
193{
194 struct arcpgu_drm_private *arcpgu = drm->dev_private;
195 struct drm_plane *plane = NULL;
196 u32 formats[ARRAY_SIZE(supported_formats)], i;
197 int ret;
198
199 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
200 if (!plane)
201 return ERR_PTR(-ENOMEM);
202
203 for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
204 formats[i] = supported_formats[i].fourcc;
205
206 ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
207 formats, ARRAY_SIZE(formats),
208 NULL,
209 DRM_PLANE_TYPE_PRIMARY, NULL);
210 if (ret)
211 return ERR_PTR(ret);
212
213 drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
214 arcpgu->plane = plane;
215
216 return plane;
217}
218
219int arc_pgu_setup_crtc(struct drm_device *drm)
220{
221 struct arcpgu_drm_private *arcpgu = drm->dev_private;
222 struct drm_plane *primary;
223 int ret;
224
225 primary = arc_pgu_plane_init(drm);
226 if (IS_ERR(primary))
227 return PTR_ERR(primary);
228
229 ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
230 &arc_pgu_crtc_funcs, NULL);
231 if (ret) {
232 arc_pgu_plane_destroy(primary);
233 return ret;
234 }
235
236 drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
237 return 0;
238}
1/*
2 * ARC PGU DRM driver.
3 *
4 * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc_helper.h>
19#include <drm/drm_fb_cma_helper.h>
20#include <drm/drm_gem_cma_helper.h>
21#include <drm/drm_plane_helper.h>
22#include <linux/clk.h>
23#include <linux/platform_data/simplefb.h>
24
25#include "arcpgu.h"
26#include "arcpgu_regs.h"
27
28#define ENCODE_PGU_XY(x, y) ((((x) - 1) << 16) | ((y) - 1))
29
30static struct simplefb_format supported_formats[] = {
31 { "r5g6b5", 16, {11, 5}, {5, 6}, {0, 5}, {0, 0}, DRM_FORMAT_RGB565 },
32 { "r8g8b8", 24, {16, 8}, {8, 8}, {0, 8}, {0, 0}, DRM_FORMAT_RGB888 },
33};
34
35static void arc_pgu_set_pxl_fmt(struct drm_crtc *crtc)
36{
37 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
38 uint32_t pixel_format = crtc->primary->state->fb->pixel_format;
39 struct simplefb_format *format = NULL;
40 int i;
41
42 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) {
43 if (supported_formats[i].fourcc == pixel_format)
44 format = &supported_formats[i];
45 }
46
47 if (WARN_ON(!format))
48 return;
49
50 if (format->fourcc == DRM_FORMAT_RGB888)
51 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
52 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
53 ARCPGU_MODE_RGB888_MASK);
54
55}
56
57static const struct drm_crtc_funcs arc_pgu_crtc_funcs = {
58 .destroy = drm_crtc_cleanup,
59 .set_config = drm_atomic_helper_set_config,
60 .page_flip = drm_atomic_helper_page_flip,
61 .reset = drm_atomic_helper_crtc_reset,
62 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
63 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
64};
65
66static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc)
67{
68 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
69 struct drm_display_mode *m = &crtc->state->adjusted_mode;
70 u32 val;
71
72 arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
73 ENCODE_PGU_XY(m->crtc_htotal, m->crtc_vtotal));
74
75 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
76 ENCODE_PGU_XY(m->crtc_hsync_start - m->crtc_hdisplay,
77 m->crtc_hsync_end - m->crtc_hdisplay));
78
79 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
80 ENCODE_PGU_XY(m->crtc_vsync_start - m->crtc_vdisplay,
81 m->crtc_vsync_end - m->crtc_vdisplay));
82
83 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
84 ENCODE_PGU_XY(m->crtc_hblank_end - m->crtc_hblank_start,
85 m->crtc_vblank_end - m->crtc_vblank_start));
86
87 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
88
89 if (m->flags & DRM_MODE_FLAG_PVSYNC)
90 val |= ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST;
91 else
92 val &= ~(ARCPGU_CTRL_VS_POL_MASK << ARCPGU_CTRL_VS_POL_OFST);
93
94 if (m->flags & DRM_MODE_FLAG_PHSYNC)
95 val |= ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST;
96 else
97 val &= ~(ARCPGU_CTRL_HS_POL_MASK << ARCPGU_CTRL_HS_POL_OFST);
98
99 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
100 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
101 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
102
103 arc_pgu_set_pxl_fmt(crtc);
104
105 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
106}
107
108static void arc_pgu_crtc_enable(struct drm_crtc *crtc)
109{
110 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
111
112 clk_prepare_enable(arcpgu->clk);
113 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
114 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
115 ARCPGU_CTRL_ENABLE_MASK);
116}
117
118static void arc_pgu_crtc_disable(struct drm_crtc *crtc)
119{
120 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
121
122 if (!crtc->primary->fb)
123 return;
124
125 clk_disable_unprepare(arcpgu->clk);
126 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
127 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
128 ~ARCPGU_CTRL_ENABLE_MASK);
129}
130
131static int arc_pgu_crtc_atomic_check(struct drm_crtc *crtc,
132 struct drm_crtc_state *state)
133{
134 struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc);
135 struct drm_display_mode *mode = &state->adjusted_mode;
136 long rate, clk_rate = mode->clock * 1000;
137
138 rate = clk_round_rate(arcpgu->clk, clk_rate);
139 if (rate != clk_rate)
140 return -EINVAL;
141
142 return 0;
143}
144
145static void arc_pgu_crtc_atomic_begin(struct drm_crtc *crtc,
146 struct drm_crtc_state *state)
147{
148 struct drm_pending_vblank_event *event = crtc->state->event;
149
150 if (event) {
151 crtc->state->event = NULL;
152
153 spin_lock_irq(&crtc->dev->event_lock);
154 drm_crtc_send_vblank_event(crtc, event);
155 spin_unlock_irq(&crtc->dev->event_lock);
156 }
157}
158
159static const struct drm_crtc_helper_funcs arc_pgu_crtc_helper_funcs = {
160 .mode_set = drm_helper_crtc_mode_set,
161 .mode_set_base = drm_helper_crtc_mode_set_base,
162 .mode_set_nofb = arc_pgu_crtc_mode_set_nofb,
163 .enable = arc_pgu_crtc_enable,
164 .disable = arc_pgu_crtc_disable,
165 .prepare = arc_pgu_crtc_disable,
166 .commit = arc_pgu_crtc_enable,
167 .atomic_check = arc_pgu_crtc_atomic_check,
168 .atomic_begin = arc_pgu_crtc_atomic_begin,
169};
170
171static void arc_pgu_plane_atomic_update(struct drm_plane *plane,
172 struct drm_plane_state *state)
173{
174 struct arcpgu_drm_private *arcpgu;
175 struct drm_gem_cma_object *gem;
176
177 if (!plane->state->crtc || !plane->state->fb)
178 return;
179
180 arcpgu = crtc_to_arcpgu_priv(plane->state->crtc);
181 gem = drm_fb_cma_get_gem_obj(plane->state->fb, 0);
182 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->paddr);
183}
184
185static const struct drm_plane_helper_funcs arc_pgu_plane_helper_funcs = {
186 .atomic_update = arc_pgu_plane_atomic_update,
187};
188
189static void arc_pgu_plane_destroy(struct drm_plane *plane)
190{
191 drm_plane_helper_disable(plane);
192 drm_plane_cleanup(plane);
193}
194
195static const struct drm_plane_funcs arc_pgu_plane_funcs = {
196 .update_plane = drm_atomic_helper_update_plane,
197 .disable_plane = drm_atomic_helper_disable_plane,
198 .destroy = arc_pgu_plane_destroy,
199 .reset = drm_atomic_helper_plane_reset,
200 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
201 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
202};
203
204static struct drm_plane *arc_pgu_plane_init(struct drm_device *drm)
205{
206 struct arcpgu_drm_private *arcpgu = drm->dev_private;
207 struct drm_plane *plane = NULL;
208 u32 formats[ARRAY_SIZE(supported_formats)], i;
209 int ret;
210
211 plane = devm_kzalloc(drm->dev, sizeof(*plane), GFP_KERNEL);
212 if (!plane)
213 return ERR_PTR(-ENOMEM);
214
215 for (i = 0; i < ARRAY_SIZE(supported_formats); i++)
216 formats[i] = supported_formats[i].fourcc;
217
218 ret = drm_universal_plane_init(drm, plane, 0xff, &arc_pgu_plane_funcs,
219 formats, ARRAY_SIZE(formats),
220 DRM_PLANE_TYPE_PRIMARY, NULL);
221 if (ret)
222 return ERR_PTR(ret);
223
224 drm_plane_helper_add(plane, &arc_pgu_plane_helper_funcs);
225 arcpgu->plane = plane;
226
227 return plane;
228}
229
230int arc_pgu_setup_crtc(struct drm_device *drm)
231{
232 struct arcpgu_drm_private *arcpgu = drm->dev_private;
233 struct drm_plane *primary;
234 int ret;
235
236 primary = arc_pgu_plane_init(drm);
237 if (IS_ERR(primary))
238 return PTR_ERR(primary);
239
240 ret = drm_crtc_init_with_planes(drm, &arcpgu->crtc, primary, NULL,
241 &arc_pgu_crtc_funcs, NULL);
242 if (ret) {
243 arc_pgu_plane_destroy(primary);
244 return ret;
245 }
246
247 drm_crtc_helper_add(&arcpgu->crtc, &arc_pgu_crtc_helper_funcs);
248 return 0;
249}