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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: John Crispin <john@phrozen.org>
5 * Sean Wang <sean.wang@mediatek.com>
6 *
7 */
8
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/clock/mt2701-clk.h>
12#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
13#include <dt-bindings/power/mt2701-power.h>
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16#include <dt-bindings/memory/mt2701-larb-port.h>
17#include <dt-bindings/reset/mt2701-resets.h>
18#include <dt-bindings/thermal/thermal.h>
19
20/ {
21 compatible = "mediatek,mt7623";
22 interrupt-parent = <&sysirq>;
23 #address-cells = <2>;
24 #size-cells = <2>;
25
26 cpu_opp_table: opp-table {
27 compatible = "operating-points-v2";
28 opp-shared;
29
30 opp-98000000 {
31 opp-hz = /bits/ 64 <98000000>;
32 opp-microvolt = <1050000>;
33 };
34
35 opp-198000000 {
36 opp-hz = /bits/ 64 <198000000>;
37 opp-microvolt = <1050000>;
38 };
39
40 opp-398000000 {
41 opp-hz = /bits/ 64 <398000000>;
42 opp-microvolt = <1050000>;
43 };
44
45 opp-598000000 {
46 opp-hz = /bits/ 64 <598000000>;
47 opp-microvolt = <1050000>;
48 };
49
50 opp-747500000 {
51 opp-hz = /bits/ 64 <747500000>;
52 opp-microvolt = <1050000>;
53 };
54
55 opp-1040000000 {
56 opp-hz = /bits/ 64 <1040000000>;
57 opp-microvolt = <1150000>;
58 };
59
60 opp-1196000000 {
61 opp-hz = /bits/ 64 <1196000000>;
62 opp-microvolt = <1200000>;
63 };
64
65 opp-1300000000 {
66 opp-hz = /bits/ 64 <1300000000>;
67 opp-microvolt = <1300000>;
68 };
69 };
70
71 cpus {
72 #address-cells = <1>;
73 #size-cells = <0>;
74 enable-method = "mediatek,mt6589-smp";
75
76 cpu0: cpu@0 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a7";
79 reg = <0x0>;
80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
81 <&apmixedsys CLK_APMIXED_MAINPLL>;
82 clock-names = "cpu", "intermediate";
83 operating-points-v2 = <&cpu_opp_table>;
84 #cooling-cells = <2>;
85 clock-frequency = <1300000000>;
86 };
87
88 cpu1: cpu@1 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a7";
91 reg = <0x1>;
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
93 <&apmixedsys CLK_APMIXED_MAINPLL>;
94 clock-names = "cpu", "intermediate";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>;
97 clock-frequency = <1300000000>;
98 };
99
100 cpu2: cpu@2 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a7";
103 reg = <0x2>;
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
105 <&apmixedsys CLK_APMIXED_MAINPLL>;
106 clock-names = "cpu", "intermediate";
107 operating-points-v2 = <&cpu_opp_table>;
108 #cooling-cells = <2>;
109 clock-frequency = <1300000000>;
110 };
111
112 cpu3: cpu@3 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a7";
115 reg = <0x3>;
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
117 <&apmixedsys CLK_APMIXED_MAINPLL>;
118 clock-names = "cpu", "intermediate";
119 operating-points-v2 = <&cpu_opp_table>;
120 #cooling-cells = <2>;
121 clock-frequency = <1300000000>;
122 };
123 };
124
125 pmu {
126 compatible = "arm,cortex-a7-pmu";
127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
128 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
131 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
132 };
133
134 system_clk: dummy13m {
135 compatible = "fixed-clock";
136 clock-frequency = <13000000>;
137 #clock-cells = <0>;
138 };
139
140 rtc32k: oscillator-1 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <32000>;
144 clock-output-names = "rtc32k";
145 };
146
147 clk26m: oscillator-0 {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <26000000>;
151 clock-output-names = "clk26m";
152 };
153
154 thermal-zones {
155 cpu_thermal: cpu-thermal {
156 polling-delay-passive = <1000>;
157 polling-delay = <1000>;
158
159 thermal-sensors = <&thermal 0>;
160
161 trips {
162 cpu_passive: cpu-passive {
163 temperature = <47000>;
164 hysteresis = <2000>;
165 type = "passive";
166 };
167
168 cpu_active: cpu-active {
169 temperature = <67000>;
170 hysteresis = <2000>;
171 type = "active";
172 };
173
174 cpu_hot: cpu-hot {
175 temperature = <87000>;
176 hysteresis = <2000>;
177 type = "hot";
178 };
179
180 cpu-crit {
181 temperature = <107000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186
187 cooling-maps {
188 map0 {
189 trip = <&cpu_passive>;
190 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
191 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
192 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 };
195
196 map1 {
197 trip = <&cpu_active>;
198 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
199 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202 };
203
204 map2 {
205 trip = <&cpu_hot>;
206 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 };
211 };
212 };
213 };
214
215 timer {
216 compatible = "arm,armv7-timer";
217 interrupt-parent = <&gic>;
218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
222 clock-frequency = <13000000>;
223 arm,cpu-registers-not-fw-configured;
224 };
225
226 topckgen: syscon@10000000 {
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
229 "syscon";
230 reg = <0 0x10000000 0 0x1000>;
231 #clock-cells = <1>;
232 };
233
234 infracfg: syscon@10001000 {
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
237 "syscon";
238 reg = <0 0x10001000 0 0x1000>;
239 #clock-cells = <1>;
240 #reset-cells = <1>;
241 };
242
243 pericfg: syscon@10003000 {
244 compatible = "mediatek,mt7623-pericfg",
245 "mediatek,mt2701-pericfg",
246 "syscon";
247 reg = <0 0x10003000 0 0x1000>;
248 #clock-cells = <1>;
249 #reset-cells = <1>;
250 };
251
252 pio: pinctrl@10005000 {
253 compatible = "mediatek,mt7623-pinctrl";
254 reg = <0 0x1000b000 0 0x1000>;
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
256 pins-are-numbered;
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
260 interrupt-parent = <&gic>;
261 #interrupt-cells = <2>;
262 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
264 };
265
266 syscfg_pctl_a: syscfg@10005000 {
267 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
268 reg = <0 0x10005000 0 0x1000>;
269 };
270
271 scpsys: scpsys@10006000 {
272 compatible = "mediatek,mt7623-scpsys",
273 "mediatek,mt2701-scpsys",
274 "syscon";
275 #power-domain-cells = <1>;
276 reg = <0 0x10006000 0 0x1000>;
277 infracfg = <&infracfg>;
278 clocks = <&topckgen CLK_TOP_MM_SEL>,
279 <&topckgen CLK_TOP_MFG_SEL>,
280 <&topckgen CLK_TOP_ETHIF_SEL>;
281 clock-names = "mm", "mfg", "ethif";
282 };
283
284 watchdog: watchdog@10007000 {
285 compatible = "mediatek,mt7623-wdt",
286 "mediatek,mt6589-wdt";
287 reg = <0 0x10007000 0 0x100>;
288 };
289
290 timer: timer@10008000 {
291 compatible = "mediatek,mt7623-timer",
292 "mediatek,mt6577-timer";
293 reg = <0 0x10008000 0 0x80>;
294 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
295 clocks = <&system_clk>, <&rtc32k>;
296 clock-names = "system-clk", "rtc-clk";
297 };
298
299 smi_common: smi@1000c000 {
300 compatible = "mediatek,mt7623-smi-common",
301 "mediatek,mt2701-smi-common";
302 reg = <0 0x1000c000 0 0x1000>;
303 clocks = <&infracfg CLK_INFRA_SMI>,
304 <&mmsys CLK_MM_SMI_COMMON>,
305 <&infracfg CLK_INFRA_SMI>;
306 clock-names = "apb", "smi", "async";
307 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
308 };
309
310 pwrap: pwrap@1000d000 {
311 compatible = "mediatek,mt7623-pwrap",
312 "mediatek,mt2701-pwrap";
313 reg = <0 0x1000d000 0 0x1000>;
314 reg-names = "pwrap";
315 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
316 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
317 reset-names = "pwrap";
318 clocks = <&infracfg CLK_INFRA_PMICSPI>,
319 <&infracfg CLK_INFRA_PMICWRAP>;
320 clock-names = "spi", "wrap";
321 };
322
323 cir: cir@10013000 {
324 compatible = "mediatek,mt7623-cir";
325 reg = <0 0x10013000 0 0x1000>;
326 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
327 clocks = <&infracfg CLK_INFRA_IRRX>;
328 clock-names = "clk";
329 status = "disabled";
330 };
331
332 sysirq: interrupt-controller@10200100 {
333 compatible = "mediatek,mt7623-sysirq",
334 "mediatek,mt6577-sysirq";
335 interrupt-controller;
336 #interrupt-cells = <3>;
337 interrupt-parent = <&gic>;
338 reg = <0 0x10200100 0 0x1c>;
339 };
340
341 iommu: mmsys_iommu@10205000 {
342 compatible = "mediatek,mt7623-m4u",
343 "mediatek,mt2701-m4u";
344 reg = <0 0x10205000 0 0x1000>;
345 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
346 clocks = <&infracfg CLK_INFRA_M4U>;
347 clock-names = "bclk";
348 mediatek,larbs = <&larb0 &larb1 &larb2>;
349 #iommu-cells = <1>;
350 };
351
352 efuse: efuse@10206000 {
353 compatible = "mediatek,mt7623-efuse",
354 "mediatek,mt8173-efuse";
355 reg = <0 0x10206000 0 0x1000>;
356 #address-cells = <1>;
357 #size-cells = <1>;
358 thermal_calibration_data: calib@424 {
359 reg = <0x424 0xc>;
360 };
361 };
362
363 apmixedsys: syscon@10209000 {
364 compatible = "mediatek,mt7623-apmixedsys",
365 "mediatek,mt2701-apmixedsys",
366 "syscon";
367 reg = <0 0x10209000 0 0x1000>;
368 #clock-cells = <1>;
369 };
370
371 rng: rng@1020f000 {
372 compatible = "mediatek,mt7623-rng";
373 reg = <0 0x1020f000 0 0x1000>;
374 clocks = <&infracfg CLK_INFRA_TRNG>;
375 clock-names = "rng";
376 };
377
378 gic: interrupt-controller@10211000 {
379 compatible = "arm,cortex-a7-gic";
380 interrupt-controller;
381 #interrupt-cells = <3>;
382 interrupt-parent = <&gic>;
383 reg = <0 0x10211000 0 0x1000>,
384 <0 0x10212000 0 0x2000>,
385 <0 0x10214000 0 0x2000>,
386 <0 0x10216000 0 0x2000>;
387 };
388
389 auxadc: adc@11001000 {
390 compatible = "mediatek,mt7623-auxadc",
391 "mediatek,mt2701-auxadc";
392 reg = <0 0x11001000 0 0x1000>;
393 clocks = <&pericfg CLK_PERI_AUXADC>;
394 clock-names = "main";
395 #io-channel-cells = <1>;
396 };
397
398 uart0: serial@11002000 {
399 compatible = "mediatek,mt7623-uart",
400 "mediatek,mt6577-uart";
401 reg = <0 0x11002000 0 0x400>;
402 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
403 clocks = <&pericfg CLK_PERI_UART0_SEL>,
404 <&pericfg CLK_PERI_UART0>;
405 clock-names = "baud", "bus";
406 status = "disabled";
407 };
408
409 uart1: serial@11003000 {
410 compatible = "mediatek,mt7623-uart",
411 "mediatek,mt6577-uart";
412 reg = <0 0x11003000 0 0x400>;
413 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
414 clocks = <&pericfg CLK_PERI_UART1_SEL>,
415 <&pericfg CLK_PERI_UART1>;
416 clock-names = "baud", "bus";
417 status = "disabled";
418 };
419
420 uart2: serial@11004000 {
421 compatible = "mediatek,mt7623-uart",
422 "mediatek,mt6577-uart";
423 reg = <0 0x11004000 0 0x400>;
424 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
425 clocks = <&pericfg CLK_PERI_UART2_SEL>,
426 <&pericfg CLK_PERI_UART2>;
427 clock-names = "baud", "bus";
428 status = "disabled";
429 };
430
431 uart3: serial@11005000 {
432 compatible = "mediatek,mt7623-uart",
433 "mediatek,mt6577-uart";
434 reg = <0 0x11005000 0 0x400>;
435 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
436 clocks = <&pericfg CLK_PERI_UART3_SEL>,
437 <&pericfg CLK_PERI_UART3>;
438 clock-names = "baud", "bus";
439 status = "disabled";
440 };
441
442 pwm: pwm@11006000 {
443 compatible = "mediatek,mt7623-pwm";
444 reg = <0 0x11006000 0 0x1000>;
445 #pwm-cells = <2>;
446 clocks = <&topckgen CLK_TOP_PWM_SEL>,
447 <&pericfg CLK_PERI_PWM>,
448 <&pericfg CLK_PERI_PWM1>,
449 <&pericfg CLK_PERI_PWM2>,
450 <&pericfg CLK_PERI_PWM3>,
451 <&pericfg CLK_PERI_PWM4>,
452 <&pericfg CLK_PERI_PWM5>;
453 clock-names = "top", "main", "pwm1", "pwm2",
454 "pwm3", "pwm4", "pwm5";
455 status = "disabled";
456 };
457
458 i2c0: i2c@11007000 {
459 compatible = "mediatek,mt7623-i2c",
460 "mediatek,mt6577-i2c";
461 reg = <0 0x11007000 0 0x70>,
462 <0 0x11000200 0 0x80>;
463 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
464 clock-div = <16>;
465 clocks = <&pericfg CLK_PERI_I2C0>,
466 <&pericfg CLK_PERI_AP_DMA>;
467 clock-names = "main", "dma";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
472
473 i2c1: i2c@11008000 {
474 compatible = "mediatek,mt7623-i2c",
475 "mediatek,mt6577-i2c";
476 reg = <0 0x11008000 0 0x70>,
477 <0 0x11000280 0 0x80>;
478 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
479 clock-div = <16>;
480 clocks = <&pericfg CLK_PERI_I2C1>,
481 <&pericfg CLK_PERI_AP_DMA>;
482 clock-names = "main", "dma";
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
487
488 i2c2: i2c@11009000 {
489 compatible = "mediatek,mt7623-i2c",
490 "mediatek,mt6577-i2c";
491 reg = <0 0x11009000 0 0x70>,
492 <0 0x11000300 0 0x80>;
493 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
494 clock-div = <16>;
495 clocks = <&pericfg CLK_PERI_I2C2>,
496 <&pericfg CLK_PERI_AP_DMA>;
497 clock-names = "main", "dma";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 status = "disabled";
501 };
502
503 spi0: spi@1100a000 {
504 compatible = "mediatek,mt7623-spi",
505 "mediatek,mt2701-spi";
506 #address-cells = <1>;
507 #size-cells = <0>;
508 reg = <0 0x1100a000 0 0x100>;
509 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
510 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
511 <&topckgen CLK_TOP_SPI0_SEL>,
512 <&pericfg CLK_PERI_SPI0>;
513 clock-names = "parent-clk", "sel-clk", "spi-clk";
514 status = "disabled";
515 };
516
517 thermal: thermal@1100b000 {
518 #thermal-sensor-cells = <1>;
519 compatible = "mediatek,mt7623-thermal",
520 "mediatek,mt2701-thermal";
521 reg = <0 0x1100b000 0 0x1000>;
522 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
523 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
524 clock-names = "therm", "auxadc";
525 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
526 reset-names = "therm";
527 mediatek,auxadc = <&auxadc>;
528 mediatek,apmixedsys = <&apmixedsys>;
529 nvmem-cells = <&thermal_calibration_data>;
530 nvmem-cell-names = "calibration-data";
531 };
532
533 btif: serial@1100c000 {
534 compatible = "mediatek,mt7623-btif",
535 "mediatek,mtk-btif";
536 reg = <0 0x1100c000 0 0x1000>;
537 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
538 clocks = <&pericfg CLK_PERI_BTIF>;
539 clock-names = "main";
540 reg-shift = <2>;
541 reg-io-width = <4>;
542 status = "disabled";
543 };
544
545 nandc: nfi@1100d000 {
546 compatible = "mediatek,mt7623-nfc",
547 "mediatek,mt2701-nfc";
548 reg = <0 0x1100d000 0 0x1000>;
549 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
550 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
551 clocks = <&pericfg CLK_PERI_NFI>,
552 <&pericfg CLK_PERI_NFI_PAD>;
553 clock-names = "nfi_clk", "pad_clk";
554 status = "disabled";
555 ecc-engine = <&bch>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558 };
559
560 bch: ecc@1100e000 {
561 compatible = "mediatek,mt7623-ecc",
562 "mediatek,mt2701-ecc";
563 reg = <0 0x1100e000 0 0x1000>;
564 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
565 clocks = <&pericfg CLK_PERI_NFI_ECC>;
566 clock-names = "nfiecc_clk";
567 status = "disabled";
568 };
569
570 nor_flash: spi@11014000 {
571 compatible = "mediatek,mt7623-nor",
572 "mediatek,mt8173-nor";
573 reg = <0 0x11014000 0 0x1000>;
574 clocks = <&pericfg CLK_PERI_FLASH>,
575 <&topckgen CLK_TOP_FLASH_SEL>;
576 clock-names = "spi", "sf";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 status = "disabled";
580 };
581
582 spi1: spi@11016000 {
583 compatible = "mediatek,mt7623-spi",
584 "mediatek,mt2701-spi";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 reg = <0 0x11016000 0 0x100>;
588 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
589 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
590 <&topckgen CLK_TOP_SPI1_SEL>,
591 <&pericfg CLK_PERI_SPI1>;
592 clock-names = "parent-clk", "sel-clk", "spi-clk";
593 status = "disabled";
594 };
595
596 spi2: spi@11017000 {
597 compatible = "mediatek,mt7623-spi",
598 "mediatek,mt2701-spi";
599 #address-cells = <1>;
600 #size-cells = <0>;
601 reg = <0 0x11017000 0 0x1000>;
602 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
603 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
604 <&topckgen CLK_TOP_SPI2_SEL>,
605 <&pericfg CLK_PERI_SPI2>;
606 clock-names = "parent-clk", "sel-clk", "spi-clk";
607 status = "disabled";
608 };
609
610 audsys: clock-controller@11220000 {
611 compatible = "mediatek,mt7623-audsys",
612 "mediatek,mt2701-audsys",
613 "syscon";
614 reg = <0 0x11220000 0 0x2000>;
615 #clock-cells = <1>;
616
617 afe: audio-controller {
618 compatible = "mediatek,mt7623-audio",
619 "mediatek,mt2701-audio";
620 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
621 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
622 interrupt-names = "afe", "asys";
623 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
624
625 clocks = <&infracfg CLK_INFRA_AUDIO>,
626 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
627 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
628 <&topckgen CLK_TOP_AUD_48K_TIMING>,
629 <&topckgen CLK_TOP_AUD_44K_TIMING>,
630 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
631 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
632 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
633 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
634 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
635 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
636 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
637 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
638 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
639 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
640 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
641 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
642 <&audsys CLK_AUD_I2SO1>,
643 <&audsys CLK_AUD_I2SO2>,
644 <&audsys CLK_AUD_I2SO3>,
645 <&audsys CLK_AUD_I2SO4>,
646 <&audsys CLK_AUD_I2SIN1>,
647 <&audsys CLK_AUD_I2SIN2>,
648 <&audsys CLK_AUD_I2SIN3>,
649 <&audsys CLK_AUD_I2SIN4>,
650 <&audsys CLK_AUD_ASRCO1>,
651 <&audsys CLK_AUD_ASRCO2>,
652 <&audsys CLK_AUD_ASRCO3>,
653 <&audsys CLK_AUD_ASRCO4>,
654 <&audsys CLK_AUD_AFE>,
655 <&audsys CLK_AUD_AFE_CONN>,
656 <&audsys CLK_AUD_A1SYS>,
657 <&audsys CLK_AUD_A2SYS>,
658 <&audsys CLK_AUD_AFE_MRGIF>;
659
660 clock-names = "infra_sys_audio_clk",
661 "top_audio_mux1_sel",
662 "top_audio_mux2_sel",
663 "top_audio_a1sys_hp",
664 "top_audio_a2sys_hp",
665 "i2s0_src_sel",
666 "i2s1_src_sel",
667 "i2s2_src_sel",
668 "i2s3_src_sel",
669 "i2s0_src_div",
670 "i2s1_src_div",
671 "i2s2_src_div",
672 "i2s3_src_div",
673 "i2s0_mclk_en",
674 "i2s1_mclk_en",
675 "i2s2_mclk_en",
676 "i2s3_mclk_en",
677 "i2so0_hop_ck",
678 "i2so1_hop_ck",
679 "i2so2_hop_ck",
680 "i2so3_hop_ck",
681 "i2si0_hop_ck",
682 "i2si1_hop_ck",
683 "i2si2_hop_ck",
684 "i2si3_hop_ck",
685 "asrc0_out_ck",
686 "asrc1_out_ck",
687 "asrc2_out_ck",
688 "asrc3_out_ck",
689 "audio_afe_pd",
690 "audio_afe_conn_pd",
691 "audio_a1sys_pd",
692 "audio_a2sys_pd",
693 "audio_mrgif_pd";
694
695 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
696 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
697 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
698 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
699 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
700 <&topckgen CLK_TOP_AUD2PLL_90M>;
701 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
702 };
703 };
704
705 mmc0: mmc@11230000 {
706 compatible = "mediatek,mt7623-mmc",
707 "mediatek,mt2701-mmc";
708 reg = <0 0x11230000 0 0x1000>;
709 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
710 clocks = <&pericfg CLK_PERI_MSDC30_0>,
711 <&topckgen CLK_TOP_MSDC30_0_SEL>;
712 clock-names = "source", "hclk";
713 status = "disabled";
714 };
715
716 mmc1: mmc@11240000 {
717 compatible = "mediatek,mt7623-mmc",
718 "mediatek,mt2701-mmc";
719 reg = <0 0x11240000 0 0x1000>;
720 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
721 clocks = <&pericfg CLK_PERI_MSDC30_1>,
722 <&topckgen CLK_TOP_MSDC30_1_SEL>;
723 clock-names = "source", "hclk";
724 status = "disabled";
725 };
726
727 g3dsys: syscon@13000000 {
728 compatible = "mediatek,mt7623-g3dsys",
729 "mediatek,mt2701-g3dsys",
730 "syscon";
731 reg = <0 0x13000000 0 0x200>;
732 #clock-cells = <1>;
733 #reset-cells = <1>;
734 };
735
736 mmsys: syscon@14000000 {
737 compatible = "mediatek,mt7623-mmsys",
738 "mediatek,mt2701-mmsys",
739 "syscon";
740 reg = <0 0x14000000 0 0x1000>;
741 #clock-cells = <1>;
742 };
743
744 larb0: larb@14010000 {
745 compatible = "mediatek,mt7623-smi-larb",
746 "mediatek,mt2701-smi-larb";
747 reg = <0 0x14010000 0 0x1000>;
748 mediatek,smi = <&smi_common>;
749 mediatek,larb-id = <0>;
750 clocks = <&mmsys CLK_MM_SMI_LARB0>,
751 <&mmsys CLK_MM_SMI_LARB0>;
752 clock-names = "apb", "smi";
753 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
754 };
755
756 imgsys: syscon@15000000 {
757 compatible = "mediatek,mt7623-imgsys",
758 "mediatek,mt2701-imgsys",
759 "syscon";
760 reg = <0 0x15000000 0 0x1000>;
761 #clock-cells = <1>;
762 };
763
764 larb2: larb@15001000 {
765 compatible = "mediatek,mt7623-smi-larb",
766 "mediatek,mt2701-smi-larb";
767 reg = <0 0x15001000 0 0x1000>;
768 mediatek,smi = <&smi_common>;
769 mediatek,larb-id = <2>;
770 clocks = <&imgsys CLK_IMG_SMI_COMM>,
771 <&imgsys CLK_IMG_SMI_COMM>;
772 clock-names = "apb", "smi";
773 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
774 };
775
776 jpegdec: jpegdec@15004000 {
777 compatible = "mediatek,mt7623-jpgdec",
778 "mediatek,mt2701-jpgdec";
779 reg = <0 0x15004000 0 0x1000>;
780 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
781 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
782 <&imgsys CLK_IMG_JPGDEC>;
783 clock-names = "jpgdec-smi",
784 "jpgdec";
785 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
786 mediatek,larb = <&larb2>;
787 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
788 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
789 };
790
791 vdecsys: syscon@16000000 {
792 compatible = "mediatek,mt7623-vdecsys",
793 "mediatek,mt2701-vdecsys",
794 "syscon";
795 reg = <0 0x16000000 0 0x1000>;
796 #clock-cells = <1>;
797 };
798
799 larb1: larb@16010000 {
800 compatible = "mediatek,mt7623-smi-larb",
801 "mediatek,mt2701-smi-larb";
802 reg = <0 0x16010000 0 0x1000>;
803 mediatek,smi = <&smi_common>;
804 mediatek,larb-id = <1>;
805 clocks = <&vdecsys CLK_VDEC_CKGEN>,
806 <&vdecsys CLK_VDEC_LARB>;
807 clock-names = "apb", "smi";
808 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
809 };
810
811 hifsys: syscon@1a000000 {
812 compatible = "mediatek,mt7623-hifsys",
813 "mediatek,mt2701-hifsys",
814 "syscon";
815 reg = <0 0x1a000000 0 0x1000>;
816 #clock-cells = <1>;
817 #reset-cells = <1>;
818 };
819
820 pcie: pcie@1a140000 {
821 compatible = "mediatek,mt7623-pcie";
822 device_type = "pci";
823 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
824 <0 0x1a142000 0 0x1000>, /* Port0 registers */
825 <0 0x1a143000 0 0x1000>, /* Port1 registers */
826 <0 0x1a144000 0 0x1000>; /* Port2 registers */
827 reg-names = "subsys", "port0", "port1", "port2";
828 #address-cells = <3>;
829 #size-cells = <2>;
830 #interrupt-cells = <1>;
831 interrupt-map-mask = <0xf800 0 0 0>;
832 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
833 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
834 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
835 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
836 <&hifsys CLK_HIFSYS_PCIE0>,
837 <&hifsys CLK_HIFSYS_PCIE1>,
838 <&hifsys CLK_HIFSYS_PCIE2>;
839 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
840 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
841 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
842 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
843 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
844 phys = <&pcie0_port PHY_TYPE_PCIE>,
845 <&pcie1_port PHY_TYPE_PCIE>,
846 <&u3port1 PHY_TYPE_PCIE>;
847 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
848 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
849 bus-range = <0x00 0xff>;
850 status = "disabled";
851 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
852 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
853
854 pcie@0,0 {
855 reg = <0x0000 0 0 0 0>;
856 #address-cells = <3>;
857 #size-cells = <2>;
858 #interrupt-cells = <1>;
859 interrupt-map-mask = <0 0 0 0>;
860 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
861 ranges;
862 status = "disabled";
863 };
864
865 pcie@1,0 {
866 reg = <0x0800 0 0 0 0>;
867 #address-cells = <3>;
868 #size-cells = <2>;
869 #interrupt-cells = <1>;
870 interrupt-map-mask = <0 0 0 0>;
871 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
872 ranges;
873 status = "disabled";
874 };
875
876 pcie@2,0 {
877 reg = <0x1000 0 0 0 0>;
878 #address-cells = <3>;
879 #size-cells = <2>;
880 #interrupt-cells = <1>;
881 interrupt-map-mask = <0 0 0 0>;
882 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
883 ranges;
884 status = "disabled";
885 };
886 };
887
888 pcie0_phy: pcie-phy@1a149000 {
889 compatible = "mediatek,generic-tphy-v1";
890 reg = <0 0x1a149000 0 0x0700>;
891 #address-cells = <2>;
892 #size-cells = <2>;
893 ranges;
894 status = "disabled";
895
896 pcie0_port: pcie-phy@1a149900 {
897 reg = <0 0x1a149900 0 0x0700>;
898 clocks = <&clk26m>;
899 clock-names = "ref";
900 #phy-cells = <1>;
901 status = "okay";
902 };
903 };
904
905 pcie1_phy: pcie-phy@1a14a000 {
906 compatible = "mediatek,generic-tphy-v1";
907 reg = <0 0x1a14a000 0 0x0700>;
908 #address-cells = <2>;
909 #size-cells = <2>;
910 ranges;
911 status = "disabled";
912
913 pcie1_port: pcie-phy@1a14a900 {
914 reg = <0 0x1a14a900 0 0x0700>;
915 clocks = <&clk26m>;
916 clock-names = "ref";
917 #phy-cells = <1>;
918 status = "okay";
919 };
920 };
921
922 usb1: usb@1a1c0000 {
923 compatible = "mediatek,mt7623-xhci",
924 "mediatek,mt8173-xhci";
925 reg = <0 0x1a1c0000 0 0x1000>,
926 <0 0x1a1c4700 0 0x0100>;
927 reg-names = "mac", "ippc";
928 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
929 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
930 <&topckgen CLK_TOP_ETHIF_SEL>;
931 clock-names = "sys_ck", "ref_ck";
932 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
933 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
934 status = "disabled";
935 };
936
937 u3phy1: usb-phy@1a1c4000 {
938 compatible = "mediatek,mt7623-u3phy",
939 "mediatek,mt2701-u3phy";
940 reg = <0 0x1a1c4000 0 0x0700>;
941 #address-cells = <2>;
942 #size-cells = <2>;
943 ranges;
944 status = "disabled";
945
946 u2port0: usb-phy@1a1c4800 {
947 reg = <0 0x1a1c4800 0 0x0100>;
948 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
949 clock-names = "ref";
950 #phy-cells = <1>;
951 status = "okay";
952 };
953
954 u3port0: usb-phy@1a1c4900 {
955 reg = <0 0x1a1c4900 0 0x0700>;
956 clocks = <&clk26m>;
957 clock-names = "ref";
958 #phy-cells = <1>;
959 status = "okay";
960 };
961 };
962
963 usb2: usb@1a240000 {
964 compatible = "mediatek,mt7623-xhci",
965 "mediatek,mt8173-xhci";
966 reg = <0 0x1a240000 0 0x1000>,
967 <0 0x1a244700 0 0x0100>;
968 reg-names = "mac", "ippc";
969 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
970 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
971 <&topckgen CLK_TOP_ETHIF_SEL>;
972 clock-names = "sys_ck", "ref_ck";
973 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
974 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
975 status = "disabled";
976 };
977
978 u3phy2: usb-phy@1a244000 {
979 compatible = "mediatek,mt7623-u3phy",
980 "mediatek,mt2701-u3phy";
981 reg = <0 0x1a244000 0 0x0700>;
982 #address-cells = <2>;
983 #size-cells = <2>;
984 ranges;
985 status = "disabled";
986
987 u2port1: usb-phy@1a244800 {
988 reg = <0 0x1a244800 0 0x0100>;
989 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
990 clock-names = "ref";
991 #phy-cells = <1>;
992 status = "okay";
993 };
994
995 u3port1: usb-phy@1a244900 {
996 reg = <0 0x1a244900 0 0x0700>;
997 clocks = <&clk26m>;
998 clock-names = "ref";
999 #phy-cells = <1>;
1000 status = "okay";
1001 };
1002 };
1003
1004 ethsys: syscon@1b000000 {
1005 compatible = "mediatek,mt7623-ethsys",
1006 "mediatek,mt2701-ethsys",
1007 "syscon";
1008 reg = <0 0x1b000000 0 0x1000>;
1009 #clock-cells = <1>;
1010 #reset-cells = <1>;
1011 };
1012
1013 hsdma: dma-controller@1b007000 {
1014 compatible = "mediatek,mt7623-hsdma";
1015 reg = <0 0x1b007000 0 0x1000>;
1016 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
1017 clocks = <ðsys CLK_ETHSYS_HSDMA>;
1018 clock-names = "hsdma";
1019 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1020 #dma-cells = <1>;
1021 };
1022
1023 eth: ethernet@1b100000 {
1024 compatible = "mediatek,mt7623-eth",
1025 "mediatek,mt2701-eth",
1026 "syscon";
1027 reg = <0 0x1b100000 0 0x20000>;
1028 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
1029 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
1030 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1031 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1032 <ðsys CLK_ETHSYS_ESW>,
1033 <ðsys CLK_ETHSYS_GP1>,
1034 <ðsys CLK_ETHSYS_GP2>,
1035 <&apmixedsys CLK_APMIXED_TRGPLL>;
1036 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
1037 resets = <ðsys MT2701_ETHSYS_FE_RST>,
1038 <ðsys MT2701_ETHSYS_GMAC_RST>,
1039 <ðsys MT2701_ETHSYS_PPE_RST>;
1040 reset-names = "fe", "gmac", "ppe";
1041 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1042 mediatek,ethsys = <ðsys>;
1043 mediatek,pctl = <&syscfg_pctl_a>;
1044 #address-cells = <1>;
1045 #size-cells = <0>;
1046 status = "disabled";
1047 };
1048
1049 crypto: crypto@1b240000 {
1050 compatible = "mediatek,eip97-crypto";
1051 reg = <0 0x1b240000 0 0x20000>;
1052 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
1053 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
1054 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
1055 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
1056 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
1057 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
1058 clock-names = "cryp";
1059 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1060 status = "disabled";
1061 };
1062
1063 bdpsys: syscon@1c000000 {
1064 compatible = "mediatek,mt7623-bdpsys",
1065 "mediatek,mt2701-bdpsys",
1066 "syscon";
1067 reg = <0 0x1c000000 0 0x1000>;
1068 #clock-cells = <1>;
1069 };
1070};
1071
1072&pio {
1073 cir_pins_a:cir-default {
1074 pins-cir {
1075 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1076 bias-disable;
1077 };
1078 };
1079
1080 i2c0_pins_a: i2c0-default {
1081 pins-i2c0 {
1082 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1083 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1084 bias-disable;
1085 };
1086 };
1087
1088 i2c1_pins_a: i2c1-default {
1089 pin-i2c1 {
1090 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1091 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1092 bias-disable;
1093 };
1094 };
1095
1096 i2c1_pins_b: i2c1-alt {
1097 pin-i2c1 {
1098 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1099 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1100 bias-disable;
1101 };
1102 };
1103
1104 i2c2_pins_a: i2c2-default {
1105 pin-i2c2 {
1106 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1107 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1108 bias-disable;
1109 };
1110 };
1111
1112 i2c2_pins_b: i2c2-alt {
1113 pin-i2c2 {
1114 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1115 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1116 bias-disable;
1117 };
1118 };
1119
1120 i2s0_pins_a: i2s0-default {
1121 pin-i2s0 {
1122 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1123 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1124 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1125 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1126 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1127 drive-strength = <MTK_DRIVE_12mA>;
1128 bias-pull-down;
1129 };
1130 };
1131
1132 i2s1_pins_a: i2s1-default {
1133 pin-i2s1 {
1134 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1135 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1136 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1137 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1138 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1139 drive-strength = <MTK_DRIVE_12mA>;
1140 bias-pull-down;
1141 };
1142 };
1143
1144 key_pins_a: keys-alt {
1145 pins-keys {
1146 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1147 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1148 input-enable;
1149 };
1150 };
1151
1152 led_pins_a: leds-alt {
1153 pins-leds {
1154 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1155 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1156 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1157 };
1158 };
1159
1160 mmc0_pins_default: mmc0default {
1161 pins-cmd-dat {
1162 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1163 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1164 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1165 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1166 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1167 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1168 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1169 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1170 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1171 input-enable;
1172 bias-pull-up;
1173 };
1174
1175 pins-clk {
1176 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1177 bias-pull-down;
1178 };
1179
1180 pins-rst {
1181 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1182 bias-pull-up;
1183 };
1184 };
1185
1186 mmc0_pins_uhs: mmc0 {
1187 pins-cmd-dat {
1188 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1189 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1190 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1191 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1192 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1193 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1194 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1195 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1196 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1197 input-enable;
1198 drive-strength = <MTK_DRIVE_2mA>;
1199 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1200 };
1201
1202 pins-clk {
1203 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1204 drive-strength = <MTK_DRIVE_2mA>;
1205 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1206 };
1207
1208 pins-rst {
1209 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1210 bias-pull-up;
1211 };
1212 };
1213
1214 mmc1_pins_default: mmc1default {
1215 pins-cmd-dat {
1216 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1217 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1218 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1219 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1220 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1221 input-enable;
1222 drive-strength = <MTK_DRIVE_4mA>;
1223 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1224 };
1225
1226 pins-clk {
1227 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1228 bias-pull-down;
1229 drive-strength = <MTK_DRIVE_4mA>;
1230 };
1231
1232 pins-wp {
1233 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1234 input-enable;
1235 bias-pull-up;
1236 };
1237
1238 pins-insert {
1239 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1240 bias-pull-up;
1241 };
1242 };
1243
1244 mmc1_pins_uhs: mmc1 {
1245 pins-cmd-dat {
1246 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1247 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1248 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1249 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1250 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1251 input-enable;
1252 drive-strength = <MTK_DRIVE_4mA>;
1253 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1254 };
1255
1256 pins-clk {
1257 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1258 drive-strength = <MTK_DRIVE_4mA>;
1259 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1260 };
1261 };
1262
1263 nand_pins_default: nanddefault {
1264 pins-ale {
1265 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1266 drive-strength = <MTK_DRIVE_8mA>;
1267 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1268 };
1269
1270 pins-dat {
1271 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1272 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1273 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1274 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1275 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1276 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1277 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1278 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1279 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1280 input-enable;
1281 drive-strength = <MTK_DRIVE_8mA>;
1282 bias-pull-up;
1283 };
1284
1285 pins-we {
1286 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1287 drive-strength = <MTK_DRIVE_8mA>;
1288 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1289 };
1290 };
1291
1292 pcie_default: pcie_pin_default {
1293 pins_cmd_dat {
1294 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1295 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1296 bias-disable;
1297 };
1298 };
1299
1300 pwm_pins_a: pwm-default {
1301 pins-pwm {
1302 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1303 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1304 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1305 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1306 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1307 };
1308 };
1309
1310 spi0_pins_a: spi0-default {
1311 pins-spi {
1312 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1313 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1314 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1315 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1316 bias-disable;
1317 };
1318 };
1319
1320 spi1_pins_a: spi1-default {
1321 pins-spi {
1322 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1323 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1324 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1325 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1326 };
1327 };
1328
1329 spi2_pins_a: spi2-default {
1330 pins-spi {
1331 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1332 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1333 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1334 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1335 };
1336 };
1337
1338 uart0_pins_a: uart0-default {
1339 pins-dat {
1340 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1341 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1342 };
1343 };
1344
1345 uart1_pins_a: uart1-default {
1346 pins-dat {
1347 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1348 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1349 };
1350 };
1351
1352 uart2_pins_a: uart2-default {
1353 pins-dat {
1354 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1355 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1356 };
1357 };
1358
1359 uart2_pins_b: uart2-alt {
1360 pins-dat {
1361 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1362 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1363 };
1364 };
1365};
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: John Crispin <john@phrozen.org>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include <dt-bindings/clock/mt2701-clk.h>
19#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
20#include <dt-bindings/power/mt2701-power.h>
21#include <dt-bindings/gpio/gpio.h>
22#include <dt-bindings/phy/phy.h>
23#include <dt-bindings/reset/mt2701-resets.h>
24#include <dt-bindings/thermal/thermal.h>
25#include "skeleton64.dtsi"
26
27/ {
28 compatible = "mediatek,mt7623";
29 interrupt-parent = <&sysirq>;
30
31 cpu_opp_table: opp-table {
32 compatible = "operating-points-v2";
33 opp-shared;
34
35 opp-98000000 {
36 opp-hz = /bits/ 64 <98000000>;
37 opp-microvolt = <1050000>;
38 };
39
40 opp-198000000 {
41 opp-hz = /bits/ 64 <198000000>;
42 opp-microvolt = <1050000>;
43 };
44
45 opp-398000000 {
46 opp-hz = /bits/ 64 <398000000>;
47 opp-microvolt = <1050000>;
48 };
49
50 opp-598000000 {
51 opp-hz = /bits/ 64 <598000000>;
52 opp-microvolt = <1050000>;
53 };
54
55 opp-747500000 {
56 opp-hz = /bits/ 64 <747500000>;
57 opp-microvolt = <1050000>;
58 };
59
60 opp-1040000000 {
61 opp-hz = /bits/ 64 <1040000000>;
62 opp-microvolt = <1150000>;
63 };
64
65 opp-1196000000 {
66 opp-hz = /bits/ 64 <1196000000>;
67 opp-microvolt = <1200000>;
68 };
69
70 opp-1300000000 {
71 opp-hz = /bits/ 64 <1300000000>;
72 opp-microvolt = <1300000>;
73 };
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 enable-method = "mediatek,mt6589-smp";
80
81 cpu0: cpu@0 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a7";
84 reg = <0x0>;
85 clocks = <&infracfg CLK_INFRA_CPUSEL>,
86 <&apmixedsys CLK_APMIXED_MAINPLL>;
87 clock-names = "cpu", "intermediate";
88 operating-points-v2 = <&cpu_opp_table>;
89 #cooling-cells = <2>;
90 clock-frequency = <1300000000>;
91 };
92
93 cpu1: cpu@1 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a7";
96 reg = <0x1>;
97 clocks = <&infracfg CLK_INFRA_CPUSEL>,
98 <&apmixedsys CLK_APMIXED_MAINPLL>;
99 clock-names = "cpu", "intermediate";
100 operating-points-v2 = <&cpu_opp_table>;
101 clock-frequency = <1300000000>;
102 };
103
104 cpu2: cpu@2 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a7";
107 reg = <0x2>;
108 clocks = <&infracfg CLK_INFRA_CPUSEL>,
109 <&apmixedsys CLK_APMIXED_MAINPLL>;
110 clock-names = "cpu", "intermediate";
111 operating-points-v2 = <&cpu_opp_table>;
112 clock-frequency = <1300000000>;
113 };
114
115 cpu3: cpu@3 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a7";
118 reg = <0x3>;
119 clocks = <&infracfg CLK_INFRA_CPUSEL>,
120 <&apmixedsys CLK_APMIXED_MAINPLL>;
121 clock-names = "cpu", "intermediate";
122 operating-points-v2 = <&cpu_opp_table>;
123 clock-frequency = <1300000000>;
124 };
125 };
126
127 system_clk: dummy13m {
128 compatible = "fixed-clock";
129 clock-frequency = <13000000>;
130 #clock-cells = <0>;
131 };
132
133 rtc32k: oscillator@1 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <32000>;
137 clock-output-names = "rtc32k";
138 };
139
140 clk26m: oscillator@0 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <26000000>;
144 clock-output-names = "clk26m";
145 };
146
147 thermal-zones {
148 cpu_thermal: cpu-thermal {
149 polling-delay-passive = <1000>;
150 polling-delay = <1000>;
151
152 thermal-sensors = <&thermal 0>;
153
154 trips {
155 cpu_passive: cpu-passive {
156 temperature = <47000>;
157 hysteresis = <2000>;
158 type = "passive";
159 };
160
161 cpu_active: cpu-active {
162 temperature = <67000>;
163 hysteresis = <2000>;
164 type = "active";
165 };
166
167 cpu_hot: cpu-hot {
168 temperature = <87000>;
169 hysteresis = <2000>;
170 type = "hot";
171 };
172
173 cpu-crit {
174 temperature = <107000>;
175 hysteresis = <2000>;
176 type = "critical";
177 };
178 };
179
180 cooling-maps {
181 map0 {
182 trip = <&cpu_passive>;
183 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
184 };
185
186 map1 {
187 trip = <&cpu_active>;
188 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
189 };
190
191 map2 {
192 trip = <&cpu_hot>;
193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 };
195 };
196 };
197 };
198
199 timer {
200 compatible = "arm,armv7-timer";
201 interrupt-parent = <&gic>;
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 clock-frequency = <13000000>;
207 arm,cpu-registers-not-fw-configured;
208 };
209
210 topckgen: syscon@10000000 {
211 compatible = "mediatek,mt7623-topckgen",
212 "mediatek,mt2701-topckgen",
213 "syscon";
214 reg = <0 0x10000000 0 0x1000>;
215 #clock-cells = <1>;
216 };
217
218 infracfg: syscon@10001000 {
219 compatible = "mediatek,mt7623-infracfg",
220 "mediatek,mt2701-infracfg",
221 "syscon";
222 reg = <0 0x10001000 0 0x1000>;
223 #clock-cells = <1>;
224 #reset-cells = <1>;
225 };
226
227 pericfg: syscon@10003000 {
228 compatible = "mediatek,mt7623-pericfg",
229 "mediatek,mt2701-pericfg",
230 "syscon";
231 reg = <0 0x10003000 0 0x1000>;
232 #clock-cells = <1>;
233 #reset-cells = <1>;
234 };
235
236 pio: pinctrl@10005000 {
237 compatible = "mediatek,mt7623-pinctrl";
238 reg = <0 0x1000b000 0 0x1000>;
239 mediatek,pctl-regmap = <&syscfg_pctl_a>;
240 pins-are-numbered;
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
244 interrupt-parent = <&gic>;
245 #interrupt-cells = <2>;
246 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
248 };
249
250 syscfg_pctl_a: syscfg@10005000 {
251 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
252 reg = <0 0x10005000 0 0x1000>;
253 };
254
255 scpsys: scpsys@10006000 {
256 compatible = "mediatek,mt7623-scpsys",
257 "mediatek,mt2701-scpsys",
258 "syscon";
259 #power-domain-cells = <1>;
260 reg = <0 0x10006000 0 0x1000>;
261 infracfg = <&infracfg>;
262 clocks = <&topckgen CLK_TOP_MM_SEL>,
263 <&topckgen CLK_TOP_MFG_SEL>,
264 <&topckgen CLK_TOP_ETHIF_SEL>;
265 clock-names = "mm", "mfg", "ethif";
266 };
267
268 watchdog: watchdog@10007000 {
269 compatible = "mediatek,mt7623-wdt",
270 "mediatek,mt6589-wdt";
271 reg = <0 0x10007000 0 0x100>;
272 };
273
274 timer: timer@10008000 {
275 compatible = "mediatek,mt7623-timer",
276 "mediatek,mt6577-timer";
277 reg = <0 0x10008000 0 0x80>;
278 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
279 clocks = <&system_clk>, <&rtc32k>;
280 clock-names = "system-clk", "rtc-clk";
281 };
282
283 pwrap: pwrap@1000d000 {
284 compatible = "mediatek,mt7623-pwrap",
285 "mediatek,mt2701-pwrap";
286 reg = <0 0x1000d000 0 0x1000>;
287 reg-names = "pwrap";
288 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
289 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
290 reset-names = "pwrap";
291 clocks = <&infracfg CLK_INFRA_PMICSPI>,
292 <&infracfg CLK_INFRA_PMICWRAP>;
293 clock-names = "spi", "wrap";
294 };
295
296 cir: cir@10013000 {
297 compatible = "mediatek,mt7623-cir";
298 reg = <0 0x10013000 0 0x1000>;
299 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
300 clocks = <&infracfg CLK_INFRA_IRRX>;
301 clock-names = "clk";
302 status = "disabled";
303 };
304
305 sysirq: interrupt-controller@10200100 {
306 compatible = "mediatek,mt7623-sysirq",
307 "mediatek,mt6577-sysirq";
308 interrupt-controller;
309 #interrupt-cells = <3>;
310 interrupt-parent = <&gic>;
311 reg = <0 0x10200100 0 0x1c>;
312 };
313
314 efuse: efuse@10206000 {
315 compatible = "mediatek,mt7623-efuse",
316 "mediatek,mt8173-efuse";
317 reg = <0 0x10206000 0 0x1000>;
318 #address-cells = <1>;
319 #size-cells = <1>;
320 thermal_calibration_data: calib@424 {
321 reg = <0x424 0xc>;
322 };
323 };
324
325 apmixedsys: syscon@10209000 {
326 compatible = "mediatek,mt7623-apmixedsys",
327 "mediatek,mt2701-apmixedsys",
328 "syscon";
329 reg = <0 0x10209000 0 0x1000>;
330 #clock-cells = <1>;
331 };
332
333 rng: rng@1020f000 {
334 compatible = "mediatek,mt7623-rng";
335 reg = <0 0x1020f000 0 0x1000>;
336 clocks = <&infracfg CLK_INFRA_TRNG>;
337 clock-names = "rng";
338 };
339
340 gic: interrupt-controller@10211000 {
341 compatible = "arm,cortex-a7-gic";
342 interrupt-controller;
343 #interrupt-cells = <3>;
344 interrupt-parent = <&gic>;
345 reg = <0 0x10211000 0 0x1000>,
346 <0 0x10212000 0 0x2000>,
347 <0 0x10214000 0 0x2000>,
348 <0 0x10216000 0 0x2000>;
349 };
350
351 auxadc: adc@11001000 {
352 compatible = "mediatek,mt7623-auxadc",
353 "mediatek,mt2701-auxadc";
354 reg = <0 0x11001000 0 0x1000>;
355 clocks = <&pericfg CLK_PERI_AUXADC>;
356 clock-names = "main";
357 #io-channel-cells = <1>;
358 };
359
360 uart0: serial@11002000 {
361 compatible = "mediatek,mt7623-uart",
362 "mediatek,mt6577-uart";
363 reg = <0 0x11002000 0 0x400>;
364 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
365 clocks = <&pericfg CLK_PERI_UART0_SEL>,
366 <&pericfg CLK_PERI_UART0>;
367 clock-names = "baud", "bus";
368 status = "disabled";
369 };
370
371 uart1: serial@11003000 {
372 compatible = "mediatek,mt7623-uart",
373 "mediatek,mt6577-uart";
374 reg = <0 0x11003000 0 0x400>;
375 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
376 clocks = <&pericfg CLK_PERI_UART1_SEL>,
377 <&pericfg CLK_PERI_UART1>;
378 clock-names = "baud", "bus";
379 status = "disabled";
380 };
381
382 uart2: serial@11004000 {
383 compatible = "mediatek,mt7623-uart",
384 "mediatek,mt6577-uart";
385 reg = <0 0x11004000 0 0x400>;
386 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
387 clocks = <&pericfg CLK_PERI_UART2_SEL>,
388 <&pericfg CLK_PERI_UART2>;
389 clock-names = "baud", "bus";
390 status = "disabled";
391 };
392
393 uart3: serial@11005000 {
394 compatible = "mediatek,mt7623-uart",
395 "mediatek,mt6577-uart";
396 reg = <0 0x11005000 0 0x400>;
397 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
398 clocks = <&pericfg CLK_PERI_UART3_SEL>,
399 <&pericfg CLK_PERI_UART3>;
400 clock-names = "baud", "bus";
401 status = "disabled";
402 };
403
404 pwm: pwm@11006000 {
405 compatible = "mediatek,mt7623-pwm";
406 reg = <0 0x11006000 0 0x1000>;
407 #pwm-cells = <2>;
408 clocks = <&topckgen CLK_TOP_PWM_SEL>,
409 <&pericfg CLK_PERI_PWM>,
410 <&pericfg CLK_PERI_PWM1>,
411 <&pericfg CLK_PERI_PWM2>,
412 <&pericfg CLK_PERI_PWM3>,
413 <&pericfg CLK_PERI_PWM4>,
414 <&pericfg CLK_PERI_PWM5>;
415 clock-names = "top", "main", "pwm1", "pwm2",
416 "pwm3", "pwm4", "pwm5";
417 status = "disabled";
418 };
419
420 i2c0: i2c@11007000 {
421 compatible = "mediatek,mt7623-i2c",
422 "mediatek,mt6577-i2c";
423 reg = <0 0x11007000 0 0x70>,
424 <0 0x11000200 0 0x80>;
425 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
426 clock-div = <16>;
427 clocks = <&pericfg CLK_PERI_I2C0>,
428 <&pericfg CLK_PERI_AP_DMA>;
429 clock-names = "main", "dma";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 status = "disabled";
433 };
434
435 i2c1: i2c@11008000 {
436 compatible = "mediatek,mt7623-i2c",
437 "mediatek,mt6577-i2c";
438 reg = <0 0x11008000 0 0x70>,
439 <0 0x11000280 0 0x80>;
440 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
441 clock-div = <16>;
442 clocks = <&pericfg CLK_PERI_I2C1>,
443 <&pericfg CLK_PERI_AP_DMA>;
444 clock-names = "main", "dma";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 status = "disabled";
448 };
449
450 i2c2: i2c@11009000 {
451 compatible = "mediatek,mt7623-i2c",
452 "mediatek,mt6577-i2c";
453 reg = <0 0x11009000 0 0x70>,
454 <0 0x11000300 0 0x80>;
455 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
456 clock-div = <16>;
457 clocks = <&pericfg CLK_PERI_I2C2>,
458 <&pericfg CLK_PERI_AP_DMA>;
459 clock-names = "main", "dma";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 status = "disabled";
463 };
464
465 spi0: spi@1100a000 {
466 compatible = "mediatek,mt7623-spi",
467 "mediatek,mt2701-spi";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 reg = <0 0x1100a000 0 0x100>;
471 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
472 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
473 <&topckgen CLK_TOP_SPI0_SEL>,
474 <&pericfg CLK_PERI_SPI0>;
475 clock-names = "parent-clk", "sel-clk", "spi-clk";
476 status = "disabled";
477 };
478
479 thermal: thermal@1100b000 {
480 #thermal-sensor-cells = <1>;
481 compatible = "mediatek,mt7623-thermal",
482 "mediatek,mt2701-thermal";
483 reg = <0 0x1100b000 0 0x1000>;
484 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
485 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
486 clock-names = "therm", "auxadc";
487 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
488 reset-names = "therm";
489 mediatek,auxadc = <&auxadc>;
490 mediatek,apmixedsys = <&apmixedsys>;
491 nvmem-cells = <&thermal_calibration_data>;
492 nvmem-cell-names = "calibration-data";
493 };
494
495 nandc: nfi@1100d000 {
496 compatible = "mediatek,mt7623-nfc",
497 "mediatek,mt2701-nfc";
498 reg = <0 0x1100d000 0 0x1000>;
499 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
500 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
501 clocks = <&pericfg CLK_PERI_NFI>,
502 <&pericfg CLK_PERI_NFI_PAD>;
503 clock-names = "nfi_clk", "pad_clk";
504 status = "disabled";
505 ecc-engine = <&bch>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 };
509
510 bch: ecc@1100e000 {
511 compatible = "mediatek,mt7623-ecc",
512 "mediatek,mt2701-ecc";
513 reg = <0 0x1100e000 0 0x1000>;
514 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
515 clocks = <&pericfg CLK_PERI_NFI_ECC>;
516 clock-names = "nfiecc_clk";
517 status = "disabled";
518 };
519
520 spi1: spi@11016000 {
521 compatible = "mediatek,mt7623-spi",
522 "mediatek,mt2701-spi";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 reg = <0 0x11016000 0 0x100>;
526 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
527 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
528 <&topckgen CLK_TOP_SPI1_SEL>,
529 <&pericfg CLK_PERI_SPI1>;
530 clock-names = "parent-clk", "sel-clk", "spi-clk";
531 status = "disabled";
532 };
533
534 spi2: spi@11017000 {
535 compatible = "mediatek,mt7623-spi",
536 "mediatek,mt2701-spi";
537 #address-cells = <1>;
538 #size-cells = <0>;
539 reg = <0 0x11017000 0 0x1000>;
540 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
541 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
542 <&topckgen CLK_TOP_SPI2_SEL>,
543 <&pericfg CLK_PERI_SPI2>;
544 clock-names = "parent-clk", "sel-clk", "spi-clk";
545 status = "disabled";
546 };
547
548 afe: audio-controller@11220000 {
549 compatible = "mediatek,mt7623-audio",
550 "mediatek,mt2701-audio";
551 reg = <0 0x11220000 0 0x2000>,
552 <0 0x112a0000 0 0x20000>;
553 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
554 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
555 interrupt-names = "afe", "asys";
556 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
557
558 clocks = <&infracfg CLK_INFRA_AUDIO>,
559 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
560 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
561 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
562 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
563 <&topckgen CLK_TOP_AUD_48K_TIMING>,
564 <&topckgen CLK_TOP_AUD_44K_TIMING>,
565 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
566 <&topckgen CLK_TOP_APLL_SEL>,
567 <&topckgen CLK_TOP_AUD1PLL_98M>,
568 <&topckgen CLK_TOP_AUD2PLL_90M>,
569 <&topckgen CLK_TOP_HADDS2PLL_98M>,
570 <&topckgen CLK_TOP_HADDS2PLL_294M>,
571 <&topckgen CLK_TOP_AUDPLL>,
572 <&topckgen CLK_TOP_AUDPLL_D4>,
573 <&topckgen CLK_TOP_AUDPLL_D8>,
574 <&topckgen CLK_TOP_AUDPLL_D16>,
575 <&topckgen CLK_TOP_AUDPLL_D24>,
576 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
577 <&clk26m>,
578 <&topckgen CLK_TOP_SYSPLL1_D4>,
579 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
580 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
581 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
582 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
583 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
584 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
585 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
586 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
587 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
588 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
589 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
590 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
591 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
592 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
593 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
594 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
595 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
596 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
597 <&topckgen CLK_TOP_ASM_M_SEL>,
598 <&topckgen CLK_TOP_ASM_H_SEL>,
599 <&topckgen CLK_TOP_UNIVPLL2_D4>,
600 <&topckgen CLK_TOP_UNIVPLL2_D2>,
601 <&topckgen CLK_TOP_SYSPLL_D5>;
602
603 clock-names = "infra_sys_audio_clk",
604 "top_audio_mux1_sel",
605 "top_audio_mux2_sel",
606 "top_audio_mux1_div",
607 "top_audio_mux2_div",
608 "top_audio_48k_timing",
609 "top_audio_44k_timing",
610 "top_audpll_mux_sel",
611 "top_apll_sel",
612 "top_aud1_pll_98M",
613 "top_aud2_pll_90M",
614 "top_hadds2_pll_98M",
615 "top_hadds2_pll_294M",
616 "top_audpll",
617 "top_audpll_d4",
618 "top_audpll_d8",
619 "top_audpll_d16",
620 "top_audpll_d24",
621 "top_audintbus_sel",
622 "clk_26m",
623 "top_syspll1_d4",
624 "top_aud_k1_src_sel",
625 "top_aud_k2_src_sel",
626 "top_aud_k3_src_sel",
627 "top_aud_k4_src_sel",
628 "top_aud_k5_src_sel",
629 "top_aud_k6_src_sel",
630 "top_aud_k1_src_div",
631 "top_aud_k2_src_div",
632 "top_aud_k3_src_div",
633 "top_aud_k4_src_div",
634 "top_aud_k5_src_div",
635 "top_aud_k6_src_div",
636 "top_aud_i2s1_mclk",
637 "top_aud_i2s2_mclk",
638 "top_aud_i2s3_mclk",
639 "top_aud_i2s4_mclk",
640 "top_aud_i2s5_mclk",
641 "top_aud_i2s6_mclk",
642 "top_asm_m_sel",
643 "top_asm_h_sel",
644 "top_univpll2_d4",
645 "top_univpll2_d2",
646 "top_syspll_d5";
647 };
648
649 mmc0: mmc@11230000 {
650 compatible = "mediatek,mt7623-mmc",
651 "mediatek,mt2701-mmc";
652 reg = <0 0x11230000 0 0x1000>;
653 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
654 clocks = <&pericfg CLK_PERI_MSDC30_0>,
655 <&topckgen CLK_TOP_MSDC30_0_SEL>;
656 clock-names = "source", "hclk";
657 status = "disabled";
658 };
659
660 mmc1: mmc@11240000 {
661 compatible = "mediatek,mt7623-mmc",
662 "mediatek,mt2701-mmc";
663 reg = <0 0x11240000 0 0x1000>;
664 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
665 clocks = <&pericfg CLK_PERI_MSDC30_1>,
666 <&topckgen CLK_TOP_MSDC30_1_SEL>;
667 clock-names = "source", "hclk";
668 status = "disabled";
669 };
670
671 hifsys: syscon@1a000000 {
672 compatible = "mediatek,mt7623-hifsys",
673 "mediatek,mt2701-hifsys",
674 "syscon";
675 reg = <0 0x1a000000 0 0x1000>;
676 #clock-cells = <1>;
677 #reset-cells = <1>;
678 };
679
680 pcie: pcie@1a140000 {
681 compatible = "mediatek,mt7623-pcie";
682 device_type = "pci";
683 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
684 <0 0x1a142000 0 0x1000>, /* Port0 registers */
685 <0 0x1a143000 0 0x1000>, /* Port1 registers */
686 <0 0x1a144000 0 0x1000>; /* Port2 registers */
687 reg-names = "subsys", "port0", "port1", "port2";
688 #address-cells = <3>;
689 #size-cells = <2>;
690 #interrupt-cells = <1>;
691 interrupt-map-mask = <0xf800 0 0 0>;
692 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
693 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
694 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
695 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
696 <&hifsys CLK_HIFSYS_PCIE0>,
697 <&hifsys CLK_HIFSYS_PCIE1>,
698 <&hifsys CLK_HIFSYS_PCIE2>;
699 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
700 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
701 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
702 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
703 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
704 phys = <&pcie0_port PHY_TYPE_PCIE>,
705 <&pcie1_port PHY_TYPE_PCIE>,
706 <&u3port1 PHY_TYPE_PCIE>;
707 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
708 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
709 bus-range = <0x00 0xff>;
710 status = "disabled";
711 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
712 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
713
714 pcie@0,0 {
715 reg = <0x0000 0 0 0 0>;
716 #address-cells = <3>;
717 #size-cells = <2>;
718 #interrupt-cells = <1>;
719 interrupt-map-mask = <0 0 0 0>;
720 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
721 ranges;
722 num-lanes = <1>;
723 status = "disabled";
724 };
725
726 pcie@1,0 {
727 reg = <0x0800 0 0 0 0>;
728 #address-cells = <3>;
729 #size-cells = <2>;
730 #interrupt-cells = <1>;
731 interrupt-map-mask = <0 0 0 0>;
732 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
733 ranges;
734 num-lanes = <1>;
735 status = "disabled";
736 };
737
738 pcie@2,0 {
739 reg = <0x1000 0 0 0 0>;
740 #address-cells = <3>;
741 #size-cells = <2>;
742 #interrupt-cells = <1>;
743 interrupt-map-mask = <0 0 0 0>;
744 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
745 ranges;
746 num-lanes = <1>;
747 status = "disabled";
748 };
749 };
750
751 pcie0_phy: pcie-phy@1a149000 {
752 compatible = "mediatek,generic-tphy-v1";
753 reg = <0 0x1a149000 0 0x0700>;
754 #address-cells = <2>;
755 #size-cells = <2>;
756 ranges;
757 status = "disabled";
758
759 pcie0_port: pcie-phy@1a149900 {
760 reg = <0 0x1a149900 0 0x0700>;
761 clocks = <&clk26m>;
762 clock-names = "ref";
763 #phy-cells = <1>;
764 status = "okay";
765 };
766 };
767
768 pcie1_phy: pcie-phy@1a14a000 {
769 compatible = "mediatek,generic-tphy-v1";
770 reg = <0 0x1a14a000 0 0x0700>;
771 #address-cells = <2>;
772 #size-cells = <2>;
773 ranges;
774 status = "disabled";
775
776 pcie1_port: pcie-phy@1a14a900 {
777 reg = <0 0x1a14a900 0 0x0700>;
778 clocks = <&clk26m>;
779 clock-names = "ref";
780 #phy-cells = <1>;
781 status = "okay";
782 };
783 };
784
785 usb1: usb@1a1c0000 {
786 compatible = "mediatek,mt7623-xhci",
787 "mediatek,mt8173-xhci";
788 reg = <0 0x1a1c0000 0 0x1000>,
789 <0 0x1a1c4700 0 0x0100>;
790 reg-names = "mac", "ippc";
791 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
792 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
793 <&topckgen CLK_TOP_ETHIF_SEL>;
794 clock-names = "sys_ck", "ref_ck";
795 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
796 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
797 status = "disabled";
798 };
799
800 u3phy1: usb-phy@1a1c4000 {
801 compatible = "mediatek,mt7623-u3phy",
802 "mediatek,mt2701-u3phy";
803 reg = <0 0x1a1c4000 0 0x0700>;
804 #address-cells = <2>;
805 #size-cells = <2>;
806 ranges;
807 status = "disabled";
808
809 u2port0: usb-phy@1a1c4800 {
810 reg = <0 0x1a1c4800 0 0x0100>;
811 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
812 clock-names = "ref";
813 #phy-cells = <1>;
814 status = "okay";
815 };
816
817 u3port0: usb-phy@1a1c4900 {
818 reg = <0 0x1a1c4900 0 0x0700>;
819 clocks = <&clk26m>;
820 clock-names = "ref";
821 #phy-cells = <1>;
822 status = "okay";
823 };
824 };
825
826 usb2: usb@1a240000 {
827 compatible = "mediatek,mt7623-xhci",
828 "mediatek,mt8173-xhci";
829 reg = <0 0x1a240000 0 0x1000>,
830 <0 0x1a244700 0 0x0100>;
831 reg-names = "mac", "ippc";
832 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
833 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
834 <&topckgen CLK_TOP_ETHIF_SEL>;
835 clock-names = "sys_ck", "ref_ck";
836 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
837 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
838 status = "disabled";
839 };
840
841 u3phy2: usb-phy@1a244000 {
842 compatible = "mediatek,mt7623-u3phy",
843 "mediatek,mt2701-u3phy";
844 reg = <0 0x1a244000 0 0x0700>;
845 #address-cells = <2>;
846 #size-cells = <2>;
847 ranges;
848 status = "disabled";
849
850 u2port1: usb-phy@1a244800 {
851 reg = <0 0x1a244800 0 0x0100>;
852 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
853 clock-names = "ref";
854 #phy-cells = <1>;
855 status = "okay";
856 };
857
858 u3port1: usb-phy@1a244900 {
859 reg = <0 0x1a244900 0 0x0700>;
860 clocks = <&clk26m>;
861 clock-names = "ref";
862 #phy-cells = <1>;
863 status = "okay";
864 };
865 };
866
867 ethsys: syscon@1b000000 {
868 compatible = "mediatek,mt7623-ethsys",
869 "mediatek,mt2701-ethsys",
870 "syscon";
871 reg = <0 0x1b000000 0 0x1000>;
872 #clock-cells = <1>;
873 #reset-cells = <1>;
874 };
875
876 eth: ethernet@1b100000 {
877 compatible = "mediatek,mt7623-eth",
878 "mediatek,mt2701-eth",
879 "syscon";
880 reg = <0 0x1b100000 0 0x20000>;
881 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
882 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
883 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
884 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
885 <ðsys CLK_ETHSYS_ESW>,
886 <ðsys CLK_ETHSYS_GP1>,
887 <ðsys CLK_ETHSYS_GP2>,
888 <&apmixedsys CLK_APMIXED_TRGPLL>;
889 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
890 resets = <ðsys MT2701_ETHSYS_FE_RST>,
891 <ðsys MT2701_ETHSYS_GMAC_RST>,
892 <ðsys MT2701_ETHSYS_PPE_RST>;
893 reset-names = "fe", "gmac", "ppe";
894 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
895 mediatek,ethsys = <ðsys>;
896 mediatek,pctl = <&syscfg_pctl_a>;
897 #address-cells = <1>;
898 #size-cells = <0>;
899 status = "disabled";
900 };
901
902 crypto: crypto@1b240000 {
903 compatible = "mediatek,eip97-crypto";
904 reg = <0 0x1b240000 0 0x20000>;
905 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
906 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
907 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
908 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
909 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
910 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
911 clock-names = "cryp";
912 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
913 status = "disabled";
914 };
915};